1/* 2 * Broadcom BCM63138 DSL SoCs Device Tree 3 */ 4 5#include <dt-bindings/interrupt-controller/arm-gic.h> 6#include <dt-bindings/interrupt-controller/irq.h> 7 8#include "skeleton.dtsi" --- 12 unchanged lines hidden (view full) --- 21 #address-cells = <1>; 22 #size-cells = <0>; 23 24 cpu@0 { 25 device_type = "cpu"; 26 compatible = "arm,cortex-a9"; 27 next-level-cache = <&L2>; 28 reg = <0>; |
29 enable-method = "brcm,bcm63138"; |
30 }; 31 32 cpu@1 { 33 device_type = "cpu"; 34 compatible = "arm,cortex-a9"; 35 next-level-cache = <&L2>; 36 reg = <1>; |
37 enable-method = "brcm,bcm63138"; 38 resets = <&pmb0 4 1>; |
39 }; 40 }; 41 42 clocks { 43 #address-cells = <1>; 44 #size-cells = <0>; 45 |
46 /* UBUS peripheral clock */ |
47 periph_clk: periph_clk { 48 #clock-cells = <0>; 49 compatible = "fixed-clock"; 50 clock-frequency = <50000000>; 51 clock-output-names = "periph"; 52 }; |
53 54 /* peripheral clock for system timer */ 55 axi_clk: axi_clk { 56 #clock-cells = <0>; 57 compatible = "fixed-factor-clock"; 58 clocks = <&armpll>; 59 clock-div = <2>; 60 clock-mult = <1>; 61 }; 62 63 /* APB bus clock */ 64 apb_clk: apb_clk { 65 #clock-cells = <0>; 66 compatible = "fixed-factor-clock"; 67 clocks = <&armpll>; 68 clock-div = <4>; 69 clock-mult = <1>; 70 }; |
71 }; 72 73 /* ARM bus */ 74 axi@80000000 { 75 compatible = "simple-bus"; 76 ranges = <0 0x80000000 0x784000>; 77 #address-cells = <1>; 78 #size-cells = <1>; --- 22 unchanged lines hidden (view full) --- 101 #address-cells = <0>; 102 interrupt-controller; 103 }; 104 105 global_timer: timer@1e200 { 106 compatible = "arm,cortex-a9-global-timer"; 107 reg = <0x1e200 0x20>; 108 interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>; |
109 clocks = <&axi_clk>; |
110 }; 111 112 local_timer: local-timer@1e600 { 113 compatible = "arm,cortex-a9-twd-timer"; 114 reg = <0x1e600 0x20>; 115 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>; |
116 clocks = <&axi_clk>; |
117 }; 118 119 twd_watchdog: watchdog@1e620 { 120 compatible = "arm,cortex-a9-twd-wdt"; 121 reg = <0x1e620 0x20>; 122 interrupts = <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>; 123 }; |
124 125 armpll: armpll { 126 #clock-cells = <0>; 127 compatible = "brcm,bcm63138-armpll"; 128 clocks = <&periph_clk>; 129 reg = <0x20000 0xf00>; 130 }; 131 132 pmb0: reset-controller@4800c0 { 133 compatible = "brcm,bcm63138-pmb"; 134 reg = <0x4800c0 0x10>; 135 #reset-cells = <2>; 136 }; 137 138 pmb1: reset-controller@4800e0 { 139 compatible = "brcm,bcm63138-pmb"; 140 reg = <0x4800e0 0x10>; 141 #reset-cells = <2>; 142 }; |
143 }; 144 145 /* Legacy UBUS base */ 146 ubus@fffe8000 { 147 compatible = "simple-bus"; 148 #address-cells = <1>; 149 #size-cells = <1>; 150 ranges = <0 0xfffe8000 0x8100>; 151 |
152 timer: timer@80 { 153 compatible = "brcm,bcm6328-timer", "syscon"; 154 reg = <0x80 0x3c>; 155 }; 156 |
157 serial0: serial@600 { 158 compatible = "brcm,bcm6345-uart"; 159 reg = <0x600 0x1b>; 160 interrupts = <GIC_SPI 32 0>; 161 clocks = <&periph_clk>; 162 clock-names = "periph"; 163 status = "disabled"; 164 }; 165 166 serial1: serial@620 { 167 compatible = "brcm,bcm6345-uart"; 168 reg = <0x620 0x1b>; 169 interrupts = <GIC_SPI 33 0>; 170 clocks = <&periph_clk>; 171 clock-names = "periph"; 172 status = "disabled"; 173 }; |
174 175 nand: nand@2000 { 176 #address-cells = <1>; 177 #size-cells = <0>; 178 compatible = "brcm,nand-bcm63138", "brcm,brcmnand-v7.0", "brcm,brcmnand"; 179 reg = <0x2000 0x600>, <0xf0 0x10>; 180 reg-names = "nand", "nand-int-base"; 181 status = "disabled"; 182 interrupts = <GIC_SPI 38 0>; 183 interrupt-names = "nand"; 184 }; 185 186 bootlut: bootlut@8000 { 187 compatible = "brcm,bcm63138-bootlut"; 188 reg = <0x8000 0x50>; 189 }; 190 191 reboot { 192 compatible = "syscon-reboot"; 193 regmap = <&timer>; 194 offset = <0x34>; 195 mask = <1>; 196 }; |
197 }; 198}; |