28a29
> enable-method = "brcm,bcm63138";
35a37,38
> enable-method = "brcm,bcm63138";
> resets = <&pmb0 4 1>;
43,48c46
< arm_timer_clk: arm_timer_clk {
< #clock-cells = <0>;
< compatible = "fixed-clock";
< clock-frequency = <500000000>;
< };
<
---
> /* UBUS peripheral clock */
54a53,70
>
> /* peripheral clock for system timer */
> axi_clk: axi_clk {
> #clock-cells = <0>;
> compatible = "fixed-factor-clock";
> clocks = <&armpll>;
> clock-div = <2>;
> clock-mult = <1>;
> };
>
> /* APB bus clock */
> apb_clk: apb_clk {
> #clock-cells = <0>;
> compatible = "fixed-factor-clock";
> clocks = <&armpll>;
> clock-div = <4>;
> clock-mult = <1>;
> };
93c109
< clocks = <&arm_timer_clk>;
---
> clocks = <&axi_clk>;
100c116
< clocks = <&arm_timer_clk>;
---
> clocks = <&axi_clk>;
107a124,142
>
> armpll: armpll {
> #clock-cells = <0>;
> compatible = "brcm,bcm63138-armpll";
> clocks = <&periph_clk>;
> reg = <0x20000 0xf00>;
> };
>
> pmb0: reset-controller@4800c0 {
> compatible = "brcm,bcm63138-pmb";
> reg = <0x4800c0 0x10>;
> #reset-cells = <2>;
> };
>
> pmb1: reset-controller@4800e0 {
> compatible = "brcm,bcm63138-pmb";
> reg = <0x4800e0 0x10>;
> #reset-cells = <2>;
> };
116a152,156
> timer: timer@80 {
> compatible = "brcm,bcm6328-timer", "syscon";
> reg = <0x80 0x3c>;
> };
>
133a174,196
>
> nand: nand@2000 {
> #address-cells = <1>;
> #size-cells = <0>;
> compatible = "brcm,nand-bcm63138", "brcm,brcmnand-v7.0", "brcm,brcmnand";
> reg = <0x2000 0x600>, <0xf0 0x10>;
> reg-names = "nand", "nand-int-base";
> status = "disabled";
> interrupts = <GIC_SPI 38 0>;
> interrupt-names = "nand";
> };
>
> bootlut: bootlut@8000 {
> compatible = "brcm,bcm63138-bootlut";
> reg = <0x8000 0x50>;
> };
>
> reboot {
> compatible = "syscon-reboot";
> regmap = <&timer>;
> offset = <0x34>;
> mask = <1>;
> };