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bcm5301x.dtsi (279385) bcm5301x.dtsi (295436)
1/*
2 * Broadcom BCM470X / BCM5301X ARM platform code.
3 * Generic DTS part for all BCM53010, BCM53011, BCM53012, BCM53014, BCM53015,
4 * BCM53016, BCM53017, BCM53018, BCM4707, BCM4708 and BCM4709 SoCs
5 *
6 * Copyright 2013-2014 Hauke Mehrtens <hauke@hauke-m.de>
7 *
8 * Licensed under the GNU/GPL. See COPYING for details.
9 */
10
1/*
2 * Broadcom BCM470X / BCM5301X ARM platform code.
3 * Generic DTS part for all BCM53010, BCM53011, BCM53012, BCM53014, BCM53015,
4 * BCM53016, BCM53017, BCM53018, BCM4707, BCM4708 and BCM4709 SoCs
5 *
6 * Copyright 2013-2014 Hauke Mehrtens <hauke@hauke-m.de>
7 *
8 * Licensed under the GNU/GPL. See COPYING for details.
9 */
10
11#include <dt-bindings/clock/bcm-nsp.h>
11#include <dt-bindings/gpio/gpio.h>
12#include <dt-bindings/input/input.h>
13#include <dt-bindings/interrupt-controller/irq.h>
14#include <dt-bindings/interrupt-controller/arm-gic.h>
15#include "skeleton.dtsi"
16
17/ {
18 interrupt-parent = <&gic>;
19
20 chipcommonA {
21 compatible = "simple-bus";
22 ranges = <0x00000000 0x18000000 0x00001000>;
23 #address-cells = <1>;
24 #size-cells = <1>;
25
26 uart0: serial@0300 {
27 compatible = "ns16550";
28 reg = <0x0300 0x100>;
29 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
12#include <dt-bindings/gpio/gpio.h>
13#include <dt-bindings/input/input.h>
14#include <dt-bindings/interrupt-controller/irq.h>
15#include <dt-bindings/interrupt-controller/arm-gic.h>
16#include "skeleton.dtsi"
17
18/ {
19 interrupt-parent = <&gic>;
20
21 chipcommonA {
22 compatible = "simple-bus";
23 ranges = <0x00000000 0x18000000 0x00001000>;
24 #address-cells = <1>;
25 #size-cells = <1>;
26
27 uart0: serial@0300 {
28 compatible = "ns16550";
29 reg = <0x0300 0x100>;
30 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
30 clock-frequency = <100000000>;
31 clocks = <&iprocslow>;
31 status = "disabled";
32 };
33
34 uart1: serial@0400 {
35 compatible = "ns16550";
36 reg = <0x0400 0x100>;
37 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
32 status = "disabled";
33 };
34
35 uart1: serial@0400 {
36 compatible = "ns16550";
37 reg = <0x0400 0x100>;
38 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
38 clock-frequency = <100000000>;
39 clocks = <&iprocslow>;
39 status = "disabled";
40 };
41 };
42
43 mpcore {
44 compatible = "simple-bus";
40 status = "disabled";
41 };
42 };
43
44 mpcore {
45 compatible = "simple-bus";
45 ranges = <0x00000000 0x19020000 0x00003000>;
46 ranges = <0x00000000 0x19000000 0x00023000>;
46 #address-cells = <1>;
47 #size-cells = <1>;
48
47 #address-cells = <1>;
48 #size-cells = <1>;
49
49 scu@0000 {
50 a9pll: arm_clk@00000 {
51 #clock-cells = <0>;
52 compatible = "brcm,nsp-armpll";
53 clocks = <&osc>;
54 reg = <0x00000 0x1000>;
55 };
56
57 scu@20000 {
50 compatible = "arm,cortex-a9-scu";
58 compatible = "arm,cortex-a9-scu";
51 reg = <0x0000 0x100>;
59 reg = <0x20000 0x100>;
52 };
53
60 };
61
54 timer@0200 {
62 timer@20200 {
55 compatible = "arm,cortex-a9-global-timer";
63 compatible = "arm,cortex-a9-global-timer";
56 reg = <0x0200 0x100>;
64 reg = <0x20200 0x100>;
57 interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
65 interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
58 clocks = <&clk_periph>;
66 clocks = <&periph_clk>;
59 };
60
67 };
68
61 local-timer@0600 {
69 local-timer@20600 {
62 compatible = "arm,cortex-a9-twd-timer";
70 compatible = "arm,cortex-a9-twd-timer";
63 reg = <0x0600 0x100>;
71 reg = <0x20600 0x100>;
64 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;
72 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;
65 clocks = <&clk_periph>;
73 clocks = <&periph_clk>;
66 };
67
74 };
75
68 gic: interrupt-controller@1000 {
76 gic: interrupt-controller@21000 {
69 compatible = "arm,cortex-a9-gic";
70 #interrupt-cells = <3>;
71 #address-cells = <0>;
72 interrupt-controller;
77 compatible = "arm,cortex-a9-gic";
78 #interrupt-cells = <3>;
79 #address-cells = <0>;
80 interrupt-controller;
73 reg = <0x1000 0x1000>,
74 <0x0100 0x100>;
81 reg = <0x21000 0x1000>,
82 <0x20100 0x100>;
75 };
76
83 };
84
77 L2: cache-controller@2000 {
85 L2: cache-controller@22000 {
78 compatible = "arm,pl310-cache";
86 compatible = "arm,pl310-cache";
79 reg = <0x2000 0x1000>;
87 reg = <0x22000 0x1000>;
80 cache-unified;
88 cache-unified;
89 arm,shared-override;
90 prefetch-data = <1>;
91 prefetch-instr = <1>;
81 cache-level = <2>;
82 };
83 };
84
92 cache-level = <2>;
93 };
94 };
95
96 pmu {
97 compatible = "arm,cortex-a9-pmu";
98 interrupts =
99 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
100 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
101 };
102
85 clocks {
86 #address-cells = <1>;
103 clocks {
104 #address-cells = <1>;
87 #size-cells = <0>;
105 #size-cells = <1>;
106 ranges;
88
107
89 /* As long as we do not have a real clock driver us this
90 * fixed clock */
91 clk_periph: periph {
108 osc: oscillator {
109 #clock-cells = <0>;
92 compatible = "fixed-clock";
110 compatible = "fixed-clock";
111 clock-frequency = <25000000>;
112 };
113
114 iprocmed: iprocmed {
93 #clock-cells = <0>;
115 #clock-cells = <0>;
94 clock-frequency = <400000000>;
116 compatible = "fixed-factor-clock";
117 clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>;
118 clock-div = <2>;
119 clock-mult = <1>;
95 };
120 };
121
122 iprocslow: iprocslow {
123 #clock-cells = <0>;
124 compatible = "fixed-factor-clock";
125 clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>;
126 clock-div = <4>;
127 clock-mult = <1>;
128 };
129
130 periph_clk: periph_clk {
131 #clock-cells = <0>;
132 compatible = "fixed-factor-clock";
133 clocks = <&a9pll>;
134 clock-div = <2>;
135 clock-mult = <1>;
136 };
96 };
97
98 axi@18000000 {
99 compatible = "brcm,bus-axi";
100 reg = <0x18000000 0x1000>;
101 ranges = <0x00000000 0x18000000 0x00100000>;
102 #address-cells = <1>;
103 #size-cells = <1>;
104
105 #interrupt-cells = <1>;
106 interrupt-map-mask = <0x000fffff 0xffff>;
107 interrupt-map =
108 /* ChipCommon */
109 <0x00000000 0 &gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
110
137 };
138
139 axi@18000000 {
140 compatible = "brcm,bus-axi";
141 reg = <0x18000000 0x1000>;
142 ranges = <0x00000000 0x18000000 0x00100000>;
143 #address-cells = <1>;
144 #size-cells = <1>;
145
146 #interrupt-cells = <1>;
147 interrupt-map-mask = <0x000fffff 0xffff>;
148 interrupt-map =
149 /* ChipCommon */
150 <0x00000000 0 &gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
151
152 /* PCIe Controller 0 */
153 <0x00012000 0 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
154 <0x00012000 1 &gic GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
155 <0x00012000 2 &gic GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
156 <0x00012000 3 &gic GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
157 <0x00012000 4 &gic GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
158 <0x00012000 5 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
159
160 /* PCIe Controller 1 */
161 <0x00013000 0 &gic GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
162 <0x00013000 1 &gic GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
163 <0x00013000 2 &gic GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
164 <0x00013000 3 &gic GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
165 <0x00013000 4 &gic GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
166 <0x00013000 5 &gic GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
167
168 /* PCIe Controller 2 */
169 <0x00014000 0 &gic GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
170 <0x00014000 1 &gic GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
171 <0x00014000 2 &gic GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
172 <0x00014000 3 &gic GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
173 <0x00014000 4 &gic GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
174 <0x00014000 5 &gic GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
175
111 /* USB 2.0 Controller */
112 <0x00021000 0 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
113
114 /* USB 3.0 Controller */
115 <0x00023000 0 &gic GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
116
117 /* Ethernet Controller 0 */
118 <0x00024000 0 &gic GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,

--- 19 unchanged lines hidden (view full) ---

138
139 chipcommon: chipcommon@0 {
140 reg = <0x00000000 0x1000>;
141
142 gpio-controller;
143 #gpio-cells = <2>;
144 };
145 };
176 /* USB 2.0 Controller */
177 <0x00021000 0 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
178
179 /* USB 3.0 Controller */
180 <0x00023000 0 &gic GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
181
182 /* Ethernet Controller 0 */
183 <0x00024000 0 &gic GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,

--- 19 unchanged lines hidden (view full) ---

203
204 chipcommon: chipcommon@0 {
205 reg = <0x00000000 0x1000>;
206
207 gpio-controller;
208 #gpio-cells = <2>;
209 };
210 };
211
212 lcpll0: lcpll0@1800c100 {
213 #clock-cells = <1>;
214 compatible = "brcm,nsp-lcpll0";
215 reg = <0x1800c100 0x14>;
216 clocks = <&osc>;
217 clock-output-names = "lcpll0", "pcie_phy", "sdio",
218 "ddr_phy";
219 };
220
221 genpll: genpll@1800c140 {
222 #clock-cells = <1>;
223 compatible = "brcm,nsp-genpll";
224 reg = <0x1800c140 0x24>;
225 clocks = <&osc>;
226 clock-output-names = "genpll", "phy", "ethernetclk",
227 "usbclk", "iprocfast", "sata1",
228 "sata2";
229 };
230
231 nand: nand@18028000 {
232 compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1", "brcm,brcmnand";
233 reg = <0x18028000 0x600>, <0x1811a408 0x600>, <0x18028f00 0x20>;
234 reg-names = "nand", "iproc-idm", "iproc-ext";
235 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
236
237 #address-cells = <1>;
238 #size-cells = <0>;
239
240 brcm,nand-has-wp;
241 };
146};
242};