10a11
> #include <dt-bindings/clock/bcm-nsp.h>
30c31
< clock-frequency = <100000000>;
---
> clocks = <&iprocslow>;
38c39
< clock-frequency = <100000000>;
---
> clocks = <&iprocslow>;
45c46
< ranges = <0x00000000 0x19020000 0x00003000>;
---
> ranges = <0x00000000 0x19000000 0x00023000>;
49c50,57
< scu@0000 {
---
> a9pll: arm_clk@00000 {
> #clock-cells = <0>;
> compatible = "brcm,nsp-armpll";
> clocks = <&osc>;
> reg = <0x00000 0x1000>;
> };
>
> scu@20000 {
51c59
< reg = <0x0000 0x100>;
---
> reg = <0x20000 0x100>;
54c62
< timer@0200 {
---
> timer@20200 {
56c64
< reg = <0x0200 0x100>;
---
> reg = <0x20200 0x100>;
58c66
< clocks = <&clk_periph>;
---
> clocks = <&periph_clk>;
61c69
< local-timer@0600 {
---
> local-timer@20600 {
63c71
< reg = <0x0600 0x100>;
---
> reg = <0x20600 0x100>;
65c73
< clocks = <&clk_periph>;
---
> clocks = <&periph_clk>;
68c76
< gic: interrupt-controller@1000 {
---
> gic: interrupt-controller@21000 {
73,74c81,82
< reg = <0x1000 0x1000>,
< <0x0100 0x100>;
---
> reg = <0x21000 0x1000>,
> <0x20100 0x100>;
77c85
< L2: cache-controller@2000 {
---
> L2: cache-controller@22000 {
79c87
< reg = <0x2000 0x1000>;
---
> reg = <0x22000 0x1000>;
80a89,91
> arm,shared-override;
> prefetch-data = <1>;
> prefetch-instr = <1>;
84a96,102
> pmu {
> compatible = "arm,cortex-a9-pmu";
> interrupts =
> <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
> <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
> };
>
87c105,106
< #size-cells = <0>;
---
> #size-cells = <1>;
> ranges;
89,91c108,109
< /* As long as we do not have a real clock driver us this
< * fixed clock */
< clk_periph: periph {
---
> osc: oscillator {
> #clock-cells = <0>;
92a111,114
> clock-frequency = <25000000>;
> };
>
> iprocmed: iprocmed {
94c116,119
< clock-frequency = <400000000>;
---
> compatible = "fixed-factor-clock";
> clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>;
> clock-div = <2>;
> clock-mult = <1>;
95a121,136
>
> iprocslow: iprocslow {
> #clock-cells = <0>;
> compatible = "fixed-factor-clock";
> clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>;
> clock-div = <4>;
> clock-mult = <1>;
> };
>
> periph_clk: periph_clk {
> #clock-cells = <0>;
> compatible = "fixed-factor-clock";
> clocks = <&a9pll>;
> clock-div = <2>;
> clock-mult = <1>;
> };
110a152,175
> /* PCIe Controller 0 */
> <0x00012000 0 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
> <0x00012000 1 &gic GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
> <0x00012000 2 &gic GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
> <0x00012000 3 &gic GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
> <0x00012000 4 &gic GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
> <0x00012000 5 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
>
> /* PCIe Controller 1 */
> <0x00013000 0 &gic GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
> <0x00013000 1 &gic GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
> <0x00013000 2 &gic GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
> <0x00013000 3 &gic GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
> <0x00013000 4 &gic GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
> <0x00013000 5 &gic GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
>
> /* PCIe Controller 2 */
> <0x00014000 0 &gic GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
> <0x00014000 1 &gic GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
> <0x00014000 2 &gic GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
> <0x00014000 3 &gic GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
> <0x00014000 4 &gic GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
> <0x00014000 5 &gic GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
>
145a211,241
>
> lcpll0: lcpll0@1800c100 {
> #clock-cells = <1>;
> compatible = "brcm,nsp-lcpll0";
> reg = <0x1800c100 0x14>;
> clocks = <&osc>;
> clock-output-names = "lcpll0", "pcie_phy", "sdio",
> "ddr_phy";
> };
>
> genpll: genpll@1800c140 {
> #clock-cells = <1>;
> compatible = "brcm,nsp-genpll";
> reg = <0x1800c140 0x24>;
> clocks = <&osc>;
> clock-output-names = "genpll", "phy", "ethernetclk",
> "usbclk", "iprocfast", "sata1",
> "sata2";
> };
>
> nand: nand@18028000 {
> compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1", "brcm,brcmnand";
> reg = <0x18028000 0x600>, <0x1811a408 0x600>, <0x18028f00 0x20>;
> reg-names = "nand", "iproc-idm", "iproc-ext";
> interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
>
> #address-cells = <1>;
> #size-cells = <0>;
>
> brcm,nand-has-wp;
> };