1/*
2 * Broadcom BCM470X / BCM5301X ARM platform code.
3 * DTS for BCM4708 SoC.
4 *
5 * Copyright 2013-2014 Hauke Mehrtens <hauke@hauke-m.de>
6 *
7 * Licensed under the GNU/GPL. See COPYING for details.
8 */
9
10#include "bcm5301x.dtsi"
11
12/ {
13 compatible = "brcm,bcm4708";
14
15 cpus {
16 #address-cells = <1>;
17 #size-cells = <0>;
18 enable-method = "brcm,bcm-nsp-smp";
19
20 cpu@0 {
21 device_type = "cpu";
22 compatible = "arm,cortex-a9";
23 next-level-cache = <&L2>;
24 reg = <0x0>;
25 };
26
27 cpu@1 {
28 device_type = "cpu";
29 compatible = "arm,cortex-a9";
30 next-level-cache = <&L2>;
31 secondary-boot-reg = <0xffff0400>;
32 reg = <0x1>;
33 };
34 };
35
36};
2 * Broadcom BCM470X / BCM5301X ARM platform code.
3 * DTS for BCM4708 SoC.
4 *
5 * Copyright 2013-2014 Hauke Mehrtens <hauke@hauke-m.de>
6 *
7 * Licensed under the GNU/GPL. See COPYING for details.
8 */
9
10#include "bcm5301x.dtsi"
11
12/ {
13 compatible = "brcm,bcm4708";
14
15 cpus {
16 #address-cells = <1>;
17 #size-cells = <0>;
18 enable-method = "brcm,bcm-nsp-smp";
19
20 cpu@0 {
21 device_type = "cpu";
22 compatible = "arm,cortex-a9";
23 next-level-cache = <&L2>;
24 reg = <0x0>;
25 };
26
27 cpu@1 {
28 device_type = "cpu";
29 compatible = "arm,cortex-a9";
30 next-level-cache = <&L2>;
31 secondary-boot-reg = <0xffff0400>;
32 reg = <0x1>;
33 };
34 };
35
36};