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armada-xp.dtsi (279385) armada-xp.dtsi (295436)
1/*
2 * Device Tree Include file for Marvell Armada XP family SoC
3 *
4 * Copyright (C) 2012 Marvell
5 *
6 * Lior Amsalem <alior@marvell.com>
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>

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52
53#include "armada-370-xp.dtsi"
54
55/ {
56 model = "Marvell Armada XP family SoC";
57 compatible = "marvell,armadaxp", "marvell,armada-370-xp";
58
59 aliases {
1/*
2 * Device Tree Include file for Marvell Armada XP family SoC
3 *
4 * Copyright (C) 2012 Marvell
5 *
6 * Lior Amsalem <alior@marvell.com>
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>

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52
53#include "armada-370-xp.dtsi"
54
55/ {
56 model = "Marvell Armada XP family SoC";
57 compatible = "marvell,armadaxp", "marvell,armada-370-xp";
58
59 aliases {
60 eth2 = &eth2;
60 serial2 = &uart2;
61 serial3 = &uart3;
61 };
62
63 soc {
64 compatible = "marvell,armadaxp-mbus", "simple-bus";
65
66 bootrom {
67 compatible = "marvell,bootrom";
68 reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>;

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73 compatible = "marvell,armada-xp-sdram-controller";
74 reg = <0x1400 0x500>;
75 };
76
77 L2: l2-cache {
78 compatible = "marvell,aurora-system-cache";
79 reg = <0x08000 0x1000>;
80 cache-id-part = <0x100>;
62 };
63
64 soc {
65 compatible = "marvell,armadaxp-mbus", "simple-bus";
66
67 bootrom {
68 compatible = "marvell,bootrom";
69 reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>;

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74 compatible = "marvell,armada-xp-sdram-controller";
75 reg = <0x1400 0x500>;
76 };
77
78 L2: l2-cache {
79 compatible = "marvell,aurora-system-cache";
80 reg = <0x08000 0x1000>;
81 cache-id-part = <0x100>;
82 cache-level = <2>;
81 cache-unified;
82 wt-override;
83 };
84
85 spi0: spi@10600 {
83 cache-unified;
84 wt-override;
85 };
86
87 spi0: spi@10600 {
88 compatible = "marvell,armada-xp-spi",
89 "marvell,orion-spi";
86 pinctrl-0 = <&spi0_pins>;
87 pinctrl-names = "default";
88 };
89
90 pinctrl-0 = <&spi0_pins>;
91 pinctrl-names = "default";
92 };
93
94 spi1: spi@10680 {
95 compatible = "marvell,armada-xp-spi",
96 "marvell,orion-spi";
97 };
98
99
90 i2c0: i2c@11000 {
91 compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
92 reg = <0x11000 0x100>;
93 };
94
95 i2c1: i2c@11100 {
96 compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
97 reg = <0x11100 0x100>;

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144 reg = <0x182b0 0x4
145 0x184d0 0x4>;
146 status = "okay";
147 };
148
149 cpuclk: clock-complex@18700 {
150 #clock-cells = <1>;
151 compatible = "marvell,armada-xp-cpu-clock";
100 i2c0: i2c@11000 {
101 compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
102 reg = <0x11000 0x100>;
103 };
104
105 i2c1: i2c@11100 {
106 compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
107 reg = <0x11100 0x100>;

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154 reg = <0x182b0 0x4
155 0x184d0 0x4>;
156 status = "okay";
157 };
158
159 cpuclk: clock-complex@18700 {
160 #clock-cells = <1>;
161 compatible = "marvell,armada-xp-cpu-clock";
152 reg = <0x18700 0xA0>, <0x1c054 0x10>;
162 reg = <0x18700 0x24>, <0x1c054 0x10>;
153 clocks = <&coreclk 1>;
154 };
155
163 clocks = <&coreclk 1>;
164 };
165
156 interrupt-controller@20000 {
166 interrupt-controller@20a00 {
157 reg = <0x20a00 0x2d0>, <0x21070 0x58>;
158 };
159
160 timer@20300 {
161 compatible = "marvell,armada-xp-timer";
162 clocks = <&coreclk 2>, <&refclk>;
163 clock-names = "nbclk", "fixed";
164 };

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169 clock-names = "nbclk", "fixed";
170 };
171
172 cpurst@20800 {
173 compatible = "marvell,armada-370-cpu-reset";
174 reg = <0x20800 0x20>;
175 };
176
167 reg = <0x20a00 0x2d0>, <0x21070 0x58>;
168 };
169
170 timer@20300 {
171 compatible = "marvell,armada-xp-timer";
172 clocks = <&coreclk 2>, <&refclk>;
173 clock-names = "nbclk", "fixed";
174 };

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179 clock-names = "nbclk", "fixed";
180 };
181
182 cpurst@20800 {
183 compatible = "marvell,armada-370-cpu-reset";
184 reg = <0x20800 0x20>;
185 };
186
187 cpu-config@21000 {
188 compatible = "marvell,armada-xp-cpu-config";
189 reg = <0x21000 0x8>;
190 };
191
177 eth2: ethernet@30000 {
192 eth2: ethernet@30000 {
178 compatible = "marvell,armada-370-neta";
193 compatible = "marvell,armada-xp-neta";
179 reg = <0x30000 0x4000>;
180 interrupts = <12>;
181 clocks = <&gateclk 2>;
182 status = "disabled";
183 };
184
185 usb@50000 {
186 clocks = <&gateclk 18>;

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213 xor11 {
214 interrupts = <52>;
215 dmacap,memcpy;
216 dmacap,xor;
217 dmacap,memset;
218 };
219 };
220
194 reg = <0x30000 0x4000>;
195 interrupts = <12>;
196 clocks = <&gateclk 2>;
197 status = "disabled";
198 };
199
200 usb@50000 {
201 clocks = <&gateclk 18>;

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228 xor11 {
229 interrupts = <52>;
230 dmacap,memcpy;
231 dmacap,xor;
232 dmacap,memset;
233 };
234 };
235
236 ethernet@70000 {
237 compatible = "marvell,armada-xp-neta";
238 };
239
240 ethernet@74000 {
241 compatible = "marvell,armada-xp-neta";
242 };
243
244 crypto@90000 {
245 compatible = "marvell,armada-xp-crypto";
246 reg = <0x90000 0x10000>;
247 reg-names = "regs";
248 interrupts = <48>, <49>;
249 clocks = <&gateclk 23>, <&gateclk 23>;
250 clock-names = "cesa0", "cesa1";
251 marvell,crypto-srams = <&crypto_sram0>,
252 <&crypto_sram1>;
253 marvell,crypto-sram-size = <0x800>;
254 };
255
221 xor@f0900 {
222 compatible = "marvell,orion-xor";
223 reg = <0xF0900 0x100
224 0xF0B00 0x100>;
225 clocks = <&gateclk 28>;
226 status = "okay";
227
228 xor00 {

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233 xor01 {
234 interrupts = <95>;
235 dmacap,memcpy;
236 dmacap,xor;
237 dmacap,memset;
238 };
239 };
240 };
256 xor@f0900 {
257 compatible = "marvell,orion-xor";
258 reg = <0xF0900 0x100
259 0xF0B00 0x100>;
260 clocks = <&gateclk 28>;
261 status = "okay";
262
263 xor00 {

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268 xor01 {
269 interrupts = <95>;
270 dmacap,memcpy;
271 dmacap,xor;
272 dmacap,memset;
273 };
274 };
275 };
276
277 crypto_sram0: sa-sram0 {
278 compatible = "mmio-sram";
279 reg = <MBUS_ID(0x09, 0x09) 0 0x800>;
280 clocks = <&gateclk 23>;
281 #address-cells = <1>;
282 #size-cells = <1>;
283 ranges = <0 MBUS_ID(0x09, 0x09) 0 0x800>;
284 };
285
286 crypto_sram1: sa-sram1 {
287 compatible = "mmio-sram";
288 reg = <MBUS_ID(0x09, 0x05) 0 0x800>;
289 clocks = <&gateclk 23>;
290 #address-cells = <1>;
291 #size-cells = <1>;
292 ranges = <0 MBUS_ID(0x09, 0x05) 0 0x800>;
293 };
241 };
242
243 clocks {
244 /* 25 MHz reference crystal */
245 refclk: oscillator {
246 compatible = "fixed-clock";
247 #clock-cells = <0>;
248 clock-frequency = <25000000>;

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282 marvell,pins = "mpp30", "mpp31", "mpp32",
283 "mpp33", "mpp34", "mpp35";
284 marvell,function = "sd0";
285 };
286
287 spi0_pins: spi0-pins {
288 marvell,pins = "mpp36", "mpp37",
289 "mpp38", "mpp39";
294 };
295
296 clocks {
297 /* 25 MHz reference crystal */
298 refclk: oscillator {
299 compatible = "fixed-clock";
300 #clock-cells = <0>;
301 clock-frequency = <25000000>;

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335 marvell,pins = "mpp30", "mpp31", "mpp32",
336 "mpp33", "mpp34", "mpp35";
337 marvell,function = "sd0";
338 };
339
340 spi0_pins: spi0-pins {
341 marvell,pins = "mpp36", "mpp37",
342 "mpp38", "mpp39";
290 marvell,function = "spi";
343 marvell,function = "spi0";
291 };
292
293 uart2_pins: uart2-pins {
294 marvell,pins = "mpp42", "mpp43";
295 marvell,function = "uart2";
296 };
297
298 uart3_pins: uart3-pins {
299 marvell,pins = "mpp44", "mpp45";
300 marvell,function = "uart3";
301 };
302};
344 };
345
346 uart2_pins: uart2-pins {
347 marvell,pins = "mpp42", "mpp43";
348 marvell,function = "uart2";
349 };
350
351 uart3_pins: uart3-pins {
352 marvell,pins = "mpp44", "mpp45";
353 marvell,function = "uart3";
354 };
355};