1/*
2 * Device Tree file for Marvell Armada 370 evaluation board
3 * (DB-88F6710-BP-DDR3)
4 *
5 * Copyright (C) 2012 Marvell
6 *
7 * Lior Amsalem <alior@marvell.com>
8 * Gregory CLEMENT <gregory.clement@free-electrons.com>
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40 * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
41 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
42 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
43 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
44 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
45 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
46 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
47 * OTHER DEALINGS IN THE SOFTWARE.
48 *
49 * Note: this Device Tree assumes that the bootloader has remapped the
50 * internal registers to 0xf1000000 (instead of the default
51 * 0xd0000000). The 0xf1000000 is the default used by the recent,
52 * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier
53 * boards were delivered with an older version of the bootloader that
54 * left internal registers mapped at 0xd0000000. If you are in this
55 * situation, you should either update your bootloader (preferred
56 * solution) or the below Device Tree should be adjusted.
57 */
58
59/dts-v1/;
60#include "armada-370.dtsi"
61
62/ {
63 model = "Marvell Armada 370 Evaluation Board";
64 compatible = "marvell,a370-db", "marvell,armada370", "marvell,armada-370-xp";
65
66 chosen {
67 stdout-path = "serial0:115200n8";
68 };
69
70 memory {
71 device_type = "memory";
72 reg = <0x00000000 0x40000000>; /* 1 GB */
73 };
74
75 soc {
76 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
77 MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000
78 MBUS_ID(0x09, 0x01) 0 0xf1100000 0x10000>;
79
80 internal-regs {
81 serial@12000 {
82 status = "okay";
83 };
84 sata@a0000 {
85 nr-ports = <2>;
86 status = "okay";
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158 spi0: spi@10600 {
159 pinctrl-0 = <&spi0_pins2>;
160 pinctrl-names = "default";
161 status = "okay";
162
163 spi-flash@0 {
164 #address-cells = <1>;
165 #size-cells = <1>;
166 compatible = "mx25l25635e", "jedec,spi-nor";
167 reg = <0>; /* Chip select 0 */
168 spi-max-frequency = <50000000>;
169 };
170 };
171 };
172
173 pcie-controller {
174 status = "okay";
--- 75 unchanged lines hidden ---
2 * Device Tree file for Marvell Armada 370 evaluation board
3 * (DB-88F6710-BP-DDR3)
4 *
5 * Copyright (C) 2012 Marvell
6 *
7 * Lior Amsalem <alior@marvell.com>
8 * Gregory CLEMENT <gregory.clement@free-electrons.com>
--- 31 unchanged lines hidden (view full) ---
40 * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
41 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
42 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
43 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
44 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
45 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
46 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
47 * OTHER DEALINGS IN THE SOFTWARE.
48 *
49 * Note: this Device Tree assumes that the bootloader has remapped the
50 * internal registers to 0xf1000000 (instead of the default
51 * 0xd0000000). The 0xf1000000 is the default used by the recent,
52 * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier
53 * boards were delivered with an older version of the bootloader that
54 * left internal registers mapped at 0xd0000000. If you are in this
55 * situation, you should either update your bootloader (preferred
56 * solution) or the below Device Tree should be adjusted.
57 */
58
59/dts-v1/;
60#include "armada-370.dtsi"
61
62/ {
63 model = "Marvell Armada 370 Evaluation Board";
64 compatible = "marvell,a370-db", "marvell,armada370", "marvell,armada-370-xp";
65
66 chosen {
67 stdout-path = "serial0:115200n8";
68 };
69
70 memory {
71 device_type = "memory";
72 reg = <0x00000000 0x40000000>; /* 1 GB */
73 };
74
75 soc {
76 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
77 MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000
78 MBUS_ID(0x09, 0x01) 0 0xf1100000 0x10000>;
79
80 internal-regs {
81 serial@12000 {
82 status = "okay";
83 };
84 sata@a0000 {
85 nr-ports = <2>;
86 status = "okay";
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158 spi0: spi@10600 {
159 pinctrl-0 = <&spi0_pins2>;
160 pinctrl-names = "default";
161 status = "okay";
162
163 spi-flash@0 {
164 #address-cells = <1>;
165 #size-cells = <1>;
166 compatible = "mx25l25635e", "jedec,spi-nor";
167 reg = <0>; /* Chip select 0 */
168 spi-max-frequency = <50000000>;
169 };
170 };
171 };
172
173 pcie-controller {
174 status = "okay";
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