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am43xx-clocks.dtsi (279385) am43xx-clocks.dtsi (295436)
1/*
2 * Device Tree Source for AM43xx clock data
3 *
4 * Copyright (C) 2013 Texas Instruments, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
1/*
2 * Device Tree Source for AM43xx clock data
3 *
4 * Copyright (C) 2013 Texas Instruments, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10&scrm_clocks {
10&scm_clocks {
11 sys_clkin_ck: sys_clkin_ck {
12 #clock-cells = <0>;
13 compatible = "ti,mux-clock";
14 clocks = <&sysboot_freq_sel_ck>, <&crystal_freq_sel_ck>;
15 ti,bit-shift = <31>;
16 reg = <0x0040>;
17 };
18

--- 83 unchanged lines hidden (view full) ---

102 clocks = <&sys_clkin_ck>;
103 clock-mult = <1>;
104 clock-div = <1>;
105 };
106
107 ehrpwm0_tbclk: ehrpwm0_tbclk {
108 #clock-cells = <0>;
109 compatible = "ti,gate-clock";
11 sys_clkin_ck: sys_clkin_ck {
12 #clock-cells = <0>;
13 compatible = "ti,mux-clock";
14 clocks = <&sysboot_freq_sel_ck>, <&crystal_freq_sel_ck>;
15 ti,bit-shift = <31>;
16 reg = <0x0040>;
17 };
18

--- 83 unchanged lines hidden (view full) ---

102 clocks = <&sys_clkin_ck>;
103 clock-mult = <1>;
104 clock-div = <1>;
105 };
106
107 ehrpwm0_tbclk: ehrpwm0_tbclk {
108 #clock-cells = <0>;
109 compatible = "ti,gate-clock";
110 clocks = <&dpll_per_m2_ck>;
110 clocks = <&l4ls_gclk>;
111 ti,bit-shift = <0>;
112 reg = <0x0664>;
113 };
114
115 ehrpwm1_tbclk: ehrpwm1_tbclk {
116 #clock-cells = <0>;
117 compatible = "ti,gate-clock";
111 ti,bit-shift = <0>;
112 reg = <0x0664>;
113 };
114
115 ehrpwm1_tbclk: ehrpwm1_tbclk {
116 #clock-cells = <0>;
117 compatible = "ti,gate-clock";
118 clocks = <&dpll_per_m2_ck>;
118 clocks = <&l4ls_gclk>;
119 ti,bit-shift = <1>;
120 reg = <0x0664>;
121 };
122
123 ehrpwm2_tbclk: ehrpwm2_tbclk {
124 #clock-cells = <0>;
125 compatible = "ti,gate-clock";
119 ti,bit-shift = <1>;
120 reg = <0x0664>;
121 };
122
123 ehrpwm2_tbclk: ehrpwm2_tbclk {
124 #clock-cells = <0>;
125 compatible = "ti,gate-clock";
126 clocks = <&dpll_per_m2_ck>;
126 clocks = <&l4ls_gclk>;
127 ti,bit-shift = <2>;
128 reg = <0x0664>;
129 };
130
131 ehrpwm3_tbclk: ehrpwm3_tbclk {
132 #clock-cells = <0>;
133 compatible = "ti,gate-clock";
127 ti,bit-shift = <2>;
128 reg = <0x0664>;
129 };
130
131 ehrpwm3_tbclk: ehrpwm3_tbclk {
132 #clock-cells = <0>;
133 compatible = "ti,gate-clock";
134 clocks = <&dpll_per_m2_ck>;
134 clocks = <&l4ls_gclk>;
135 ti,bit-shift = <4>;
136 reg = <0x0664>;
137 };
138
139 ehrpwm4_tbclk: ehrpwm4_tbclk {
140 #clock-cells = <0>;
141 compatible = "ti,gate-clock";
135 ti,bit-shift = <4>;
136 reg = <0x0664>;
137 };
138
139 ehrpwm4_tbclk: ehrpwm4_tbclk {
140 #clock-cells = <0>;
141 compatible = "ti,gate-clock";
142 clocks = <&dpll_per_m2_ck>;
142 clocks = <&l4ls_gclk>;
143 ti,bit-shift = <5>;
144 reg = <0x0664>;
145 };
146
147 ehrpwm5_tbclk: ehrpwm5_tbclk {
148 #clock-cells = <0>;
149 compatible = "ti,gate-clock";
143 ti,bit-shift = <5>;
144 reg = <0x0664>;
145 };
146
147 ehrpwm5_tbclk: ehrpwm5_tbclk {
148 #clock-cells = <0>;
149 compatible = "ti,gate-clock";
150 clocks = <&dpll_per_m2_ck>;
150 clocks = <&l4ls_gclk>;
151 ti,bit-shift = <6>;
152 reg = <0x0664>;
153 };
154};
155&prcm_clocks {
156 clk_32768_ck: clk_32768_ck {
157 #clock-cells = <0>;
158 compatible = "fixed-clock";

--- 95 unchanged lines hidden (view full) ---

254 clocks = <&dpll_mpu_ck>;
255 ti,max-div = <31>;
256 ti,autoidle-shift = <8>;
257 reg = <0x2d70>;
258 ti,index-starts-at-one;
259 ti,invert-autoidle-bit;
260 };
261
151 ti,bit-shift = <6>;
152 reg = <0x0664>;
153 };
154};
155&prcm_clocks {
156 clk_32768_ck: clk_32768_ck {
157 #clock-cells = <0>;
158 compatible = "fixed-clock";

--- 95 unchanged lines hidden (view full) ---

254 clocks = <&dpll_mpu_ck>;
255 ti,max-div = <31>;
256 ti,autoidle-shift = <8>;
257 reg = <0x2d70>;
258 ti,index-starts-at-one;
259 ti,invert-autoidle-bit;
260 };
261
262 mpu_periphclk: mpu_periphclk {
263 #clock-cells = <0>;
264 compatible = "fixed-factor-clock";
265 clocks = <&dpll_mpu_m2_ck>;
266 clock-mult = <1>;
267 clock-div = <2>;
268 };
269
262 dpll_ddr_ck: dpll_ddr_ck {
263 #clock-cells = <0>;
264 compatible = "ti,am3-dpll-clock";
265 clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
266 reg = <0x2da0>, <0x2da4>, <0x2dac>;
267 };
268
269 dpll_ddr_m2_ck: dpll_ddr_m2_ck {

--- 211 unchanged lines hidden (view full) ---

481
482 cpsw_cpts_rft_clk: cpsw_cpts_rft_clk {
483 #clock-cells = <0>;
484 compatible = "ti,mux-clock";
485 clocks = <&sysclk_div>, <&dpll_core_m5_ck>, <&dpll_disp_m2_ck>;
486 reg = <0x4238>;
487 };
488
270 dpll_ddr_ck: dpll_ddr_ck {
271 #clock-cells = <0>;
272 compatible = "ti,am3-dpll-clock";
273 clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
274 reg = <0x2da0>, <0x2da4>, <0x2dac>;
275 };
276
277 dpll_ddr_m2_ck: dpll_ddr_m2_ck {

--- 211 unchanged lines hidden (view full) ---

489
490 cpsw_cpts_rft_clk: cpsw_cpts_rft_clk {
491 #clock-cells = <0>;
492 compatible = "ti,mux-clock";
493 clocks = <&sysclk_div>, <&dpll_core_m5_ck>, <&dpll_disp_m2_ck>;
494 reg = <0x4238>;
495 };
496
497 dpll_clksel_mac_clk: dpll_clksel_mac_clk {
498 #clock-cells = <0>;
499 compatible = "ti,divider-clock";
500 clocks = <&dpll_core_m5_ck>;
501 reg = <0x4234>;
502 ti,bit-shift = <2>;
503 ti,dividers = <2>, <5>;
504 };
505
489 clk_32k_mosc_ck: clk_32k_mosc_ck {
490 #clock-cells = <0>;
491 compatible = "fixed-clock";
492 clock-frequency = <32768>;
493 };
494
495 gpio0_dbclk_mux_ck: gpio0_dbclk_mux_ck {
496 #clock-cells = <0>;

--- 261 unchanged lines hidden --- 		506 clk_32k_mosc_ck: clk_32k_mosc_ck {
507 #clock-cells = <0>;
508 compatible = "fixed-clock";
509 clock-frequency = <32768>;
510 };
511
512 gpio0_dbclk_mux_ck: gpio0_dbclk_mux_ck {
513 #clock-cells = <0>;

--- 261 unchanged lines hidden ---