10c10
< &scrm_clocks {
---
> &scm_clocks {
110c110
< clocks = <&dpll_per_m2_ck>;
---
> clocks = <&l4ls_gclk>;
118c118
< clocks = <&dpll_per_m2_ck>;
---
> clocks = <&l4ls_gclk>;
126c126
< clocks = <&dpll_per_m2_ck>;
---
> clocks = <&l4ls_gclk>;
134c134
< clocks = <&dpll_per_m2_ck>;
---
> clocks = <&l4ls_gclk>;
142c142
< clocks = <&dpll_per_m2_ck>;
---
> clocks = <&l4ls_gclk>;
150c150
< clocks = <&dpll_per_m2_ck>;
---
> clocks = <&l4ls_gclk>;
261a262,269
> mpu_periphclk: mpu_periphclk {
> #clock-cells = <0>;
> compatible = "fixed-factor-clock";
> clocks = <&dpll_mpu_m2_ck>;
> clock-mult = <1>;
> clock-div = <2>;
> };
>
488a497,505
> dpll_clksel_mac_clk: dpll_clksel_mac_clk {
> #clock-cells = <0>;
> compatible = "ti,divider-clock";
> clocks = <&dpll_core_m5_ck>;
> reg = <0x4234>;
> ti,bit-shift = <2>;
> ti,dividers = <2>, <5>;
> };
>