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am335x-nano.dts (279385) am335x-nano.dts (295436)
1/*
2 * Copyright (C) 2013 Newflow Ltd - http://www.newflow.co.uk/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8/dts-v1/;

--- 27 unchanged lines hidden (view full) ---

36};
37
38&am33xx_pinmux {
39 pinctrl-names = "default";
40 pinctrl-0 = <&misc_pins>;
41
42 misc_pins: misc_pins {
43 pinctrl-single,pins = <
1/*
2 * Copyright (C) 2013 Newflow Ltd - http://www.newflow.co.uk/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8/dts-v1/;

--- 27 unchanged lines hidden (view full) ---

36};
37
38&am33xx_pinmux {
39 pinctrl-names = "default";
40 pinctrl-0 = <&misc_pins>;
41
42 misc_pins: misc_pins {
43 pinctrl-single,pins = <
44 0x15c (PIN_OUTPUT | MUX_MODE7) /* spi0_cs0.gpio0_5 */
44 AM33XX_IOPAD(0x95c, PIN_OUTPUT | MUX_MODE7) /* spi0_cs0.gpio0_5 */
45 >;
46 };
47
48 gpmc_pins: gpmc_pins {
49 pinctrl-single,pins = <
45 >;
46 };
47
48 gpmc_pins: gpmc_pins {
49 pinctrl-single,pins = <
50 0x0 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */
51 0x4 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */
52 0x8 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */
53 0xc (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */
54 0x10 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */
55 0x14 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */
56 0x18 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */
57 0x1c (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */
58 0x20 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad8.gpmc_ad8 */
59 0x24 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad9.gpmc_ad9 */
60 0x28 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad10.gpmc_ad10 */
61 0x2c (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad11.gpmc_ad11 */
62 0x30 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad12.gpmc_ad12 */
63 0x34 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad13.gpmc_ad13 */
64 0x38 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad14.gpmc_ad14 */
65 0x3c (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad15.gpmc_ad15 */
50 AM33XX_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */
51 AM33XX_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */
52 AM33XX_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */
53 AM33XX_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */
54 AM33XX_IOPAD(0x810, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */
55 AM33XX_IOPAD(0x814, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */
56 AM33XX_IOPAD(0x818, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */
57 AM33XX_IOPAD(0x81c, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */
58 AM33XX_IOPAD(0x820, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad8.gpmc_ad8 */
59 AM33XX_IOPAD(0x824, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad9.gpmc_ad9 */
60 AM33XX_IOPAD(0x828, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad10.gpmc_ad10 */
61 AM33XX_IOPAD(0x82c, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad11.gpmc_ad11 */
62 AM33XX_IOPAD(0x830, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad12.gpmc_ad12 */
63 AM33XX_IOPAD(0x834, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad13.gpmc_ad13 */
64 AM33XX_IOPAD(0x838, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad14.gpmc_ad14 */
65 AM33XX_IOPAD(0x83c, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad15.gpmc_ad15 */
66
66
67 0x70 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */
68 0x7c (PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */
69 0x80 (PIN_OUTPUT | MUX_MODE0) /* gpmc_csn1.gpmc_csn1 */
70 0x84 (PIN_OUTPUT | MUX_MODE0) /* gpmc_csn2.gpmc_csn2 */
71 0x88 (PIN_OUTPUT | MUX_MODE0) /* gpmc_csn3.gpmc_csn3 */
67 AM33XX_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */
68 AM33XX_IOPAD(0x87c, PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */
69 AM33XX_IOPAD(0x880, PIN_OUTPUT | MUX_MODE0) /* gpmc_csn1.gpmc_csn1 */
70 AM33XX_IOPAD(0x884, PIN_OUTPUT | MUX_MODE0) /* gpmc_csn2.gpmc_csn2 */
71 AM33XX_IOPAD(0x888, PIN_OUTPUT | MUX_MODE0) /* gpmc_csn3.gpmc_csn3 */
72
72
73 0x90 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */
74 0x94 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */
75 0x98 (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */
76 0x9c (PIN_OUTPUT | MUX_MODE0) /* gpmc_ben0_cle.gpmc_ben0_cle */
73 AM33XX_IOPAD(0x890, PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */
74 AM33XX_IOPAD(0x894, PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */
75 AM33XX_IOPAD(0x898, PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */
76 AM33XX_IOPAD(0x89c, PIN_OUTPUT | MUX_MODE0) /* gpmc_ben0_cle.gpmc_ben0_cle */
77
77
78 0xa4 (PIN_OUTPUT | MUX_MODE1) /* lcd_data1.gpmc_a1 */
79 0xa8 (PIN_OUTPUT | MUX_MODE1) /* lcd_data2.gpmc_a2 */
80 0xac (PIN_OUTPUT | MUX_MODE1) /* lcd_data3.gpmc_a3 */
81 0xb0 (PIN_OUTPUT | MUX_MODE1) /* lcd_data4.gpmc_a4 */
82 0xb4 (PIN_OUTPUT | MUX_MODE1) /* lcd_data5.gpmc_a5 */
83 0xb8 (PIN_OUTPUT | MUX_MODE1) /* lcd_data6.gpmc_a6 */
84 0xbc (PIN_OUTPUT | MUX_MODE1) /* lcd_data7.gpmc_a7 */
78 AM33XX_IOPAD(0x8a4, PIN_OUTPUT | MUX_MODE1) /* lcd_data1.gpmc_a1 */
79 AM33XX_IOPAD(0x8a8, PIN_OUTPUT | MUX_MODE1) /* lcd_data2.gpmc_a2 */
80 AM33XX_IOPAD(0x8ac, PIN_OUTPUT | MUX_MODE1) /* lcd_data3.gpmc_a3 */
81 AM33XX_IOPAD(0x8b0, PIN_OUTPUT | MUX_MODE1) /* lcd_data4.gpmc_a4 */
82 AM33XX_IOPAD(0x8b4, PIN_OUTPUT | MUX_MODE1) /* lcd_data5.gpmc_a5 */
83 AM33XX_IOPAD(0x8b8, PIN_OUTPUT | MUX_MODE1) /* lcd_data6.gpmc_a6 */
84 AM33XX_IOPAD(0x8bc, PIN_OUTPUT | MUX_MODE1) /* lcd_data7.gpmc_a7 */
85
85
86 0xe0 (PIN_OUTPUT | MUX_MODE1) /* lcd_vsync.gpmc_a8 */
87 0xe4 (PIN_OUTPUT | MUX_MODE1) /* lcd_hsync.gpmc_a9 */
88 0xe8 (PIN_OUTPUT | MUX_MODE1) /* lcd_pclk.gpmc_a10 */
86 AM33XX_IOPAD(0x8e0, PIN_OUTPUT | MUX_MODE1) /* lcd_vsync.gpmc_a8 */
87 AM33XX_IOPAD(0x8e4, PIN_OUTPUT | MUX_MODE1) /* lcd_hsync.gpmc_a9 */
88 AM33XX_IOPAD(0x8e8, PIN_OUTPUT | MUX_MODE1) /* lcd_pclk.gpmc_a10 */
89 >;
90 };
91
92 i2c0_pins: i2c0_pins {
93 pinctrl-single,pins = <
89 >;
90 };
91
92 i2c0_pins: i2c0_pins {
93 pinctrl-single,pins = <
94 0x188 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* i2c0_sda.i2c0_sda */
95 0x18c (PIN_INPUT_PULLDOWN | MUX_MODE0) /* i2c0_scl.i2c0_scl */
94 AM33XX_IOPAD(0x988, PIN_INPUT_PULLDOWN | MUX_MODE0) /* i2c0_sda.i2c0_sda */
95 AM33XX_IOPAD(0x98c, PIN_INPUT_PULLDOWN | MUX_MODE0) /* i2c0_scl.i2c0_scl */
96 >;
97 };
98
99 uart0_pins: uart0_pins {
100 pinctrl-single,pins = <
96 >;
97 };
98
99 uart0_pins: uart0_pins {
100 pinctrl-single,pins = <
101 0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */
102 0x174 (PIN_OUTPUT | MUX_MODE0) /* uart0_txd.uart0_txd */
101 AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */
102 AM33XX_IOPAD(0x974, PIN_OUTPUT | MUX_MODE0) /* uart0_txd.uart0_txd */
103 >;
104 };
105
106 uart1_pins: uart1_pins {
107 pinctrl-single,pins = <
103 >;
104 };
105
106 uart1_pins: uart1_pins {
107 pinctrl-single,pins = <
108 0x178 (PIN_OUTPUT | MUX_MODE7) /* uart1_ctsn.uart1_ctsn */
109 0x17c (PIN_OUTPUT | MUX_MODE7) /* uart1_rtsn.uart1_rtsn */
110 0x180 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart1_rxd.uart1_rxd */
111 0x184 (PIN_OUTPUT | MUX_MODE0) /* uart1_txd.uart1_txd */
108 AM33XX_IOPAD(0x978, PIN_OUTPUT | MUX_MODE7) /* uart1_ctsn.uart1_ctsn */
109 AM33XX_IOPAD(0x97c, PIN_OUTPUT | MUX_MODE7) /* uart1_rtsn.uart1_rtsn */
110 AM33XX_IOPAD(0x980, PIN_INPUT_PULLUP | MUX_MODE0) /* uart1_rxd.uart1_rxd */
111 AM33XX_IOPAD(0x984, PIN_OUTPUT | MUX_MODE0) /* uart1_txd.uart1_txd */
112 >;
113 };
114
115 uart2_pins: uart2_pins {
116 pinctrl-single,pins = <
112 >;
113 };
114
115 uart2_pins: uart2_pins {
116 pinctrl-single,pins = <
117 0xc0 (PIN_INPUT_PULLUP | MUX_MODE7) /* lcd_data8.gpio2[14] */
118 0xc4 (PIN_OUTPUT | MUX_MODE7) /* lcd_data9.gpio2[15] */
119 0x150 (PIN_INPUT | MUX_MODE1) /* spi0_sclk.uart2_rxd */
120 0x154 (PIN_OUTPUT | MUX_MODE1) /* spi0_d0.uart2_txd */
117 AM33XX_IOPAD(0x8c0, PIN_INPUT_PULLUP | MUX_MODE7) /* lcd_data8.gpio2[14] */
118 AM33XX_IOPAD(0x8c4, PIN_OUTPUT | MUX_MODE7) /* lcd_data9.gpio2[15] */
119 AM33XX_IOPAD(0x950, PIN_INPUT | MUX_MODE1) /* spi0_sclk.uart2_rxd */
120 AM33XX_IOPAD(0x954, PIN_OUTPUT | MUX_MODE1) /* spi0_d0.uart2_txd */
121 >;
122 };
123
124 uart3_pins: uart3_pins {
125 pinctrl-single,pins = <
121 >;
122 };
123
124 uart3_pins: uart3_pins {
125 pinctrl-single,pins = <
126 0xc8 (PIN_INPUT_PULLUP | MUX_MODE6) /* lcd_data10.uart3_ctsn */
127 0xcc (PIN_OUTPUT | MUX_MODE6) /* lcd_data11.uart3_rtsn */
128 0x160 (PIN_INPUT | MUX_MODE1) /* spi0_cs1.uart3_rxd */
129 0x164 (PIN_OUTPUT | MUX_MODE1) /* ecap0_in_pwm0_out.uart3_txd */
126 AM33XX_IOPAD(0x8c8, PIN_INPUT_PULLUP | MUX_MODE6) /* lcd_data10.uart3_ctsn */
127 AM33XX_IOPAD(0x8cc, PIN_OUTPUT | MUX_MODE6) /* lcd_data11.uart3_rtsn */
128 AM33XX_IOPAD(0x960, PIN_INPUT | MUX_MODE1) /* spi0_cs1.uart3_rxd */
129 AM33XX_IOPAD(0x964, PIN_OUTPUT | MUX_MODE1) /* ecap0_in_pwm0_out.uart3_txd */
130 >;
131 };
132
133 uart4_pins: uart4_pins {
134 pinctrl-single,pins = <
130 >;
131 };
132
133 uart4_pins: uart4_pins {
134 pinctrl-single,pins = <
135 0xd0 (PIN_INPUT_PULLUP | MUX_MODE6) /* lcd_data12.uart4_ctsn */
136 0xd4 (PIN_OUTPUT | MUX_MODE6) /* lcd_data13.uart4_rtsn */
137 0x168 (PIN_INPUT | MUX_MODE1) /* uart0_ctsn.uart4_rxd */
138 0x16c (PIN_OUTPUT | MUX_MODE1) /* uart0_rtsn.uart4_txd */
135 AM33XX_IOPAD(0x8d0, PIN_INPUT_PULLUP | MUX_MODE6) /* lcd_data12.uart4_ctsn */
136 AM33XX_IOPAD(0x8d4, PIN_OUTPUT | MUX_MODE6) /* lcd_data13.uart4_rtsn */
137 AM33XX_IOPAD(0x968, PIN_INPUT | MUX_MODE1) /* uart0_ctsn.uart4_rxd */
138 AM33XX_IOPAD(0x96c, PIN_OUTPUT | MUX_MODE1) /* uart0_rtsn.uart4_txd */
139 >;
140 };
141
142 uart5_pins: uart5_pins {
143 pinctrl-single,pins = <
139 >;
140 };
141
142 uart5_pins: uart5_pins {
143 pinctrl-single,pins = <
144 0xd8 (PIN_INPUT | MUX_MODE4) /* lcd_data14.uart5_rxd */
145 0x144 (PIN_OUTPUT | MUX_MODE3) /* rmiii1_refclk.uart5_txd */
144 AM33XX_IOPAD(0x8d8, PIN_INPUT | MUX_MODE4) /* lcd_data14.uart5_rxd */
145 AM33XX_IOPAD(0x944, PIN_OUTPUT | MUX_MODE3) /* rmiii1_refclk.uart5_txd */
146 >;
147 };
148
149 mmc1_pins: mmc1_pins {
150 pinctrl-single,pins = <
146 >;
147 };
148
149 mmc1_pins: mmc1_pins {
150 pinctrl-single,pins = <
151 0xf0 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat0.mmc0_dat0 */
152 0xf4 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat1.mmc0_dat1 */
153 0xf8 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat2.mmc0_dat2 */
154 0xfc (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat3.mmc0_dat3 */
155 0x100 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_clk.mmc0_clk */
156 0x104 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_cmd.mmc0_cmd */
157 0x1e8 (PIN_INPUT_PULLUP | MUX_MODE7) /* emu1.gpio3[8] */
158 0x1a0 (PIN_INPUT_PULLUP | MUX_MODE7) /* mcasp0_aclkr.gpio3[18] */
151 AM33XX_IOPAD(0x8f0, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat0.mmc0_dat0 */
152 AM33XX_IOPAD(0x8f4, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat1.mmc0_dat1 */
153 AM33XX_IOPAD(0x8f8, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat2.mmc0_dat2 */
154 AM33XX_IOPAD(0x8fc, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat3.mmc0_dat3 */
155 AM33XX_IOPAD(0x900, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_clk.mmc0_clk */
156 AM33XX_IOPAD(0x904, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_cmd.mmc0_cmd */
157 AM33XX_IOPAD(0x9e8, PIN_INPUT_PULLUP | MUX_MODE7) /* emu1.gpio3[8] */
158 AM33XX_IOPAD(0x9a0, PIN_INPUT_PULLUP | MUX_MODE7) /* mcasp0_aclkr.gpio3[18] */
159 >;
160 };
161};
162
163&uart0 {
164 pinctrl-names = "default";
165 pinctrl-0 = <&uart0_pins>;
166 status = "okay";

--- 41 unchanged lines hidden (view full) ---

208&i2c0 {
209 status = "okay";
210 pinctrl-names = "default";
211 clock-frequency = <400000>;
212 pinctrl-names = "default";
213 pinctrl-0 = <&i2c0_pins>;
214
215 gpio@20 {
159 >;
160 };
161};
162
163&uart0 {
164 pinctrl-names = "default";
165 pinctrl-0 = <&uart0_pins>;
166 status = "okay";

--- 41 unchanged lines hidden (view full) ---

208&i2c0 {
209 status = "okay";
210 pinctrl-names = "default";
211 clock-frequency = <400000>;
212 pinctrl-names = "default";
213 pinctrl-0 = <&i2c0_pins>;
214
215 gpio@20 {
216 compatible = "mcp,mcp23017";
216 compatible = "microchip,mcp23017";
217 gpio-controller;
218 #gpio-cells = <2>;
217 reg = <0x20>;
218 };
219
220 tps: tps@24 {
221 reg = <0x24>;
222 };
223
224 eeprom@53 {
219 reg = <0x20>;
220 };
221
222 tps: tps@24 {
223 reg = <0x24>;
224 };
225
226 eeprom@53 {
225 compatible = "mcp,24c02";
227 compatible = "microchip,24c02";
226 reg = <0x53>;
227 pagesize = <8>;
228 };
229
230 rtc@68 {
231 compatible = "dallas,ds1307";
232 reg = <0x68>;
233 };

--- 58 unchanged lines hidden (view full) ---

292 | |-->0x000E0000-> ENV2 start
293 | |
294 | |-->0x000FFFFF-> ENV2 end
295 | |-->0x00100000-> Kernel start
296 | |
297 | |-->0x004FFFFF-> Kernel end
298 | |-->0x00500000-> File system start
299 | |
228 reg = <0x53>;
229 pagesize = <8>;
230 };
231
232 rtc@68 {
233 compatible = "dallas,ds1307";
234 reg = <0x68>;
235 };

--- 58 unchanged lines hidden (view full) ---

294 | |-->0x000E0000-> ENV2 start
295 | |
296 | |-->0x000FFFFF-> ENV2 end
297 | |-->0x00100000-> Kernel start
298 | |
299 | |-->0x004FFFFF-> Kernel end
300 | |-->0x00500000-> File system start
301 | |
300 | |-->0x014FFFFF-> File system end
301 | |-->0x01500000-> User data start
302 | |-->0x01FFFFFF-> File system end
303 | |-->0x02000000-> User data start
302 | |
303 | |-->0x03FFFFFF-> User data end
304 | |-->0x04000000-> Data storage start
305 | |
306 +------------+-->0x08000000-> NOR end (Free end)
307 */
308 partition@0 {
309 label = "boot";

--- 12 unchanged lines hidden (view full) ---

322
323 partition@3 {
324 label = "kernel";
325 reg = <0x00100000 0x00400000>; /* 4MB */
326 };
327
328 partition@4 {
329 label = "rootfs";
304 | |
305 | |-->0x03FFFFFF-> User data end
306 | |-->0x04000000-> Data storage start
307 | |
308 +------------+-->0x08000000-> NOR end (Free end)
309 */
310 partition@0 {
311 label = "boot";

--- 12 unchanged lines hidden (view full) ---

324
325 partition@3 {
326 label = "kernel";
327 reg = <0x00100000 0x00400000>; /* 4MB */
328 };
329
330 partition@4 {
331 label = "rootfs";
330 reg = <0x00500000 0x01000000>; /* 16MB */
332 reg = <0x00500000 0x01b00000>; /* 27MB */
331 };
332
333 partition@5 {
334 label = "user";
333 };
334
335 partition@5 {
336 label = "user";
335 reg = <0x01500000 0x02b00000>; /* 43MB */
337 reg = <0x02000000 0x02000000>; /* 32MB */
336 };
337
338 partition@6 {
339 label = "data";
340 reg = <0x04000000 0x04000000>; /* 64MB */
341 };
342 };
343};
344
345&mac {
338 };
339
340 partition@6 {
341 label = "data";
342 reg = <0x04000000 0x04000000>; /* 64MB */
343 };
344 };
345};
346
347&mac {
346 dual_emac = <1>;
348 dual_emac;
347 status = "okay";
348};
349
350&davinci_mdio {
351 status = "okay";
352};
353
354&cpsw_emac0 {
355 phy_id = <&davinci_mdio>, <0>;
349 status = "okay";
350};
351
352&davinci_mdio {
353 status = "okay";
354};
355
356&cpsw_emac0 {
357 phy_id = <&davinci_mdio>, <0>;
358 phy-mode = "mii";
356 dual_emac_res_vlan = <1>;
357};
358
359&cpsw_emac1 {
360 phy_id = <&davinci_mdio>, <1>;
359 dual_emac_res_vlan = <1>;
360};
361
362&cpsw_emac1 {
363 phy_id = <&davinci_mdio>, <1>;
364 phy-mode = "mii";
361 dual_emac_res_vlan = <2>;
362};
363
364&mmc1 {
365 status = "okay";
366 vmmc-supply = <&ldo4_reg>;
367 pinctrl-names = "default";
368 pinctrl-0 = <&mmc1_pins>;
369 bus-width = <4>;
370 cd-gpios = <&gpio3 8 0>;
371 wp-gpios = <&gpio3 18 0>;
372};
373
365 dual_emac_res_vlan = <2>;
366};
367
368&mmc1 {
369 status = "okay";
370 vmmc-supply = <&ldo4_reg>;
371 pinctrl-names = "default";
372 pinctrl-0 = <&mmc1_pins>;
373 bus-width = <4>;
374 cd-gpios = <&gpio3 8 0>;
375 wp-gpios = <&gpio3 18 0>;
376};
377
374#include "tps65217.dtsi"
375
376&tps {
378&tps {
379 compatible = "ti,tps65217";
380
377 regulators {
381 regulators {
382 #address-cells = <1>;
383 #size-cells = <0>;
384
378 dcdc1_reg: regulator@0 {
385 dcdc1_reg: regulator@0 {
386 reg = <0>;
379 /* +1.5V voltage with ��4% tolerance */
380 regulator-min-microvolt = <1450000>;
381 regulator-max-microvolt = <1550000>;
382 regulator-boot-on;
383 regulator-always-on;
384 };
385
386 dcdc2_reg: regulator@1 {
387 /* +1.5V voltage with ��4% tolerance */
388 regulator-min-microvolt = <1450000>;
389 regulator-max-microvolt = <1550000>;
390 regulator-boot-on;
391 regulator-always-on;
392 };
393
394 dcdc2_reg: regulator@1 {
395 reg = <1>;
387 /* VDD_MPU voltage limits 0.95V - 1.1V with ��4% tolerance */
388 regulator-name = "vdd_mpu";
389 regulator-min-microvolt = <915000>;
390 regulator-max-microvolt = <1140000>;
391 regulator-boot-on;
392 regulator-always-on;
393 };
394
395 dcdc3_reg: regulator@2 {
396 /* VDD_MPU voltage limits 0.95V - 1.1V with ��4% tolerance */
397 regulator-name = "vdd_mpu";
398 regulator-min-microvolt = <915000>;
399 regulator-max-microvolt = <1140000>;
400 regulator-boot-on;
401 regulator-always-on;
402 };
403
404 dcdc3_reg: regulator@2 {
405 reg = <2>;
396 /* VDD_CORE voltage limits 0.95V - 1.1V with ��4% tolerance */
397 regulator-name = "vdd_core";
398 regulator-min-microvolt = <915000>;
399 regulator-max-microvolt = <1140000>;
400 regulator-boot-on;
401 regulator-always-on;
402 };
403
404 ldo1_reg: regulator@3 {
406 /* VDD_CORE voltage limits 0.95V - 1.1V with ��4% tolerance */
407 regulator-name = "vdd_core";
408 regulator-min-microvolt = <915000>;
409 regulator-max-microvolt = <1140000>;
410 regulator-boot-on;
411 regulator-always-on;
412 };
413
414 ldo1_reg: regulator@3 {
415 reg = <3>;
405 /* +1.8V voltage with ��4% tolerance */
406 regulator-min-microvolt = <1750000>;
407 regulator-max-microvolt = <1870000>;
408 regulator-boot-on;
409 regulator-always-on;
410 };
411
412 ldo2_reg: regulator@4 {
416 /* +1.8V voltage with ��4% tolerance */
417 regulator-min-microvolt = <1750000>;
418 regulator-max-microvolt = <1870000>;
419 regulator-boot-on;
420 regulator-always-on;
421 };
422
423 ldo2_reg: regulator@4 {
424 reg = <4>;
413 /* +3.3V voltage with ��4% tolerance */
414 regulator-min-microvolt = <3175000>;
415 regulator-max-microvolt = <3430000>;
416 regulator-boot-on;
417 regulator-always-on;
418 };
419
420 ldo3_reg: regulator@5 {
425 /* +3.3V voltage with ��4% tolerance */
426 regulator-min-microvolt = <3175000>;
427 regulator-max-microvolt = <3430000>;
428 regulator-boot-on;
429 regulator-always-on;
430 };
431
432 ldo3_reg: regulator@5 {
433 reg = <5>;
421 /* +1.8V voltage with ��4% tolerance */
422 regulator-min-microvolt = <1750000>;
423 regulator-max-microvolt = <1870000>;
424 regulator-boot-on;
425 regulator-always-on;
426 };
427
428 ldo4_reg: regulator@6 {
434 /* +1.8V voltage with ��4% tolerance */
435 regulator-min-microvolt = <1750000>;
436 regulator-max-microvolt = <1870000>;
437 regulator-boot-on;
438 regulator-always-on;
439 };
440
441 ldo4_reg: regulator@6 {
442 reg = <6>;
429 /* +3.3V voltage with ��4% tolerance */
430 regulator-min-microvolt = <3175000>;
431 regulator-max-microvolt = <3430000>;
432 regulator-boot-on;
433 regulator-always-on;
434 };
435 };
436};
443 /* +3.3V voltage with ��4% tolerance */
444 regulator-min-microvolt = <3175000>;
445 regulator-max-microvolt = <3430000>;
446 regulator-boot-on;
447 regulator-always-on;
448 };
449 };
450};