19#include <sys/param.h>
20#include <sys/sockio.h>
21#include <sys/sysctl.h>
22#include <sys/lock.h>
23#include <sys/mutex.h>
24#include <sys/mbuf.h>
25#include <sys/kernel.h>
26#include <sys/socket.h>
27#include <sys/systm.h>
28#include <sys/malloc.h>
29#include <sys/module.h>
30#include <sys/bus.h>
31#include <sys/endian.h>
32#include <sys/kdb.h>
33
34#include <machine/bus.h>
35#include <machine/resource.h>
36#include <sys/rman.h>
37
38#include <net/if.h>
39#include <net/if_arp.h>
40#include <net/ethernet.h>
41#include <net/if_dl.h>
42#include <net/if_media.h>
43#include <net/if_types.h>
44
45#ifdef INET
46#include <netinet/in.h>
47#include <netinet/in_systm.h>
48#include <netinet/in_var.h>
49#include <netinet/if_ether.h>
50#include <netinet/ip.h>
51#endif
52
53#include <net80211/ieee80211_var.h>
54#include <net80211/ieee80211_regdomain.h>
55#include <net80211/ieee80211_radiotap.h>
56
57#include <dev/usb/usb.h>
58#include <dev/usb/usbdi.h>
59#include "usbdevs.h"
60
61#include <dev/usb/wlan/if_urtwreg.h>
62#include <dev/usb/wlan/if_urtwvar.h>
63
64static SYSCTL_NODE(_hw_usb, OID_AUTO, urtw, CTLFLAG_RW, 0, "USB Realtek 8187L");
65#ifdef URTW_DEBUG
66int urtw_debug = 0;
67SYSCTL_INT(_hw_usb_urtw, OID_AUTO, debug, CTLFLAG_RW | CTLFLAG_TUN, &urtw_debug, 0,
68 "control debugging printfs");
69TUNABLE_INT("hw.usb.urtw.debug", &urtw_debug);
70enum {
71 URTW_DEBUG_XMIT = 0x00000001, /* basic xmit operation */
72 URTW_DEBUG_RECV = 0x00000002, /* basic recv operation */
73 URTW_DEBUG_RESET = 0x00000004, /* reset processing */
74 URTW_DEBUG_TX_PROC = 0x00000008, /* tx ISR proc */
75 URTW_DEBUG_RX_PROC = 0x00000010, /* rx ISR proc */
76 URTW_DEBUG_STATE = 0x00000020, /* 802.11 state transitions */
77 URTW_DEBUG_STAT = 0x00000040, /* statistic */
78 URTW_DEBUG_INIT = 0x00000080, /* initialization of dev */
79 URTW_DEBUG_TXSTATUS = 0x00000100, /* tx status */
80 URTW_DEBUG_ANY = 0xffffffff
81};
82#define DPRINTF(sc, m, fmt, ...) do { \
83 if (sc->sc_debug & (m)) \
84 printf(fmt, __VA_ARGS__); \
85} while (0)
86#else
87#define DPRINTF(sc, m, fmt, ...) do { \
88 (void) sc; \
89} while (0)
90#endif
91static int urtw_preamble_mode = URTW_PREAMBLE_MODE_LONG;
92SYSCTL_INT(_hw_usb_urtw, OID_AUTO, preamble_mode, CTLFLAG_RW | CTLFLAG_TUN,
93 &urtw_preamble_mode, 0, "set the preable mode (long or short)");
94TUNABLE_INT("hw.usb.urtw.preamble_mode", &urtw_preamble_mode);
95
96/* recognized device vendors/products */
97#define urtw_lookup(v, p) \
98 ((const struct urtw_type *)usb_lookup(urtw_devs, v, p))
99#define URTW_DEV_B(v,p) \
100 { USB_VPI(USB_VENDOR_##v, USB_PRODUCT_##v##_##p, URTW_REV_RTL8187B) }
101#define URTW_DEV_L(v,p) \
102 { USB_VPI(USB_VENDOR_##v, USB_PRODUCT_##v##_##p, URTW_REV_RTL8187L) }
103#define URTW_REV_RTL8187B 0
104#define URTW_REV_RTL8187L 1
105static const STRUCT_USB_HOST_ID urtw_devs[] = {
106 URTW_DEV_B(NETGEAR, WG111V3),
107 URTW_DEV_B(REALTEK, RTL8187B_0),
108 URTW_DEV_B(REALTEK, RTL8187B_1),
109 URTW_DEV_B(REALTEK, RTL8187B_2),
110 URTW_DEV_B(SITECOMEU, WL168V4),
111 URTW_DEV_L(ASUS, P5B_WIFI),
112 URTW_DEV_L(BELKIN, F5D7050E),
113 URTW_DEV_L(LINKSYS4, WUSB54GCV2),
114 URTW_DEV_L(NETGEAR, WG111V2),
115 URTW_DEV_L(REALTEK, RTL8187),
116 URTW_DEV_L(SITECOMEU, WL168V1),
117 URTW_DEV_L(SURECOM, EP9001G2A),
118 { USB_VPI(USB_VENDOR_OVISLINK, 0x8187, URTW_REV_RTL8187L) },
119 { USB_VPI(USB_VENDOR_DICKSMITH, 0x9401, URTW_REV_RTL8187L) },
120 { USB_VPI(USB_VENDOR_HP, 0xca02, URTW_REV_RTL8187L) },
121 { USB_VPI(USB_VENDOR_LOGITEC, 0x010c, URTW_REV_RTL8187L) },
122 { USB_VPI(USB_VENDOR_NETGEAR, 0x6100, URTW_REV_RTL8187L) },
123 { USB_VPI(USB_VENDOR_SPHAIRON, 0x0150, URTW_REV_RTL8187L) },
124 { USB_VPI(USB_VENDOR_QCOM, 0x6232, URTW_REV_RTL8187L) },
125#undef URTW_DEV_L
126#undef URTW_DEV_B
127};
128
129#define urtw_read8_m(sc, val, data) do { \
130 error = urtw_read8_c(sc, val, data); \
131 if (error != 0) \
132 goto fail; \
133} while (0)
134#define urtw_write8_m(sc, val, data) do { \
135 error = urtw_write8_c(sc, val, data); \
136 if (error != 0) \
137 goto fail; \
138} while (0)
139#define urtw_read16_m(sc, val, data) do { \
140 error = urtw_read16_c(sc, val, data); \
141 if (error != 0) \
142 goto fail; \
143} while (0)
144#define urtw_write16_m(sc, val, data) do { \
145 error = urtw_write16_c(sc, val, data); \
146 if (error != 0) \
147 goto fail; \
148} while (0)
149#define urtw_read32_m(sc, val, data) do { \
150 error = urtw_read32_c(sc, val, data); \
151 if (error != 0) \
152 goto fail; \
153} while (0)
154#define urtw_write32_m(sc, val, data) do { \
155 error = urtw_write32_c(sc, val, data); \
156 if (error != 0) \
157 goto fail; \
158} while (0)
159#define urtw_8187_write_phy_ofdm(sc, val, data) do { \
160 error = urtw_8187_write_phy_ofdm_c(sc, val, data); \
161 if (error != 0) \
162 goto fail; \
163} while (0)
164#define urtw_8187_write_phy_cck(sc, val, data) do { \
165 error = urtw_8187_write_phy_cck_c(sc, val, data); \
166 if (error != 0) \
167 goto fail; \
168} while (0)
169#define urtw_8225_write(sc, val, data) do { \
170 error = urtw_8225_write_c(sc, val, data); \
171 if (error != 0) \
172 goto fail; \
173} while (0)
174
175struct urtw_pair {
176 uint32_t reg;
177 uint32_t val;
178};
179
180static uint8_t urtw_8225_agc[] = {
181 0x9e, 0x9e, 0x9e, 0x9e, 0x9e, 0x9e, 0x9e, 0x9e, 0x9d, 0x9c, 0x9b,
182 0x9a, 0x99, 0x98, 0x97, 0x96, 0x95, 0x94, 0x93, 0x92, 0x91, 0x90,
183 0x8f, 0x8e, 0x8d, 0x8c, 0x8b, 0x8a, 0x89, 0x88, 0x87, 0x86, 0x85,
184 0x84, 0x83, 0x82, 0x81, 0x80, 0x3f, 0x3e, 0x3d, 0x3c, 0x3b, 0x3a,
185 0x39, 0x38, 0x37, 0x36, 0x35, 0x34, 0x33, 0x32, 0x31, 0x30, 0x2f,
186 0x2e, 0x2d, 0x2c, 0x2b, 0x2a, 0x29, 0x28, 0x27, 0x26, 0x25, 0x24,
187 0x23, 0x22, 0x21, 0x20, 0x1f, 0x1e, 0x1d, 0x1c, 0x1b, 0x1a, 0x19,
188 0x18, 0x17, 0x16, 0x15, 0x14, 0x13, 0x12, 0x11, 0x10, 0x0f, 0x0e,
189 0x0d, 0x0c, 0x0b, 0x0a, 0x09, 0x08, 0x07, 0x06, 0x05, 0x04, 0x03,
190 0x02, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
191 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
192 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01
193};
194
195static uint8_t urtw_8225z2_agc[] = {
196 0x5e, 0x5e, 0x5e, 0x5e, 0x5d, 0x5b, 0x59, 0x57, 0x55, 0x53, 0x51,
197 0x4f, 0x4d, 0x4b, 0x49, 0x47, 0x45, 0x43, 0x41, 0x3f, 0x3d, 0x3b,
198 0x39, 0x37, 0x35, 0x33, 0x31, 0x2f, 0x2d, 0x2b, 0x29, 0x27, 0x25,
199 0x23, 0x21, 0x1f, 0x1d, 0x1b, 0x19, 0x17, 0x15, 0x13, 0x11, 0x0f,
200 0x0d, 0x0b, 0x09, 0x07, 0x05, 0x03, 0x01, 0x01, 0x01, 0x01, 0x01,
201 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x19, 0x19,
202 0x19, 0x19, 0x19, 0x19, 0x19, 0x19, 0x19, 0x20, 0x21, 0x22, 0x23,
203 0x24, 0x25, 0x26, 0x26, 0x27, 0x27, 0x28, 0x28, 0x29, 0x2a, 0x2a,
204 0x2a, 0x2b, 0x2b, 0x2b, 0x2c, 0x2c, 0x2c, 0x2d, 0x2d, 0x2d, 0x2d,
205 0x2e, 0x2e, 0x2e, 0x2e, 0x2f, 0x2f, 0x2f, 0x30, 0x30, 0x31, 0x31,
206 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31,
207 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31
208};
209
210static uint32_t urtw_8225_channel[] = {
211 0x0000, /* dummy channel 0 */
212 0x085c, /* 1 */
213 0x08dc, /* 2 */
214 0x095c, /* 3 */
215 0x09dc, /* 4 */
216 0x0a5c, /* 5 */
217 0x0adc, /* 6 */
218 0x0b5c, /* 7 */
219 0x0bdc, /* 8 */
220 0x0c5c, /* 9 */
221 0x0cdc, /* 10 */
222 0x0d5c, /* 11 */
223 0x0ddc, /* 12 */
224 0x0e5c, /* 13 */
225 0x0f72, /* 14 */
226};
227
228static uint8_t urtw_8225_gain[] = {
229 0x23, 0x88, 0x7c, 0xa5, /* -82dbm */
230 0x23, 0x88, 0x7c, 0xb5, /* -82dbm */
231 0x23, 0x88, 0x7c, 0xc5, /* -82dbm */
232 0x33, 0x80, 0x79, 0xc5, /* -78dbm */
233 0x43, 0x78, 0x76, 0xc5, /* -74dbm */
234 0x53, 0x60, 0x73, 0xc5, /* -70dbm */
235 0x63, 0x58, 0x70, 0xc5, /* -66dbm */
236};
237
238static struct urtw_pair urtw_8225_rf_part1[] = {
239 { 0x00, 0x0067 }, { 0x01, 0x0fe0 }, { 0x02, 0x044d }, { 0x03, 0x0441 },
240 { 0x04, 0x0486 }, { 0x05, 0x0bc0 }, { 0x06, 0x0ae6 }, { 0x07, 0x082a },
241 { 0x08, 0x001f }, { 0x09, 0x0334 }, { 0x0a, 0x0fd4 }, { 0x0b, 0x0391 },
242 { 0x0c, 0x0050 }, { 0x0d, 0x06db }, { 0x0e, 0x0029 }, { 0x0f, 0x0914 },
243};
244
245static struct urtw_pair urtw_8225_rf_part2[] = {
246 { 0x00, 0x01 }, { 0x01, 0x02 }, { 0x02, 0x42 }, { 0x03, 0x00 },
247 { 0x04, 0x00 }, { 0x05, 0x00 }, { 0x06, 0x40 }, { 0x07, 0x00 },
248 { 0x08, 0x40 }, { 0x09, 0xfe }, { 0x0a, 0x09 }, { 0x0b, 0x80 },
249 { 0x0c, 0x01 }, { 0x0e, 0xd3 }, { 0x0f, 0x38 }, { 0x10, 0x84 },
250 { 0x11, 0x06 }, { 0x12, 0x20 }, { 0x13, 0x20 }, { 0x14, 0x00 },
251 { 0x15, 0x40 }, { 0x16, 0x00 }, { 0x17, 0x40 }, { 0x18, 0xef },
252 { 0x19, 0x19 }, { 0x1a, 0x20 }, { 0x1b, 0x76 }, { 0x1c, 0x04 },
253 { 0x1e, 0x95 }, { 0x1f, 0x75 }, { 0x20, 0x1f }, { 0x21, 0x27 },
254 { 0x22, 0x16 }, { 0x24, 0x46 }, { 0x25, 0x20 }, { 0x26, 0x90 },
255 { 0x27, 0x88 }
256};
257
258static struct urtw_pair urtw_8225_rf_part3[] = {
259 { 0x00, 0x98 }, { 0x03, 0x20 }, { 0x04, 0x7e }, { 0x05, 0x12 },
260 { 0x06, 0xfc }, { 0x07, 0x78 }, { 0x08, 0x2e }, { 0x10, 0x9b },
261 { 0x11, 0x88 }, { 0x12, 0x47 }, { 0x13, 0xd0 }, { 0x19, 0x00 },
262 { 0x1a, 0xa0 }, { 0x1b, 0x08 }, { 0x40, 0x86 }, { 0x41, 0x8d },
263 { 0x42, 0x15 }, { 0x43, 0x18 }, { 0x44, 0x1f }, { 0x45, 0x1e },
264 { 0x46, 0x1a }, { 0x47, 0x15 }, { 0x48, 0x10 }, { 0x49, 0x0a },
265 { 0x4a, 0x05 }, { 0x4b, 0x02 }, { 0x4c, 0x05 }
266};
267
268static uint16_t urtw_8225_rxgain[] = {
269 0x0400, 0x0401, 0x0402, 0x0403, 0x0404, 0x0405, 0x0408, 0x0409,
270 0x040a, 0x040b, 0x0502, 0x0503, 0x0504, 0x0505, 0x0540, 0x0541,
271 0x0542, 0x0543, 0x0544, 0x0545, 0x0580, 0x0581, 0x0582, 0x0583,
272 0x0584, 0x0585, 0x0588, 0x0589, 0x058a, 0x058b, 0x0643, 0x0644,
273 0x0645, 0x0680, 0x0681, 0x0682, 0x0683, 0x0684, 0x0685, 0x0688,
274 0x0689, 0x068a, 0x068b, 0x068c, 0x0742, 0x0743, 0x0744, 0x0745,
275 0x0780, 0x0781, 0x0782, 0x0783, 0x0784, 0x0785, 0x0788, 0x0789,
276 0x078a, 0x078b, 0x078c, 0x078d, 0x0790, 0x0791, 0x0792, 0x0793,
277 0x0794, 0x0795, 0x0798, 0x0799, 0x079a, 0x079b, 0x079c, 0x079d,
278 0x07a0, 0x07a1, 0x07a2, 0x07a3, 0x07a4, 0x07a5, 0x07a8, 0x07a9,
279 0x07aa, 0x07ab, 0x07ac, 0x07ad, 0x07b0, 0x07b1, 0x07b2, 0x07b3,
280 0x07b4, 0x07b5, 0x07b8, 0x07b9, 0x07ba, 0x07bb, 0x07bb
281};
282
283static uint8_t urtw_8225_threshold[] = {
284 0x8d, 0x8d, 0x8d, 0x8d, 0x9d, 0xad, 0xbd,
285};
286
287static uint8_t urtw_8225_tx_gain_cck_ofdm[] = {
288 0x02, 0x06, 0x0e, 0x1e, 0x3e, 0x7e
289};
290
291static uint8_t urtw_8225_txpwr_cck[] = {
292 0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02,
293 0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02,
294 0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02,
295 0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02,
296 0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03,
297 0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03
298};
299
300static uint8_t urtw_8225_txpwr_cck_ch14[] = {
301 0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00,
302 0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00,
303 0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00,
304 0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00,
305 0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00,
306 0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00
307};
308
309static uint8_t urtw_8225_txpwr_ofdm[]={
310 0x80, 0x90, 0xa2, 0xb5, 0xcb, 0xe4
311};
312
313static uint8_t urtw_8225v2_gain_bg[]={
314 0x23, 0x15, 0xa5, /* -82-1dbm */
315 0x23, 0x15, 0xb5, /* -82-2dbm */
316 0x23, 0x15, 0xc5, /* -82-3dbm */
317 0x33, 0x15, 0xc5, /* -78dbm */
318 0x43, 0x15, 0xc5, /* -74dbm */
319 0x53, 0x15, 0xc5, /* -70dbm */
320 0x63, 0x15, 0xc5, /* -66dbm */
321};
322
323static struct urtw_pair urtw_8225v2_rf_part1[] = {
324 { 0x00, 0x02bf }, { 0x01, 0x0ee0 }, { 0x02, 0x044d }, { 0x03, 0x0441 },
325 { 0x04, 0x08c3 }, { 0x05, 0x0c72 }, { 0x06, 0x00e6 }, { 0x07, 0x082a },
326 { 0x08, 0x003f }, { 0x09, 0x0335 }, { 0x0a, 0x09d4 }, { 0x0b, 0x07bb },
327 { 0x0c, 0x0850 }, { 0x0d, 0x0cdf }, { 0x0e, 0x002b }, { 0x0f, 0x0114 }
328};
329
330static struct urtw_pair urtw_8225v2b_rf_part0[] = {
331 { 0x00, 0x00b7 }, { 0x01, 0x0ee0 }, { 0x02, 0x044d }, { 0x03, 0x0441 },
332 { 0x04, 0x08c3 }, { 0x05, 0x0c72 }, { 0x06, 0x00e6 }, { 0x07, 0x082a },
333 { 0x08, 0x003f }, { 0x09, 0x0335 }, { 0x0a, 0x09d4 }, { 0x0b, 0x07bb },
334 { 0x0c, 0x0850 }, { 0x0d, 0x0cdf }, { 0x0e, 0x002b }, { 0x0f, 0x0114 }
335};
336
337static struct urtw_pair urtw_8225v2b_rf_part1[] = {
338 {0x0f0, 0x32}, {0x0f1, 0x32}, {0x0f2, 0x00},
339 {0x0f3, 0x00}, {0x0f4, 0x32}, {0x0f5, 0x43},
340 {0x0f6, 0x00}, {0x0f7, 0x00}, {0x0f8, 0x46},
341 {0x0f9, 0xa4}, {0x0fa, 0x00}, {0x0fb, 0x00},
342 {0x0fc, 0x96}, {0x0fd, 0xa4}, {0x0fe, 0x00},
343 {0x0ff, 0x00}, {0x158, 0x4b}, {0x159, 0x00},
344 {0x15a, 0x4b}, {0x15b, 0x00}, {0x160, 0x4b},
345 {0x161, 0x09}, {0x162, 0x4b}, {0x163, 0x09},
346 {0x1ce, 0x0f}, {0x1cf, 0x00}, {0x1e0, 0xff},
347 {0x1e1, 0x0f}, {0x1e2, 0x00}, {0x1f0, 0x4e},
348 {0x1f1, 0x01}, {0x1f2, 0x02}, {0x1f3, 0x03},
349 {0x1f4, 0x04}, {0x1f5, 0x05}, {0x1f6, 0x06},
350 {0x1f7, 0x07}, {0x1f8, 0x08}, {0x24e, 0x00},
351 {0x20c, 0x04}, {0x221, 0x61}, {0x222, 0x68},
352 {0x223, 0x6f}, {0x224, 0x76}, {0x225, 0x7d},
353 {0x226, 0x84}, {0x227, 0x8d}, {0x24d, 0x08},
354 {0x250, 0x05}, {0x251, 0xf5}, {0x252, 0x04},
355 {0x253, 0xa0}, {0x254, 0x1f}, {0x255, 0x23},
356 {0x256, 0x45}, {0x257, 0x67}, {0x258, 0x08},
357 {0x259, 0x08}, {0x25a, 0x08}, {0x25b, 0x08},
358 {0x260, 0x08}, {0x261, 0x08}, {0x262, 0x08},
359 {0x263, 0x08}, {0x264, 0xcf}, {0x272, 0x56},
360 {0x273, 0x9a}, {0x034, 0xf0}, {0x035, 0x0f},
361 {0x05b, 0x40}, {0x084, 0x88}, {0x085, 0x24},
362 {0x088, 0x54}, {0x08b, 0xb8}, {0x08c, 0x07},
363 {0x08d, 0x00}, {0x094, 0x1b}, {0x095, 0x12},
364 {0x096, 0x00}, {0x097, 0x06}, {0x09d, 0x1a},
365 {0x09f, 0x10}, {0x0b4, 0x22}, {0x0be, 0x80},
366 {0x0db, 0x00}, {0x0ee, 0x00}, {0x091, 0x03},
367 {0x24c, 0x00}, {0x39f, 0x00}, {0x08c, 0x01},
368 {0x08d, 0x10}, {0x08e, 0x08}, {0x08f, 0x00}
369};
370
371static struct urtw_pair urtw_8225v2_rf_part2[] = {
372 { 0x00, 0x01 }, { 0x01, 0x02 }, { 0x02, 0x42 }, { 0x03, 0x00 },
373 { 0x04, 0x00 }, { 0x05, 0x00 }, { 0x06, 0x40 }, { 0x07, 0x00 },
374 { 0x08, 0x40 }, { 0x09, 0xfe }, { 0x0a, 0x08 }, { 0x0b, 0x80 },
375 { 0x0c, 0x01 }, { 0x0d, 0x43 }, { 0x0e, 0xd3 }, { 0x0f, 0x38 },
376 { 0x10, 0x84 }, { 0x11, 0x07 }, { 0x12, 0x20 }, { 0x13, 0x20 },
377 { 0x14, 0x00 }, { 0x15, 0x40 }, { 0x16, 0x00 }, { 0x17, 0x40 },
378 { 0x18, 0xef }, { 0x19, 0x19 }, { 0x1a, 0x20 }, { 0x1b, 0x15 },
379 { 0x1c, 0x04 }, { 0x1d, 0xc5 }, { 0x1e, 0x95 }, { 0x1f, 0x75 },
380 { 0x20, 0x1f }, { 0x21, 0x17 }, { 0x22, 0x16 }, { 0x23, 0x80 },
381 { 0x24, 0x46 }, { 0x25, 0x00 }, { 0x26, 0x90 }, { 0x27, 0x88 }
382};
383
384static struct urtw_pair urtw_8225v2b_rf_part2[] = {
385 { 0x00, 0x10 }, { 0x01, 0x0d }, { 0x02, 0x01 }, { 0x03, 0x00 },
386 { 0x04, 0x14 }, { 0x05, 0xfb }, { 0x06, 0xfb }, { 0x07, 0x60 },
387 { 0x08, 0x00 }, { 0x09, 0x60 }, { 0x0a, 0x00 }, { 0x0b, 0x00 },
388 { 0x0c, 0x00 }, { 0x0d, 0x5c }, { 0x0e, 0x00 }, { 0x0f, 0x00 },
389 { 0x10, 0x40 }, { 0x11, 0x00 }, { 0x12, 0x40 }, { 0x13, 0x00 },
390 { 0x14, 0x00 }, { 0x15, 0x00 }, { 0x16, 0xa8 }, { 0x17, 0x26 },
391 { 0x18, 0x32 }, { 0x19, 0x33 }, { 0x1a, 0x07 }, { 0x1b, 0xa5 },
392 { 0x1c, 0x6f }, { 0x1d, 0x55 }, { 0x1e, 0xc8 }, { 0x1f, 0xb3 },
393 { 0x20, 0x0a }, { 0x21, 0xe1 }, { 0x22, 0x2C }, { 0x23, 0x8a },
394 { 0x24, 0x86 }, { 0x25, 0x83 }, { 0x26, 0x34 }, { 0x27, 0x0f },
395 { 0x28, 0x4f }, { 0x29, 0x24 }, { 0x2a, 0x6f }, { 0x2b, 0xc2 },
396 { 0x2c, 0x6b }, { 0x2d, 0x40 }, { 0x2e, 0x80 }, { 0x2f, 0x00 },
397 { 0x30, 0xc0 }, { 0x31, 0xc1 }, { 0x32, 0x58 }, { 0x33, 0xf1 },
398 { 0x34, 0x00 }, { 0x35, 0xe4 }, { 0x36, 0x90 }, { 0x37, 0x3e },
399 { 0x38, 0x6d }, { 0x39, 0x3c }, { 0x3a, 0xfb }, { 0x3b, 0x07 }
400};
401
402static struct urtw_pair urtw_8225v2_rf_part3[] = {
403 { 0x00, 0x98 }, { 0x03, 0x20 }, { 0x04, 0x7e }, { 0x05, 0x12 },
404 { 0x06, 0xfc }, { 0x07, 0x78 }, { 0x08, 0x2e }, { 0x09, 0x11 },
405 { 0x0a, 0x17 }, { 0x0b, 0x11 }, { 0x10, 0x9b }, { 0x11, 0x88 },
406 { 0x12, 0x47 }, { 0x13, 0xd0 }, { 0x19, 0x00 }, { 0x1a, 0xa0 },
407 { 0x1b, 0x08 }, { 0x1d, 0x00 }, { 0x40, 0x86 }, { 0x41, 0x9d },
408 { 0x42, 0x15 }, { 0x43, 0x18 }, { 0x44, 0x36 }, { 0x45, 0x35 },
409 { 0x46, 0x2e }, { 0x47, 0x25 }, { 0x48, 0x1c }, { 0x49, 0x12 },
410 { 0x4a, 0x09 }, { 0x4b, 0x04 }, { 0x4c, 0x05 }
411};
412
413static uint16_t urtw_8225v2_rxgain[] = {
414 0x0000, 0x0001, 0x0002, 0x0003, 0x0004, 0x0005, 0x0008, 0x0009,
415 0x000a, 0x000b, 0x0102, 0x0103, 0x0104, 0x0105, 0x0140, 0x0141,
416 0x0142, 0x0143, 0x0144, 0x0145, 0x0180, 0x0181, 0x0182, 0x0183,
417 0x0184, 0x0185, 0x0188, 0x0189, 0x018a, 0x018b, 0x0243, 0x0244,
418 0x0245, 0x0280, 0x0281, 0x0282, 0x0283, 0x0284, 0x0285, 0x0288,
419 0x0289, 0x028a, 0x028b, 0x028c, 0x0342, 0x0343, 0x0344, 0x0345,
420 0x0380, 0x0381, 0x0382, 0x0383, 0x0384, 0x0385, 0x0388, 0x0389,
421 0x038a, 0x038b, 0x038c, 0x038d, 0x0390, 0x0391, 0x0392, 0x0393,
422 0x0394, 0x0395, 0x0398, 0x0399, 0x039a, 0x039b, 0x039c, 0x039d,
423 0x03a0, 0x03a1, 0x03a2, 0x03a3, 0x03a4, 0x03a5, 0x03a8, 0x03a9,
424 0x03aa, 0x03ab, 0x03ac, 0x03ad, 0x03b0, 0x03b1, 0x03b2, 0x03b3,
425 0x03b4, 0x03b5, 0x03b8, 0x03b9, 0x03ba, 0x03bb, 0x03bb
426};
427
428static uint16_t urtw_8225v2b_rxgain[] = {
429 0x0400, 0x0401, 0x0402, 0x0403, 0x0404, 0x0405, 0x0408, 0x0409,
430 0x040a, 0x040b, 0x0502, 0x0503, 0x0504, 0x0505, 0x0540, 0x0541,
431 0x0542, 0x0543, 0x0544, 0x0545, 0x0580, 0x0581, 0x0582, 0x0583,
432 0x0584, 0x0585, 0x0588, 0x0589, 0x058a, 0x058b, 0x0643, 0x0644,
433 0x0645, 0x0680, 0x0681, 0x0682, 0x0683, 0x0684, 0x0685, 0x0688,
434 0x0689, 0x068a, 0x068b, 0x068c, 0x0742, 0x0743, 0x0744, 0x0745,
435 0x0780, 0x0781, 0x0782, 0x0783, 0x0784, 0x0785, 0x0788, 0x0789,
436 0x078a, 0x078b, 0x078c, 0x078d, 0x0790, 0x0791, 0x0792, 0x0793,
437 0x0794, 0x0795, 0x0798, 0x0799, 0x079a, 0x079b, 0x079c, 0x079d,
438 0x07a0, 0x07a1, 0x07a2, 0x07a3, 0x07a4, 0x07a5, 0x07a8, 0x07a9,
439 0x03aa, 0x03ab, 0x03ac, 0x03ad, 0x03b0, 0x03b1, 0x03b2, 0x03b3,
440 0x03b4, 0x03b5, 0x03b8, 0x03b9, 0x03ba, 0x03bb, 0x03bb
441};
442
443static uint8_t urtw_8225v2_tx_gain_cck_ofdm[] = {
444 0x00, 0x01, 0x02, 0x03, 0x04, 0x05,
445 0x06, 0x07, 0x08, 0x09, 0x0a, 0x0b,
446 0x0c, 0x0d, 0x0e, 0x0f, 0x10, 0x11,
447 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
448 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d,
449 0x1e, 0x1f, 0x20, 0x21, 0x22, 0x23,
450};
451
452static uint8_t urtw_8225v2_txpwr_cck[] = {
453 0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04
454};
455
456static uint8_t urtw_8225v2_txpwr_cck_ch14[] = {
457 0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00
458};
459
460static uint8_t urtw_8225v2b_txpwr_cck[] = {
461 0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04,
462 0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03,
463 0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03,
464 0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03
465};
466
467static uint8_t urtw_8225v2b_txpwr_cck_ch14[] = {
468 0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00,
469 0x30, 0x2f, 0x29, 0x15, 0x00, 0x00, 0x00, 0x00,
470 0x30, 0x2f, 0x29, 0x15, 0x00, 0x00, 0x00, 0x00,
471 0x30, 0x2f, 0x29, 0x15, 0x00, 0x00, 0x00, 0x00
472};
473
474static struct urtw_pair urtw_ratetable[] = {
475 { 2, 0 }, { 4, 1 }, { 11, 2 }, { 12, 4 }, { 18, 5 },
476 { 22, 3 }, { 24, 6 }, { 36, 7 }, { 48, 8 }, { 72, 9 },
477 { 96, 10 }, { 108, 11 }
478};
479
480static const uint8_t urtw_8187b_reg_table[][3] = {
481 { 0xf0, 0x32, 0 }, { 0xf1, 0x32, 0 }, { 0xf2, 0x00, 0 },
482 { 0xf3, 0x00, 0 }, { 0xf4, 0x32, 0 }, { 0xf5, 0x43, 0 },
483 { 0xf6, 0x00, 0 }, { 0xf7, 0x00, 0 }, { 0xf8, 0x46, 0 },
484 { 0xf9, 0xa4, 0 }, { 0xfa, 0x00, 0 }, { 0xfb, 0x00, 0 },
485 { 0xfc, 0x96, 0 }, { 0xfd, 0xa4, 0 }, { 0xfe, 0x00, 0 },
486 { 0xff, 0x00, 0 }, { 0x58, 0x4b, 1 }, { 0x59, 0x00, 1 },
487 { 0x5a, 0x4b, 1 }, { 0x5b, 0x00, 1 }, { 0x60, 0x4b, 1 },
488 { 0x61, 0x09, 1 }, { 0x62, 0x4b, 1 }, { 0x63, 0x09, 1 },
489 { 0xce, 0x0f, 1 }, { 0xcf, 0x00, 1 }, { 0xe0, 0xff, 1 },
490 { 0xe1, 0x0f, 1 }, { 0xe2, 0x00, 1 }, { 0xf0, 0x4e, 1 },
491 { 0xf1, 0x01, 1 }, { 0xf2, 0x02, 1 }, { 0xf3, 0x03, 1 },
492 { 0xf4, 0x04, 1 }, { 0xf5, 0x05, 1 }, { 0xf6, 0x06, 1 },
493 { 0xf7, 0x07, 1 }, { 0xf8, 0x08, 1 }, { 0x4e, 0x00, 2 },
494 { 0x0c, 0x04, 2 }, { 0x21, 0x61, 2 }, { 0x22, 0x68, 2 },
495 { 0x23, 0x6f, 2 }, { 0x24, 0x76, 2 }, { 0x25, 0x7d, 2 },
496 { 0x26, 0x84, 2 }, { 0x27, 0x8d, 2 }, { 0x4d, 0x08, 2 },
497 { 0x50, 0x05, 2 }, { 0x51, 0xf5, 2 }, { 0x52, 0x04, 2 },
498 { 0x53, 0xa0, 2 }, { 0x54, 0x1f, 2 }, { 0x55, 0x23, 2 },
499 { 0x56, 0x45, 2 }, { 0x57, 0x67, 2 }, { 0x58, 0x08, 2 },
500 { 0x59, 0x08, 2 }, { 0x5a, 0x08, 2 }, { 0x5b, 0x08, 2 },
501 { 0x60, 0x08, 2 }, { 0x61, 0x08, 2 }, { 0x62, 0x08, 2 },
502 { 0x63, 0x08, 2 }, { 0x64, 0xcf, 2 }, { 0x72, 0x56, 2 },
503 { 0x73, 0x9a, 2 }, { 0x34, 0xf0, 0 }, { 0x35, 0x0f, 0 },
504 { 0x5b, 0x40, 0 }, { 0x84, 0x88, 0 }, { 0x85, 0x24, 0 },
505 { 0x88, 0x54, 0 }, { 0x8b, 0xb8, 0 }, { 0x8c, 0x07, 0 },
506 { 0x8d, 0x00, 0 }, { 0x94, 0x1b, 0 }, { 0x95, 0x12, 0 },
507 { 0x96, 0x00, 0 }, { 0x97, 0x06, 0 }, { 0x9d, 0x1a, 0 },
508 { 0x9f, 0x10, 0 }, { 0xb4, 0x22, 0 }, { 0xbe, 0x80, 0 },
509 { 0xdb, 0x00, 0 }, { 0xee, 0x00, 0 }, { 0x91, 0x03, 0 },
510 { 0x4c, 0x00, 2 }, { 0x9f, 0x00, 3 }, { 0x8c, 0x01, 0 },
511 { 0x8d, 0x10, 0 }, { 0x8e, 0x08, 0 }, { 0x8f, 0x00, 0 }
512};
513
514static usb_callback_t urtw_bulk_rx_callback;
515static usb_callback_t urtw_bulk_tx_callback;
516static usb_callback_t urtw_bulk_tx_status_callback;
517
518static const struct usb_config urtw_8187b_usbconfig[URTW_8187B_N_XFERS] = {
519 [URTW_8187B_BULK_RX] = {
520 .type = UE_BULK,
521 .endpoint = 0x83,
522 .direction = UE_DIR_IN,
523 .bufsize = MCLBYTES,
524 .flags = {
525 .ext_buffer = 1,
526 .pipe_bof = 1,
527 .short_xfer_ok = 1
528 },
529 .callback = urtw_bulk_rx_callback
530 },
531 [URTW_8187B_BULK_TX_STATUS] = {
532 .type = UE_BULK,
533 .endpoint = 0x89,
534 .direction = UE_DIR_IN,
| 19#include <sys/param.h>
20#include <sys/sockio.h>
21#include <sys/sysctl.h>
22#include <sys/lock.h>
23#include <sys/mutex.h>
24#include <sys/mbuf.h>
25#include <sys/kernel.h>
26#include <sys/socket.h>
27#include <sys/systm.h>
28#include <sys/malloc.h>
29#include <sys/module.h>
30#include <sys/bus.h>
31#include <sys/endian.h>
32#include <sys/kdb.h>
33
34#include <machine/bus.h>
35#include <machine/resource.h>
36#include <sys/rman.h>
37
38#include <net/if.h>
39#include <net/if_arp.h>
40#include <net/ethernet.h>
41#include <net/if_dl.h>
42#include <net/if_media.h>
43#include <net/if_types.h>
44
45#ifdef INET
46#include <netinet/in.h>
47#include <netinet/in_systm.h>
48#include <netinet/in_var.h>
49#include <netinet/if_ether.h>
50#include <netinet/ip.h>
51#endif
52
53#include <net80211/ieee80211_var.h>
54#include <net80211/ieee80211_regdomain.h>
55#include <net80211/ieee80211_radiotap.h>
56
57#include <dev/usb/usb.h>
58#include <dev/usb/usbdi.h>
59#include "usbdevs.h"
60
61#include <dev/usb/wlan/if_urtwreg.h>
62#include <dev/usb/wlan/if_urtwvar.h>
63
64static SYSCTL_NODE(_hw_usb, OID_AUTO, urtw, CTLFLAG_RW, 0, "USB Realtek 8187L");
65#ifdef URTW_DEBUG
66int urtw_debug = 0;
67SYSCTL_INT(_hw_usb_urtw, OID_AUTO, debug, CTLFLAG_RW | CTLFLAG_TUN, &urtw_debug, 0,
68 "control debugging printfs");
69TUNABLE_INT("hw.usb.urtw.debug", &urtw_debug);
70enum {
71 URTW_DEBUG_XMIT = 0x00000001, /* basic xmit operation */
72 URTW_DEBUG_RECV = 0x00000002, /* basic recv operation */
73 URTW_DEBUG_RESET = 0x00000004, /* reset processing */
74 URTW_DEBUG_TX_PROC = 0x00000008, /* tx ISR proc */
75 URTW_DEBUG_RX_PROC = 0x00000010, /* rx ISR proc */
76 URTW_DEBUG_STATE = 0x00000020, /* 802.11 state transitions */
77 URTW_DEBUG_STAT = 0x00000040, /* statistic */
78 URTW_DEBUG_INIT = 0x00000080, /* initialization of dev */
79 URTW_DEBUG_TXSTATUS = 0x00000100, /* tx status */
80 URTW_DEBUG_ANY = 0xffffffff
81};
82#define DPRINTF(sc, m, fmt, ...) do { \
83 if (sc->sc_debug & (m)) \
84 printf(fmt, __VA_ARGS__); \
85} while (0)
86#else
87#define DPRINTF(sc, m, fmt, ...) do { \
88 (void) sc; \
89} while (0)
90#endif
91static int urtw_preamble_mode = URTW_PREAMBLE_MODE_LONG;
92SYSCTL_INT(_hw_usb_urtw, OID_AUTO, preamble_mode, CTLFLAG_RW | CTLFLAG_TUN,
93 &urtw_preamble_mode, 0, "set the preable mode (long or short)");
94TUNABLE_INT("hw.usb.urtw.preamble_mode", &urtw_preamble_mode);
95
96/* recognized device vendors/products */
97#define urtw_lookup(v, p) \
98 ((const struct urtw_type *)usb_lookup(urtw_devs, v, p))
99#define URTW_DEV_B(v,p) \
100 { USB_VPI(USB_VENDOR_##v, USB_PRODUCT_##v##_##p, URTW_REV_RTL8187B) }
101#define URTW_DEV_L(v,p) \
102 { USB_VPI(USB_VENDOR_##v, USB_PRODUCT_##v##_##p, URTW_REV_RTL8187L) }
103#define URTW_REV_RTL8187B 0
104#define URTW_REV_RTL8187L 1
105static const STRUCT_USB_HOST_ID urtw_devs[] = {
106 URTW_DEV_B(NETGEAR, WG111V3),
107 URTW_DEV_B(REALTEK, RTL8187B_0),
108 URTW_DEV_B(REALTEK, RTL8187B_1),
109 URTW_DEV_B(REALTEK, RTL8187B_2),
110 URTW_DEV_B(SITECOMEU, WL168V4),
111 URTW_DEV_L(ASUS, P5B_WIFI),
112 URTW_DEV_L(BELKIN, F5D7050E),
113 URTW_DEV_L(LINKSYS4, WUSB54GCV2),
114 URTW_DEV_L(NETGEAR, WG111V2),
115 URTW_DEV_L(REALTEK, RTL8187),
116 URTW_DEV_L(SITECOMEU, WL168V1),
117 URTW_DEV_L(SURECOM, EP9001G2A),
118 { USB_VPI(USB_VENDOR_OVISLINK, 0x8187, URTW_REV_RTL8187L) },
119 { USB_VPI(USB_VENDOR_DICKSMITH, 0x9401, URTW_REV_RTL8187L) },
120 { USB_VPI(USB_VENDOR_HP, 0xca02, URTW_REV_RTL8187L) },
121 { USB_VPI(USB_VENDOR_LOGITEC, 0x010c, URTW_REV_RTL8187L) },
122 { USB_VPI(USB_VENDOR_NETGEAR, 0x6100, URTW_REV_RTL8187L) },
123 { USB_VPI(USB_VENDOR_SPHAIRON, 0x0150, URTW_REV_RTL8187L) },
124 { USB_VPI(USB_VENDOR_QCOM, 0x6232, URTW_REV_RTL8187L) },
125#undef URTW_DEV_L
126#undef URTW_DEV_B
127};
128
129#define urtw_read8_m(sc, val, data) do { \
130 error = urtw_read8_c(sc, val, data); \
131 if (error != 0) \
132 goto fail; \
133} while (0)
134#define urtw_write8_m(sc, val, data) do { \
135 error = urtw_write8_c(sc, val, data); \
136 if (error != 0) \
137 goto fail; \
138} while (0)
139#define urtw_read16_m(sc, val, data) do { \
140 error = urtw_read16_c(sc, val, data); \
141 if (error != 0) \
142 goto fail; \
143} while (0)
144#define urtw_write16_m(sc, val, data) do { \
145 error = urtw_write16_c(sc, val, data); \
146 if (error != 0) \
147 goto fail; \
148} while (0)
149#define urtw_read32_m(sc, val, data) do { \
150 error = urtw_read32_c(sc, val, data); \
151 if (error != 0) \
152 goto fail; \
153} while (0)
154#define urtw_write32_m(sc, val, data) do { \
155 error = urtw_write32_c(sc, val, data); \
156 if (error != 0) \
157 goto fail; \
158} while (0)
159#define urtw_8187_write_phy_ofdm(sc, val, data) do { \
160 error = urtw_8187_write_phy_ofdm_c(sc, val, data); \
161 if (error != 0) \
162 goto fail; \
163} while (0)
164#define urtw_8187_write_phy_cck(sc, val, data) do { \
165 error = urtw_8187_write_phy_cck_c(sc, val, data); \
166 if (error != 0) \
167 goto fail; \
168} while (0)
169#define urtw_8225_write(sc, val, data) do { \
170 error = urtw_8225_write_c(sc, val, data); \
171 if (error != 0) \
172 goto fail; \
173} while (0)
174
175struct urtw_pair {
176 uint32_t reg;
177 uint32_t val;
178};
179
180static uint8_t urtw_8225_agc[] = {
181 0x9e, 0x9e, 0x9e, 0x9e, 0x9e, 0x9e, 0x9e, 0x9e, 0x9d, 0x9c, 0x9b,
182 0x9a, 0x99, 0x98, 0x97, 0x96, 0x95, 0x94, 0x93, 0x92, 0x91, 0x90,
183 0x8f, 0x8e, 0x8d, 0x8c, 0x8b, 0x8a, 0x89, 0x88, 0x87, 0x86, 0x85,
184 0x84, 0x83, 0x82, 0x81, 0x80, 0x3f, 0x3e, 0x3d, 0x3c, 0x3b, 0x3a,
185 0x39, 0x38, 0x37, 0x36, 0x35, 0x34, 0x33, 0x32, 0x31, 0x30, 0x2f,
186 0x2e, 0x2d, 0x2c, 0x2b, 0x2a, 0x29, 0x28, 0x27, 0x26, 0x25, 0x24,
187 0x23, 0x22, 0x21, 0x20, 0x1f, 0x1e, 0x1d, 0x1c, 0x1b, 0x1a, 0x19,
188 0x18, 0x17, 0x16, 0x15, 0x14, 0x13, 0x12, 0x11, 0x10, 0x0f, 0x0e,
189 0x0d, 0x0c, 0x0b, 0x0a, 0x09, 0x08, 0x07, 0x06, 0x05, 0x04, 0x03,
190 0x02, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
191 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
192 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01
193};
194
195static uint8_t urtw_8225z2_agc[] = {
196 0x5e, 0x5e, 0x5e, 0x5e, 0x5d, 0x5b, 0x59, 0x57, 0x55, 0x53, 0x51,
197 0x4f, 0x4d, 0x4b, 0x49, 0x47, 0x45, 0x43, 0x41, 0x3f, 0x3d, 0x3b,
198 0x39, 0x37, 0x35, 0x33, 0x31, 0x2f, 0x2d, 0x2b, 0x29, 0x27, 0x25,
199 0x23, 0x21, 0x1f, 0x1d, 0x1b, 0x19, 0x17, 0x15, 0x13, 0x11, 0x0f,
200 0x0d, 0x0b, 0x09, 0x07, 0x05, 0x03, 0x01, 0x01, 0x01, 0x01, 0x01,
201 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x19, 0x19,
202 0x19, 0x19, 0x19, 0x19, 0x19, 0x19, 0x19, 0x20, 0x21, 0x22, 0x23,
203 0x24, 0x25, 0x26, 0x26, 0x27, 0x27, 0x28, 0x28, 0x29, 0x2a, 0x2a,
204 0x2a, 0x2b, 0x2b, 0x2b, 0x2c, 0x2c, 0x2c, 0x2d, 0x2d, 0x2d, 0x2d,
205 0x2e, 0x2e, 0x2e, 0x2e, 0x2f, 0x2f, 0x2f, 0x30, 0x30, 0x31, 0x31,
206 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31,
207 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31
208};
209
210static uint32_t urtw_8225_channel[] = {
211 0x0000, /* dummy channel 0 */
212 0x085c, /* 1 */
213 0x08dc, /* 2 */
214 0x095c, /* 3 */
215 0x09dc, /* 4 */
216 0x0a5c, /* 5 */
217 0x0adc, /* 6 */
218 0x0b5c, /* 7 */
219 0x0bdc, /* 8 */
220 0x0c5c, /* 9 */
221 0x0cdc, /* 10 */
222 0x0d5c, /* 11 */
223 0x0ddc, /* 12 */
224 0x0e5c, /* 13 */
225 0x0f72, /* 14 */
226};
227
228static uint8_t urtw_8225_gain[] = {
229 0x23, 0x88, 0x7c, 0xa5, /* -82dbm */
230 0x23, 0x88, 0x7c, 0xb5, /* -82dbm */
231 0x23, 0x88, 0x7c, 0xc5, /* -82dbm */
232 0x33, 0x80, 0x79, 0xc5, /* -78dbm */
233 0x43, 0x78, 0x76, 0xc5, /* -74dbm */
234 0x53, 0x60, 0x73, 0xc5, /* -70dbm */
235 0x63, 0x58, 0x70, 0xc5, /* -66dbm */
236};
237
238static struct urtw_pair urtw_8225_rf_part1[] = {
239 { 0x00, 0x0067 }, { 0x01, 0x0fe0 }, { 0x02, 0x044d }, { 0x03, 0x0441 },
240 { 0x04, 0x0486 }, { 0x05, 0x0bc0 }, { 0x06, 0x0ae6 }, { 0x07, 0x082a },
241 { 0x08, 0x001f }, { 0x09, 0x0334 }, { 0x0a, 0x0fd4 }, { 0x0b, 0x0391 },
242 { 0x0c, 0x0050 }, { 0x0d, 0x06db }, { 0x0e, 0x0029 }, { 0x0f, 0x0914 },
243};
244
245static struct urtw_pair urtw_8225_rf_part2[] = {
246 { 0x00, 0x01 }, { 0x01, 0x02 }, { 0x02, 0x42 }, { 0x03, 0x00 },
247 { 0x04, 0x00 }, { 0x05, 0x00 }, { 0x06, 0x40 }, { 0x07, 0x00 },
248 { 0x08, 0x40 }, { 0x09, 0xfe }, { 0x0a, 0x09 }, { 0x0b, 0x80 },
249 { 0x0c, 0x01 }, { 0x0e, 0xd3 }, { 0x0f, 0x38 }, { 0x10, 0x84 },
250 { 0x11, 0x06 }, { 0x12, 0x20 }, { 0x13, 0x20 }, { 0x14, 0x00 },
251 { 0x15, 0x40 }, { 0x16, 0x00 }, { 0x17, 0x40 }, { 0x18, 0xef },
252 { 0x19, 0x19 }, { 0x1a, 0x20 }, { 0x1b, 0x76 }, { 0x1c, 0x04 },
253 { 0x1e, 0x95 }, { 0x1f, 0x75 }, { 0x20, 0x1f }, { 0x21, 0x27 },
254 { 0x22, 0x16 }, { 0x24, 0x46 }, { 0x25, 0x20 }, { 0x26, 0x90 },
255 { 0x27, 0x88 }
256};
257
258static struct urtw_pair urtw_8225_rf_part3[] = {
259 { 0x00, 0x98 }, { 0x03, 0x20 }, { 0x04, 0x7e }, { 0x05, 0x12 },
260 { 0x06, 0xfc }, { 0x07, 0x78 }, { 0x08, 0x2e }, { 0x10, 0x9b },
261 { 0x11, 0x88 }, { 0x12, 0x47 }, { 0x13, 0xd0 }, { 0x19, 0x00 },
262 { 0x1a, 0xa0 }, { 0x1b, 0x08 }, { 0x40, 0x86 }, { 0x41, 0x8d },
263 { 0x42, 0x15 }, { 0x43, 0x18 }, { 0x44, 0x1f }, { 0x45, 0x1e },
264 { 0x46, 0x1a }, { 0x47, 0x15 }, { 0x48, 0x10 }, { 0x49, 0x0a },
265 { 0x4a, 0x05 }, { 0x4b, 0x02 }, { 0x4c, 0x05 }
266};
267
268static uint16_t urtw_8225_rxgain[] = {
269 0x0400, 0x0401, 0x0402, 0x0403, 0x0404, 0x0405, 0x0408, 0x0409,
270 0x040a, 0x040b, 0x0502, 0x0503, 0x0504, 0x0505, 0x0540, 0x0541,
271 0x0542, 0x0543, 0x0544, 0x0545, 0x0580, 0x0581, 0x0582, 0x0583,
272 0x0584, 0x0585, 0x0588, 0x0589, 0x058a, 0x058b, 0x0643, 0x0644,
273 0x0645, 0x0680, 0x0681, 0x0682, 0x0683, 0x0684, 0x0685, 0x0688,
274 0x0689, 0x068a, 0x068b, 0x068c, 0x0742, 0x0743, 0x0744, 0x0745,
275 0x0780, 0x0781, 0x0782, 0x0783, 0x0784, 0x0785, 0x0788, 0x0789,
276 0x078a, 0x078b, 0x078c, 0x078d, 0x0790, 0x0791, 0x0792, 0x0793,
277 0x0794, 0x0795, 0x0798, 0x0799, 0x079a, 0x079b, 0x079c, 0x079d,
278 0x07a0, 0x07a1, 0x07a2, 0x07a3, 0x07a4, 0x07a5, 0x07a8, 0x07a9,
279 0x07aa, 0x07ab, 0x07ac, 0x07ad, 0x07b0, 0x07b1, 0x07b2, 0x07b3,
280 0x07b4, 0x07b5, 0x07b8, 0x07b9, 0x07ba, 0x07bb, 0x07bb
281};
282
283static uint8_t urtw_8225_threshold[] = {
284 0x8d, 0x8d, 0x8d, 0x8d, 0x9d, 0xad, 0xbd,
285};
286
287static uint8_t urtw_8225_tx_gain_cck_ofdm[] = {
288 0x02, 0x06, 0x0e, 0x1e, 0x3e, 0x7e
289};
290
291static uint8_t urtw_8225_txpwr_cck[] = {
292 0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02,
293 0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02,
294 0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02,
295 0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02,
296 0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03,
297 0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03
298};
299
300static uint8_t urtw_8225_txpwr_cck_ch14[] = {
301 0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00,
302 0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00,
303 0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00,
304 0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00,
305 0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00,
306 0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00
307};
308
309static uint8_t urtw_8225_txpwr_ofdm[]={
310 0x80, 0x90, 0xa2, 0xb5, 0xcb, 0xe4
311};
312
313static uint8_t urtw_8225v2_gain_bg[]={
314 0x23, 0x15, 0xa5, /* -82-1dbm */
315 0x23, 0x15, 0xb5, /* -82-2dbm */
316 0x23, 0x15, 0xc5, /* -82-3dbm */
317 0x33, 0x15, 0xc5, /* -78dbm */
318 0x43, 0x15, 0xc5, /* -74dbm */
319 0x53, 0x15, 0xc5, /* -70dbm */
320 0x63, 0x15, 0xc5, /* -66dbm */
321};
322
323static struct urtw_pair urtw_8225v2_rf_part1[] = {
324 { 0x00, 0x02bf }, { 0x01, 0x0ee0 }, { 0x02, 0x044d }, { 0x03, 0x0441 },
325 { 0x04, 0x08c3 }, { 0x05, 0x0c72 }, { 0x06, 0x00e6 }, { 0x07, 0x082a },
326 { 0x08, 0x003f }, { 0x09, 0x0335 }, { 0x0a, 0x09d4 }, { 0x0b, 0x07bb },
327 { 0x0c, 0x0850 }, { 0x0d, 0x0cdf }, { 0x0e, 0x002b }, { 0x0f, 0x0114 }
328};
329
330static struct urtw_pair urtw_8225v2b_rf_part0[] = {
331 { 0x00, 0x00b7 }, { 0x01, 0x0ee0 }, { 0x02, 0x044d }, { 0x03, 0x0441 },
332 { 0x04, 0x08c3 }, { 0x05, 0x0c72 }, { 0x06, 0x00e6 }, { 0x07, 0x082a },
333 { 0x08, 0x003f }, { 0x09, 0x0335 }, { 0x0a, 0x09d4 }, { 0x0b, 0x07bb },
334 { 0x0c, 0x0850 }, { 0x0d, 0x0cdf }, { 0x0e, 0x002b }, { 0x0f, 0x0114 }
335};
336
337static struct urtw_pair urtw_8225v2b_rf_part1[] = {
338 {0x0f0, 0x32}, {0x0f1, 0x32}, {0x0f2, 0x00},
339 {0x0f3, 0x00}, {0x0f4, 0x32}, {0x0f5, 0x43},
340 {0x0f6, 0x00}, {0x0f7, 0x00}, {0x0f8, 0x46},
341 {0x0f9, 0xa4}, {0x0fa, 0x00}, {0x0fb, 0x00},
342 {0x0fc, 0x96}, {0x0fd, 0xa4}, {0x0fe, 0x00},
343 {0x0ff, 0x00}, {0x158, 0x4b}, {0x159, 0x00},
344 {0x15a, 0x4b}, {0x15b, 0x00}, {0x160, 0x4b},
345 {0x161, 0x09}, {0x162, 0x4b}, {0x163, 0x09},
346 {0x1ce, 0x0f}, {0x1cf, 0x00}, {0x1e0, 0xff},
347 {0x1e1, 0x0f}, {0x1e2, 0x00}, {0x1f0, 0x4e},
348 {0x1f1, 0x01}, {0x1f2, 0x02}, {0x1f3, 0x03},
349 {0x1f4, 0x04}, {0x1f5, 0x05}, {0x1f6, 0x06},
350 {0x1f7, 0x07}, {0x1f8, 0x08}, {0x24e, 0x00},
351 {0x20c, 0x04}, {0x221, 0x61}, {0x222, 0x68},
352 {0x223, 0x6f}, {0x224, 0x76}, {0x225, 0x7d},
353 {0x226, 0x84}, {0x227, 0x8d}, {0x24d, 0x08},
354 {0x250, 0x05}, {0x251, 0xf5}, {0x252, 0x04},
355 {0x253, 0xa0}, {0x254, 0x1f}, {0x255, 0x23},
356 {0x256, 0x45}, {0x257, 0x67}, {0x258, 0x08},
357 {0x259, 0x08}, {0x25a, 0x08}, {0x25b, 0x08},
358 {0x260, 0x08}, {0x261, 0x08}, {0x262, 0x08},
359 {0x263, 0x08}, {0x264, 0xcf}, {0x272, 0x56},
360 {0x273, 0x9a}, {0x034, 0xf0}, {0x035, 0x0f},
361 {0x05b, 0x40}, {0x084, 0x88}, {0x085, 0x24},
362 {0x088, 0x54}, {0x08b, 0xb8}, {0x08c, 0x07},
363 {0x08d, 0x00}, {0x094, 0x1b}, {0x095, 0x12},
364 {0x096, 0x00}, {0x097, 0x06}, {0x09d, 0x1a},
365 {0x09f, 0x10}, {0x0b4, 0x22}, {0x0be, 0x80},
366 {0x0db, 0x00}, {0x0ee, 0x00}, {0x091, 0x03},
367 {0x24c, 0x00}, {0x39f, 0x00}, {0x08c, 0x01},
368 {0x08d, 0x10}, {0x08e, 0x08}, {0x08f, 0x00}
369};
370
371static struct urtw_pair urtw_8225v2_rf_part2[] = {
372 { 0x00, 0x01 }, { 0x01, 0x02 }, { 0x02, 0x42 }, { 0x03, 0x00 },
373 { 0x04, 0x00 }, { 0x05, 0x00 }, { 0x06, 0x40 }, { 0x07, 0x00 },
374 { 0x08, 0x40 }, { 0x09, 0xfe }, { 0x0a, 0x08 }, { 0x0b, 0x80 },
375 { 0x0c, 0x01 }, { 0x0d, 0x43 }, { 0x0e, 0xd3 }, { 0x0f, 0x38 },
376 { 0x10, 0x84 }, { 0x11, 0x07 }, { 0x12, 0x20 }, { 0x13, 0x20 },
377 { 0x14, 0x00 }, { 0x15, 0x40 }, { 0x16, 0x00 }, { 0x17, 0x40 },
378 { 0x18, 0xef }, { 0x19, 0x19 }, { 0x1a, 0x20 }, { 0x1b, 0x15 },
379 { 0x1c, 0x04 }, { 0x1d, 0xc5 }, { 0x1e, 0x95 }, { 0x1f, 0x75 },
380 { 0x20, 0x1f }, { 0x21, 0x17 }, { 0x22, 0x16 }, { 0x23, 0x80 },
381 { 0x24, 0x46 }, { 0x25, 0x00 }, { 0x26, 0x90 }, { 0x27, 0x88 }
382};
383
384static struct urtw_pair urtw_8225v2b_rf_part2[] = {
385 { 0x00, 0x10 }, { 0x01, 0x0d }, { 0x02, 0x01 }, { 0x03, 0x00 },
386 { 0x04, 0x14 }, { 0x05, 0xfb }, { 0x06, 0xfb }, { 0x07, 0x60 },
387 { 0x08, 0x00 }, { 0x09, 0x60 }, { 0x0a, 0x00 }, { 0x0b, 0x00 },
388 { 0x0c, 0x00 }, { 0x0d, 0x5c }, { 0x0e, 0x00 }, { 0x0f, 0x00 },
389 { 0x10, 0x40 }, { 0x11, 0x00 }, { 0x12, 0x40 }, { 0x13, 0x00 },
390 { 0x14, 0x00 }, { 0x15, 0x00 }, { 0x16, 0xa8 }, { 0x17, 0x26 },
391 { 0x18, 0x32 }, { 0x19, 0x33 }, { 0x1a, 0x07 }, { 0x1b, 0xa5 },
392 { 0x1c, 0x6f }, { 0x1d, 0x55 }, { 0x1e, 0xc8 }, { 0x1f, 0xb3 },
393 { 0x20, 0x0a }, { 0x21, 0xe1 }, { 0x22, 0x2C }, { 0x23, 0x8a },
394 { 0x24, 0x86 }, { 0x25, 0x83 }, { 0x26, 0x34 }, { 0x27, 0x0f },
395 { 0x28, 0x4f }, { 0x29, 0x24 }, { 0x2a, 0x6f }, { 0x2b, 0xc2 },
396 { 0x2c, 0x6b }, { 0x2d, 0x40 }, { 0x2e, 0x80 }, { 0x2f, 0x00 },
397 { 0x30, 0xc0 }, { 0x31, 0xc1 }, { 0x32, 0x58 }, { 0x33, 0xf1 },
398 { 0x34, 0x00 }, { 0x35, 0xe4 }, { 0x36, 0x90 }, { 0x37, 0x3e },
399 { 0x38, 0x6d }, { 0x39, 0x3c }, { 0x3a, 0xfb }, { 0x3b, 0x07 }
400};
401
402static struct urtw_pair urtw_8225v2_rf_part3[] = {
403 { 0x00, 0x98 }, { 0x03, 0x20 }, { 0x04, 0x7e }, { 0x05, 0x12 },
404 { 0x06, 0xfc }, { 0x07, 0x78 }, { 0x08, 0x2e }, { 0x09, 0x11 },
405 { 0x0a, 0x17 }, { 0x0b, 0x11 }, { 0x10, 0x9b }, { 0x11, 0x88 },
406 { 0x12, 0x47 }, { 0x13, 0xd0 }, { 0x19, 0x00 }, { 0x1a, 0xa0 },
407 { 0x1b, 0x08 }, { 0x1d, 0x00 }, { 0x40, 0x86 }, { 0x41, 0x9d },
408 { 0x42, 0x15 }, { 0x43, 0x18 }, { 0x44, 0x36 }, { 0x45, 0x35 },
409 { 0x46, 0x2e }, { 0x47, 0x25 }, { 0x48, 0x1c }, { 0x49, 0x12 },
410 { 0x4a, 0x09 }, { 0x4b, 0x04 }, { 0x4c, 0x05 }
411};
412
413static uint16_t urtw_8225v2_rxgain[] = {
414 0x0000, 0x0001, 0x0002, 0x0003, 0x0004, 0x0005, 0x0008, 0x0009,
415 0x000a, 0x000b, 0x0102, 0x0103, 0x0104, 0x0105, 0x0140, 0x0141,
416 0x0142, 0x0143, 0x0144, 0x0145, 0x0180, 0x0181, 0x0182, 0x0183,
417 0x0184, 0x0185, 0x0188, 0x0189, 0x018a, 0x018b, 0x0243, 0x0244,
418 0x0245, 0x0280, 0x0281, 0x0282, 0x0283, 0x0284, 0x0285, 0x0288,
419 0x0289, 0x028a, 0x028b, 0x028c, 0x0342, 0x0343, 0x0344, 0x0345,
420 0x0380, 0x0381, 0x0382, 0x0383, 0x0384, 0x0385, 0x0388, 0x0389,
421 0x038a, 0x038b, 0x038c, 0x038d, 0x0390, 0x0391, 0x0392, 0x0393,
422 0x0394, 0x0395, 0x0398, 0x0399, 0x039a, 0x039b, 0x039c, 0x039d,
423 0x03a0, 0x03a1, 0x03a2, 0x03a3, 0x03a4, 0x03a5, 0x03a8, 0x03a9,
424 0x03aa, 0x03ab, 0x03ac, 0x03ad, 0x03b0, 0x03b1, 0x03b2, 0x03b3,
425 0x03b4, 0x03b5, 0x03b8, 0x03b9, 0x03ba, 0x03bb, 0x03bb
426};
427
428static uint16_t urtw_8225v2b_rxgain[] = {
429 0x0400, 0x0401, 0x0402, 0x0403, 0x0404, 0x0405, 0x0408, 0x0409,
430 0x040a, 0x040b, 0x0502, 0x0503, 0x0504, 0x0505, 0x0540, 0x0541,
431 0x0542, 0x0543, 0x0544, 0x0545, 0x0580, 0x0581, 0x0582, 0x0583,
432 0x0584, 0x0585, 0x0588, 0x0589, 0x058a, 0x058b, 0x0643, 0x0644,
433 0x0645, 0x0680, 0x0681, 0x0682, 0x0683, 0x0684, 0x0685, 0x0688,
434 0x0689, 0x068a, 0x068b, 0x068c, 0x0742, 0x0743, 0x0744, 0x0745,
435 0x0780, 0x0781, 0x0782, 0x0783, 0x0784, 0x0785, 0x0788, 0x0789,
436 0x078a, 0x078b, 0x078c, 0x078d, 0x0790, 0x0791, 0x0792, 0x0793,
437 0x0794, 0x0795, 0x0798, 0x0799, 0x079a, 0x079b, 0x079c, 0x079d,
438 0x07a0, 0x07a1, 0x07a2, 0x07a3, 0x07a4, 0x07a5, 0x07a8, 0x07a9,
439 0x03aa, 0x03ab, 0x03ac, 0x03ad, 0x03b0, 0x03b1, 0x03b2, 0x03b3,
440 0x03b4, 0x03b5, 0x03b8, 0x03b9, 0x03ba, 0x03bb, 0x03bb
441};
442
443static uint8_t urtw_8225v2_tx_gain_cck_ofdm[] = {
444 0x00, 0x01, 0x02, 0x03, 0x04, 0x05,
445 0x06, 0x07, 0x08, 0x09, 0x0a, 0x0b,
446 0x0c, 0x0d, 0x0e, 0x0f, 0x10, 0x11,
447 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
448 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d,
449 0x1e, 0x1f, 0x20, 0x21, 0x22, 0x23,
450};
451
452static uint8_t urtw_8225v2_txpwr_cck[] = {
453 0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04
454};
455
456static uint8_t urtw_8225v2_txpwr_cck_ch14[] = {
457 0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00
458};
459
460static uint8_t urtw_8225v2b_txpwr_cck[] = {
461 0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04,
462 0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03,
463 0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03,
464 0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03
465};
466
467static uint8_t urtw_8225v2b_txpwr_cck_ch14[] = {
468 0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00,
469 0x30, 0x2f, 0x29, 0x15, 0x00, 0x00, 0x00, 0x00,
470 0x30, 0x2f, 0x29, 0x15, 0x00, 0x00, 0x00, 0x00,
471 0x30, 0x2f, 0x29, 0x15, 0x00, 0x00, 0x00, 0x00
472};
473
474static struct urtw_pair urtw_ratetable[] = {
475 { 2, 0 }, { 4, 1 }, { 11, 2 }, { 12, 4 }, { 18, 5 },
476 { 22, 3 }, { 24, 6 }, { 36, 7 }, { 48, 8 }, { 72, 9 },
477 { 96, 10 }, { 108, 11 }
478};
479
480static const uint8_t urtw_8187b_reg_table[][3] = {
481 { 0xf0, 0x32, 0 }, { 0xf1, 0x32, 0 }, { 0xf2, 0x00, 0 },
482 { 0xf3, 0x00, 0 }, { 0xf4, 0x32, 0 }, { 0xf5, 0x43, 0 },
483 { 0xf6, 0x00, 0 }, { 0xf7, 0x00, 0 }, { 0xf8, 0x46, 0 },
484 { 0xf9, 0xa4, 0 }, { 0xfa, 0x00, 0 }, { 0xfb, 0x00, 0 },
485 { 0xfc, 0x96, 0 }, { 0xfd, 0xa4, 0 }, { 0xfe, 0x00, 0 },
486 { 0xff, 0x00, 0 }, { 0x58, 0x4b, 1 }, { 0x59, 0x00, 1 },
487 { 0x5a, 0x4b, 1 }, { 0x5b, 0x00, 1 }, { 0x60, 0x4b, 1 },
488 { 0x61, 0x09, 1 }, { 0x62, 0x4b, 1 }, { 0x63, 0x09, 1 },
489 { 0xce, 0x0f, 1 }, { 0xcf, 0x00, 1 }, { 0xe0, 0xff, 1 },
490 { 0xe1, 0x0f, 1 }, { 0xe2, 0x00, 1 }, { 0xf0, 0x4e, 1 },
491 { 0xf1, 0x01, 1 }, { 0xf2, 0x02, 1 }, { 0xf3, 0x03, 1 },
492 { 0xf4, 0x04, 1 }, { 0xf5, 0x05, 1 }, { 0xf6, 0x06, 1 },
493 { 0xf7, 0x07, 1 }, { 0xf8, 0x08, 1 }, { 0x4e, 0x00, 2 },
494 { 0x0c, 0x04, 2 }, { 0x21, 0x61, 2 }, { 0x22, 0x68, 2 },
495 { 0x23, 0x6f, 2 }, { 0x24, 0x76, 2 }, { 0x25, 0x7d, 2 },
496 { 0x26, 0x84, 2 }, { 0x27, 0x8d, 2 }, { 0x4d, 0x08, 2 },
497 { 0x50, 0x05, 2 }, { 0x51, 0xf5, 2 }, { 0x52, 0x04, 2 },
498 { 0x53, 0xa0, 2 }, { 0x54, 0x1f, 2 }, { 0x55, 0x23, 2 },
499 { 0x56, 0x45, 2 }, { 0x57, 0x67, 2 }, { 0x58, 0x08, 2 },
500 { 0x59, 0x08, 2 }, { 0x5a, 0x08, 2 }, { 0x5b, 0x08, 2 },
501 { 0x60, 0x08, 2 }, { 0x61, 0x08, 2 }, { 0x62, 0x08, 2 },
502 { 0x63, 0x08, 2 }, { 0x64, 0xcf, 2 }, { 0x72, 0x56, 2 },
503 { 0x73, 0x9a, 2 }, { 0x34, 0xf0, 0 }, { 0x35, 0x0f, 0 },
504 { 0x5b, 0x40, 0 }, { 0x84, 0x88, 0 }, { 0x85, 0x24, 0 },
505 { 0x88, 0x54, 0 }, { 0x8b, 0xb8, 0 }, { 0x8c, 0x07, 0 },
506 { 0x8d, 0x00, 0 }, { 0x94, 0x1b, 0 }, { 0x95, 0x12, 0 },
507 { 0x96, 0x00, 0 }, { 0x97, 0x06, 0 }, { 0x9d, 0x1a, 0 },
508 { 0x9f, 0x10, 0 }, { 0xb4, 0x22, 0 }, { 0xbe, 0x80, 0 },
509 { 0xdb, 0x00, 0 }, { 0xee, 0x00, 0 }, { 0x91, 0x03, 0 },
510 { 0x4c, 0x00, 2 }, { 0x9f, 0x00, 3 }, { 0x8c, 0x01, 0 },
511 { 0x8d, 0x10, 0 }, { 0x8e, 0x08, 0 }, { 0x8f, 0x00, 0 }
512};
513
514static usb_callback_t urtw_bulk_rx_callback;
515static usb_callback_t urtw_bulk_tx_callback;
516static usb_callback_t urtw_bulk_tx_status_callback;
517
518static const struct usb_config urtw_8187b_usbconfig[URTW_8187B_N_XFERS] = {
519 [URTW_8187B_BULK_RX] = {
520 .type = UE_BULK,
521 .endpoint = 0x83,
522 .direction = UE_DIR_IN,
523 .bufsize = MCLBYTES,
524 .flags = {
525 .ext_buffer = 1,
526 .pipe_bof = 1,
527 .short_xfer_ok = 1
528 },
529 .callback = urtw_bulk_rx_callback
530 },
531 [URTW_8187B_BULK_TX_STATUS] = {
532 .type = UE_BULK,
533 .endpoint = 0x89,
534 .direction = UE_DIR_IN,
|
1518 if (error != 0)
1519 return (error);
1520
1521 STAILQ_INIT(&sc->sc_tx_active);
1522 STAILQ_INIT(&sc->sc_tx_inactive);
1523 STAILQ_INIT(&sc->sc_tx_pending);
1524
1525 for (i = 0; i < URTW_TX_DATA_LIST_COUNT; i++)
1526 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, &sc->sc_tx[i],
1527 next);
1528
1529 return (0);
1530}
1531
1532static int
1533urtw_raw_xmit(struct ieee80211_node *ni, struct mbuf *m,
1534 const struct ieee80211_bpf_params *params)
1535{
1536 struct ieee80211com *ic = ni->ni_ic;
1537 struct ifnet *ifp = ic->ic_ifp;
1538 struct urtw_data *bf;
1539 struct urtw_softc *sc = ifp->if_softc;
1540
1541 /* prevent management frames from being sent if we're not ready */
1542 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
1543 m_freem(m);
1544 ieee80211_free_node(ni);
1545 return ENETDOWN;
1546 }
1547 URTW_LOCK(sc);
1548 bf = urtw_getbuf(sc);
1549 if (bf == NULL) {
1550 ieee80211_free_node(ni);
1551 m_freem(m);
1552 URTW_UNLOCK(sc);
1553 return (ENOBUFS); /* XXX */
1554 }
1555
1556 ifp->if_opackets++;
1557 if (urtw_tx_start(sc, ni, m, bf, URTW_PRIORITY_LOW) != 0) {
1558 ieee80211_free_node(ni);
1559 ifp->if_oerrors++;
1560 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, bf, next);
1561 URTW_UNLOCK(sc);
1562 return (EIO);
1563 }
1564 URTW_UNLOCK(sc);
1565
1566 sc->sc_txtimer = 5;
1567 return (0);
1568}
1569
1570static void
1571urtw_scan_start(struct ieee80211com *ic)
1572{
1573
1574 /* XXX do nothing? */
1575}
1576
1577static void
1578urtw_scan_end(struct ieee80211com *ic)
1579{
1580
1581 /* XXX do nothing? */
1582}
1583
1584static void
1585urtw_set_channel(struct ieee80211com *ic)
1586{
1587 struct urtw_softc *sc = ic->ic_ifp->if_softc;
1588 struct ifnet *ifp = sc->sc_ifp;
1589 uint32_t data, orig;
1590 usb_error_t error;
1591
1592 /*
1593 * if the user set a channel explicitly using ifconfig(8) this function
1594 * can be called earlier than we're expected that in some cases the
1595 * initialization would be failed if setting a channel is called before
1596 * the init have done.
1597 */
1598 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING))
1599 return;
1600
1601 if (sc->sc_curchan != NULL && sc->sc_curchan == ic->ic_curchan)
1602 return;
1603
1604 URTW_LOCK(sc);
1605
1606 /*
1607 * during changing th channel we need to temporarily be disable
1608 * TX.
1609 */
1610 urtw_read32_m(sc, URTW_TX_CONF, &orig);
1611 data = orig & ~URTW_TX_LOOPBACK_MASK;
1612 urtw_write32_m(sc, URTW_TX_CONF, data | URTW_TX_LOOPBACK_MAC);
1613
1614 error = sc->sc_rf_set_chan(sc, ieee80211_chan2ieee(ic, ic->ic_curchan));
1615 if (error != 0)
1616 goto fail;
1617 usb_pause_mtx(&sc->sc_mtx, 10);
1618 urtw_write32_m(sc, URTW_TX_CONF, orig);
1619
1620 urtw_write16_m(sc, URTW_ATIM_WND, 2);
1621 urtw_write16_m(sc, URTW_ATIM_TR_ITV, 100);
1622 urtw_write16_m(sc, URTW_BEACON_INTERVAL, 100);
1623 urtw_write16_m(sc, URTW_BEACON_INTERVAL_TIME, 100);
1624
1625fail:
1626 URTW_UNLOCK(sc);
1627
1628 sc->sc_curchan = ic->ic_curchan;
1629
1630 if (error != 0)
1631 device_printf(sc->sc_dev, "could not change the channel\n");
1632}
1633
1634static void
1635urtw_update_mcast(struct ifnet *ifp)
1636{
1637
1638 /* XXX do nothing? */
1639}
1640
1641static int
1642urtw_tx_start(struct urtw_softc *sc, struct ieee80211_node *ni, struct mbuf *m0,
1643 struct urtw_data *data, int prior)
1644{
1645 struct ifnet *ifp = sc->sc_ifp;
1646 struct ieee80211_frame *wh = mtod(m0, struct ieee80211_frame *);
1647 struct ieee80211_key *k;
1648 const struct ieee80211_txparam *tp;
1649 struct ieee80211com *ic = ifp->if_l2com;
1650 struct ieee80211vap *vap = ni->ni_vap;
1651 struct usb_xfer *rtl8187b_pipes[URTW_8187B_TXPIPE_MAX] = {
1652 sc->sc_xfer[URTW_8187B_BULK_TX_BE],
1653 sc->sc_xfer[URTW_8187B_BULK_TX_BK],
1654 sc->sc_xfer[URTW_8187B_BULK_TX_VI],
1655 sc->sc_xfer[URTW_8187B_BULK_TX_VO]
1656 };
1657 struct usb_xfer *xfer;
1658 int dur = 0, rtsdur = 0, rtsenable = 0, ctsenable = 0, rate,
1659 pkttime = 0, txdur = 0, isshort = 0, xferlen;
1660 uint16_t acktime, rtstime, ctstime;
1661 uint32_t flags;
1662 usb_error_t error;
1663
1664 URTW_ASSERT_LOCKED(sc);
1665
1666 /*
1667 * Software crypto.
1668 */
1669 if (wh->i_fc[1] & IEEE80211_FC1_WEP) {
1670 k = ieee80211_crypto_encap(ni, m0);
1671 if (k == NULL) {
1672 device_printf(sc->sc_dev,
1673 "ieee80211_crypto_encap returns NULL.\n");
1674 /* XXX we don't expect the fragmented frames */
1675 m_freem(m0);
1676 return (ENOBUFS);
1677 }
1678
1679 /* in case packet header moved, reset pointer */
1680 wh = mtod(m0, struct ieee80211_frame *);
1681 }
1682
1683 if (ieee80211_radiotap_active_vap(vap)) {
1684 struct urtw_tx_radiotap_header *tap = &sc->sc_txtap;
1685
1686 /* XXX Are variables correct? */
1687 tap->wt_flags = 0;
1688 tap->wt_chan_freq = htole16(ic->ic_curchan->ic_freq);
1689 tap->wt_chan_flags = htole16(ic->ic_curchan->ic_flags);
1690
1691 ieee80211_radiotap_tx(vap, m0);
1692 }
1693
1694 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) == IEEE80211_FC0_TYPE_MGT ||
1695 (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) == IEEE80211_FC0_TYPE_CTL) {
1696 tp = &vap->iv_txparms[ieee80211_chan2mode(ic->ic_curchan)];
1697 rate = tp->mgmtrate;
1698 } else {
1699 tp = &vap->iv_txparms[ieee80211_chan2mode(ni->ni_chan)];
1700 /* for data frames */
1701 if (IEEE80211_IS_MULTICAST(wh->i_addr1))
1702 rate = tp->mcastrate;
1703 else if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE)
1704 rate = tp->ucastrate;
1705 else
1706 rate = urtw_rtl2rate(sc->sc_currate);
1707 }
1708
1709 sc->sc_stats.txrates[sc->sc_currate]++;
1710
1711 if (IEEE80211_IS_MULTICAST(wh->i_addr1))
1712 txdur = pkttime = urtw_compute_txtime(m0->m_pkthdr.len +
1713 IEEE80211_CRC_LEN, rate, 0, 0);
1714 else {
1715 acktime = urtw_compute_txtime(14, 2,0, 0);
1716 if ((m0->m_pkthdr.len + 4) > vap->iv_rtsthreshold) {
1717 rtsenable = 1;
1718 ctsenable = 0;
1719 rtstime = urtw_compute_txtime(URTW_ACKCTS_LEN, 2, 0, 0);
1720 ctstime = urtw_compute_txtime(14, 2, 0, 0);
1721 pkttime = urtw_compute_txtime(m0->m_pkthdr.len +
1722 IEEE80211_CRC_LEN, rate, 0, isshort);
1723 rtsdur = ctstime + pkttime + acktime +
1724 3 * URTW_ASIFS_TIME;
1725 txdur = rtstime + rtsdur;
1726 } else {
1727 rtsenable = ctsenable = rtsdur = 0;
1728 pkttime = urtw_compute_txtime(m0->m_pkthdr.len +
1729 IEEE80211_CRC_LEN, rate, 0, isshort);
1730 txdur = pkttime + URTW_ASIFS_TIME + acktime;
1731 }
1732
1733 if (wh->i_fc[1] & IEEE80211_FC1_MORE_FRAG)
1734 dur = urtw_compute_txtime(m0->m_pkthdr.len +
1735 IEEE80211_CRC_LEN, rate, 0, isshort) +
1736 3 * URTW_ASIFS_TIME +
1737 2 * acktime;
1738 else
1739 dur = URTW_ASIFS_TIME + acktime;
1740 }
1741 *(uint16_t *)wh->i_dur = htole16(dur);
1742
1743 xferlen = m0->m_pkthdr.len;
1744 xferlen += (sc->sc_flags & URTW_RTL8187B) ? (4 * 8) : (4 * 3);
1745 if ((0 == xferlen % 64) || (0 == xferlen % 512))
1746 xferlen += 1;
1747
1748 memset(data->buf, 0, URTW_TX_MAXSIZE);
1749 flags = m0->m_pkthdr.len & 0xfff;
1750 flags |= URTW_TX_FLAG_NO_ENC;
1751 if ((ic->ic_flags & IEEE80211_F_SHPREAMBLE) &&
1752 (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE) &&
1753 (sc->sc_preamble_mode == URTW_PREAMBLE_MODE_SHORT) &&
1754 (sc->sc_currate != 0))
1755 flags |= URTW_TX_FLAG_SPLCP;
1756 if (wh->i_fc[1] & IEEE80211_FC1_MORE_FRAG)
1757 flags |= URTW_TX_FLAG_MOREFRAG;
1758
1759 flags |= (sc->sc_currate & 0xf) << URTW_TX_FLAG_TXRATE_SHIFT;
1760
1761 if (sc->sc_flags & URTW_RTL8187B) {
1762 struct urtw_8187b_txhdr *tx;
1763
1764 tx = (struct urtw_8187b_txhdr *)data->buf;
1765 if (ctsenable)
1766 flags |= URTW_TX_FLAG_CTS;
1767 if (rtsenable) {
1768 flags |= URTW_TX_FLAG_RTS;
1769 flags |= (urtw_rate2rtl(11) & 0xf) <<
1770 URTW_TX_FLAG_RTSRATE_SHIFT;
1771 tx->rtsdur = rtsdur;
1772 }
1773 tx->flag = htole32(flags);
1774 tx->txdur = txdur;
1775 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) ==
1776 IEEE80211_FC0_TYPE_MGT &&
1777 (wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) ==
1778 IEEE80211_FC0_SUBTYPE_PROBE_RESP)
1779 tx->retry = 1;
1780 else
1781 tx->retry = URTW_TX_MAXRETRY;
1782 m_copydata(m0, 0, m0->m_pkthdr.len, (uint8_t *)(tx + 1));
1783 } else {
1784 struct urtw_8187l_txhdr *tx;
1785
1786 tx = (struct urtw_8187l_txhdr *)data->buf;
1787 if (rtsenable) {
1788 flags |= URTW_TX_FLAG_RTS;
1789 tx->rtsdur = rtsdur;
1790 }
1791 flags |= (urtw_rate2rtl(11) & 0xf) << URTW_TX_FLAG_RTSRATE_SHIFT;
1792 tx->flag = htole32(flags);
1793 tx->retry = 3; /* CW minimum */
1794 tx->retry = 7 << 4; /* CW maximum */
1795 tx->retry = URTW_TX_MAXRETRY << 8; /* retry limitation */
1796 m_copydata(m0, 0, m0->m_pkthdr.len, (uint8_t *)(tx + 1));
1797 }
1798
1799 data->buflen = xferlen;
1800 data->ni = ni;
1801 data->m = m0;
1802
1803 if (sc->sc_flags & URTW_RTL8187B) {
1804 switch (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) {
1805 case IEEE80211_FC0_TYPE_CTL:
1806 case IEEE80211_FC0_TYPE_MGT:
1807 xfer = sc->sc_xfer[URTW_8187B_BULK_TX_EP12];
1808 break;
1809 default:
1810 KASSERT(M_WME_GETAC(m0) < URTW_8187B_TXPIPE_MAX,
1811 ("unsupported WME pipe %d", M_WME_GETAC(m0)));
1812 xfer = rtl8187b_pipes[M_WME_GETAC(m0)];
1813 break;
1814 }
1815 } else
1816 xfer = (prior == URTW_PRIORITY_LOW) ?
1817 sc->sc_xfer[URTW_8187L_BULK_TX_LOW] :
1818 sc->sc_xfer[URTW_8187L_BULK_TX_NORMAL];
1819
1820 STAILQ_INSERT_TAIL(&sc->sc_tx_pending, data, next);
1821 usbd_transfer_start(xfer);
1822
1823 error = urtw_led_ctl(sc, URTW_LED_CTL_TX);
1824 if (error != 0)
1825 device_printf(sc->sc_dev, "could not control LED (%d)\n",
1826 error);
1827 return (0);
1828}
1829
1830static int
1831urtw_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg)
1832{
1833 struct ieee80211com *ic = vap->iv_ic;
1834 struct urtw_softc *sc = ic->ic_ifp->if_softc;
1835 struct urtw_vap *uvp = URTW_VAP(vap);
1836 struct ieee80211_node *ni;
1837 usb_error_t error = 0;
1838
1839 DPRINTF(sc, URTW_DEBUG_STATE, "%s: %s -> %s\n", __func__,
1840 ieee80211_state_name[vap->iv_state],
1841 ieee80211_state_name[nstate]);
1842
1843 sc->sc_state = nstate;
1844
1845 IEEE80211_UNLOCK(ic);
1846 URTW_LOCK(sc);
1847 usb_callout_stop(&sc->sc_led_ch);
1848 callout_stop(&sc->sc_watchdog_ch);
1849
1850 switch (nstate) {
1851 case IEEE80211_S_INIT:
1852 case IEEE80211_S_SCAN:
1853 case IEEE80211_S_AUTH:
1854 case IEEE80211_S_ASSOC:
1855 break;
1856 case IEEE80211_S_RUN:
1857 ni = ieee80211_ref_node(vap->iv_bss);
1858 /* setting bssid. */
1859 urtw_write32_m(sc, URTW_BSSID, ((uint32_t *)ni->ni_bssid)[0]);
1860 urtw_write16_m(sc, URTW_BSSID + 4,
1861 ((uint16_t *)ni->ni_bssid)[2]);
1862 urtw_update_msr(sc);
1863 /* XXX maybe the below would be incorrect. */
1864 urtw_write16_m(sc, URTW_ATIM_WND, 2);
1865 urtw_write16_m(sc, URTW_ATIM_TR_ITV, 100);
1866 urtw_write16_m(sc, URTW_BEACON_INTERVAL, 0x64);
1867 urtw_write16_m(sc, URTW_BEACON_INTERVAL_TIME, 100);
1868 error = urtw_led_ctl(sc, URTW_LED_CTL_LINK);
1869 if (error != 0)
1870 device_printf(sc->sc_dev,
1871 "could not control LED (%d)\n", error);
1872 ieee80211_free_node(ni);
1873 break;
1874 default:
1875 break;
1876 }
1877fail:
1878 URTW_UNLOCK(sc);
1879 IEEE80211_LOCK(ic);
1880 return (uvp->newstate(vap, nstate, arg));
1881}
1882
1883static void
1884urtw_watchdog(void *arg)
1885{
1886 struct urtw_softc *sc = arg;
1887 struct ifnet *ifp = sc->sc_ifp;
1888
1889 if (sc->sc_txtimer > 0) {
1890 if (--sc->sc_txtimer == 0) {
1891 device_printf(sc->sc_dev, "device timeout\n");
1892 ifp->if_oerrors++;
1893 return;
1894 }
1895 callout_reset(&sc->sc_watchdog_ch, hz, urtw_watchdog, sc);
1896 }
1897}
1898
1899static void
1900urtw_set_multi(void *arg)
1901{
1902 struct urtw_softc *sc = arg;
1903 struct ifnet *ifp = sc->sc_ifp;
1904
1905 if (!(ifp->if_flags & IFF_UP))
1906 return;
1907
1908 /*
1909 * XXX don't know how to set a device. Lack of docs. Just try to set
1910 * IFF_ALLMULTI flag here.
1911 */
1912 ifp->if_flags |= IFF_ALLMULTI;
1913}
1914
1915static usb_error_t
1916urtw_set_rate(struct urtw_softc *sc)
1917{
1918 int i, basic_rate, min_rr_rate, max_rr_rate;
1919 uint16_t data;
1920 usb_error_t error;
1921
1922 basic_rate = urtw_rate2rtl(48);
1923 min_rr_rate = urtw_rate2rtl(12);
1924 max_rr_rate = urtw_rate2rtl(48);
1925
1926 urtw_write8_m(sc, URTW_RESP_RATE,
1927 max_rr_rate << URTW_RESP_MAX_RATE_SHIFT |
1928 min_rr_rate << URTW_RESP_MIN_RATE_SHIFT);
1929
1930 urtw_read16_m(sc, URTW_BRSR, &data);
1931 data &= ~URTW_BRSR_MBR_8185;
1932
1933 for (i = 0; i <= basic_rate; i++)
1934 data |= (1 << i);
1935
1936 urtw_write16_m(sc, URTW_BRSR, data);
1937fail:
1938 return (error);
1939}
1940
1941static uint16_t
1942urtw_rate2rtl(uint32_t rate)
1943{
1944#define N(a) ((int)(sizeof(a) / sizeof((a)[0])))
1945 int i;
1946
1947 for (i = 0; i < N(urtw_ratetable); i++) {
1948 if (rate == urtw_ratetable[i].reg)
1949 return urtw_ratetable[i].val;
1950 }
1951
1952 return (3);
1953#undef N
1954}
1955
1956static uint16_t
1957urtw_rtl2rate(uint32_t rate)
1958{
1959#define N(a) ((int)(sizeof(a) / sizeof((a)[0])))
1960 int i;
1961
1962 for (i = 0; i < N(urtw_ratetable); i++) {
1963 if (rate == urtw_ratetable[i].val)
1964 return urtw_ratetable[i].reg;
1965 }
1966
1967 return (0);
1968#undef N
1969}
1970
1971static usb_error_t
1972urtw_update_msr(struct urtw_softc *sc)
1973{
1974 struct ifnet *ifp = sc->sc_ifp;
1975 struct ieee80211com *ic = ifp->if_l2com;
1976 uint8_t data;
1977 usb_error_t error;
1978
1979 urtw_read8_m(sc, URTW_MSR, &data);
1980 data &= ~URTW_MSR_LINK_MASK;
1981
1982 if (sc->sc_state == IEEE80211_S_RUN) {
1983 switch (ic->ic_opmode) {
1984 case IEEE80211_M_STA:
1985 case IEEE80211_M_MONITOR:
1986 data |= URTW_MSR_LINK_STA;
1987 if (sc->sc_flags & URTW_RTL8187B)
1988 data |= URTW_MSR_LINK_ENEDCA;
1989 break;
1990 case IEEE80211_M_IBSS:
1991 data |= URTW_MSR_LINK_ADHOC;
1992 break;
1993 case IEEE80211_M_HOSTAP:
1994 data |= URTW_MSR_LINK_HOSTAP;
1995 break;
1996 default:
1997 panic("unsupported operation mode 0x%x\n",
1998 ic->ic_opmode);
1999 /* never reach */
2000 }
2001 } else
2002 data |= URTW_MSR_LINK_NONE;
2003
2004 urtw_write8_m(sc, URTW_MSR, data);
2005fail:
2006 return (error);
2007}
2008
2009static usb_error_t
2010urtw_read8_c(struct urtw_softc *sc, int val, uint8_t *data)
2011{
2012 struct usb_device_request req;
2013 usb_error_t error;
2014
2015 URTW_ASSERT_LOCKED(sc);
2016
2017 req.bmRequestType = UT_READ_VENDOR_DEVICE;
2018 req.bRequest = URTW_8187_GETREGS_REQ;
2019 USETW(req.wValue, (val & 0xff) | 0xff00);
2020 USETW(req.wIndex, (val >> 8) & 0x3);
2021 USETW(req.wLength, sizeof(uint8_t));
2022
2023 error = urtw_do_request(sc, &req, data);
2024 return (error);
2025}
2026
2027static usb_error_t
2028urtw_read16_c(struct urtw_softc *sc, int val, uint16_t *data)
2029{
2030 struct usb_device_request req;
2031 usb_error_t error;
2032
2033 URTW_ASSERT_LOCKED(sc);
2034
2035 req.bmRequestType = UT_READ_VENDOR_DEVICE;
2036 req.bRequest = URTW_8187_GETREGS_REQ;
2037 USETW(req.wValue, (val & 0xff) | 0xff00);
2038 USETW(req.wIndex, (val >> 8) & 0x3);
2039 USETW(req.wLength, sizeof(uint16_t));
2040
2041 error = urtw_do_request(sc, &req, data);
2042 return (error);
2043}
2044
2045static usb_error_t
2046urtw_read32_c(struct urtw_softc *sc, int val, uint32_t *data)
2047{
2048 struct usb_device_request req;
2049 usb_error_t error;
2050
2051 URTW_ASSERT_LOCKED(sc);
2052
2053 req.bmRequestType = UT_READ_VENDOR_DEVICE;
2054 req.bRequest = URTW_8187_GETREGS_REQ;
2055 USETW(req.wValue, (val & 0xff) | 0xff00);
2056 USETW(req.wIndex, (val >> 8) & 0x3);
2057 USETW(req.wLength, sizeof(uint32_t));
2058
2059 error = urtw_do_request(sc, &req, data);
2060 return (error);
2061}
2062
2063static usb_error_t
2064urtw_write8_c(struct urtw_softc *sc, int val, uint8_t data)
2065{
2066 struct usb_device_request req;
2067
2068 URTW_ASSERT_LOCKED(sc);
2069
2070 req.bmRequestType = UT_WRITE_VENDOR_DEVICE;
2071 req.bRequest = URTW_8187_SETREGS_REQ;
2072 USETW(req.wValue, (val & 0xff) | 0xff00);
2073 USETW(req.wIndex, (val >> 8) & 0x3);
2074 USETW(req.wLength, sizeof(uint8_t));
2075
2076 return (urtw_do_request(sc, &req, &data));
2077}
2078
2079static usb_error_t
2080urtw_write16_c(struct urtw_softc *sc, int val, uint16_t data)
2081{
2082 struct usb_device_request req;
2083
2084 URTW_ASSERT_LOCKED(sc);
2085
2086 req.bmRequestType = UT_WRITE_VENDOR_DEVICE;
2087 req.bRequest = URTW_8187_SETREGS_REQ;
2088 USETW(req.wValue, (val & 0xff) | 0xff00);
2089 USETW(req.wIndex, (val >> 8) & 0x3);
2090 USETW(req.wLength, sizeof(uint16_t));
2091
2092 return (urtw_do_request(sc, &req, &data));
2093}
2094
2095static usb_error_t
2096urtw_write32_c(struct urtw_softc *sc, int val, uint32_t data)
2097{
2098 struct usb_device_request req;
2099
2100 URTW_ASSERT_LOCKED(sc);
2101
2102 req.bmRequestType = UT_WRITE_VENDOR_DEVICE;
2103 req.bRequest = URTW_8187_SETREGS_REQ;
2104 USETW(req.wValue, (val & 0xff) | 0xff00);
2105 USETW(req.wIndex, (val >> 8) & 0x3);
2106 USETW(req.wLength, sizeof(uint32_t));
2107
2108 return (urtw_do_request(sc, &req, &data));
2109}
2110
2111static usb_error_t
2112urtw_get_macaddr(struct urtw_softc *sc)
2113{
2114 uint32_t data;
2115 usb_error_t error;
2116
2117 error = urtw_eprom_read32(sc, URTW_EPROM_MACADDR, &data);
2118 if (error != 0)
2119 goto fail;
2120 sc->sc_bssid[0] = data & 0xff;
2121 sc->sc_bssid[1] = (data & 0xff00) >> 8;
2122 error = urtw_eprom_read32(sc, URTW_EPROM_MACADDR + 1, &data);
2123 if (error != 0)
2124 goto fail;
2125 sc->sc_bssid[2] = data & 0xff;
2126 sc->sc_bssid[3] = (data & 0xff00) >> 8;
2127 error = urtw_eprom_read32(sc, URTW_EPROM_MACADDR + 2, &data);
2128 if (error != 0)
2129 goto fail;
2130 sc->sc_bssid[4] = data & 0xff;
2131 sc->sc_bssid[5] = (data & 0xff00) >> 8;
2132fail:
2133 return (error);
2134}
2135
2136static usb_error_t
2137urtw_eprom_read32(struct urtw_softc *sc, uint32_t addr, uint32_t *data)
2138{
2139#define URTW_READCMD_LEN 3
2140 int addrlen, i;
2141 int16_t addrstr[8], data16, readcmd[] = { 1, 1, 0 };
2142 usb_error_t error;
2143
2144 /* NB: make sure the buffer is initialized */
2145 *data = 0;
2146
2147 /* enable EPROM programming */
2148 urtw_write8_m(sc, URTW_EPROM_CMD, URTW_EPROM_CMD_PROGRAM_MODE);
2149 DELAY(URTW_EPROM_DELAY);
2150
2151 error = urtw_eprom_cs(sc, URTW_EPROM_ENABLE);
2152 if (error != 0)
2153 goto fail;
2154 error = urtw_eprom_ck(sc);
2155 if (error != 0)
2156 goto fail;
2157 error = urtw_eprom_sendbits(sc, readcmd, URTW_READCMD_LEN);
2158 if (error != 0)
2159 goto fail;
2160 if (sc->sc_epromtype == URTW_EEPROM_93C56) {
2161 addrlen = 8;
2162 addrstr[0] = addr & (1 << 7);
2163 addrstr[1] = addr & (1 << 6);
2164 addrstr[2] = addr & (1 << 5);
2165 addrstr[3] = addr & (1 << 4);
2166 addrstr[4] = addr & (1 << 3);
2167 addrstr[5] = addr & (1 << 2);
2168 addrstr[6] = addr & (1 << 1);
2169 addrstr[7] = addr & (1 << 0);
2170 } else {
2171 addrlen=6;
2172 addrstr[0] = addr & (1 << 5);
2173 addrstr[1] = addr & (1 << 4);
2174 addrstr[2] = addr & (1 << 3);
2175 addrstr[3] = addr & (1 << 2);
2176 addrstr[4] = addr & (1 << 1);
2177 addrstr[5] = addr & (1 << 0);
2178 }
2179 error = urtw_eprom_sendbits(sc, addrstr, addrlen);
2180 if (error != 0)
2181 goto fail;
2182
2183 error = urtw_eprom_writebit(sc, 0);
2184 if (error != 0)
2185 goto fail;
2186
2187 for (i = 0; i < 16; i++) {
2188 error = urtw_eprom_ck(sc);
2189 if (error != 0)
2190 goto fail;
2191 error = urtw_eprom_readbit(sc, &data16);
2192 if (error != 0)
2193 goto fail;
2194
2195 (*data) |= (data16 << (15 - i));
2196 }
2197
2198 error = urtw_eprom_cs(sc, URTW_EPROM_DISABLE);
2199 if (error != 0)
2200 goto fail;
2201 error = urtw_eprom_ck(sc);
2202 if (error != 0)
2203 goto fail;
2204
2205 /* now disable EPROM programming */
2206 urtw_write8_m(sc, URTW_EPROM_CMD, URTW_EPROM_CMD_NORMAL_MODE);
2207fail:
2208 return (error);
2209#undef URTW_READCMD_LEN
2210}
2211
2212static usb_error_t
2213urtw_eprom_cs(struct urtw_softc *sc, int able)
2214{
2215 uint8_t data;
2216 usb_error_t error;
2217
2218 urtw_read8_m(sc, URTW_EPROM_CMD, &data);
2219 if (able == URTW_EPROM_ENABLE)
2220 urtw_write8_m(sc, URTW_EPROM_CMD, data | URTW_EPROM_CS);
2221 else
2222 urtw_write8_m(sc, URTW_EPROM_CMD, data & ~URTW_EPROM_CS);
2223 DELAY(URTW_EPROM_DELAY);
2224fail:
2225 return (error);
2226}
2227
2228static usb_error_t
2229urtw_eprom_ck(struct urtw_softc *sc)
2230{
2231 uint8_t data;
2232 usb_error_t error;
2233
2234 /* masking */
2235 urtw_read8_m(sc, URTW_EPROM_CMD, &data);
2236 urtw_write8_m(sc, URTW_EPROM_CMD, data | URTW_EPROM_CK);
2237 DELAY(URTW_EPROM_DELAY);
2238 /* unmasking */
2239 urtw_read8_m(sc, URTW_EPROM_CMD, &data);
2240 urtw_write8_m(sc, URTW_EPROM_CMD, data & ~URTW_EPROM_CK);
2241 DELAY(URTW_EPROM_DELAY);
2242fail:
2243 return (error);
2244}
2245
2246static usb_error_t
2247urtw_eprom_readbit(struct urtw_softc *sc, int16_t *data)
2248{
2249 uint8_t data8;
2250 usb_error_t error;
2251
2252 urtw_read8_m(sc, URTW_EPROM_CMD, &data8);
2253 *data = (data8 & URTW_EPROM_READBIT) ? 1 : 0;
2254 DELAY(URTW_EPROM_DELAY);
2255
2256fail:
2257 return (error);
2258}
2259
2260static usb_error_t
2261urtw_eprom_writebit(struct urtw_softc *sc, int16_t bit)
2262{
2263 uint8_t data;
2264 usb_error_t error;
2265
2266 urtw_read8_m(sc, URTW_EPROM_CMD, &data);
2267 if (bit != 0)
2268 urtw_write8_m(sc, URTW_EPROM_CMD, data | URTW_EPROM_WRITEBIT);
2269 else
2270 urtw_write8_m(sc, URTW_EPROM_CMD, data & ~URTW_EPROM_WRITEBIT);
2271 DELAY(URTW_EPROM_DELAY);
2272fail:
2273 return (error);
2274}
2275
2276static usb_error_t
2277urtw_eprom_sendbits(struct urtw_softc *sc, int16_t *buf, int buflen)
2278{
2279 int i = 0;
2280 usb_error_t error = 0;
2281
2282 for (i = 0; i < buflen; i++) {
2283 error = urtw_eprom_writebit(sc, buf[i]);
2284 if (error != 0)
2285 goto fail;
2286 error = urtw_eprom_ck(sc);
2287 if (error != 0)
2288 goto fail;
2289 }
2290fail:
2291 return (error);
2292}
2293
2294
2295static usb_error_t
2296urtw_get_txpwr(struct urtw_softc *sc)
2297{
2298 int i, j;
2299 uint32_t data;
2300 usb_error_t error;
2301
2302 error = urtw_eprom_read32(sc, URTW_EPROM_TXPW_BASE, &data);
2303 if (error != 0)
2304 goto fail;
2305 sc->sc_txpwr_cck_base = data & 0xf;
2306 sc->sc_txpwr_ofdm_base = (data >> 4) & 0xf;
2307
2308 for (i = 1, j = 0; i < 6; i += 2, j++) {
2309 error = urtw_eprom_read32(sc, URTW_EPROM_TXPW0 + j, &data);
2310 if (error != 0)
2311 goto fail;
2312 sc->sc_txpwr_cck[i] = data & 0xf;
2313 sc->sc_txpwr_cck[i + 1] = (data & 0xf00) >> 8;
2314 sc->sc_txpwr_ofdm[i] = (data & 0xf0) >> 4;
2315 sc->sc_txpwr_ofdm[i + 1] = (data & 0xf000) >> 12;
2316 }
2317 for (i = 1, j = 0; i < 4; i += 2, j++) {
2318 error = urtw_eprom_read32(sc, URTW_EPROM_TXPW1 + j, &data);
2319 if (error != 0)
2320 goto fail;
2321 sc->sc_txpwr_cck[i + 6] = data & 0xf;
2322 sc->sc_txpwr_cck[i + 6 + 1] = (data & 0xf00) >> 8;
2323 sc->sc_txpwr_ofdm[i + 6] = (data & 0xf0) >> 4;
2324 sc->sc_txpwr_ofdm[i + 6 + 1] = (data & 0xf000) >> 12;
2325 }
2326 if (sc->sc_flags & URTW_RTL8187B) {
2327 error = urtw_eprom_read32(sc, URTW_EPROM_TXPW2, &data);
2328 if (error != 0)
2329 goto fail;
2330 sc->sc_txpwr_cck[1 + 6 + 4] = data & 0xf;
2331 sc->sc_txpwr_ofdm[1 + 6 + 4] = (data & 0xf0) >> 4;
2332 error = urtw_eprom_read32(sc, 0x0a, &data);
2333 if (error != 0)
2334 goto fail;
2335 sc->sc_txpwr_cck[2 + 6 + 4] = data & 0xf;
2336 sc->sc_txpwr_ofdm[2 + 6 + 4] = (data & 0xf0) >> 4;
2337 error = urtw_eprom_read32(sc, 0x1c, &data);
2338 if (error != 0)
2339 goto fail;
2340 sc->sc_txpwr_cck[3 + 6 + 4] = data & 0xf;
2341 sc->sc_txpwr_cck[3 + 6 + 4 + 1] = (data & 0xf00) >> 8;
2342 sc->sc_txpwr_ofdm[3 + 6 + 4] = (data & 0xf0) >> 4;
2343 sc->sc_txpwr_ofdm[3 + 6 + 4 + 1] = (data & 0xf000) >> 12;
2344 } else {
2345 for (i = 1, j = 0; i < 4; i += 2, j++) {
2346 error = urtw_eprom_read32(sc, URTW_EPROM_TXPW2 + j,
2347 &data);
2348 if (error != 0)
2349 goto fail;
2350 sc->sc_txpwr_cck[i + 6 + 4] = data & 0xf;
2351 sc->sc_txpwr_cck[i + 6 + 4 + 1] = (data & 0xf00) >> 8;
2352 sc->sc_txpwr_ofdm[i + 6 + 4] = (data & 0xf0) >> 4;
2353 sc->sc_txpwr_ofdm[i + 6 + 4 + 1] = (data & 0xf000) >> 12;
2354 }
2355 }
2356fail:
2357 return (error);
2358}
2359
2360
2361static usb_error_t
2362urtw_get_rfchip(struct urtw_softc *sc)
2363{
2364 int ret;
2365 uint8_t data8;
2366 uint32_t data;
2367 usb_error_t error;
2368
2369 if (sc->sc_flags & URTW_RTL8187B) {
2370 urtw_read8_m(sc, 0xe1, &data8);
2371 switch (data8) {
2372 case 0:
2373 sc->sc_flags |= URTW_RTL8187B_REV_B;
2374 break;
2375 case 1:
2376 sc->sc_flags |= URTW_RTL8187B_REV_D;
2377 break;
2378 case 2:
2379 sc->sc_flags |= URTW_RTL8187B_REV_E;
2380 break;
2381 default:
2382 device_printf(sc->sc_dev, "unknown type: %#x\n", data8);
2383 sc->sc_flags |= URTW_RTL8187B_REV_B;
2384 break;
2385 }
2386 } else {
2387 urtw_read32_m(sc, URTW_TX_CONF, &data);
2388 switch (data & URTW_TX_HWMASK) {
2389 case URTW_TX_R8187vD_B:
2390 sc->sc_flags |= URTW_RTL8187B;
2391 break;
2392 case URTW_TX_R8187vD:
2393 break;
2394 default:
2395 device_printf(sc->sc_dev, "unknown RTL8187L type: %#x\n",
2396 data & URTW_TX_HWMASK);
2397 break;
2398 }
2399 }
2400
2401 error = urtw_eprom_read32(sc, URTW_EPROM_RFCHIPID, &data);
2402 if (error != 0)
2403 goto fail;
2404 switch (data & 0xff) {
2405 case URTW_EPROM_RFCHIPID_RTL8225U:
2406 error = urtw_8225_isv2(sc, &ret);
2407 if (error != 0)
2408 goto fail;
2409 if (ret == 0) {
2410 sc->sc_rf_init = urtw_8225_rf_init;
2411 sc->sc_rf_set_sens = urtw_8225_rf_set_sens;
2412 sc->sc_rf_set_chan = urtw_8225_rf_set_chan;
2413 sc->sc_rf_stop = urtw_8225_rf_stop;
2414 } else {
2415 sc->sc_rf_init = urtw_8225v2_rf_init;
2416 sc->sc_rf_set_chan = urtw_8225v2_rf_set_chan;
2417 sc->sc_rf_stop = urtw_8225_rf_stop;
2418 }
2419 sc->sc_max_sens = URTW_8225_RF_MAX_SENS;
2420 sc->sc_sens = URTW_8225_RF_DEF_SENS;
2421 break;
2422 case URTW_EPROM_RFCHIPID_RTL8225Z2:
2423 sc->sc_rf_init = urtw_8225v2b_rf_init;
2424 sc->sc_rf_set_chan = urtw_8225v2b_rf_set_chan;
2425 sc->sc_max_sens = URTW_8225_RF_MAX_SENS;
2426 sc->sc_sens = URTW_8225_RF_DEF_SENS;
2427 sc->sc_rf_stop = urtw_8225_rf_stop;
2428 break;
2429 default:
2430 panic("unsupported RF chip %d\n", data & 0xff);
2431 /* never reach */
2432 }
2433
2434 device_printf(sc->sc_dev, "%s rf %s hwrev %s\n",
2435 (sc->sc_flags & URTW_RTL8187B) ? "rtl8187b" : "rtl8187l",
2436 ((data & 0xff) == URTW_EPROM_RFCHIPID_RTL8225U) ? "rtl8225u" :
2437 "rtl8225z2",
2438 (sc->sc_flags & URTW_RTL8187B) ? ((data8 == 0) ? "b" :
2439 (data8 == 1) ? "d" : "e") : "none");
2440
2441fail:
2442 return (error);
2443}
2444
2445
2446static usb_error_t
2447urtw_led_init(struct urtw_softc *sc)
2448{
2449 uint32_t rev;
2450 usb_error_t error;
2451
2452 urtw_read8_m(sc, URTW_PSR, &sc->sc_psr);
2453 error = urtw_eprom_read32(sc, URTW_EPROM_SWREV, &rev);
2454 if (error != 0)
2455 goto fail;
2456
2457 switch (rev & URTW_EPROM_CID_MASK) {
2458 case URTW_EPROM_CID_ALPHA0:
2459 sc->sc_strategy = URTW_SW_LED_MODE1;
2460 break;
2461 case URTW_EPROM_CID_SERCOMM_PS:
2462 sc->sc_strategy = URTW_SW_LED_MODE3;
2463 break;
2464 case URTW_EPROM_CID_HW_LED:
2465 sc->sc_strategy = URTW_HW_LED;
2466 break;
2467 case URTW_EPROM_CID_RSVD0:
2468 case URTW_EPROM_CID_RSVD1:
2469 default:
2470 sc->sc_strategy = URTW_SW_LED_MODE0;
2471 break;
2472 }
2473
2474 sc->sc_gpio_ledpin = URTW_LED_PIN_GPIO0;
2475
2476fail:
2477 return (error);
2478}
2479
2480
2481static usb_error_t
2482urtw_8225_rf_init(struct urtw_softc *sc)
2483{
2484#define N(a) ((int)(sizeof(a) / sizeof((a)[0])))
2485 int i;
2486 uint16_t data;
2487 usb_error_t error;
2488
2489 error = urtw_8180_set_anaparam(sc, URTW_8225_ANAPARAM_ON);
2490 if (error)
2491 goto fail;
2492
2493 error = urtw_8225_usb_init(sc);
2494 if (error)
2495 goto fail;
2496
2497 urtw_write32_m(sc, URTW_RF_TIMING, 0x000a8008);
2498 urtw_read16_m(sc, URTW_BRSR, &data); /* XXX ??? */
2499 urtw_write16_m(sc, URTW_BRSR, 0xffff);
2500 urtw_write32_m(sc, URTW_RF_PARA, 0x100044);
2501
2502 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG);
2503 if (error)
2504 goto fail;
2505 urtw_write8_m(sc, URTW_CONFIG3, 0x44);
2506 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL);
2507 if (error)
2508 goto fail;
2509
2510 error = urtw_8185_rf_pins_enable(sc);
2511 if (error)
2512 goto fail;
2513 usb_pause_mtx(&sc->sc_mtx, 1000);
2514
2515 for (i = 0; i < N(urtw_8225_rf_part1); i++) {
2516 urtw_8225_write(sc, urtw_8225_rf_part1[i].reg,
2517 urtw_8225_rf_part1[i].val);
2518 usb_pause_mtx(&sc->sc_mtx, 1);
2519 }
2520 usb_pause_mtx(&sc->sc_mtx, 100);
2521 urtw_8225_write(sc,
2522 URTW_8225_ADDR_2_MAGIC, URTW_8225_ADDR_2_DATA_MAGIC1);
2523 usb_pause_mtx(&sc->sc_mtx, 200);
2524 urtw_8225_write(sc,
2525 URTW_8225_ADDR_2_MAGIC, URTW_8225_ADDR_2_DATA_MAGIC2);
2526 usb_pause_mtx(&sc->sc_mtx, 200);
2527 urtw_8225_write(sc,
2528 URTW_8225_ADDR_0_MAGIC, URTW_8225_ADDR_0_DATA_MAGIC3);
2529
2530 for (i = 0; i < 95; i++) {
2531 urtw_8225_write(sc, URTW_8225_ADDR_1_MAGIC, (uint8_t)(i + 1));
2532 urtw_8225_write(sc, URTW_8225_ADDR_2_MAGIC, urtw_8225_rxgain[i]);
2533 }
2534
2535 urtw_8225_write(sc,
2536 URTW_8225_ADDR_0_MAGIC, URTW_8225_ADDR_0_DATA_MAGIC4);
2537 urtw_8225_write(sc,
2538 URTW_8225_ADDR_0_MAGIC, URTW_8225_ADDR_0_DATA_MAGIC5);
2539
2540 for (i = 0; i < 128; i++) {
2541 urtw_8187_write_phy_ofdm(sc, 0xb, urtw_8225_agc[i]);
2542 usb_pause_mtx(&sc->sc_mtx, 1);
2543 urtw_8187_write_phy_ofdm(sc, 0xa, (uint8_t)i + 0x80);
2544 usb_pause_mtx(&sc->sc_mtx, 1);
2545 }
2546
2547 for (i = 0; i < N(urtw_8225_rf_part2); i++) {
2548 urtw_8187_write_phy_ofdm(sc, urtw_8225_rf_part2[i].reg,
2549 urtw_8225_rf_part2[i].val);
2550 usb_pause_mtx(&sc->sc_mtx, 1);
2551 }
2552
2553 error = urtw_8225_setgain(sc, 4);
2554 if (error)
2555 goto fail;
2556
2557 for (i = 0; i < N(urtw_8225_rf_part3); i++) {
2558 urtw_8187_write_phy_cck(sc, urtw_8225_rf_part3[i].reg,
2559 urtw_8225_rf_part3[i].val);
2560 usb_pause_mtx(&sc->sc_mtx, 1);
2561 }
2562
2563 urtw_write8_m(sc, URTW_TESTR, 0x0d);
2564
2565 error = urtw_8225_set_txpwrlvl(sc, 1);
2566 if (error)
2567 goto fail;
2568
2569 urtw_8187_write_phy_cck(sc, 0x10, 0x9b);
2570 usb_pause_mtx(&sc->sc_mtx, 1);
2571 urtw_8187_write_phy_ofdm(sc, 0x26, 0x90);
2572 usb_pause_mtx(&sc->sc_mtx, 1);
2573
2574 /* TX ant A, 0x0 for B */
2575 error = urtw_8185_tx_antenna(sc, 0x3);
2576 if (error)
2577 goto fail;
2578 urtw_write32_m(sc, URTW_HSSI_PARA, 0x3dc00002);
2579
2580 error = urtw_8225_rf_set_chan(sc, 1);
2581fail:
2582 return (error);
2583#undef N
2584}
2585
2586static usb_error_t
2587urtw_8185_rf_pins_enable(struct urtw_softc *sc)
2588{
2589 usb_error_t error = 0;
2590
2591 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, 0x1ff7);
2592fail:
2593 return (error);
2594}
2595
2596static usb_error_t
2597urtw_8185_tx_antenna(struct urtw_softc *sc, uint8_t ant)
2598{
2599 usb_error_t error;
2600
2601 urtw_write8_m(sc, URTW_TX_ANTENNA, ant);
2602 usb_pause_mtx(&sc->sc_mtx, 1);
2603fail:
2604 return (error);
2605}
2606
2607static usb_error_t
2608urtw_8187_write_phy_ofdm_c(struct urtw_softc *sc, uint8_t addr, uint32_t data)
2609{
2610
2611 data = data & 0xff;
2612 return urtw_8187_write_phy(sc, addr, data);
2613}
2614
2615static usb_error_t
2616urtw_8187_write_phy_cck_c(struct urtw_softc *sc, uint8_t addr, uint32_t data)
2617{
2618
2619 data = data & 0xff;
2620 return urtw_8187_write_phy(sc, addr, data | 0x10000);
2621}
2622
2623static usb_error_t
2624urtw_8187_write_phy(struct urtw_softc *sc, uint8_t addr, uint32_t data)
2625{
2626 uint32_t phyw;
2627 usb_error_t error;
2628
2629 phyw = ((data << 8) | (addr | 0x80));
2630 urtw_write8_m(sc, URTW_PHY_MAGIC4, ((phyw & 0xff000000) >> 24));
2631 urtw_write8_m(sc, URTW_PHY_MAGIC3, ((phyw & 0x00ff0000) >> 16));
2632 urtw_write8_m(sc, URTW_PHY_MAGIC2, ((phyw & 0x0000ff00) >> 8));
2633 urtw_write8_m(sc, URTW_PHY_MAGIC1, ((phyw & 0x000000ff)));
2634 usb_pause_mtx(&sc->sc_mtx, 1);
2635fail:
2636 return (error);
2637}
2638
2639static usb_error_t
2640urtw_8225_setgain(struct urtw_softc *sc, int16_t gain)
2641{
2642 usb_error_t error;
2643
2644 urtw_8187_write_phy_ofdm(sc, 0x0d, urtw_8225_gain[gain * 4]);
2645 urtw_8187_write_phy_ofdm(sc, 0x1b, urtw_8225_gain[gain * 4 + 2]);
2646 urtw_8187_write_phy_ofdm(sc, 0x1d, urtw_8225_gain[gain * 4 + 3]);
2647 urtw_8187_write_phy_ofdm(sc, 0x23, urtw_8225_gain[gain * 4 + 1]);
2648fail:
2649 return (error);
2650}
2651
2652static usb_error_t
2653urtw_8225_usb_init(struct urtw_softc *sc)
2654{
2655 uint8_t data;
2656 usb_error_t error;
2657
2658 urtw_write8_m(sc, URTW_RF_PINS_SELECT + 1, 0);
2659 urtw_write8_m(sc, URTW_GPIO, 0);
2660 error = urtw_read8e(sc, 0x53, &data);
2661 if (error)
2662 goto fail;
2663 error = urtw_write8e(sc, 0x53, data | (1 << 7));
2664 if (error)
2665 goto fail;
2666 urtw_write8_m(sc, URTW_RF_PINS_SELECT + 1, 4);
2667 urtw_write8_m(sc, URTW_GPIO, 0x20);
2668 urtw_write8_m(sc, URTW_GP_ENABLE, 0);
2669
2670 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, 0x80);
2671 urtw_write16_m(sc, URTW_RF_PINS_SELECT, 0x80);
2672 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, 0x80);
2673
2674 usb_pause_mtx(&sc->sc_mtx, 500);
2675fail:
2676 return (error);
2677}
2678
2679static usb_error_t
2680urtw_8225_write_c(struct urtw_softc *sc, uint8_t addr, uint16_t data)
2681{
2682 uint16_t d80, d82, d84;
2683 usb_error_t error;
2684
2685 urtw_read16_m(sc, URTW_RF_PINS_OUTPUT, &d80);
2686 d80 &= URTW_RF_PINS_MAGIC1;
2687 urtw_read16_m(sc, URTW_RF_PINS_ENABLE, &d82);
2688 urtw_read16_m(sc, URTW_RF_PINS_SELECT, &d84);
2689 d84 &= URTW_RF_PINS_MAGIC2;
2690 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, d82 | URTW_RF_PINS_MAGIC3);
2691 urtw_write16_m(sc, URTW_RF_PINS_SELECT, d84 | URTW_RF_PINS_MAGIC3);
2692 DELAY(10);
2693
2694 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, d80 | URTW_BB_HOST_BANG_EN);
2695 DELAY(2);
2696 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, d80);
2697 DELAY(10);
2698
2699 error = urtw_8225_write_s16(sc, addr, 0x8225, &data);
2700 if (error != 0)
2701 goto fail;
2702
2703 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, d80 | URTW_BB_HOST_BANG_EN);
2704 DELAY(10);
2705 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, d80 | URTW_BB_HOST_BANG_EN);
2706 urtw_write16_m(sc, URTW_RF_PINS_SELECT, d84);
2707 usb_pause_mtx(&sc->sc_mtx, 2);
2708fail:
2709 return (error);
2710}
2711
| 1515 if (error != 0)
1516 return (error);
1517
1518 STAILQ_INIT(&sc->sc_tx_active);
1519 STAILQ_INIT(&sc->sc_tx_inactive);
1520 STAILQ_INIT(&sc->sc_tx_pending);
1521
1522 for (i = 0; i < URTW_TX_DATA_LIST_COUNT; i++)
1523 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, &sc->sc_tx[i],
1524 next);
1525
1526 return (0);
1527}
1528
1529static int
1530urtw_raw_xmit(struct ieee80211_node *ni, struct mbuf *m,
1531 const struct ieee80211_bpf_params *params)
1532{
1533 struct ieee80211com *ic = ni->ni_ic;
1534 struct ifnet *ifp = ic->ic_ifp;
1535 struct urtw_data *bf;
1536 struct urtw_softc *sc = ifp->if_softc;
1537
1538 /* prevent management frames from being sent if we're not ready */
1539 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
1540 m_freem(m);
1541 ieee80211_free_node(ni);
1542 return ENETDOWN;
1543 }
1544 URTW_LOCK(sc);
1545 bf = urtw_getbuf(sc);
1546 if (bf == NULL) {
1547 ieee80211_free_node(ni);
1548 m_freem(m);
1549 URTW_UNLOCK(sc);
1550 return (ENOBUFS); /* XXX */
1551 }
1552
1553 ifp->if_opackets++;
1554 if (urtw_tx_start(sc, ni, m, bf, URTW_PRIORITY_LOW) != 0) {
1555 ieee80211_free_node(ni);
1556 ifp->if_oerrors++;
1557 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, bf, next);
1558 URTW_UNLOCK(sc);
1559 return (EIO);
1560 }
1561 URTW_UNLOCK(sc);
1562
1563 sc->sc_txtimer = 5;
1564 return (0);
1565}
1566
1567static void
1568urtw_scan_start(struct ieee80211com *ic)
1569{
1570
1571 /* XXX do nothing? */
1572}
1573
1574static void
1575urtw_scan_end(struct ieee80211com *ic)
1576{
1577
1578 /* XXX do nothing? */
1579}
1580
1581static void
1582urtw_set_channel(struct ieee80211com *ic)
1583{
1584 struct urtw_softc *sc = ic->ic_ifp->if_softc;
1585 struct ifnet *ifp = sc->sc_ifp;
1586 uint32_t data, orig;
1587 usb_error_t error;
1588
1589 /*
1590 * if the user set a channel explicitly using ifconfig(8) this function
1591 * can be called earlier than we're expected that in some cases the
1592 * initialization would be failed if setting a channel is called before
1593 * the init have done.
1594 */
1595 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING))
1596 return;
1597
1598 if (sc->sc_curchan != NULL && sc->sc_curchan == ic->ic_curchan)
1599 return;
1600
1601 URTW_LOCK(sc);
1602
1603 /*
1604 * during changing th channel we need to temporarily be disable
1605 * TX.
1606 */
1607 urtw_read32_m(sc, URTW_TX_CONF, &orig);
1608 data = orig & ~URTW_TX_LOOPBACK_MASK;
1609 urtw_write32_m(sc, URTW_TX_CONF, data | URTW_TX_LOOPBACK_MAC);
1610
1611 error = sc->sc_rf_set_chan(sc, ieee80211_chan2ieee(ic, ic->ic_curchan));
1612 if (error != 0)
1613 goto fail;
1614 usb_pause_mtx(&sc->sc_mtx, 10);
1615 urtw_write32_m(sc, URTW_TX_CONF, orig);
1616
1617 urtw_write16_m(sc, URTW_ATIM_WND, 2);
1618 urtw_write16_m(sc, URTW_ATIM_TR_ITV, 100);
1619 urtw_write16_m(sc, URTW_BEACON_INTERVAL, 100);
1620 urtw_write16_m(sc, URTW_BEACON_INTERVAL_TIME, 100);
1621
1622fail:
1623 URTW_UNLOCK(sc);
1624
1625 sc->sc_curchan = ic->ic_curchan;
1626
1627 if (error != 0)
1628 device_printf(sc->sc_dev, "could not change the channel\n");
1629}
1630
1631static void
1632urtw_update_mcast(struct ifnet *ifp)
1633{
1634
1635 /* XXX do nothing? */
1636}
1637
1638static int
1639urtw_tx_start(struct urtw_softc *sc, struct ieee80211_node *ni, struct mbuf *m0,
1640 struct urtw_data *data, int prior)
1641{
1642 struct ifnet *ifp = sc->sc_ifp;
1643 struct ieee80211_frame *wh = mtod(m0, struct ieee80211_frame *);
1644 struct ieee80211_key *k;
1645 const struct ieee80211_txparam *tp;
1646 struct ieee80211com *ic = ifp->if_l2com;
1647 struct ieee80211vap *vap = ni->ni_vap;
1648 struct usb_xfer *rtl8187b_pipes[URTW_8187B_TXPIPE_MAX] = {
1649 sc->sc_xfer[URTW_8187B_BULK_TX_BE],
1650 sc->sc_xfer[URTW_8187B_BULK_TX_BK],
1651 sc->sc_xfer[URTW_8187B_BULK_TX_VI],
1652 sc->sc_xfer[URTW_8187B_BULK_TX_VO]
1653 };
1654 struct usb_xfer *xfer;
1655 int dur = 0, rtsdur = 0, rtsenable = 0, ctsenable = 0, rate,
1656 pkttime = 0, txdur = 0, isshort = 0, xferlen;
1657 uint16_t acktime, rtstime, ctstime;
1658 uint32_t flags;
1659 usb_error_t error;
1660
1661 URTW_ASSERT_LOCKED(sc);
1662
1663 /*
1664 * Software crypto.
1665 */
1666 if (wh->i_fc[1] & IEEE80211_FC1_WEP) {
1667 k = ieee80211_crypto_encap(ni, m0);
1668 if (k == NULL) {
1669 device_printf(sc->sc_dev,
1670 "ieee80211_crypto_encap returns NULL.\n");
1671 /* XXX we don't expect the fragmented frames */
1672 m_freem(m0);
1673 return (ENOBUFS);
1674 }
1675
1676 /* in case packet header moved, reset pointer */
1677 wh = mtod(m0, struct ieee80211_frame *);
1678 }
1679
1680 if (ieee80211_radiotap_active_vap(vap)) {
1681 struct urtw_tx_radiotap_header *tap = &sc->sc_txtap;
1682
1683 /* XXX Are variables correct? */
1684 tap->wt_flags = 0;
1685 tap->wt_chan_freq = htole16(ic->ic_curchan->ic_freq);
1686 tap->wt_chan_flags = htole16(ic->ic_curchan->ic_flags);
1687
1688 ieee80211_radiotap_tx(vap, m0);
1689 }
1690
1691 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) == IEEE80211_FC0_TYPE_MGT ||
1692 (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) == IEEE80211_FC0_TYPE_CTL) {
1693 tp = &vap->iv_txparms[ieee80211_chan2mode(ic->ic_curchan)];
1694 rate = tp->mgmtrate;
1695 } else {
1696 tp = &vap->iv_txparms[ieee80211_chan2mode(ni->ni_chan)];
1697 /* for data frames */
1698 if (IEEE80211_IS_MULTICAST(wh->i_addr1))
1699 rate = tp->mcastrate;
1700 else if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE)
1701 rate = tp->ucastrate;
1702 else
1703 rate = urtw_rtl2rate(sc->sc_currate);
1704 }
1705
1706 sc->sc_stats.txrates[sc->sc_currate]++;
1707
1708 if (IEEE80211_IS_MULTICAST(wh->i_addr1))
1709 txdur = pkttime = urtw_compute_txtime(m0->m_pkthdr.len +
1710 IEEE80211_CRC_LEN, rate, 0, 0);
1711 else {
1712 acktime = urtw_compute_txtime(14, 2,0, 0);
1713 if ((m0->m_pkthdr.len + 4) > vap->iv_rtsthreshold) {
1714 rtsenable = 1;
1715 ctsenable = 0;
1716 rtstime = urtw_compute_txtime(URTW_ACKCTS_LEN, 2, 0, 0);
1717 ctstime = urtw_compute_txtime(14, 2, 0, 0);
1718 pkttime = urtw_compute_txtime(m0->m_pkthdr.len +
1719 IEEE80211_CRC_LEN, rate, 0, isshort);
1720 rtsdur = ctstime + pkttime + acktime +
1721 3 * URTW_ASIFS_TIME;
1722 txdur = rtstime + rtsdur;
1723 } else {
1724 rtsenable = ctsenable = rtsdur = 0;
1725 pkttime = urtw_compute_txtime(m0->m_pkthdr.len +
1726 IEEE80211_CRC_LEN, rate, 0, isshort);
1727 txdur = pkttime + URTW_ASIFS_TIME + acktime;
1728 }
1729
1730 if (wh->i_fc[1] & IEEE80211_FC1_MORE_FRAG)
1731 dur = urtw_compute_txtime(m0->m_pkthdr.len +
1732 IEEE80211_CRC_LEN, rate, 0, isshort) +
1733 3 * URTW_ASIFS_TIME +
1734 2 * acktime;
1735 else
1736 dur = URTW_ASIFS_TIME + acktime;
1737 }
1738 *(uint16_t *)wh->i_dur = htole16(dur);
1739
1740 xferlen = m0->m_pkthdr.len;
1741 xferlen += (sc->sc_flags & URTW_RTL8187B) ? (4 * 8) : (4 * 3);
1742 if ((0 == xferlen % 64) || (0 == xferlen % 512))
1743 xferlen += 1;
1744
1745 memset(data->buf, 0, URTW_TX_MAXSIZE);
1746 flags = m0->m_pkthdr.len & 0xfff;
1747 flags |= URTW_TX_FLAG_NO_ENC;
1748 if ((ic->ic_flags & IEEE80211_F_SHPREAMBLE) &&
1749 (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE) &&
1750 (sc->sc_preamble_mode == URTW_PREAMBLE_MODE_SHORT) &&
1751 (sc->sc_currate != 0))
1752 flags |= URTW_TX_FLAG_SPLCP;
1753 if (wh->i_fc[1] & IEEE80211_FC1_MORE_FRAG)
1754 flags |= URTW_TX_FLAG_MOREFRAG;
1755
1756 flags |= (sc->sc_currate & 0xf) << URTW_TX_FLAG_TXRATE_SHIFT;
1757
1758 if (sc->sc_flags & URTW_RTL8187B) {
1759 struct urtw_8187b_txhdr *tx;
1760
1761 tx = (struct urtw_8187b_txhdr *)data->buf;
1762 if (ctsenable)
1763 flags |= URTW_TX_FLAG_CTS;
1764 if (rtsenable) {
1765 flags |= URTW_TX_FLAG_RTS;
1766 flags |= (urtw_rate2rtl(11) & 0xf) <<
1767 URTW_TX_FLAG_RTSRATE_SHIFT;
1768 tx->rtsdur = rtsdur;
1769 }
1770 tx->flag = htole32(flags);
1771 tx->txdur = txdur;
1772 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) ==
1773 IEEE80211_FC0_TYPE_MGT &&
1774 (wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) ==
1775 IEEE80211_FC0_SUBTYPE_PROBE_RESP)
1776 tx->retry = 1;
1777 else
1778 tx->retry = URTW_TX_MAXRETRY;
1779 m_copydata(m0, 0, m0->m_pkthdr.len, (uint8_t *)(tx + 1));
1780 } else {
1781 struct urtw_8187l_txhdr *tx;
1782
1783 tx = (struct urtw_8187l_txhdr *)data->buf;
1784 if (rtsenable) {
1785 flags |= URTW_TX_FLAG_RTS;
1786 tx->rtsdur = rtsdur;
1787 }
1788 flags |= (urtw_rate2rtl(11) & 0xf) << URTW_TX_FLAG_RTSRATE_SHIFT;
1789 tx->flag = htole32(flags);
1790 tx->retry = 3; /* CW minimum */
1791 tx->retry = 7 << 4; /* CW maximum */
1792 tx->retry = URTW_TX_MAXRETRY << 8; /* retry limitation */
1793 m_copydata(m0, 0, m0->m_pkthdr.len, (uint8_t *)(tx + 1));
1794 }
1795
1796 data->buflen = xferlen;
1797 data->ni = ni;
1798 data->m = m0;
1799
1800 if (sc->sc_flags & URTW_RTL8187B) {
1801 switch (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) {
1802 case IEEE80211_FC0_TYPE_CTL:
1803 case IEEE80211_FC0_TYPE_MGT:
1804 xfer = sc->sc_xfer[URTW_8187B_BULK_TX_EP12];
1805 break;
1806 default:
1807 KASSERT(M_WME_GETAC(m0) < URTW_8187B_TXPIPE_MAX,
1808 ("unsupported WME pipe %d", M_WME_GETAC(m0)));
1809 xfer = rtl8187b_pipes[M_WME_GETAC(m0)];
1810 break;
1811 }
1812 } else
1813 xfer = (prior == URTW_PRIORITY_LOW) ?
1814 sc->sc_xfer[URTW_8187L_BULK_TX_LOW] :
1815 sc->sc_xfer[URTW_8187L_BULK_TX_NORMAL];
1816
1817 STAILQ_INSERT_TAIL(&sc->sc_tx_pending, data, next);
1818 usbd_transfer_start(xfer);
1819
1820 error = urtw_led_ctl(sc, URTW_LED_CTL_TX);
1821 if (error != 0)
1822 device_printf(sc->sc_dev, "could not control LED (%d)\n",
1823 error);
1824 return (0);
1825}
1826
1827static int
1828urtw_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg)
1829{
1830 struct ieee80211com *ic = vap->iv_ic;
1831 struct urtw_softc *sc = ic->ic_ifp->if_softc;
1832 struct urtw_vap *uvp = URTW_VAP(vap);
1833 struct ieee80211_node *ni;
1834 usb_error_t error = 0;
1835
1836 DPRINTF(sc, URTW_DEBUG_STATE, "%s: %s -> %s\n", __func__,
1837 ieee80211_state_name[vap->iv_state],
1838 ieee80211_state_name[nstate]);
1839
1840 sc->sc_state = nstate;
1841
1842 IEEE80211_UNLOCK(ic);
1843 URTW_LOCK(sc);
1844 usb_callout_stop(&sc->sc_led_ch);
1845 callout_stop(&sc->sc_watchdog_ch);
1846
1847 switch (nstate) {
1848 case IEEE80211_S_INIT:
1849 case IEEE80211_S_SCAN:
1850 case IEEE80211_S_AUTH:
1851 case IEEE80211_S_ASSOC:
1852 break;
1853 case IEEE80211_S_RUN:
1854 ni = ieee80211_ref_node(vap->iv_bss);
1855 /* setting bssid. */
1856 urtw_write32_m(sc, URTW_BSSID, ((uint32_t *)ni->ni_bssid)[0]);
1857 urtw_write16_m(sc, URTW_BSSID + 4,
1858 ((uint16_t *)ni->ni_bssid)[2]);
1859 urtw_update_msr(sc);
1860 /* XXX maybe the below would be incorrect. */
1861 urtw_write16_m(sc, URTW_ATIM_WND, 2);
1862 urtw_write16_m(sc, URTW_ATIM_TR_ITV, 100);
1863 urtw_write16_m(sc, URTW_BEACON_INTERVAL, 0x64);
1864 urtw_write16_m(sc, URTW_BEACON_INTERVAL_TIME, 100);
1865 error = urtw_led_ctl(sc, URTW_LED_CTL_LINK);
1866 if (error != 0)
1867 device_printf(sc->sc_dev,
1868 "could not control LED (%d)\n", error);
1869 ieee80211_free_node(ni);
1870 break;
1871 default:
1872 break;
1873 }
1874fail:
1875 URTW_UNLOCK(sc);
1876 IEEE80211_LOCK(ic);
1877 return (uvp->newstate(vap, nstate, arg));
1878}
1879
1880static void
1881urtw_watchdog(void *arg)
1882{
1883 struct urtw_softc *sc = arg;
1884 struct ifnet *ifp = sc->sc_ifp;
1885
1886 if (sc->sc_txtimer > 0) {
1887 if (--sc->sc_txtimer == 0) {
1888 device_printf(sc->sc_dev, "device timeout\n");
1889 ifp->if_oerrors++;
1890 return;
1891 }
1892 callout_reset(&sc->sc_watchdog_ch, hz, urtw_watchdog, sc);
1893 }
1894}
1895
1896static void
1897urtw_set_multi(void *arg)
1898{
1899 struct urtw_softc *sc = arg;
1900 struct ifnet *ifp = sc->sc_ifp;
1901
1902 if (!(ifp->if_flags & IFF_UP))
1903 return;
1904
1905 /*
1906 * XXX don't know how to set a device. Lack of docs. Just try to set
1907 * IFF_ALLMULTI flag here.
1908 */
1909 ifp->if_flags |= IFF_ALLMULTI;
1910}
1911
1912static usb_error_t
1913urtw_set_rate(struct urtw_softc *sc)
1914{
1915 int i, basic_rate, min_rr_rate, max_rr_rate;
1916 uint16_t data;
1917 usb_error_t error;
1918
1919 basic_rate = urtw_rate2rtl(48);
1920 min_rr_rate = urtw_rate2rtl(12);
1921 max_rr_rate = urtw_rate2rtl(48);
1922
1923 urtw_write8_m(sc, URTW_RESP_RATE,
1924 max_rr_rate << URTW_RESP_MAX_RATE_SHIFT |
1925 min_rr_rate << URTW_RESP_MIN_RATE_SHIFT);
1926
1927 urtw_read16_m(sc, URTW_BRSR, &data);
1928 data &= ~URTW_BRSR_MBR_8185;
1929
1930 for (i = 0; i <= basic_rate; i++)
1931 data |= (1 << i);
1932
1933 urtw_write16_m(sc, URTW_BRSR, data);
1934fail:
1935 return (error);
1936}
1937
1938static uint16_t
1939urtw_rate2rtl(uint32_t rate)
1940{
1941#define N(a) ((int)(sizeof(a) / sizeof((a)[0])))
1942 int i;
1943
1944 for (i = 0; i < N(urtw_ratetable); i++) {
1945 if (rate == urtw_ratetable[i].reg)
1946 return urtw_ratetable[i].val;
1947 }
1948
1949 return (3);
1950#undef N
1951}
1952
1953static uint16_t
1954urtw_rtl2rate(uint32_t rate)
1955{
1956#define N(a) ((int)(sizeof(a) / sizeof((a)[0])))
1957 int i;
1958
1959 for (i = 0; i < N(urtw_ratetable); i++) {
1960 if (rate == urtw_ratetable[i].val)
1961 return urtw_ratetable[i].reg;
1962 }
1963
1964 return (0);
1965#undef N
1966}
1967
1968static usb_error_t
1969urtw_update_msr(struct urtw_softc *sc)
1970{
1971 struct ifnet *ifp = sc->sc_ifp;
1972 struct ieee80211com *ic = ifp->if_l2com;
1973 uint8_t data;
1974 usb_error_t error;
1975
1976 urtw_read8_m(sc, URTW_MSR, &data);
1977 data &= ~URTW_MSR_LINK_MASK;
1978
1979 if (sc->sc_state == IEEE80211_S_RUN) {
1980 switch (ic->ic_opmode) {
1981 case IEEE80211_M_STA:
1982 case IEEE80211_M_MONITOR:
1983 data |= URTW_MSR_LINK_STA;
1984 if (sc->sc_flags & URTW_RTL8187B)
1985 data |= URTW_MSR_LINK_ENEDCA;
1986 break;
1987 case IEEE80211_M_IBSS:
1988 data |= URTW_MSR_LINK_ADHOC;
1989 break;
1990 case IEEE80211_M_HOSTAP:
1991 data |= URTW_MSR_LINK_HOSTAP;
1992 break;
1993 default:
1994 panic("unsupported operation mode 0x%x\n",
1995 ic->ic_opmode);
1996 /* never reach */
1997 }
1998 } else
1999 data |= URTW_MSR_LINK_NONE;
2000
2001 urtw_write8_m(sc, URTW_MSR, data);
2002fail:
2003 return (error);
2004}
2005
2006static usb_error_t
2007urtw_read8_c(struct urtw_softc *sc, int val, uint8_t *data)
2008{
2009 struct usb_device_request req;
2010 usb_error_t error;
2011
2012 URTW_ASSERT_LOCKED(sc);
2013
2014 req.bmRequestType = UT_READ_VENDOR_DEVICE;
2015 req.bRequest = URTW_8187_GETREGS_REQ;
2016 USETW(req.wValue, (val & 0xff) | 0xff00);
2017 USETW(req.wIndex, (val >> 8) & 0x3);
2018 USETW(req.wLength, sizeof(uint8_t));
2019
2020 error = urtw_do_request(sc, &req, data);
2021 return (error);
2022}
2023
2024static usb_error_t
2025urtw_read16_c(struct urtw_softc *sc, int val, uint16_t *data)
2026{
2027 struct usb_device_request req;
2028 usb_error_t error;
2029
2030 URTW_ASSERT_LOCKED(sc);
2031
2032 req.bmRequestType = UT_READ_VENDOR_DEVICE;
2033 req.bRequest = URTW_8187_GETREGS_REQ;
2034 USETW(req.wValue, (val & 0xff) | 0xff00);
2035 USETW(req.wIndex, (val >> 8) & 0x3);
2036 USETW(req.wLength, sizeof(uint16_t));
2037
2038 error = urtw_do_request(sc, &req, data);
2039 return (error);
2040}
2041
2042static usb_error_t
2043urtw_read32_c(struct urtw_softc *sc, int val, uint32_t *data)
2044{
2045 struct usb_device_request req;
2046 usb_error_t error;
2047
2048 URTW_ASSERT_LOCKED(sc);
2049
2050 req.bmRequestType = UT_READ_VENDOR_DEVICE;
2051 req.bRequest = URTW_8187_GETREGS_REQ;
2052 USETW(req.wValue, (val & 0xff) | 0xff00);
2053 USETW(req.wIndex, (val >> 8) & 0x3);
2054 USETW(req.wLength, sizeof(uint32_t));
2055
2056 error = urtw_do_request(sc, &req, data);
2057 return (error);
2058}
2059
2060static usb_error_t
2061urtw_write8_c(struct urtw_softc *sc, int val, uint8_t data)
2062{
2063 struct usb_device_request req;
2064
2065 URTW_ASSERT_LOCKED(sc);
2066
2067 req.bmRequestType = UT_WRITE_VENDOR_DEVICE;
2068 req.bRequest = URTW_8187_SETREGS_REQ;
2069 USETW(req.wValue, (val & 0xff) | 0xff00);
2070 USETW(req.wIndex, (val >> 8) & 0x3);
2071 USETW(req.wLength, sizeof(uint8_t));
2072
2073 return (urtw_do_request(sc, &req, &data));
2074}
2075
2076static usb_error_t
2077urtw_write16_c(struct urtw_softc *sc, int val, uint16_t data)
2078{
2079 struct usb_device_request req;
2080
2081 URTW_ASSERT_LOCKED(sc);
2082
2083 req.bmRequestType = UT_WRITE_VENDOR_DEVICE;
2084 req.bRequest = URTW_8187_SETREGS_REQ;
2085 USETW(req.wValue, (val & 0xff) | 0xff00);
2086 USETW(req.wIndex, (val >> 8) & 0x3);
2087 USETW(req.wLength, sizeof(uint16_t));
2088
2089 return (urtw_do_request(sc, &req, &data));
2090}
2091
2092static usb_error_t
2093urtw_write32_c(struct urtw_softc *sc, int val, uint32_t data)
2094{
2095 struct usb_device_request req;
2096
2097 URTW_ASSERT_LOCKED(sc);
2098
2099 req.bmRequestType = UT_WRITE_VENDOR_DEVICE;
2100 req.bRequest = URTW_8187_SETREGS_REQ;
2101 USETW(req.wValue, (val & 0xff) | 0xff00);
2102 USETW(req.wIndex, (val >> 8) & 0x3);
2103 USETW(req.wLength, sizeof(uint32_t));
2104
2105 return (urtw_do_request(sc, &req, &data));
2106}
2107
2108static usb_error_t
2109urtw_get_macaddr(struct urtw_softc *sc)
2110{
2111 uint32_t data;
2112 usb_error_t error;
2113
2114 error = urtw_eprom_read32(sc, URTW_EPROM_MACADDR, &data);
2115 if (error != 0)
2116 goto fail;
2117 sc->sc_bssid[0] = data & 0xff;
2118 sc->sc_bssid[1] = (data & 0xff00) >> 8;
2119 error = urtw_eprom_read32(sc, URTW_EPROM_MACADDR + 1, &data);
2120 if (error != 0)
2121 goto fail;
2122 sc->sc_bssid[2] = data & 0xff;
2123 sc->sc_bssid[3] = (data & 0xff00) >> 8;
2124 error = urtw_eprom_read32(sc, URTW_EPROM_MACADDR + 2, &data);
2125 if (error != 0)
2126 goto fail;
2127 sc->sc_bssid[4] = data & 0xff;
2128 sc->sc_bssid[5] = (data & 0xff00) >> 8;
2129fail:
2130 return (error);
2131}
2132
2133static usb_error_t
2134urtw_eprom_read32(struct urtw_softc *sc, uint32_t addr, uint32_t *data)
2135{
2136#define URTW_READCMD_LEN 3
2137 int addrlen, i;
2138 int16_t addrstr[8], data16, readcmd[] = { 1, 1, 0 };
2139 usb_error_t error;
2140
2141 /* NB: make sure the buffer is initialized */
2142 *data = 0;
2143
2144 /* enable EPROM programming */
2145 urtw_write8_m(sc, URTW_EPROM_CMD, URTW_EPROM_CMD_PROGRAM_MODE);
2146 DELAY(URTW_EPROM_DELAY);
2147
2148 error = urtw_eprom_cs(sc, URTW_EPROM_ENABLE);
2149 if (error != 0)
2150 goto fail;
2151 error = urtw_eprom_ck(sc);
2152 if (error != 0)
2153 goto fail;
2154 error = urtw_eprom_sendbits(sc, readcmd, URTW_READCMD_LEN);
2155 if (error != 0)
2156 goto fail;
2157 if (sc->sc_epromtype == URTW_EEPROM_93C56) {
2158 addrlen = 8;
2159 addrstr[0] = addr & (1 << 7);
2160 addrstr[1] = addr & (1 << 6);
2161 addrstr[2] = addr & (1 << 5);
2162 addrstr[3] = addr & (1 << 4);
2163 addrstr[4] = addr & (1 << 3);
2164 addrstr[5] = addr & (1 << 2);
2165 addrstr[6] = addr & (1 << 1);
2166 addrstr[7] = addr & (1 << 0);
2167 } else {
2168 addrlen=6;
2169 addrstr[0] = addr & (1 << 5);
2170 addrstr[1] = addr & (1 << 4);
2171 addrstr[2] = addr & (1 << 3);
2172 addrstr[3] = addr & (1 << 2);
2173 addrstr[4] = addr & (1 << 1);
2174 addrstr[5] = addr & (1 << 0);
2175 }
2176 error = urtw_eprom_sendbits(sc, addrstr, addrlen);
2177 if (error != 0)
2178 goto fail;
2179
2180 error = urtw_eprom_writebit(sc, 0);
2181 if (error != 0)
2182 goto fail;
2183
2184 for (i = 0; i < 16; i++) {
2185 error = urtw_eprom_ck(sc);
2186 if (error != 0)
2187 goto fail;
2188 error = urtw_eprom_readbit(sc, &data16);
2189 if (error != 0)
2190 goto fail;
2191
2192 (*data) |= (data16 << (15 - i));
2193 }
2194
2195 error = urtw_eprom_cs(sc, URTW_EPROM_DISABLE);
2196 if (error != 0)
2197 goto fail;
2198 error = urtw_eprom_ck(sc);
2199 if (error != 0)
2200 goto fail;
2201
2202 /* now disable EPROM programming */
2203 urtw_write8_m(sc, URTW_EPROM_CMD, URTW_EPROM_CMD_NORMAL_MODE);
2204fail:
2205 return (error);
2206#undef URTW_READCMD_LEN
2207}
2208
2209static usb_error_t
2210urtw_eprom_cs(struct urtw_softc *sc, int able)
2211{
2212 uint8_t data;
2213 usb_error_t error;
2214
2215 urtw_read8_m(sc, URTW_EPROM_CMD, &data);
2216 if (able == URTW_EPROM_ENABLE)
2217 urtw_write8_m(sc, URTW_EPROM_CMD, data | URTW_EPROM_CS);
2218 else
2219 urtw_write8_m(sc, URTW_EPROM_CMD, data & ~URTW_EPROM_CS);
2220 DELAY(URTW_EPROM_DELAY);
2221fail:
2222 return (error);
2223}
2224
2225static usb_error_t
2226urtw_eprom_ck(struct urtw_softc *sc)
2227{
2228 uint8_t data;
2229 usb_error_t error;
2230
2231 /* masking */
2232 urtw_read8_m(sc, URTW_EPROM_CMD, &data);
2233 urtw_write8_m(sc, URTW_EPROM_CMD, data | URTW_EPROM_CK);
2234 DELAY(URTW_EPROM_DELAY);
2235 /* unmasking */
2236 urtw_read8_m(sc, URTW_EPROM_CMD, &data);
2237 urtw_write8_m(sc, URTW_EPROM_CMD, data & ~URTW_EPROM_CK);
2238 DELAY(URTW_EPROM_DELAY);
2239fail:
2240 return (error);
2241}
2242
2243static usb_error_t
2244urtw_eprom_readbit(struct urtw_softc *sc, int16_t *data)
2245{
2246 uint8_t data8;
2247 usb_error_t error;
2248
2249 urtw_read8_m(sc, URTW_EPROM_CMD, &data8);
2250 *data = (data8 & URTW_EPROM_READBIT) ? 1 : 0;
2251 DELAY(URTW_EPROM_DELAY);
2252
2253fail:
2254 return (error);
2255}
2256
2257static usb_error_t
2258urtw_eprom_writebit(struct urtw_softc *sc, int16_t bit)
2259{
2260 uint8_t data;
2261 usb_error_t error;
2262
2263 urtw_read8_m(sc, URTW_EPROM_CMD, &data);
2264 if (bit != 0)
2265 urtw_write8_m(sc, URTW_EPROM_CMD, data | URTW_EPROM_WRITEBIT);
2266 else
2267 urtw_write8_m(sc, URTW_EPROM_CMD, data & ~URTW_EPROM_WRITEBIT);
2268 DELAY(URTW_EPROM_DELAY);
2269fail:
2270 return (error);
2271}
2272
2273static usb_error_t
2274urtw_eprom_sendbits(struct urtw_softc *sc, int16_t *buf, int buflen)
2275{
2276 int i = 0;
2277 usb_error_t error = 0;
2278
2279 for (i = 0; i < buflen; i++) {
2280 error = urtw_eprom_writebit(sc, buf[i]);
2281 if (error != 0)
2282 goto fail;
2283 error = urtw_eprom_ck(sc);
2284 if (error != 0)
2285 goto fail;
2286 }
2287fail:
2288 return (error);
2289}
2290
2291
2292static usb_error_t
2293urtw_get_txpwr(struct urtw_softc *sc)
2294{
2295 int i, j;
2296 uint32_t data;
2297 usb_error_t error;
2298
2299 error = urtw_eprom_read32(sc, URTW_EPROM_TXPW_BASE, &data);
2300 if (error != 0)
2301 goto fail;
2302 sc->sc_txpwr_cck_base = data & 0xf;
2303 sc->sc_txpwr_ofdm_base = (data >> 4) & 0xf;
2304
2305 for (i = 1, j = 0; i < 6; i += 2, j++) {
2306 error = urtw_eprom_read32(sc, URTW_EPROM_TXPW0 + j, &data);
2307 if (error != 0)
2308 goto fail;
2309 sc->sc_txpwr_cck[i] = data & 0xf;
2310 sc->sc_txpwr_cck[i + 1] = (data & 0xf00) >> 8;
2311 sc->sc_txpwr_ofdm[i] = (data & 0xf0) >> 4;
2312 sc->sc_txpwr_ofdm[i + 1] = (data & 0xf000) >> 12;
2313 }
2314 for (i = 1, j = 0; i < 4; i += 2, j++) {
2315 error = urtw_eprom_read32(sc, URTW_EPROM_TXPW1 + j, &data);
2316 if (error != 0)
2317 goto fail;
2318 sc->sc_txpwr_cck[i + 6] = data & 0xf;
2319 sc->sc_txpwr_cck[i + 6 + 1] = (data & 0xf00) >> 8;
2320 sc->sc_txpwr_ofdm[i + 6] = (data & 0xf0) >> 4;
2321 sc->sc_txpwr_ofdm[i + 6 + 1] = (data & 0xf000) >> 12;
2322 }
2323 if (sc->sc_flags & URTW_RTL8187B) {
2324 error = urtw_eprom_read32(sc, URTW_EPROM_TXPW2, &data);
2325 if (error != 0)
2326 goto fail;
2327 sc->sc_txpwr_cck[1 + 6 + 4] = data & 0xf;
2328 sc->sc_txpwr_ofdm[1 + 6 + 4] = (data & 0xf0) >> 4;
2329 error = urtw_eprom_read32(sc, 0x0a, &data);
2330 if (error != 0)
2331 goto fail;
2332 sc->sc_txpwr_cck[2 + 6 + 4] = data & 0xf;
2333 sc->sc_txpwr_ofdm[2 + 6 + 4] = (data & 0xf0) >> 4;
2334 error = urtw_eprom_read32(sc, 0x1c, &data);
2335 if (error != 0)
2336 goto fail;
2337 sc->sc_txpwr_cck[3 + 6 + 4] = data & 0xf;
2338 sc->sc_txpwr_cck[3 + 6 + 4 + 1] = (data & 0xf00) >> 8;
2339 sc->sc_txpwr_ofdm[3 + 6 + 4] = (data & 0xf0) >> 4;
2340 sc->sc_txpwr_ofdm[3 + 6 + 4 + 1] = (data & 0xf000) >> 12;
2341 } else {
2342 for (i = 1, j = 0; i < 4; i += 2, j++) {
2343 error = urtw_eprom_read32(sc, URTW_EPROM_TXPW2 + j,
2344 &data);
2345 if (error != 0)
2346 goto fail;
2347 sc->sc_txpwr_cck[i + 6 + 4] = data & 0xf;
2348 sc->sc_txpwr_cck[i + 6 + 4 + 1] = (data & 0xf00) >> 8;
2349 sc->sc_txpwr_ofdm[i + 6 + 4] = (data & 0xf0) >> 4;
2350 sc->sc_txpwr_ofdm[i + 6 + 4 + 1] = (data & 0xf000) >> 12;
2351 }
2352 }
2353fail:
2354 return (error);
2355}
2356
2357
2358static usb_error_t
2359urtw_get_rfchip(struct urtw_softc *sc)
2360{
2361 int ret;
2362 uint8_t data8;
2363 uint32_t data;
2364 usb_error_t error;
2365
2366 if (sc->sc_flags & URTW_RTL8187B) {
2367 urtw_read8_m(sc, 0xe1, &data8);
2368 switch (data8) {
2369 case 0:
2370 sc->sc_flags |= URTW_RTL8187B_REV_B;
2371 break;
2372 case 1:
2373 sc->sc_flags |= URTW_RTL8187B_REV_D;
2374 break;
2375 case 2:
2376 sc->sc_flags |= URTW_RTL8187B_REV_E;
2377 break;
2378 default:
2379 device_printf(sc->sc_dev, "unknown type: %#x\n", data8);
2380 sc->sc_flags |= URTW_RTL8187B_REV_B;
2381 break;
2382 }
2383 } else {
2384 urtw_read32_m(sc, URTW_TX_CONF, &data);
2385 switch (data & URTW_TX_HWMASK) {
2386 case URTW_TX_R8187vD_B:
2387 sc->sc_flags |= URTW_RTL8187B;
2388 break;
2389 case URTW_TX_R8187vD:
2390 break;
2391 default:
2392 device_printf(sc->sc_dev, "unknown RTL8187L type: %#x\n",
2393 data & URTW_TX_HWMASK);
2394 break;
2395 }
2396 }
2397
2398 error = urtw_eprom_read32(sc, URTW_EPROM_RFCHIPID, &data);
2399 if (error != 0)
2400 goto fail;
2401 switch (data & 0xff) {
2402 case URTW_EPROM_RFCHIPID_RTL8225U:
2403 error = urtw_8225_isv2(sc, &ret);
2404 if (error != 0)
2405 goto fail;
2406 if (ret == 0) {
2407 sc->sc_rf_init = urtw_8225_rf_init;
2408 sc->sc_rf_set_sens = urtw_8225_rf_set_sens;
2409 sc->sc_rf_set_chan = urtw_8225_rf_set_chan;
2410 sc->sc_rf_stop = urtw_8225_rf_stop;
2411 } else {
2412 sc->sc_rf_init = urtw_8225v2_rf_init;
2413 sc->sc_rf_set_chan = urtw_8225v2_rf_set_chan;
2414 sc->sc_rf_stop = urtw_8225_rf_stop;
2415 }
2416 sc->sc_max_sens = URTW_8225_RF_MAX_SENS;
2417 sc->sc_sens = URTW_8225_RF_DEF_SENS;
2418 break;
2419 case URTW_EPROM_RFCHIPID_RTL8225Z2:
2420 sc->sc_rf_init = urtw_8225v2b_rf_init;
2421 sc->sc_rf_set_chan = urtw_8225v2b_rf_set_chan;
2422 sc->sc_max_sens = URTW_8225_RF_MAX_SENS;
2423 sc->sc_sens = URTW_8225_RF_DEF_SENS;
2424 sc->sc_rf_stop = urtw_8225_rf_stop;
2425 break;
2426 default:
2427 panic("unsupported RF chip %d\n", data & 0xff);
2428 /* never reach */
2429 }
2430
2431 device_printf(sc->sc_dev, "%s rf %s hwrev %s\n",
2432 (sc->sc_flags & URTW_RTL8187B) ? "rtl8187b" : "rtl8187l",
2433 ((data & 0xff) == URTW_EPROM_RFCHIPID_RTL8225U) ? "rtl8225u" :
2434 "rtl8225z2",
2435 (sc->sc_flags & URTW_RTL8187B) ? ((data8 == 0) ? "b" :
2436 (data8 == 1) ? "d" : "e") : "none");
2437
2438fail:
2439 return (error);
2440}
2441
2442
2443static usb_error_t
2444urtw_led_init(struct urtw_softc *sc)
2445{
2446 uint32_t rev;
2447 usb_error_t error;
2448
2449 urtw_read8_m(sc, URTW_PSR, &sc->sc_psr);
2450 error = urtw_eprom_read32(sc, URTW_EPROM_SWREV, &rev);
2451 if (error != 0)
2452 goto fail;
2453
2454 switch (rev & URTW_EPROM_CID_MASK) {
2455 case URTW_EPROM_CID_ALPHA0:
2456 sc->sc_strategy = URTW_SW_LED_MODE1;
2457 break;
2458 case URTW_EPROM_CID_SERCOMM_PS:
2459 sc->sc_strategy = URTW_SW_LED_MODE3;
2460 break;
2461 case URTW_EPROM_CID_HW_LED:
2462 sc->sc_strategy = URTW_HW_LED;
2463 break;
2464 case URTW_EPROM_CID_RSVD0:
2465 case URTW_EPROM_CID_RSVD1:
2466 default:
2467 sc->sc_strategy = URTW_SW_LED_MODE0;
2468 break;
2469 }
2470
2471 sc->sc_gpio_ledpin = URTW_LED_PIN_GPIO0;
2472
2473fail:
2474 return (error);
2475}
2476
2477
2478static usb_error_t
2479urtw_8225_rf_init(struct urtw_softc *sc)
2480{
2481#define N(a) ((int)(sizeof(a) / sizeof((a)[0])))
2482 int i;
2483 uint16_t data;
2484 usb_error_t error;
2485
2486 error = urtw_8180_set_anaparam(sc, URTW_8225_ANAPARAM_ON);
2487 if (error)
2488 goto fail;
2489
2490 error = urtw_8225_usb_init(sc);
2491 if (error)
2492 goto fail;
2493
2494 urtw_write32_m(sc, URTW_RF_TIMING, 0x000a8008);
2495 urtw_read16_m(sc, URTW_BRSR, &data); /* XXX ??? */
2496 urtw_write16_m(sc, URTW_BRSR, 0xffff);
2497 urtw_write32_m(sc, URTW_RF_PARA, 0x100044);
2498
2499 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG);
2500 if (error)
2501 goto fail;
2502 urtw_write8_m(sc, URTW_CONFIG3, 0x44);
2503 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL);
2504 if (error)
2505 goto fail;
2506
2507 error = urtw_8185_rf_pins_enable(sc);
2508 if (error)
2509 goto fail;
2510 usb_pause_mtx(&sc->sc_mtx, 1000);
2511
2512 for (i = 0; i < N(urtw_8225_rf_part1); i++) {
2513 urtw_8225_write(sc, urtw_8225_rf_part1[i].reg,
2514 urtw_8225_rf_part1[i].val);
2515 usb_pause_mtx(&sc->sc_mtx, 1);
2516 }
2517 usb_pause_mtx(&sc->sc_mtx, 100);
2518 urtw_8225_write(sc,
2519 URTW_8225_ADDR_2_MAGIC, URTW_8225_ADDR_2_DATA_MAGIC1);
2520 usb_pause_mtx(&sc->sc_mtx, 200);
2521 urtw_8225_write(sc,
2522 URTW_8225_ADDR_2_MAGIC, URTW_8225_ADDR_2_DATA_MAGIC2);
2523 usb_pause_mtx(&sc->sc_mtx, 200);
2524 urtw_8225_write(sc,
2525 URTW_8225_ADDR_0_MAGIC, URTW_8225_ADDR_0_DATA_MAGIC3);
2526
2527 for (i = 0; i < 95; i++) {
2528 urtw_8225_write(sc, URTW_8225_ADDR_1_MAGIC, (uint8_t)(i + 1));
2529 urtw_8225_write(sc, URTW_8225_ADDR_2_MAGIC, urtw_8225_rxgain[i]);
2530 }
2531
2532 urtw_8225_write(sc,
2533 URTW_8225_ADDR_0_MAGIC, URTW_8225_ADDR_0_DATA_MAGIC4);
2534 urtw_8225_write(sc,
2535 URTW_8225_ADDR_0_MAGIC, URTW_8225_ADDR_0_DATA_MAGIC5);
2536
2537 for (i = 0; i < 128; i++) {
2538 urtw_8187_write_phy_ofdm(sc, 0xb, urtw_8225_agc[i]);
2539 usb_pause_mtx(&sc->sc_mtx, 1);
2540 urtw_8187_write_phy_ofdm(sc, 0xa, (uint8_t)i + 0x80);
2541 usb_pause_mtx(&sc->sc_mtx, 1);
2542 }
2543
2544 for (i = 0; i < N(urtw_8225_rf_part2); i++) {
2545 urtw_8187_write_phy_ofdm(sc, urtw_8225_rf_part2[i].reg,
2546 urtw_8225_rf_part2[i].val);
2547 usb_pause_mtx(&sc->sc_mtx, 1);
2548 }
2549
2550 error = urtw_8225_setgain(sc, 4);
2551 if (error)
2552 goto fail;
2553
2554 for (i = 0; i < N(urtw_8225_rf_part3); i++) {
2555 urtw_8187_write_phy_cck(sc, urtw_8225_rf_part3[i].reg,
2556 urtw_8225_rf_part3[i].val);
2557 usb_pause_mtx(&sc->sc_mtx, 1);
2558 }
2559
2560 urtw_write8_m(sc, URTW_TESTR, 0x0d);
2561
2562 error = urtw_8225_set_txpwrlvl(sc, 1);
2563 if (error)
2564 goto fail;
2565
2566 urtw_8187_write_phy_cck(sc, 0x10, 0x9b);
2567 usb_pause_mtx(&sc->sc_mtx, 1);
2568 urtw_8187_write_phy_ofdm(sc, 0x26, 0x90);
2569 usb_pause_mtx(&sc->sc_mtx, 1);
2570
2571 /* TX ant A, 0x0 for B */
2572 error = urtw_8185_tx_antenna(sc, 0x3);
2573 if (error)
2574 goto fail;
2575 urtw_write32_m(sc, URTW_HSSI_PARA, 0x3dc00002);
2576
2577 error = urtw_8225_rf_set_chan(sc, 1);
2578fail:
2579 return (error);
2580#undef N
2581}
2582
2583static usb_error_t
2584urtw_8185_rf_pins_enable(struct urtw_softc *sc)
2585{
2586 usb_error_t error = 0;
2587
2588 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, 0x1ff7);
2589fail:
2590 return (error);
2591}
2592
2593static usb_error_t
2594urtw_8185_tx_antenna(struct urtw_softc *sc, uint8_t ant)
2595{
2596 usb_error_t error;
2597
2598 urtw_write8_m(sc, URTW_TX_ANTENNA, ant);
2599 usb_pause_mtx(&sc->sc_mtx, 1);
2600fail:
2601 return (error);
2602}
2603
2604static usb_error_t
2605urtw_8187_write_phy_ofdm_c(struct urtw_softc *sc, uint8_t addr, uint32_t data)
2606{
2607
2608 data = data & 0xff;
2609 return urtw_8187_write_phy(sc, addr, data);
2610}
2611
2612static usb_error_t
2613urtw_8187_write_phy_cck_c(struct urtw_softc *sc, uint8_t addr, uint32_t data)
2614{
2615
2616 data = data & 0xff;
2617 return urtw_8187_write_phy(sc, addr, data | 0x10000);
2618}
2619
2620static usb_error_t
2621urtw_8187_write_phy(struct urtw_softc *sc, uint8_t addr, uint32_t data)
2622{
2623 uint32_t phyw;
2624 usb_error_t error;
2625
2626 phyw = ((data << 8) | (addr | 0x80));
2627 urtw_write8_m(sc, URTW_PHY_MAGIC4, ((phyw & 0xff000000) >> 24));
2628 urtw_write8_m(sc, URTW_PHY_MAGIC3, ((phyw & 0x00ff0000) >> 16));
2629 urtw_write8_m(sc, URTW_PHY_MAGIC2, ((phyw & 0x0000ff00) >> 8));
2630 urtw_write8_m(sc, URTW_PHY_MAGIC1, ((phyw & 0x000000ff)));
2631 usb_pause_mtx(&sc->sc_mtx, 1);
2632fail:
2633 return (error);
2634}
2635
2636static usb_error_t
2637urtw_8225_setgain(struct urtw_softc *sc, int16_t gain)
2638{
2639 usb_error_t error;
2640
2641 urtw_8187_write_phy_ofdm(sc, 0x0d, urtw_8225_gain[gain * 4]);
2642 urtw_8187_write_phy_ofdm(sc, 0x1b, urtw_8225_gain[gain * 4 + 2]);
2643 urtw_8187_write_phy_ofdm(sc, 0x1d, urtw_8225_gain[gain * 4 + 3]);
2644 urtw_8187_write_phy_ofdm(sc, 0x23, urtw_8225_gain[gain * 4 + 1]);
2645fail:
2646 return (error);
2647}
2648
2649static usb_error_t
2650urtw_8225_usb_init(struct urtw_softc *sc)
2651{
2652 uint8_t data;
2653 usb_error_t error;
2654
2655 urtw_write8_m(sc, URTW_RF_PINS_SELECT + 1, 0);
2656 urtw_write8_m(sc, URTW_GPIO, 0);
2657 error = urtw_read8e(sc, 0x53, &data);
2658 if (error)
2659 goto fail;
2660 error = urtw_write8e(sc, 0x53, data | (1 << 7));
2661 if (error)
2662 goto fail;
2663 urtw_write8_m(sc, URTW_RF_PINS_SELECT + 1, 4);
2664 urtw_write8_m(sc, URTW_GPIO, 0x20);
2665 urtw_write8_m(sc, URTW_GP_ENABLE, 0);
2666
2667 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, 0x80);
2668 urtw_write16_m(sc, URTW_RF_PINS_SELECT, 0x80);
2669 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, 0x80);
2670
2671 usb_pause_mtx(&sc->sc_mtx, 500);
2672fail:
2673 return (error);
2674}
2675
2676static usb_error_t
2677urtw_8225_write_c(struct urtw_softc *sc, uint8_t addr, uint16_t data)
2678{
2679 uint16_t d80, d82, d84;
2680 usb_error_t error;
2681
2682 urtw_read16_m(sc, URTW_RF_PINS_OUTPUT, &d80);
2683 d80 &= URTW_RF_PINS_MAGIC1;
2684 urtw_read16_m(sc, URTW_RF_PINS_ENABLE, &d82);
2685 urtw_read16_m(sc, URTW_RF_PINS_SELECT, &d84);
2686 d84 &= URTW_RF_PINS_MAGIC2;
2687 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, d82 | URTW_RF_PINS_MAGIC3);
2688 urtw_write16_m(sc, URTW_RF_PINS_SELECT, d84 | URTW_RF_PINS_MAGIC3);
2689 DELAY(10);
2690
2691 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, d80 | URTW_BB_HOST_BANG_EN);
2692 DELAY(2);
2693 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, d80);
2694 DELAY(10);
2695
2696 error = urtw_8225_write_s16(sc, addr, 0x8225, &data);
2697 if (error != 0)
2698 goto fail;
2699
2700 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, d80 | URTW_BB_HOST_BANG_EN);
2701 DELAY(10);
2702 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, d80 | URTW_BB_HOST_BANG_EN);
2703 urtw_write16_m(sc, URTW_RF_PINS_SELECT, d84);
2704 usb_pause_mtx(&sc->sc_mtx, 2);
2705fail:
2706 return (error);
2707}
2708
|
2748}
2749
2750static usb_error_t
2751urtw_8225_rf_set_chan(struct urtw_softc *sc, int chan)
2752{
2753 usb_error_t error;
2754
2755 error = urtw_8225_set_txpwrlvl(sc, chan);
2756 if (error)
2757 goto fail;
2758 urtw_8225_write(sc, URTW_8225_ADDR_7_MAGIC, urtw_8225_channel[chan]);
2759 usb_pause_mtx(&sc->sc_mtx, 10);
2760fail:
2761 return (error);
2762}
2763
2764static usb_error_t
2765urtw_8225_rf_set_sens(struct urtw_softc *sc, int sens)
2766{
2767 usb_error_t error;
2768
2769 if (sens < 0 || sens > 6)
2770 return -1;
2771
2772 if (sens > 4)
2773 urtw_8225_write(sc,
2774 URTW_8225_ADDR_C_MAGIC, URTW_8225_ADDR_C_DATA_MAGIC1);
2775 else
2776 urtw_8225_write(sc,
2777 URTW_8225_ADDR_C_MAGIC, URTW_8225_ADDR_C_DATA_MAGIC2);
2778
2779 sens = 6 - sens;
2780 error = urtw_8225_setgain(sc, sens);
2781 if (error)
2782 goto fail;
2783
2784 urtw_8187_write_phy_cck(sc, 0x41, urtw_8225_threshold[sens]);
2785
2786fail:
2787 return (error);
2788}
2789
2790static usb_error_t
2791urtw_8225_set_txpwrlvl(struct urtw_softc *sc, int chan)
2792{
2793 int i, idx, set;
2794 uint8_t *cck_pwltable;
2795 uint8_t cck_pwrlvl_max, ofdm_pwrlvl_min, ofdm_pwrlvl_max;
2796 uint8_t cck_pwrlvl = sc->sc_txpwr_cck[chan] & 0xff;
2797 uint8_t ofdm_pwrlvl = sc->sc_txpwr_ofdm[chan] & 0xff;
2798 usb_error_t error;
2799
2800 cck_pwrlvl_max = 11;
2801 ofdm_pwrlvl_max = 25; /* 12 -> 25 */
2802 ofdm_pwrlvl_min = 10;
2803
2804 /* CCK power setting */
2805 cck_pwrlvl = (cck_pwrlvl > cck_pwrlvl_max) ? cck_pwrlvl_max : cck_pwrlvl;
2806 idx = cck_pwrlvl % 6;
2807 set = cck_pwrlvl / 6;
2808 cck_pwltable = (chan == 14) ? urtw_8225_txpwr_cck_ch14 :
2809 urtw_8225_txpwr_cck;
2810
2811 urtw_write8_m(sc, URTW_TX_GAIN_CCK,
2812 urtw_8225_tx_gain_cck_ofdm[set] >> 1);
2813 for (i = 0; i < 8; i++) {
2814 urtw_8187_write_phy_cck(sc, 0x44 + i,
2815 cck_pwltable[idx * 8 + i]);
2816 }
2817 usb_pause_mtx(&sc->sc_mtx, 1);
2818
2819 /* OFDM power setting */
2820 ofdm_pwrlvl = (ofdm_pwrlvl > (ofdm_pwrlvl_max - ofdm_pwrlvl_min)) ?
2821 ofdm_pwrlvl_max : ofdm_pwrlvl + ofdm_pwrlvl_min;
2822 ofdm_pwrlvl = (ofdm_pwrlvl > 35) ? 35 : ofdm_pwrlvl;
2823
2824 idx = ofdm_pwrlvl % 6;
2825 set = ofdm_pwrlvl / 6;
2826
2827 error = urtw_8185_set_anaparam2(sc, URTW_8225_ANAPARAM2_ON);
2828 if (error)
2829 goto fail;
2830 urtw_8187_write_phy_ofdm(sc, 2, 0x42);
2831 urtw_8187_write_phy_ofdm(sc, 6, 0);
2832 urtw_8187_write_phy_ofdm(sc, 8, 0);
2833
2834 urtw_write8_m(sc, URTW_TX_GAIN_OFDM,
2835 urtw_8225_tx_gain_cck_ofdm[set] >> 1);
2836 urtw_8187_write_phy_ofdm(sc, 0x5, urtw_8225_txpwr_ofdm[idx]);
2837 urtw_8187_write_phy_ofdm(sc, 0x7, urtw_8225_txpwr_ofdm[idx]);
2838 usb_pause_mtx(&sc->sc_mtx, 1);
2839fail:
2840 return (error);
2841}
2842
2843
2844static usb_error_t
2845urtw_8225_rf_stop(struct urtw_softc *sc)
2846{
2847 uint8_t data;
2848 usb_error_t error;
2849
2850 urtw_8225_write(sc, 0x4, 0x1f);
2851
2852 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG);
2853 if (error)
2854 goto fail;
2855
2856 urtw_read8_m(sc, URTW_CONFIG3, &data);
2857 urtw_write8_m(sc, URTW_CONFIG3, data | URTW_CONFIG3_ANAPARAM_WRITE);
2858 if (sc->sc_flags & URTW_RTL8187B) {
2859 urtw_write32_m(sc, URTW_ANAPARAM2,
2860 URTW_8187B_8225_ANAPARAM2_OFF);
2861 urtw_write32_m(sc, URTW_ANAPARAM, URTW_8187B_8225_ANAPARAM_OFF);
2862 urtw_write32_m(sc, URTW_ANAPARAM3,
2863 URTW_8187B_8225_ANAPARAM3_OFF);
2864 } else {
2865 urtw_write32_m(sc, URTW_ANAPARAM2, URTW_8225_ANAPARAM2_OFF);
2866 urtw_write32_m(sc, URTW_ANAPARAM, URTW_8225_ANAPARAM_OFF);
2867 }
2868
2869 urtw_write8_m(sc, URTW_CONFIG3, data & ~URTW_CONFIG3_ANAPARAM_WRITE);
2870 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL);
2871 if (error)
2872 goto fail;
2873
2874fail:
2875 return (error);
2876}
2877
2878static usb_error_t
2879urtw_8225v2_rf_init(struct urtw_softc *sc)
2880{
2881#define N(a) ((int)(sizeof(a) / sizeof((a)[0])))
2882 int i;
2883 uint16_t data;
2884 uint32_t data32;
2885 usb_error_t error;
2886
2887 error = urtw_8180_set_anaparam(sc, URTW_8225_ANAPARAM_ON);
2888 if (error)
2889 goto fail;
2890
2891 error = urtw_8225_usb_init(sc);
2892 if (error)
2893 goto fail;
2894
2895 urtw_write32_m(sc, URTW_RF_TIMING, 0x000a8008);
2896 urtw_read16_m(sc, URTW_BRSR, &data); /* XXX ??? */
2897 urtw_write16_m(sc, URTW_BRSR, 0xffff);
2898 urtw_write32_m(sc, URTW_RF_PARA, 0x100044);
2899
2900 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG);
2901 if (error)
2902 goto fail;
2903 urtw_write8_m(sc, URTW_CONFIG3, 0x44);
2904 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL);
2905 if (error)
2906 goto fail;
2907
2908 error = urtw_8185_rf_pins_enable(sc);
2909 if (error)
2910 goto fail;
2911
2912 usb_pause_mtx(&sc->sc_mtx, 500);
2913
2914 for (i = 0; i < N(urtw_8225v2_rf_part1); i++) {
2915 urtw_8225_write(sc, urtw_8225v2_rf_part1[i].reg,
2916 urtw_8225v2_rf_part1[i].val);
2917 }
2918 usb_pause_mtx(&sc->sc_mtx, 50);
2919
2920 urtw_8225_write(sc,
2921 URTW_8225_ADDR_0_MAGIC, URTW_8225_ADDR_0_DATA_MAGIC1);
2922
2923 for (i = 0; i < 95; i++) {
2924 urtw_8225_write(sc, URTW_8225_ADDR_1_MAGIC, (uint8_t)(i + 1));
2925 urtw_8225_write(sc, URTW_8225_ADDR_2_MAGIC,
2926 urtw_8225v2_rxgain[i]);
2927 }
2928
2929 urtw_8225_write(sc,
2930 URTW_8225_ADDR_3_MAGIC, URTW_8225_ADDR_3_DATA_MAGIC1);
2931 urtw_8225_write(sc,
2932 URTW_8225_ADDR_5_MAGIC, URTW_8225_ADDR_5_DATA_MAGIC1);
2933 urtw_8225_write(sc,
2934 URTW_8225_ADDR_0_MAGIC, URTW_8225_ADDR_0_DATA_MAGIC2);
2935 urtw_8225_write(sc,
2936 URTW_8225_ADDR_2_MAGIC, URTW_8225_ADDR_2_DATA_MAGIC1);
2937 usb_pause_mtx(&sc->sc_mtx, 100);
2938 urtw_8225_write(sc,
2939 URTW_8225_ADDR_2_MAGIC, URTW_8225_ADDR_2_DATA_MAGIC2);
2940 usb_pause_mtx(&sc->sc_mtx, 100);
2941
2942 error = urtw_8225_read(sc, URTW_8225_ADDR_6_MAGIC, &data32);
2943 if (error != 0)
2944 goto fail;
2945 if (data32 != URTW_8225_ADDR_6_DATA_MAGIC1)
2946 device_printf(sc->sc_dev, "expect 0xe6!! (0x%x)\n", data32);
2947 if (!(data32 & URTW_8225_ADDR_6_DATA_MAGIC2)) {
2948 urtw_8225_write(sc,
2949 URTW_8225_ADDR_2_MAGIC, URTW_8225_ADDR_2_DATA_MAGIC1);
2950 usb_pause_mtx(&sc->sc_mtx, 100);
2951 urtw_8225_write(sc,
2952 URTW_8225_ADDR_2_MAGIC, URTW_8225_ADDR_2_DATA_MAGIC2);
2953 usb_pause_mtx(&sc->sc_mtx, 50);
2954 error = urtw_8225_read(sc, URTW_8225_ADDR_6_MAGIC, &data32);
2955 if (error != 0)
2956 goto fail;
2957 if (!(data32 & URTW_8225_ADDR_6_DATA_MAGIC2))
2958 device_printf(sc->sc_dev, "RF calibration failed\n");
2959 }
2960 usb_pause_mtx(&sc->sc_mtx, 100);
2961
2962 urtw_8225_write(sc,
2963 URTW_8225_ADDR_0_MAGIC, URTW_8225_ADDR_0_DATA_MAGIC6);
2964 for (i = 0; i < 128; i++) {
2965 urtw_8187_write_phy_ofdm(sc, 0xb, urtw_8225_agc[i]);
2966 urtw_8187_write_phy_ofdm(sc, 0xa, (uint8_t)i + 0x80);
2967 }
2968
2969 for (i = 0; i < N(urtw_8225v2_rf_part2); i++) {
2970 urtw_8187_write_phy_ofdm(sc, urtw_8225v2_rf_part2[i].reg,
2971 urtw_8225v2_rf_part2[i].val);
2972 }
2973
2974 error = urtw_8225v2_setgain(sc, 4);
2975 if (error)
2976 goto fail;
2977
2978 for (i = 0; i < N(urtw_8225v2_rf_part3); i++) {
2979 urtw_8187_write_phy_cck(sc, urtw_8225v2_rf_part3[i].reg,
2980 urtw_8225v2_rf_part3[i].val);
2981 }
2982
2983 urtw_write8_m(sc, URTW_TESTR, 0x0d);
2984
2985 error = urtw_8225v2_set_txpwrlvl(sc, 1);
2986 if (error)
2987 goto fail;
2988
2989 urtw_8187_write_phy_cck(sc, 0x10, 0x9b);
2990 urtw_8187_write_phy_ofdm(sc, 0x26, 0x90);
2991
2992 /* TX ant A, 0x0 for B */
2993 error = urtw_8185_tx_antenna(sc, 0x3);
2994 if (error)
2995 goto fail;
2996 urtw_write32_m(sc, URTW_HSSI_PARA, 0x3dc00002);
2997
2998 error = urtw_8225_rf_set_chan(sc, 1);
2999fail:
3000 return (error);
3001#undef N
3002}
3003
3004static usb_error_t
3005urtw_8225v2_rf_set_chan(struct urtw_softc *sc, int chan)
3006{
3007 usb_error_t error;
3008
3009 error = urtw_8225v2_set_txpwrlvl(sc, chan);
3010 if (error)
3011 goto fail;
3012
3013 urtw_8225_write(sc, URTW_8225_ADDR_7_MAGIC, urtw_8225_channel[chan]);
3014 usb_pause_mtx(&sc->sc_mtx, 10);
3015fail:
3016 return (error);
3017}
3018
3019static usb_error_t
3020urtw_8225_read(struct urtw_softc *sc, uint8_t addr, uint32_t *data)
3021{
3022 int i;
3023 int16_t bit;
3024 uint8_t rlen = 12, wlen = 6;
3025 uint16_t o1, o2, o3, tmp;
3026 uint32_t d2w = ((uint32_t)(addr & 0x1f)) << 27;
3027 uint32_t mask = 0x80000000, value = 0;
3028 usb_error_t error;
3029
3030 urtw_read16_m(sc, URTW_RF_PINS_OUTPUT, &o1);
3031 urtw_read16_m(sc, URTW_RF_PINS_ENABLE, &o2);
3032 urtw_read16_m(sc, URTW_RF_PINS_SELECT, &o3);
3033 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, o2 | URTW_RF_PINS_MAGIC4);
3034 urtw_write16_m(sc, URTW_RF_PINS_SELECT, o3 | URTW_RF_PINS_MAGIC4);
3035 o1 &= ~URTW_RF_PINS_MAGIC4;
3036 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, o1 | URTW_BB_HOST_BANG_EN);
3037 DELAY(5);
3038 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, o1);
3039 DELAY(5);
3040
3041 for (i = 0; i < (wlen / 2); i++, mask = mask >> 1) {
3042 bit = ((d2w & mask) != 0) ? 1 : 0;
3043
3044 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1);
3045 DELAY(2);
3046 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 |
3047 URTW_BB_HOST_BANG_CLK);
3048 DELAY(2);
3049 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 |
3050 URTW_BB_HOST_BANG_CLK);
3051 DELAY(2);
3052 mask = mask >> 1;
3053 if (i == 2)
3054 break;
3055 bit = ((d2w & mask) != 0) ? 1 : 0;
3056 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 |
3057 URTW_BB_HOST_BANG_CLK);
3058 DELAY(2);
3059 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 |
3060 URTW_BB_HOST_BANG_CLK);
3061 DELAY(2);
3062 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1);
3063 DELAY(1);
3064 }
3065 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 | URTW_BB_HOST_BANG_RW |
3066 URTW_BB_HOST_BANG_CLK);
3067 DELAY(2);
3068 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 | URTW_BB_HOST_BANG_RW);
3069 DELAY(2);
3070 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, o1 | URTW_BB_HOST_BANG_RW);
3071 DELAY(2);
3072
3073 mask = 0x800;
3074 for (i = 0; i < rlen; i++, mask = mask >> 1) {
3075 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT,
3076 o1 | URTW_BB_HOST_BANG_RW);
3077 DELAY(2);
3078 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT,
3079 o1 | URTW_BB_HOST_BANG_RW | URTW_BB_HOST_BANG_CLK);
3080 DELAY(2);
3081 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT,
3082 o1 | URTW_BB_HOST_BANG_RW | URTW_BB_HOST_BANG_CLK);
3083 DELAY(2);
3084 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT,
3085 o1 | URTW_BB_HOST_BANG_RW | URTW_BB_HOST_BANG_CLK);
3086 DELAY(2);
3087
3088 urtw_read16_m(sc, URTW_RF_PINS_INPUT, &tmp);
3089 value |= ((tmp & URTW_BB_HOST_BANG_CLK) ? mask : 0);
3090 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT,
3091 o1 | URTW_BB_HOST_BANG_RW);
3092 DELAY(2);
3093 }
3094
3095 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, o1 | URTW_BB_HOST_BANG_EN |
3096 URTW_BB_HOST_BANG_RW);
3097 DELAY(2);
3098
3099 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, o2);
3100 urtw_write16_m(sc, URTW_RF_PINS_SELECT, o3);
3101 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, URTW_RF_PINS_OUTPUT_MAGIC1);
3102
3103 if (data != NULL)
3104 *data = value;
3105fail:
3106 return (error);
3107}
3108
3109
3110static usb_error_t
3111urtw_8225v2_set_txpwrlvl(struct urtw_softc *sc, int chan)
3112{
3113 int i;
3114 uint8_t *cck_pwrtable;
3115 uint8_t cck_pwrlvl_max = 15, ofdm_pwrlvl_max = 25, ofdm_pwrlvl_min = 10;
3116 uint8_t cck_pwrlvl = sc->sc_txpwr_cck[chan] & 0xff;
3117 uint8_t ofdm_pwrlvl = sc->sc_txpwr_ofdm[chan] & 0xff;
3118 usb_error_t error;
3119
3120 /* CCK power setting */
3121 cck_pwrlvl = (cck_pwrlvl > cck_pwrlvl_max) ? cck_pwrlvl_max : cck_pwrlvl;
3122 cck_pwrlvl += sc->sc_txpwr_cck_base;
3123 cck_pwrlvl = (cck_pwrlvl > 35) ? 35 : cck_pwrlvl;
3124 cck_pwrtable = (chan == 14) ? urtw_8225v2_txpwr_cck_ch14 :
3125 urtw_8225v2_txpwr_cck;
3126
3127 for (i = 0; i < 8; i++)
3128 urtw_8187_write_phy_cck(sc, 0x44 + i, cck_pwrtable[i]);
3129
3130 urtw_write8_m(sc, URTW_TX_GAIN_CCK,
3131 urtw_8225v2_tx_gain_cck_ofdm[cck_pwrlvl]);
3132 usb_pause_mtx(&sc->sc_mtx, 1);
3133
3134 /* OFDM power setting */
3135 ofdm_pwrlvl = (ofdm_pwrlvl > (ofdm_pwrlvl_max - ofdm_pwrlvl_min)) ?
3136 ofdm_pwrlvl_max : ofdm_pwrlvl + ofdm_pwrlvl_min;
3137 ofdm_pwrlvl += sc->sc_txpwr_ofdm_base;
3138 ofdm_pwrlvl = (ofdm_pwrlvl > 35) ? 35 : ofdm_pwrlvl;
3139
3140 error = urtw_8185_set_anaparam2(sc, URTW_8225_ANAPARAM2_ON);
3141 if (error)
3142 goto fail;
3143
3144 urtw_8187_write_phy_ofdm(sc, 2, 0x42);
3145 urtw_8187_write_phy_ofdm(sc, 5, 0x0);
3146 urtw_8187_write_phy_ofdm(sc, 6, 0x40);
3147 urtw_8187_write_phy_ofdm(sc, 7, 0x0);
3148 urtw_8187_write_phy_ofdm(sc, 8, 0x40);
3149
3150 urtw_write8_m(sc, URTW_TX_GAIN_OFDM,
3151 urtw_8225v2_tx_gain_cck_ofdm[ofdm_pwrlvl]);
3152 usb_pause_mtx(&sc->sc_mtx, 1);
3153fail:
3154 return (error);
3155}
3156
3157static usb_error_t
3158urtw_8225v2_setgain(struct urtw_softc *sc, int16_t gain)
3159{
3160 uint8_t *gainp;
3161 usb_error_t error;
3162
3163 /* XXX for A? */
3164 gainp = urtw_8225v2_gain_bg;
3165 urtw_8187_write_phy_ofdm(sc, 0x0d, gainp[gain * 3]);
3166 usb_pause_mtx(&sc->sc_mtx, 1);
3167 urtw_8187_write_phy_ofdm(sc, 0x1b, gainp[gain * 3 + 1]);
3168 usb_pause_mtx(&sc->sc_mtx, 1);
3169 urtw_8187_write_phy_ofdm(sc, 0x1d, gainp[gain * 3 + 2]);
3170 usb_pause_mtx(&sc->sc_mtx, 1);
3171 urtw_8187_write_phy_ofdm(sc, 0x21, 0x17);
3172 usb_pause_mtx(&sc->sc_mtx, 1);
3173fail:
3174 return (error);
3175}
3176
3177static usb_error_t
3178urtw_8225_isv2(struct urtw_softc *sc, int *ret)
3179{
3180 uint32_t data;
3181 usb_error_t error;
3182
3183 *ret = 1;
3184
3185 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, URTW_RF_PINS_MAGIC5);
3186 urtw_write16_m(sc, URTW_RF_PINS_SELECT, URTW_RF_PINS_MAGIC5);
3187 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, URTW_RF_PINS_MAGIC5);
3188 usb_pause_mtx(&sc->sc_mtx, 500);
3189
3190 urtw_8225_write(sc, URTW_8225_ADDR_0_MAGIC,
3191 URTW_8225_ADDR_0_DATA_MAGIC1);
3192
3193 error = urtw_8225_read(sc, URTW_8225_ADDR_8_MAGIC, &data);
3194 if (error != 0)
3195 goto fail;
3196 if (data != URTW_8225_ADDR_8_DATA_MAGIC1)
3197 *ret = 0;
3198 else {
3199 error = urtw_8225_read(sc, URTW_8225_ADDR_9_MAGIC, &data);
3200 if (error != 0)
3201 goto fail;
3202 if (data != URTW_8225_ADDR_9_DATA_MAGIC1)
3203 *ret = 0;
3204 }
3205
3206 urtw_8225_write(sc, URTW_8225_ADDR_0_MAGIC,
3207 URTW_8225_ADDR_0_DATA_MAGIC2);
3208fail:
3209 return (error);
3210}
3211
3212static usb_error_t
3213urtw_8225v2b_rf_init(struct urtw_softc *sc)
3214{
3215#define N(a) ((int)(sizeof(a) / sizeof((a)[0])))
3216 int i;
3217 uint8_t data8;
3218 usb_error_t error;
3219
3220 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG);
3221 if (error)
3222 goto fail;
3223
3224 /*
3225 * initialize extra registers on 8187
3226 */
3227 urtw_write16_m(sc, URTW_BRSR_8187B, 0xfff);
3228
3229 /* retry limit */
3230 urtw_read8_m(sc, URTW_CW_CONF, &data8);
3231 data8 |= URTW_CW_CONF_PERPACKET_RETRY;
3232 urtw_write8_m(sc, URTW_CW_CONF, data8);
3233
3234 /* TX AGC */
3235 urtw_read8_m(sc, URTW_TX_AGC_CTL, &data8);
3236 data8 |= URTW_TX_AGC_CTL_PERPACKET_GAIN;
3237 urtw_write8_m(sc, URTW_TX_AGC_CTL, data8);
3238
3239 /* Auto Rate Fallback Control */
3240#define URTW_ARFR 0x1e0
3241 urtw_write16_m(sc, URTW_ARFR, 0xfff);
3242 urtw_read8_m(sc, URTW_RATE_FALLBACK, &data8);
3243 urtw_write8_m(sc, URTW_RATE_FALLBACK,
3244 data8 | URTW_RATE_FALLBACK_ENABLE);
3245
3246 urtw_read8_m(sc, URTW_MSR, &data8);
3247 urtw_write8_m(sc, URTW_MSR, data8 & 0xf3);
3248 urtw_read8_m(sc, URTW_MSR, &data8);
3249 urtw_write8_m(sc, URTW_MSR, data8 | URTW_MSR_LINK_ENEDCA);
3250 urtw_write8_m(sc, URTW_ACM_CONTROL, sc->sc_acmctl);
3251
3252 urtw_write16_m(sc, URTW_ATIM_WND, 2);
3253 urtw_write16_m(sc, URTW_BEACON_INTERVAL, 100);
3254#define URTW_FEMR_FOR_8187B 0x1d4
3255 urtw_write16_m(sc, URTW_FEMR_FOR_8187B, 0xffff);
3256
3257 /* led type */
3258 urtw_read8_m(sc, URTW_CONFIG1, &data8);
3259 data8 = (data8 & 0x3f) | 0x80;
3260 urtw_write8_m(sc, URTW_CONFIG1, data8);
3261
3262 /* applying MAC address again. */
3263 urtw_write32_m(sc, URTW_MAC0, ((uint32_t *)sc->sc_bssid)[0]);
3264 urtw_write16_m(sc, URTW_MAC4, ((uint32_t *)sc->sc_bssid)[1] & 0xffff);
3265
3266 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL);
3267 if (error)
3268 goto fail;
3269
3270 urtw_write8_m(sc, URTW_WPA_CONFIG, 0);
3271
3272 /*
3273 * MAC configuration
3274 */
3275 for (i = 0; i < N(urtw_8225v2b_rf_part1); i++)
3276 urtw_write8_m(sc, urtw_8225v2b_rf_part1[i].reg,
3277 urtw_8225v2b_rf_part1[i].val);
3278 urtw_write16_m(sc, URTW_TID_AC_MAP, 0xfa50);
3279 urtw_write16_m(sc, URTW_INT_MIG, 0x0000);
3280 urtw_write32_m(sc, 0x1f0, 0);
3281 urtw_write32_m(sc, 0x1f4, 0);
3282 urtw_write8_m(sc, 0x1f8, 0);
3283 urtw_write32_m(sc, URTW_RF_TIMING, 0x4001);
3284
3285#define URTW_RFSW_CTRL 0x272
3286 urtw_write16_m(sc, URTW_RFSW_CTRL, 0x569a);
3287
3288 /*
3289 * initialize PHY
3290 */
3291 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG);
3292 if (error)
3293 goto fail;
3294 urtw_read8_m(sc, URTW_CONFIG3, &data8);
3295 urtw_write8_m(sc, URTW_CONFIG3,
3296 data8 | URTW_CONFIG3_ANAPARAM_WRITE);
3297
3298 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL);
3299 if (error)
3300 goto fail;
3301
3302 /* setup RFE initial timing */
3303 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, 0x0480);
3304 urtw_write16_m(sc, URTW_RF_PINS_SELECT, 0x2488);
3305 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, 0x1fff);
3306 usb_pause_mtx(&sc->sc_mtx, 1100);
3307
3308 for (i = 0; i < N(urtw_8225v2b_rf_part0); i++) {
3309 urtw_8225_write(sc, urtw_8225v2b_rf_part0[i].reg,
3310 urtw_8225v2b_rf_part0[i].val);
3311 usb_pause_mtx(&sc->sc_mtx, 1);
3312 }
3313 urtw_8225_write(sc, 0x00, 0x01b7);
3314
3315 for (i = 0; i < 95; i++) {
3316 urtw_8225_write(sc, URTW_8225_ADDR_1_MAGIC, (uint8_t)(i + 1));
3317 usb_pause_mtx(&sc->sc_mtx, 1);
3318 urtw_8225_write(sc, URTW_8225_ADDR_2_MAGIC,
3319 urtw_8225v2b_rxgain[i]);
3320 usb_pause_mtx(&sc->sc_mtx, 1);
3321 }
3322
3323 urtw_8225_write(sc, URTW_8225_ADDR_3_MAGIC, 0x080);
3324 usb_pause_mtx(&sc->sc_mtx, 1);
3325 urtw_8225_write(sc, URTW_8225_ADDR_5_MAGIC, 0x004);
3326 usb_pause_mtx(&sc->sc_mtx, 1);
3327 urtw_8225_write(sc, URTW_8225_ADDR_0_MAGIC, 0x0b7);
3328 usb_pause_mtx(&sc->sc_mtx, 1);
3329 usb_pause_mtx(&sc->sc_mtx, 3000);
3330 urtw_8225_write(sc, URTW_8225_ADDR_2_MAGIC, 0xc4d);
3331 usb_pause_mtx(&sc->sc_mtx, 2000);
3332 urtw_8225_write(sc, URTW_8225_ADDR_2_MAGIC, 0x44d);
3333 usb_pause_mtx(&sc->sc_mtx, 1);
3334 urtw_8225_write(sc, URTW_8225_ADDR_0_MAGIC, 0x2bf);
3335 usb_pause_mtx(&sc->sc_mtx, 1);
3336
3337 urtw_write8_m(sc, URTW_TX_GAIN_CCK, 0x03);
3338 urtw_write8_m(sc, URTW_TX_GAIN_OFDM, 0x07);
3339 urtw_write8_m(sc, URTW_TX_ANTENNA, 0x03);
3340
3341 urtw_8187_write_phy_ofdm(sc, 0x80, 0x12);
3342 for (i = 0; i < 128; i++) {
3343 uint32_t addr, data;
3344
3345 data = (urtw_8225z2_agc[i] << 8) | 0x0000008f;
3346 addr = ((i + 0x80) << 8) | 0x0000008e;
3347
3348 urtw_8187_write_phy_ofdm(sc, data & 0x7f, (data >> 8) & 0xff);
3349 urtw_8187_write_phy_ofdm(sc, addr & 0x7f, (addr >> 8) & 0xff);
3350 urtw_8187_write_phy_ofdm(sc, 0x0e, 0x00);
3351 }
3352 urtw_8187_write_phy_ofdm(sc, 0x80, 0x10);
3353
3354 for (i = 0; i < N(urtw_8225v2b_rf_part2); i++)
3355 urtw_8187_write_phy_ofdm(sc, i, urtw_8225v2b_rf_part2[i].val);
3356
3357 urtw_write32_m(sc, URTW_8187B_AC_VO, (7 << 12) | (3 << 8) | 0x1c);
3358 urtw_write32_m(sc, URTW_8187B_AC_VI, (7 << 12) | (3 << 8) | 0x1c);
3359 urtw_write32_m(sc, URTW_8187B_AC_BE, (7 << 12) | (3 << 8) | 0x1c);
3360 urtw_write32_m(sc, URTW_8187B_AC_BK, (7 << 12) | (3 << 8) | 0x1c);
3361
3362 urtw_8187_write_phy_ofdm(sc, 0x97, 0x46);
3363 urtw_8187_write_phy_ofdm(sc, 0xa4, 0xb6);
3364 urtw_8187_write_phy_ofdm(sc, 0x85, 0xfc);
3365 urtw_8187_write_phy_cck(sc, 0xc1, 0x88);
3366
3367fail:
3368 return (error);
3369#undef N
3370}
3371
3372static usb_error_t
3373urtw_8225v2b_rf_set_chan(struct urtw_softc *sc, int chan)
3374{
3375 usb_error_t error;
3376
3377 error = urtw_8225v2b_set_txpwrlvl(sc, chan);
3378 if (error)
3379 goto fail;
3380
3381 urtw_8225_write(sc, URTW_8225_ADDR_7_MAGIC, urtw_8225_channel[chan]);
3382 usb_pause_mtx(&sc->sc_mtx, 10);
3383fail:
3384 return (error);
3385}
3386
3387static usb_error_t
3388urtw_8225v2b_set_txpwrlvl(struct urtw_softc *sc, int chan)
3389{
3390 int i;
3391 uint8_t *cck_pwrtable;
3392 uint8_t cck_pwrlvl_max = 15;
3393 uint8_t cck_pwrlvl = sc->sc_txpwr_cck[chan] & 0xff;
3394 uint8_t ofdm_pwrlvl = sc->sc_txpwr_ofdm[chan] & 0xff;
3395 usb_error_t error;
3396
3397 /* CCK power setting */
3398 cck_pwrlvl = (cck_pwrlvl > cck_pwrlvl_max) ?
3399 ((sc->sc_flags & URTW_RTL8187B_REV_B) ? cck_pwrlvl_max : 22) :
3400 (cck_pwrlvl + ((sc->sc_flags & URTW_RTL8187B_REV_B) ? 0 : 7));
3401 cck_pwrlvl += sc->sc_txpwr_cck_base;
3402 cck_pwrlvl = (cck_pwrlvl > 35) ? 35 : cck_pwrlvl;
3403 cck_pwrtable = (chan == 14) ? urtw_8225v2b_txpwr_cck_ch14 :
3404 urtw_8225v2b_txpwr_cck;
3405
3406 if (sc->sc_flags & URTW_RTL8187B_REV_B)
3407 cck_pwrtable += (cck_pwrlvl <= 6) ? 0 :
3408 ((cck_pwrlvl <= 11) ? 8 : 16);
3409 else
3410 cck_pwrtable += (cck_pwrlvl <= 5) ? 0 :
3411 ((cck_pwrlvl <= 11) ? 8 : ((cck_pwrlvl <= 17) ? 16 : 24));
3412
3413 for (i = 0; i < 8; i++)
3414 urtw_8187_write_phy_cck(sc, 0x44 + i, cck_pwrtable[i]);
3415
3416 urtw_write8_m(sc, URTW_TX_GAIN_CCK,
3417 urtw_8225v2_tx_gain_cck_ofdm[cck_pwrlvl] << 1);
3418 usb_pause_mtx(&sc->sc_mtx, 1);
3419
3420 /* OFDM power setting */
3421 ofdm_pwrlvl = (ofdm_pwrlvl > 15) ?
3422 ((sc->sc_flags & URTW_RTL8187B_REV_B) ? 17 : 25) :
3423 (ofdm_pwrlvl + ((sc->sc_flags & URTW_RTL8187B_REV_B) ? 2 : 10));
3424 ofdm_pwrlvl += sc->sc_txpwr_ofdm_base;
3425 ofdm_pwrlvl = (ofdm_pwrlvl > 35) ? 35 : ofdm_pwrlvl;
3426
3427 urtw_write8_m(sc, URTW_TX_GAIN_OFDM,
3428 urtw_8225v2_tx_gain_cck_ofdm[ofdm_pwrlvl] << 1);
3429
3430 if (sc->sc_flags & URTW_RTL8187B_REV_B) {
3431 if (ofdm_pwrlvl <= 11) {
3432 urtw_8187_write_phy_ofdm(sc, 0x87, 0x60);
3433 urtw_8187_write_phy_ofdm(sc, 0x89, 0x60);
3434 } else {
3435 urtw_8187_write_phy_ofdm(sc, 0x87, 0x5c);
3436 urtw_8187_write_phy_ofdm(sc, 0x89, 0x5c);
3437 }
3438 } else {
3439 if (ofdm_pwrlvl <= 11) {
3440 urtw_8187_write_phy_ofdm(sc, 0x87, 0x5c);
3441 urtw_8187_write_phy_ofdm(sc, 0x89, 0x5c);
3442 } else if (ofdm_pwrlvl <= 17) {
3443 urtw_8187_write_phy_ofdm(sc, 0x87, 0x54);
3444 urtw_8187_write_phy_ofdm(sc, 0x89, 0x54);
3445 } else {
3446 urtw_8187_write_phy_ofdm(sc, 0x87, 0x50);
3447 urtw_8187_write_phy_ofdm(sc, 0x89, 0x50);
3448 }
3449 }
3450 usb_pause_mtx(&sc->sc_mtx, 1);
3451fail:
3452 return (error);
3453}
3454
3455static usb_error_t
3456urtw_read8e(struct urtw_softc *sc, int val, uint8_t *data)
3457{
3458 struct usb_device_request req;
3459 usb_error_t error;
3460
3461 req.bmRequestType = UT_READ_VENDOR_DEVICE;
3462 req.bRequest = URTW_8187_GETREGS_REQ;
3463 USETW(req.wValue, val | 0xfe00);
3464 USETW(req.wIndex, 0);
3465 USETW(req.wLength, sizeof(uint8_t));
3466
3467 error = urtw_do_request(sc, &req, data);
3468 return (error);
3469}
3470
3471static usb_error_t
3472urtw_write8e(struct urtw_softc *sc, int val, uint8_t data)
3473{
3474 struct usb_device_request req;
3475
3476 req.bmRequestType = UT_WRITE_VENDOR_DEVICE;
3477 req.bRequest = URTW_8187_SETREGS_REQ;
3478 USETW(req.wValue, val | 0xfe00);
3479 USETW(req.wIndex, 0);
3480 USETW(req.wLength, sizeof(uint8_t));
3481
3482 return (urtw_do_request(sc, &req, &data));
3483}
3484
3485static usb_error_t
3486urtw_8180_set_anaparam(struct urtw_softc *sc, uint32_t val)
3487{
3488 uint8_t data;
3489 usb_error_t error;
3490
3491 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG);
3492 if (error)
3493 goto fail;
3494
3495 urtw_read8_m(sc, URTW_CONFIG3, &data);
3496 urtw_write8_m(sc, URTW_CONFIG3, data | URTW_CONFIG3_ANAPARAM_WRITE);
3497 urtw_write32_m(sc, URTW_ANAPARAM, val);
3498 urtw_read8_m(sc, URTW_CONFIG3, &data);
3499 urtw_write8_m(sc, URTW_CONFIG3, data & ~URTW_CONFIG3_ANAPARAM_WRITE);
3500
3501 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL);
3502 if (error)
3503 goto fail;
3504fail:
3505 return (error);
3506}
3507
3508static usb_error_t
3509urtw_8185_set_anaparam2(struct urtw_softc *sc, uint32_t val)
3510{
3511 uint8_t data;
3512 usb_error_t error;
3513
3514 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG);
3515 if (error)
3516 goto fail;
3517
3518 urtw_read8_m(sc, URTW_CONFIG3, &data);
3519 urtw_write8_m(sc, URTW_CONFIG3, data | URTW_CONFIG3_ANAPARAM_WRITE);
3520 urtw_write32_m(sc, URTW_ANAPARAM2, val);
3521 urtw_read8_m(sc, URTW_CONFIG3, &data);
3522 urtw_write8_m(sc, URTW_CONFIG3, data & ~URTW_CONFIG3_ANAPARAM_WRITE);
3523
3524 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL);
3525 if (error)
3526 goto fail;
3527fail:
3528 return (error);
3529}
3530
3531static usb_error_t
3532urtw_intr_enable(struct urtw_softc *sc)
3533{
3534 usb_error_t error;
3535
3536 urtw_write16_m(sc, URTW_INTR_MASK, 0xffff);
3537fail:
3538 return (error);
3539}
3540
3541static usb_error_t
3542urtw_intr_disable(struct urtw_softc *sc)
3543{
3544 usb_error_t error;
3545
3546 urtw_write16_m(sc, URTW_INTR_MASK, 0);
3547fail:
3548 return (error);
3549}
3550
3551static usb_error_t
3552urtw_reset(struct urtw_softc *sc)
3553{
3554 uint8_t data;
3555 usb_error_t error;
3556
3557 error = urtw_8180_set_anaparam(sc, URTW_8225_ANAPARAM_ON);
3558 if (error)
3559 goto fail;
3560 error = urtw_8185_set_anaparam2(sc, URTW_8225_ANAPARAM2_ON);
3561 if (error)
3562 goto fail;
3563
3564 error = urtw_intr_disable(sc);
3565 if (error)
3566 goto fail;
3567 usb_pause_mtx(&sc->sc_mtx, 100);
3568
3569 error = urtw_write8e(sc, 0x18, 0x10);
3570 if (error != 0)
3571 goto fail;
3572 error = urtw_write8e(sc, 0x18, 0x11);
3573 if (error != 0)
3574 goto fail;
3575 error = urtw_write8e(sc, 0x18, 0x00);
3576 if (error != 0)
3577 goto fail;
3578 usb_pause_mtx(&sc->sc_mtx, 100);
3579
3580 urtw_read8_m(sc, URTW_CMD, &data);
3581 data = (data & 0x2) | URTW_CMD_RST;
3582 urtw_write8_m(sc, URTW_CMD, data);
3583 usb_pause_mtx(&sc->sc_mtx, 100);
3584
3585 urtw_read8_m(sc, URTW_CMD, &data);
3586 if (data & URTW_CMD_RST) {
3587 device_printf(sc->sc_dev, "reset timeout\n");
3588 goto fail;
3589 }
3590
3591 error = urtw_set_mode(sc, URTW_EPROM_CMD_LOAD);
3592 if (error)
3593 goto fail;
3594 usb_pause_mtx(&sc->sc_mtx, 100);
3595
3596 error = urtw_8180_set_anaparam(sc, URTW_8225_ANAPARAM_ON);
3597 if (error)
3598 goto fail;
3599 error = urtw_8185_set_anaparam2(sc, URTW_8225_ANAPARAM2_ON);
3600 if (error)
3601 goto fail;
3602fail:
3603 return (error);
3604}
3605
3606static usb_error_t
3607urtw_led_ctl(struct urtw_softc *sc, int mode)
3608{
3609 usb_error_t error = 0;
3610
3611 switch (sc->sc_strategy) {
3612 case URTW_SW_LED_MODE0:
3613 error = urtw_led_mode0(sc, mode);
3614 break;
3615 case URTW_SW_LED_MODE1:
3616 error = urtw_led_mode1(sc, mode);
3617 break;
3618 case URTW_SW_LED_MODE2:
3619 error = urtw_led_mode2(sc, mode);
3620 break;
3621 case URTW_SW_LED_MODE3:
3622 error = urtw_led_mode3(sc, mode);
3623 break;
3624 default:
3625 panic("unsupported LED mode %d\n", sc->sc_strategy);
3626 /* never reach */
3627 }
3628
3629 return (error);
3630}
3631
3632static usb_error_t
3633urtw_led_mode0(struct urtw_softc *sc, int mode)
3634{
3635
3636 switch (mode) {
3637 case URTW_LED_CTL_POWER_ON:
3638 sc->sc_gpio_ledstate = URTW_LED_POWER_ON_BLINK;
3639 break;
3640 case URTW_LED_CTL_TX:
3641 if (sc->sc_gpio_ledinprogress == 1)
3642 return (0);
3643
3644 sc->sc_gpio_ledstate = URTW_LED_BLINK_NORMAL;
3645 sc->sc_gpio_blinktime = 2;
3646 break;
3647 case URTW_LED_CTL_LINK:
3648 sc->sc_gpio_ledstate = URTW_LED_ON;
3649 break;
3650 default:
3651 panic("unsupported LED mode 0x%x", mode);
3652 /* never reach */
3653 }
3654
3655 switch (sc->sc_gpio_ledstate) {
3656 case URTW_LED_ON:
3657 if (sc->sc_gpio_ledinprogress != 0)
3658 break;
3659 urtw_led_on(sc, URTW_LED_GPIO);
3660 break;
3661 case URTW_LED_BLINK_NORMAL:
3662 if (sc->sc_gpio_ledinprogress != 0)
3663 break;
3664 sc->sc_gpio_ledinprogress = 1;
3665 sc->sc_gpio_blinkstate = (sc->sc_gpio_ledon != 0) ?
3666 URTW_LED_OFF : URTW_LED_ON;
3667 usb_callout_reset(&sc->sc_led_ch, hz, urtw_led_ch, sc);
3668 break;
3669 case URTW_LED_POWER_ON_BLINK:
3670 urtw_led_on(sc, URTW_LED_GPIO);
3671 usb_pause_mtx(&sc->sc_mtx, 100);
3672 urtw_led_off(sc, URTW_LED_GPIO);
3673 break;
3674 default:
3675 panic("unknown LED status 0x%x", sc->sc_gpio_ledstate);
3676 /* never reach */
3677 }
3678 return (0);
3679}
3680
3681static usb_error_t
3682urtw_led_mode1(struct urtw_softc *sc, int mode)
3683{
3684
3685 return (USB_ERR_INVAL);
3686}
3687
3688static usb_error_t
3689urtw_led_mode2(struct urtw_softc *sc, int mode)
3690{
3691
3692 return (USB_ERR_INVAL);
3693}
3694
3695static usb_error_t
3696urtw_led_mode3(struct urtw_softc *sc, int mode)
3697{
3698
3699 return (USB_ERR_INVAL);
3700}
3701
3702static usb_error_t
3703urtw_led_on(struct urtw_softc *sc, int type)
3704{
3705 usb_error_t error;
3706
3707 if (type == URTW_LED_GPIO) {
3708 switch (sc->sc_gpio_ledpin) {
3709 case URTW_LED_PIN_GPIO0:
3710 urtw_write8_m(sc, URTW_GPIO, 0x01);
3711 urtw_write8_m(sc, URTW_GP_ENABLE, 0x00);
3712 break;
3713 default:
3714 panic("unsupported LED PIN type 0x%x",
3715 sc->sc_gpio_ledpin);
3716 /* never reach */
3717 }
3718 } else {
3719 panic("unsupported LED type 0x%x", type);
3720 /* never reach */
3721 }
3722
3723 sc->sc_gpio_ledon = 1;
3724fail:
3725 return (error);
3726}
3727
3728static usb_error_t
3729urtw_led_off(struct urtw_softc *sc, int type)
3730{
3731 usb_error_t error;
3732
3733 if (type == URTW_LED_GPIO) {
3734 switch (sc->sc_gpio_ledpin) {
3735 case URTW_LED_PIN_GPIO0:
3736 urtw_write8_m(sc, URTW_GPIO, URTW_GPIO_DATA_MAGIC1);
3737 urtw_write8_m(sc,
3738 URTW_GP_ENABLE, URTW_GP_ENABLE_DATA_MAGIC1);
3739 break;
3740 default:
3741 panic("unsupported LED PIN type 0x%x",
3742 sc->sc_gpio_ledpin);
3743 /* never reach */
3744 }
3745 } else {
3746 panic("unsupported LED type 0x%x", type);
3747 /* never reach */
3748 }
3749
3750 sc->sc_gpio_ledon = 0;
3751
3752fail:
3753 return (error);
3754}
3755
3756static void
3757urtw_led_ch(void *arg)
3758{
3759 struct urtw_softc *sc = arg;
3760 struct ifnet *ifp = sc->sc_ifp;
3761 struct ieee80211com *ic = ifp->if_l2com;
3762
3763 ieee80211_runtask(ic, &sc->sc_led_task);
3764}
3765
3766static void
3767urtw_ledtask(void *arg, int pending)
3768{
3769 struct urtw_softc *sc = arg;
3770
3771 if (sc->sc_strategy != URTW_SW_LED_MODE0)
3772 panic("could not process a LED strategy 0x%x", sc->sc_strategy);
3773
3774 URTW_LOCK(sc);
3775 urtw_led_blink(sc);
3776 URTW_UNLOCK(sc);
3777}
3778
3779static usb_error_t
3780urtw_led_blink(struct urtw_softc *sc)
3781{
3782 uint8_t ing = 0;
3783 usb_error_t error;
3784
3785 if (sc->sc_gpio_blinkstate == URTW_LED_ON)
3786 error = urtw_led_on(sc, URTW_LED_GPIO);
3787 else
3788 error = urtw_led_off(sc, URTW_LED_GPIO);
3789 sc->sc_gpio_blinktime--;
3790 if (sc->sc_gpio_blinktime == 0)
3791 ing = 1;
3792 else {
3793 if (sc->sc_gpio_ledstate != URTW_LED_BLINK_NORMAL &&
3794 sc->sc_gpio_ledstate != URTW_LED_BLINK_SLOWLY &&
3795 sc->sc_gpio_ledstate != URTW_LED_BLINK_CM3)
3796 ing = 1;
3797 }
3798 if (ing == 1) {
3799 if (sc->sc_gpio_ledstate == URTW_LED_ON &&
3800 sc->sc_gpio_ledon == 0)
3801 error = urtw_led_on(sc, URTW_LED_GPIO);
3802 else if (sc->sc_gpio_ledstate == URTW_LED_OFF &&
3803 sc->sc_gpio_ledon == 1)
3804 error = urtw_led_off(sc, URTW_LED_GPIO);
3805
3806 sc->sc_gpio_blinktime = 0;
3807 sc->sc_gpio_ledinprogress = 0;
3808 return (0);
3809 }
3810
3811 sc->sc_gpio_blinkstate = (sc->sc_gpio_blinkstate != URTW_LED_ON) ?
3812 URTW_LED_ON : URTW_LED_OFF;
3813
3814 switch (sc->sc_gpio_ledstate) {
3815 case URTW_LED_BLINK_NORMAL:
3816 usb_callout_reset(&sc->sc_led_ch, hz, urtw_led_ch, sc);
3817 break;
3818 default:
3819 panic("unknown LED status 0x%x", sc->sc_gpio_ledstate);
3820 /* never reach */
3821 }
3822 return (0);
3823}
3824
3825static usb_error_t
3826urtw_rx_enable(struct urtw_softc *sc)
3827{
3828 uint8_t data;
3829 usb_error_t error;
3830
3831 usbd_transfer_start((sc->sc_flags & URTW_RTL8187B) ?
3832 sc->sc_xfer[URTW_8187B_BULK_RX] : sc->sc_xfer[URTW_8187L_BULK_RX]);
3833
3834 error = urtw_rx_setconf(sc);
3835 if (error != 0)
3836 goto fail;
3837
3838 if ((sc->sc_flags & URTW_RTL8187B) == 0) {
3839 urtw_read8_m(sc, URTW_CMD, &data);
3840 urtw_write8_m(sc, URTW_CMD, data | URTW_CMD_RX_ENABLE);
3841 }
3842fail:
3843 return (error);
3844}
3845
3846static usb_error_t
3847urtw_tx_enable(struct urtw_softc *sc)
3848{
3849 uint8_t data8;
3850 uint32_t data;
3851 usb_error_t error;
3852
3853 if (sc->sc_flags & URTW_RTL8187B) {
3854 urtw_read32_m(sc, URTW_TX_CONF, &data);
3855 data &= ~URTW_TX_LOOPBACK_MASK;
3856 data &= ~(URTW_TX_DPRETRY_MASK | URTW_TX_RTSRETRY_MASK);
3857 data &= ~(URTW_TX_NOCRC | URTW_TX_MXDMA_MASK);
3858 data &= ~URTW_TX_SWPLCPLEN;
3859 data |= URTW_TX_HW_SEQNUM | URTW_TX_DISREQQSIZE |
3860 (7 << 8) | /* short retry limit */
3861 (7 << 0) | /* long retry limit */
3862 (7 << 21); /* MAX TX DMA */
3863 urtw_write32_m(sc, URTW_TX_CONF, data);
3864
3865 urtw_read8_m(sc, URTW_MSR, &data8);
3866 data8 |= URTW_MSR_LINK_ENEDCA;
3867 urtw_write8_m(sc, URTW_MSR, data8);
3868 return (error);
3869 }
3870
3871 urtw_read8_m(sc, URTW_CW_CONF, &data8);
3872 data8 &= ~(URTW_CW_CONF_PERPACKET_CW | URTW_CW_CONF_PERPACKET_RETRY);
3873 urtw_write8_m(sc, URTW_CW_CONF, data8);
3874
3875 urtw_read8_m(sc, URTW_TX_AGC_CTL, &data8);
3876 data8 &= ~URTW_TX_AGC_CTL_PERPACKET_GAIN;
3877 data8 &= ~URTW_TX_AGC_CTL_PERPACKET_ANTSEL;
3878 data8 &= ~URTW_TX_AGC_CTL_FEEDBACK_ANT;
3879 urtw_write8_m(sc, URTW_TX_AGC_CTL, data8);
3880
3881 urtw_read32_m(sc, URTW_TX_CONF, &data);
3882 data &= ~URTW_TX_LOOPBACK_MASK;
3883 data |= URTW_TX_LOOPBACK_NONE;
3884 data &= ~(URTW_TX_DPRETRY_MASK | URTW_TX_RTSRETRY_MASK);
3885 data |= sc->sc_tx_retry << URTW_TX_DPRETRY_SHIFT;
3886 data |= sc->sc_rts_retry << URTW_TX_RTSRETRY_SHIFT;
3887 data &= ~(URTW_TX_NOCRC | URTW_TX_MXDMA_MASK);
3888 data |= URTW_TX_MXDMA_2048 | URTW_TX_CWMIN | URTW_TX_DISCW;
3889 data &= ~URTW_TX_SWPLCPLEN;
3890 data |= URTW_TX_NOICV;
3891 urtw_write32_m(sc, URTW_TX_CONF, data);
3892
3893 urtw_read8_m(sc, URTW_CMD, &data8);
3894 urtw_write8_m(sc, URTW_CMD, data8 | URTW_CMD_TX_ENABLE);
3895fail:
3896 return (error);
3897}
3898
3899static usb_error_t
3900urtw_rx_setconf(struct urtw_softc *sc)
3901{
3902 struct ifnet *ifp = sc->sc_ifp;
3903 struct ieee80211com *ic = ifp->if_l2com;
3904 uint32_t data;
3905 usb_error_t error;
3906
3907 urtw_read32_m(sc, URTW_RX, &data);
3908 data = data &~ URTW_RX_FILTER_MASK;
3909 if (sc->sc_flags & URTW_RTL8187B) {
3910 data = data | URTW_RX_FILTER_MNG | URTW_RX_FILTER_DATA |
3911 URTW_RX_FILTER_MCAST | URTW_RX_FILTER_BCAST |
3912 URTW_RX_FILTER_NICMAC | URTW_RX_CHECK_BSSID |
3913 URTW_RX_FIFO_THRESHOLD_NONE |
3914 URTW_MAX_RX_DMA_2048 |
3915 URTW_RX_AUTORESETPHY | URTW_RCR_ONLYERLPKT;
3916 } else {
3917 data = data | URTW_RX_FILTER_MNG | URTW_RX_FILTER_DATA;
3918 data = data | URTW_RX_FILTER_BCAST | URTW_RX_FILTER_MCAST;
3919
3920 if (ic->ic_opmode == IEEE80211_M_MONITOR) {
3921 data = data | URTW_RX_FILTER_ICVERR;
3922 data = data | URTW_RX_FILTER_PWR;
3923 }
3924 if (sc->sc_crcmon == 1 && ic->ic_opmode == IEEE80211_M_MONITOR)
3925 data = data | URTW_RX_FILTER_CRCERR;
3926
3927 if (ic->ic_opmode == IEEE80211_M_MONITOR ||
3928 (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC))) {
3929 data = data | URTW_RX_FILTER_ALLMAC;
3930 } else {
3931 data = data | URTW_RX_FILTER_NICMAC;
3932 data = data | URTW_RX_CHECK_BSSID;
3933 }
3934
3935 data = data &~ URTW_RX_FIFO_THRESHOLD_MASK;
3936 data = data | URTW_RX_FIFO_THRESHOLD_NONE |
3937 URTW_RX_AUTORESETPHY;
3938 data = data &~ URTW_MAX_RX_DMA_MASK;
3939 data = data | URTW_MAX_RX_DMA_2048 | URTW_RCR_ONLYERLPKT;
3940 }
3941
3942 urtw_write32_m(sc, URTW_RX, data);
3943fail:
3944 return (error);
3945}
3946
3947static struct mbuf *
3948urtw_rxeof(struct usb_xfer *xfer, struct urtw_data *data, int *rssi_p,
3949 int8_t *nf_p)
3950{
3951 int actlen, flen, rssi;
3952 struct ieee80211_frame *wh;
3953 struct mbuf *m, *mnew;
3954 struct urtw_softc *sc = data->sc;
3955 struct ifnet *ifp = sc->sc_ifp;
3956 struct ieee80211com *ic = ifp->if_l2com;
3957 uint8_t noise = 0, rate;
3958
3959 usbd_xfer_status(xfer, &actlen, NULL, NULL, NULL);
3960
3961 if (actlen < (int)URTW_MIN_RXBUFSZ) {
3962 ifp->if_ierrors++;
3963 return (NULL);
3964 }
3965
3966 if (sc->sc_flags & URTW_RTL8187B) {
3967 struct urtw_8187b_rxhdr *rx;
3968
3969 rx = (struct urtw_8187b_rxhdr *)(data->buf +
3970 (actlen - (sizeof(struct urtw_8187b_rxhdr))));
3971 flen = le32toh(rx->flag) & 0xfff;
3972 if (flen > actlen) {
3973 ifp->if_ierrors++;
3974 return (NULL);
3975 }
3976 rate = (le32toh(rx->flag) >> URTW_RX_FLAG_RXRATE_SHIFT) & 0xf;
3977 /* XXX correct? */
3978 rssi = rx->rssi & URTW_RX_RSSI_MASK;
3979 noise = rx->noise;
3980 } else {
3981 struct urtw_8187l_rxhdr *rx;
3982
3983 rx = (struct urtw_8187l_rxhdr *)(data->buf +
3984 (actlen - (sizeof(struct urtw_8187l_rxhdr))));
3985 flen = le32toh(rx->flag) & 0xfff;
3986 if (flen > actlen) {
3987 ifp->if_ierrors++;
3988 return (NULL);
3989 }
3990
3991 rate = (le32toh(rx->flag) >> URTW_RX_FLAG_RXRATE_SHIFT) & 0xf;
3992 /* XXX correct? */
3993 rssi = rx->rssi & URTW_RX_8187L_RSSI_MASK;
3994 noise = rx->noise;
3995 }
3996
3997 mnew = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
3998 if (mnew == NULL) {
3999 ifp->if_ierrors++;
4000 return (NULL);
4001 }
4002
4003 m = data->m;
4004 data->m = mnew;
4005 data->buf = mtod(mnew, uint8_t *);
4006
4007 /* finalize mbuf */
4008 m->m_pkthdr.rcvif = ifp;
4009 m->m_pkthdr.len = m->m_len = flen - IEEE80211_CRC_LEN;
4010
4011 if (ieee80211_radiotap_active(ic)) {
4012 struct urtw_rx_radiotap_header *tap = &sc->sc_rxtap;
4013
4014 /* XXX Are variables correct? */
4015 tap->wr_chan_freq = htole16(ic->ic_curchan->ic_freq);
4016 tap->wr_chan_flags = htole16(ic->ic_curchan->ic_flags);
4017 tap->wr_dbm_antsignal = (int8_t)rssi;
4018 }
4019
4020 wh = mtod(m, struct ieee80211_frame *);
4021 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) == IEEE80211_FC0_TYPE_DATA)
4022 sc->sc_currate = (rate > 0) ? rate : sc->sc_currate;
4023
4024 *rssi_p = rssi;
4025 *nf_p = noise; /* XXX correct? */
4026
4027 return (m);
4028}
4029
4030static void
4031urtw_bulk_rx_callback(struct usb_xfer *xfer, usb_error_t error)
4032{
4033 struct urtw_softc *sc = usbd_xfer_softc(xfer);
4034 struct ifnet *ifp = sc->sc_ifp;
4035 struct ieee80211com *ic = ifp->if_l2com;
4036 struct ieee80211_frame *wh;
4037 struct ieee80211_node *ni;
4038 struct mbuf *m = NULL;
4039 struct urtw_data *data;
4040 int8_t nf = -95;
4041 int rssi = 1;
4042
4043 URTW_ASSERT_LOCKED(sc);
4044
4045 switch (USB_GET_STATE(xfer)) {
4046 case USB_ST_TRANSFERRED:
4047 data = STAILQ_FIRST(&sc->sc_rx_active);
4048 if (data == NULL)
4049 goto setup;
4050 STAILQ_REMOVE_HEAD(&sc->sc_rx_active, next);
4051 m = urtw_rxeof(xfer, data, &rssi, &nf);
4052 STAILQ_INSERT_TAIL(&sc->sc_rx_inactive, data, next);
4053 /* FALLTHROUGH */
4054 case USB_ST_SETUP:
4055setup:
4056 data = STAILQ_FIRST(&sc->sc_rx_inactive);
4057 if (data == NULL) {
4058 KASSERT(m == NULL, ("mbuf isn't NULL"));
4059 return;
4060 }
4061 STAILQ_REMOVE_HEAD(&sc->sc_rx_inactive, next);
4062 STAILQ_INSERT_TAIL(&sc->sc_rx_active, data, next);
4063 usbd_xfer_set_frame_data(xfer, 0, data->buf,
4064 usbd_xfer_max_len(xfer));
4065 usbd_transfer_submit(xfer);
4066
4067 /*
4068 * To avoid LOR we should unlock our private mutex here to call
4069 * ieee80211_input() because here is at the end of a USB
4070 * callback and safe to unlock.
4071 */
4072 URTW_UNLOCK(sc);
4073 if (m != NULL) {
4074 wh = mtod(m, struct ieee80211_frame *);
4075 ni = ieee80211_find_rxnode(ic,
4076 (struct ieee80211_frame_min *)wh);
4077 if (ni != NULL) {
4078 (void) ieee80211_input(ni, m, rssi, nf);
4079 /* node is no longer needed */
4080 ieee80211_free_node(ni);
4081 } else
4082 (void) ieee80211_input_all(ic, m, rssi, nf);
4083 m = NULL;
4084 }
4085 URTW_LOCK(sc);
4086 break;
4087 default:
4088 /* needs it to the inactive queue due to a error. */
4089 data = STAILQ_FIRST(&sc->sc_rx_active);
4090 if (data != NULL) {
4091 STAILQ_REMOVE_HEAD(&sc->sc_rx_active, next);
4092 STAILQ_INSERT_TAIL(&sc->sc_rx_inactive, data, next);
4093 }
4094 if (error != USB_ERR_CANCELLED) {
4095 usbd_xfer_set_stall(xfer);
4096 ifp->if_ierrors++;
4097 goto setup;
4098 }
4099 break;
4100 }
4101}
4102
4103#define URTW_STATUS_TYPE_TXCLOSE 1
4104#define URTW_STATUS_TYPE_BEACON_INTR 0
4105
4106static void
4107urtw_txstatus_eof(struct usb_xfer *xfer)
4108{
4109 struct urtw_softc *sc = usbd_xfer_softc(xfer);
4110 struct ifnet *ifp = sc->sc_ifp;
4111 int actlen, type, pktretry, seq;
4112 uint64_t val;
4113
4114 usbd_xfer_status(xfer, &actlen, NULL, NULL, NULL);
4115
4116 if (actlen != sizeof(uint64_t))
4117 return;
4118
4119 val = le64toh(sc->sc_txstatus);
4120 type = (val >> 30) & 0x3;
4121 if (type == URTW_STATUS_TYPE_TXCLOSE) {
4122 pktretry = val & 0xff;
4123 seq = (val >> 16) & 0xff;
4124 if (pktretry == URTW_TX_MAXRETRY)
4125 ifp->if_oerrors++;
4126 DPRINTF(sc, URTW_DEBUG_TXSTATUS, "pktretry %d seq %#x\n",
4127 pktretry, seq);
4128 }
4129}
4130
4131static void
4132urtw_bulk_tx_status_callback(struct usb_xfer *xfer, usb_error_t error)
4133{
4134 struct urtw_softc *sc = usbd_xfer_softc(xfer);
4135 struct ifnet *ifp = sc->sc_ifp;
| 2731}
2732
2733static usb_error_t
2734urtw_8225_rf_set_chan(struct urtw_softc *sc, int chan)
2735{
2736 usb_error_t error;
2737
2738 error = urtw_8225_set_txpwrlvl(sc, chan);
2739 if (error)
2740 goto fail;
2741 urtw_8225_write(sc, URTW_8225_ADDR_7_MAGIC, urtw_8225_channel[chan]);
2742 usb_pause_mtx(&sc->sc_mtx, 10);
2743fail:
2744 return (error);
2745}
2746
2747static usb_error_t
2748urtw_8225_rf_set_sens(struct urtw_softc *sc, int sens)
2749{
2750 usb_error_t error;
2751
2752 if (sens < 0 || sens > 6)
2753 return -1;
2754
2755 if (sens > 4)
2756 urtw_8225_write(sc,
2757 URTW_8225_ADDR_C_MAGIC, URTW_8225_ADDR_C_DATA_MAGIC1);
2758 else
2759 urtw_8225_write(sc,
2760 URTW_8225_ADDR_C_MAGIC, URTW_8225_ADDR_C_DATA_MAGIC2);
2761
2762 sens = 6 - sens;
2763 error = urtw_8225_setgain(sc, sens);
2764 if (error)
2765 goto fail;
2766
2767 urtw_8187_write_phy_cck(sc, 0x41, urtw_8225_threshold[sens]);
2768
2769fail:
2770 return (error);
2771}
2772
2773static usb_error_t
2774urtw_8225_set_txpwrlvl(struct urtw_softc *sc, int chan)
2775{
2776 int i, idx, set;
2777 uint8_t *cck_pwltable;
2778 uint8_t cck_pwrlvl_max, ofdm_pwrlvl_min, ofdm_pwrlvl_max;
2779 uint8_t cck_pwrlvl = sc->sc_txpwr_cck[chan] & 0xff;
2780 uint8_t ofdm_pwrlvl = sc->sc_txpwr_ofdm[chan] & 0xff;
2781 usb_error_t error;
2782
2783 cck_pwrlvl_max = 11;
2784 ofdm_pwrlvl_max = 25; /* 12 -> 25 */
2785 ofdm_pwrlvl_min = 10;
2786
2787 /* CCK power setting */
2788 cck_pwrlvl = (cck_pwrlvl > cck_pwrlvl_max) ? cck_pwrlvl_max : cck_pwrlvl;
2789 idx = cck_pwrlvl % 6;
2790 set = cck_pwrlvl / 6;
2791 cck_pwltable = (chan == 14) ? urtw_8225_txpwr_cck_ch14 :
2792 urtw_8225_txpwr_cck;
2793
2794 urtw_write8_m(sc, URTW_TX_GAIN_CCK,
2795 urtw_8225_tx_gain_cck_ofdm[set] >> 1);
2796 for (i = 0; i < 8; i++) {
2797 urtw_8187_write_phy_cck(sc, 0x44 + i,
2798 cck_pwltable[idx * 8 + i]);
2799 }
2800 usb_pause_mtx(&sc->sc_mtx, 1);
2801
2802 /* OFDM power setting */
2803 ofdm_pwrlvl = (ofdm_pwrlvl > (ofdm_pwrlvl_max - ofdm_pwrlvl_min)) ?
2804 ofdm_pwrlvl_max : ofdm_pwrlvl + ofdm_pwrlvl_min;
2805 ofdm_pwrlvl = (ofdm_pwrlvl > 35) ? 35 : ofdm_pwrlvl;
2806
2807 idx = ofdm_pwrlvl % 6;
2808 set = ofdm_pwrlvl / 6;
2809
2810 error = urtw_8185_set_anaparam2(sc, URTW_8225_ANAPARAM2_ON);
2811 if (error)
2812 goto fail;
2813 urtw_8187_write_phy_ofdm(sc, 2, 0x42);
2814 urtw_8187_write_phy_ofdm(sc, 6, 0);
2815 urtw_8187_write_phy_ofdm(sc, 8, 0);
2816
2817 urtw_write8_m(sc, URTW_TX_GAIN_OFDM,
2818 urtw_8225_tx_gain_cck_ofdm[set] >> 1);
2819 urtw_8187_write_phy_ofdm(sc, 0x5, urtw_8225_txpwr_ofdm[idx]);
2820 urtw_8187_write_phy_ofdm(sc, 0x7, urtw_8225_txpwr_ofdm[idx]);
2821 usb_pause_mtx(&sc->sc_mtx, 1);
2822fail:
2823 return (error);
2824}
2825
2826
2827static usb_error_t
2828urtw_8225_rf_stop(struct urtw_softc *sc)
2829{
2830 uint8_t data;
2831 usb_error_t error;
2832
2833 urtw_8225_write(sc, 0x4, 0x1f);
2834
2835 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG);
2836 if (error)
2837 goto fail;
2838
2839 urtw_read8_m(sc, URTW_CONFIG3, &data);
2840 urtw_write8_m(sc, URTW_CONFIG3, data | URTW_CONFIG3_ANAPARAM_WRITE);
2841 if (sc->sc_flags & URTW_RTL8187B) {
2842 urtw_write32_m(sc, URTW_ANAPARAM2,
2843 URTW_8187B_8225_ANAPARAM2_OFF);
2844 urtw_write32_m(sc, URTW_ANAPARAM, URTW_8187B_8225_ANAPARAM_OFF);
2845 urtw_write32_m(sc, URTW_ANAPARAM3,
2846 URTW_8187B_8225_ANAPARAM3_OFF);
2847 } else {
2848 urtw_write32_m(sc, URTW_ANAPARAM2, URTW_8225_ANAPARAM2_OFF);
2849 urtw_write32_m(sc, URTW_ANAPARAM, URTW_8225_ANAPARAM_OFF);
2850 }
2851
2852 urtw_write8_m(sc, URTW_CONFIG3, data & ~URTW_CONFIG3_ANAPARAM_WRITE);
2853 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL);
2854 if (error)
2855 goto fail;
2856
2857fail:
2858 return (error);
2859}
2860
2861static usb_error_t
2862urtw_8225v2_rf_init(struct urtw_softc *sc)
2863{
2864#define N(a) ((int)(sizeof(a) / sizeof((a)[0])))
2865 int i;
2866 uint16_t data;
2867 uint32_t data32;
2868 usb_error_t error;
2869
2870 error = urtw_8180_set_anaparam(sc, URTW_8225_ANAPARAM_ON);
2871 if (error)
2872 goto fail;
2873
2874 error = urtw_8225_usb_init(sc);
2875 if (error)
2876 goto fail;
2877
2878 urtw_write32_m(sc, URTW_RF_TIMING, 0x000a8008);
2879 urtw_read16_m(sc, URTW_BRSR, &data); /* XXX ??? */
2880 urtw_write16_m(sc, URTW_BRSR, 0xffff);
2881 urtw_write32_m(sc, URTW_RF_PARA, 0x100044);
2882
2883 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG);
2884 if (error)
2885 goto fail;
2886 urtw_write8_m(sc, URTW_CONFIG3, 0x44);
2887 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL);
2888 if (error)
2889 goto fail;
2890
2891 error = urtw_8185_rf_pins_enable(sc);
2892 if (error)
2893 goto fail;
2894
2895 usb_pause_mtx(&sc->sc_mtx, 500);
2896
2897 for (i = 0; i < N(urtw_8225v2_rf_part1); i++) {
2898 urtw_8225_write(sc, urtw_8225v2_rf_part1[i].reg,
2899 urtw_8225v2_rf_part1[i].val);
2900 }
2901 usb_pause_mtx(&sc->sc_mtx, 50);
2902
2903 urtw_8225_write(sc,
2904 URTW_8225_ADDR_0_MAGIC, URTW_8225_ADDR_0_DATA_MAGIC1);
2905
2906 for (i = 0; i < 95; i++) {
2907 urtw_8225_write(sc, URTW_8225_ADDR_1_MAGIC, (uint8_t)(i + 1));
2908 urtw_8225_write(sc, URTW_8225_ADDR_2_MAGIC,
2909 urtw_8225v2_rxgain[i]);
2910 }
2911
2912 urtw_8225_write(sc,
2913 URTW_8225_ADDR_3_MAGIC, URTW_8225_ADDR_3_DATA_MAGIC1);
2914 urtw_8225_write(sc,
2915 URTW_8225_ADDR_5_MAGIC, URTW_8225_ADDR_5_DATA_MAGIC1);
2916 urtw_8225_write(sc,
2917 URTW_8225_ADDR_0_MAGIC, URTW_8225_ADDR_0_DATA_MAGIC2);
2918 urtw_8225_write(sc,
2919 URTW_8225_ADDR_2_MAGIC, URTW_8225_ADDR_2_DATA_MAGIC1);
2920 usb_pause_mtx(&sc->sc_mtx, 100);
2921 urtw_8225_write(sc,
2922 URTW_8225_ADDR_2_MAGIC, URTW_8225_ADDR_2_DATA_MAGIC2);
2923 usb_pause_mtx(&sc->sc_mtx, 100);
2924
2925 error = urtw_8225_read(sc, URTW_8225_ADDR_6_MAGIC, &data32);
2926 if (error != 0)
2927 goto fail;
2928 if (data32 != URTW_8225_ADDR_6_DATA_MAGIC1)
2929 device_printf(sc->sc_dev, "expect 0xe6!! (0x%x)\n", data32);
2930 if (!(data32 & URTW_8225_ADDR_6_DATA_MAGIC2)) {
2931 urtw_8225_write(sc,
2932 URTW_8225_ADDR_2_MAGIC, URTW_8225_ADDR_2_DATA_MAGIC1);
2933 usb_pause_mtx(&sc->sc_mtx, 100);
2934 urtw_8225_write(sc,
2935 URTW_8225_ADDR_2_MAGIC, URTW_8225_ADDR_2_DATA_MAGIC2);
2936 usb_pause_mtx(&sc->sc_mtx, 50);
2937 error = urtw_8225_read(sc, URTW_8225_ADDR_6_MAGIC, &data32);
2938 if (error != 0)
2939 goto fail;
2940 if (!(data32 & URTW_8225_ADDR_6_DATA_MAGIC2))
2941 device_printf(sc->sc_dev, "RF calibration failed\n");
2942 }
2943 usb_pause_mtx(&sc->sc_mtx, 100);
2944
2945 urtw_8225_write(sc,
2946 URTW_8225_ADDR_0_MAGIC, URTW_8225_ADDR_0_DATA_MAGIC6);
2947 for (i = 0; i < 128; i++) {
2948 urtw_8187_write_phy_ofdm(sc, 0xb, urtw_8225_agc[i]);
2949 urtw_8187_write_phy_ofdm(sc, 0xa, (uint8_t)i + 0x80);
2950 }
2951
2952 for (i = 0; i < N(urtw_8225v2_rf_part2); i++) {
2953 urtw_8187_write_phy_ofdm(sc, urtw_8225v2_rf_part2[i].reg,
2954 urtw_8225v2_rf_part2[i].val);
2955 }
2956
2957 error = urtw_8225v2_setgain(sc, 4);
2958 if (error)
2959 goto fail;
2960
2961 for (i = 0; i < N(urtw_8225v2_rf_part3); i++) {
2962 urtw_8187_write_phy_cck(sc, urtw_8225v2_rf_part3[i].reg,
2963 urtw_8225v2_rf_part3[i].val);
2964 }
2965
2966 urtw_write8_m(sc, URTW_TESTR, 0x0d);
2967
2968 error = urtw_8225v2_set_txpwrlvl(sc, 1);
2969 if (error)
2970 goto fail;
2971
2972 urtw_8187_write_phy_cck(sc, 0x10, 0x9b);
2973 urtw_8187_write_phy_ofdm(sc, 0x26, 0x90);
2974
2975 /* TX ant A, 0x0 for B */
2976 error = urtw_8185_tx_antenna(sc, 0x3);
2977 if (error)
2978 goto fail;
2979 urtw_write32_m(sc, URTW_HSSI_PARA, 0x3dc00002);
2980
2981 error = urtw_8225_rf_set_chan(sc, 1);
2982fail:
2983 return (error);
2984#undef N
2985}
2986
2987static usb_error_t
2988urtw_8225v2_rf_set_chan(struct urtw_softc *sc, int chan)
2989{
2990 usb_error_t error;
2991
2992 error = urtw_8225v2_set_txpwrlvl(sc, chan);
2993 if (error)
2994 goto fail;
2995
2996 urtw_8225_write(sc, URTW_8225_ADDR_7_MAGIC, urtw_8225_channel[chan]);
2997 usb_pause_mtx(&sc->sc_mtx, 10);
2998fail:
2999 return (error);
3000}
3001
3002static usb_error_t
3003urtw_8225_read(struct urtw_softc *sc, uint8_t addr, uint32_t *data)
3004{
3005 int i;
3006 int16_t bit;
3007 uint8_t rlen = 12, wlen = 6;
3008 uint16_t o1, o2, o3, tmp;
3009 uint32_t d2w = ((uint32_t)(addr & 0x1f)) << 27;
3010 uint32_t mask = 0x80000000, value = 0;
3011 usb_error_t error;
3012
3013 urtw_read16_m(sc, URTW_RF_PINS_OUTPUT, &o1);
3014 urtw_read16_m(sc, URTW_RF_PINS_ENABLE, &o2);
3015 urtw_read16_m(sc, URTW_RF_PINS_SELECT, &o3);
3016 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, o2 | URTW_RF_PINS_MAGIC4);
3017 urtw_write16_m(sc, URTW_RF_PINS_SELECT, o3 | URTW_RF_PINS_MAGIC4);
3018 o1 &= ~URTW_RF_PINS_MAGIC4;
3019 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, o1 | URTW_BB_HOST_BANG_EN);
3020 DELAY(5);
3021 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, o1);
3022 DELAY(5);
3023
3024 for (i = 0; i < (wlen / 2); i++, mask = mask >> 1) {
3025 bit = ((d2w & mask) != 0) ? 1 : 0;
3026
3027 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1);
3028 DELAY(2);
3029 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 |
3030 URTW_BB_HOST_BANG_CLK);
3031 DELAY(2);
3032 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 |
3033 URTW_BB_HOST_BANG_CLK);
3034 DELAY(2);
3035 mask = mask >> 1;
3036 if (i == 2)
3037 break;
3038 bit = ((d2w & mask) != 0) ? 1 : 0;
3039 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 |
3040 URTW_BB_HOST_BANG_CLK);
3041 DELAY(2);
3042 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 |
3043 URTW_BB_HOST_BANG_CLK);
3044 DELAY(2);
3045 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1);
3046 DELAY(1);
3047 }
3048 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 | URTW_BB_HOST_BANG_RW |
3049 URTW_BB_HOST_BANG_CLK);
3050 DELAY(2);
3051 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 | URTW_BB_HOST_BANG_RW);
3052 DELAY(2);
3053 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, o1 | URTW_BB_HOST_BANG_RW);
3054 DELAY(2);
3055
3056 mask = 0x800;
3057 for (i = 0; i < rlen; i++, mask = mask >> 1) {
3058 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT,
3059 o1 | URTW_BB_HOST_BANG_RW);
3060 DELAY(2);
3061 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT,
3062 o1 | URTW_BB_HOST_BANG_RW | URTW_BB_HOST_BANG_CLK);
3063 DELAY(2);
3064 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT,
3065 o1 | URTW_BB_HOST_BANG_RW | URTW_BB_HOST_BANG_CLK);
3066 DELAY(2);
3067 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT,
3068 o1 | URTW_BB_HOST_BANG_RW | URTW_BB_HOST_BANG_CLK);
3069 DELAY(2);
3070
3071 urtw_read16_m(sc, URTW_RF_PINS_INPUT, &tmp);
3072 value |= ((tmp & URTW_BB_HOST_BANG_CLK) ? mask : 0);
3073 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT,
3074 o1 | URTW_BB_HOST_BANG_RW);
3075 DELAY(2);
3076 }
3077
3078 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, o1 | URTW_BB_HOST_BANG_EN |
3079 URTW_BB_HOST_BANG_RW);
3080 DELAY(2);
3081
3082 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, o2);
3083 urtw_write16_m(sc, URTW_RF_PINS_SELECT, o3);
3084 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, URTW_RF_PINS_OUTPUT_MAGIC1);
3085
3086 if (data != NULL)
3087 *data = value;
3088fail:
3089 return (error);
3090}
3091
3092
3093static usb_error_t
3094urtw_8225v2_set_txpwrlvl(struct urtw_softc *sc, int chan)
3095{
3096 int i;
3097 uint8_t *cck_pwrtable;
3098 uint8_t cck_pwrlvl_max = 15, ofdm_pwrlvl_max = 25, ofdm_pwrlvl_min = 10;
3099 uint8_t cck_pwrlvl = sc->sc_txpwr_cck[chan] & 0xff;
3100 uint8_t ofdm_pwrlvl = sc->sc_txpwr_ofdm[chan] & 0xff;
3101 usb_error_t error;
3102
3103 /* CCK power setting */
3104 cck_pwrlvl = (cck_pwrlvl > cck_pwrlvl_max) ? cck_pwrlvl_max : cck_pwrlvl;
3105 cck_pwrlvl += sc->sc_txpwr_cck_base;
3106 cck_pwrlvl = (cck_pwrlvl > 35) ? 35 : cck_pwrlvl;
3107 cck_pwrtable = (chan == 14) ? urtw_8225v2_txpwr_cck_ch14 :
3108 urtw_8225v2_txpwr_cck;
3109
3110 for (i = 0; i < 8; i++)
3111 urtw_8187_write_phy_cck(sc, 0x44 + i, cck_pwrtable[i]);
3112
3113 urtw_write8_m(sc, URTW_TX_GAIN_CCK,
3114 urtw_8225v2_tx_gain_cck_ofdm[cck_pwrlvl]);
3115 usb_pause_mtx(&sc->sc_mtx, 1);
3116
3117 /* OFDM power setting */
3118 ofdm_pwrlvl = (ofdm_pwrlvl > (ofdm_pwrlvl_max - ofdm_pwrlvl_min)) ?
3119 ofdm_pwrlvl_max : ofdm_pwrlvl + ofdm_pwrlvl_min;
3120 ofdm_pwrlvl += sc->sc_txpwr_ofdm_base;
3121 ofdm_pwrlvl = (ofdm_pwrlvl > 35) ? 35 : ofdm_pwrlvl;
3122
3123 error = urtw_8185_set_anaparam2(sc, URTW_8225_ANAPARAM2_ON);
3124 if (error)
3125 goto fail;
3126
3127 urtw_8187_write_phy_ofdm(sc, 2, 0x42);
3128 urtw_8187_write_phy_ofdm(sc, 5, 0x0);
3129 urtw_8187_write_phy_ofdm(sc, 6, 0x40);
3130 urtw_8187_write_phy_ofdm(sc, 7, 0x0);
3131 urtw_8187_write_phy_ofdm(sc, 8, 0x40);
3132
3133 urtw_write8_m(sc, URTW_TX_GAIN_OFDM,
3134 urtw_8225v2_tx_gain_cck_ofdm[ofdm_pwrlvl]);
3135 usb_pause_mtx(&sc->sc_mtx, 1);
3136fail:
3137 return (error);
3138}
3139
3140static usb_error_t
3141urtw_8225v2_setgain(struct urtw_softc *sc, int16_t gain)
3142{
3143 uint8_t *gainp;
3144 usb_error_t error;
3145
3146 /* XXX for A? */
3147 gainp = urtw_8225v2_gain_bg;
3148 urtw_8187_write_phy_ofdm(sc, 0x0d, gainp[gain * 3]);
3149 usb_pause_mtx(&sc->sc_mtx, 1);
3150 urtw_8187_write_phy_ofdm(sc, 0x1b, gainp[gain * 3 + 1]);
3151 usb_pause_mtx(&sc->sc_mtx, 1);
3152 urtw_8187_write_phy_ofdm(sc, 0x1d, gainp[gain * 3 + 2]);
3153 usb_pause_mtx(&sc->sc_mtx, 1);
3154 urtw_8187_write_phy_ofdm(sc, 0x21, 0x17);
3155 usb_pause_mtx(&sc->sc_mtx, 1);
3156fail:
3157 return (error);
3158}
3159
3160static usb_error_t
3161urtw_8225_isv2(struct urtw_softc *sc, int *ret)
3162{
3163 uint32_t data;
3164 usb_error_t error;
3165
3166 *ret = 1;
3167
3168 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, URTW_RF_PINS_MAGIC5);
3169 urtw_write16_m(sc, URTW_RF_PINS_SELECT, URTW_RF_PINS_MAGIC5);
3170 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, URTW_RF_PINS_MAGIC5);
3171 usb_pause_mtx(&sc->sc_mtx, 500);
3172
3173 urtw_8225_write(sc, URTW_8225_ADDR_0_MAGIC,
3174 URTW_8225_ADDR_0_DATA_MAGIC1);
3175
3176 error = urtw_8225_read(sc, URTW_8225_ADDR_8_MAGIC, &data);
3177 if (error != 0)
3178 goto fail;
3179 if (data != URTW_8225_ADDR_8_DATA_MAGIC1)
3180 *ret = 0;
3181 else {
3182 error = urtw_8225_read(sc, URTW_8225_ADDR_9_MAGIC, &data);
3183 if (error != 0)
3184 goto fail;
3185 if (data != URTW_8225_ADDR_9_DATA_MAGIC1)
3186 *ret = 0;
3187 }
3188
3189 urtw_8225_write(sc, URTW_8225_ADDR_0_MAGIC,
3190 URTW_8225_ADDR_0_DATA_MAGIC2);
3191fail:
3192 return (error);
3193}
3194
3195static usb_error_t
3196urtw_8225v2b_rf_init(struct urtw_softc *sc)
3197{
3198#define N(a) ((int)(sizeof(a) / sizeof((a)[0])))
3199 int i;
3200 uint8_t data8;
3201 usb_error_t error;
3202
3203 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG);
3204 if (error)
3205 goto fail;
3206
3207 /*
3208 * initialize extra registers on 8187
3209 */
3210 urtw_write16_m(sc, URTW_BRSR_8187B, 0xfff);
3211
3212 /* retry limit */
3213 urtw_read8_m(sc, URTW_CW_CONF, &data8);
3214 data8 |= URTW_CW_CONF_PERPACKET_RETRY;
3215 urtw_write8_m(sc, URTW_CW_CONF, data8);
3216
3217 /* TX AGC */
3218 urtw_read8_m(sc, URTW_TX_AGC_CTL, &data8);
3219 data8 |= URTW_TX_AGC_CTL_PERPACKET_GAIN;
3220 urtw_write8_m(sc, URTW_TX_AGC_CTL, data8);
3221
3222 /* Auto Rate Fallback Control */
3223#define URTW_ARFR 0x1e0
3224 urtw_write16_m(sc, URTW_ARFR, 0xfff);
3225 urtw_read8_m(sc, URTW_RATE_FALLBACK, &data8);
3226 urtw_write8_m(sc, URTW_RATE_FALLBACK,
3227 data8 | URTW_RATE_FALLBACK_ENABLE);
3228
3229 urtw_read8_m(sc, URTW_MSR, &data8);
3230 urtw_write8_m(sc, URTW_MSR, data8 & 0xf3);
3231 urtw_read8_m(sc, URTW_MSR, &data8);
3232 urtw_write8_m(sc, URTW_MSR, data8 | URTW_MSR_LINK_ENEDCA);
3233 urtw_write8_m(sc, URTW_ACM_CONTROL, sc->sc_acmctl);
3234
3235 urtw_write16_m(sc, URTW_ATIM_WND, 2);
3236 urtw_write16_m(sc, URTW_BEACON_INTERVAL, 100);
3237#define URTW_FEMR_FOR_8187B 0x1d4
3238 urtw_write16_m(sc, URTW_FEMR_FOR_8187B, 0xffff);
3239
3240 /* led type */
3241 urtw_read8_m(sc, URTW_CONFIG1, &data8);
3242 data8 = (data8 & 0x3f) | 0x80;
3243 urtw_write8_m(sc, URTW_CONFIG1, data8);
3244
3245 /* applying MAC address again. */
3246 urtw_write32_m(sc, URTW_MAC0, ((uint32_t *)sc->sc_bssid)[0]);
3247 urtw_write16_m(sc, URTW_MAC4, ((uint32_t *)sc->sc_bssid)[1] & 0xffff);
3248
3249 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL);
3250 if (error)
3251 goto fail;
3252
3253 urtw_write8_m(sc, URTW_WPA_CONFIG, 0);
3254
3255 /*
3256 * MAC configuration
3257 */
3258 for (i = 0; i < N(urtw_8225v2b_rf_part1); i++)
3259 urtw_write8_m(sc, urtw_8225v2b_rf_part1[i].reg,
3260 urtw_8225v2b_rf_part1[i].val);
3261 urtw_write16_m(sc, URTW_TID_AC_MAP, 0xfa50);
3262 urtw_write16_m(sc, URTW_INT_MIG, 0x0000);
3263 urtw_write32_m(sc, 0x1f0, 0);
3264 urtw_write32_m(sc, 0x1f4, 0);
3265 urtw_write8_m(sc, 0x1f8, 0);
3266 urtw_write32_m(sc, URTW_RF_TIMING, 0x4001);
3267
3268#define URTW_RFSW_CTRL 0x272
3269 urtw_write16_m(sc, URTW_RFSW_CTRL, 0x569a);
3270
3271 /*
3272 * initialize PHY
3273 */
3274 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG);
3275 if (error)
3276 goto fail;
3277 urtw_read8_m(sc, URTW_CONFIG3, &data8);
3278 urtw_write8_m(sc, URTW_CONFIG3,
3279 data8 | URTW_CONFIG3_ANAPARAM_WRITE);
3280
3281 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL);
3282 if (error)
3283 goto fail;
3284
3285 /* setup RFE initial timing */
3286 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, 0x0480);
3287 urtw_write16_m(sc, URTW_RF_PINS_SELECT, 0x2488);
3288 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, 0x1fff);
3289 usb_pause_mtx(&sc->sc_mtx, 1100);
3290
3291 for (i = 0; i < N(urtw_8225v2b_rf_part0); i++) {
3292 urtw_8225_write(sc, urtw_8225v2b_rf_part0[i].reg,
3293 urtw_8225v2b_rf_part0[i].val);
3294 usb_pause_mtx(&sc->sc_mtx, 1);
3295 }
3296 urtw_8225_write(sc, 0x00, 0x01b7);
3297
3298 for (i = 0; i < 95; i++) {
3299 urtw_8225_write(sc, URTW_8225_ADDR_1_MAGIC, (uint8_t)(i + 1));
3300 usb_pause_mtx(&sc->sc_mtx, 1);
3301 urtw_8225_write(sc, URTW_8225_ADDR_2_MAGIC,
3302 urtw_8225v2b_rxgain[i]);
3303 usb_pause_mtx(&sc->sc_mtx, 1);
3304 }
3305
3306 urtw_8225_write(sc, URTW_8225_ADDR_3_MAGIC, 0x080);
3307 usb_pause_mtx(&sc->sc_mtx, 1);
3308 urtw_8225_write(sc, URTW_8225_ADDR_5_MAGIC, 0x004);
3309 usb_pause_mtx(&sc->sc_mtx, 1);
3310 urtw_8225_write(sc, URTW_8225_ADDR_0_MAGIC, 0x0b7);
3311 usb_pause_mtx(&sc->sc_mtx, 1);
3312 usb_pause_mtx(&sc->sc_mtx, 3000);
3313 urtw_8225_write(sc, URTW_8225_ADDR_2_MAGIC, 0xc4d);
3314 usb_pause_mtx(&sc->sc_mtx, 2000);
3315 urtw_8225_write(sc, URTW_8225_ADDR_2_MAGIC, 0x44d);
3316 usb_pause_mtx(&sc->sc_mtx, 1);
3317 urtw_8225_write(sc, URTW_8225_ADDR_0_MAGIC, 0x2bf);
3318 usb_pause_mtx(&sc->sc_mtx, 1);
3319
3320 urtw_write8_m(sc, URTW_TX_GAIN_CCK, 0x03);
3321 urtw_write8_m(sc, URTW_TX_GAIN_OFDM, 0x07);
3322 urtw_write8_m(sc, URTW_TX_ANTENNA, 0x03);
3323
3324 urtw_8187_write_phy_ofdm(sc, 0x80, 0x12);
3325 for (i = 0; i < 128; i++) {
3326 uint32_t addr, data;
3327
3328 data = (urtw_8225z2_agc[i] << 8) | 0x0000008f;
3329 addr = ((i + 0x80) << 8) | 0x0000008e;
3330
3331 urtw_8187_write_phy_ofdm(sc, data & 0x7f, (data >> 8) & 0xff);
3332 urtw_8187_write_phy_ofdm(sc, addr & 0x7f, (addr >> 8) & 0xff);
3333 urtw_8187_write_phy_ofdm(sc, 0x0e, 0x00);
3334 }
3335 urtw_8187_write_phy_ofdm(sc, 0x80, 0x10);
3336
3337 for (i = 0; i < N(urtw_8225v2b_rf_part2); i++)
3338 urtw_8187_write_phy_ofdm(sc, i, urtw_8225v2b_rf_part2[i].val);
3339
3340 urtw_write32_m(sc, URTW_8187B_AC_VO, (7 << 12) | (3 << 8) | 0x1c);
3341 urtw_write32_m(sc, URTW_8187B_AC_VI, (7 << 12) | (3 << 8) | 0x1c);
3342 urtw_write32_m(sc, URTW_8187B_AC_BE, (7 << 12) | (3 << 8) | 0x1c);
3343 urtw_write32_m(sc, URTW_8187B_AC_BK, (7 << 12) | (3 << 8) | 0x1c);
3344
3345 urtw_8187_write_phy_ofdm(sc, 0x97, 0x46);
3346 urtw_8187_write_phy_ofdm(sc, 0xa4, 0xb6);
3347 urtw_8187_write_phy_ofdm(sc, 0x85, 0xfc);
3348 urtw_8187_write_phy_cck(sc, 0xc1, 0x88);
3349
3350fail:
3351 return (error);
3352#undef N
3353}
3354
3355static usb_error_t
3356urtw_8225v2b_rf_set_chan(struct urtw_softc *sc, int chan)
3357{
3358 usb_error_t error;
3359
3360 error = urtw_8225v2b_set_txpwrlvl(sc, chan);
3361 if (error)
3362 goto fail;
3363
3364 urtw_8225_write(sc, URTW_8225_ADDR_7_MAGIC, urtw_8225_channel[chan]);
3365 usb_pause_mtx(&sc->sc_mtx, 10);
3366fail:
3367 return (error);
3368}
3369
3370static usb_error_t
3371urtw_8225v2b_set_txpwrlvl(struct urtw_softc *sc, int chan)
3372{
3373 int i;
3374 uint8_t *cck_pwrtable;
3375 uint8_t cck_pwrlvl_max = 15;
3376 uint8_t cck_pwrlvl = sc->sc_txpwr_cck[chan] & 0xff;
3377 uint8_t ofdm_pwrlvl = sc->sc_txpwr_ofdm[chan] & 0xff;
3378 usb_error_t error;
3379
3380 /* CCK power setting */
3381 cck_pwrlvl = (cck_pwrlvl > cck_pwrlvl_max) ?
3382 ((sc->sc_flags & URTW_RTL8187B_REV_B) ? cck_pwrlvl_max : 22) :
3383 (cck_pwrlvl + ((sc->sc_flags & URTW_RTL8187B_REV_B) ? 0 : 7));
3384 cck_pwrlvl += sc->sc_txpwr_cck_base;
3385 cck_pwrlvl = (cck_pwrlvl > 35) ? 35 : cck_pwrlvl;
3386 cck_pwrtable = (chan == 14) ? urtw_8225v2b_txpwr_cck_ch14 :
3387 urtw_8225v2b_txpwr_cck;
3388
3389 if (sc->sc_flags & URTW_RTL8187B_REV_B)
3390 cck_pwrtable += (cck_pwrlvl <= 6) ? 0 :
3391 ((cck_pwrlvl <= 11) ? 8 : 16);
3392 else
3393 cck_pwrtable += (cck_pwrlvl <= 5) ? 0 :
3394 ((cck_pwrlvl <= 11) ? 8 : ((cck_pwrlvl <= 17) ? 16 : 24));
3395
3396 for (i = 0; i < 8; i++)
3397 urtw_8187_write_phy_cck(sc, 0x44 + i, cck_pwrtable[i]);
3398
3399 urtw_write8_m(sc, URTW_TX_GAIN_CCK,
3400 urtw_8225v2_tx_gain_cck_ofdm[cck_pwrlvl] << 1);
3401 usb_pause_mtx(&sc->sc_mtx, 1);
3402
3403 /* OFDM power setting */
3404 ofdm_pwrlvl = (ofdm_pwrlvl > 15) ?
3405 ((sc->sc_flags & URTW_RTL8187B_REV_B) ? 17 : 25) :
3406 (ofdm_pwrlvl + ((sc->sc_flags & URTW_RTL8187B_REV_B) ? 2 : 10));
3407 ofdm_pwrlvl += sc->sc_txpwr_ofdm_base;
3408 ofdm_pwrlvl = (ofdm_pwrlvl > 35) ? 35 : ofdm_pwrlvl;
3409
3410 urtw_write8_m(sc, URTW_TX_GAIN_OFDM,
3411 urtw_8225v2_tx_gain_cck_ofdm[ofdm_pwrlvl] << 1);
3412
3413 if (sc->sc_flags & URTW_RTL8187B_REV_B) {
3414 if (ofdm_pwrlvl <= 11) {
3415 urtw_8187_write_phy_ofdm(sc, 0x87, 0x60);
3416 urtw_8187_write_phy_ofdm(sc, 0x89, 0x60);
3417 } else {
3418 urtw_8187_write_phy_ofdm(sc, 0x87, 0x5c);
3419 urtw_8187_write_phy_ofdm(sc, 0x89, 0x5c);
3420 }
3421 } else {
3422 if (ofdm_pwrlvl <= 11) {
3423 urtw_8187_write_phy_ofdm(sc, 0x87, 0x5c);
3424 urtw_8187_write_phy_ofdm(sc, 0x89, 0x5c);
3425 } else if (ofdm_pwrlvl <= 17) {
3426 urtw_8187_write_phy_ofdm(sc, 0x87, 0x54);
3427 urtw_8187_write_phy_ofdm(sc, 0x89, 0x54);
3428 } else {
3429 urtw_8187_write_phy_ofdm(sc, 0x87, 0x50);
3430 urtw_8187_write_phy_ofdm(sc, 0x89, 0x50);
3431 }
3432 }
3433 usb_pause_mtx(&sc->sc_mtx, 1);
3434fail:
3435 return (error);
3436}
3437
3438static usb_error_t
3439urtw_read8e(struct urtw_softc *sc, int val, uint8_t *data)
3440{
3441 struct usb_device_request req;
3442 usb_error_t error;
3443
3444 req.bmRequestType = UT_READ_VENDOR_DEVICE;
3445 req.bRequest = URTW_8187_GETREGS_REQ;
3446 USETW(req.wValue, val | 0xfe00);
3447 USETW(req.wIndex, 0);
3448 USETW(req.wLength, sizeof(uint8_t));
3449
3450 error = urtw_do_request(sc, &req, data);
3451 return (error);
3452}
3453
3454static usb_error_t
3455urtw_write8e(struct urtw_softc *sc, int val, uint8_t data)
3456{
3457 struct usb_device_request req;
3458
3459 req.bmRequestType = UT_WRITE_VENDOR_DEVICE;
3460 req.bRequest = URTW_8187_SETREGS_REQ;
3461 USETW(req.wValue, val | 0xfe00);
3462 USETW(req.wIndex, 0);
3463 USETW(req.wLength, sizeof(uint8_t));
3464
3465 return (urtw_do_request(sc, &req, &data));
3466}
3467
3468static usb_error_t
3469urtw_8180_set_anaparam(struct urtw_softc *sc, uint32_t val)
3470{
3471 uint8_t data;
3472 usb_error_t error;
3473
3474 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG);
3475 if (error)
3476 goto fail;
3477
3478 urtw_read8_m(sc, URTW_CONFIG3, &data);
3479 urtw_write8_m(sc, URTW_CONFIG3, data | URTW_CONFIG3_ANAPARAM_WRITE);
3480 urtw_write32_m(sc, URTW_ANAPARAM, val);
3481 urtw_read8_m(sc, URTW_CONFIG3, &data);
3482 urtw_write8_m(sc, URTW_CONFIG3, data & ~URTW_CONFIG3_ANAPARAM_WRITE);
3483
3484 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL);
3485 if (error)
3486 goto fail;
3487fail:
3488 return (error);
3489}
3490
3491static usb_error_t
3492urtw_8185_set_anaparam2(struct urtw_softc *sc, uint32_t val)
3493{
3494 uint8_t data;
3495 usb_error_t error;
3496
3497 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG);
3498 if (error)
3499 goto fail;
3500
3501 urtw_read8_m(sc, URTW_CONFIG3, &data);
3502 urtw_write8_m(sc, URTW_CONFIG3, data | URTW_CONFIG3_ANAPARAM_WRITE);
3503 urtw_write32_m(sc, URTW_ANAPARAM2, val);
3504 urtw_read8_m(sc, URTW_CONFIG3, &data);
3505 urtw_write8_m(sc, URTW_CONFIG3, data & ~URTW_CONFIG3_ANAPARAM_WRITE);
3506
3507 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL);
3508 if (error)
3509 goto fail;
3510fail:
3511 return (error);
3512}
3513
3514static usb_error_t
3515urtw_intr_enable(struct urtw_softc *sc)
3516{
3517 usb_error_t error;
3518
3519 urtw_write16_m(sc, URTW_INTR_MASK, 0xffff);
3520fail:
3521 return (error);
3522}
3523
3524static usb_error_t
3525urtw_intr_disable(struct urtw_softc *sc)
3526{
3527 usb_error_t error;
3528
3529 urtw_write16_m(sc, URTW_INTR_MASK, 0);
3530fail:
3531 return (error);
3532}
3533
3534static usb_error_t
3535urtw_reset(struct urtw_softc *sc)
3536{
3537 uint8_t data;
3538 usb_error_t error;
3539
3540 error = urtw_8180_set_anaparam(sc, URTW_8225_ANAPARAM_ON);
3541 if (error)
3542 goto fail;
3543 error = urtw_8185_set_anaparam2(sc, URTW_8225_ANAPARAM2_ON);
3544 if (error)
3545 goto fail;
3546
3547 error = urtw_intr_disable(sc);
3548 if (error)
3549 goto fail;
3550 usb_pause_mtx(&sc->sc_mtx, 100);
3551
3552 error = urtw_write8e(sc, 0x18, 0x10);
3553 if (error != 0)
3554 goto fail;
3555 error = urtw_write8e(sc, 0x18, 0x11);
3556 if (error != 0)
3557 goto fail;
3558 error = urtw_write8e(sc, 0x18, 0x00);
3559 if (error != 0)
3560 goto fail;
3561 usb_pause_mtx(&sc->sc_mtx, 100);
3562
3563 urtw_read8_m(sc, URTW_CMD, &data);
3564 data = (data & 0x2) | URTW_CMD_RST;
3565 urtw_write8_m(sc, URTW_CMD, data);
3566 usb_pause_mtx(&sc->sc_mtx, 100);
3567
3568 urtw_read8_m(sc, URTW_CMD, &data);
3569 if (data & URTW_CMD_RST) {
3570 device_printf(sc->sc_dev, "reset timeout\n");
3571 goto fail;
3572 }
3573
3574 error = urtw_set_mode(sc, URTW_EPROM_CMD_LOAD);
3575 if (error)
3576 goto fail;
3577 usb_pause_mtx(&sc->sc_mtx, 100);
3578
3579 error = urtw_8180_set_anaparam(sc, URTW_8225_ANAPARAM_ON);
3580 if (error)
3581 goto fail;
3582 error = urtw_8185_set_anaparam2(sc, URTW_8225_ANAPARAM2_ON);
3583 if (error)
3584 goto fail;
3585fail:
3586 return (error);
3587}
3588
3589static usb_error_t
3590urtw_led_ctl(struct urtw_softc *sc, int mode)
3591{
3592 usb_error_t error = 0;
3593
3594 switch (sc->sc_strategy) {
3595 case URTW_SW_LED_MODE0:
3596 error = urtw_led_mode0(sc, mode);
3597 break;
3598 case URTW_SW_LED_MODE1:
3599 error = urtw_led_mode1(sc, mode);
3600 break;
3601 case URTW_SW_LED_MODE2:
3602 error = urtw_led_mode2(sc, mode);
3603 break;
3604 case URTW_SW_LED_MODE3:
3605 error = urtw_led_mode3(sc, mode);
3606 break;
3607 default:
3608 panic("unsupported LED mode %d\n", sc->sc_strategy);
3609 /* never reach */
3610 }
3611
3612 return (error);
3613}
3614
3615static usb_error_t
3616urtw_led_mode0(struct urtw_softc *sc, int mode)
3617{
3618
3619 switch (mode) {
3620 case URTW_LED_CTL_POWER_ON:
3621 sc->sc_gpio_ledstate = URTW_LED_POWER_ON_BLINK;
3622 break;
3623 case URTW_LED_CTL_TX:
3624 if (sc->sc_gpio_ledinprogress == 1)
3625 return (0);
3626
3627 sc->sc_gpio_ledstate = URTW_LED_BLINK_NORMAL;
3628 sc->sc_gpio_blinktime = 2;
3629 break;
3630 case URTW_LED_CTL_LINK:
3631 sc->sc_gpio_ledstate = URTW_LED_ON;
3632 break;
3633 default:
3634 panic("unsupported LED mode 0x%x", mode);
3635 /* never reach */
3636 }
3637
3638 switch (sc->sc_gpio_ledstate) {
3639 case URTW_LED_ON:
3640 if (sc->sc_gpio_ledinprogress != 0)
3641 break;
3642 urtw_led_on(sc, URTW_LED_GPIO);
3643 break;
3644 case URTW_LED_BLINK_NORMAL:
3645 if (sc->sc_gpio_ledinprogress != 0)
3646 break;
3647 sc->sc_gpio_ledinprogress = 1;
3648 sc->sc_gpio_blinkstate = (sc->sc_gpio_ledon != 0) ?
3649 URTW_LED_OFF : URTW_LED_ON;
3650 usb_callout_reset(&sc->sc_led_ch, hz, urtw_led_ch, sc);
3651 break;
3652 case URTW_LED_POWER_ON_BLINK:
3653 urtw_led_on(sc, URTW_LED_GPIO);
3654 usb_pause_mtx(&sc->sc_mtx, 100);
3655 urtw_led_off(sc, URTW_LED_GPIO);
3656 break;
3657 default:
3658 panic("unknown LED status 0x%x", sc->sc_gpio_ledstate);
3659 /* never reach */
3660 }
3661 return (0);
3662}
3663
3664static usb_error_t
3665urtw_led_mode1(struct urtw_softc *sc, int mode)
3666{
3667
3668 return (USB_ERR_INVAL);
3669}
3670
3671static usb_error_t
3672urtw_led_mode2(struct urtw_softc *sc, int mode)
3673{
3674
3675 return (USB_ERR_INVAL);
3676}
3677
3678static usb_error_t
3679urtw_led_mode3(struct urtw_softc *sc, int mode)
3680{
3681
3682 return (USB_ERR_INVAL);
3683}
3684
3685static usb_error_t
3686urtw_led_on(struct urtw_softc *sc, int type)
3687{
3688 usb_error_t error;
3689
3690 if (type == URTW_LED_GPIO) {
3691 switch (sc->sc_gpio_ledpin) {
3692 case URTW_LED_PIN_GPIO0:
3693 urtw_write8_m(sc, URTW_GPIO, 0x01);
3694 urtw_write8_m(sc, URTW_GP_ENABLE, 0x00);
3695 break;
3696 default:
3697 panic("unsupported LED PIN type 0x%x",
3698 sc->sc_gpio_ledpin);
3699 /* never reach */
3700 }
3701 } else {
3702 panic("unsupported LED type 0x%x", type);
3703 /* never reach */
3704 }
3705
3706 sc->sc_gpio_ledon = 1;
3707fail:
3708 return (error);
3709}
3710
3711static usb_error_t
3712urtw_led_off(struct urtw_softc *sc, int type)
3713{
3714 usb_error_t error;
3715
3716 if (type == URTW_LED_GPIO) {
3717 switch (sc->sc_gpio_ledpin) {
3718 case URTW_LED_PIN_GPIO0:
3719 urtw_write8_m(sc, URTW_GPIO, URTW_GPIO_DATA_MAGIC1);
3720 urtw_write8_m(sc,
3721 URTW_GP_ENABLE, URTW_GP_ENABLE_DATA_MAGIC1);
3722 break;
3723 default:
3724 panic("unsupported LED PIN type 0x%x",
3725 sc->sc_gpio_ledpin);
3726 /* never reach */
3727 }
3728 } else {
3729 panic("unsupported LED type 0x%x", type);
3730 /* never reach */
3731 }
3732
3733 sc->sc_gpio_ledon = 0;
3734
3735fail:
3736 return (error);
3737}
3738
3739static void
3740urtw_led_ch(void *arg)
3741{
3742 struct urtw_softc *sc = arg;
3743 struct ifnet *ifp = sc->sc_ifp;
3744 struct ieee80211com *ic = ifp->if_l2com;
3745
3746 ieee80211_runtask(ic, &sc->sc_led_task);
3747}
3748
3749static void
3750urtw_ledtask(void *arg, int pending)
3751{
3752 struct urtw_softc *sc = arg;
3753
3754 if (sc->sc_strategy != URTW_SW_LED_MODE0)
3755 panic("could not process a LED strategy 0x%x", sc->sc_strategy);
3756
3757 URTW_LOCK(sc);
3758 urtw_led_blink(sc);
3759 URTW_UNLOCK(sc);
3760}
3761
3762static usb_error_t
3763urtw_led_blink(struct urtw_softc *sc)
3764{
3765 uint8_t ing = 0;
3766 usb_error_t error;
3767
3768 if (sc->sc_gpio_blinkstate == URTW_LED_ON)
3769 error = urtw_led_on(sc, URTW_LED_GPIO);
3770 else
3771 error = urtw_led_off(sc, URTW_LED_GPIO);
3772 sc->sc_gpio_blinktime--;
3773 if (sc->sc_gpio_blinktime == 0)
3774 ing = 1;
3775 else {
3776 if (sc->sc_gpio_ledstate != URTW_LED_BLINK_NORMAL &&
3777 sc->sc_gpio_ledstate != URTW_LED_BLINK_SLOWLY &&
3778 sc->sc_gpio_ledstate != URTW_LED_BLINK_CM3)
3779 ing = 1;
3780 }
3781 if (ing == 1) {
3782 if (sc->sc_gpio_ledstate == URTW_LED_ON &&
3783 sc->sc_gpio_ledon == 0)
3784 error = urtw_led_on(sc, URTW_LED_GPIO);
3785 else if (sc->sc_gpio_ledstate == URTW_LED_OFF &&
3786 sc->sc_gpio_ledon == 1)
3787 error = urtw_led_off(sc, URTW_LED_GPIO);
3788
3789 sc->sc_gpio_blinktime = 0;
3790 sc->sc_gpio_ledinprogress = 0;
3791 return (0);
3792 }
3793
3794 sc->sc_gpio_blinkstate = (sc->sc_gpio_blinkstate != URTW_LED_ON) ?
3795 URTW_LED_ON : URTW_LED_OFF;
3796
3797 switch (sc->sc_gpio_ledstate) {
3798 case URTW_LED_BLINK_NORMAL:
3799 usb_callout_reset(&sc->sc_led_ch, hz, urtw_led_ch, sc);
3800 break;
3801 default:
3802 panic("unknown LED status 0x%x", sc->sc_gpio_ledstate);
3803 /* never reach */
3804 }
3805 return (0);
3806}
3807
3808static usb_error_t
3809urtw_rx_enable(struct urtw_softc *sc)
3810{
3811 uint8_t data;
3812 usb_error_t error;
3813
3814 usbd_transfer_start((sc->sc_flags & URTW_RTL8187B) ?
3815 sc->sc_xfer[URTW_8187B_BULK_RX] : sc->sc_xfer[URTW_8187L_BULK_RX]);
3816
3817 error = urtw_rx_setconf(sc);
3818 if (error != 0)
3819 goto fail;
3820
3821 if ((sc->sc_flags & URTW_RTL8187B) == 0) {
3822 urtw_read8_m(sc, URTW_CMD, &data);
3823 urtw_write8_m(sc, URTW_CMD, data | URTW_CMD_RX_ENABLE);
3824 }
3825fail:
3826 return (error);
3827}
3828
3829static usb_error_t
3830urtw_tx_enable(struct urtw_softc *sc)
3831{
3832 uint8_t data8;
3833 uint32_t data;
3834 usb_error_t error;
3835
3836 if (sc->sc_flags & URTW_RTL8187B) {
3837 urtw_read32_m(sc, URTW_TX_CONF, &data);
3838 data &= ~URTW_TX_LOOPBACK_MASK;
3839 data &= ~(URTW_TX_DPRETRY_MASK | URTW_TX_RTSRETRY_MASK);
3840 data &= ~(URTW_TX_NOCRC | URTW_TX_MXDMA_MASK);
3841 data &= ~URTW_TX_SWPLCPLEN;
3842 data |= URTW_TX_HW_SEQNUM | URTW_TX_DISREQQSIZE |
3843 (7 << 8) | /* short retry limit */
3844 (7 << 0) | /* long retry limit */
3845 (7 << 21); /* MAX TX DMA */
3846 urtw_write32_m(sc, URTW_TX_CONF, data);
3847
3848 urtw_read8_m(sc, URTW_MSR, &data8);
3849 data8 |= URTW_MSR_LINK_ENEDCA;
3850 urtw_write8_m(sc, URTW_MSR, data8);
3851 return (error);
3852 }
3853
3854 urtw_read8_m(sc, URTW_CW_CONF, &data8);
3855 data8 &= ~(URTW_CW_CONF_PERPACKET_CW | URTW_CW_CONF_PERPACKET_RETRY);
3856 urtw_write8_m(sc, URTW_CW_CONF, data8);
3857
3858 urtw_read8_m(sc, URTW_TX_AGC_CTL, &data8);
3859 data8 &= ~URTW_TX_AGC_CTL_PERPACKET_GAIN;
3860 data8 &= ~URTW_TX_AGC_CTL_PERPACKET_ANTSEL;
3861 data8 &= ~URTW_TX_AGC_CTL_FEEDBACK_ANT;
3862 urtw_write8_m(sc, URTW_TX_AGC_CTL, data8);
3863
3864 urtw_read32_m(sc, URTW_TX_CONF, &data);
3865 data &= ~URTW_TX_LOOPBACK_MASK;
3866 data |= URTW_TX_LOOPBACK_NONE;
3867 data &= ~(URTW_TX_DPRETRY_MASK | URTW_TX_RTSRETRY_MASK);
3868 data |= sc->sc_tx_retry << URTW_TX_DPRETRY_SHIFT;
3869 data |= sc->sc_rts_retry << URTW_TX_RTSRETRY_SHIFT;
3870 data &= ~(URTW_TX_NOCRC | URTW_TX_MXDMA_MASK);
3871 data |= URTW_TX_MXDMA_2048 | URTW_TX_CWMIN | URTW_TX_DISCW;
3872 data &= ~URTW_TX_SWPLCPLEN;
3873 data |= URTW_TX_NOICV;
3874 urtw_write32_m(sc, URTW_TX_CONF, data);
3875
3876 urtw_read8_m(sc, URTW_CMD, &data8);
3877 urtw_write8_m(sc, URTW_CMD, data8 | URTW_CMD_TX_ENABLE);
3878fail:
3879 return (error);
3880}
3881
3882static usb_error_t
3883urtw_rx_setconf(struct urtw_softc *sc)
3884{
3885 struct ifnet *ifp = sc->sc_ifp;
3886 struct ieee80211com *ic = ifp->if_l2com;
3887 uint32_t data;
3888 usb_error_t error;
3889
3890 urtw_read32_m(sc, URTW_RX, &data);
3891 data = data &~ URTW_RX_FILTER_MASK;
3892 if (sc->sc_flags & URTW_RTL8187B) {
3893 data = data | URTW_RX_FILTER_MNG | URTW_RX_FILTER_DATA |
3894 URTW_RX_FILTER_MCAST | URTW_RX_FILTER_BCAST |
3895 URTW_RX_FILTER_NICMAC | URTW_RX_CHECK_BSSID |
3896 URTW_RX_FIFO_THRESHOLD_NONE |
3897 URTW_MAX_RX_DMA_2048 |
3898 URTW_RX_AUTORESETPHY | URTW_RCR_ONLYERLPKT;
3899 } else {
3900 data = data | URTW_RX_FILTER_MNG | URTW_RX_FILTER_DATA;
3901 data = data | URTW_RX_FILTER_BCAST | URTW_RX_FILTER_MCAST;
3902
3903 if (ic->ic_opmode == IEEE80211_M_MONITOR) {
3904 data = data | URTW_RX_FILTER_ICVERR;
3905 data = data | URTW_RX_FILTER_PWR;
3906 }
3907 if (sc->sc_crcmon == 1 && ic->ic_opmode == IEEE80211_M_MONITOR)
3908 data = data | URTW_RX_FILTER_CRCERR;
3909
3910 if (ic->ic_opmode == IEEE80211_M_MONITOR ||
3911 (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC))) {
3912 data = data | URTW_RX_FILTER_ALLMAC;
3913 } else {
3914 data = data | URTW_RX_FILTER_NICMAC;
3915 data = data | URTW_RX_CHECK_BSSID;
3916 }
3917
3918 data = data &~ URTW_RX_FIFO_THRESHOLD_MASK;
3919 data = data | URTW_RX_FIFO_THRESHOLD_NONE |
3920 URTW_RX_AUTORESETPHY;
3921 data = data &~ URTW_MAX_RX_DMA_MASK;
3922 data = data | URTW_MAX_RX_DMA_2048 | URTW_RCR_ONLYERLPKT;
3923 }
3924
3925 urtw_write32_m(sc, URTW_RX, data);
3926fail:
3927 return (error);
3928}
3929
3930static struct mbuf *
3931urtw_rxeof(struct usb_xfer *xfer, struct urtw_data *data, int *rssi_p,
3932 int8_t *nf_p)
3933{
3934 int actlen, flen, rssi;
3935 struct ieee80211_frame *wh;
3936 struct mbuf *m, *mnew;
3937 struct urtw_softc *sc = data->sc;
3938 struct ifnet *ifp = sc->sc_ifp;
3939 struct ieee80211com *ic = ifp->if_l2com;
3940 uint8_t noise = 0, rate;
3941
3942 usbd_xfer_status(xfer, &actlen, NULL, NULL, NULL);
3943
3944 if (actlen < (int)URTW_MIN_RXBUFSZ) {
3945 ifp->if_ierrors++;
3946 return (NULL);
3947 }
3948
3949 if (sc->sc_flags & URTW_RTL8187B) {
3950 struct urtw_8187b_rxhdr *rx;
3951
3952 rx = (struct urtw_8187b_rxhdr *)(data->buf +
3953 (actlen - (sizeof(struct urtw_8187b_rxhdr))));
3954 flen = le32toh(rx->flag) & 0xfff;
3955 if (flen > actlen) {
3956 ifp->if_ierrors++;
3957 return (NULL);
3958 }
3959 rate = (le32toh(rx->flag) >> URTW_RX_FLAG_RXRATE_SHIFT) & 0xf;
3960 /* XXX correct? */
3961 rssi = rx->rssi & URTW_RX_RSSI_MASK;
3962 noise = rx->noise;
3963 } else {
3964 struct urtw_8187l_rxhdr *rx;
3965
3966 rx = (struct urtw_8187l_rxhdr *)(data->buf +
3967 (actlen - (sizeof(struct urtw_8187l_rxhdr))));
3968 flen = le32toh(rx->flag) & 0xfff;
3969 if (flen > actlen) {
3970 ifp->if_ierrors++;
3971 return (NULL);
3972 }
3973
3974 rate = (le32toh(rx->flag) >> URTW_RX_FLAG_RXRATE_SHIFT) & 0xf;
3975 /* XXX correct? */
3976 rssi = rx->rssi & URTW_RX_8187L_RSSI_MASK;
3977 noise = rx->noise;
3978 }
3979
3980 mnew = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
3981 if (mnew == NULL) {
3982 ifp->if_ierrors++;
3983 return (NULL);
3984 }
3985
3986 m = data->m;
3987 data->m = mnew;
3988 data->buf = mtod(mnew, uint8_t *);
3989
3990 /* finalize mbuf */
3991 m->m_pkthdr.rcvif = ifp;
3992 m->m_pkthdr.len = m->m_len = flen - IEEE80211_CRC_LEN;
3993
3994 if (ieee80211_radiotap_active(ic)) {
3995 struct urtw_rx_radiotap_header *tap = &sc->sc_rxtap;
3996
3997 /* XXX Are variables correct? */
3998 tap->wr_chan_freq = htole16(ic->ic_curchan->ic_freq);
3999 tap->wr_chan_flags = htole16(ic->ic_curchan->ic_flags);
4000 tap->wr_dbm_antsignal = (int8_t)rssi;
4001 }
4002
4003 wh = mtod(m, struct ieee80211_frame *);
4004 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) == IEEE80211_FC0_TYPE_DATA)
4005 sc->sc_currate = (rate > 0) ? rate : sc->sc_currate;
4006
4007 *rssi_p = rssi;
4008 *nf_p = noise; /* XXX correct? */
4009
4010 return (m);
4011}
4012
4013static void
4014urtw_bulk_rx_callback(struct usb_xfer *xfer, usb_error_t error)
4015{
4016 struct urtw_softc *sc = usbd_xfer_softc(xfer);
4017 struct ifnet *ifp = sc->sc_ifp;
4018 struct ieee80211com *ic = ifp->if_l2com;
4019 struct ieee80211_frame *wh;
4020 struct ieee80211_node *ni;
4021 struct mbuf *m = NULL;
4022 struct urtw_data *data;
4023 int8_t nf = -95;
4024 int rssi = 1;
4025
4026 URTW_ASSERT_LOCKED(sc);
4027
4028 switch (USB_GET_STATE(xfer)) {
4029 case USB_ST_TRANSFERRED:
4030 data = STAILQ_FIRST(&sc->sc_rx_active);
4031 if (data == NULL)
4032 goto setup;
4033 STAILQ_REMOVE_HEAD(&sc->sc_rx_active, next);
4034 m = urtw_rxeof(xfer, data, &rssi, &nf);
4035 STAILQ_INSERT_TAIL(&sc->sc_rx_inactive, data, next);
4036 /* FALLTHROUGH */
4037 case USB_ST_SETUP:
4038setup:
4039 data = STAILQ_FIRST(&sc->sc_rx_inactive);
4040 if (data == NULL) {
4041 KASSERT(m == NULL, ("mbuf isn't NULL"));
4042 return;
4043 }
4044 STAILQ_REMOVE_HEAD(&sc->sc_rx_inactive, next);
4045 STAILQ_INSERT_TAIL(&sc->sc_rx_active, data, next);
4046 usbd_xfer_set_frame_data(xfer, 0, data->buf,
4047 usbd_xfer_max_len(xfer));
4048 usbd_transfer_submit(xfer);
4049
4050 /*
4051 * To avoid LOR we should unlock our private mutex here to call
4052 * ieee80211_input() because here is at the end of a USB
4053 * callback and safe to unlock.
4054 */
4055 URTW_UNLOCK(sc);
4056 if (m != NULL) {
4057 wh = mtod(m, struct ieee80211_frame *);
4058 ni = ieee80211_find_rxnode(ic,
4059 (struct ieee80211_frame_min *)wh);
4060 if (ni != NULL) {
4061 (void) ieee80211_input(ni, m, rssi, nf);
4062 /* node is no longer needed */
4063 ieee80211_free_node(ni);
4064 } else
4065 (void) ieee80211_input_all(ic, m, rssi, nf);
4066 m = NULL;
4067 }
4068 URTW_LOCK(sc);
4069 break;
4070 default:
4071 /* needs it to the inactive queue due to a error. */
4072 data = STAILQ_FIRST(&sc->sc_rx_active);
4073 if (data != NULL) {
4074 STAILQ_REMOVE_HEAD(&sc->sc_rx_active, next);
4075 STAILQ_INSERT_TAIL(&sc->sc_rx_inactive, data, next);
4076 }
4077 if (error != USB_ERR_CANCELLED) {
4078 usbd_xfer_set_stall(xfer);
4079 ifp->if_ierrors++;
4080 goto setup;
4081 }
4082 break;
4083 }
4084}
4085
4086#define URTW_STATUS_TYPE_TXCLOSE 1
4087#define URTW_STATUS_TYPE_BEACON_INTR 0
4088
4089static void
4090urtw_txstatus_eof(struct usb_xfer *xfer)
4091{
4092 struct urtw_softc *sc = usbd_xfer_softc(xfer);
4093 struct ifnet *ifp = sc->sc_ifp;
4094 int actlen, type, pktretry, seq;
4095 uint64_t val;
4096
4097 usbd_xfer_status(xfer, &actlen, NULL, NULL, NULL);
4098
4099 if (actlen != sizeof(uint64_t))
4100 return;
4101
4102 val = le64toh(sc->sc_txstatus);
4103 type = (val >> 30) & 0x3;
4104 if (type == URTW_STATUS_TYPE_TXCLOSE) {
4105 pktretry = val & 0xff;
4106 seq = (val >> 16) & 0xff;
4107 if (pktretry == URTW_TX_MAXRETRY)
4108 ifp->if_oerrors++;
4109 DPRINTF(sc, URTW_DEBUG_TXSTATUS, "pktretry %d seq %#x\n",
4110 pktretry, seq);
4111 }
4112}
4113
4114static void
4115urtw_bulk_tx_status_callback(struct usb_xfer *xfer, usb_error_t error)
4116{
4117 struct urtw_softc *sc = usbd_xfer_softc(xfer);
4118 struct ifnet *ifp = sc->sc_ifp;
|