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if_axgereg.h (258331) if_axgereg.h (266738)
1/*-
1/*-
2 * Copyright (c) 2013 Kevin Lo
2 * Copyright (c) 2013-2014 Kevin Lo
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright

--- 7 unchanged lines hidden (view full) ---

18 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
19 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
20 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
21 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
22 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
23 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
24 * THE POSSIBILITY OF SUCH DAMAGE.
25 *
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright

--- 7 unchanged lines hidden (view full) ---

18 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
19 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
20 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
21 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
22 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
23 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
24 * THE POSSIBILITY OF SUCH DAMAGE.
25 *
26 * $FreeBSD: head/sys/dev/usb/net/if_axgereg.h 258331 2013-11-19 00:37:53Z markj $
26 * $FreeBSD: head/sys/dev/usb/net/if_axgereg.h 266738 2014-05-27 08:14:54Z kevlo $
27 */
28
27 */
28
29#define AX88179_PHY_ID 0x03
30#define AXGE_MCAST_FILTER_SIZE 8
31#define AXGE_MAXGE_MCAST 64
32#define AXGE_EEPROM_LEN 0x40
33#define AXGE_RX_CHECKSUM 1
34#define AXGE_TX_CHECKSUM 2
35
36#define AXGE_ACCESS_MAC 0x01
37#define AXGE_ACCESS_PHY 0x02
38#define AXGE_ACCESS_WAKEUP 0x03
39#define AXGE_ACCESS_EEPROM 0x04
40#define AXGE_ACCESS_EFUSE 0x05
41#define AXGE_RELOAD_EEPROM_EFUSE 0x06
42#define AXGE_WRITE_EFUSE_EN 0x09
43#define AXGE_WRITE_EFUSE_DIS 0x0A
44#define AXGE_ACCESS_MFAB 0x10
45
29#define AXGE_ACCESS_MAC 0x01
30#define AXGE_ACCESS_PHY 0x02
31#define AXGE_ACCESS_WAKEUP 0x03
32#define AXGE_ACCESS_EEPROM 0x04
33#define AXGE_ACCESS_EFUSE 0x05
34#define AXGE_RELOAD_EEPROM_EFUSE 0x06
35#define AXGE_WRITE_EFUSE_EN 0x09
36#define AXGE_WRITE_EFUSE_DIS 0x0A
37#define AXGE_ACCESS_MFAB 0x10
38
46#define AXGE_LINK_STATUS 0x02
47#define AXGE_LINK_STATUS_USB_FS 0x01
48#define AXGE_LINK_STATUS_USB_HS 0x02
49#define AXGE_LINK_STATUS_USB_SS 0x04
39/* Physical link status register */
40#define AXGE_PLSR 0x02
41#define PLSR_USB_FS 0x01
42#define PLSR_USB_HS 0x02
43#define PLSR_USB_SS 0x04
50
44
51#define AXGE_SROM_ADDR 0x07
52#define AXGE_SROM_DATA_LOW 0x08
53#define AXGE_SROM_DATA_HIGH 0x09
54#define AXGE_SROM_CMD 0x0a
55#define AXGE_SROM_CMD_RD 0x04 /* EEprom read command */
56#define AXGE_SROM_CMD_WR 0x08 /* EEprom write command */
57#define AXGE_SROM_CMD_BUSY 0x10 /* EEprom access module busy */
45/* EEPROM address register */
46#define AXGE_EAR 0x07
58
47
59#define AXGE_RX_CTL 0x0b
60#define AXGE_RX_CTL_DROPCRCERR 0x0100 /* Drop CRC error packet */
61#define AXGE_RX_CTL_IPE 0x0200 /* 4-byte IP header alignment */
62#define AXGE_RX_CTL_TXPADCRC 0x0400 /* Csum value in rx header 3 */
63#define AXGE_RX_CTL_START 0x0080 /* Ethernet MAC start */
64#define AXGE_RX_CTL_AP 0x0020 /* Accept physical address from
65 multicast array */
66#define AXGE_RX_CTL_AM 0x0010
67#define AXGE_RX_CTL_AB 0x0008
68#define AXGE_RX_CTL_HA8B 0x0004
69#define AXGE_RX_CTL_AMALL 0x0002 /* Accept all multicast frames */
70#define AXGE_RX_CTL_PRO 0x0001 /* Promiscuous Mode */
71#define AXGE_RX_CTL_STOP 0x0000 /* Stop MAC */
48/* EEPROM data low register */
49#define AXGE_EDLR 0x08
72
50
73#define AXGE_NODE_ID 0x10
74#define AXGE_MULTI_FILTER_ARRY 0x16
51/* EEPROM data high register */
52#define AXGE_EDHR 0x09
75
53
76#define AXGE_MEDIUM_STATUS_MODE 0x22
77#define AXGE_MEDIUM_GIGAMODE 0x0001
78#define AXGE_MEDIUM_FULL_DUPLEX 0x0002
79#define AXGE_MEDIUM_ALWAYS_ONE 0x0004
80#define AXGE_MEDIUM_EN_125MHZ 0x0008
81#define AXGE_MEDIUM_RXFLOW_CTRLEN 0x0010
82#define AXGE_MEDIUM_TXFLOW_CTRLEN 0x0020
83#define AXGE_MEDIUM_RECEIVE_EN 0x0100
84#define AXGE_MEDIUM_PS 0x0200
85#define AXGE_MEDIUM_JUMBO_EN 0x8040
54/* EEPROM command register */
55#define AXGE_ECR 0x0a
86
56
87#define AXGE_MONITOR_MODE 0x24
88#define AXGE_MONITOR_MODE_RWLC 0x02
89#define AXGE_MONITOR_MODE_RWMP 0x04
90#define AXGE_MONITOR_MODE_RWWF 0x08
91#define AXGE_MONITOR_MODE_RW_FLAG 0x10
92#define AXGE_MONITOR_MODE_PMEPOL 0x20
93#define AXGE_MONITOR_MODE_PMETYPE 0x40
57/* Rx control register */
58#define AXGE_RCR 0x0b
59#define RCR_STOP 0x0000
60#define RCR_PRO 0x0001
61#define RCR_AMALL 0x0002
62#define RCR_AB 0x0008
63#define RCR_AM 0x0010
64#define RCR_AP 0x0020
65#define RCR_SO 0x0080
66#define RCR_DROP_CRCE 0x0100
67#define RCR_IPE 0x0200
68#define RCR_TX_CRC_PAD 0x0400
94
69
95#define AXGE_GPIO_CTRL 0x25
96#define AXGE_GPIO_CTRL_GPIO3EN 0x80
97#define AXGE_GPIO_CTRL_GPIO2EN 0x40
98#define AXGE_GPIO_CTRL_GPIO1EN 0x20
70/* Node id register */
71#define AXGE_NIDR 0x10
99
72
100#define AXGE_PHYPWR_RSTCTL 0x26
101#define AXGE_PHYPWR_RSTCTL_BZ 0x0010
102#define AXGE_PHYPWR_RSTCTL_IPRL 0x0020
103#define AXGE_PHYPWR_RSTCTL_AUTODETACH 0x1000
73/* Multicast filter array */
74#define AXGE_MFA 0x16
104
75
105#define AXGE_RX_BULKIN_QCTRL 0x2e
106#define AXGE_RX_BULKIN_QCTRL_TIME 0x01
107#define AXGE_RX_BULKIN_QCTRL_IFG 0x02
108#define AXGE_RX_BULKIN_QCTRL_SIZE 0x04
76/* Medium status register */
77#define AXGE_MSR 0x22
78#define MSR_GM 0x0001
79#define MSR_FD 0x0002
80#define MSR_EN_125MHZ 0x0008
81#define MSR_RFC 0x0010
82#define MSR_TFC 0x0020
83#define MSR_RE 0x0100
84#define MSR_PS 0x0200
109
85
110#define AXGE_RX_BULKIN_QTIMR_LOW 0x2f
111#define AXGE_RX_BULKIN_QTIMR_HIGH 0x30
112#define AXGE_RX_BULKIN_QSIZE 0x31
113#define AXGE_RX_BULKIN_QIFG 0x32
86/* Monitor mode status register */
87#define AXGE_MMSR 0x24
88#define MMSR_RWLC 0x02
89#define MMSR_RWMP 0x04
90#define MMSR_RWWF 0x08
91#define MMSR_RW_FLAG 0x10
92#define MMSR_PME_POL 0x20
93#define MMSR_PME_TYPE 0x40
94#define MMSR_PME_IND 0x80
114
95
96/* GPIO control/status register */
97#define AXGE_GPIOCR 0x25
98
99/* Ethernet PHY power & reset control register */
100#define AXGE_EPPRCR 0x26
101#define EPPRCR_BZ 0x0010
102#define EPPRCR_IPRL 0x0020
103#define EPPRCR_AUTODETACH 0x1000
104
105#define AXGE_RX_BULKIN_QCTRL 0x2e
106
115#define AXGE_CLK_SELECT 0x33
116#define AXGE_CLK_SELECT_BCS 0x01
117#define AXGE_CLK_SELECT_ACS 0x02
118#define AXGE_CLK_SELECT_ACSREQ 0x10
119#define AXGE_CLK_SELECT_ULR 0x08
120
107#define AXGE_CLK_SELECT 0x33
108#define AXGE_CLK_SELECT_BCS 0x01
109#define AXGE_CLK_SELECT_ACS 0x02
110#define AXGE_CLK_SELECT_ACSREQ 0x10
111#define AXGE_CLK_SELECT_ULR 0x08
112
121#define AXGE_RXCOE_CTL 0x34
122#define AXGE_RXCOE_IP 0x01
123#define AXGE_RXCOE_TCP 0x02
124#define AXGE_RXCOE_UDP 0x04
125#define AXGE_RXCOE_ICMP 0x08
126#define AXGE_RXCOE_IGMP 0x10
127#define AXGE_RXCOE_TCPV6 0x20
128#define AXGE_RXCOE_UDPV6 0x40
129#define AXGE_RXCOE_ICMV6 0x80
113/* COE Rx control register */
114#define AXGE_CRCR 0x34
115#define CRCR_IP 0x01
116#define CRCR_TCP 0x02
117#define CRCR_UDP 0x04
118#define CRCR_ICMP 0x08
119#define CRCR_IGMP 0x10
120#define CRCR_TCPV6 0x20
121#define CRCR_UDPV6 0x40
122#define CRCR_ICMPV6 0x80
130
123
131#define AXGE_TXCOE_CTL 0x35
132#define AXGE_TXCOE_IP 0x01
133#define AXGE_TXCOE_TCP 0x02
134#define AXGE_TXCOE_UDP 0x04
135#define AXGE_TXCOE_ICMP 0x08
136#define AXGE_TXCOE_IGMP 0x10
137#define AXGE_TXCOE_TCPV6 0x20
138#define AXGE_TXCOE_UDPV6 0x40
139#define AXGE_TXCOE_ICMV6 0x80
124/* COE Tx control register */
125#define AXGE_CTCR 0x35
126#define CTCR_IP 0x01
127#define CTCR_TCP 0x02
128#define CTCR_UDP 0x04
129#define CTCR_ICMP 0x08
130#define CTCR_IGMP 0x10
131#define CTCR_TCPV6 0x20
132#define CTCR_UDPV6 0x40
133#define CTCR_ICMPV6 0x80
140
134
141#define AXGE_PAUSE_WATERLVL_HIGH 0x54
142#define AXGE_PAUSE_WATERLVL_LOW 0x55
135/* Pause water level high register */
136#define AXGE_PWLHR 0x54
143
137
144#define AXGE_EEP_EFUSE_CORRECT 0x00
145#define AX88179_EEPROM_MAGIC 0x17900b95
138/* Pause water level low register */
139#define AXGE_PWLLR 0x55
146
147#define AXGE_CONFIG_IDX 0 /* config number 1 */
148#define AXGE_IFACE_IDX 0
149
140
141#define AXGE_CONFIG_IDX 0 /* config number 1 */
142#define AXGE_IFACE_IDX 0
143
150#define AXGE_RXHDR_CRC_ERR 0x80000000
151#define AXGE_RXHDR_L4_ERR (1 << 8)
152#define AXGE_RXHDR_L3_ERR (1 << 9)
153
154#define AXGE_RXHDR_L4_TYPE_ICMP 2
155#define AXGE_RXHDR_L4_TYPE_IGMP 3
156#define AXGE_RXHDR_L4_TYPE_TCMPV6 5
157
158#define AXGE_RXHDR_L3_TYPE_IP 1
159#define AXGE_RXHDR_L3_TYPE_IPV6 2
160
161#define AXGE_RXHDR_L4_TYPE_MASK 0x1c
144#define AXGE_RXHDR_L4_TYPE_MASK 0x1c
145#define AXGE_RXHDR_L4CSUM_ERR 1
146#define AXGE_RXHDR_L3CSUM_ERR 2
162#define AXGE_RXHDR_L4_TYPE_UDP 4
163#define AXGE_RXHDR_L4_TYPE_TCP 16
147#define AXGE_RXHDR_L4_TYPE_UDP 4
148#define AXGE_RXHDR_L4_TYPE_TCP 16
164#define AXGE_RXHDR_L3CSUM_ERR 2
165#define AXGE_RXHDR_L4CSUM_ERR 1
166#define AXGE_RXHDR_CRC_ERR 0x80000000
167#define AXGE_RXHDR_DROP_ERR 0x40000000
149#define AXGE_RXHDR_CRC_ERR 0x20000000
150#define AXGE_RXHDR_DROP_ERR 0x80000000
168
151
169struct axge_csum_hdr {
170 uint16_t cstatus;
171#define AXGE_CSUM_HDR_L4_CSUM_ERR 0x0001
172#define AXGE_CSUM_HDR_L3_CSUM_ERR 0x0002
173#define AXGE_CSUM_HDR_L4_TYPE_UDP 0x0004
174#define AXGE_CSUM_HDR_L4_TYPE_ICMP 0x0008
175#define AXGE_CSUM_HDR_L4_TYPE_IGMP 0x000C
176#define AXGE_CSUM_HDR_L4_TYPE_TCP 0x0010
177#define AXGE_CSUM_HDR_L4_TYPE_TCPV6 0x0014
178#define AXGE_CSUM_HDR_L4_TYPE_MASK 0x001C
179#define AXGE_CSUM_HDR_L3_TYPE_IPV4 0x0020
180#define AXGE_CSUM_HDR_L3_TYPE_IPV6 0x0040
181#define AXGE_CSUM_HDR_VLAN_MASK 0x0700
182 uint16_t len;
183#define AXGE_CSUM_HDR_LEN_MASK 0x1FFF
184#define AXGE_CSUM_HDR_CRC_ERR 0x2000
185#define AXGE_CSUM_HDR_MII_ERR 0x4000
186#define AXGE_CSUM_HDR_DROP 0x8000
187} __packed;
188
189#define AXGE_CSUM_RXBYTES(x) ((x) & AXGE_CSUM_HDR_LEN_MASK)
190
191#define GET_MII(sc) uether_getmii(&(sc)->sc_ue)
192
193/* The interrupt endpoint is currently unused by the ASIX part. */
194enum {
195 AXGE_BULK_DT_WR,
196 AXGE_BULK_DT_RD,
197 AXGE_N_TRANSFER,
198};

--- 14 unchanged lines hidden --- 		152#define GET_MII(sc) uether_getmii(&(sc)->sc_ue)
153
154/* The interrupt endpoint is currently unused by the ASIX part. */
155enum {
156 AXGE_BULK_DT_WR,
157 AXGE_BULK_DT_RD,
158 AXGE_N_TRANSFER,
159};

--- 14 unchanged lines hidden ---