1/*- 2 * Copyright (c) 2013-2014 Kevin Lo 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 11 unchanged lines hidden (view full) --- 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27#include <sys/cdefs.h> |
28__FBSDID("$FreeBSD: head/sys/dev/usb/net/if_axge.c 266738 2014-05-27 08:14:54Z kevlo $"); |
29 30/* 31 * ASIX Electronics AX88178A/AX88179 USB 2.0/3.0 gigabit ethernet driver. 32 */ 33 34#include <sys/param.h> 35#include <sys/systm.h> 36#include <sys/bus.h> --- 24 unchanged lines hidden (view full) --- 61/* 62 * Various supported device vendors/products. 63 */ 64 65static const STRUCT_USB_HOST_ID axge_devs[] = { 66#define AXGE_DEV(v,p) { USB_VP(USB_VENDOR_##v, USB_PRODUCT_##v##_##p) } 67 AXGE_DEV(ASIX, AX88178A), 68 AXGE_DEV(ASIX, AX88179), |
69 AXGE_DEV(DLINK, DUB1312), 70 AXGE_DEV(SITECOMEU, LN032), |
71#undef AXGE_DEV 72}; 73 74static const struct { 75 uint8_t ctrl; 76 uint8_t timer_l; 77 uint8_t timer_h; 78 uint8_t size; --- 25 unchanged lines hidden (view full) --- 104static uether_fn_t axge_tick; 105static uether_fn_t axge_setmulti; 106static uether_fn_t axge_setpromisc; 107 108static int axge_read_mem(struct axge_softc *, uint8_t, uint16_t, 109 uint16_t, void *, int); 110static void axge_write_mem(struct axge_softc *, uint8_t, uint16_t, 111 uint16_t, void *, int); |
112static uint8_t axge_read_cmd_1(struct axge_softc *, uint8_t, uint16_t); |
113static uint16_t axge_read_cmd_2(struct axge_softc *, uint8_t, uint16_t, 114 uint16_t); 115static void axge_write_cmd_1(struct axge_softc *, uint8_t, uint16_t, |
116 uint8_t); |
117static void axge_write_cmd_2(struct axge_softc *, uint8_t, uint16_t, 118 uint16_t, uint16_t); 119static void axge_chip_init(struct axge_softc *); 120static void axge_reset(struct axge_softc *); 121 122static int axge_attach_post_sub(struct usb_ether *); 123static int axge_ifmedia_upd(struct ifnet *); 124static void axge_ifmedia_sts(struct ifnet *, struct ifmediareq *); 125static int axge_ioctl(struct ifnet *, u_long, caddr_t); 126static int axge_rx_frame(struct usb_ether *, struct usb_page_cache *, int); 127static int axge_rxeof(struct usb_ether *, struct usb_page_cache *, |
128 unsigned int, unsigned int, uint32_t); |
129static void axge_csum_cfg(struct usb_ether *); 130 131#define AXGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 132 133#ifdef USB_DEBUG 134static int axge_debug = 0; 135 136static SYSCTL_NODE(_hw_usb, OID_AUTO, axge, CTLFLAG_RW, 0, "USB axge"); 137SYSCTL_INT(_hw_usb_axge, OID_AUTO, debug, CTLFLAG_RW, &axge_debug, 0, 138 "Debug level"); 139#endif 140 141static const struct usb_config axge_config[AXGE_N_TRANSFER] = { 142 [AXGE_BULK_DT_WR] = { 143 .type = UE_BULK, 144 .endpoint = UE_ADDR_ANY, 145 .direction = UE_DIR_OUT, 146 .frames = 16, |
147 .bufsize = 16 * MCLBYTES, |
148 .flags = {.pipe_bof = 1,.force_short_xfer = 1,}, 149 .callback = axge_bulk_write_callback, 150 .timeout = 10000, /* 10 seconds */ 151 }, 152 [AXGE_BULK_DT_RD] = { 153 .type = UE_BULK, 154 .endpoint = UE_ADDR_ANY, 155 .direction = UE_DIR_IN, --- 79 unchanged lines hidden (view full) --- 235 USETW(req.wLength, len); 236 237 if (uether_do_request(&sc->sc_ue, &req, buf, 1000)) { 238 /* Error ignored. */ 239 } 240} 241 242static uint8_t |
243axge_read_cmd_1(struct axge_softc *sc, uint8_t cmd, uint16_t reg) |
244{ 245 uint8_t val; 246 |
247 axge_read_mem(sc, cmd, 1, reg, &val, 1); |
248 return (val); 249} 250 251static uint16_t 252axge_read_cmd_2(struct axge_softc *sc, uint8_t cmd, uint16_t index, 253 uint16_t reg) 254{ 255 uint8_t val[2]; 256 257 axge_read_mem(sc, cmd, index, reg, &val, 2); 258 return (UGETW(val)); 259} 260 261static void |
262axge_write_cmd_1(struct axge_softc *sc, uint8_t cmd, uint16_t reg, uint8_t val) |
263{ |
264 axge_write_mem(sc, cmd, 1, reg, &val, 1); |
265} 266 267static void 268axge_write_cmd_2(struct axge_softc *sc, uint8_t cmd, uint16_t index, 269 uint16_t reg, uint16_t val) 270{ 271 uint8_t temp[2]; 272 --- 76 unchanged lines hidden (view full) --- 349 break; 350 } 351 } 352 353 /* Lost link, do nothing. */ 354 if ((sc->sc_flags & AXGE_FLAG_LINK) == 0) 355 goto done; 356 |
357 link_status = axge_read_cmd_1(sc, AXGE_ACCESS_MAC, AXGE_PLSR); |
358 359 val = 0; 360 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { |
361 val |= MSR_FD; |
362 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) |
363 val |= MSR_TFC; |
364 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) |
365 val |= MSR_RFC; |
366 } |
367 val |= MSR_RE; |
368 switch (IFM_SUBTYPE(mii->mii_media_active)) { 369 case IFM_1000_T: |
370 val |= MSR_GM | MSR_EN_125MHZ; 371 if (link_status & PLSR_USB_SS) |
372 memcpy(tmp, &axge_bulk_size[0], 5); |
373 else if (link_status & PLSR_USB_HS) |
374 memcpy(tmp, &axge_bulk_size[1], 5); 375 else 376 memcpy(tmp, &axge_bulk_size[3], 5); 377 break; 378 case IFM_100_TX: |
379 val |= MSR_PS; 380 if (link_status & (PLSR_USB_SS | PLSR_USB_HS)) |
381 memcpy(tmp, &axge_bulk_size[2], 5); 382 else 383 memcpy(tmp, &axge_bulk_size[3], 5); 384 break; 385 case IFM_10_T: 386 memcpy(tmp, &axge_bulk_size[3], 5); 387 break; 388 } 389 /* Rx bulk configuration. */ 390 axge_write_mem(sc, AXGE_ACCESS_MAC, 5, AXGE_RX_BULKIN_QCTRL, tmp, 5); |
391 axge_write_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_MSR, val); |
392done: 393 if (!locked) 394 AXGE_UNLOCK(sc); 395} 396 397static void 398axge_chip_init(struct axge_softc *sc) 399{ 400 /* Power up ethernet PHY. */ |
401 axge_write_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_EPPRCR, 0); 402 axge_write_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_EPPRCR, EPPRCR_IPRL); |
403 uether_pause(&sc->sc_ue, hz / 4); |
404 axge_write_cmd_1(sc, AXGE_ACCESS_MAC, AXGE_CLK_SELECT, |
405 AXGE_CLK_SELECT_ACS | AXGE_CLK_SELECT_BCS); 406 uether_pause(&sc->sc_ue, hz / 10); 407} 408 409static void 410axge_reset(struct axge_softc *sc) 411{ 412 struct usb_config_descriptor *cd; --- 18 unchanged lines hidden (view full) --- 431{ 432 struct axge_softc *sc; 433 434 sc = uether_getsc(ue); 435 sc->sc_phyno = 3; 436 437 /* Initialize controller and get station address. */ 438 axge_chip_init(sc); |
439 axge_read_mem(sc, AXGE_ACCESS_MAC, ETHER_ADDR_LEN, AXGE_NIDR, |
440 ue->ue_eaddr, ETHER_ADDR_LEN); 441} 442 443static int 444axge_attach_post_sub(struct usb_ether *ue) 445{ 446 struct axge_softc *sc; 447 struct ifnet *ifp; --- 152 unchanged lines hidden (view full) --- 600 601 sc = usbd_xfer_softc(xfer); 602 ue = &sc->sc_ue; 603 usbd_xfer_status(xfer, &actlen, NULL, NULL, NULL); 604 605 switch (USB_GET_STATE(xfer)) { 606 case USB_ST_TRANSFERRED: 607 pc = usbd_xfer_get_frame(xfer, 0); |
608 if (axge_rx_frame(ue, pc, actlen) != 0) 609 goto tr_setup; |
610 611 /* FALLTHROUGH */ 612 case USB_ST_SETUP: 613tr_setup: 614 usbd_xfer_set_frame_len(xfer, 0, usbd_xfer_max_len(xfer)); 615 usbd_transfer_submit(xfer); 616 uether_rxflush(ue); 617 return; --- 11 unchanged lines hidden (view full) --- 629static void 630axge_bulk_write_callback(struct usb_xfer *xfer, usb_error_t error) 631{ 632 struct axge_softc *sc; 633 struct ifnet *ifp; 634 struct usb_page_cache *pc; 635 struct mbuf *m; 636 uint32_t txhdr; |
637 int nframes, pos; |
638 639 sc = usbd_xfer_softc(xfer); 640 ifp = uether_getifp(&sc->sc_ue); 641 642 switch (USB_GET_STATE(xfer)) { 643 case USB_ST_TRANSFERRED: 644 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 645 /* FALLTHROUGH */ --- 10 unchanged lines hidden (view full) --- 656 657 for (nframes = 0; nframes < 16 && 658 !IFQ_DRV_IS_EMPTY(&ifp->if_snd); nframes++) { 659 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 660 if (m == NULL) 661 break; 662 usbd_xfer_set_frame_offset(xfer, nframes * MCLBYTES, 663 nframes); |
664 pos = 0; |
665 pc = usbd_xfer_get_frame(xfer, nframes); |
666 txhdr = htole32(m->m_pkthdr.len); |
667 usbd_copy_in(pc, 0, &txhdr, sizeof(txhdr)); |
668 txhdr = 0; 669 txhdr = htole32(txhdr); 670 usbd_copy_in(pc, 4, &txhdr, sizeof(txhdr)); 671 pos += 8; 672 usbd_m_copy_in(pc, pos, m, 0, m->m_pkthdr.len); 673 pos += m->m_pkthdr.len; 674 if ((pos % usbd_xfer_max_framelen(xfer)) == 0) 675 txhdr |= 0x80008000; |
676 |
677 /* 678 * XXX 679 * Update TX packet counter here. This is not 680 * correct way but it seems that there is no way 681 * to know how many packets are sent at the end 682 * of transfer because controller combines 683 * multiple writes into single one if there is 684 * room in TX buffer of controller. --- 4 unchanged lines hidden (view full) --- 689 * if there's a BPF listener, bounce a copy 690 * of this frame to him: 691 */ 692 BPF_MTAP(ifp, m); 693 694 m_freem(m); 695 696 /* Set frame length. */ |
697 usbd_xfer_set_frame_len(xfer, nframes, pos); |
698 } 699 if (nframes != 0) { 700 usbd_xfer_set_frames(xfer, nframes); 701 usbd_transfer_submit(xfer); 702 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 703 } 704 return; 705 /* NOTREACHED */ --- 38 unchanged lines hidden (view full) --- 744 uint16_t rxmode; 745 uint8_t hashtbl[8] = { 0, 0, 0, 0, 0, 0, 0, 0 }; 746 747 sc = uether_getsc(ue); 748 ifp = uether_getifp(ue); 749 h = 0; 750 AXGE_LOCK_ASSERT(sc, MA_OWNED); 751 |
752 rxmode = axge_read_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_RCR); |
753 if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) { |
754 rxmode |= RCR_AMALL; 755 axge_write_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_RCR, rxmode); |
756 return; 757 } |
758 rxmode &= ~RCR_AMALL; |
759 760 if_maddr_rlock(ifp); 761 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 762 if (ifma->ifma_addr->sa_family != AF_LINK) 763 continue; 764 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 765 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 766 hashtbl[h / 8] |= 1 << (h % 8); 767 } 768 if_maddr_runlock(ifp); 769 |
770 axge_write_mem(sc, AXGE_ACCESS_MAC, 8, AXGE_MFA, (void *)&hashtbl, 8); 771 axge_write_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_RCR, rxmode); |
772} 773 774static void 775axge_setpromisc(struct usb_ether *ue) 776{ 777 struct axge_softc *sc; 778 struct ifnet *ifp; 779 uint16_t rxmode; 780 781 sc = uether_getsc(ue); 782 ifp = uether_getifp(ue); |
783 rxmode = axge_read_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_RCR); |
784 785 if (ifp->if_flags & IFF_PROMISC) |
786 rxmode |= RCR_PRO; |
787 else |
788 rxmode &= ~RCR_PRO; |
789 |
790 axge_write_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_RCR, rxmode); |
791 axge_setmulti(ue); 792} 793 794static void 795axge_start(struct usb_ether *ue) 796{ 797 struct axge_softc *sc; 798 --- 22 unchanged lines hidden (view full) --- 821 /* 822 * Cancel pending I/O and free all RX/TX buffers. 823 */ 824 axge_stop(ue); 825 826 axge_reset(sc); 827 828 /* Set MAC address. */ |
829 axge_write_mem(sc, AXGE_ACCESS_MAC, ETHER_ADDR_LEN, AXGE_NIDR, |
830 IF_LLADDR(ifp), ETHER_ADDR_LEN); 831 |
832 axge_write_cmd_1(sc, AXGE_ACCESS_MAC, AXGE_PWLLR, 0x34); 833 axge_write_cmd_1(sc, AXGE_ACCESS_MAC, AXGE_PWLHR, 0x52); |
834 835 /* Configure TX/RX checksum offloading. */ 836 axge_csum_cfg(ue); 837 838 /* Configure RX settings. */ |
839 rxmode = (RCR_AM | RCR_SO | RCR_DROP_CRCE); 840 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 841 rxmode |= RCR_IPE; |
842 843 /* If we want promiscuous mode, set the allframes bit. */ 844 if (ifp->if_flags & IFF_PROMISC) |
845 rxmode |= RCR_PRO; |
846 847 if (ifp->if_flags & IFF_BROADCAST) |
848 rxmode |= RCR_AB; |
849 |
850 axge_write_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_RCR, rxmode); |
851 |
852 axge_write_cmd_1(sc, AXGE_ACCESS_MAC, AXGE_MMSR, 853 MMSR_PME_TYPE | MMSR_PME_POL | MMSR_RWMP); 854 |
855 /* Load the multicast filter. */ 856 axge_setmulti(ue); 857 858 usbd_xfer_set_stall(sc->sc_xfer[AXGE_BULK_DT_WR]); 859 860 ifp->if_drv_flags |= IFF_DRV_RUNNING; 861 /* Switch to selected media. */ 862 axge_ifmedia_upd(ifp); --- 61 unchanged lines hidden (view full) --- 924 error = uether_ioctl(ifp, cmd, data); 925 926 return (error); 927} 928 929static int 930axge_rx_frame(struct usb_ether *ue, struct usb_page_cache *pc, int actlen) 931{ |
932 int error, pos; |
933 int pkt_cnt; |
934 uint32_t rxhdr, pkt_hdr; |
935 uint16_t hdr_off; |
936 uint16_t len, pktlen; |
937 938 pos = 0; 939 len = 0; 940 error = 0; 941 942 usbd_copy_out(pc, actlen - sizeof(rxhdr), &rxhdr, sizeof(rxhdr)); |
943 rxhdr = le32toh(rxhdr); 944 945 pkt_cnt = (uint16_t)rxhdr; 946 hdr_off = (uint16_t)(rxhdr >> 16); 947 |
948 usbd_copy_out(pc, hdr_off, &pkt_hdr, sizeof(pkt_hdr)); |
949 |
950 while (pkt_cnt > 0) { 951 if ((int)(sizeof(pkt_hdr)) > actlen) { |
952 error = EINVAL; 953 break; 954 } |
955 pkt_hdr = le32toh(pkt_hdr); 956 pktlen = (pkt_hdr >> 16) & 0x1fff; 957 if ((pkt_hdr & AXGE_RXHDR_CRC_ERR) || 958 (pkt_hdr & AXGE_RXHDR_DROP_ERR)) 959 ue->ue_ifp->if_ierrors++; 960 axge_rxeof(ue, pc, pos + 2, pktlen - 6, pkt_hdr); 961 len = (pktlen + 7) & ~7; 962 pos += len; 963 pkt_hdr++; 964 pkt_cnt--; |
965 } 966 967 if (error != 0) 968 ue->ue_ifp->if_ierrors++; 969 return (error); 970} 971 972static int 973axge_rxeof(struct usb_ether *ue, struct usb_page_cache *pc, |
974 unsigned int offset, unsigned int len, uint32_t pkt_hdr) |
975{ 976 struct ifnet *ifp; 977 struct mbuf *m; 978 979 ifp = ue->ue_ifp; 980 if (len < ETHER_HDR_LEN || len > MCLBYTES - ETHER_ALIGN) { 981 ifp->if_ierrors++; 982 return (EINVAL); --- 8 unchanged lines hidden (view full) --- 991 m_adj(m, ETHER_ALIGN); 992 993 usbd_copy_out(pc, offset, mtod(m, uint8_t *), len); 994 995 ifp->if_ipackets++; 996 m->m_pkthdr.rcvif = ifp; 997 m->m_pkthdr.len = m->m_len = len; 998 |
999 if ((pkt_hdr & (AXGE_RXHDR_L4CSUM_ERR | AXGE_RXHDR_L3CSUM_ERR)) == 0) { 1000 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED | CSUM_IP_VALID; 1001 if ((pkt_hdr & AXGE_RXHDR_L4_TYPE_MASK) == 1002 AXGE_RXHDR_L4_TYPE_TCP || 1003 (pkt_hdr & AXGE_RXHDR_L4_TYPE_MASK) == 1004 AXGE_RXHDR_L4_TYPE_UDP) { 1005 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID | 1006 CSUM_PSEUDO_HDR; 1007 m->m_pkthdr.csum_data = 0xffff; |
1008 } 1009 } 1010 1011 _IF_ENQUEUE(&ue->ue_rxq, m); 1012 return (0); 1013} 1014 1015static void --- 4 unchanged lines hidden (view full) --- 1020 uint8_t csum; 1021 1022 sc = uether_getsc(ue); 1023 AXGE_LOCK_ASSERT(sc, MA_OWNED); 1024 ifp = uether_getifp(ue); 1025 1026 csum = 0; 1027 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) |
1028 csum |= CTCR_IP | CTCR_TCP | CTCR_UDP; 1029 axge_write_cmd_1(sc, AXGE_ACCESS_MAC, AXGE_CTCR, csum); |
1030 1031 csum = 0; 1032 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) |
1033 csum |= CRCR_IP | CRCR_TCP | CRCR_UDP; 1034 axge_write_cmd_1(sc, AXGE_ACCESS_MAC, AXGE_CRCR, csum); |
1035} |