1/*-
2 * Copyright (c) 2013-2014 Kevin Lo
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27#include <sys/cdefs.h>
| 1/*-
2 * Copyright (c) 2013-2014 Kevin Lo
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27#include <sys/cdefs.h>
|
28__FBSDID("$FreeBSD: head/sys/dev/usb/net/if_axge.c 266490 2014-05-21 08:09:44Z kevlo $");
| 28__FBSDID("$FreeBSD: head/sys/dev/usb/net/if_axge.c 266738 2014-05-27 08:14:54Z kevlo $");
|
29
30/*
31 * ASIX Electronics AX88178A/AX88179 USB 2.0/3.0 gigabit ethernet driver.
32 */
33
34#include <sys/param.h>
35#include <sys/systm.h>
36#include <sys/bus.h>
37#include <sys/condvar.h>
38#include <sys/kernel.h>
39#include <sys/lock.h>
40#include <sys/module.h>
41#include <sys/mutex.h>
42#include <sys/socket.h>
43#include <sys/sysctl.h>
44#include <sys/unistd.h>
45
46#include <net/if.h>
47#include <net/if_var.h>
48
49#include <dev/usb/usb.h>
50#include <dev/usb/usbdi.h>
51#include <dev/usb/usbdi_util.h>
52#include "usbdevs.h"
53
54#define USB_DEBUG_VAR axge_debug
55#include <dev/usb/usb_debug.h>
56#include <dev/usb/usb_process.h>
57
58#include <dev/usb/net/usb_ethernet.h>
59#include <dev/usb/net/if_axgereg.h>
60
61/*
62 * Various supported device vendors/products.
63 */
64
65static const STRUCT_USB_HOST_ID axge_devs[] = {
66#define AXGE_DEV(v,p) { USB_VP(USB_VENDOR_##v, USB_PRODUCT_##v##_##p) }
67 AXGE_DEV(ASIX, AX88178A),
68 AXGE_DEV(ASIX, AX88179),
| 29
30/*
31 * ASIX Electronics AX88178A/AX88179 USB 2.0/3.0 gigabit ethernet driver.
32 */
33
34#include <sys/param.h>
35#include <sys/systm.h>
36#include <sys/bus.h>
37#include <sys/condvar.h>
38#include <sys/kernel.h>
39#include <sys/lock.h>
40#include <sys/module.h>
41#include <sys/mutex.h>
42#include <sys/socket.h>
43#include <sys/sysctl.h>
44#include <sys/unistd.h>
45
46#include <net/if.h>
47#include <net/if_var.h>
48
49#include <dev/usb/usb.h>
50#include <dev/usb/usbdi.h>
51#include <dev/usb/usbdi_util.h>
52#include "usbdevs.h"
53
54#define USB_DEBUG_VAR axge_debug
55#include <dev/usb/usb_debug.h>
56#include <dev/usb/usb_process.h>
57
58#include <dev/usb/net/usb_ethernet.h>
59#include <dev/usb/net/if_axgereg.h>
60
61/*
62 * Various supported device vendors/products.
63 */
64
65static const STRUCT_USB_HOST_ID axge_devs[] = {
66#define AXGE_DEV(v,p) { USB_VP(USB_VENDOR_##v, USB_PRODUCT_##v##_##p) }
67 AXGE_DEV(ASIX, AX88178A),
68 AXGE_DEV(ASIX, AX88179),
|
69 /* AXGE_DEV(SITECOMEU, LN032), */
| 69 AXGE_DEV(DLINK, DUB1312),
70 AXGE_DEV(SITECOMEU, LN032),
|
70#undef AXGE_DEV
71};
72
73static const struct {
74 uint8_t ctrl;
75 uint8_t timer_l;
76 uint8_t timer_h;
77 uint8_t size;
78 uint8_t ifg;
79} axge_bulk_size[] = {
80 { 7, 0x4f, 0x00, 0x12, 0xff },
81 { 7, 0x20, 0x03, 0x16, 0xff },
82 { 7, 0xae, 0x07, 0x18, 0xff },
83 { 7, 0xcc, 0x4c, 0x18, 0x08 }
84};
85
86/* prototypes */
87
88static device_probe_t axge_probe;
89static device_attach_t axge_attach;
90static device_detach_t axge_detach;
91
92static usb_callback_t axge_bulk_read_callback;
93static usb_callback_t axge_bulk_write_callback;
94
95static miibus_readreg_t axge_miibus_readreg;
96static miibus_writereg_t axge_miibus_writereg;
97static miibus_statchg_t axge_miibus_statchg;
98
99static uether_fn_t axge_attach_post;
100static uether_fn_t axge_init;
101static uether_fn_t axge_stop;
102static uether_fn_t axge_start;
103static uether_fn_t axge_tick;
104static uether_fn_t axge_setmulti;
105static uether_fn_t axge_setpromisc;
106
107static int axge_read_mem(struct axge_softc *, uint8_t, uint16_t,
108 uint16_t, void *, int);
109static void axge_write_mem(struct axge_softc *, uint8_t, uint16_t,
110 uint16_t, void *, int);
| 71#undef AXGE_DEV
72};
73
74static const struct {
75 uint8_t ctrl;
76 uint8_t timer_l;
77 uint8_t timer_h;
78 uint8_t size;
79 uint8_t ifg;
80} axge_bulk_size[] = {
81 { 7, 0x4f, 0x00, 0x12, 0xff },
82 { 7, 0x20, 0x03, 0x16, 0xff },
83 { 7, 0xae, 0x07, 0x18, 0xff },
84 { 7, 0xcc, 0x4c, 0x18, 0x08 }
85};
86
87/* prototypes */
88
89static device_probe_t axge_probe;
90static device_attach_t axge_attach;
91static device_detach_t axge_detach;
92
93static usb_callback_t axge_bulk_read_callback;
94static usb_callback_t axge_bulk_write_callback;
95
96static miibus_readreg_t axge_miibus_readreg;
97static miibus_writereg_t axge_miibus_writereg;
98static miibus_statchg_t axge_miibus_statchg;
99
100static uether_fn_t axge_attach_post;
101static uether_fn_t axge_init;
102static uether_fn_t axge_stop;
103static uether_fn_t axge_start;
104static uether_fn_t axge_tick;
105static uether_fn_t axge_setmulti;
106static uether_fn_t axge_setpromisc;
107
108static int axge_read_mem(struct axge_softc *, uint8_t, uint16_t,
109 uint16_t, void *, int);
110static void axge_write_mem(struct axge_softc *, uint8_t, uint16_t,
111 uint16_t, void *, int);
|
111static uint8_t axge_read_cmd_1(struct axge_softc *, uint8_t, uint16_t,
112 uint16_t);
| 112static uint8_t axge_read_cmd_1(struct axge_softc *, uint8_t, uint16_t);
|
113static uint16_t axge_read_cmd_2(struct axge_softc *, uint8_t, uint16_t,
114 uint16_t);
115static void axge_write_cmd_1(struct axge_softc *, uint8_t, uint16_t,
| 113static uint16_t axge_read_cmd_2(struct axge_softc *, uint8_t, uint16_t,
114 uint16_t);
115static void axge_write_cmd_1(struct axge_softc *, uint8_t, uint16_t,
|
116 uint16_t, uint8_t);
| 116 uint8_t);
|
117static void axge_write_cmd_2(struct axge_softc *, uint8_t, uint16_t,
118 uint16_t, uint16_t);
119static void axge_chip_init(struct axge_softc *);
120static void axge_reset(struct axge_softc *);
121
122static int axge_attach_post_sub(struct usb_ether *);
123static int axge_ifmedia_upd(struct ifnet *);
124static void axge_ifmedia_sts(struct ifnet *, struct ifmediareq *);
125static int axge_ioctl(struct ifnet *, u_long, caddr_t);
126static int axge_rx_frame(struct usb_ether *, struct usb_page_cache *, int);
127static int axge_rxeof(struct usb_ether *, struct usb_page_cache *,
| 117static void axge_write_cmd_2(struct axge_softc *, uint8_t, uint16_t,
118 uint16_t, uint16_t);
119static void axge_chip_init(struct axge_softc *);
120static void axge_reset(struct axge_softc *);
121
122static int axge_attach_post_sub(struct usb_ether *);
123static int axge_ifmedia_upd(struct ifnet *);
124static void axge_ifmedia_sts(struct ifnet *, struct ifmediareq *);
125static int axge_ioctl(struct ifnet *, u_long, caddr_t);
126static int axge_rx_frame(struct usb_ether *, struct usb_page_cache *, int);
127static int axge_rxeof(struct usb_ether *, struct usb_page_cache *,
|
128 unsigned int, unsigned int, struct axge_csum_hdr *);
| 128 unsigned int, unsigned int, uint32_t);
|
129static void axge_csum_cfg(struct usb_ether *);
130
131#define AXGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
132
133#ifdef USB_DEBUG
134static int axge_debug = 0;
135
136static SYSCTL_NODE(_hw_usb, OID_AUTO, axge, CTLFLAG_RW, 0, "USB axge");
137SYSCTL_INT(_hw_usb_axge, OID_AUTO, debug, CTLFLAG_RW, &axge_debug, 0,
138 "Debug level");
139#endif
140
141static const struct usb_config axge_config[AXGE_N_TRANSFER] = {
142 [AXGE_BULK_DT_WR] = {
143 .type = UE_BULK,
144 .endpoint = UE_ADDR_ANY,
145 .direction = UE_DIR_OUT,
146 .frames = 16,
| 129static void axge_csum_cfg(struct usb_ether *);
130
131#define AXGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
132
133#ifdef USB_DEBUG
134static int axge_debug = 0;
135
136static SYSCTL_NODE(_hw_usb, OID_AUTO, axge, CTLFLAG_RW, 0, "USB axge");
137SYSCTL_INT(_hw_usb_axge, OID_AUTO, debug, CTLFLAG_RW, &axge_debug, 0,
138 "Debug level");
139#endif
140
141static const struct usb_config axge_config[AXGE_N_TRANSFER] = {
142 [AXGE_BULK_DT_WR] = {
143 .type = UE_BULK,
144 .endpoint = UE_ADDR_ANY,
145 .direction = UE_DIR_OUT,
146 .frames = 16,
|
147 .bufsize = 16 * (MCLBYTES + 16),
| 147 .bufsize = 16 * MCLBYTES,
|
148 .flags = {.pipe_bof = 1,.force_short_xfer = 1,},
149 .callback = axge_bulk_write_callback,
150 .timeout = 10000, /* 10 seconds */
151 },
152 [AXGE_BULK_DT_RD] = {
153 .type = UE_BULK,
154 .endpoint = UE_ADDR_ANY,
155 .direction = UE_DIR_IN,
156 .bufsize = 20480,
157 .flags = {.pipe_bof = 1,.short_xfer_ok = 1,},
158 .callback = axge_bulk_read_callback,
159 .timeout = 0, /* no timeout */
160 },
161};
162
163static device_method_t axge_methods[] = {
164 /* Device interface. */
165 DEVMETHOD(device_probe, axge_probe),
166 DEVMETHOD(device_attach, axge_attach),
167 DEVMETHOD(device_detach, axge_detach),
168
169 /* MII interface. */
170 DEVMETHOD(miibus_readreg, axge_miibus_readreg),
171 DEVMETHOD(miibus_writereg, axge_miibus_writereg),
172 DEVMETHOD(miibus_statchg, axge_miibus_statchg),
173
174 DEVMETHOD_END
175};
176
177static driver_t axge_driver = {
178 .name = "axge",
179 .methods = axge_methods,
180 .size = sizeof(struct axge_softc),
181};
182
183static devclass_t axge_devclass;
184
185DRIVER_MODULE(axge, uhub, axge_driver, axge_devclass, NULL, NULL);
186DRIVER_MODULE(miibus, axge, miibus_driver, miibus_devclass, NULL, NULL);
187MODULE_DEPEND(axge, uether, 1, 1, 1);
188MODULE_DEPEND(axge, usb, 1, 1, 1);
189MODULE_DEPEND(axge, ether, 1, 1, 1);
190MODULE_DEPEND(axge, miibus, 1, 1, 1);
191MODULE_VERSION(axge, 1);
192
193static const struct usb_ether_methods axge_ue_methods = {
194 .ue_attach_post = axge_attach_post,
195 .ue_attach_post_sub = axge_attach_post_sub,
196 .ue_start = axge_start,
197 .ue_init = axge_init,
198 .ue_stop = axge_stop,
199 .ue_tick = axge_tick,
200 .ue_setmulti = axge_setmulti,
201 .ue_setpromisc = axge_setpromisc,
202 .ue_mii_upd = axge_ifmedia_upd,
203 .ue_mii_sts = axge_ifmedia_sts,
204};
205
206static int
207axge_read_mem(struct axge_softc *sc, uint8_t cmd, uint16_t index,
208 uint16_t val, void *buf, int len)
209{
210 struct usb_device_request req;
211
212 AXGE_LOCK_ASSERT(sc, MA_OWNED);
213
214 req.bmRequestType = UT_READ_VENDOR_DEVICE;
215 req.bRequest = cmd;
216 USETW(req.wValue, val);
217 USETW(req.wIndex, index);
218 USETW(req.wLength, len);
219
220 return (uether_do_request(&sc->sc_ue, &req, buf, 1000));
221}
222
223static void
224axge_write_mem(struct axge_softc *sc, uint8_t cmd, uint16_t index,
225 uint16_t val, void *buf, int len)
226{
227 struct usb_device_request req;
228
229 AXGE_LOCK_ASSERT(sc, MA_OWNED);
230
231 req.bmRequestType = UT_WRITE_VENDOR_DEVICE;
232 req.bRequest = cmd;
233 USETW(req.wValue, val);
234 USETW(req.wIndex, index);
235 USETW(req.wLength, len);
236
237 if (uether_do_request(&sc->sc_ue, &req, buf, 1000)) {
238 /* Error ignored. */
239 }
240}
241
242static uint8_t
| 148 .flags = {.pipe_bof = 1,.force_short_xfer = 1,},
149 .callback = axge_bulk_write_callback,
150 .timeout = 10000, /* 10 seconds */
151 },
152 [AXGE_BULK_DT_RD] = {
153 .type = UE_BULK,
154 .endpoint = UE_ADDR_ANY,
155 .direction = UE_DIR_IN,
156 .bufsize = 20480,
157 .flags = {.pipe_bof = 1,.short_xfer_ok = 1,},
158 .callback = axge_bulk_read_callback,
159 .timeout = 0, /* no timeout */
160 },
161};
162
163static device_method_t axge_methods[] = {
164 /* Device interface. */
165 DEVMETHOD(device_probe, axge_probe),
166 DEVMETHOD(device_attach, axge_attach),
167 DEVMETHOD(device_detach, axge_detach),
168
169 /* MII interface. */
170 DEVMETHOD(miibus_readreg, axge_miibus_readreg),
171 DEVMETHOD(miibus_writereg, axge_miibus_writereg),
172 DEVMETHOD(miibus_statchg, axge_miibus_statchg),
173
174 DEVMETHOD_END
175};
176
177static driver_t axge_driver = {
178 .name = "axge",
179 .methods = axge_methods,
180 .size = sizeof(struct axge_softc),
181};
182
183static devclass_t axge_devclass;
184
185DRIVER_MODULE(axge, uhub, axge_driver, axge_devclass, NULL, NULL);
186DRIVER_MODULE(miibus, axge, miibus_driver, miibus_devclass, NULL, NULL);
187MODULE_DEPEND(axge, uether, 1, 1, 1);
188MODULE_DEPEND(axge, usb, 1, 1, 1);
189MODULE_DEPEND(axge, ether, 1, 1, 1);
190MODULE_DEPEND(axge, miibus, 1, 1, 1);
191MODULE_VERSION(axge, 1);
192
193static const struct usb_ether_methods axge_ue_methods = {
194 .ue_attach_post = axge_attach_post,
195 .ue_attach_post_sub = axge_attach_post_sub,
196 .ue_start = axge_start,
197 .ue_init = axge_init,
198 .ue_stop = axge_stop,
199 .ue_tick = axge_tick,
200 .ue_setmulti = axge_setmulti,
201 .ue_setpromisc = axge_setpromisc,
202 .ue_mii_upd = axge_ifmedia_upd,
203 .ue_mii_sts = axge_ifmedia_sts,
204};
205
206static int
207axge_read_mem(struct axge_softc *sc, uint8_t cmd, uint16_t index,
208 uint16_t val, void *buf, int len)
209{
210 struct usb_device_request req;
211
212 AXGE_LOCK_ASSERT(sc, MA_OWNED);
213
214 req.bmRequestType = UT_READ_VENDOR_DEVICE;
215 req.bRequest = cmd;
216 USETW(req.wValue, val);
217 USETW(req.wIndex, index);
218 USETW(req.wLength, len);
219
220 return (uether_do_request(&sc->sc_ue, &req, buf, 1000));
221}
222
223static void
224axge_write_mem(struct axge_softc *sc, uint8_t cmd, uint16_t index,
225 uint16_t val, void *buf, int len)
226{
227 struct usb_device_request req;
228
229 AXGE_LOCK_ASSERT(sc, MA_OWNED);
230
231 req.bmRequestType = UT_WRITE_VENDOR_DEVICE;
232 req.bRequest = cmd;
233 USETW(req.wValue, val);
234 USETW(req.wIndex, index);
235 USETW(req.wLength, len);
236
237 if (uether_do_request(&sc->sc_ue, &req, buf, 1000)) {
238 /* Error ignored. */
239 }
240}
241
242static uint8_t
|
243axge_read_cmd_1(struct axge_softc *sc, uint8_t cmd, uint16_t index,
244 uint16_t reg)
| 243axge_read_cmd_1(struct axge_softc *sc, uint8_t cmd, uint16_t reg)
|
245{
246 uint8_t val;
247
| 244{
245 uint8_t val;
246
|
248 axge_read_mem(sc, cmd, index, reg, &val, 1);
| 247 axge_read_mem(sc, cmd, 1, reg, &val, 1);
|
249 return (val);
250}
251
252static uint16_t
253axge_read_cmd_2(struct axge_softc *sc, uint8_t cmd, uint16_t index,
254 uint16_t reg)
255{
256 uint8_t val[2];
257
258 axge_read_mem(sc, cmd, index, reg, &val, 2);
259 return (UGETW(val));
260}
261
262static void
| 248 return (val);
249}
250
251static uint16_t
252axge_read_cmd_2(struct axge_softc *sc, uint8_t cmd, uint16_t index,
253 uint16_t reg)
254{
255 uint8_t val[2];
256
257 axge_read_mem(sc, cmd, index, reg, &val, 2);
258 return (UGETW(val));
259}
260
261static void
|
263axge_write_cmd_1(struct axge_softc *sc, uint8_t cmd, uint16_t index,
264 uint16_t reg, uint8_t val)
| 262axge_write_cmd_1(struct axge_softc *sc, uint8_t cmd, uint16_t reg, uint8_t val)
|
265{
| 263{
|
266 axge_write_mem(sc, cmd, index, reg, &val, 1);
| 264 axge_write_mem(sc, cmd, 1, reg, &val, 1);
|
267}
268
269static void
270axge_write_cmd_2(struct axge_softc *sc, uint8_t cmd, uint16_t index,
271 uint16_t reg, uint16_t val)
272{
273 uint8_t temp[2];
274
275 USETW(temp, val);
276 axge_write_mem(sc, cmd, index, reg, &temp, 2);
277}
278
279static int
280axge_miibus_readreg(device_t dev, int phy, int reg)
281{
282 struct axge_softc *sc;
283 uint16_t val;
284 int locked;
285
286 sc = device_get_softc(dev);
287 locked = mtx_owned(&sc->sc_mtx);
288 if (!locked)
289 AXGE_LOCK(sc);
290
291 val = axge_read_cmd_2(sc, AXGE_ACCESS_PHY, reg, phy);
292
293 if (!locked)
294 AXGE_UNLOCK(sc);
295
296 return (val);
297}
298
299static int
300axge_miibus_writereg(device_t dev, int phy, int reg, int val)
301{
302 struct axge_softc *sc;
303 int locked;
304
305 sc = device_get_softc(dev);
306 if (sc->sc_phyno != phy)
307 return (0);
308 locked = mtx_owned(&sc->sc_mtx);
309 if (!locked)
310 AXGE_LOCK(sc);
311
312 axge_write_cmd_2(sc, AXGE_ACCESS_PHY, reg, phy, val);
313
314 if (!locked)
315 AXGE_UNLOCK(sc);
316
317 return (0);
318}
319
320static void
321axge_miibus_statchg(device_t dev)
322{
323 struct axge_softc *sc;
324 struct mii_data *mii;
325 struct ifnet *ifp;
326 uint8_t link_status, tmp[5];
327 uint16_t val;
328 int locked;
329
330 sc = device_get_softc(dev);
331 mii = GET_MII(sc);
332 locked = mtx_owned(&sc->sc_mtx);
333 if (!locked)
334 AXGE_LOCK(sc);
335
336 ifp = uether_getifp(&sc->sc_ue);
337 if (mii == NULL || ifp == NULL ||
338 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
339 goto done;
340
341 sc->sc_flags &= ~AXGE_FLAG_LINK;
342 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
343 (IFM_ACTIVE | IFM_AVALID)) {
344 switch (IFM_SUBTYPE(mii->mii_media_active)) {
345 case IFM_10_T:
346 case IFM_100_TX:
347 case IFM_1000_T:
348 sc->sc_flags |= AXGE_FLAG_LINK;
349 break;
350 default:
351 break;
352 }
353 }
354
355 /* Lost link, do nothing. */
356 if ((sc->sc_flags & AXGE_FLAG_LINK) == 0)
357 goto done;
358
| 265}
266
267static void
268axge_write_cmd_2(struct axge_softc *sc, uint8_t cmd, uint16_t index,
269 uint16_t reg, uint16_t val)
270{
271 uint8_t temp[2];
272
273 USETW(temp, val);
274 axge_write_mem(sc, cmd, index, reg, &temp, 2);
275}
276
277static int
278axge_miibus_readreg(device_t dev, int phy, int reg)
279{
280 struct axge_softc *sc;
281 uint16_t val;
282 int locked;
283
284 sc = device_get_softc(dev);
285 locked = mtx_owned(&sc->sc_mtx);
286 if (!locked)
287 AXGE_LOCK(sc);
288
289 val = axge_read_cmd_2(sc, AXGE_ACCESS_PHY, reg, phy);
290
291 if (!locked)
292 AXGE_UNLOCK(sc);
293
294 return (val);
295}
296
297static int
298axge_miibus_writereg(device_t dev, int phy, int reg, int val)
299{
300 struct axge_softc *sc;
301 int locked;
302
303 sc = device_get_softc(dev);
304 if (sc->sc_phyno != phy)
305 return (0);
306 locked = mtx_owned(&sc->sc_mtx);
307 if (!locked)
308 AXGE_LOCK(sc);
309
310 axge_write_cmd_2(sc, AXGE_ACCESS_PHY, reg, phy, val);
311
312 if (!locked)
313 AXGE_UNLOCK(sc);
314
315 return (0);
316}
317
318static void
319axge_miibus_statchg(device_t dev)
320{
321 struct axge_softc *sc;
322 struct mii_data *mii;
323 struct ifnet *ifp;
324 uint8_t link_status, tmp[5];
325 uint16_t val;
326 int locked;
327
328 sc = device_get_softc(dev);
329 mii = GET_MII(sc);
330 locked = mtx_owned(&sc->sc_mtx);
331 if (!locked)
332 AXGE_LOCK(sc);
333
334 ifp = uether_getifp(&sc->sc_ue);
335 if (mii == NULL || ifp == NULL ||
336 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
337 goto done;
338
339 sc->sc_flags &= ~AXGE_FLAG_LINK;
340 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
341 (IFM_ACTIVE | IFM_AVALID)) {
342 switch (IFM_SUBTYPE(mii->mii_media_active)) {
343 case IFM_10_T:
344 case IFM_100_TX:
345 case IFM_1000_T:
346 sc->sc_flags |= AXGE_FLAG_LINK;
347 break;
348 default:
349 break;
350 }
351 }
352
353 /* Lost link, do nothing. */
354 if ((sc->sc_flags & AXGE_FLAG_LINK) == 0)
355 goto done;
356
|
359 link_status = axge_read_cmd_1(sc, AXGE_ACCESS_MAC, 1, AXGE_LINK_STATUS);
| 357 link_status = axge_read_cmd_1(sc, AXGE_ACCESS_MAC, AXGE_PLSR);
|
360
361 val = 0;
362 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) {
| 358
359 val = 0;
360 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) {
|
363 val |= AXGE_MEDIUM_FULL_DUPLEX;
| 361 val |= MSR_FD;
|
364 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0)
| 362 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0)
|
365 val |= AXGE_MEDIUM_TXFLOW_CTRLEN;
| 363 val |= MSR_TFC;
|
366 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0)
| 364 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0)
|
367 val |= AXGE_MEDIUM_RXFLOW_CTRLEN;
| 365 val |= MSR_RFC;
|
368 }
| 366 }
|
369 val |= AXGE_MEDIUM_RECEIVE_EN;
| 367 val |= MSR_RE;
|
370 switch (IFM_SUBTYPE(mii->mii_media_active)) {
371 case IFM_1000_T:
| 368 switch (IFM_SUBTYPE(mii->mii_media_active)) {
369 case IFM_1000_T:
|
372 val |= AXGE_MEDIUM_GIGAMODE | AXGE_MEDIUM_EN_125MHZ;
373 if (link_status & AXGE_LINK_STATUS_USB_SS)
| 370 val |= MSR_GM | MSR_EN_125MHZ;
371 if (link_status & PLSR_USB_SS)
|
374 memcpy(tmp, &axge_bulk_size[0], 5);
| 372 memcpy(tmp, &axge_bulk_size[0], 5);
|
375 else if (link_status & AXGE_LINK_STATUS_USB_HS)
| 373 else if (link_status & PLSR_USB_HS)
|
376 memcpy(tmp, &axge_bulk_size[1], 5);
377 else
378 memcpy(tmp, &axge_bulk_size[3], 5);
379 break;
380 case IFM_100_TX:
| 374 memcpy(tmp, &axge_bulk_size[1], 5);
375 else
376 memcpy(tmp, &axge_bulk_size[3], 5);
377 break;
378 case IFM_100_TX:
|
381 val |= AXGE_MEDIUM_PS;
382 if (link_status &
383 (AXGE_LINK_STATUS_USB_SS | AXGE_LINK_STATUS_USB_HS))
| 379 val |= MSR_PS;
380 if (link_status & (PLSR_USB_SS | PLSR_USB_HS))
|
384 memcpy(tmp, &axge_bulk_size[2], 5);
385 else
386 memcpy(tmp, &axge_bulk_size[3], 5);
387 break;
388 case IFM_10_T:
389 memcpy(tmp, &axge_bulk_size[3], 5);
390 break;
391 }
392 /* Rx bulk configuration. */
393 axge_write_mem(sc, AXGE_ACCESS_MAC, 5, AXGE_RX_BULKIN_QCTRL, tmp, 5);
| 381 memcpy(tmp, &axge_bulk_size[2], 5);
382 else
383 memcpy(tmp, &axge_bulk_size[3], 5);
384 break;
385 case IFM_10_T:
386 memcpy(tmp, &axge_bulk_size[3], 5);
387 break;
388 }
389 /* Rx bulk configuration. */
390 axge_write_mem(sc, AXGE_ACCESS_MAC, 5, AXGE_RX_BULKIN_QCTRL, tmp, 5);
|
394 axge_write_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_MEDIUM_STATUS_MODE, val);
| 391 axge_write_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_MSR, val);
|
395done:
396 if (!locked)
397 AXGE_UNLOCK(sc);
398}
399
400static void
401axge_chip_init(struct axge_softc *sc)
402{
403 /* Power up ethernet PHY. */
| 392done:
393 if (!locked)
394 AXGE_UNLOCK(sc);
395}
396
397static void
398axge_chip_init(struct axge_softc *sc)
399{
400 /* Power up ethernet PHY. */
|
404 axge_write_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_PHYPWR_RSTCTL, 0);
405 axge_write_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_PHYPWR_RSTCTL,
406 AXGE_PHYPWR_RSTCTL_IPRL);
| 401 axge_write_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_EPPRCR, 0);
402 axge_write_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_EPPRCR, EPPRCR_IPRL);
|
407 uether_pause(&sc->sc_ue, hz / 4);
| 403 uether_pause(&sc->sc_ue, hz / 4);
|
408 axge_write_cmd_1(sc, AXGE_ACCESS_MAC, 1, AXGE_CLK_SELECT,
| 404 axge_write_cmd_1(sc, AXGE_ACCESS_MAC, AXGE_CLK_SELECT,
|
409 AXGE_CLK_SELECT_ACS | AXGE_CLK_SELECT_BCS);
410 uether_pause(&sc->sc_ue, hz / 10);
411}
412
413static void
414axge_reset(struct axge_softc *sc)
415{
416 struct usb_config_descriptor *cd;
417 usb_error_t err;
418
419 cd = usbd_get_config_descriptor(sc->sc_ue.ue_udev);
420
421 err = usbd_req_set_config(sc->sc_ue.ue_udev, &sc->sc_mtx,
422 cd->bConfigurationValue);
423 if (err)
424 DPRINTF("reset failed (ignored)\n");
425
426 /* Wait a little while for the chip to get its brains in order. */
427 uether_pause(&sc->sc_ue, hz / 100);
428
429 /* Reinitialize controller to achieve full reset. */
430 axge_chip_init(sc);
431}
432
433static void
434axge_attach_post(struct usb_ether *ue)
435{
436 struct axge_softc *sc;
437
438 sc = uether_getsc(ue);
439 sc->sc_phyno = 3;
440
441 /* Initialize controller and get station address. */
442 axge_chip_init(sc);
| 405 AXGE_CLK_SELECT_ACS | AXGE_CLK_SELECT_BCS);
406 uether_pause(&sc->sc_ue, hz / 10);
407}
408
409static void
410axge_reset(struct axge_softc *sc)
411{
412 struct usb_config_descriptor *cd;
413 usb_error_t err;
414
415 cd = usbd_get_config_descriptor(sc->sc_ue.ue_udev);
416
417 err = usbd_req_set_config(sc->sc_ue.ue_udev, &sc->sc_mtx,
418 cd->bConfigurationValue);
419 if (err)
420 DPRINTF("reset failed (ignored)\n");
421
422 /* Wait a little while for the chip to get its brains in order. */
423 uether_pause(&sc->sc_ue, hz / 100);
424
425 /* Reinitialize controller to achieve full reset. */
426 axge_chip_init(sc);
427}
428
429static void
430axge_attach_post(struct usb_ether *ue)
431{
432 struct axge_softc *sc;
433
434 sc = uether_getsc(ue);
435 sc->sc_phyno = 3;
436
437 /* Initialize controller and get station address. */
438 axge_chip_init(sc);
|
443 axge_read_mem(sc, AXGE_ACCESS_MAC, ETHER_ADDR_LEN, AXGE_NODE_ID,
| 439 axge_read_mem(sc, AXGE_ACCESS_MAC, ETHER_ADDR_LEN, AXGE_NIDR,
|
444 ue->ue_eaddr, ETHER_ADDR_LEN);
445}
446
447static int
448axge_attach_post_sub(struct usb_ether *ue)
449{
450 struct axge_softc *sc;
451 struct ifnet *ifp;
452 int error;
453
454 sc = uether_getsc(ue);
455 ifp = ue->ue_ifp;
456 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
457 ifp->if_start = uether_start;
458 ifp->if_ioctl = axge_ioctl;
459 ifp->if_init = uether_init;
460 IFQ_SET_MAXLEN(&ifp->if_snd, ifqmaxlen);
461 ifp->if_snd.ifq_drv_maxlen = ifqmaxlen;
462 IFQ_SET_READY(&ifp->if_snd);
463
464 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_TXCSUM | IFCAP_RXCSUM;
465 ifp->if_hwassist = AXGE_CSUM_FEATURES;
466 ifp->if_capenable = ifp->if_capabilities;
467
468 mtx_lock(&Giant);
469 error = mii_attach(ue->ue_dev, &ue->ue_miibus, ifp,
470 uether_ifmedia_upd, ue->ue_methods->ue_mii_sts,
471 BMSR_DEFCAPMASK, sc->sc_phyno, MII_OFFSET_ANY, MIIF_DOPAUSE);
472 mtx_unlock(&Giant);
473
474 return (error);
475}
476
477/*
478 * Set media options.
479 */
480static int
481axge_ifmedia_upd(struct ifnet *ifp)
482{
483 struct axge_softc *sc;
484 struct mii_data *mii;
485 struct mii_softc *miisc;
486 int error;
487
488 sc = ifp->if_softc;
489 mii = GET_MII(sc);
490 AXGE_LOCK_ASSERT(sc, MA_OWNED);
491
492 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
493 PHY_RESET(miisc);
494 error = mii_mediachg(mii);
495
496 return (error);
497}
498
499/*
500 * Report current media status.
501 */
502static void
503axge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
504{
505 struct axge_softc *sc;
506 struct mii_data *mii;
507
508 sc = ifp->if_softc;
509 mii = GET_MII(sc);
510 AXGE_LOCK(sc);
511 mii_pollstat(mii);
512 ifmr->ifm_active = mii->mii_media_active;
513 ifmr->ifm_status = mii->mii_media_status;
514 AXGE_UNLOCK(sc);
515}
516
517/*
518 * Probe for a AX88179 chip.
519 */
520static int
521axge_probe(device_t dev)
522{
523 struct usb_attach_arg *uaa;
524
525 uaa = device_get_ivars(dev);
526 if (uaa->usb_mode != USB_MODE_HOST)
527 return (ENXIO);
528 if (uaa->info.bConfigIndex != AXGE_CONFIG_IDX)
529 return (ENXIO);
530 if (uaa->info.bIfaceIndex != AXGE_IFACE_IDX)
531 return (ENXIO);
532
533 return (usbd_lookup_id_by_uaa(axge_devs, sizeof(axge_devs), uaa));
534}
535
536/*
537 * Attach the interface. Allocate softc structures, do ifmedia
538 * setup and ethernet/BPF attach.
539 */
540static int
541axge_attach(device_t dev)
542{
543 struct usb_attach_arg *uaa;
544 struct axge_softc *sc;
545 struct usb_ether *ue;
546 uint8_t iface_index;
547 int error;
548
549 uaa = device_get_ivars(dev);
550 sc = device_get_softc(dev);
551 ue = &sc->sc_ue;
552
553 device_set_usb_desc(dev);
554 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), NULL, MTX_DEF);
555
556 iface_index = AXGE_IFACE_IDX;
557 error = usbd_transfer_setup(uaa->device, &iface_index,
558 sc->sc_xfer, axge_config, AXGE_N_TRANSFER, sc, &sc->sc_mtx);
559 if (error) {
560 device_printf(dev, "allocating USB transfers failed\n");
561 goto detach;
562 }
563
564 ue->ue_sc = sc;
565 ue->ue_dev = dev;
566 ue->ue_udev = uaa->device;
567 ue->ue_mtx = &sc->sc_mtx;
568 ue->ue_methods = &axge_ue_methods;
569
570 error = uether_ifattach(ue);
571 if (error) {
572 device_printf(dev, "could not attach interface\n");
573 goto detach;
574 }
575 return (0); /* success */
576
577detach:
578 axge_detach(dev);
579 return (ENXIO); /* failure */
580}
581
582static int
583axge_detach(device_t dev)
584{
585 struct axge_softc *sc;
586 struct usb_ether *ue;
587
588 sc = device_get_softc(dev);
589 ue = &sc->sc_ue;
590 usbd_transfer_unsetup(sc->sc_xfer, AXGE_N_TRANSFER);
591 uether_ifdetach(ue);
592 mtx_destroy(&sc->sc_mtx);
593
594 return (0);
595}
596
597static void
598axge_bulk_read_callback(struct usb_xfer *xfer, usb_error_t error)
599{
600 struct axge_softc *sc;
601 struct usb_ether *ue;
602 struct usb_page_cache *pc;
603 int actlen;
604
605 sc = usbd_xfer_softc(xfer);
606 ue = &sc->sc_ue;
607 usbd_xfer_status(xfer, &actlen, NULL, NULL, NULL);
608
609 switch (USB_GET_STATE(xfer)) {
610 case USB_ST_TRANSFERRED:
611 pc = usbd_xfer_get_frame(xfer, 0);
| 440 ue->ue_eaddr, ETHER_ADDR_LEN);
441}
442
443static int
444axge_attach_post_sub(struct usb_ether *ue)
445{
446 struct axge_softc *sc;
447 struct ifnet *ifp;
448 int error;
449
450 sc = uether_getsc(ue);
451 ifp = ue->ue_ifp;
452 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
453 ifp->if_start = uether_start;
454 ifp->if_ioctl = axge_ioctl;
455 ifp->if_init = uether_init;
456 IFQ_SET_MAXLEN(&ifp->if_snd, ifqmaxlen);
457 ifp->if_snd.ifq_drv_maxlen = ifqmaxlen;
458 IFQ_SET_READY(&ifp->if_snd);
459
460 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_TXCSUM | IFCAP_RXCSUM;
461 ifp->if_hwassist = AXGE_CSUM_FEATURES;
462 ifp->if_capenable = ifp->if_capabilities;
463
464 mtx_lock(&Giant);
465 error = mii_attach(ue->ue_dev, &ue->ue_miibus, ifp,
466 uether_ifmedia_upd, ue->ue_methods->ue_mii_sts,
467 BMSR_DEFCAPMASK, sc->sc_phyno, MII_OFFSET_ANY, MIIF_DOPAUSE);
468 mtx_unlock(&Giant);
469
470 return (error);
471}
472
473/*
474 * Set media options.
475 */
476static int
477axge_ifmedia_upd(struct ifnet *ifp)
478{
479 struct axge_softc *sc;
480 struct mii_data *mii;
481 struct mii_softc *miisc;
482 int error;
483
484 sc = ifp->if_softc;
485 mii = GET_MII(sc);
486 AXGE_LOCK_ASSERT(sc, MA_OWNED);
487
488 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
489 PHY_RESET(miisc);
490 error = mii_mediachg(mii);
491
492 return (error);
493}
494
495/*
496 * Report current media status.
497 */
498static void
499axge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
500{
501 struct axge_softc *sc;
502 struct mii_data *mii;
503
504 sc = ifp->if_softc;
505 mii = GET_MII(sc);
506 AXGE_LOCK(sc);
507 mii_pollstat(mii);
508 ifmr->ifm_active = mii->mii_media_active;
509 ifmr->ifm_status = mii->mii_media_status;
510 AXGE_UNLOCK(sc);
511}
512
513/*
514 * Probe for a AX88179 chip.
515 */
516static int
517axge_probe(device_t dev)
518{
519 struct usb_attach_arg *uaa;
520
521 uaa = device_get_ivars(dev);
522 if (uaa->usb_mode != USB_MODE_HOST)
523 return (ENXIO);
524 if (uaa->info.bConfigIndex != AXGE_CONFIG_IDX)
525 return (ENXIO);
526 if (uaa->info.bIfaceIndex != AXGE_IFACE_IDX)
527 return (ENXIO);
528
529 return (usbd_lookup_id_by_uaa(axge_devs, sizeof(axge_devs), uaa));
530}
531
532/*
533 * Attach the interface. Allocate softc structures, do ifmedia
534 * setup and ethernet/BPF attach.
535 */
536static int
537axge_attach(device_t dev)
538{
539 struct usb_attach_arg *uaa;
540 struct axge_softc *sc;
541 struct usb_ether *ue;
542 uint8_t iface_index;
543 int error;
544
545 uaa = device_get_ivars(dev);
546 sc = device_get_softc(dev);
547 ue = &sc->sc_ue;
548
549 device_set_usb_desc(dev);
550 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), NULL, MTX_DEF);
551
552 iface_index = AXGE_IFACE_IDX;
553 error = usbd_transfer_setup(uaa->device, &iface_index,
554 sc->sc_xfer, axge_config, AXGE_N_TRANSFER, sc, &sc->sc_mtx);
555 if (error) {
556 device_printf(dev, "allocating USB transfers failed\n");
557 goto detach;
558 }
559
560 ue->ue_sc = sc;
561 ue->ue_dev = dev;
562 ue->ue_udev = uaa->device;
563 ue->ue_mtx = &sc->sc_mtx;
564 ue->ue_methods = &axge_ue_methods;
565
566 error = uether_ifattach(ue);
567 if (error) {
568 device_printf(dev, "could not attach interface\n");
569 goto detach;
570 }
571 return (0); /* success */
572
573detach:
574 axge_detach(dev);
575 return (ENXIO); /* failure */
576}
577
578static int
579axge_detach(device_t dev)
580{
581 struct axge_softc *sc;
582 struct usb_ether *ue;
583
584 sc = device_get_softc(dev);
585 ue = &sc->sc_ue;
586 usbd_transfer_unsetup(sc->sc_xfer, AXGE_N_TRANSFER);
587 uether_ifdetach(ue);
588 mtx_destroy(&sc->sc_mtx);
589
590 return (0);
591}
592
593static void
594axge_bulk_read_callback(struct usb_xfer *xfer, usb_error_t error)
595{
596 struct axge_softc *sc;
597 struct usb_ether *ue;
598 struct usb_page_cache *pc;
599 int actlen;
600
601 sc = usbd_xfer_softc(xfer);
602 ue = &sc->sc_ue;
603 usbd_xfer_status(xfer, &actlen, NULL, NULL, NULL);
604
605 switch (USB_GET_STATE(xfer)) {
606 case USB_ST_TRANSFERRED:
607 pc = usbd_xfer_get_frame(xfer, 0);
|
612 axge_rx_frame(ue, pc, actlen);
| 608 if (axge_rx_frame(ue, pc, actlen) != 0)
609 goto tr_setup;
|
613
614 /* FALLTHROUGH */
615 case USB_ST_SETUP:
616tr_setup:
617 usbd_xfer_set_frame_len(xfer, 0, usbd_xfer_max_len(xfer));
618 usbd_transfer_submit(xfer);
619 uether_rxflush(ue);
620 return;
621
622 default:
623 if (error != USB_ERR_CANCELLED) {
624 usbd_xfer_set_stall(xfer);
625 goto tr_setup;
626 }
627 return;
628
629 }
630}
631
632static void
633axge_bulk_write_callback(struct usb_xfer *xfer, usb_error_t error)
634{
635 struct axge_softc *sc;
636 struct ifnet *ifp;
637 struct usb_page_cache *pc;
638 struct mbuf *m;
639 uint32_t txhdr;
| 610
611 /* FALLTHROUGH */
612 case USB_ST_SETUP:
613tr_setup:
614 usbd_xfer_set_frame_len(xfer, 0, usbd_xfer_max_len(xfer));
615 usbd_transfer_submit(xfer);
616 uether_rxflush(ue);
617 return;
618
619 default:
620 if (error != USB_ERR_CANCELLED) {
621 usbd_xfer_set_stall(xfer);
622 goto tr_setup;
623 }
624 return;
625
626 }
627}
628
629static void
630axge_bulk_write_callback(struct usb_xfer *xfer, usb_error_t error)
631{
632 struct axge_softc *sc;
633 struct ifnet *ifp;
634 struct usb_page_cache *pc;
635 struct mbuf *m;
636 uint32_t txhdr;
|
640 uint32_t txhdr2;
641 int nframes;
642 int frm_len;
| 637 int nframes, pos;
|
643
644 sc = usbd_xfer_softc(xfer);
645 ifp = uether_getifp(&sc->sc_ue);
646
647 switch (USB_GET_STATE(xfer)) {
648 case USB_ST_TRANSFERRED:
649 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
650 /* FALLTHROUGH */
651 case USB_ST_SETUP:
652tr_setup:
653 if ((sc->sc_flags & AXGE_FLAG_LINK) == 0 ||
654 (ifp->if_drv_flags & IFF_DRV_OACTIVE) != 0) {
655 /*
656 * Don't send anything if there is no link or
657 * controller is busy.
658 */
659 return;
660 }
661
662 for (nframes = 0; nframes < 16 &&
663 !IFQ_DRV_IS_EMPTY(&ifp->if_snd); nframes++) {
664 IFQ_DRV_DEQUEUE(&ifp->if_snd, m);
665 if (m == NULL)
666 break;
667 usbd_xfer_set_frame_offset(xfer, nframes * MCLBYTES,
668 nframes);
| 638
639 sc = usbd_xfer_softc(xfer);
640 ifp = uether_getifp(&sc->sc_ue);
641
642 switch (USB_GET_STATE(xfer)) {
643 case USB_ST_TRANSFERRED:
644 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
645 /* FALLTHROUGH */
646 case USB_ST_SETUP:
647tr_setup:
648 if ((sc->sc_flags & AXGE_FLAG_LINK) == 0 ||
649 (ifp->if_drv_flags & IFF_DRV_OACTIVE) != 0) {
650 /*
651 * Don't send anything if there is no link or
652 * controller is busy.
653 */
654 return;
655 }
656
657 for (nframes = 0; nframes < 16 &&
658 !IFQ_DRV_IS_EMPTY(&ifp->if_snd); nframes++) {
659 IFQ_DRV_DEQUEUE(&ifp->if_snd, m);
660 if (m == NULL)
661 break;
662 usbd_xfer_set_frame_offset(xfer, nframes * MCLBYTES,
663 nframes);
|
669 frm_len = 0;
| 664 pos = 0;
|
670 pc = usbd_xfer_get_frame(xfer, nframes);
| 665 pc = usbd_xfer_get_frame(xfer, nframes);
|
671
672 txhdr = m->m_pkthdr.len;
673 txhdr = htole32(txhdr);
| 666 txhdr = htole32(m->m_pkthdr.len);
|
674 usbd_copy_in(pc, 0, &txhdr, sizeof(txhdr));
| 667 usbd_copy_in(pc, 0, &txhdr, sizeof(txhdr));
|
675 frm_len += sizeof(txhdr);
| 668 txhdr = 0;
669 txhdr = htole32(txhdr);
670 usbd_copy_in(pc, 4, &txhdr, sizeof(txhdr));
671 pos += 8;
672 usbd_m_copy_in(pc, pos, m, 0, m->m_pkthdr.len);
673 pos += m->m_pkthdr.len;
674 if ((pos % usbd_xfer_max_framelen(xfer)) == 0)
675 txhdr |= 0x80008000;
|
676
| 676
|
677 txhdr2 = 0;
678 if ((m->m_pkthdr.len + sizeof(txhdr) + sizeof(txhdr2)) %
679 usbd_xfer_max_framelen(xfer) == 0) {
680 txhdr2 |= 0x80008000;
681 }
682 txhdr2 = htole32(txhdr2);
683 usbd_copy_in(pc, frm_len, &txhdr2, sizeof(txhdr2));
684 frm_len += sizeof(txhdr2);
685
686 /* Next copy in the actual packet. */
687 usbd_m_copy_in(pc, frm_len, m, 0, m->m_pkthdr.len);
688 frm_len += m->m_pkthdr.len;
689
| |
690 /*
691 * XXX
692 * Update TX packet counter here. This is not
693 * correct way but it seems that there is no way
694 * to know how many packets are sent at the end
695 * of transfer because controller combines
696 * multiple writes into single one if there is
697 * room in TX buffer of controller.
698 */
699 ifp->if_opackets++;
700
701 /*
702 * if there's a BPF listener, bounce a copy
703 * of this frame to him:
704 */
705 BPF_MTAP(ifp, m);
706
707 m_freem(m);
708
709 /* Set frame length. */
| 677 /*
678 * XXX
679 * Update TX packet counter here. This is not
680 * correct way but it seems that there is no way
681 * to know how many packets are sent at the end
682 * of transfer because controller combines
683 * multiple writes into single one if there is
684 * room in TX buffer of controller.
685 */
686 ifp->if_opackets++;
687
688 /*
689 * if there's a BPF listener, bounce a copy
690 * of this frame to him:
691 */
692 BPF_MTAP(ifp, m);
693
694 m_freem(m);
695
696 /* Set frame length. */
|
710 usbd_xfer_set_frame_len(xfer, nframes, frm_len);
| 697 usbd_xfer_set_frame_len(xfer, nframes, pos);
|
711 }
712 if (nframes != 0) {
713 usbd_xfer_set_frames(xfer, nframes);
714 usbd_transfer_submit(xfer);
715 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
716 }
717 return;
718 /* NOTREACHED */
719 default:
720 ifp->if_oerrors++;
721 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
722
723 if (error != USB_ERR_CANCELLED) {
724 usbd_xfer_set_stall(xfer);
725 goto tr_setup;
726 }
727 return;
728
729 }
730}
731
732static void
733axge_tick(struct usb_ether *ue)
734{
735 struct axge_softc *sc;
736 struct mii_data *mii;
737
738 sc = uether_getsc(ue);
739 mii = GET_MII(sc);
740 AXGE_LOCK_ASSERT(sc, MA_OWNED);
741
742 mii_tick(mii);
743 if ((sc->sc_flags & AXGE_FLAG_LINK) == 0) {
744 axge_miibus_statchg(ue->ue_dev);
745 if ((sc->sc_flags & AXGE_FLAG_LINK) != 0)
746 axge_start(ue);
747 }
748}
749
750static void
751axge_setmulti(struct usb_ether *ue)
752{
753 struct axge_softc *sc;
754 struct ifnet *ifp;
755 struct ifmultiaddr *ifma;
756 uint32_t h;
757 uint16_t rxmode;
758 uint8_t hashtbl[8] = { 0, 0, 0, 0, 0, 0, 0, 0 };
759
760 sc = uether_getsc(ue);
761 ifp = uether_getifp(ue);
762 h = 0;
763 AXGE_LOCK_ASSERT(sc, MA_OWNED);
764
| 698 }
699 if (nframes != 0) {
700 usbd_xfer_set_frames(xfer, nframes);
701 usbd_transfer_submit(xfer);
702 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
703 }
704 return;
705 /* NOTREACHED */
706 default:
707 ifp->if_oerrors++;
708 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
709
710 if (error != USB_ERR_CANCELLED) {
711 usbd_xfer_set_stall(xfer);
712 goto tr_setup;
713 }
714 return;
715
716 }
717}
718
719static void
720axge_tick(struct usb_ether *ue)
721{
722 struct axge_softc *sc;
723 struct mii_data *mii;
724
725 sc = uether_getsc(ue);
726 mii = GET_MII(sc);
727 AXGE_LOCK_ASSERT(sc, MA_OWNED);
728
729 mii_tick(mii);
730 if ((sc->sc_flags & AXGE_FLAG_LINK) == 0) {
731 axge_miibus_statchg(ue->ue_dev);
732 if ((sc->sc_flags & AXGE_FLAG_LINK) != 0)
733 axge_start(ue);
734 }
735}
736
737static void
738axge_setmulti(struct usb_ether *ue)
739{
740 struct axge_softc *sc;
741 struct ifnet *ifp;
742 struct ifmultiaddr *ifma;
743 uint32_t h;
744 uint16_t rxmode;
745 uint8_t hashtbl[8] = { 0, 0, 0, 0, 0, 0, 0, 0 };
746
747 sc = uether_getsc(ue);
748 ifp = uether_getifp(ue);
749 h = 0;
750 AXGE_LOCK_ASSERT(sc, MA_OWNED);
751
|
765 rxmode = axge_read_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_RX_CTL);
| 752 rxmode = axge_read_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_RCR);
|
766 if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) {
| 753 if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) {
|
767 rxmode |= AXGE_RX_CTL_AMALL;
768 axge_write_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_RX_CTL, rxmode);
| 754 rxmode |= RCR_AMALL;
755 axge_write_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_RCR, rxmode);
|
769 return;
770 }
| 756 return;
757 }
|
771 rxmode &= ~AXGE_RX_CTL_AMALL;
| 758 rxmode &= ~RCR_AMALL;
|
772
773 if_maddr_rlock(ifp);
774 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
775 if (ifma->ifma_addr->sa_family != AF_LINK)
776 continue;
777 h = ether_crc32_be(LLADDR((struct sockaddr_dl *)
778 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26;
779 hashtbl[h / 8] |= 1 << (h % 8);
780 }
781 if_maddr_runlock(ifp);
782
| 759
760 if_maddr_rlock(ifp);
761 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
762 if (ifma->ifma_addr->sa_family != AF_LINK)
763 continue;
764 h = ether_crc32_be(LLADDR((struct sockaddr_dl *)
765 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26;
766 hashtbl[h / 8] |= 1 << (h % 8);
767 }
768 if_maddr_runlock(ifp);
769
|
783 axge_write_mem(sc, AXGE_ACCESS_MAC, 8, AXGE_MULTI_FILTER_ARRY,
784 (void *)&hashtbl, 8);
785 axge_write_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_RX_CTL, rxmode);
| 770 axge_write_mem(sc, AXGE_ACCESS_MAC, 8, AXGE_MFA, (void *)&hashtbl, 8);
771 axge_write_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_RCR, rxmode);
|
786}
787
788static void
789axge_setpromisc(struct usb_ether *ue)
790{
791 struct axge_softc *sc;
792 struct ifnet *ifp;
793 uint16_t rxmode;
794
795 sc = uether_getsc(ue);
796 ifp = uether_getifp(ue);
| 772}
773
774static void
775axge_setpromisc(struct usb_ether *ue)
776{
777 struct axge_softc *sc;
778 struct ifnet *ifp;
779 uint16_t rxmode;
780
781 sc = uether_getsc(ue);
782 ifp = uether_getifp(ue);
|
797 rxmode = axge_read_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_RX_CTL);
| 783 rxmode = axge_read_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_RCR);
|
798
799 if (ifp->if_flags & IFF_PROMISC)
| 784
785 if (ifp->if_flags & IFF_PROMISC)
|
800 rxmode |= AXGE_RX_CTL_PRO;
| 786 rxmode |= RCR_PRO;
|
801 else
| 787 else
|
802 rxmode &= ~AXGE_RX_CTL_PRO;
| 788 rxmode &= ~RCR_PRO;
|
803
| 789
|
804 axge_write_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_RX_CTL, rxmode);
| 790 axge_write_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_RCR, rxmode);
|
805 axge_setmulti(ue);
806}
807
808static void
809axge_start(struct usb_ether *ue)
810{
811 struct axge_softc *sc;
812
813 sc = uether_getsc(ue);
814 /*
815 * Start the USB transfers, if not already started.
816 */
817 usbd_transfer_start(sc->sc_xfer[AXGE_BULK_DT_RD]);
818 usbd_transfer_start(sc->sc_xfer[AXGE_BULK_DT_WR]);
819}
820
821static void
822axge_init(struct usb_ether *ue)
823{
824 struct axge_softc *sc;
825 struct ifnet *ifp;
826 uint16_t rxmode;
827
828 sc = uether_getsc(ue);
829 ifp = uether_getifp(ue);
830 AXGE_LOCK_ASSERT(sc, MA_OWNED);
831
832 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
833 return;
834
835 /*
836 * Cancel pending I/O and free all RX/TX buffers.
837 */
838 axge_stop(ue);
839
840 axge_reset(sc);
841
842 /* Set MAC address. */
| 791 axge_setmulti(ue);
792}
793
794static void
795axge_start(struct usb_ether *ue)
796{
797 struct axge_softc *sc;
798
799 sc = uether_getsc(ue);
800 /*
801 * Start the USB transfers, if not already started.
802 */
803 usbd_transfer_start(sc->sc_xfer[AXGE_BULK_DT_RD]);
804 usbd_transfer_start(sc->sc_xfer[AXGE_BULK_DT_WR]);
805}
806
807static void
808axge_init(struct usb_ether *ue)
809{
810 struct axge_softc *sc;
811 struct ifnet *ifp;
812 uint16_t rxmode;
813
814 sc = uether_getsc(ue);
815 ifp = uether_getifp(ue);
816 AXGE_LOCK_ASSERT(sc, MA_OWNED);
817
818 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
819 return;
820
821 /*
822 * Cancel pending I/O and free all RX/TX buffers.
823 */
824 axge_stop(ue);
825
826 axge_reset(sc);
827
828 /* Set MAC address. */
|
843 axge_write_mem(sc, AXGE_ACCESS_MAC, ETHER_ADDR_LEN, AXGE_NODE_ID,
| 829 axge_write_mem(sc, AXGE_ACCESS_MAC, ETHER_ADDR_LEN, AXGE_NIDR,
|
844 IF_LLADDR(ifp), ETHER_ADDR_LEN);
845
| 830 IF_LLADDR(ifp), ETHER_ADDR_LEN);
831
|
846 axge_write_cmd_1(sc, AXGE_ACCESS_MAC, 1, AXGE_PAUSE_WATERLVL_LOW, 0x34);
847 axge_write_cmd_1(sc, AXGE_ACCESS_MAC, 1, AXGE_PAUSE_WATERLVL_HIGH,
848 0x52);
| 832 axge_write_cmd_1(sc, AXGE_ACCESS_MAC, AXGE_PWLLR, 0x34);
833 axge_write_cmd_1(sc, AXGE_ACCESS_MAC, AXGE_PWLHR, 0x52);
|
849
850 /* Configure TX/RX checksum offloading. */
851 axge_csum_cfg(ue);
852
853 /* Configure RX settings. */
| 834
835 /* Configure TX/RX checksum offloading. */
836 axge_csum_cfg(ue);
837
838 /* Configure RX settings. */
|
854 rxmode = (AXGE_RX_CTL_IPE | AXGE_RX_CTL_AM | AXGE_RX_CTL_START);
| 839 rxmode = (RCR_AM | RCR_SO | RCR_DROP_CRCE);
840 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0)
841 rxmode |= RCR_IPE;
|
855
856 /* If we want promiscuous mode, set the allframes bit. */
857 if (ifp->if_flags & IFF_PROMISC)
| 842
843 /* If we want promiscuous mode, set the allframes bit. */
844 if (ifp->if_flags & IFF_PROMISC)
|
858 rxmode |= AXGE_RX_CTL_PRO;
| 845 rxmode |= RCR_PRO;
|
859
860 if (ifp->if_flags & IFF_BROADCAST)
| 846
847 if (ifp->if_flags & IFF_BROADCAST)
|
861 rxmode |= AXGE_RX_CTL_AB;
| 848 rxmode |= RCR_AB;
|
862
| 849
|
863 axge_write_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_RX_CTL, rxmode);
| 850 axge_write_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_RCR, rxmode);
|
864
| 851
|
| 852 axge_write_cmd_1(sc, AXGE_ACCESS_MAC, AXGE_MMSR,
853 MMSR_PME_TYPE | MMSR_PME_POL | MMSR_RWMP);
854
|
865 /* Load the multicast filter. */
866 axge_setmulti(ue);
867
868 usbd_xfer_set_stall(sc->sc_xfer[AXGE_BULK_DT_WR]);
869
870 ifp->if_drv_flags |= IFF_DRV_RUNNING;
871 /* Switch to selected media. */
872 axge_ifmedia_upd(ifp);
873}
874
875static void
876axge_stop(struct usb_ether *ue)
877{
878 struct axge_softc *sc;
879 struct ifnet *ifp;
880
881 sc = uether_getsc(ue);
882 ifp = uether_getifp(ue);
883
884 AXGE_LOCK_ASSERT(sc, MA_OWNED);
885
886 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
887 sc->sc_flags &= ~AXGE_FLAG_LINK;
888
889 /*
890 * Stop all the transfers, if not already stopped:
891 */
892 usbd_transfer_stop(sc->sc_xfer[AXGE_BULK_DT_WR]);
893 usbd_transfer_stop(sc->sc_xfer[AXGE_BULK_DT_RD]);
894}
895
896static int
897axge_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
898{
899 struct usb_ether *ue;
900 struct axge_softc *sc;
901 struct ifreq *ifr;
902 int error, mask, reinit;
903
904 ue = ifp->if_softc;
905 sc = uether_getsc(ue);
906 ifr = (struct ifreq *)data;
907 error = 0;
908 reinit = 0;
909 if (cmd == SIOCSIFCAP) {
910 AXGE_LOCK(sc);
911 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
912 if ((mask & IFCAP_TXCSUM) != 0 &&
913 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) {
914 ifp->if_capenable ^= IFCAP_TXCSUM;
915 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0)
916 ifp->if_hwassist |= AXGE_CSUM_FEATURES;
917 else
918 ifp->if_hwassist &= ~AXGE_CSUM_FEATURES;
919 reinit++;
920 }
921 if ((mask & IFCAP_RXCSUM) != 0 &&
922 (ifp->if_capabilities & IFCAP_RXCSUM) != 0) {
923 ifp->if_capenable ^= IFCAP_RXCSUM;
924 reinit++;
925 }
926 if (reinit > 0 && ifp->if_drv_flags & IFF_DRV_RUNNING)
927 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
928 else
929 reinit = 0;
930 AXGE_UNLOCK(sc);
931 if (reinit > 0)
932 uether_init(ue);
933 } else
934 error = uether_ioctl(ifp, cmd, data);
935
936 return (error);
937}
938
939static int
940axge_rx_frame(struct usb_ether *ue, struct usb_page_cache *pc, int actlen)
941{
| 855 /* Load the multicast filter. */
856 axge_setmulti(ue);
857
858 usbd_xfer_set_stall(sc->sc_xfer[AXGE_BULK_DT_WR]);
859
860 ifp->if_drv_flags |= IFF_DRV_RUNNING;
861 /* Switch to selected media. */
862 axge_ifmedia_upd(ifp);
863}
864
865static void
866axge_stop(struct usb_ether *ue)
867{
868 struct axge_softc *sc;
869 struct ifnet *ifp;
870
871 sc = uether_getsc(ue);
872 ifp = uether_getifp(ue);
873
874 AXGE_LOCK_ASSERT(sc, MA_OWNED);
875
876 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
877 sc->sc_flags &= ~AXGE_FLAG_LINK;
878
879 /*
880 * Stop all the transfers, if not already stopped:
881 */
882 usbd_transfer_stop(sc->sc_xfer[AXGE_BULK_DT_WR]);
883 usbd_transfer_stop(sc->sc_xfer[AXGE_BULK_DT_RD]);
884}
885
886static int
887axge_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
888{
889 struct usb_ether *ue;
890 struct axge_softc *sc;
891 struct ifreq *ifr;
892 int error, mask, reinit;
893
894 ue = ifp->if_softc;
895 sc = uether_getsc(ue);
896 ifr = (struct ifreq *)data;
897 error = 0;
898 reinit = 0;
899 if (cmd == SIOCSIFCAP) {
900 AXGE_LOCK(sc);
901 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
902 if ((mask & IFCAP_TXCSUM) != 0 &&
903 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) {
904 ifp->if_capenable ^= IFCAP_TXCSUM;
905 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0)
906 ifp->if_hwassist |= AXGE_CSUM_FEATURES;
907 else
908 ifp->if_hwassist &= ~AXGE_CSUM_FEATURES;
909 reinit++;
910 }
911 if ((mask & IFCAP_RXCSUM) != 0 &&
912 (ifp->if_capabilities & IFCAP_RXCSUM) != 0) {
913 ifp->if_capenable ^= IFCAP_RXCSUM;
914 reinit++;
915 }
916 if (reinit > 0 && ifp->if_drv_flags & IFF_DRV_RUNNING)
917 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
918 else
919 reinit = 0;
920 AXGE_UNLOCK(sc);
921 if (reinit > 0)
922 uether_init(ue);
923 } else
924 error = uether_ioctl(ifp, cmd, data);
925
926 return (error);
927}
928
929static int
930axge_rx_frame(struct usb_ether *ue, struct usb_page_cache *pc, int actlen)
931{
|
942 struct axge_csum_hdr csum_hdr;
943 int error, len, pos;
| 932 int error, pos;
|
944 int pkt_cnt;
| 933 int pkt_cnt;
|
945 uint32_t rxhdr;
| 934 uint32_t rxhdr, pkt_hdr;
|
946 uint16_t hdr_off;
| 935 uint16_t hdr_off;
|
947 uint16_t pktlen;
| 936 uint16_t len, pktlen;
|
948
949 pos = 0;
950 len = 0;
951 error = 0;
952
953 usbd_copy_out(pc, actlen - sizeof(rxhdr), &rxhdr, sizeof(rxhdr));
| 937
938 pos = 0;
939 len = 0;
940 error = 0;
941
942 usbd_copy_out(pc, actlen - sizeof(rxhdr), &rxhdr, sizeof(rxhdr));
|
954 actlen -= sizeof(rxhdr);
| |
955 rxhdr = le32toh(rxhdr);
956
957 pkt_cnt = (uint16_t)rxhdr;
958 hdr_off = (uint16_t)(rxhdr >> 16);
959
| 943 rxhdr = le32toh(rxhdr);
944
945 pkt_cnt = (uint16_t)rxhdr;
946 hdr_off = (uint16_t)(rxhdr >> 16);
947
|
960 usbd_copy_out(pc, pos + hdr_off, &csum_hdr, sizeof(csum_hdr));
961 csum_hdr.len = le16toh(csum_hdr.len);
962 csum_hdr.cstatus = le16toh(csum_hdr.cstatus);
| 948 usbd_copy_out(pc, hdr_off, &pkt_hdr, sizeof(pkt_hdr));
|
963
| 949
|
964 while (pkt_cnt--) {
965 if (actlen <= sizeof(csum_hdr) + sizeof(struct ether_header)) {
| 950 while (pkt_cnt > 0) {
951 if ((int)(sizeof(pkt_hdr)) > actlen) {
|
966 error = EINVAL;
967 break;
968 }
| 952 error = EINVAL;
953 break;
954 }
|
969 pktlen = AXGE_CSUM_RXBYTES(csum_hdr.len);
970
971 if (pkt_cnt == 0)
972 /* Skip the 2-byte IP alignment header. */
973 axge_rxeof(ue, pc, 2, pktlen - 2, &csum_hdr);
| 955 pkt_hdr = le32toh(pkt_hdr);
956 pktlen = (pkt_hdr >> 16) & 0x1fff;
957 if ((pkt_hdr & AXGE_RXHDR_CRC_ERR) ||
958 (pkt_hdr & AXGE_RXHDR_DROP_ERR))
959 ue->ue_ifp->if_ierrors++;
960 axge_rxeof(ue, pc, pos + 2, pktlen - 6, pkt_hdr);
961 len = (pktlen + 7) & ~7;
962 pos += len;
963 pkt_hdr++;
964 pkt_cnt--;
|
974 }
975
976 if (error != 0)
977 ue->ue_ifp->if_ierrors++;
978 return (error);
979}
980
981static int
982axge_rxeof(struct usb_ether *ue, struct usb_page_cache *pc,
| 965 }
966
967 if (error != 0)
968 ue->ue_ifp->if_ierrors++;
969 return (error);
970}
971
972static int
973axge_rxeof(struct usb_ether *ue, struct usb_page_cache *pc,
|
983 unsigned int offset, unsigned int len, struct axge_csum_hdr *csum_hdr)
| 974 unsigned int offset, unsigned int len, uint32_t pkt_hdr)
|
984{
985 struct ifnet *ifp;
986 struct mbuf *m;
987
988 ifp = ue->ue_ifp;
989 if (len < ETHER_HDR_LEN || len > MCLBYTES - ETHER_ALIGN) {
990 ifp->if_ierrors++;
991 return (EINVAL);
992 }
993
994 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
995 if (m == NULL) {
996 ifp->if_iqdrops++;
997 return (ENOMEM);
998 }
999 m->m_len = m->m_pkthdr.len = MCLBYTES;
1000 m_adj(m, ETHER_ALIGN);
1001
1002 usbd_copy_out(pc, offset, mtod(m, uint8_t *), len);
1003
1004 ifp->if_ipackets++;
1005 m->m_pkthdr.rcvif = ifp;
1006 m->m_pkthdr.len = m->m_len = len;
1007
| 975{
976 struct ifnet *ifp;
977 struct mbuf *m;
978
979 ifp = ue->ue_ifp;
980 if (len < ETHER_HDR_LEN || len > MCLBYTES - ETHER_ALIGN) {
981 ifp->if_ierrors++;
982 return (EINVAL);
983 }
984
985 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
986 if (m == NULL) {
987 ifp->if_iqdrops++;
988 return (ENOMEM);
989 }
990 m->m_len = m->m_pkthdr.len = MCLBYTES;
991 m_adj(m, ETHER_ALIGN);
992
993 usbd_copy_out(pc, offset, mtod(m, uint8_t *), len);
994
995 ifp->if_ipackets++;
996 m->m_pkthdr.rcvif = ifp;
997 m->m_pkthdr.len = m->m_len = len;
998
|
1008 if (csum_hdr != NULL &&
1009 csum_hdr->cstatus & AXGE_CSUM_HDR_L3_TYPE_IPV4) {
1010 if ((csum_hdr->cstatus & (AXGE_CSUM_HDR_L4_CSUM_ERR |
1011 AXGE_RXHDR_L4CSUM_ERR)) == 0) {
1012 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED |
1013 CSUM_IP_VALID;
1014 if ((csum_hdr->cstatus & AXGE_CSUM_HDR_L4_TYPE_MASK) ==
1015 AXGE_CSUM_HDR_L4_TYPE_TCP ||
1016 (csum_hdr->cstatus & AXGE_CSUM_HDR_L4_TYPE_MASK) ==
1017 AXGE_CSUM_HDR_L4_TYPE_UDP) {
1018 m->m_pkthdr.csum_flags |=
1019 CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
1020 m->m_pkthdr.csum_data = 0xffff;
1021 }
| 999 if ((pkt_hdr & (AXGE_RXHDR_L4CSUM_ERR | AXGE_RXHDR_L3CSUM_ERR)) == 0) {
1000 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED | CSUM_IP_VALID;
1001 if ((pkt_hdr & AXGE_RXHDR_L4_TYPE_MASK) ==
1002 AXGE_RXHDR_L4_TYPE_TCP ||
1003 (pkt_hdr & AXGE_RXHDR_L4_TYPE_MASK) ==
1004 AXGE_RXHDR_L4_TYPE_UDP) {
1005 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
1006 CSUM_PSEUDO_HDR;
1007 m->m_pkthdr.csum_data = 0xffff;
|
1022 }
1023 }
1024
1025 _IF_ENQUEUE(&ue->ue_rxq, m);
1026 return (0);
1027}
1028
1029static void
1030axge_csum_cfg(struct usb_ether *ue)
1031{
1032 struct axge_softc *sc;
1033 struct ifnet *ifp;
1034 uint8_t csum;
1035
1036 sc = uether_getsc(ue);
1037 AXGE_LOCK_ASSERT(sc, MA_OWNED);
1038 ifp = uether_getifp(ue);
1039
1040 csum = 0;
1041 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0)
| 1008 }
1009 }
1010
1011 _IF_ENQUEUE(&ue->ue_rxq, m);
1012 return (0);
1013}
1014
1015static void
1016axge_csum_cfg(struct usb_ether *ue)
1017{
1018 struct axge_softc *sc;
1019 struct ifnet *ifp;
1020 uint8_t csum;
1021
1022 sc = uether_getsc(ue);
1023 AXGE_LOCK_ASSERT(sc, MA_OWNED);
1024 ifp = uether_getifp(ue);
1025
1026 csum = 0;
1027 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0)
|
1042 csum |= AXGE_TXCOE_IP | AXGE_TXCOE_TCP | AXGE_TXCOE_UDP;
1043 axge_write_cmd_1(sc, AXGE_ACCESS_MAC, 1, AXGE_TXCOE_CTL, csum);
| 1028 csum |= CTCR_IP | CTCR_TCP | CTCR_UDP;
1029 axge_write_cmd_1(sc, AXGE_ACCESS_MAC, AXGE_CTCR, csum);
|
1044
1045 csum = 0;
1046 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0)
| 1030
1031 csum = 0;
1032 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0)
|
1047 csum |= AXGE_RXCOE_IP | AXGE_RXCOE_TCP | AXGE_RXCOE_UDP |
1048 AXGE_RXCOE_ICMP | AXGE_RXCOE_IGMP;
1049 axge_write_cmd_1(sc, AXGE_ACCESS_MAC, 1, AXGE_RXCOE_CTL, csum);
| 1033 csum |= CRCR_IP | CRCR_TCP | CRCR_UDP;
1034 axge_write_cmd_1(sc, AXGE_ACCESS_MAC, AXGE_CRCR, csum);
|
1050}
| 1035}
|