1/*-
2 * Copyright (c) 2013-2014 Kevin Lo
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
--- 11 unchanged lines hidden (view full) ---
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27#include <sys/cdefs.h>
28__FBSDID("$FreeBSD: head/sys/dev/usb/net/if_axge.c 266490 2014-05-21 08:09:44Z kevlo $");
29
30/*
31 * ASIX Electronics AX88178A/AX88179 USB 2.0/3.0 gigabit ethernet driver.
32 */
33
34#include <sys/param.h>
35#include <sys/systm.h>
36#include <sys/bus.h>
--- 24 unchanged lines hidden (view full) ---
61/*
62 * Various supported device vendors/products.
63 */
64
65static const STRUCT_USB_HOST_ID axge_devs[] = {
66#define AXGE_DEV(v,p) { USB_VP(USB_VENDOR_##v, USB_PRODUCT_##v##_##p) }
67 AXGE_DEV(ASIX, AX88178A),
68 AXGE_DEV(ASIX, AX88179),
69 /* AXGE_DEV(SITECOMEU, LN032), */
70#undef AXGE_DEV
71};
72
73static const struct {
74 uint8_t ctrl;
75 uint8_t timer_l;
76 uint8_t timer_h;
77 uint8_t size;
--- 25 unchanged lines hidden (view full) ---
103static uether_fn_t axge_tick;
104static uether_fn_t axge_setmulti;
105static uether_fn_t axge_setpromisc;
106
107static int axge_read_mem(struct axge_softc *, uint8_t, uint16_t,
108 uint16_t, void *, int);
109static void axge_write_mem(struct axge_softc *, uint8_t, uint16_t,
110 uint16_t, void *, int);
111static uint8_t axge_read_cmd_1(struct axge_softc *, uint8_t, uint16_t,
112 uint16_t);
113static uint16_t axge_read_cmd_2(struct axge_softc *, uint8_t, uint16_t,
114 uint16_t);
115static void axge_write_cmd_1(struct axge_softc *, uint8_t, uint16_t,
116 uint16_t, uint8_t);
117static void axge_write_cmd_2(struct axge_softc *, uint8_t, uint16_t,
118 uint16_t, uint16_t);
119static void axge_chip_init(struct axge_softc *);
120static void axge_reset(struct axge_softc *);
121
122static int axge_attach_post_sub(struct usb_ether *);
123static int axge_ifmedia_upd(struct ifnet *);
124static void axge_ifmedia_sts(struct ifnet *, struct ifmediareq *);
125static int axge_ioctl(struct ifnet *, u_long, caddr_t);
126static int axge_rx_frame(struct usb_ether *, struct usb_page_cache *, int);
127static int axge_rxeof(struct usb_ether *, struct usb_page_cache *,
128 unsigned int, unsigned int, struct axge_csum_hdr *);
129static void axge_csum_cfg(struct usb_ether *);
130
131#define AXGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
132
133#ifdef USB_DEBUG
134static int axge_debug = 0;
135
136static SYSCTL_NODE(_hw_usb, OID_AUTO, axge, CTLFLAG_RW, 0, "USB axge");
137SYSCTL_INT(_hw_usb_axge, OID_AUTO, debug, CTLFLAG_RW, &axge_debug, 0,
138 "Debug level");
139#endif
140
141static const struct usb_config axge_config[AXGE_N_TRANSFER] = {
142 [AXGE_BULK_DT_WR] = {
143 .type = UE_BULK,
144 .endpoint = UE_ADDR_ANY,
145 .direction = UE_DIR_OUT,
146 .frames = 16,
147 .bufsize = 16 * (MCLBYTES + 16),
148 .flags = {.pipe_bof = 1,.force_short_xfer = 1,},
149 .callback = axge_bulk_write_callback,
150 .timeout = 10000, /* 10 seconds */
151 },
152 [AXGE_BULK_DT_RD] = {
153 .type = UE_BULK,
154 .endpoint = UE_ADDR_ANY,
155 .direction = UE_DIR_IN,
--- 79 unchanged lines hidden (view full) ---
235 USETW(req.wLength, len);
236
237 if (uether_do_request(&sc->sc_ue, &req, buf, 1000)) {
238 /* Error ignored. */
239 }
240}
241
242static uint8_t
243axge_read_cmd_1(struct axge_softc *sc, uint8_t cmd, uint16_t index,
244 uint16_t reg)
245{
246 uint8_t val;
247
248 axge_read_mem(sc, cmd, index, reg, &val, 1);
249 return (val);
250}
251
252static uint16_t
253axge_read_cmd_2(struct axge_softc *sc, uint8_t cmd, uint16_t index,
254 uint16_t reg)
255{
256 uint8_t val[2];
257
258 axge_read_mem(sc, cmd, index, reg, &val, 2);
259 return (UGETW(val));
260}
261
262static void
263axge_write_cmd_1(struct axge_softc *sc, uint8_t cmd, uint16_t index,
264 uint16_t reg, uint8_t val)
265{
266 axge_write_mem(sc, cmd, index, reg, &val, 1);
267}
268
269static void
270axge_write_cmd_2(struct axge_softc *sc, uint8_t cmd, uint16_t index,
271 uint16_t reg, uint16_t val)
272{
273 uint8_t temp[2];
274
--- 76 unchanged lines hidden (view full) ---
351 break;
352 }
353 }
354
355 /* Lost link, do nothing. */
356 if ((sc->sc_flags & AXGE_FLAG_LINK) == 0)
357 goto done;
358
359 link_status = axge_read_cmd_1(sc, AXGE_ACCESS_MAC, 1, AXGE_LINK_STATUS);
360
361 val = 0;
362 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) {
363 val |= AXGE_MEDIUM_FULL_DUPLEX;
364 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0)
365 val |= AXGE_MEDIUM_TXFLOW_CTRLEN;
366 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0)
367 val |= AXGE_MEDIUM_RXFLOW_CTRLEN;
368 }
369 val |= AXGE_MEDIUM_RECEIVE_EN;
370 switch (IFM_SUBTYPE(mii->mii_media_active)) {
371 case IFM_1000_T:
372 val |= AXGE_MEDIUM_GIGAMODE | AXGE_MEDIUM_EN_125MHZ;
373 if (link_status & AXGE_LINK_STATUS_USB_SS)
374 memcpy(tmp, &axge_bulk_size[0], 5);
375 else if (link_status & AXGE_LINK_STATUS_USB_HS)
376 memcpy(tmp, &axge_bulk_size[1], 5);
377 else
378 memcpy(tmp, &axge_bulk_size[3], 5);
379 break;
380 case IFM_100_TX:
381 val |= AXGE_MEDIUM_PS;
382 if (link_status &
383 (AXGE_LINK_STATUS_USB_SS | AXGE_LINK_STATUS_USB_HS))
384 memcpy(tmp, &axge_bulk_size[2], 5);
385 else
386 memcpy(tmp, &axge_bulk_size[3], 5);
387 break;
388 case IFM_10_T:
389 memcpy(tmp, &axge_bulk_size[3], 5);
390 break;
391 }
392 /* Rx bulk configuration. */
393 axge_write_mem(sc, AXGE_ACCESS_MAC, 5, AXGE_RX_BULKIN_QCTRL, tmp, 5);
394 axge_write_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_MEDIUM_STATUS_MODE, val);
395done:
396 if (!locked)
397 AXGE_UNLOCK(sc);
398}
399
400static void
401axge_chip_init(struct axge_softc *sc)
402{
403 /* Power up ethernet PHY. */
404 axge_write_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_PHYPWR_RSTCTL, 0);
405 axge_write_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_PHYPWR_RSTCTL,
406 AXGE_PHYPWR_RSTCTL_IPRL);
407 uether_pause(&sc->sc_ue, hz / 4);
408 axge_write_cmd_1(sc, AXGE_ACCESS_MAC, 1, AXGE_CLK_SELECT,
409 AXGE_CLK_SELECT_ACS | AXGE_CLK_SELECT_BCS);
410 uether_pause(&sc->sc_ue, hz / 10);
411}
412
413static void
414axge_reset(struct axge_softc *sc)
415{
416 struct usb_config_descriptor *cd;
--- 18 unchanged lines hidden (view full) ---
435{
436 struct axge_softc *sc;
437
438 sc = uether_getsc(ue);
439 sc->sc_phyno = 3;
440
441 /* Initialize controller and get station address. */
442 axge_chip_init(sc);
443 axge_read_mem(sc, AXGE_ACCESS_MAC, ETHER_ADDR_LEN, AXGE_NODE_ID,
444 ue->ue_eaddr, ETHER_ADDR_LEN);
445}
446
447static int
448axge_attach_post_sub(struct usb_ether *ue)
449{
450 struct axge_softc *sc;
451 struct ifnet *ifp;
--- 152 unchanged lines hidden (view full) ---
604
605 sc = usbd_xfer_softc(xfer);
606 ue = &sc->sc_ue;
607 usbd_xfer_status(xfer, &actlen, NULL, NULL, NULL);
608
609 switch (USB_GET_STATE(xfer)) {
610 case USB_ST_TRANSFERRED:
611 pc = usbd_xfer_get_frame(xfer, 0);
612 axge_rx_frame(ue, pc, actlen);
613
614 /* FALLTHROUGH */
615 case USB_ST_SETUP:
616tr_setup:
617 usbd_xfer_set_frame_len(xfer, 0, usbd_xfer_max_len(xfer));
618 usbd_transfer_submit(xfer);
619 uether_rxflush(ue);
620 return;
--- 11 unchanged lines hidden (view full) ---
632static void
633axge_bulk_write_callback(struct usb_xfer *xfer, usb_error_t error)
634{
635 struct axge_softc *sc;
636 struct ifnet *ifp;
637 struct usb_page_cache *pc;
638 struct mbuf *m;
639 uint32_t txhdr;
640 uint32_t txhdr2;
641 int nframes;
642 int frm_len;
643
644 sc = usbd_xfer_softc(xfer);
645 ifp = uether_getifp(&sc->sc_ue);
646
647 switch (USB_GET_STATE(xfer)) {
648 case USB_ST_TRANSFERRED:
649 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
650 /* FALLTHROUGH */
--- 10 unchanged lines hidden (view full) ---
661
662 for (nframes = 0; nframes < 16 &&
663 !IFQ_DRV_IS_EMPTY(&ifp->if_snd); nframes++) {
664 IFQ_DRV_DEQUEUE(&ifp->if_snd, m);
665 if (m == NULL)
666 break;
667 usbd_xfer_set_frame_offset(xfer, nframes * MCLBYTES,
668 nframes);
669 frm_len = 0;
670 pc = usbd_xfer_get_frame(xfer, nframes);
671
672 txhdr = m->m_pkthdr.len;
673 txhdr = htole32(txhdr);
674 usbd_copy_in(pc, 0, &txhdr, sizeof(txhdr));
675 frm_len += sizeof(txhdr);
676
677 txhdr2 = 0;
678 if ((m->m_pkthdr.len + sizeof(txhdr) + sizeof(txhdr2)) %
679 usbd_xfer_max_framelen(xfer) == 0) {
680 txhdr2 |= 0x80008000;
681 }
682 txhdr2 = htole32(txhdr2);
683 usbd_copy_in(pc, frm_len, &txhdr2, sizeof(txhdr2));
684 frm_len += sizeof(txhdr2);
685
686 /* Next copy in the actual packet. */
687 usbd_m_copy_in(pc, frm_len, m, 0, m->m_pkthdr.len);
688 frm_len += m->m_pkthdr.len;
689
690 /*
691 * XXX
692 * Update TX packet counter here. This is not
693 * correct way but it seems that there is no way
694 * to know how many packets are sent at the end
695 * of transfer because controller combines
696 * multiple writes into single one if there is
697 * room in TX buffer of controller.
--- 4 unchanged lines hidden (view full) ---
702 * if there's a BPF listener, bounce a copy
703 * of this frame to him:
704 */
705 BPF_MTAP(ifp, m);
706
707 m_freem(m);
708
709 /* Set frame length. */
710 usbd_xfer_set_frame_len(xfer, nframes, frm_len);
711 }
712 if (nframes != 0) {
713 usbd_xfer_set_frames(xfer, nframes);
714 usbd_transfer_submit(xfer);
715 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
716 }
717 return;
718 /* NOTREACHED */
--- 38 unchanged lines hidden (view full) ---
757 uint16_t rxmode;
758 uint8_t hashtbl[8] = { 0, 0, 0, 0, 0, 0, 0, 0 };
759
760 sc = uether_getsc(ue);
761 ifp = uether_getifp(ue);
762 h = 0;
763 AXGE_LOCK_ASSERT(sc, MA_OWNED);
764
765 rxmode = axge_read_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_RX_CTL);
766 if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) {
767 rxmode |= AXGE_RX_CTL_AMALL;
768 axge_write_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_RX_CTL, rxmode);
769 return;
770 }
771 rxmode &= ~AXGE_RX_CTL_AMALL;
772
773 if_maddr_rlock(ifp);
774 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
775 if (ifma->ifma_addr->sa_family != AF_LINK)
776 continue;
777 h = ether_crc32_be(LLADDR((struct sockaddr_dl *)
778 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26;
779 hashtbl[h / 8] |= 1 << (h % 8);
780 }
781 if_maddr_runlock(ifp);
782
783 axge_write_mem(sc, AXGE_ACCESS_MAC, 8, AXGE_MULTI_FILTER_ARRY,
784 (void *)&hashtbl, 8);
785 axge_write_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_RX_CTL, rxmode);
786}
787
788static void
789axge_setpromisc(struct usb_ether *ue)
790{
791 struct axge_softc *sc;
792 struct ifnet *ifp;
793 uint16_t rxmode;
794
795 sc = uether_getsc(ue);
796 ifp = uether_getifp(ue);
797 rxmode = axge_read_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_RX_CTL);
798
799 if (ifp->if_flags & IFF_PROMISC)
800 rxmode |= AXGE_RX_CTL_PRO;
801 else
802 rxmode &= ~AXGE_RX_CTL_PRO;
803
804 axge_write_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_RX_CTL, rxmode);
805 axge_setmulti(ue);
806}
807
808static void
809axge_start(struct usb_ether *ue)
810{
811 struct axge_softc *sc;
812
--- 22 unchanged lines hidden (view full) ---
835 /*
836 * Cancel pending I/O and free all RX/TX buffers.
837 */
838 axge_stop(ue);
839
840 axge_reset(sc);
841
842 /* Set MAC address. */
843 axge_write_mem(sc, AXGE_ACCESS_MAC, ETHER_ADDR_LEN, AXGE_NODE_ID,
844 IF_LLADDR(ifp), ETHER_ADDR_LEN);
845
846 axge_write_cmd_1(sc, AXGE_ACCESS_MAC, 1, AXGE_PAUSE_WATERLVL_LOW, 0x34);
847 axge_write_cmd_1(sc, AXGE_ACCESS_MAC, 1, AXGE_PAUSE_WATERLVL_HIGH,
848 0x52);
849
850 /* Configure TX/RX checksum offloading. */
851 axge_csum_cfg(ue);
852
853 /* Configure RX settings. */
854 rxmode = (AXGE_RX_CTL_IPE | AXGE_RX_CTL_AM | AXGE_RX_CTL_START);
855
856 /* If we want promiscuous mode, set the allframes bit. */
857 if (ifp->if_flags & IFF_PROMISC)
858 rxmode |= AXGE_RX_CTL_PRO;
859
860 if (ifp->if_flags & IFF_BROADCAST)
861 rxmode |= AXGE_RX_CTL_AB;
862
863 axge_write_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_RX_CTL, rxmode);
864
865 /* Load the multicast filter. */
866 axge_setmulti(ue);
867
868 usbd_xfer_set_stall(sc->sc_xfer[AXGE_BULK_DT_WR]);
869
870 ifp->if_drv_flags |= IFF_DRV_RUNNING;
871 /* Switch to selected media. */
872 axge_ifmedia_upd(ifp);
--- 61 unchanged lines hidden (view full) ---
934 error = uether_ioctl(ifp, cmd, data);
935
936 return (error);
937}
938
939static int
940axge_rx_frame(struct usb_ether *ue, struct usb_page_cache *pc, int actlen)
941{
942 struct axge_csum_hdr csum_hdr;
943 int error, len, pos;
944 int pkt_cnt;
945 uint32_t rxhdr;
946 uint16_t hdr_off;
947 uint16_t pktlen;
948
949 pos = 0;
950 len = 0;
951 error = 0;
952
953 usbd_copy_out(pc, actlen - sizeof(rxhdr), &rxhdr, sizeof(rxhdr));
954 actlen -= sizeof(rxhdr);
955 rxhdr = le32toh(rxhdr);
956
957 pkt_cnt = (uint16_t)rxhdr;
958 hdr_off = (uint16_t)(rxhdr >> 16);
959
960 usbd_copy_out(pc, pos + hdr_off, &csum_hdr, sizeof(csum_hdr));
961 csum_hdr.len = le16toh(csum_hdr.len);
962 csum_hdr.cstatus = le16toh(csum_hdr.cstatus);
963
964 while (pkt_cnt--) {
965 if (actlen <= sizeof(csum_hdr) + sizeof(struct ether_header)) {
966 error = EINVAL;
967 break;
968 }
969 pktlen = AXGE_CSUM_RXBYTES(csum_hdr.len);
970
971 if (pkt_cnt == 0)
972 /* Skip the 2-byte IP alignment header. */
973 axge_rxeof(ue, pc, 2, pktlen - 2, &csum_hdr);
974 }
975
976 if (error != 0)
977 ue->ue_ifp->if_ierrors++;
978 return (error);
979}
980
981static int
982axge_rxeof(struct usb_ether *ue, struct usb_page_cache *pc,
983 unsigned int offset, unsigned int len, struct axge_csum_hdr *csum_hdr)
984{
985 struct ifnet *ifp;
986 struct mbuf *m;
987
988 ifp = ue->ue_ifp;
989 if (len < ETHER_HDR_LEN || len > MCLBYTES - ETHER_ALIGN) {
990 ifp->if_ierrors++;
991 return (EINVAL);
--- 8 unchanged lines hidden (view full) ---
1000 m_adj(m, ETHER_ALIGN);
1001
1002 usbd_copy_out(pc, offset, mtod(m, uint8_t *), len);
1003
1004 ifp->if_ipackets++;
1005 m->m_pkthdr.rcvif = ifp;
1006 m->m_pkthdr.len = m->m_len = len;
1007
1008 if (csum_hdr != NULL &&
1009 csum_hdr->cstatus & AXGE_CSUM_HDR_L3_TYPE_IPV4) {
1010 if ((csum_hdr->cstatus & (AXGE_CSUM_HDR_L4_CSUM_ERR |
1011 AXGE_RXHDR_L4CSUM_ERR)) == 0) {
1012 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED |
1013 CSUM_IP_VALID;
1014 if ((csum_hdr->cstatus & AXGE_CSUM_HDR_L4_TYPE_MASK) ==
1015 AXGE_CSUM_HDR_L4_TYPE_TCP ||
1016 (csum_hdr->cstatus & AXGE_CSUM_HDR_L4_TYPE_MASK) ==
1017 AXGE_CSUM_HDR_L4_TYPE_UDP) {
1018 m->m_pkthdr.csum_flags |=
1019 CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
1020 m->m_pkthdr.csum_data = 0xffff;
1021 }
1022 }
1023 }
1024
1025 _IF_ENQUEUE(&ue->ue_rxq, m);
1026 return (0);
1027}
1028
1029static void
--- 4 unchanged lines hidden (view full) ---
1034 uint8_t csum;
1035
1036 sc = uether_getsc(ue);
1037 AXGE_LOCK_ASSERT(sc, MA_OWNED);
1038 ifp = uether_getifp(ue);
1039
1040 csum = 0;
1041 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0)
1042 csum |= AXGE_TXCOE_IP | AXGE_TXCOE_TCP | AXGE_TXCOE_UDP;
1043 axge_write_cmd_1(sc, AXGE_ACCESS_MAC, 1, AXGE_TXCOE_CTL, csum);
1044
1045 csum = 0;
1046 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0)
1047 csum |= AXGE_RXCOE_IP | AXGE_RXCOE_TCP | AXGE_RXCOE_UDP |
1048 AXGE_RXCOE_ICMP | AXGE_RXCOE_IGMP;
1049 axge_write_cmd_1(sc, AXGE_ACCESS_MAC, 1, AXGE_RXCOE_CTL, csum);
1050}
2 * Copyright (c) 2013-2014 Kevin Lo
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
--- 11 unchanged lines hidden (view full) ---
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27#include <sys/cdefs.h>
28__FBSDID("$FreeBSD: head/sys/dev/usb/net/if_axge.c 266490 2014-05-21 08:09:44Z kevlo $");
29
30/*
31 * ASIX Electronics AX88178A/AX88179 USB 2.0/3.0 gigabit ethernet driver.
32 */
33
34#include <sys/param.h>
35#include <sys/systm.h>
36#include <sys/bus.h>
--- 24 unchanged lines hidden (view full) ---
61/*
62 * Various supported device vendors/products.
63 */
64
65static const STRUCT_USB_HOST_ID axge_devs[] = {
66#define AXGE_DEV(v,p) { USB_VP(USB_VENDOR_##v, USB_PRODUCT_##v##_##p) }
67 AXGE_DEV(ASIX, AX88178A),
68 AXGE_DEV(ASIX, AX88179),
69 /* AXGE_DEV(SITECOMEU, LN032), */
70#undef AXGE_DEV
71};
72
73static const struct {
74 uint8_t ctrl;
75 uint8_t timer_l;
76 uint8_t timer_h;
77 uint8_t size;
--- 25 unchanged lines hidden (view full) ---
103static uether_fn_t axge_tick;
104static uether_fn_t axge_setmulti;
105static uether_fn_t axge_setpromisc;
106
107static int axge_read_mem(struct axge_softc *, uint8_t, uint16_t,
108 uint16_t, void *, int);
109static void axge_write_mem(struct axge_softc *, uint8_t, uint16_t,
110 uint16_t, void *, int);
111static uint8_t axge_read_cmd_1(struct axge_softc *, uint8_t, uint16_t,
112 uint16_t);
113static uint16_t axge_read_cmd_2(struct axge_softc *, uint8_t, uint16_t,
114 uint16_t);
115static void axge_write_cmd_1(struct axge_softc *, uint8_t, uint16_t,
116 uint16_t, uint8_t);
117static void axge_write_cmd_2(struct axge_softc *, uint8_t, uint16_t,
118 uint16_t, uint16_t);
119static void axge_chip_init(struct axge_softc *);
120static void axge_reset(struct axge_softc *);
121
122static int axge_attach_post_sub(struct usb_ether *);
123static int axge_ifmedia_upd(struct ifnet *);
124static void axge_ifmedia_sts(struct ifnet *, struct ifmediareq *);
125static int axge_ioctl(struct ifnet *, u_long, caddr_t);
126static int axge_rx_frame(struct usb_ether *, struct usb_page_cache *, int);
127static int axge_rxeof(struct usb_ether *, struct usb_page_cache *,
128 unsigned int, unsigned int, struct axge_csum_hdr *);
129static void axge_csum_cfg(struct usb_ether *);
130
131#define AXGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
132
133#ifdef USB_DEBUG
134static int axge_debug = 0;
135
136static SYSCTL_NODE(_hw_usb, OID_AUTO, axge, CTLFLAG_RW, 0, "USB axge");
137SYSCTL_INT(_hw_usb_axge, OID_AUTO, debug, CTLFLAG_RW, &axge_debug, 0,
138 "Debug level");
139#endif
140
141static const struct usb_config axge_config[AXGE_N_TRANSFER] = {
142 [AXGE_BULK_DT_WR] = {
143 .type = UE_BULK,
144 .endpoint = UE_ADDR_ANY,
145 .direction = UE_DIR_OUT,
146 .frames = 16,
147 .bufsize = 16 * (MCLBYTES + 16),
148 .flags = {.pipe_bof = 1,.force_short_xfer = 1,},
149 .callback = axge_bulk_write_callback,
150 .timeout = 10000, /* 10 seconds */
151 },
152 [AXGE_BULK_DT_RD] = {
153 .type = UE_BULK,
154 .endpoint = UE_ADDR_ANY,
155 .direction = UE_DIR_IN,
--- 79 unchanged lines hidden (view full) ---
235 USETW(req.wLength, len);
236
237 if (uether_do_request(&sc->sc_ue, &req, buf, 1000)) {
238 /* Error ignored. */
239 }
240}
241
242static uint8_t
243axge_read_cmd_1(struct axge_softc *sc, uint8_t cmd, uint16_t index,
244 uint16_t reg)
245{
246 uint8_t val;
247
248 axge_read_mem(sc, cmd, index, reg, &val, 1);
249 return (val);
250}
251
252static uint16_t
253axge_read_cmd_2(struct axge_softc *sc, uint8_t cmd, uint16_t index,
254 uint16_t reg)
255{
256 uint8_t val[2];
257
258 axge_read_mem(sc, cmd, index, reg, &val, 2);
259 return (UGETW(val));
260}
261
262static void
263axge_write_cmd_1(struct axge_softc *sc, uint8_t cmd, uint16_t index,
264 uint16_t reg, uint8_t val)
265{
266 axge_write_mem(sc, cmd, index, reg, &val, 1);
267}
268
269static void
270axge_write_cmd_2(struct axge_softc *sc, uint8_t cmd, uint16_t index,
271 uint16_t reg, uint16_t val)
272{
273 uint8_t temp[2];
274
--- 76 unchanged lines hidden (view full) ---
351 break;
352 }
353 }
354
355 /* Lost link, do nothing. */
356 if ((sc->sc_flags & AXGE_FLAG_LINK) == 0)
357 goto done;
358
359 link_status = axge_read_cmd_1(sc, AXGE_ACCESS_MAC, 1, AXGE_LINK_STATUS);
360
361 val = 0;
362 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) {
363 val |= AXGE_MEDIUM_FULL_DUPLEX;
364 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0)
365 val |= AXGE_MEDIUM_TXFLOW_CTRLEN;
366 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0)
367 val |= AXGE_MEDIUM_RXFLOW_CTRLEN;
368 }
369 val |= AXGE_MEDIUM_RECEIVE_EN;
370 switch (IFM_SUBTYPE(mii->mii_media_active)) {
371 case IFM_1000_T:
372 val |= AXGE_MEDIUM_GIGAMODE | AXGE_MEDIUM_EN_125MHZ;
373 if (link_status & AXGE_LINK_STATUS_USB_SS)
374 memcpy(tmp, &axge_bulk_size[0], 5);
375 else if (link_status & AXGE_LINK_STATUS_USB_HS)
376 memcpy(tmp, &axge_bulk_size[1], 5);
377 else
378 memcpy(tmp, &axge_bulk_size[3], 5);
379 break;
380 case IFM_100_TX:
381 val |= AXGE_MEDIUM_PS;
382 if (link_status &
383 (AXGE_LINK_STATUS_USB_SS | AXGE_LINK_STATUS_USB_HS))
384 memcpy(tmp, &axge_bulk_size[2], 5);
385 else
386 memcpy(tmp, &axge_bulk_size[3], 5);
387 break;
388 case IFM_10_T:
389 memcpy(tmp, &axge_bulk_size[3], 5);
390 break;
391 }
392 /* Rx bulk configuration. */
393 axge_write_mem(sc, AXGE_ACCESS_MAC, 5, AXGE_RX_BULKIN_QCTRL, tmp, 5);
394 axge_write_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_MEDIUM_STATUS_MODE, val);
395done:
396 if (!locked)
397 AXGE_UNLOCK(sc);
398}
399
400static void
401axge_chip_init(struct axge_softc *sc)
402{
403 /* Power up ethernet PHY. */
404 axge_write_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_PHYPWR_RSTCTL, 0);
405 axge_write_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_PHYPWR_RSTCTL,
406 AXGE_PHYPWR_RSTCTL_IPRL);
407 uether_pause(&sc->sc_ue, hz / 4);
408 axge_write_cmd_1(sc, AXGE_ACCESS_MAC, 1, AXGE_CLK_SELECT,
409 AXGE_CLK_SELECT_ACS | AXGE_CLK_SELECT_BCS);
410 uether_pause(&sc->sc_ue, hz / 10);
411}
412
413static void
414axge_reset(struct axge_softc *sc)
415{
416 struct usb_config_descriptor *cd;
--- 18 unchanged lines hidden (view full) ---
435{
436 struct axge_softc *sc;
437
438 sc = uether_getsc(ue);
439 sc->sc_phyno = 3;
440
441 /* Initialize controller and get station address. */
442 axge_chip_init(sc);
443 axge_read_mem(sc, AXGE_ACCESS_MAC, ETHER_ADDR_LEN, AXGE_NODE_ID,
444 ue->ue_eaddr, ETHER_ADDR_LEN);
445}
446
447static int
448axge_attach_post_sub(struct usb_ether *ue)
449{
450 struct axge_softc *sc;
451 struct ifnet *ifp;
--- 152 unchanged lines hidden (view full) ---
604
605 sc = usbd_xfer_softc(xfer);
606 ue = &sc->sc_ue;
607 usbd_xfer_status(xfer, &actlen, NULL, NULL, NULL);
608
609 switch (USB_GET_STATE(xfer)) {
610 case USB_ST_TRANSFERRED:
611 pc = usbd_xfer_get_frame(xfer, 0);
612 axge_rx_frame(ue, pc, actlen);
613
614 /* FALLTHROUGH */
615 case USB_ST_SETUP:
616tr_setup:
617 usbd_xfer_set_frame_len(xfer, 0, usbd_xfer_max_len(xfer));
618 usbd_transfer_submit(xfer);
619 uether_rxflush(ue);
620 return;
--- 11 unchanged lines hidden (view full) ---
632static void
633axge_bulk_write_callback(struct usb_xfer *xfer, usb_error_t error)
634{
635 struct axge_softc *sc;
636 struct ifnet *ifp;
637 struct usb_page_cache *pc;
638 struct mbuf *m;
639 uint32_t txhdr;
640 uint32_t txhdr2;
641 int nframes;
642 int frm_len;
643
644 sc = usbd_xfer_softc(xfer);
645 ifp = uether_getifp(&sc->sc_ue);
646
647 switch (USB_GET_STATE(xfer)) {
648 case USB_ST_TRANSFERRED:
649 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
650 /* FALLTHROUGH */
--- 10 unchanged lines hidden (view full) ---
661
662 for (nframes = 0; nframes < 16 &&
663 !IFQ_DRV_IS_EMPTY(&ifp->if_snd); nframes++) {
664 IFQ_DRV_DEQUEUE(&ifp->if_snd, m);
665 if (m == NULL)
666 break;
667 usbd_xfer_set_frame_offset(xfer, nframes * MCLBYTES,
668 nframes);
669 frm_len = 0;
670 pc = usbd_xfer_get_frame(xfer, nframes);
671
672 txhdr = m->m_pkthdr.len;
673 txhdr = htole32(txhdr);
674 usbd_copy_in(pc, 0, &txhdr, sizeof(txhdr));
675 frm_len += sizeof(txhdr);
676
677 txhdr2 = 0;
678 if ((m->m_pkthdr.len + sizeof(txhdr) + sizeof(txhdr2)) %
679 usbd_xfer_max_framelen(xfer) == 0) {
680 txhdr2 |= 0x80008000;
681 }
682 txhdr2 = htole32(txhdr2);
683 usbd_copy_in(pc, frm_len, &txhdr2, sizeof(txhdr2));
684 frm_len += sizeof(txhdr2);
685
686 /* Next copy in the actual packet. */
687 usbd_m_copy_in(pc, frm_len, m, 0, m->m_pkthdr.len);
688 frm_len += m->m_pkthdr.len;
689
690 /*
691 * XXX
692 * Update TX packet counter here. This is not
693 * correct way but it seems that there is no way
694 * to know how many packets are sent at the end
695 * of transfer because controller combines
696 * multiple writes into single one if there is
697 * room in TX buffer of controller.
--- 4 unchanged lines hidden (view full) ---
702 * if there's a BPF listener, bounce a copy
703 * of this frame to him:
704 */
705 BPF_MTAP(ifp, m);
706
707 m_freem(m);
708
709 /* Set frame length. */
710 usbd_xfer_set_frame_len(xfer, nframes, frm_len);
711 }
712 if (nframes != 0) {
713 usbd_xfer_set_frames(xfer, nframes);
714 usbd_transfer_submit(xfer);
715 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
716 }
717 return;
718 /* NOTREACHED */
--- 38 unchanged lines hidden (view full) ---
757 uint16_t rxmode;
758 uint8_t hashtbl[8] = { 0, 0, 0, 0, 0, 0, 0, 0 };
759
760 sc = uether_getsc(ue);
761 ifp = uether_getifp(ue);
762 h = 0;
763 AXGE_LOCK_ASSERT(sc, MA_OWNED);
764
765 rxmode = axge_read_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_RX_CTL);
766 if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) {
767 rxmode |= AXGE_RX_CTL_AMALL;
768 axge_write_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_RX_CTL, rxmode);
769 return;
770 }
771 rxmode &= ~AXGE_RX_CTL_AMALL;
772
773 if_maddr_rlock(ifp);
774 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
775 if (ifma->ifma_addr->sa_family != AF_LINK)
776 continue;
777 h = ether_crc32_be(LLADDR((struct sockaddr_dl *)
778 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26;
779 hashtbl[h / 8] |= 1 << (h % 8);
780 }
781 if_maddr_runlock(ifp);
782
783 axge_write_mem(sc, AXGE_ACCESS_MAC, 8, AXGE_MULTI_FILTER_ARRY,
784 (void *)&hashtbl, 8);
785 axge_write_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_RX_CTL, rxmode);
786}
787
788static void
789axge_setpromisc(struct usb_ether *ue)
790{
791 struct axge_softc *sc;
792 struct ifnet *ifp;
793 uint16_t rxmode;
794
795 sc = uether_getsc(ue);
796 ifp = uether_getifp(ue);
797 rxmode = axge_read_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_RX_CTL);
798
799 if (ifp->if_flags & IFF_PROMISC)
800 rxmode |= AXGE_RX_CTL_PRO;
801 else
802 rxmode &= ~AXGE_RX_CTL_PRO;
803
804 axge_write_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_RX_CTL, rxmode);
805 axge_setmulti(ue);
806}
807
808static void
809axge_start(struct usb_ether *ue)
810{
811 struct axge_softc *sc;
812
--- 22 unchanged lines hidden (view full) ---
835 /*
836 * Cancel pending I/O and free all RX/TX buffers.
837 */
838 axge_stop(ue);
839
840 axge_reset(sc);
841
842 /* Set MAC address. */
843 axge_write_mem(sc, AXGE_ACCESS_MAC, ETHER_ADDR_LEN, AXGE_NODE_ID,
844 IF_LLADDR(ifp), ETHER_ADDR_LEN);
845
846 axge_write_cmd_1(sc, AXGE_ACCESS_MAC, 1, AXGE_PAUSE_WATERLVL_LOW, 0x34);
847 axge_write_cmd_1(sc, AXGE_ACCESS_MAC, 1, AXGE_PAUSE_WATERLVL_HIGH,
848 0x52);
849
850 /* Configure TX/RX checksum offloading. */
851 axge_csum_cfg(ue);
852
853 /* Configure RX settings. */
854 rxmode = (AXGE_RX_CTL_IPE | AXGE_RX_CTL_AM | AXGE_RX_CTL_START);
855
856 /* If we want promiscuous mode, set the allframes bit. */
857 if (ifp->if_flags & IFF_PROMISC)
858 rxmode |= AXGE_RX_CTL_PRO;
859
860 if (ifp->if_flags & IFF_BROADCAST)
861 rxmode |= AXGE_RX_CTL_AB;
862
863 axge_write_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_RX_CTL, rxmode);
864
865 /* Load the multicast filter. */
866 axge_setmulti(ue);
867
868 usbd_xfer_set_stall(sc->sc_xfer[AXGE_BULK_DT_WR]);
869
870 ifp->if_drv_flags |= IFF_DRV_RUNNING;
871 /* Switch to selected media. */
872 axge_ifmedia_upd(ifp);
--- 61 unchanged lines hidden (view full) ---
934 error = uether_ioctl(ifp, cmd, data);
935
936 return (error);
937}
938
939static int
940axge_rx_frame(struct usb_ether *ue, struct usb_page_cache *pc, int actlen)
941{
942 struct axge_csum_hdr csum_hdr;
943 int error, len, pos;
944 int pkt_cnt;
945 uint32_t rxhdr;
946 uint16_t hdr_off;
947 uint16_t pktlen;
948
949 pos = 0;
950 len = 0;
951 error = 0;
952
953 usbd_copy_out(pc, actlen - sizeof(rxhdr), &rxhdr, sizeof(rxhdr));
954 actlen -= sizeof(rxhdr);
955 rxhdr = le32toh(rxhdr);
956
957 pkt_cnt = (uint16_t)rxhdr;
958 hdr_off = (uint16_t)(rxhdr >> 16);
959
960 usbd_copy_out(pc, pos + hdr_off, &csum_hdr, sizeof(csum_hdr));
961 csum_hdr.len = le16toh(csum_hdr.len);
962 csum_hdr.cstatus = le16toh(csum_hdr.cstatus);
963
964 while (pkt_cnt--) {
965 if (actlen <= sizeof(csum_hdr) + sizeof(struct ether_header)) {
966 error = EINVAL;
967 break;
968 }
969 pktlen = AXGE_CSUM_RXBYTES(csum_hdr.len);
970
971 if (pkt_cnt == 0)
972 /* Skip the 2-byte IP alignment header. */
973 axge_rxeof(ue, pc, 2, pktlen - 2, &csum_hdr);
974 }
975
976 if (error != 0)
977 ue->ue_ifp->if_ierrors++;
978 return (error);
979}
980
981static int
982axge_rxeof(struct usb_ether *ue, struct usb_page_cache *pc,
983 unsigned int offset, unsigned int len, struct axge_csum_hdr *csum_hdr)
984{
985 struct ifnet *ifp;
986 struct mbuf *m;
987
988 ifp = ue->ue_ifp;
989 if (len < ETHER_HDR_LEN || len > MCLBYTES - ETHER_ALIGN) {
990 ifp->if_ierrors++;
991 return (EINVAL);
--- 8 unchanged lines hidden (view full) ---
1000 m_adj(m, ETHER_ALIGN);
1001
1002 usbd_copy_out(pc, offset, mtod(m, uint8_t *), len);
1003
1004 ifp->if_ipackets++;
1005 m->m_pkthdr.rcvif = ifp;
1006 m->m_pkthdr.len = m->m_len = len;
1007
1008 if (csum_hdr != NULL &&
1009 csum_hdr->cstatus & AXGE_CSUM_HDR_L3_TYPE_IPV4) {
1010 if ((csum_hdr->cstatus & (AXGE_CSUM_HDR_L4_CSUM_ERR |
1011 AXGE_RXHDR_L4CSUM_ERR)) == 0) {
1012 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED |
1013 CSUM_IP_VALID;
1014 if ((csum_hdr->cstatus & AXGE_CSUM_HDR_L4_TYPE_MASK) ==
1015 AXGE_CSUM_HDR_L4_TYPE_TCP ||
1016 (csum_hdr->cstatus & AXGE_CSUM_HDR_L4_TYPE_MASK) ==
1017 AXGE_CSUM_HDR_L4_TYPE_UDP) {
1018 m->m_pkthdr.csum_flags |=
1019 CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
1020 m->m_pkthdr.csum_data = 0xffff;
1021 }
1022 }
1023 }
1024
1025 _IF_ENQUEUE(&ue->ue_rxq, m);
1026 return (0);
1027}
1028
1029static void
--- 4 unchanged lines hidden (view full) ---
1034 uint8_t csum;
1035
1036 sc = uether_getsc(ue);
1037 AXGE_LOCK_ASSERT(sc, MA_OWNED);
1038 ifp = uether_getifp(ue);
1039
1040 csum = 0;
1041 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0)
1042 csum |= AXGE_TXCOE_IP | AXGE_TXCOE_TCP | AXGE_TXCOE_UDP;
1043 axge_write_cmd_1(sc, AXGE_ACCESS_MAC, 1, AXGE_TXCOE_CTL, csum);
1044
1045 csum = 0;
1046 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0)
1047 csum |= AXGE_RXCOE_IP | AXGE_RXCOE_TCP | AXGE_RXCOE_UDP |
1048 AXGE_RXCOE_ICMP | AXGE_RXCOE_IGMP;
1049 axge_write_cmd_1(sc, AXGE_ACCESS_MAC, 1, AXGE_RXCOE_CTL, csum);
1050}