1/*-
2 * Copyright (c) 1997, 1998, 1999, 2000-2003
3 * Bill Paul <wpaul@windriver.com>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
31 */
32
33#include <sys/cdefs.h>
| 1/*-
2 * Copyright (c) 1997, 1998, 1999, 2000-2003
3 * Bill Paul <wpaul@windriver.com>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
31 */
32
33#include <sys/cdefs.h>
|
34__FBSDID("$FreeBSD: head/sys/dev/usb/net/if_axe.c 215966 2010-11-28 01:16:37Z yongari $");
| 34__FBSDID("$FreeBSD: head/sys/dev/usb/net/if_axe.c 215968 2010-11-28 01:43:28Z yongari $");
|
35
36/*
37 * ASIX Electronics AX88172/AX88178/AX88778 USB 2.0 ethernet driver.
38 * Used in the LinkSys USB200M and various other adapters.
39 *
40 * Manuals available from:
41 * http://www.asix.com.tw/datasheet/mac/Ax88172.PDF
42 * Note: you need the manual for the AX88170 chip (USB 1.x ethernet
43 * controller) to find the definitions for the RX control register.
44 * http://www.asix.com.tw/datasheet/mac/Ax88170.PDF
45 *
46 * Written by Bill Paul <wpaul@windriver.com>
47 * Senior Engineer
48 * Wind River Systems
49 */
50
51/*
52 * The AX88172 provides USB ethernet supports at 10 and 100Mbps.
53 * It uses an external PHY (reference designs use a RealTek chip),
54 * and has a 64-bit multicast hash filter. There is some information
55 * missing from the manual which one needs to know in order to make
56 * the chip function:
57 *
58 * - You must set bit 7 in the RX control register, otherwise the
59 * chip won't receive any packets.
60 * - You must initialize all 3 IPG registers, or you won't be able
61 * to send any packets.
62 *
63 * Note that this device appears to only support loading the station
64 * address via autload from the EEPROM (i.e. there's no way to manaully
65 * set it).
66 *
67 * (Adam Weinberger wanted me to name this driver if_gir.c.)
68 */
69
70/*
71 * Ax88178 and Ax88772 support backported from the OpenBSD driver.
72 * 2007/02/12, J.R. Oldroyd, fbsd@opal.com
73 *
74 * Manual here:
75 * http://www.asix.com.tw/FrootAttach/datasheet/AX88178_datasheet_Rev10.pdf
76 * http://www.asix.com.tw/FrootAttach/datasheet/AX88772_datasheet_Rev10.pdf
77 */
78
79#include <sys/stdint.h>
80#include <sys/stddef.h>
81#include <sys/param.h>
82#include <sys/queue.h>
83#include <sys/types.h>
84#include <sys/systm.h>
85#include <sys/kernel.h>
86#include <sys/bus.h>
87#include <sys/linker_set.h>
88#include <sys/module.h>
89#include <sys/lock.h>
90#include <sys/mutex.h>
91#include <sys/condvar.h>
92#include <sys/sysctl.h>
93#include <sys/sx.h>
94#include <sys/unistd.h>
95#include <sys/callout.h>
96#include <sys/malloc.h>
97#include <sys/priv.h>
98
99#include <dev/usb/usb.h>
100#include <dev/usb/usbdi.h>
101#include <dev/usb/usbdi_util.h>
102#include "usbdevs.h"
103
104#define USB_DEBUG_VAR axe_debug
105#include <dev/usb/usb_debug.h>
106#include <dev/usb/usb_process.h>
107
108#include <dev/usb/net/usb_ethernet.h>
109#include <dev/usb/net/if_axereg.h>
110
111/*
112 * AXE_178_MAX_FRAME_BURST
113 * max frame burst size for Ax88178 and Ax88772
114 * 0 2048 bytes
115 * 1 4096 bytes
116 * 2 8192 bytes
117 * 3 16384 bytes
118 * use the largest your system can handle without USB stalling.
119 *
120 * NB: 88772 parts appear to generate lots of input errors with
121 * a 2K rx buffer and 8K is only slightly faster than 4K on an
122 * EHCI port on a T42 so change at your own risk.
123 */
124#define AXE_178_MAX_FRAME_BURST 1
125
126#ifdef USB_DEBUG
127static int axe_debug = 0;
128
129SYSCTL_NODE(_hw_usb, OID_AUTO, axe, CTLFLAG_RW, 0, "USB axe");
130SYSCTL_INT(_hw_usb_axe, OID_AUTO, debug, CTLFLAG_RW, &axe_debug, 0,
131 "Debug level");
132#endif
133
134/*
135 * Various supported device vendors/products.
136 */
137static const struct usb_device_id axe_devs[] = {
138#define AXE_DEV(v,p,i) { USB_VPI(USB_VENDOR_##v, USB_PRODUCT_##v##_##p, i) }
139 AXE_DEV(ABOCOM, UF200, 0),
140 AXE_DEV(ACERCM, EP1427X2, 0),
141 AXE_DEV(APPLE, ETHERNET, AXE_FLAG_772),
142 AXE_DEV(ASIX, AX88172, 0),
143 AXE_DEV(ASIX, AX88178, AXE_FLAG_178),
144 AXE_DEV(ASIX, AX88772, AXE_FLAG_772),
145 AXE_DEV(ASIX, AX88772A, AXE_FLAG_772),
146 AXE_DEV(ATEN, UC210T, 0),
147 AXE_DEV(BELKIN, F5D5055, AXE_FLAG_178),
148 AXE_DEV(BILLIONTON, USB2AR, 0),
149 AXE_DEV(CISCOLINKSYS, USB200MV2, AXE_FLAG_772),
150 AXE_DEV(COREGA, FETHER_USB2_TX, 0),
151 AXE_DEV(DLINK, DUBE100, 0),
152 AXE_DEV(DLINK, DUBE100B1, AXE_FLAG_772),
153 AXE_DEV(GOODWAY, GWUSB2E, 0),
154 AXE_DEV(IODATA, ETGUS2, AXE_FLAG_178),
155 AXE_DEV(JVC, MP_PRX1, 0),
156 AXE_DEV(LINKSYS2, USB200M, 0),
157 AXE_DEV(LINKSYS4, USB1000, AXE_FLAG_178),
158 AXE_DEV(LOGITEC, LAN_GTJU2A, AXE_FLAG_178),
159 AXE_DEV(MELCO, LUAU2KTX, 0),
160 AXE_DEV(MELCO, LUA3U2AGT, AXE_FLAG_178),
161 AXE_DEV(NETGEAR, FA120, 0),
162 AXE_DEV(OQO, ETHER01PLUS, AXE_FLAG_772),
163 AXE_DEV(PLANEX3, GU1000T, AXE_FLAG_178),
164 AXE_DEV(SITECOM, LN029, 0),
165 AXE_DEV(SITECOMEU, LN028, AXE_FLAG_178),
166 AXE_DEV(SYSTEMTALKS, SGCX2UL, 0),
167#undef AXE_DEV
168};
169
170static device_probe_t axe_probe;
171static device_attach_t axe_attach;
172static device_detach_t axe_detach;
173
174static usb_callback_t axe_bulk_read_callback;
175static usb_callback_t axe_bulk_write_callback;
176
177static miibus_readreg_t axe_miibus_readreg;
178static miibus_writereg_t axe_miibus_writereg;
179static miibus_statchg_t axe_miibus_statchg;
180
181static uether_fn_t axe_attach_post;
182static uether_fn_t axe_init;
183static uether_fn_t axe_stop;
184static uether_fn_t axe_start;
185static uether_fn_t axe_tick;
186static uether_fn_t axe_setmulti;
187static uether_fn_t axe_setpromisc;
188
189static int axe_ifmedia_upd(struct ifnet *);
190static void axe_ifmedia_sts(struct ifnet *, struct ifmediareq *);
191static int axe_cmd(struct axe_softc *, int, int, int, void *);
192static void axe_ax88178_init(struct axe_softc *);
193static void axe_ax88772_init(struct axe_softc *);
194static int axe_get_phyno(struct axe_softc *, int);
195
196static const struct usb_config axe_config[AXE_N_TRANSFER] = {
197
198 [AXE_BULK_DT_WR] = {
199 .type = UE_BULK,
200 .endpoint = UE_ADDR_ANY,
201 .direction = UE_DIR_OUT,
202 .bufsize = AXE_BULK_BUF_SIZE,
203 .flags = {.pipe_bof = 1,.force_short_xfer = 1,},
204 .callback = axe_bulk_write_callback,
205 .timeout = 10000, /* 10 seconds */
206 },
207
208 [AXE_BULK_DT_RD] = {
209 .type = UE_BULK,
210 .endpoint = UE_ADDR_ANY,
211 .direction = UE_DIR_IN,
212 .bufsize = 16384, /* bytes */
213 .flags = {.pipe_bof = 1,.short_xfer_ok = 1,},
214 .callback = axe_bulk_read_callback,
215 .timeout = 0, /* no timeout */
216 },
217};
218
219static device_method_t axe_methods[] = {
220 /* Device interface */
221 DEVMETHOD(device_probe, axe_probe),
222 DEVMETHOD(device_attach, axe_attach),
223 DEVMETHOD(device_detach, axe_detach),
224
225 /* bus interface */
226 DEVMETHOD(bus_print_child, bus_generic_print_child),
227 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
228
229 /* MII interface */
230 DEVMETHOD(miibus_readreg, axe_miibus_readreg),
231 DEVMETHOD(miibus_writereg, axe_miibus_writereg),
232 DEVMETHOD(miibus_statchg, axe_miibus_statchg),
233
234 {0, 0}
235};
236
237static driver_t axe_driver = {
238 .name = "axe",
239 .methods = axe_methods,
240 .size = sizeof(struct axe_softc),
241};
242
243static devclass_t axe_devclass;
244
245DRIVER_MODULE(axe, uhub, axe_driver, axe_devclass, NULL, 0);
246DRIVER_MODULE(miibus, axe, miibus_driver, miibus_devclass, 0, 0);
247MODULE_DEPEND(axe, uether, 1, 1, 1);
248MODULE_DEPEND(axe, usb, 1, 1, 1);
249MODULE_DEPEND(axe, ether, 1, 1, 1);
250MODULE_DEPEND(axe, miibus, 1, 1, 1);
251MODULE_VERSION(axe, 1);
252
253static const struct usb_ether_methods axe_ue_methods = {
254 .ue_attach_post = axe_attach_post,
255 .ue_start = axe_start,
256 .ue_init = axe_init,
257 .ue_stop = axe_stop,
258 .ue_tick = axe_tick,
259 .ue_setmulti = axe_setmulti,
260 .ue_setpromisc = axe_setpromisc,
261 .ue_mii_upd = axe_ifmedia_upd,
262 .ue_mii_sts = axe_ifmedia_sts,
263};
264
265static int
266axe_cmd(struct axe_softc *sc, int cmd, int index, int val, void *buf)
267{
268 struct usb_device_request req;
269 usb_error_t err;
270
271 AXE_LOCK_ASSERT(sc, MA_OWNED);
272
273 req.bmRequestType = (AXE_CMD_IS_WRITE(cmd) ?
274 UT_WRITE_VENDOR_DEVICE :
275 UT_READ_VENDOR_DEVICE);
276 req.bRequest = AXE_CMD_CMD(cmd);
277 USETW(req.wValue, val);
278 USETW(req.wIndex, index);
279 USETW(req.wLength, AXE_CMD_LEN(cmd));
280
281 err = uether_do_request(&sc->sc_ue, &req, buf, 1000);
282
283 return (err);
284}
285
286static int
287axe_miibus_readreg(device_t dev, int phy, int reg)
288{
289 struct axe_softc *sc = device_get_softc(dev);
290 uint16_t val;
291 int locked;
292
293 if (sc->sc_phyno != phy)
294 return (0);
295
296 locked = mtx_owned(&sc->sc_mtx);
297 if (!locked)
298 AXE_LOCK(sc);
299
300 axe_cmd(sc, AXE_CMD_MII_OPMODE_SW, 0, 0, NULL);
301 axe_cmd(sc, AXE_CMD_MII_READ_REG, reg, phy, &val);
302 axe_cmd(sc, AXE_CMD_MII_OPMODE_HW, 0, 0, NULL);
303
304 val = le16toh(val);
| 35
36/*
37 * ASIX Electronics AX88172/AX88178/AX88778 USB 2.0 ethernet driver.
38 * Used in the LinkSys USB200M and various other adapters.
39 *
40 * Manuals available from:
41 * http://www.asix.com.tw/datasheet/mac/Ax88172.PDF
42 * Note: you need the manual for the AX88170 chip (USB 1.x ethernet
43 * controller) to find the definitions for the RX control register.
44 * http://www.asix.com.tw/datasheet/mac/Ax88170.PDF
45 *
46 * Written by Bill Paul <wpaul@windriver.com>
47 * Senior Engineer
48 * Wind River Systems
49 */
50
51/*
52 * The AX88172 provides USB ethernet supports at 10 and 100Mbps.
53 * It uses an external PHY (reference designs use a RealTek chip),
54 * and has a 64-bit multicast hash filter. There is some information
55 * missing from the manual which one needs to know in order to make
56 * the chip function:
57 *
58 * - You must set bit 7 in the RX control register, otherwise the
59 * chip won't receive any packets.
60 * - You must initialize all 3 IPG registers, or you won't be able
61 * to send any packets.
62 *
63 * Note that this device appears to only support loading the station
64 * address via autload from the EEPROM (i.e. there's no way to manaully
65 * set it).
66 *
67 * (Adam Weinberger wanted me to name this driver if_gir.c.)
68 */
69
70/*
71 * Ax88178 and Ax88772 support backported from the OpenBSD driver.
72 * 2007/02/12, J.R. Oldroyd, fbsd@opal.com
73 *
74 * Manual here:
75 * http://www.asix.com.tw/FrootAttach/datasheet/AX88178_datasheet_Rev10.pdf
76 * http://www.asix.com.tw/FrootAttach/datasheet/AX88772_datasheet_Rev10.pdf
77 */
78
79#include <sys/stdint.h>
80#include <sys/stddef.h>
81#include <sys/param.h>
82#include <sys/queue.h>
83#include <sys/types.h>
84#include <sys/systm.h>
85#include <sys/kernel.h>
86#include <sys/bus.h>
87#include <sys/linker_set.h>
88#include <sys/module.h>
89#include <sys/lock.h>
90#include <sys/mutex.h>
91#include <sys/condvar.h>
92#include <sys/sysctl.h>
93#include <sys/sx.h>
94#include <sys/unistd.h>
95#include <sys/callout.h>
96#include <sys/malloc.h>
97#include <sys/priv.h>
98
99#include <dev/usb/usb.h>
100#include <dev/usb/usbdi.h>
101#include <dev/usb/usbdi_util.h>
102#include "usbdevs.h"
103
104#define USB_DEBUG_VAR axe_debug
105#include <dev/usb/usb_debug.h>
106#include <dev/usb/usb_process.h>
107
108#include <dev/usb/net/usb_ethernet.h>
109#include <dev/usb/net/if_axereg.h>
110
111/*
112 * AXE_178_MAX_FRAME_BURST
113 * max frame burst size for Ax88178 and Ax88772
114 * 0 2048 bytes
115 * 1 4096 bytes
116 * 2 8192 bytes
117 * 3 16384 bytes
118 * use the largest your system can handle without USB stalling.
119 *
120 * NB: 88772 parts appear to generate lots of input errors with
121 * a 2K rx buffer and 8K is only slightly faster than 4K on an
122 * EHCI port on a T42 so change at your own risk.
123 */
124#define AXE_178_MAX_FRAME_BURST 1
125
126#ifdef USB_DEBUG
127static int axe_debug = 0;
128
129SYSCTL_NODE(_hw_usb, OID_AUTO, axe, CTLFLAG_RW, 0, "USB axe");
130SYSCTL_INT(_hw_usb_axe, OID_AUTO, debug, CTLFLAG_RW, &axe_debug, 0,
131 "Debug level");
132#endif
133
134/*
135 * Various supported device vendors/products.
136 */
137static const struct usb_device_id axe_devs[] = {
138#define AXE_DEV(v,p,i) { USB_VPI(USB_VENDOR_##v, USB_PRODUCT_##v##_##p, i) }
139 AXE_DEV(ABOCOM, UF200, 0),
140 AXE_DEV(ACERCM, EP1427X2, 0),
141 AXE_DEV(APPLE, ETHERNET, AXE_FLAG_772),
142 AXE_DEV(ASIX, AX88172, 0),
143 AXE_DEV(ASIX, AX88178, AXE_FLAG_178),
144 AXE_DEV(ASIX, AX88772, AXE_FLAG_772),
145 AXE_DEV(ASIX, AX88772A, AXE_FLAG_772),
146 AXE_DEV(ATEN, UC210T, 0),
147 AXE_DEV(BELKIN, F5D5055, AXE_FLAG_178),
148 AXE_DEV(BILLIONTON, USB2AR, 0),
149 AXE_DEV(CISCOLINKSYS, USB200MV2, AXE_FLAG_772),
150 AXE_DEV(COREGA, FETHER_USB2_TX, 0),
151 AXE_DEV(DLINK, DUBE100, 0),
152 AXE_DEV(DLINK, DUBE100B1, AXE_FLAG_772),
153 AXE_DEV(GOODWAY, GWUSB2E, 0),
154 AXE_DEV(IODATA, ETGUS2, AXE_FLAG_178),
155 AXE_DEV(JVC, MP_PRX1, 0),
156 AXE_DEV(LINKSYS2, USB200M, 0),
157 AXE_DEV(LINKSYS4, USB1000, AXE_FLAG_178),
158 AXE_DEV(LOGITEC, LAN_GTJU2A, AXE_FLAG_178),
159 AXE_DEV(MELCO, LUAU2KTX, 0),
160 AXE_DEV(MELCO, LUA3U2AGT, AXE_FLAG_178),
161 AXE_DEV(NETGEAR, FA120, 0),
162 AXE_DEV(OQO, ETHER01PLUS, AXE_FLAG_772),
163 AXE_DEV(PLANEX3, GU1000T, AXE_FLAG_178),
164 AXE_DEV(SITECOM, LN029, 0),
165 AXE_DEV(SITECOMEU, LN028, AXE_FLAG_178),
166 AXE_DEV(SYSTEMTALKS, SGCX2UL, 0),
167#undef AXE_DEV
168};
169
170static device_probe_t axe_probe;
171static device_attach_t axe_attach;
172static device_detach_t axe_detach;
173
174static usb_callback_t axe_bulk_read_callback;
175static usb_callback_t axe_bulk_write_callback;
176
177static miibus_readreg_t axe_miibus_readreg;
178static miibus_writereg_t axe_miibus_writereg;
179static miibus_statchg_t axe_miibus_statchg;
180
181static uether_fn_t axe_attach_post;
182static uether_fn_t axe_init;
183static uether_fn_t axe_stop;
184static uether_fn_t axe_start;
185static uether_fn_t axe_tick;
186static uether_fn_t axe_setmulti;
187static uether_fn_t axe_setpromisc;
188
189static int axe_ifmedia_upd(struct ifnet *);
190static void axe_ifmedia_sts(struct ifnet *, struct ifmediareq *);
191static int axe_cmd(struct axe_softc *, int, int, int, void *);
192static void axe_ax88178_init(struct axe_softc *);
193static void axe_ax88772_init(struct axe_softc *);
194static int axe_get_phyno(struct axe_softc *, int);
195
196static const struct usb_config axe_config[AXE_N_TRANSFER] = {
197
198 [AXE_BULK_DT_WR] = {
199 .type = UE_BULK,
200 .endpoint = UE_ADDR_ANY,
201 .direction = UE_DIR_OUT,
202 .bufsize = AXE_BULK_BUF_SIZE,
203 .flags = {.pipe_bof = 1,.force_short_xfer = 1,},
204 .callback = axe_bulk_write_callback,
205 .timeout = 10000, /* 10 seconds */
206 },
207
208 [AXE_BULK_DT_RD] = {
209 .type = UE_BULK,
210 .endpoint = UE_ADDR_ANY,
211 .direction = UE_DIR_IN,
212 .bufsize = 16384, /* bytes */
213 .flags = {.pipe_bof = 1,.short_xfer_ok = 1,},
214 .callback = axe_bulk_read_callback,
215 .timeout = 0, /* no timeout */
216 },
217};
218
219static device_method_t axe_methods[] = {
220 /* Device interface */
221 DEVMETHOD(device_probe, axe_probe),
222 DEVMETHOD(device_attach, axe_attach),
223 DEVMETHOD(device_detach, axe_detach),
224
225 /* bus interface */
226 DEVMETHOD(bus_print_child, bus_generic_print_child),
227 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
228
229 /* MII interface */
230 DEVMETHOD(miibus_readreg, axe_miibus_readreg),
231 DEVMETHOD(miibus_writereg, axe_miibus_writereg),
232 DEVMETHOD(miibus_statchg, axe_miibus_statchg),
233
234 {0, 0}
235};
236
237static driver_t axe_driver = {
238 .name = "axe",
239 .methods = axe_methods,
240 .size = sizeof(struct axe_softc),
241};
242
243static devclass_t axe_devclass;
244
245DRIVER_MODULE(axe, uhub, axe_driver, axe_devclass, NULL, 0);
246DRIVER_MODULE(miibus, axe, miibus_driver, miibus_devclass, 0, 0);
247MODULE_DEPEND(axe, uether, 1, 1, 1);
248MODULE_DEPEND(axe, usb, 1, 1, 1);
249MODULE_DEPEND(axe, ether, 1, 1, 1);
250MODULE_DEPEND(axe, miibus, 1, 1, 1);
251MODULE_VERSION(axe, 1);
252
253static const struct usb_ether_methods axe_ue_methods = {
254 .ue_attach_post = axe_attach_post,
255 .ue_start = axe_start,
256 .ue_init = axe_init,
257 .ue_stop = axe_stop,
258 .ue_tick = axe_tick,
259 .ue_setmulti = axe_setmulti,
260 .ue_setpromisc = axe_setpromisc,
261 .ue_mii_upd = axe_ifmedia_upd,
262 .ue_mii_sts = axe_ifmedia_sts,
263};
264
265static int
266axe_cmd(struct axe_softc *sc, int cmd, int index, int val, void *buf)
267{
268 struct usb_device_request req;
269 usb_error_t err;
270
271 AXE_LOCK_ASSERT(sc, MA_OWNED);
272
273 req.bmRequestType = (AXE_CMD_IS_WRITE(cmd) ?
274 UT_WRITE_VENDOR_DEVICE :
275 UT_READ_VENDOR_DEVICE);
276 req.bRequest = AXE_CMD_CMD(cmd);
277 USETW(req.wValue, val);
278 USETW(req.wIndex, index);
279 USETW(req.wLength, AXE_CMD_LEN(cmd));
280
281 err = uether_do_request(&sc->sc_ue, &req, buf, 1000);
282
283 return (err);
284}
285
286static int
287axe_miibus_readreg(device_t dev, int phy, int reg)
288{
289 struct axe_softc *sc = device_get_softc(dev);
290 uint16_t val;
291 int locked;
292
293 if (sc->sc_phyno != phy)
294 return (0);
295
296 locked = mtx_owned(&sc->sc_mtx);
297 if (!locked)
298 AXE_LOCK(sc);
299
300 axe_cmd(sc, AXE_CMD_MII_OPMODE_SW, 0, 0, NULL);
301 axe_cmd(sc, AXE_CMD_MII_READ_REG, reg, phy, &val);
302 axe_cmd(sc, AXE_CMD_MII_OPMODE_HW, 0, 0, NULL);
303
304 val = le16toh(val);
|
305 if ((sc->sc_flags & AXE_FLAG_772) != 0 && reg == MII_BMSR) {
| 305 if (AXE_IS_772(sc) && reg == MII_BMSR) {
|
306 /*
307 * BMSR of AX88772 indicates that it supports extended
308 * capability but the extended status register is
309 * revered for embedded ethernet PHY. So clear the
310 * extended capability bit of BMSR.
311 */
312 val &= ~BMSR_EXTCAP;
313 }
314
315 if (!locked)
316 AXE_UNLOCK(sc);
317 return (val);
318}
319
320static int
321axe_miibus_writereg(device_t dev, int phy, int reg, int val)
322{
323 struct axe_softc *sc = device_get_softc(dev);
324 int locked;
325
326 val = htole32(val);
327
328 if (sc->sc_phyno != phy)
329 return (0);
330
331 locked = mtx_owned(&sc->sc_mtx);
332 if (!locked)
333 AXE_LOCK(sc);
334
335 axe_cmd(sc, AXE_CMD_MII_OPMODE_SW, 0, 0, NULL);
336 axe_cmd(sc, AXE_CMD_MII_WRITE_REG, reg, phy, &val);
337 axe_cmd(sc, AXE_CMD_MII_OPMODE_HW, 0, 0, NULL);
338
339 if (!locked)
340 AXE_UNLOCK(sc);
341 return (0);
342}
343
344static void
345axe_miibus_statchg(device_t dev)
346{
347 struct axe_softc *sc = device_get_softc(dev);
348 struct mii_data *mii = GET_MII(sc);
349 struct ifnet *ifp;
350 uint16_t val;
351 int err, locked;
352
353 locked = mtx_owned(&sc->sc_mtx);
354 if (!locked)
355 AXE_LOCK(sc);
356
357 ifp = uether_getifp(&sc->sc_ue);
358 if (mii == NULL || ifp == NULL ||
359 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
360 goto done;
361
362 sc->sc_flags &= ~AXE_FLAG_LINK;
363 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
364 (IFM_ACTIVE | IFM_AVALID)) {
365 switch (IFM_SUBTYPE(mii->mii_media_active)) {
366 case IFM_10_T:
367 case IFM_100_TX:
368 sc->sc_flags |= AXE_FLAG_LINK;
369 break;
370 case IFM_1000_T:
371 if ((sc->sc_flags & AXE_FLAG_178) == 0)
372 break;
373 sc->sc_flags |= AXE_FLAG_LINK;
374 break;
375 default:
376 break;
377 }
378 }
379
380 /* Lost link, do nothing. */
381 if ((sc->sc_flags & AXE_FLAG_LINK) == 0)
382 goto done;
383
384 val = 0;
385 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0)
386 val |= AXE_MEDIA_FULL_DUPLEX;
| 306 /*
307 * BMSR of AX88772 indicates that it supports extended
308 * capability but the extended status register is
309 * revered for embedded ethernet PHY. So clear the
310 * extended capability bit of BMSR.
311 */
312 val &= ~BMSR_EXTCAP;
313 }
314
315 if (!locked)
316 AXE_UNLOCK(sc);
317 return (val);
318}
319
320static int
321axe_miibus_writereg(device_t dev, int phy, int reg, int val)
322{
323 struct axe_softc *sc = device_get_softc(dev);
324 int locked;
325
326 val = htole32(val);
327
328 if (sc->sc_phyno != phy)
329 return (0);
330
331 locked = mtx_owned(&sc->sc_mtx);
332 if (!locked)
333 AXE_LOCK(sc);
334
335 axe_cmd(sc, AXE_CMD_MII_OPMODE_SW, 0, 0, NULL);
336 axe_cmd(sc, AXE_CMD_MII_WRITE_REG, reg, phy, &val);
337 axe_cmd(sc, AXE_CMD_MII_OPMODE_HW, 0, 0, NULL);
338
339 if (!locked)
340 AXE_UNLOCK(sc);
341 return (0);
342}
343
344static void
345axe_miibus_statchg(device_t dev)
346{
347 struct axe_softc *sc = device_get_softc(dev);
348 struct mii_data *mii = GET_MII(sc);
349 struct ifnet *ifp;
350 uint16_t val;
351 int err, locked;
352
353 locked = mtx_owned(&sc->sc_mtx);
354 if (!locked)
355 AXE_LOCK(sc);
356
357 ifp = uether_getifp(&sc->sc_ue);
358 if (mii == NULL || ifp == NULL ||
359 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
360 goto done;
361
362 sc->sc_flags &= ~AXE_FLAG_LINK;
363 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
364 (IFM_ACTIVE | IFM_AVALID)) {
365 switch (IFM_SUBTYPE(mii->mii_media_active)) {
366 case IFM_10_T:
367 case IFM_100_TX:
368 sc->sc_flags |= AXE_FLAG_LINK;
369 break;
370 case IFM_1000_T:
371 if ((sc->sc_flags & AXE_FLAG_178) == 0)
372 break;
373 sc->sc_flags |= AXE_FLAG_LINK;
374 break;
375 default:
376 break;
377 }
378 }
379
380 /* Lost link, do nothing. */
381 if ((sc->sc_flags & AXE_FLAG_LINK) == 0)
382 goto done;
383
384 val = 0;
385 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0)
386 val |= AXE_MEDIA_FULL_DUPLEX;
|
387 if (sc->sc_flags & (AXE_FLAG_178 | AXE_FLAG_772)) {
| 387 if (AXE_IS_178_FAMILY(sc)) {
|
388 val |= AXE_178_MEDIA_RX_EN | AXE_178_MEDIA_MAGIC;
389 if ((sc->sc_flags & AXE_FLAG_178) != 0)
390 val |= AXE_178_MEDIA_ENCK;
391 switch (IFM_SUBTYPE(mii->mii_media_active)) {
392 case IFM_1000_T:
393 val |= AXE_178_MEDIA_GMII | AXE_178_MEDIA_ENCK;
394 break;
395 case IFM_100_TX:
396 val |= AXE_178_MEDIA_100TX;
397 break;
398 case IFM_10_T:
399 /* doesn't need to be handled */
400 break;
401 }
402 }
403 err = axe_cmd(sc, AXE_CMD_WRITE_MEDIA, 0, val, NULL);
404 if (err)
405 device_printf(dev, "media change failed, error %d\n", err);
406done:
407 if (!locked)
408 AXE_UNLOCK(sc);
409}
410
411/*
412 * Set media options.
413 */
414static int
415axe_ifmedia_upd(struct ifnet *ifp)
416{
417 struct axe_softc *sc = ifp->if_softc;
418 struct mii_data *mii = GET_MII(sc);
419 int error;
420
421 AXE_LOCK_ASSERT(sc, MA_OWNED);
422
423 if (mii->mii_instance) {
424 struct mii_softc *miisc;
425
426 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
427 mii_phy_reset(miisc);
428 }
429 error = mii_mediachg(mii);
430 return (error);
431}
432
433/*
434 * Report current media status.
435 */
436static void
437axe_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
438{
439 struct axe_softc *sc = ifp->if_softc;
440 struct mii_data *mii = GET_MII(sc);
441
442 AXE_LOCK(sc);
443 mii_pollstat(mii);
444 AXE_UNLOCK(sc);
445 ifmr->ifm_active = mii->mii_media_active;
446 ifmr->ifm_status = mii->mii_media_status;
447}
448
449static void
450axe_setmulti(struct usb_ether *ue)
451{
452 struct axe_softc *sc = uether_getsc(ue);
453 struct ifnet *ifp = uether_getifp(ue);
454 struct ifmultiaddr *ifma;
455 uint32_t h = 0;
456 uint16_t rxmode;
457 uint8_t hashtbl[8] = { 0, 0, 0, 0, 0, 0, 0, 0 };
458
459 AXE_LOCK_ASSERT(sc, MA_OWNED);
460
461 axe_cmd(sc, AXE_CMD_RXCTL_READ, 0, 0, &rxmode);
462 rxmode = le16toh(rxmode);
463
464 if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) {
465 rxmode |= AXE_RXCMD_ALLMULTI;
466 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL);
467 return;
468 }
469 rxmode &= ~AXE_RXCMD_ALLMULTI;
470
471 if_maddr_rlock(ifp);
472 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link)
473 {
474 if (ifma->ifma_addr->sa_family != AF_LINK)
475 continue;
476 h = ether_crc32_be(LLADDR((struct sockaddr_dl *)
477 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26;
478 hashtbl[h / 8] |= 1 << (h % 8);
479 }
480 if_maddr_runlock(ifp);
481
482 axe_cmd(sc, AXE_CMD_WRITE_MCAST, 0, 0, (void *)&hashtbl);
483 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL);
484}
485
486static int
487axe_get_phyno(struct axe_softc *sc, int sel)
488{
489 int phyno;
490
491 switch (AXE_PHY_TYPE(sc->sc_phyaddrs[sel])) {
492 case PHY_TYPE_100_HOME:
493 case PHY_TYPE_GIG:
494 phyno = AXE_PHY_NO(sc->sc_phyaddrs[sel]);
495 break;
496 case PHY_TYPE_SPECIAL:
497 /* FALLTHROUGH */
498 case PHY_TYPE_RSVD:
499 /* FALLTHROUGH */
500 case PHY_TYPE_NON_SUP:
501 /* FALLTHROUGH */
502 default:
503 phyno = -1;
504 break;
505 }
506
507 return (phyno);
508}
509
510#define AXE_GPIO_WRITE(x, y) do { \
511 axe_cmd(sc, AXE_CMD_WRITE_GPIO, 0, (x), NULL); \
512 uether_pause(ue, (y)); \
513} while (0)
514
515static void
516axe_ax88178_init(struct axe_softc *sc)
517{
518 struct usb_ether *ue;
519 int gpio0, phymode;
520 uint16_t eeprom, val;
521
522 ue = &sc->sc_ue;
523 axe_cmd(sc, AXE_CMD_SROM_WR_ENABLE, 0, 0, NULL);
524 /* XXX magic */
525 axe_cmd(sc, AXE_CMD_SROM_READ, 0, 0x0017, &eeprom);
526 eeprom = le16toh(eeprom);
527 axe_cmd(sc, AXE_CMD_SROM_WR_DISABLE, 0, 0, NULL);
528
529 /* if EEPROM is invalid we have to use to GPIO0 */
530 if (eeprom == 0xffff) {
531 phymode = AXE_PHY_MODE_MARVELL;
532 gpio0 = 1;
533 } else {
534 phymode = eeprom & 0x7f;
535 gpio0 = (eeprom & 0x80) ? 0 : 1;
536 }
537
538 if (bootverbose)
539 device_printf(sc->sc_ue.ue_dev,
540 "EEPROM data : 0x%04x, phymode : 0x%02x\n", eeprom,
541 phymode);
542 /* Program GPIOs depending on PHY hardware. */
543 switch (phymode) {
544 case AXE_PHY_MODE_MARVELL:
545 if (gpio0 == 1) {
546 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO0_EN,
547 hz / 32);
548 AXE_GPIO_WRITE(AXE_GPIO0_EN | AXE_GPIO2 | AXE_GPIO2_EN,
549 hz / 32);
550 AXE_GPIO_WRITE(AXE_GPIO0_EN | AXE_GPIO2_EN, hz / 4);
551 AXE_GPIO_WRITE(AXE_GPIO0_EN | AXE_GPIO2 | AXE_GPIO2_EN,
552 hz / 32);
553 } else
554 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO1 |
555 AXE_GPIO1_EN, hz / 32);
556 break;
557 case AXE_PHY_MODE_CICADA:
558 case AXE_PHY_MODE_CICADA_V2:
559 case AXE_PHY_MODE_CICADA_V2_ASIX:
560 if (gpio0 == 1)
561 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO0 |
562 AXE_GPIO0_EN, hz / 32);
563 else
564 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO1 |
565 AXE_GPIO1_EN, hz / 32);
566 break;
567 case AXE_PHY_MODE_AGERE:
568 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO1 |
569 AXE_GPIO1_EN, hz / 32);
570 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | AXE_GPIO2 |
571 AXE_GPIO2_EN, hz / 32);
572 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | AXE_GPIO2_EN, hz / 4);
573 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | AXE_GPIO2 |
574 AXE_GPIO2_EN, hz / 32);
575 break;
576 case AXE_PHY_MODE_REALTEK_8211CL:
577 case AXE_PHY_MODE_REALTEK_8211BN:
578 case AXE_PHY_MODE_REALTEK_8251CL:
579 val = gpio0 == 1 ? AXE_GPIO0 | AXE_GPIO0_EN :
580 AXE_GPIO1 | AXE_GPIO1_EN;
581 AXE_GPIO_WRITE(val, hz / 32);
582 AXE_GPIO_WRITE(val | AXE_GPIO2 | AXE_GPIO2_EN, hz / 32);
583 AXE_GPIO_WRITE(val | AXE_GPIO2_EN, hz / 4);
584 AXE_GPIO_WRITE(val | AXE_GPIO2 | AXE_GPIO2_EN, hz / 32);
585 if (phymode == AXE_PHY_MODE_REALTEK_8211CL) {
586 axe_miibus_writereg(ue->ue_dev, sc->sc_phyno,
587 0x1F, 0x0005);
588 axe_miibus_writereg(ue->ue_dev, sc->sc_phyno,
589 0x0C, 0x0000);
590 val = axe_miibus_readreg(ue->ue_dev, sc->sc_phyno,
591 0x0001);
592 axe_miibus_writereg(ue->ue_dev, sc->sc_phyno,
593 0x01, val | 0x0080);
594 axe_miibus_writereg(ue->ue_dev, sc->sc_phyno,
595 0x1F, 0x0000);
596 }
597 break;
598 default:
599 /* Unknown PHY model or no need to program GPIOs. */
600 break;
601 }
602
603 /* soft reset */
604 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_CLEAR, NULL);
605 uether_pause(ue, hz / 4);
606
607 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0,
608 AXE_SW_RESET_PRL | AXE_178_RESET_MAGIC, NULL);
609 uether_pause(ue, hz / 4);
610 /* Enable MII/GMII/RGMII interface to work with external PHY. */
611 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, 0, NULL);
612 uether_pause(ue, hz / 4);
613
614 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL);
615}
616#undef AXE_GPIO_WRITE
617
618static void
619axe_ax88772_init(struct axe_softc *sc)
620{
621 axe_cmd(sc, AXE_CMD_WRITE_GPIO, 0, 0x00b0, NULL);
622 uether_pause(&sc->sc_ue, hz / 16);
623
624 if (sc->sc_phyno == AXE_772_PHY_NO_EPHY) {
625 /* ask for the embedded PHY */
626 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, 0x01, NULL);
627 uether_pause(&sc->sc_ue, hz / 64);
628
629 /* power down and reset state, pin reset state */
630 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0,
631 AXE_SW_RESET_CLEAR, NULL);
632 uether_pause(&sc->sc_ue, hz / 16);
633
634 /* power down/reset state, pin operating state */
635 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0,
636 AXE_SW_RESET_IPPD | AXE_SW_RESET_PRL, NULL);
637 uether_pause(&sc->sc_ue, hz / 4);
638
639 /* power up, reset */
640 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_PRL, NULL);
641
642 /* power up, operating */
643 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0,
644 AXE_SW_RESET_IPRL | AXE_SW_RESET_PRL, NULL);
645 } else {
646 /* ask for external PHY */
647 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, 0x00, NULL);
648 uether_pause(&sc->sc_ue, hz / 64);
649
650 /* power down internal PHY */
651 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0,
652 AXE_SW_RESET_IPPD | AXE_SW_RESET_PRL, NULL);
653 }
654
655 uether_pause(&sc->sc_ue, hz / 4);
656 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL);
657}
658
659static void
660axe_reset(struct axe_softc *sc)
661{
662 struct usb_config_descriptor *cd;
663 usb_error_t err;
664
665 cd = usbd_get_config_descriptor(sc->sc_ue.ue_udev);
666
667 err = usbd_req_set_config(sc->sc_ue.ue_udev, &sc->sc_mtx,
668 cd->bConfigurationValue);
669 if (err)
670 DPRINTF("reset failed (ignored)\n");
671
672 /* Wait a little while for the chip to get its brains in order. */
673 uether_pause(&sc->sc_ue, hz / 100);
674
675 /* Reinitialize controller to achieve full reset. */
676 if (sc->sc_flags & AXE_FLAG_178)
677 axe_ax88178_init(sc);
678 else if (sc->sc_flags & AXE_FLAG_772)
679 axe_ax88772_init(sc);
680}
681
682static void
683axe_attach_post(struct usb_ether *ue)
684{
685 struct axe_softc *sc = uether_getsc(ue);
686
687 /*
688 * Load PHY indexes first. Needed by axe_xxx_init().
689 */
690 axe_cmd(sc, AXE_CMD_READ_PHYID, 0, 0, sc->sc_phyaddrs);
691 if (bootverbose)
692 device_printf(sc->sc_ue.ue_dev, "PHYADDR 0x%02x:0x%02x\n",
693 sc->sc_phyaddrs[0], sc->sc_phyaddrs[1]);
694 sc->sc_phyno = axe_get_phyno(sc, AXE_PHY_SEL_PRI);
695 if (sc->sc_phyno == -1)
696 sc->sc_phyno = axe_get_phyno(sc, AXE_PHY_SEL_SEC);
697 if (sc->sc_phyno == -1) {
698 device_printf(sc->sc_ue.ue_dev,
699 "no valid PHY address found, assuming PHY address 0\n");
700 sc->sc_phyno = 0;
701 }
702
| 388 val |= AXE_178_MEDIA_RX_EN | AXE_178_MEDIA_MAGIC;
389 if ((sc->sc_flags & AXE_FLAG_178) != 0)
390 val |= AXE_178_MEDIA_ENCK;
391 switch (IFM_SUBTYPE(mii->mii_media_active)) {
392 case IFM_1000_T:
393 val |= AXE_178_MEDIA_GMII | AXE_178_MEDIA_ENCK;
394 break;
395 case IFM_100_TX:
396 val |= AXE_178_MEDIA_100TX;
397 break;
398 case IFM_10_T:
399 /* doesn't need to be handled */
400 break;
401 }
402 }
403 err = axe_cmd(sc, AXE_CMD_WRITE_MEDIA, 0, val, NULL);
404 if (err)
405 device_printf(dev, "media change failed, error %d\n", err);
406done:
407 if (!locked)
408 AXE_UNLOCK(sc);
409}
410
411/*
412 * Set media options.
413 */
414static int
415axe_ifmedia_upd(struct ifnet *ifp)
416{
417 struct axe_softc *sc = ifp->if_softc;
418 struct mii_data *mii = GET_MII(sc);
419 int error;
420
421 AXE_LOCK_ASSERT(sc, MA_OWNED);
422
423 if (mii->mii_instance) {
424 struct mii_softc *miisc;
425
426 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
427 mii_phy_reset(miisc);
428 }
429 error = mii_mediachg(mii);
430 return (error);
431}
432
433/*
434 * Report current media status.
435 */
436static void
437axe_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
438{
439 struct axe_softc *sc = ifp->if_softc;
440 struct mii_data *mii = GET_MII(sc);
441
442 AXE_LOCK(sc);
443 mii_pollstat(mii);
444 AXE_UNLOCK(sc);
445 ifmr->ifm_active = mii->mii_media_active;
446 ifmr->ifm_status = mii->mii_media_status;
447}
448
449static void
450axe_setmulti(struct usb_ether *ue)
451{
452 struct axe_softc *sc = uether_getsc(ue);
453 struct ifnet *ifp = uether_getifp(ue);
454 struct ifmultiaddr *ifma;
455 uint32_t h = 0;
456 uint16_t rxmode;
457 uint8_t hashtbl[8] = { 0, 0, 0, 0, 0, 0, 0, 0 };
458
459 AXE_LOCK_ASSERT(sc, MA_OWNED);
460
461 axe_cmd(sc, AXE_CMD_RXCTL_READ, 0, 0, &rxmode);
462 rxmode = le16toh(rxmode);
463
464 if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) {
465 rxmode |= AXE_RXCMD_ALLMULTI;
466 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL);
467 return;
468 }
469 rxmode &= ~AXE_RXCMD_ALLMULTI;
470
471 if_maddr_rlock(ifp);
472 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link)
473 {
474 if (ifma->ifma_addr->sa_family != AF_LINK)
475 continue;
476 h = ether_crc32_be(LLADDR((struct sockaddr_dl *)
477 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26;
478 hashtbl[h / 8] |= 1 << (h % 8);
479 }
480 if_maddr_runlock(ifp);
481
482 axe_cmd(sc, AXE_CMD_WRITE_MCAST, 0, 0, (void *)&hashtbl);
483 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL);
484}
485
486static int
487axe_get_phyno(struct axe_softc *sc, int sel)
488{
489 int phyno;
490
491 switch (AXE_PHY_TYPE(sc->sc_phyaddrs[sel])) {
492 case PHY_TYPE_100_HOME:
493 case PHY_TYPE_GIG:
494 phyno = AXE_PHY_NO(sc->sc_phyaddrs[sel]);
495 break;
496 case PHY_TYPE_SPECIAL:
497 /* FALLTHROUGH */
498 case PHY_TYPE_RSVD:
499 /* FALLTHROUGH */
500 case PHY_TYPE_NON_SUP:
501 /* FALLTHROUGH */
502 default:
503 phyno = -1;
504 break;
505 }
506
507 return (phyno);
508}
509
510#define AXE_GPIO_WRITE(x, y) do { \
511 axe_cmd(sc, AXE_CMD_WRITE_GPIO, 0, (x), NULL); \
512 uether_pause(ue, (y)); \
513} while (0)
514
515static void
516axe_ax88178_init(struct axe_softc *sc)
517{
518 struct usb_ether *ue;
519 int gpio0, phymode;
520 uint16_t eeprom, val;
521
522 ue = &sc->sc_ue;
523 axe_cmd(sc, AXE_CMD_SROM_WR_ENABLE, 0, 0, NULL);
524 /* XXX magic */
525 axe_cmd(sc, AXE_CMD_SROM_READ, 0, 0x0017, &eeprom);
526 eeprom = le16toh(eeprom);
527 axe_cmd(sc, AXE_CMD_SROM_WR_DISABLE, 0, 0, NULL);
528
529 /* if EEPROM is invalid we have to use to GPIO0 */
530 if (eeprom == 0xffff) {
531 phymode = AXE_PHY_MODE_MARVELL;
532 gpio0 = 1;
533 } else {
534 phymode = eeprom & 0x7f;
535 gpio0 = (eeprom & 0x80) ? 0 : 1;
536 }
537
538 if (bootverbose)
539 device_printf(sc->sc_ue.ue_dev,
540 "EEPROM data : 0x%04x, phymode : 0x%02x\n", eeprom,
541 phymode);
542 /* Program GPIOs depending on PHY hardware. */
543 switch (phymode) {
544 case AXE_PHY_MODE_MARVELL:
545 if (gpio0 == 1) {
546 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO0_EN,
547 hz / 32);
548 AXE_GPIO_WRITE(AXE_GPIO0_EN | AXE_GPIO2 | AXE_GPIO2_EN,
549 hz / 32);
550 AXE_GPIO_WRITE(AXE_GPIO0_EN | AXE_GPIO2_EN, hz / 4);
551 AXE_GPIO_WRITE(AXE_GPIO0_EN | AXE_GPIO2 | AXE_GPIO2_EN,
552 hz / 32);
553 } else
554 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO1 |
555 AXE_GPIO1_EN, hz / 32);
556 break;
557 case AXE_PHY_MODE_CICADA:
558 case AXE_PHY_MODE_CICADA_V2:
559 case AXE_PHY_MODE_CICADA_V2_ASIX:
560 if (gpio0 == 1)
561 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO0 |
562 AXE_GPIO0_EN, hz / 32);
563 else
564 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO1 |
565 AXE_GPIO1_EN, hz / 32);
566 break;
567 case AXE_PHY_MODE_AGERE:
568 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO1 |
569 AXE_GPIO1_EN, hz / 32);
570 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | AXE_GPIO2 |
571 AXE_GPIO2_EN, hz / 32);
572 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | AXE_GPIO2_EN, hz / 4);
573 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | AXE_GPIO2 |
574 AXE_GPIO2_EN, hz / 32);
575 break;
576 case AXE_PHY_MODE_REALTEK_8211CL:
577 case AXE_PHY_MODE_REALTEK_8211BN:
578 case AXE_PHY_MODE_REALTEK_8251CL:
579 val = gpio0 == 1 ? AXE_GPIO0 | AXE_GPIO0_EN :
580 AXE_GPIO1 | AXE_GPIO1_EN;
581 AXE_GPIO_WRITE(val, hz / 32);
582 AXE_GPIO_WRITE(val | AXE_GPIO2 | AXE_GPIO2_EN, hz / 32);
583 AXE_GPIO_WRITE(val | AXE_GPIO2_EN, hz / 4);
584 AXE_GPIO_WRITE(val | AXE_GPIO2 | AXE_GPIO2_EN, hz / 32);
585 if (phymode == AXE_PHY_MODE_REALTEK_8211CL) {
586 axe_miibus_writereg(ue->ue_dev, sc->sc_phyno,
587 0x1F, 0x0005);
588 axe_miibus_writereg(ue->ue_dev, sc->sc_phyno,
589 0x0C, 0x0000);
590 val = axe_miibus_readreg(ue->ue_dev, sc->sc_phyno,
591 0x0001);
592 axe_miibus_writereg(ue->ue_dev, sc->sc_phyno,
593 0x01, val | 0x0080);
594 axe_miibus_writereg(ue->ue_dev, sc->sc_phyno,
595 0x1F, 0x0000);
596 }
597 break;
598 default:
599 /* Unknown PHY model or no need to program GPIOs. */
600 break;
601 }
602
603 /* soft reset */
604 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_CLEAR, NULL);
605 uether_pause(ue, hz / 4);
606
607 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0,
608 AXE_SW_RESET_PRL | AXE_178_RESET_MAGIC, NULL);
609 uether_pause(ue, hz / 4);
610 /* Enable MII/GMII/RGMII interface to work with external PHY. */
611 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, 0, NULL);
612 uether_pause(ue, hz / 4);
613
614 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL);
615}
616#undef AXE_GPIO_WRITE
617
618static void
619axe_ax88772_init(struct axe_softc *sc)
620{
621 axe_cmd(sc, AXE_CMD_WRITE_GPIO, 0, 0x00b0, NULL);
622 uether_pause(&sc->sc_ue, hz / 16);
623
624 if (sc->sc_phyno == AXE_772_PHY_NO_EPHY) {
625 /* ask for the embedded PHY */
626 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, 0x01, NULL);
627 uether_pause(&sc->sc_ue, hz / 64);
628
629 /* power down and reset state, pin reset state */
630 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0,
631 AXE_SW_RESET_CLEAR, NULL);
632 uether_pause(&sc->sc_ue, hz / 16);
633
634 /* power down/reset state, pin operating state */
635 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0,
636 AXE_SW_RESET_IPPD | AXE_SW_RESET_PRL, NULL);
637 uether_pause(&sc->sc_ue, hz / 4);
638
639 /* power up, reset */
640 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_PRL, NULL);
641
642 /* power up, operating */
643 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0,
644 AXE_SW_RESET_IPRL | AXE_SW_RESET_PRL, NULL);
645 } else {
646 /* ask for external PHY */
647 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, 0x00, NULL);
648 uether_pause(&sc->sc_ue, hz / 64);
649
650 /* power down internal PHY */
651 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0,
652 AXE_SW_RESET_IPPD | AXE_SW_RESET_PRL, NULL);
653 }
654
655 uether_pause(&sc->sc_ue, hz / 4);
656 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL);
657}
658
659static void
660axe_reset(struct axe_softc *sc)
661{
662 struct usb_config_descriptor *cd;
663 usb_error_t err;
664
665 cd = usbd_get_config_descriptor(sc->sc_ue.ue_udev);
666
667 err = usbd_req_set_config(sc->sc_ue.ue_udev, &sc->sc_mtx,
668 cd->bConfigurationValue);
669 if (err)
670 DPRINTF("reset failed (ignored)\n");
671
672 /* Wait a little while for the chip to get its brains in order. */
673 uether_pause(&sc->sc_ue, hz / 100);
674
675 /* Reinitialize controller to achieve full reset. */
676 if (sc->sc_flags & AXE_FLAG_178)
677 axe_ax88178_init(sc);
678 else if (sc->sc_flags & AXE_FLAG_772)
679 axe_ax88772_init(sc);
680}
681
682static void
683axe_attach_post(struct usb_ether *ue)
684{
685 struct axe_softc *sc = uether_getsc(ue);
686
687 /*
688 * Load PHY indexes first. Needed by axe_xxx_init().
689 */
690 axe_cmd(sc, AXE_CMD_READ_PHYID, 0, 0, sc->sc_phyaddrs);
691 if (bootverbose)
692 device_printf(sc->sc_ue.ue_dev, "PHYADDR 0x%02x:0x%02x\n",
693 sc->sc_phyaddrs[0], sc->sc_phyaddrs[1]);
694 sc->sc_phyno = axe_get_phyno(sc, AXE_PHY_SEL_PRI);
695 if (sc->sc_phyno == -1)
696 sc->sc_phyno = axe_get_phyno(sc, AXE_PHY_SEL_SEC);
697 if (sc->sc_phyno == -1) {
698 device_printf(sc->sc_ue.ue_dev,
699 "no valid PHY address found, assuming PHY address 0\n");
700 sc->sc_phyno = 0;
701 }
702
|
703 if (sc->sc_flags & AXE_FLAG_178)
| 703 if (sc->sc_flags & AXE_FLAG_178) {
|
704 axe_ax88178_init(sc);
| 704 axe_ax88178_init(sc);
|
705 else if (sc->sc_flags & AXE_FLAG_772)
| 705 sc->sc_tx_bufsz = 16 * 1024;
706 } else if (sc->sc_flags & AXE_FLAG_772) {
|
706 axe_ax88772_init(sc);
| 707 axe_ax88772_init(sc);
|
| 708 sc->sc_tx_bufsz = 8 * 1024;
709 }
|
707
708 /*
709 * Get station address.
710 */
| 710
711 /*
712 * Get station address.
713 */
|
711 if (sc->sc_flags & (AXE_FLAG_178 | AXE_FLAG_772))
| 714 if (AXE_IS_178_FAMILY(sc))
|
712 axe_cmd(sc, AXE_178_CMD_READ_NODEID, 0, 0, ue->ue_eaddr);
713 else
714 axe_cmd(sc, AXE_172_CMD_READ_NODEID, 0, 0, ue->ue_eaddr);
715
716 /*
717 * Fetch IPG values.
718 */
719 axe_cmd(sc, AXE_CMD_READ_IPG012, 0, 0, sc->sc_ipgs);
720}
721
722/*
723 * Probe for a AX88172 chip.
724 */
725static int
726axe_probe(device_t dev)
727{
728 struct usb_attach_arg *uaa = device_get_ivars(dev);
729
730 if (uaa->usb_mode != USB_MODE_HOST)
731 return (ENXIO);
732 if (uaa->info.bConfigIndex != AXE_CONFIG_IDX)
733 return (ENXIO);
734 if (uaa->info.bIfaceIndex != AXE_IFACE_IDX)
735 return (ENXIO);
736
737 return (usbd_lookup_id_by_uaa(axe_devs, sizeof(axe_devs), uaa));
738}
739
740/*
741 * Attach the interface. Allocate softc structures, do ifmedia
742 * setup and ethernet/BPF attach.
743 */
744static int
745axe_attach(device_t dev)
746{
747 struct usb_attach_arg *uaa = device_get_ivars(dev);
748 struct axe_softc *sc = device_get_softc(dev);
749 struct usb_ether *ue = &sc->sc_ue;
750 uint8_t iface_index;
751 int error;
752
753 sc->sc_flags = USB_GET_DRIVER_INFO(uaa);
754
755 device_set_usb_desc(dev);
756
757 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), NULL, MTX_DEF);
758
759 iface_index = AXE_IFACE_IDX;
760 error = usbd_transfer_setup(uaa->device, &iface_index, sc->sc_xfer,
761 axe_config, AXE_N_TRANSFER, sc, &sc->sc_mtx);
762 if (error) {
763 device_printf(dev, "allocating USB transfers failed\n");
764 goto detach;
765 }
766
767 ue->ue_sc = sc;
768 ue->ue_dev = dev;
769 ue->ue_udev = uaa->device;
770 ue->ue_mtx = &sc->sc_mtx;
771 ue->ue_methods = &axe_ue_methods;
772
773 error = uether_ifattach(ue);
774 if (error) {
775 device_printf(dev, "could not attach interface\n");
776 goto detach;
777 }
778 return (0); /* success */
779
780detach:
781 axe_detach(dev);
782 return (ENXIO); /* failure */
783}
784
785static int
786axe_detach(device_t dev)
787{
788 struct axe_softc *sc = device_get_softc(dev);
789 struct usb_ether *ue = &sc->sc_ue;
790
791 usbd_transfer_unsetup(sc->sc_xfer, AXE_N_TRANSFER);
792 uether_ifdetach(ue);
793 mtx_destroy(&sc->sc_mtx);
794
795 return (0);
796}
797
798#if (AXE_BULK_BUF_SIZE >= 0x10000)
799#error "Please update axe_bulk_read_callback()!"
800#endif
801
802static void
803axe_bulk_read_callback(struct usb_xfer *xfer, usb_error_t error)
804{
805 struct axe_softc *sc = usbd_xfer_softc(xfer);
806 struct usb_ether *ue = &sc->sc_ue;
807 struct ifnet *ifp = uether_getifp(ue);
808 struct axe_sframe_hdr hdr;
809 struct usb_page_cache *pc;
810 int err, pos, len;
811 int actlen;
812
813 usbd_xfer_status(xfer, &actlen, NULL, NULL, NULL);
814
815 switch (USB_GET_STATE(xfer)) {
816 case USB_ST_TRANSFERRED:
817 pos = 0;
818 len = 0;
819 err = 0;
820
821 pc = usbd_xfer_get_frame(xfer, 0);
| 715 axe_cmd(sc, AXE_178_CMD_READ_NODEID, 0, 0, ue->ue_eaddr);
716 else
717 axe_cmd(sc, AXE_172_CMD_READ_NODEID, 0, 0, ue->ue_eaddr);
718
719 /*
720 * Fetch IPG values.
721 */
722 axe_cmd(sc, AXE_CMD_READ_IPG012, 0, 0, sc->sc_ipgs);
723}
724
725/*
726 * Probe for a AX88172 chip.
727 */
728static int
729axe_probe(device_t dev)
730{
731 struct usb_attach_arg *uaa = device_get_ivars(dev);
732
733 if (uaa->usb_mode != USB_MODE_HOST)
734 return (ENXIO);
735 if (uaa->info.bConfigIndex != AXE_CONFIG_IDX)
736 return (ENXIO);
737 if (uaa->info.bIfaceIndex != AXE_IFACE_IDX)
738 return (ENXIO);
739
740 return (usbd_lookup_id_by_uaa(axe_devs, sizeof(axe_devs), uaa));
741}
742
743/*
744 * Attach the interface. Allocate softc structures, do ifmedia
745 * setup and ethernet/BPF attach.
746 */
747static int
748axe_attach(device_t dev)
749{
750 struct usb_attach_arg *uaa = device_get_ivars(dev);
751 struct axe_softc *sc = device_get_softc(dev);
752 struct usb_ether *ue = &sc->sc_ue;
753 uint8_t iface_index;
754 int error;
755
756 sc->sc_flags = USB_GET_DRIVER_INFO(uaa);
757
758 device_set_usb_desc(dev);
759
760 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), NULL, MTX_DEF);
761
762 iface_index = AXE_IFACE_IDX;
763 error = usbd_transfer_setup(uaa->device, &iface_index, sc->sc_xfer,
764 axe_config, AXE_N_TRANSFER, sc, &sc->sc_mtx);
765 if (error) {
766 device_printf(dev, "allocating USB transfers failed\n");
767 goto detach;
768 }
769
770 ue->ue_sc = sc;
771 ue->ue_dev = dev;
772 ue->ue_udev = uaa->device;
773 ue->ue_mtx = &sc->sc_mtx;
774 ue->ue_methods = &axe_ue_methods;
775
776 error = uether_ifattach(ue);
777 if (error) {
778 device_printf(dev, "could not attach interface\n");
779 goto detach;
780 }
781 return (0); /* success */
782
783detach:
784 axe_detach(dev);
785 return (ENXIO); /* failure */
786}
787
788static int
789axe_detach(device_t dev)
790{
791 struct axe_softc *sc = device_get_softc(dev);
792 struct usb_ether *ue = &sc->sc_ue;
793
794 usbd_transfer_unsetup(sc->sc_xfer, AXE_N_TRANSFER);
795 uether_ifdetach(ue);
796 mtx_destroy(&sc->sc_mtx);
797
798 return (0);
799}
800
801#if (AXE_BULK_BUF_SIZE >= 0x10000)
802#error "Please update axe_bulk_read_callback()!"
803#endif
804
805static void
806axe_bulk_read_callback(struct usb_xfer *xfer, usb_error_t error)
807{
808 struct axe_softc *sc = usbd_xfer_softc(xfer);
809 struct usb_ether *ue = &sc->sc_ue;
810 struct ifnet *ifp = uether_getifp(ue);
811 struct axe_sframe_hdr hdr;
812 struct usb_page_cache *pc;
813 int err, pos, len;
814 int actlen;
815
816 usbd_xfer_status(xfer, &actlen, NULL, NULL, NULL);
817
818 switch (USB_GET_STATE(xfer)) {
819 case USB_ST_TRANSFERRED:
820 pos = 0;
821 len = 0;
822 err = 0;
823
824 pc = usbd_xfer_get_frame(xfer, 0);
|
822 if (sc->sc_flags & (AXE_FLAG_772 | AXE_FLAG_178)) {
| 825 if (AXE_IS_178_FAMILY(sc)) {
|
823 while (pos < actlen) {
824 if ((pos + sizeof(hdr)) > actlen) {
825 /* too little data */
826 err = EINVAL;
827 break;
828 }
829 usbd_copy_out(pc, pos, &hdr, sizeof(hdr));
830
831 if ((hdr.len ^ hdr.ilen) != 0xFFFF) {
832 /* we lost sync */
833 err = EINVAL;
834 break;
835 }
836 pos += sizeof(hdr);
837
838 len = le16toh(hdr.len);
839 if ((pos + len) > actlen) {
840 /* invalid length */
841 err = EINVAL;
842 break;
843 }
844 uether_rxbuf(ue, pc, pos, len);
845
846 pos += len + (len % 2);
847 }
848 } else
849 uether_rxbuf(ue, pc, 0, actlen);
850
851 if (err != 0)
852 ifp->if_ierrors++;
853
854 /* FALLTHROUGH */
855 case USB_ST_SETUP:
856tr_setup:
857 usbd_xfer_set_frame_len(xfer, 0, usbd_xfer_max_len(xfer));
858 usbd_transfer_submit(xfer);
859 uether_rxflush(ue);
860 return;
861
862 default: /* Error */
863 DPRINTF("bulk read error, %s\n", usbd_errstr(error));
864
865 if (error != USB_ERR_CANCELLED) {
866 /* try to clear stall first */
867 usbd_xfer_set_stall(xfer);
868 goto tr_setup;
869 }
870 return;
871
872 }
873}
874
875#if ((AXE_BULK_BUF_SIZE >= 0x10000) || (AXE_BULK_BUF_SIZE < (MCLBYTES+4)))
876#error "Please update axe_bulk_write_callback()!"
877#endif
878
879static void
880axe_bulk_write_callback(struct usb_xfer *xfer, usb_error_t error)
881{
882 struct axe_softc *sc = usbd_xfer_softc(xfer);
883 struct axe_sframe_hdr hdr;
884 struct ifnet *ifp = uether_getifp(&sc->sc_ue);
885 struct usb_page_cache *pc;
886 struct mbuf *m;
887 int pos;
888
889 switch (USB_GET_STATE(xfer)) {
890 case USB_ST_TRANSFERRED:
891 DPRINTFN(11, "transfer complete\n");
892 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
893 /* FALLTHROUGH */
894 case USB_ST_SETUP:
895tr_setup:
896 if ((sc->sc_flags & AXE_FLAG_LINK) == 0 ||
897 (ifp->if_drv_flags & IFF_DRV_OACTIVE) != 0) {
898 /*
899 * Don't send anything if there is no link or
900 * controller is busy.
901 */
902 return;
903 }
904 pos = 0;
905 pc = usbd_xfer_get_frame(xfer, 0);
906
907 while (1) {
908
909 IFQ_DRV_DEQUEUE(&ifp->if_snd, m);
910
911 if (m == NULL) {
912 if (pos > 0)
913 break; /* send out data */
914 return;
915 }
916 if (m->m_pkthdr.len > MCLBYTES) {
917 m->m_pkthdr.len = MCLBYTES;
918 }
| 826 while (pos < actlen) {
827 if ((pos + sizeof(hdr)) > actlen) {
828 /* too little data */
829 err = EINVAL;
830 break;
831 }
832 usbd_copy_out(pc, pos, &hdr, sizeof(hdr));
833
834 if ((hdr.len ^ hdr.ilen) != 0xFFFF) {
835 /* we lost sync */
836 err = EINVAL;
837 break;
838 }
839 pos += sizeof(hdr);
840
841 len = le16toh(hdr.len);
842 if ((pos + len) > actlen) {
843 /* invalid length */
844 err = EINVAL;
845 break;
846 }
847 uether_rxbuf(ue, pc, pos, len);
848
849 pos += len + (len % 2);
850 }
851 } else
852 uether_rxbuf(ue, pc, 0, actlen);
853
854 if (err != 0)
855 ifp->if_ierrors++;
856
857 /* FALLTHROUGH */
858 case USB_ST_SETUP:
859tr_setup:
860 usbd_xfer_set_frame_len(xfer, 0, usbd_xfer_max_len(xfer));
861 usbd_transfer_submit(xfer);
862 uether_rxflush(ue);
863 return;
864
865 default: /* Error */
866 DPRINTF("bulk read error, %s\n", usbd_errstr(error));
867
868 if (error != USB_ERR_CANCELLED) {
869 /* try to clear stall first */
870 usbd_xfer_set_stall(xfer);
871 goto tr_setup;
872 }
873 return;
874
875 }
876}
877
878#if ((AXE_BULK_BUF_SIZE >= 0x10000) || (AXE_BULK_BUF_SIZE < (MCLBYTES+4)))
879#error "Please update axe_bulk_write_callback()!"
880#endif
881
882static void
883axe_bulk_write_callback(struct usb_xfer *xfer, usb_error_t error)
884{
885 struct axe_softc *sc = usbd_xfer_softc(xfer);
886 struct axe_sframe_hdr hdr;
887 struct ifnet *ifp = uether_getifp(&sc->sc_ue);
888 struct usb_page_cache *pc;
889 struct mbuf *m;
890 int pos;
891
892 switch (USB_GET_STATE(xfer)) {
893 case USB_ST_TRANSFERRED:
894 DPRINTFN(11, "transfer complete\n");
895 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
896 /* FALLTHROUGH */
897 case USB_ST_SETUP:
898tr_setup:
899 if ((sc->sc_flags & AXE_FLAG_LINK) == 0 ||
900 (ifp->if_drv_flags & IFF_DRV_OACTIVE) != 0) {
901 /*
902 * Don't send anything if there is no link or
903 * controller is busy.
904 */
905 return;
906 }
907 pos = 0;
908 pc = usbd_xfer_get_frame(xfer, 0);
909
910 while (1) {
911
912 IFQ_DRV_DEQUEUE(&ifp->if_snd, m);
913
914 if (m == NULL) {
915 if (pos > 0)
916 break; /* send out data */
917 return;
918 }
919 if (m->m_pkthdr.len > MCLBYTES) {
920 m->m_pkthdr.len = MCLBYTES;
921 }
|
919 if (sc->sc_flags & (AXE_FLAG_772 | AXE_FLAG_178)) {
| 922 if (AXE_IS_178_FAMILY(sc)) {
|
920
921 hdr.len = htole16(m->m_pkthdr.len);
922 hdr.ilen = ~hdr.len;
923
924 usbd_copy_in(pc, pos, &hdr, sizeof(hdr));
925
926 pos += sizeof(hdr);
927
928 /*
929 * NOTE: Some drivers force a short packet
930 * by appending a dummy header with zero
931 * length at then end of the USB transfer.
932 * This driver uses the
933 * USB_FORCE_SHORT_XFER flag instead.
934 */
935 }
936 usbd_m_copy_in(pc, pos, m, 0, m->m_pkthdr.len);
937 pos += m->m_pkthdr.len;
938
939 /*
940 * XXX
941 * Update TX packet counter here. This is not
942 * correct way but it seems that there is no way
943 * to know how many packets are sent at the end
944 * of transfer because controller combines
945 * multiple writes into single one if there is
946 * room in TX buffer of controller.
947 */
948 ifp->if_opackets++;
949
950 /*
951 * if there's a BPF listener, bounce a copy
952 * of this frame to him:
953 */
954 BPF_MTAP(ifp, m);
955
956 m_freem(m);
957
| 923
924 hdr.len = htole16(m->m_pkthdr.len);
925 hdr.ilen = ~hdr.len;
926
927 usbd_copy_in(pc, pos, &hdr, sizeof(hdr));
928
929 pos += sizeof(hdr);
930
931 /*
932 * NOTE: Some drivers force a short packet
933 * by appending a dummy header with zero
934 * length at then end of the USB transfer.
935 * This driver uses the
936 * USB_FORCE_SHORT_XFER flag instead.
937 */
938 }
939 usbd_m_copy_in(pc, pos, m, 0, m->m_pkthdr.len);
940 pos += m->m_pkthdr.len;
941
942 /*
943 * XXX
944 * Update TX packet counter here. This is not
945 * correct way but it seems that there is no way
946 * to know how many packets are sent at the end
947 * of transfer because controller combines
948 * multiple writes into single one if there is
949 * room in TX buffer of controller.
950 */
951 ifp->if_opackets++;
952
953 /*
954 * if there's a BPF listener, bounce a copy
955 * of this frame to him:
956 */
957 BPF_MTAP(ifp, m);
958
959 m_freem(m);
960
|
958 if (sc->sc_flags & (AXE_FLAG_772 | AXE_FLAG_178)) {
| 961 if (AXE_IS_178_FAMILY(sc)) {
|
959 if (pos > (AXE_BULK_BUF_SIZE - MCLBYTES - sizeof(hdr))) {
960 /* send out frame(s) */
961 break;
962 }
963 } else {
964 /* send out frame */
965 break;
966 }
967 }
968
969 usbd_xfer_set_frame_len(xfer, 0, pos);
970 usbd_transfer_submit(xfer);
971 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
972 return;
973
974 default: /* Error */
975 DPRINTFN(11, "transfer error, %s\n",
976 usbd_errstr(error));
977
978 ifp->if_oerrors++;
979 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
980
981 if (error != USB_ERR_CANCELLED) {
982 /* try to clear stall first */
983 usbd_xfer_set_stall(xfer);
984 goto tr_setup;
985 }
986 return;
987
988 }
989}
990
991static void
992axe_tick(struct usb_ether *ue)
993{
994 struct axe_softc *sc = uether_getsc(ue);
995 struct mii_data *mii = GET_MII(sc);
996
997 AXE_LOCK_ASSERT(sc, MA_OWNED);
998
999 mii_tick(mii);
1000 if ((sc->sc_flags & AXE_FLAG_LINK) == 0) {
1001 axe_miibus_statchg(ue->ue_dev);
1002 if ((sc->sc_flags & AXE_FLAG_LINK) != 0)
1003 axe_start(ue);
1004 }
1005}
1006
1007static void
1008axe_start(struct usb_ether *ue)
1009{
1010 struct axe_softc *sc = uether_getsc(ue);
1011
1012 /*
1013 * start the USB transfers, if not already started:
1014 */
1015 usbd_transfer_start(sc->sc_xfer[AXE_BULK_DT_RD]);
1016 usbd_transfer_start(sc->sc_xfer[AXE_BULK_DT_WR]);
1017}
1018
1019static void
1020axe_init(struct usb_ether *ue)
1021{
1022 struct axe_softc *sc = uether_getsc(ue);
1023 struct ifnet *ifp = uether_getifp(ue);
1024 uint16_t rxmode;
1025
1026 AXE_LOCK_ASSERT(sc, MA_OWNED);
1027
1028 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
1029 return;
1030
1031 /* Cancel pending I/O */
1032 axe_stop(ue);
1033
1034 axe_reset(sc);
1035
1036 /* Set MAC address. */
| 962 if (pos > (AXE_BULK_BUF_SIZE - MCLBYTES - sizeof(hdr))) {
963 /* send out frame(s) */
964 break;
965 }
966 } else {
967 /* send out frame */
968 break;
969 }
970 }
971
972 usbd_xfer_set_frame_len(xfer, 0, pos);
973 usbd_transfer_submit(xfer);
974 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
975 return;
976
977 default: /* Error */
978 DPRINTFN(11, "transfer error, %s\n",
979 usbd_errstr(error));
980
981 ifp->if_oerrors++;
982 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
983
984 if (error != USB_ERR_CANCELLED) {
985 /* try to clear stall first */
986 usbd_xfer_set_stall(xfer);
987 goto tr_setup;
988 }
989 return;
990
991 }
992}
993
994static void
995axe_tick(struct usb_ether *ue)
996{
997 struct axe_softc *sc = uether_getsc(ue);
998 struct mii_data *mii = GET_MII(sc);
999
1000 AXE_LOCK_ASSERT(sc, MA_OWNED);
1001
1002 mii_tick(mii);
1003 if ((sc->sc_flags & AXE_FLAG_LINK) == 0) {
1004 axe_miibus_statchg(ue->ue_dev);
1005 if ((sc->sc_flags & AXE_FLAG_LINK) != 0)
1006 axe_start(ue);
1007 }
1008}
1009
1010static void
1011axe_start(struct usb_ether *ue)
1012{
1013 struct axe_softc *sc = uether_getsc(ue);
1014
1015 /*
1016 * start the USB transfers, if not already started:
1017 */
1018 usbd_transfer_start(sc->sc_xfer[AXE_BULK_DT_RD]);
1019 usbd_transfer_start(sc->sc_xfer[AXE_BULK_DT_WR]);
1020}
1021
1022static void
1023axe_init(struct usb_ether *ue)
1024{
1025 struct axe_softc *sc = uether_getsc(ue);
1026 struct ifnet *ifp = uether_getifp(ue);
1027 uint16_t rxmode;
1028
1029 AXE_LOCK_ASSERT(sc, MA_OWNED);
1030
1031 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
1032 return;
1033
1034 /* Cancel pending I/O */
1035 axe_stop(ue);
1036
1037 axe_reset(sc);
1038
1039 /* Set MAC address. */
|
1037 if (sc->sc_flags & (AXE_FLAG_178 | AXE_FLAG_772))
| 1040 if (AXE_IS_178_FAMILY(sc))
|
1038 axe_cmd(sc, AXE_178_CMD_WRITE_NODEID, 0, 0, IF_LLADDR(ifp));
1039 else
1040 axe_cmd(sc, AXE_172_CMD_WRITE_NODEID, 0, 0, IF_LLADDR(ifp));
1041
1042 /* Set transmitter IPG values */
| 1041 axe_cmd(sc, AXE_178_CMD_WRITE_NODEID, 0, 0, IF_LLADDR(ifp));
1042 else
1043 axe_cmd(sc, AXE_172_CMD_WRITE_NODEID, 0, 0, IF_LLADDR(ifp));
1044
1045 /* Set transmitter IPG values */
|
1043 if (sc->sc_flags & (AXE_FLAG_178 | AXE_FLAG_772)) {
| 1046 if (AXE_IS_178_FAMILY(sc))
|
1044 axe_cmd(sc, AXE_178_CMD_WRITE_IPG012, sc->sc_ipgs[2],
1045 (sc->sc_ipgs[1] << 8) | (sc->sc_ipgs[0]), NULL);
| 1047 axe_cmd(sc, AXE_178_CMD_WRITE_IPG012, sc->sc_ipgs[2],
1048 (sc->sc_ipgs[1] << 8) | (sc->sc_ipgs[0]), NULL);
|
1046 } else {
| 1049 else {
|
1047 axe_cmd(sc, AXE_172_CMD_WRITE_IPG0, 0, sc->sc_ipgs[0], NULL);
1048 axe_cmd(sc, AXE_172_CMD_WRITE_IPG1, 0, sc->sc_ipgs[1], NULL);
1049 axe_cmd(sc, AXE_172_CMD_WRITE_IPG2, 0, sc->sc_ipgs[2], NULL);
1050 }
1051
1052 /* Enable receiver, set RX mode */
1053 rxmode = (AXE_RXCMD_MULTICAST | AXE_RXCMD_ENABLE);
| 1050 axe_cmd(sc, AXE_172_CMD_WRITE_IPG0, 0, sc->sc_ipgs[0], NULL);
1051 axe_cmd(sc, AXE_172_CMD_WRITE_IPG1, 0, sc->sc_ipgs[1], NULL);
1052 axe_cmd(sc, AXE_172_CMD_WRITE_IPG2, 0, sc->sc_ipgs[2], NULL);
1053 }
1054
1055 /* Enable receiver, set RX mode */
1056 rxmode = (AXE_RXCMD_MULTICAST | AXE_RXCMD_ENABLE);
|
1054 if (sc->sc_flags & (AXE_FLAG_178 | AXE_FLAG_772)) {
| 1057 if (AXE_IS_178_FAMILY(sc)) {
|
1055#if 0
1056 rxmode |= AXE_178_RXCMD_MFB_2048; /* chip default */
1057#else
1058 /*
1059 * Default Rx buffer size is too small to get
1060 * maximum performance.
1061 */
1062 rxmode |= AXE_178_RXCMD_MFB_16384;
1063#endif
1064 } else {
1065 rxmode |= AXE_172_RXCMD_UNICAST;
1066 }
1067
1068 /* If we want promiscuous mode, set the allframes bit. */
1069 if (ifp->if_flags & IFF_PROMISC)
1070 rxmode |= AXE_RXCMD_PROMISC;
1071
1072 if (ifp->if_flags & IFF_BROADCAST)
1073 rxmode |= AXE_RXCMD_BROADCAST;
1074
1075 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL);
1076
1077 /* Load the multicast filter. */
1078 axe_setmulti(ue);
1079
1080 usbd_xfer_set_stall(sc->sc_xfer[AXE_BULK_DT_WR]);
1081
1082 ifp->if_drv_flags |= IFF_DRV_RUNNING;
1083 /* Switch to selected media. */
1084 axe_ifmedia_upd(ifp);
1085 axe_start(ue);
1086}
1087
1088static void
1089axe_setpromisc(struct usb_ether *ue)
1090{
1091 struct axe_softc *sc = uether_getsc(ue);
1092 struct ifnet *ifp = uether_getifp(ue);
1093 uint16_t rxmode;
1094
1095 axe_cmd(sc, AXE_CMD_RXCTL_READ, 0, 0, &rxmode);
1096
1097 rxmode = le16toh(rxmode);
1098
1099 if (ifp->if_flags & IFF_PROMISC) {
1100 rxmode |= AXE_RXCMD_PROMISC;
1101 } else {
1102 rxmode &= ~AXE_RXCMD_PROMISC;
1103 }
1104
1105 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL);
1106
1107 axe_setmulti(ue);
1108}
1109
1110static void
1111axe_stop(struct usb_ether *ue)
1112{
1113 struct axe_softc *sc = uether_getsc(ue);
1114 struct ifnet *ifp = uether_getifp(ue);
1115
1116 AXE_LOCK_ASSERT(sc, MA_OWNED);
1117
1118 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
1119 sc->sc_flags &= ~AXE_FLAG_LINK;
1120
1121 /*
1122 * stop all the transfers, if not already stopped:
1123 */
1124 usbd_transfer_stop(sc->sc_xfer[AXE_BULK_DT_WR]);
1125 usbd_transfer_stop(sc->sc_xfer[AXE_BULK_DT_RD]);
1126}
| 1058#if 0
1059 rxmode |= AXE_178_RXCMD_MFB_2048; /* chip default */
1060#else
1061 /*
1062 * Default Rx buffer size is too small to get
1063 * maximum performance.
1064 */
1065 rxmode |= AXE_178_RXCMD_MFB_16384;
1066#endif
1067 } else {
1068 rxmode |= AXE_172_RXCMD_UNICAST;
1069 }
1070
1071 /* If we want promiscuous mode, set the allframes bit. */
1072 if (ifp->if_flags & IFF_PROMISC)
1073 rxmode |= AXE_RXCMD_PROMISC;
1074
1075 if (ifp->if_flags & IFF_BROADCAST)
1076 rxmode |= AXE_RXCMD_BROADCAST;
1077
1078 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL);
1079
1080 /* Load the multicast filter. */
1081 axe_setmulti(ue);
1082
1083 usbd_xfer_set_stall(sc->sc_xfer[AXE_BULK_DT_WR]);
1084
1085 ifp->if_drv_flags |= IFF_DRV_RUNNING;
1086 /* Switch to selected media. */
1087 axe_ifmedia_upd(ifp);
1088 axe_start(ue);
1089}
1090
1091static void
1092axe_setpromisc(struct usb_ether *ue)
1093{
1094 struct axe_softc *sc = uether_getsc(ue);
1095 struct ifnet *ifp = uether_getifp(ue);
1096 uint16_t rxmode;
1097
1098 axe_cmd(sc, AXE_CMD_RXCTL_READ, 0, 0, &rxmode);
1099
1100 rxmode = le16toh(rxmode);
1101
1102 if (ifp->if_flags & IFF_PROMISC) {
1103 rxmode |= AXE_RXCMD_PROMISC;
1104 } else {
1105 rxmode &= ~AXE_RXCMD_PROMISC;
1106 }
1107
1108 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL);
1109
1110 axe_setmulti(ue);
1111}
1112
1113static void
1114axe_stop(struct usb_ether *ue)
1115{
1116 struct axe_softc *sc = uether_getsc(ue);
1117 struct ifnet *ifp = uether_getifp(ue);
1118
1119 AXE_LOCK_ASSERT(sc, MA_OWNED);
1120
1121 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
1122 sc->sc_flags &= ~AXE_FLAG_LINK;
1123
1124 /*
1125 * stop all the transfers, if not already stopped:
1126 */
1127 usbd_transfer_stop(sc->sc_xfer[AXE_BULK_DT_WR]);
1128 usbd_transfer_stop(sc->sc_xfer[AXE_BULK_DT_RD]);
1129}
|