1/*-
2 * Copyright (c) 1997, 1998, 1999, 2000-2003
3 * Bill Paul <wpaul@windriver.com>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
31 */
32
33#include <sys/cdefs.h>
34__FBSDID("$FreeBSD: head/sys/dev/usb/net/if_axe.c 226479 2011-10-17 19:51:38Z yongari $");
35
36/*
37 * ASIX Electronics AX88172/AX88178/AX88778 USB 2.0 ethernet driver.
38 * Used in the LinkSys USB200M and various other adapters.
39 *
40 * Manuals available from:
41 * http://www.asix.com.tw/datasheet/mac/Ax88172.PDF
42 * Note: you need the manual for the AX88170 chip (USB 1.x ethernet
43 * controller) to find the definitions for the RX control register.
44 * http://www.asix.com.tw/datasheet/mac/Ax88170.PDF
45 *
46 * Written by Bill Paul <wpaul@windriver.com>
47 * Senior Engineer
48 * Wind River Systems
49 */
50
51/*
52 * The AX88172 provides USB ethernet supports at 10 and 100Mbps.
53 * It uses an external PHY (reference designs use a RealTek chip),
54 * and has a 64-bit multicast hash filter. There is some information
55 * missing from the manual which one needs to know in order to make
56 * the chip function:
57 *
58 * - You must set bit 7 in the RX control register, otherwise the
59 * chip won't receive any packets.
60 * - You must initialize all 3 IPG registers, or you won't be able
61 * to send any packets.
62 *
63 * Note that this device appears to only support loading the station
64 * address via autload from the EEPROM (i.e. there's no way to manaully
65 * set it).
66 *
67 * (Adam Weinberger wanted me to name this driver if_gir.c.)
68 */
69
70/*
71 * Ax88178 and Ax88772 support backported from the OpenBSD driver.
72 * 2007/02/12, J.R. Oldroyd, fbsd@opal.com
73 *
74 * Manual here:
75 * http://www.asix.com.tw/FrootAttach/datasheet/AX88178_datasheet_Rev10.pdf
76 * http://www.asix.com.tw/FrootAttach/datasheet/AX88772_datasheet_Rev10.pdf
77 */
78
79#include <sys/stdint.h>
80#include <sys/stddef.h>
81#include <sys/param.h>
82#include <sys/queue.h>
83#include <sys/types.h>
84#include <sys/systm.h>
85#include <sys/kernel.h>
86#include <sys/bus.h>
87#include <sys/module.h>
88#include <sys/lock.h>
89#include <sys/mutex.h>
90#include <sys/condvar.h>
91#include <sys/sysctl.h>
92#include <sys/sx.h>
93#include <sys/unistd.h>
94#include <sys/callout.h>
95#include <sys/malloc.h>
96#include <sys/priv.h>
97
98#include <dev/usb/usb.h>
99#include <dev/usb/usbdi.h>
100#include <dev/usb/usbdi_util.h>
101#include "usbdevs.h"
102
103#define USB_DEBUG_VAR axe_debug
104#include <dev/usb/usb_debug.h>
105#include <dev/usb/usb_process.h>
106
107#include <dev/usb/net/usb_ethernet.h>
108#include <dev/usb/net/if_axereg.h>
109
110/*
111 * AXE_178_MAX_FRAME_BURST
112 * max frame burst size for Ax88178 and Ax88772
113 * 0 2048 bytes
114 * 1 4096 bytes
115 * 2 8192 bytes
116 * 3 16384 bytes
117 * use the largest your system can handle without USB stalling.
118 *
119 * NB: 88772 parts appear to generate lots of input errors with
120 * a 2K rx buffer and 8K is only slightly faster than 4K on an
121 * EHCI port on a T42 so change at your own risk.
122 */
123#define AXE_178_MAX_FRAME_BURST 1
124
125#ifdef USB_DEBUG
126static int axe_debug = 0;
127
128SYSCTL_NODE(_hw_usb, OID_AUTO, axe, CTLFLAG_RW, 0, "USB axe");
129SYSCTL_INT(_hw_usb_axe, OID_AUTO, debug, CTLFLAG_RW, &axe_debug, 0,
130 "Debug level");
131#endif
132
133/*
134 * Various supported device vendors/products.
135 */
136static const STRUCT_USB_HOST_ID axe_devs[] = {
137#define AXE_DEV(v,p,i) { USB_VPI(USB_VENDOR_##v, USB_PRODUCT_##v##_##p, i) }
138 AXE_DEV(ABOCOM, UF200, 0),
139 AXE_DEV(ACERCM, EP1427X2, 0),
140 AXE_DEV(APPLE, ETHERNET, AXE_FLAG_772),
141 AXE_DEV(ASIX, AX88172, 0),
142 AXE_DEV(ASIX, AX88178, AXE_FLAG_178),
143 AXE_DEV(ASIX, AX88772, AXE_FLAG_772),
144 AXE_DEV(ASIX, AX88772A, AXE_FLAG_772A),
145 AXE_DEV(ASIX, AX88772B, AXE_FLAG_772B),
146 AXE_DEV(ATEN, UC210T, 0),
147 AXE_DEV(BELKIN, F5D5055, AXE_FLAG_178),
148 AXE_DEV(BILLIONTON, USB2AR, 0),
149 AXE_DEV(CISCOLINKSYS, USB200MV2, AXE_FLAG_772A),
150 AXE_DEV(COREGA, FETHER_USB2_TX, 0),
151 AXE_DEV(DLINK, DUBE100, 0),
152 AXE_DEV(DLINK, DUBE100B1, AXE_FLAG_772),
153 AXE_DEV(GOODWAY, GWUSB2E, 0),
154 AXE_DEV(IODATA, ETGUS2, AXE_FLAG_178),
155 AXE_DEV(JVC, MP_PRX1, 0),
156 AXE_DEV(LINKSYS2, USB200M, 0),
157 AXE_DEV(LINKSYS4, USB1000, AXE_FLAG_178),
158 AXE_DEV(LOGITEC, LAN_GTJU2A, AXE_FLAG_178),
159 AXE_DEV(MELCO, LUAU2KTX, 0),
160 AXE_DEV(MELCO, LUA3U2AGT, AXE_FLAG_178),
161 AXE_DEV(NETGEAR, FA120, 0),
162 AXE_DEV(OQO, ETHER01PLUS, AXE_FLAG_772),
163 AXE_DEV(PLANEX3, GU1000T, AXE_FLAG_178),
164 AXE_DEV(SITECOM, LN029, 0),
165 AXE_DEV(SITECOMEU, LN028, AXE_FLAG_178),
166 AXE_DEV(SYSTEMTALKS, SGCX2UL, 0),
167#undef AXE_DEV
168};
169
170static device_probe_t axe_probe;
171static device_attach_t axe_attach;
172static device_detach_t axe_detach;
173
174static usb_callback_t axe_bulk_read_callback;
175static usb_callback_t axe_bulk_write_callback;
176
177static miibus_readreg_t axe_miibus_readreg;
178static miibus_writereg_t axe_miibus_writereg;
179static miibus_statchg_t axe_miibus_statchg;
180
181static uether_fn_t axe_attach_post;
182static uether_fn_t axe_init;
183static uether_fn_t axe_stop;
184static uether_fn_t axe_start;
185static uether_fn_t axe_tick;
186static uether_fn_t axe_setmulti;
187static uether_fn_t axe_setpromisc;
188
189static int axe_ifmedia_upd(struct ifnet *);
190static void axe_ifmedia_sts(struct ifnet *, struct ifmediareq *);
191static int axe_cmd(struct axe_softc *, int, int, int, void *);
192static void axe_ax88178_init(struct axe_softc *);
193static void axe_ax88772_init(struct axe_softc *);
194static void axe_ax88772_phywake(struct axe_softc *);
195static void axe_ax88772a_init(struct axe_softc *);
196static void axe_ax88772b_init(struct axe_softc *);
197static int axe_get_phyno(struct axe_softc *, int);
198
199static const struct usb_config axe_config[AXE_N_TRANSFER] = {
200
201 [AXE_BULK_DT_WR] = {
202 .type = UE_BULK,
203 .endpoint = UE_ADDR_ANY,
204 .direction = UE_DIR_OUT,
205 .frames = 16,
206 .bufsize = 16 * MCLBYTES,
207 .flags = {.pipe_bof = 1,.force_short_xfer = 1,},
208 .callback = axe_bulk_write_callback,
209 .timeout = 10000, /* 10 seconds */
210 },
211
212 [AXE_BULK_DT_RD] = {
213 .type = UE_BULK,
214 .endpoint = UE_ADDR_ANY,
215 .direction = UE_DIR_IN,
216 .bufsize = 16384, /* bytes */
217 .flags = {.pipe_bof = 1,.short_xfer_ok = 1,},
218 .callback = axe_bulk_read_callback,
219 .timeout = 0, /* no timeout */
220 },
221};
222
223static const struct ax88772b_mfb ax88772b_mfb_table[] = {
224 { 0x8000, 0x8001, 2048 },
225 { 0x8100, 0x8147, 4096},
226 { 0x8200, 0x81EB, 6144},
227 { 0x8300, 0x83D7, 8192},
228 { 0x8400, 0x851E, 16384},
229 { 0x8500, 0x8666, 20480},
230 { 0x8600, 0x87AE, 24576},
231 { 0x8700, 0x8A3D, 32768}
232};
233
234static device_method_t axe_methods[] = {
235 /* Device interface */
236 DEVMETHOD(device_probe, axe_probe),
237 DEVMETHOD(device_attach, axe_attach),
238 DEVMETHOD(device_detach, axe_detach),
239
240 /* bus interface */
241 DEVMETHOD(bus_print_child, bus_generic_print_child),
242
243 /* MII interface */
244 DEVMETHOD(miibus_readreg, axe_miibus_readreg),
245 DEVMETHOD(miibus_writereg, axe_miibus_writereg),
246 DEVMETHOD(miibus_statchg, axe_miibus_statchg),
247
248 {0, 0}
249};
250
251static driver_t axe_driver = {
252 .name = "axe",
253 .methods = axe_methods,
254 .size = sizeof(struct axe_softc),
255};
256
257static devclass_t axe_devclass;
258
259DRIVER_MODULE(axe, uhub, axe_driver, axe_devclass, NULL, 0);
260DRIVER_MODULE(miibus, axe, miibus_driver, miibus_devclass, 0, 0);
261MODULE_DEPEND(axe, uether, 1, 1, 1);
262MODULE_DEPEND(axe, usb, 1, 1, 1);
263MODULE_DEPEND(axe, ether, 1, 1, 1);
264MODULE_DEPEND(axe, miibus, 1, 1, 1);
265MODULE_VERSION(axe, 1);
266
267static const struct usb_ether_methods axe_ue_methods = {
268 .ue_attach_post = axe_attach_post,
269 .ue_start = axe_start,
270 .ue_init = axe_init,
271 .ue_stop = axe_stop,
272 .ue_tick = axe_tick,
273 .ue_setmulti = axe_setmulti,
274 .ue_setpromisc = axe_setpromisc,
275 .ue_mii_upd = axe_ifmedia_upd,
276 .ue_mii_sts = axe_ifmedia_sts,
277};
278
279static int
280axe_cmd(struct axe_softc *sc, int cmd, int index, int val, void *buf)
281{
282 struct usb_device_request req;
283 usb_error_t err;
284
285 AXE_LOCK_ASSERT(sc, MA_OWNED);
286
287 req.bmRequestType = (AXE_CMD_IS_WRITE(cmd) ?
288 UT_WRITE_VENDOR_DEVICE :
289 UT_READ_VENDOR_DEVICE);
290 req.bRequest = AXE_CMD_CMD(cmd);
291 USETW(req.wValue, val);
292 USETW(req.wIndex, index);
293 USETW(req.wLength, AXE_CMD_LEN(cmd));
294
295 err = uether_do_request(&sc->sc_ue, &req, buf, 1000);
296
297 return (err);
298}
299
300static int
301axe_miibus_readreg(device_t dev, int phy, int reg)
302{
303 struct axe_softc *sc = device_get_softc(dev);
304 uint16_t val;
305 int locked;
306
307 if (sc->sc_phyno != phy)
308 return (0);
309
310 locked = mtx_owned(&sc->sc_mtx);
311 if (!locked)
312 AXE_LOCK(sc);
313
314 axe_cmd(sc, AXE_CMD_MII_OPMODE_SW, 0, 0, NULL);
315 axe_cmd(sc, AXE_CMD_MII_READ_REG, reg, phy, &val);
316 axe_cmd(sc, AXE_CMD_MII_OPMODE_HW, 0, 0, NULL);
317
318 val = le16toh(val);
319 if (AXE_IS_772(sc) && reg == MII_BMSR) {
320 /*
321 * BMSR of AX88772 indicates that it supports extended
322 * capability but the extended status register is
323 * revered for embedded ethernet PHY. So clear the
324 * extended capability bit of BMSR.
325 */
326 val &= ~BMSR_EXTCAP;
327 }
328
329 if (!locked)
330 AXE_UNLOCK(sc);
331 return (val);
332}
333
334static int
335axe_miibus_writereg(device_t dev, int phy, int reg, int val)
336{
337 struct axe_softc *sc = device_get_softc(dev);
338 int locked;
339
340 val = htole32(val);
341
342 if (sc->sc_phyno != phy)
343 return (0);
344
345 locked = mtx_owned(&sc->sc_mtx);
346 if (!locked)
347 AXE_LOCK(sc);
348
349 axe_cmd(sc, AXE_CMD_MII_OPMODE_SW, 0, 0, NULL);
350 axe_cmd(sc, AXE_CMD_MII_WRITE_REG, reg, phy, &val);
351 axe_cmd(sc, AXE_CMD_MII_OPMODE_HW, 0, 0, NULL);
352
353 if (!locked)
354 AXE_UNLOCK(sc);
355 return (0);
356}
357
358static void
359axe_miibus_statchg(device_t dev)
360{
361 struct axe_softc *sc = device_get_softc(dev);
362 struct mii_data *mii = GET_MII(sc);
363 struct ifnet *ifp;
364 uint16_t val;
365 int err, locked;
366
367 locked = mtx_owned(&sc->sc_mtx);
368 if (!locked)
369 AXE_LOCK(sc);
370
371 ifp = uether_getifp(&sc->sc_ue);
372 if (mii == NULL || ifp == NULL ||
373 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
374 goto done;
375
376 sc->sc_flags &= ~AXE_FLAG_LINK;
377 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
378 (IFM_ACTIVE | IFM_AVALID)) {
379 switch (IFM_SUBTYPE(mii->mii_media_active)) {
380 case IFM_10_T:
381 case IFM_100_TX:
382 sc->sc_flags |= AXE_FLAG_LINK;
383 break;
384 case IFM_1000_T:
385 if ((sc->sc_flags & AXE_FLAG_178) == 0)
386 break;
387 sc->sc_flags |= AXE_FLAG_LINK;
388 break;
389 default:
390 break;
391 }
392 }
393
394 /* Lost link, do nothing. */
395 if ((sc->sc_flags & AXE_FLAG_LINK) == 0)
396 goto done;
397
398 val = 0;
399 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0)
400 val |= AXE_MEDIA_FULL_DUPLEX;
401 if (AXE_IS_178_FAMILY(sc)) {
402 val |= AXE_178_MEDIA_RX_EN | AXE_178_MEDIA_MAGIC;
403 if ((sc->sc_flags & AXE_FLAG_178) != 0)
404 val |= AXE_178_MEDIA_ENCK;
405 switch (IFM_SUBTYPE(mii->mii_media_active)) {
406 case IFM_1000_T:
407 val |= AXE_178_MEDIA_GMII | AXE_178_MEDIA_ENCK;
408 break;
409 case IFM_100_TX:
410 val |= AXE_178_MEDIA_100TX;
411 break;
412 case IFM_10_T:
413 /* doesn't need to be handled */
414 break;
415 }
416 }
417 err = axe_cmd(sc, AXE_CMD_WRITE_MEDIA, 0, val, NULL);
418 if (err)
419 device_printf(dev, "media change failed, error %d\n", err);
420done:
421 if (!locked)
422 AXE_UNLOCK(sc);
423}
424
425/*
426 * Set media options.
427 */
428static int
429axe_ifmedia_upd(struct ifnet *ifp)
430{
431 struct axe_softc *sc = ifp->if_softc;
432 struct mii_data *mii = GET_MII(sc);
433 struct mii_softc *miisc;
434 int error;
435
436 AXE_LOCK_ASSERT(sc, MA_OWNED);
437
438 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
439 PHY_RESET(miisc);
440 error = mii_mediachg(mii);
441 return (error);
442}
443
444/*
445 * Report current media status.
446 */
447static void
448axe_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
449{
450 struct axe_softc *sc = ifp->if_softc;
451 struct mii_data *mii = GET_MII(sc);
452
453 AXE_LOCK(sc);
454 mii_pollstat(mii);
455 ifmr->ifm_active = mii->mii_media_active;
456 ifmr->ifm_status = mii->mii_media_status;
457 AXE_UNLOCK(sc);
458}
459
460static void
461axe_setmulti(struct usb_ether *ue)
462{
463 struct axe_softc *sc = uether_getsc(ue);
464 struct ifnet *ifp = uether_getifp(ue);
465 struct ifmultiaddr *ifma;
466 uint32_t h = 0;
467 uint16_t rxmode;
468 uint8_t hashtbl[8] = { 0, 0, 0, 0, 0, 0, 0, 0 };
469
470 AXE_LOCK_ASSERT(sc, MA_OWNED);
471
472 axe_cmd(sc, AXE_CMD_RXCTL_READ, 0, 0, &rxmode);
473 rxmode = le16toh(rxmode);
474
475 if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) {
476 rxmode |= AXE_RXCMD_ALLMULTI;
477 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL);
478 return;
479 }
480 rxmode &= ~AXE_RXCMD_ALLMULTI;
481
482 if_maddr_rlock(ifp);
483 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link)
484 {
485 if (ifma->ifma_addr->sa_family != AF_LINK)
486 continue;
487 h = ether_crc32_be(LLADDR((struct sockaddr_dl *)
488 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26;
489 hashtbl[h / 8] |= 1 << (h % 8);
490 }
491 if_maddr_runlock(ifp);
492
493 axe_cmd(sc, AXE_CMD_WRITE_MCAST, 0, 0, (void *)&hashtbl);
494 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL);
495}
496
497static int
498axe_get_phyno(struct axe_softc *sc, int sel)
499{
500 int phyno;
501
502 switch (AXE_PHY_TYPE(sc->sc_phyaddrs[sel])) {
503 case PHY_TYPE_100_HOME:
504 case PHY_TYPE_GIG:
505 phyno = AXE_PHY_NO(sc->sc_phyaddrs[sel]);
506 break;
507 case PHY_TYPE_SPECIAL:
508 /* FALLTHROUGH */
509 case PHY_TYPE_RSVD:
510 /* FALLTHROUGH */
511 case PHY_TYPE_NON_SUP:
512 /* FALLTHROUGH */
513 default:
514 phyno = -1;
515 break;
516 }
517
518 return (phyno);
519}
520
521#define AXE_GPIO_WRITE(x, y) do { \
522 axe_cmd(sc, AXE_CMD_WRITE_GPIO, 0, (x), NULL); \
523 uether_pause(ue, (y)); \
524} while (0)
525
526static void
527axe_ax88178_init(struct axe_softc *sc)
528{
529 struct usb_ether *ue;
530 int gpio0, ledmode, phymode;
531 uint16_t eeprom, val;
532
533 ue = &sc->sc_ue;
534 axe_cmd(sc, AXE_CMD_SROM_WR_ENABLE, 0, 0, NULL);
535 /* XXX magic */
536 axe_cmd(sc, AXE_CMD_SROM_READ, 0, 0x0017, &eeprom);
537 eeprom = le16toh(eeprom);
538 axe_cmd(sc, AXE_CMD_SROM_WR_DISABLE, 0, 0, NULL);
539
540 /* if EEPROM is invalid we have to use to GPIO0 */
541 if (eeprom == 0xffff) {
542 phymode = AXE_PHY_MODE_MARVELL;
543 gpio0 = 1;
544 ledmode = 0;
545 } else {
546 phymode = eeprom & 0x7f;
547 gpio0 = (eeprom & 0x80) ? 0 : 1;
548 ledmode = eeprom >> 8;
549 }
550
551 if (bootverbose)
552 device_printf(sc->sc_ue.ue_dev,
553 "EEPROM data : 0x%04x, phymode : 0x%02x\n", eeprom,
554 phymode);
555 /* Program GPIOs depending on PHY hardware. */
556 switch (phymode) {
557 case AXE_PHY_MODE_MARVELL:
558 if (gpio0 == 1) {
559 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO0_EN,
560 hz / 32);
561 AXE_GPIO_WRITE(AXE_GPIO0_EN | AXE_GPIO2 | AXE_GPIO2_EN,
562 hz / 32);
563 AXE_GPIO_WRITE(AXE_GPIO0_EN | AXE_GPIO2_EN, hz / 4);
564 AXE_GPIO_WRITE(AXE_GPIO0_EN | AXE_GPIO2 | AXE_GPIO2_EN,
565 hz / 32);
566 } else {
567 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO1 |
568 AXE_GPIO1_EN, hz / 3);
569 if (ledmode == 1) {
570 AXE_GPIO_WRITE(AXE_GPIO1_EN, hz / 3);
571 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN,
572 hz / 3);
573 } else {
574 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN |
575 AXE_GPIO2 | AXE_GPIO2_EN, hz / 32);
576 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN |
577 AXE_GPIO2_EN, hz / 4);
578 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN |
579 AXE_GPIO2 | AXE_GPIO2_EN, hz / 32);
580 }
581 }
582 break;
583 case AXE_PHY_MODE_CICADA:
584 case AXE_PHY_MODE_CICADA_V2:
585 case AXE_PHY_MODE_CICADA_V2_ASIX:
586 if (gpio0 == 1)
587 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO0 |
588 AXE_GPIO0_EN, hz / 32);
589 else
590 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO1 |
591 AXE_GPIO1_EN, hz / 32);
592 break;
593 case AXE_PHY_MODE_AGERE:
594 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO1 |
595 AXE_GPIO1_EN, hz / 32);
596 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | AXE_GPIO2 |
597 AXE_GPIO2_EN, hz / 32);
598 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | AXE_GPIO2_EN, hz / 4);
599 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | AXE_GPIO2 |
600 AXE_GPIO2_EN, hz / 32);
601 break;
602 case AXE_PHY_MODE_REALTEK_8211CL:
603 case AXE_PHY_MODE_REALTEK_8211BN:
604 case AXE_PHY_MODE_REALTEK_8251CL:
605 val = gpio0 == 1 ? AXE_GPIO0 | AXE_GPIO0_EN :
606 AXE_GPIO1 | AXE_GPIO1_EN;
607 AXE_GPIO_WRITE(val, hz / 32);
608 AXE_GPIO_WRITE(val | AXE_GPIO2 | AXE_GPIO2_EN, hz / 32);
609 AXE_GPIO_WRITE(val | AXE_GPIO2_EN, hz / 4);
610 AXE_GPIO_WRITE(val | AXE_GPIO2 | AXE_GPIO2_EN, hz / 32);
611 if (phymode == AXE_PHY_MODE_REALTEK_8211CL) {
612 axe_miibus_writereg(ue->ue_dev, sc->sc_phyno,
613 0x1F, 0x0005);
614 axe_miibus_writereg(ue->ue_dev, sc->sc_phyno,
615 0x0C, 0x0000);
616 val = axe_miibus_readreg(ue->ue_dev, sc->sc_phyno,
617 0x0001);
618 axe_miibus_writereg(ue->ue_dev, sc->sc_phyno,
619 0x01, val | 0x0080);
620 axe_miibus_writereg(ue->ue_dev, sc->sc_phyno,
621 0x1F, 0x0000);
622 }
623 break;
624 default:
625 /* Unknown PHY model or no need to program GPIOs. */
626 break;
627 }
628
629 /* soft reset */
630 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_CLEAR, NULL);
631 uether_pause(ue, hz / 4);
632
633 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0,
634 AXE_SW_RESET_PRL | AXE_178_RESET_MAGIC, NULL);
635 uether_pause(ue, hz / 4);
636 /* Enable MII/GMII/RGMII interface to work with external PHY. */
637 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, 0, NULL);
638 uether_pause(ue, hz / 4);
639
640 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL);
641}
642
643static void
644axe_ax88772_init(struct axe_softc *sc)
645{
646 axe_cmd(sc, AXE_CMD_WRITE_GPIO, 0, 0x00b0, NULL);
647 uether_pause(&sc->sc_ue, hz / 16);
648
649 if (sc->sc_phyno == AXE_772_PHY_NO_EPHY) {
650 /* ask for the embedded PHY */
651 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, 0x01, NULL);
652 uether_pause(&sc->sc_ue, hz / 64);
653
654 /* power down and reset state, pin reset state */
655 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0,
656 AXE_SW_RESET_CLEAR, NULL);
657 uether_pause(&sc->sc_ue, hz / 16);
658
659 /* power down/reset state, pin operating state */
660 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0,
661 AXE_SW_RESET_IPPD | AXE_SW_RESET_PRL, NULL);
662 uether_pause(&sc->sc_ue, hz / 4);
663
664 /* power up, reset */
665 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_PRL, NULL);
666
667 /* power up, operating */
668 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0,
669 AXE_SW_RESET_IPRL | AXE_SW_RESET_PRL, NULL);
670 } else {
671 /* ask for external PHY */
672 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, 0x00, NULL);
673 uether_pause(&sc->sc_ue, hz / 64);
674
675 /* power down internal PHY */
676 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0,
677 AXE_SW_RESET_IPPD | AXE_SW_RESET_PRL, NULL);
678 }
679
680 uether_pause(&sc->sc_ue, hz / 4);
681 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL);
682}
683
684static void
685axe_ax88772_phywake(struct axe_softc *sc)
686{
687 struct usb_ether *ue;
688
689 ue = &sc->sc_ue;
690 if (sc->sc_phyno == AXE_772_PHY_NO_EPHY) {
691 /* Manually select internal(embedded) PHY - MAC mode. */
692 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, AXE_SW_PHY_SELECT_SS_ENB |
693 AXE_SW_PHY_SELECT_EMBEDDED | AXE_SW_PHY_SELECT_SS_MII,
694 NULL);
695 uether_pause(&sc->sc_ue, hz / 32);
696 } else {
697 /*
698 * Manually select external PHY - MAC mode.
699 * Reverse MII/RMII is for AX88772A PHY mode.
700 */
701 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, AXE_SW_PHY_SELECT_SS_ENB |
702 AXE_SW_PHY_SELECT_EXT | AXE_SW_PHY_SELECT_SS_MII, NULL);
703 uether_pause(&sc->sc_ue, hz / 32);
704 }
705 /* Take PHY out of power down. */
706 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_IPPD |
707 AXE_SW_RESET_IPRL, NULL);
708 uether_pause(&sc->sc_ue, hz / 4);
709 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_IPRL, NULL);
710 uether_pause(&sc->sc_ue, hz);
711 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_CLEAR, NULL);
712 uether_pause(&sc->sc_ue, hz / 32);
713 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_IPRL, NULL);
714 uether_pause(&sc->sc_ue, hz / 32);
715}
716
717static void
718axe_ax88772a_init(struct axe_softc *sc)
719{
720 struct usb_ether *ue;
721
722 ue = &sc->sc_ue;
723 /* Reload EEPROM. */
724 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM, hz / 32);
725 axe_ax88772_phywake(sc);
726 /* Stop MAC. */
727 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL);
728}
729
730static void
731axe_ax88772b_init(struct axe_softc *sc)
732{
733 struct usb_ether *ue;
734 uint16_t eeprom;
735 uint8_t *eaddr;
736 int i;
737
738 ue = &sc->sc_ue;
739 /* Reload EEPROM. */
740 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM, hz / 32);
741 /*
742 * Save PHY power saving configuration(high byte) and
743 * clear EEPROM checksum value(low byte).
744 */
745 axe_cmd(sc, AXE_CMD_SROM_READ, 0, AXE_EEPROM_772B_PHY_PWRCFG, &eeprom);
746 sc->sc_pwrcfg = le16toh(eeprom) & 0xFF00;
747
748 /*
749 * Auto-loaded default station address from internal ROM is
750 * 00:00:00:00:00:00 such that an explicit access to EEPROM
751 * is required to get real station address.
752 */
753 eaddr = ue->ue_eaddr;
754 for (i = 0; i < ETHER_ADDR_LEN / 2; i++) {
755 axe_cmd(sc, AXE_CMD_SROM_READ, 0, AXE_EEPROM_772B_NODE_ID + i,
756 &eeprom);
757 eeprom = le16toh(eeprom);
758 *eaddr++ = (uint8_t)(eeprom & 0xFF);
759 *eaddr++ = (uint8_t)((eeprom >> 8) & 0xFF);
760 }
761 /* Wakeup PHY. */
762 axe_ax88772_phywake(sc);
763 /* Stop MAC. */
764 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL);
765}
766
767#undef AXE_GPIO_WRITE
768
769static void
770axe_reset(struct axe_softc *sc)
771{
772 struct usb_config_descriptor *cd;
773 usb_error_t err;
774
775 cd = usbd_get_config_descriptor(sc->sc_ue.ue_udev);
776
777 err = usbd_req_set_config(sc->sc_ue.ue_udev, &sc->sc_mtx,
778 cd->bConfigurationValue);
779 if (err)
780 DPRINTF("reset failed (ignored)\n");
781
782 /* Wait a little while for the chip to get its brains in order. */
783 uether_pause(&sc->sc_ue, hz / 100);
784
785 /* Reinitialize controller to achieve full reset. */
786 if (sc->sc_flags & AXE_FLAG_178)
787 axe_ax88178_init(sc);
788 else if (sc->sc_flags & AXE_FLAG_772)
789 axe_ax88772_init(sc);
790 else if (sc->sc_flags & AXE_FLAG_772A)
791 axe_ax88772a_init(sc);
792 else if (sc->sc_flags & AXE_FLAG_772B)
793 axe_ax88772b_init(sc);
794}
795
796static void
797axe_attach_post(struct usb_ether *ue)
798{
799 struct axe_softc *sc = uether_getsc(ue);
800
801 /*
802 * Load PHY indexes first. Needed by axe_xxx_init().
803 */
804 axe_cmd(sc, AXE_CMD_READ_PHYID, 0, 0, sc->sc_phyaddrs);
805 if (bootverbose)
806 device_printf(sc->sc_ue.ue_dev, "PHYADDR 0x%02x:0x%02x\n",
807 sc->sc_phyaddrs[0], sc->sc_phyaddrs[1]);
808 sc->sc_phyno = axe_get_phyno(sc, AXE_PHY_SEL_PRI);
809 if (sc->sc_phyno == -1)
810 sc->sc_phyno = axe_get_phyno(sc, AXE_PHY_SEL_SEC);
811 if (sc->sc_phyno == -1) {
812 device_printf(sc->sc_ue.ue_dev,
813 "no valid PHY address found, assuming PHY address 0\n");
814 sc->sc_phyno = 0;
815 }
816
817 /* Initialize controller and get station address. */
818 if (sc->sc_flags & AXE_FLAG_178) {
819 axe_ax88178_init(sc);
820 sc->sc_tx_bufsz = 16 * 1024;
821 axe_cmd(sc, AXE_178_CMD_READ_NODEID, 0, 0, ue->ue_eaddr);
822 } else if (sc->sc_flags & AXE_FLAG_772) {
823 axe_ax88772_init(sc);
824 sc->sc_tx_bufsz = 8 * 1024;
825 axe_cmd(sc, AXE_178_CMD_READ_NODEID, 0, 0, ue->ue_eaddr);
826 } else if (sc->sc_flags & AXE_FLAG_772A) {
827 axe_ax88772a_init(sc);
828 sc->sc_tx_bufsz = 8 * 1024;
829 axe_cmd(sc, AXE_178_CMD_READ_NODEID, 0, 0, ue->ue_eaddr);
830 } else if (sc->sc_flags & AXE_FLAG_772B) {
831 axe_ax88772b_init(sc);
832 sc->sc_tx_bufsz = 8 * 1024;
833 } else
834 axe_cmd(sc, AXE_172_CMD_READ_NODEID, 0, 0, ue->ue_eaddr);
835
836 /*
837 * Fetch IPG values.
838 */
839 if (sc->sc_flags & (AXE_FLAG_772A | AXE_FLAG_772B)) {
840 /* Set IPG values. */
841 sc->sc_ipgs[0] = 0x15;
842 sc->sc_ipgs[1] = 0x16;
843 sc->sc_ipgs[2] = 0x1A;
844 } else
845 axe_cmd(sc, AXE_CMD_READ_IPG012, 0, 0, sc->sc_ipgs);
846}
847
848/*
849 * Probe for a AX88172 chip.
850 */
851static int
852axe_probe(device_t dev)
853{
854 struct usb_attach_arg *uaa = device_get_ivars(dev);
855
856 if (uaa->usb_mode != USB_MODE_HOST)
857 return (ENXIO);
858 if (uaa->info.bConfigIndex != AXE_CONFIG_IDX)
859 return (ENXIO);
860 if (uaa->info.bIfaceIndex != AXE_IFACE_IDX)
861 return (ENXIO);
862
863 return (usbd_lookup_id_by_uaa(axe_devs, sizeof(axe_devs), uaa));
864}
865
866/*
867 * Attach the interface. Allocate softc structures, do ifmedia
868 * setup and ethernet/BPF attach.
869 */
870static int
871axe_attach(device_t dev)
872{
873 struct usb_attach_arg *uaa = device_get_ivars(dev);
874 struct axe_softc *sc = device_get_softc(dev);
875 struct usb_ether *ue = &sc->sc_ue;
876 uint8_t iface_index;
877 int error;
878
879 sc->sc_flags = USB_GET_DRIVER_INFO(uaa);
880
881 device_set_usb_desc(dev);
882
883 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), NULL, MTX_DEF);
884
885 iface_index = AXE_IFACE_IDX;
886 error = usbd_transfer_setup(uaa->device, &iface_index, sc->sc_xfer,
887 axe_config, AXE_N_TRANSFER, sc, &sc->sc_mtx);
888 if (error) {
889 device_printf(dev, "allocating USB transfers failed\n");
890 goto detach;
891 }
892
893 ue->ue_sc = sc;
894 ue->ue_dev = dev;
895 ue->ue_udev = uaa->device;
896 ue->ue_mtx = &sc->sc_mtx;
897 ue->ue_methods = &axe_ue_methods;
898
899 error = uether_ifattach(ue);
900 if (error) {
901 device_printf(dev, "could not attach interface\n");
902 goto detach;
903 }
904 return (0); /* success */
905
906detach:
907 axe_detach(dev);
908 return (ENXIO); /* failure */
909}
910
911static int
912axe_detach(device_t dev)
913{
914 struct axe_softc *sc = device_get_softc(dev);
915 struct usb_ether *ue = &sc->sc_ue;
916
917 usbd_transfer_unsetup(sc->sc_xfer, AXE_N_TRANSFER);
918 uether_ifdetach(ue);
919 mtx_destroy(&sc->sc_mtx);
920
921 return (0);
922}
923
924#if (AXE_BULK_BUF_SIZE >= 0x10000)
925#error "Please update axe_bulk_read_callback()!"
926#endif
927
928static void
929axe_bulk_read_callback(struct usb_xfer *xfer, usb_error_t error)
930{
931 struct axe_softc *sc = usbd_xfer_softc(xfer);
932 struct usb_ether *ue = &sc->sc_ue;
933 struct ifnet *ifp = uether_getifp(ue);
934 struct axe_sframe_hdr hdr;
935 struct usb_page_cache *pc;
936 int err, pos, len;
937 int actlen;
938
939 usbd_xfer_status(xfer, &actlen, NULL, NULL, NULL);
940
941 switch (USB_GET_STATE(xfer)) {
942 case USB_ST_TRANSFERRED:
943 pos = 0;
944 len = 0;
945 err = 0;
946
947 pc = usbd_xfer_get_frame(xfer, 0);
948 if (AXE_IS_178_FAMILY(sc)) {
949 while (pos < actlen) {
950 if ((pos + sizeof(hdr)) > actlen) {
951 /* too little data */
952 err = EINVAL;
953 break;
954 }
955 usbd_copy_out(pc, pos, &hdr, sizeof(hdr));
956
957 if ((hdr.len ^ hdr.ilen) != 0xFFFF) {
958 /* we lost sync */
959 err = EINVAL;
960 break;
961 }
962 pos += sizeof(hdr);
963
964 len = le16toh(hdr.len);
965 if ((pos + len) > actlen) {
966 /* invalid length */
967 err = EINVAL;
968 break;
969 }
970 uether_rxbuf(ue, pc, pos, len);
971
972 pos += len + (len % 2);
973 }
974 } else
975 uether_rxbuf(ue, pc, 0, actlen);
976
977 if (err != 0)
978 ifp->if_ierrors++;
979
980 /* FALLTHROUGH */
981 case USB_ST_SETUP:
982tr_setup:
983 usbd_xfer_set_frame_len(xfer, 0, usbd_xfer_max_len(xfer));
984 usbd_transfer_submit(xfer);
985 uether_rxflush(ue);
986 return;
987
988 default: /* Error */
989 DPRINTF("bulk read error, %s\n", usbd_errstr(error));
990
991 if (error != USB_ERR_CANCELLED) {
992 /* try to clear stall first */
993 usbd_xfer_set_stall(xfer);
994 goto tr_setup;
995 }
996 return;
997
998 }
999}
1000
1001#if ((AXE_BULK_BUF_SIZE >= 0x10000) || (AXE_BULK_BUF_SIZE < (MCLBYTES+4)))
1002#error "Please update axe_bulk_write_callback()!"
1003#endif
1004
1005static void
1006axe_bulk_write_callback(struct usb_xfer *xfer, usb_error_t error)
1007{
1008 struct axe_softc *sc = usbd_xfer_softc(xfer);
1009 struct axe_sframe_hdr hdr;
1010 struct ifnet *ifp = uether_getifp(&sc->sc_ue);
1011 struct usb_page_cache *pc;
1012 struct mbuf *m;
1013 int nframes, pos;
1014
1015 switch (USB_GET_STATE(xfer)) {
1016 case USB_ST_TRANSFERRED:
1017 DPRINTFN(11, "transfer complete\n");
1018 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1019 /* FALLTHROUGH */
1020 case USB_ST_SETUP:
1021tr_setup:
1022 if ((sc->sc_flags & AXE_FLAG_LINK) == 0 ||
1023 (ifp->if_drv_flags & IFF_DRV_OACTIVE) != 0) {
1024 /*
1025 * Don't send anything if there is no link or
1026 * controller is busy.
1027 */
1028 return;
1029 }
1030
1031 for (nframes = 0; nframes < 16 &&
1032 !IFQ_DRV_IS_EMPTY(&ifp->if_snd); nframes++) {
1033 IFQ_DRV_DEQUEUE(&ifp->if_snd, m);
1034 if (m == NULL)
1035 break;
1036 usbd_xfer_set_frame_offset(xfer, nframes * MCLBYTES,
1037 nframes);
1038 pos = 0;
1039 pc = usbd_xfer_get_frame(xfer, nframes);
1040 if (AXE_IS_178_FAMILY(sc)) {
1041 hdr.len = htole16(m->m_pkthdr.len);
1042 hdr.ilen = ~hdr.len;
1043 usbd_copy_in(pc, pos, &hdr, sizeof(hdr));
1044 pos += sizeof(hdr);
1045 usbd_m_copy_in(pc, pos, m, 0, m->m_pkthdr.len);
1046 pos += m->m_pkthdr.len;
1047 if ((pos % 512) == 0) {
1048 hdr.len = 0;
1049 hdr.ilen = 0xffff;
1050 usbd_copy_in(pc, pos, &hdr,
1051 sizeof(hdr));
1052 pos += sizeof(hdr);
1053 }
1054 } else {
1055 usbd_m_copy_in(pc, pos, m, 0, m->m_pkthdr.len);
1056 pos += m->m_pkthdr.len;
1057 }
1058
1059 /*
1060 * XXX
1061 * Update TX packet counter here. This is not
1062 * correct way but it seems that there is no way
1063 * to know how many packets are sent at the end
1064 * of transfer because controller combines
1065 * multiple writes into single one if there is
1066 * room in TX buffer of controller.
1067 */
1068 ifp->if_opackets++;
1069
1070 /*
1071 * if there's a BPF listener, bounce a copy
1072 * of this frame to him:
1073 */
1074 BPF_MTAP(ifp, m);
1075
1076 m_freem(m);
1077
1078 /* Set frame length. */
1079 usbd_xfer_set_frame_len(xfer, nframes, pos);
1080 }
1081 if (nframes != 0) {
1082 usbd_xfer_set_frames(xfer, nframes);
1083 usbd_transfer_submit(xfer);
1084 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1085 }
1086 return;
1087 /* NOTREACHED */
1088 default: /* Error */
1089 DPRINTFN(11, "transfer error, %s\n",
1090 usbd_errstr(error));
1091
1092 ifp->if_oerrors++;
1093 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1094
1095 if (error != USB_ERR_CANCELLED) {
1096 /* try to clear stall first */
1097 usbd_xfer_set_stall(xfer);
1098 goto tr_setup;
1099 }
1100 return;
1101
1102 }
1103}
1104
1105static void
1106axe_tick(struct usb_ether *ue)
1107{
1108 struct axe_softc *sc = uether_getsc(ue);
1109 struct mii_data *mii = GET_MII(sc);
1110
1111 AXE_LOCK_ASSERT(sc, MA_OWNED);
1112
1113 mii_tick(mii);
1114 if ((sc->sc_flags & AXE_FLAG_LINK) == 0) {
1115 axe_miibus_statchg(ue->ue_dev);
1116 if ((sc->sc_flags & AXE_FLAG_LINK) != 0)
1117 axe_start(ue);
1118 }
1119}
1120
1121static void
1122axe_start(struct usb_ether *ue)
1123{
1124 struct axe_softc *sc = uether_getsc(ue);
1125
1126 /*
1127 * start the USB transfers, if not already started:
1128 */
1129 usbd_transfer_start(sc->sc_xfer[AXE_BULK_DT_RD]);
1130 usbd_transfer_start(sc->sc_xfer[AXE_BULK_DT_WR]);
1131}
1132
1133static void
1134axe_init(struct usb_ether *ue)
1135{
1136 struct axe_softc *sc = uether_getsc(ue);
1137 struct ifnet *ifp = uether_getifp(ue);
1138 uint16_t rxmode;
1139
1140 AXE_LOCK_ASSERT(sc, MA_OWNED);
1141
1142 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
1143 return;
1144
1145 /* Cancel pending I/O */
1146 axe_stop(ue);
1147
1148 axe_reset(sc);
1149
1150 /* Set MAC address. */
1151 if (AXE_IS_178_FAMILY(sc))
1152 axe_cmd(sc, AXE_178_CMD_WRITE_NODEID, 0, 0, IF_LLADDR(ifp));
1153 else
1154 axe_cmd(sc, AXE_172_CMD_WRITE_NODEID, 0, 0, IF_LLADDR(ifp));
1155
1156 /* Set transmitter IPG values */
1157 if (AXE_IS_178_FAMILY(sc))
1158 axe_cmd(sc, AXE_178_CMD_WRITE_IPG012, sc->sc_ipgs[2],
1159 (sc->sc_ipgs[1] << 8) | (sc->sc_ipgs[0]), NULL);
1160 else {
1161 axe_cmd(sc, AXE_172_CMD_WRITE_IPG0, 0, sc->sc_ipgs[0], NULL);
1162 axe_cmd(sc, AXE_172_CMD_WRITE_IPG1, 0, sc->sc_ipgs[1], NULL);
1163 axe_cmd(sc, AXE_172_CMD_WRITE_IPG2, 0, sc->sc_ipgs[2], NULL);
1164 }
1165
1166 /* AX88772B uses different maximum frame burst configuration. */
1167 if (sc->sc_flags & AXE_FLAG_772B)
1168 axe_cmd(sc, AXE_772B_CMD_RXCTL_WRITE_CFG,
1169 ax88772b_mfb_table[AX88772B_MFB_16K].threshold,
1170 ax88772b_mfb_table[AX88772B_MFB_16K].byte_cnt, NULL);
1171
1172 /* Enable receiver, set RX mode. */
1173 rxmode = (AXE_RXCMD_MULTICAST | AXE_RXCMD_ENABLE);
1174 if (AXE_IS_178_FAMILY(sc)) {
1175 if (sc->sc_flags & AXE_FLAG_772B) {
1176 /*
1177 * Select RX header format type 1. Aligning IP
1178 * header on 4 byte boundary is not needed
1179 * because we always copy the received frame in
1180 * RX handler.
1181 */
1182 rxmode |= AXE_772B_RXCMD_HDR_TYPE_1;
1183 } else {
1184 /*
1185 * Default Rx buffer size is too small to get
1186 * maximum performance.
1187 */
1188 rxmode |= AXE_178_RXCMD_MFB_16384;
1189 }
1190 } else {
1191 rxmode |= AXE_172_RXCMD_UNICAST;
1192 }
1193
1194 /* If we want promiscuous mode, set the allframes bit. */
1195 if (ifp->if_flags & IFF_PROMISC)
1196 rxmode |= AXE_RXCMD_PROMISC;
1197
1198 if (ifp->if_flags & IFF_BROADCAST)
1199 rxmode |= AXE_RXCMD_BROADCAST;
1200
1201 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL);
1202
1203 /* Load the multicast filter. */
1204 axe_setmulti(ue);
1205
1206 usbd_xfer_set_stall(sc->sc_xfer[AXE_BULK_DT_WR]);
1207
1208 ifp->if_drv_flags |= IFF_DRV_RUNNING;
1209 /* Switch to selected media. */
1210 axe_ifmedia_upd(ifp);
1211 axe_start(ue);
1212}
1213
1214static void
1215axe_setpromisc(struct usb_ether *ue)
1216{
1217 struct axe_softc *sc = uether_getsc(ue);
1218 struct ifnet *ifp = uether_getifp(ue);
1219 uint16_t rxmode;
1220
1221 axe_cmd(sc, AXE_CMD_RXCTL_READ, 0, 0, &rxmode);
1222
1223 rxmode = le16toh(rxmode);
1224
1225 if (ifp->if_flags & IFF_PROMISC) {
1226 rxmode |= AXE_RXCMD_PROMISC;
1227 } else {
1228 rxmode &= ~AXE_RXCMD_PROMISC;
1229 }
1230
1231 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL);
1232
1233 axe_setmulti(ue);
1234}
1235
1236static void
1237axe_stop(struct usb_ether *ue)
1238{
1239 struct axe_softc *sc = uether_getsc(ue);
1240 struct ifnet *ifp = uether_getifp(ue);
1241
1242 AXE_LOCK_ASSERT(sc, MA_OWNED);
1243
1244 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
1245 sc->sc_flags &= ~AXE_FLAG_LINK;
1246
1247 /*
1248 * stop all the transfers, if not already stopped:
1249 */
1250 usbd_transfer_stop(sc->sc_xfer[AXE_BULK_DT_WR]);
1251 usbd_transfer_stop(sc->sc_xfer[AXE_BULK_DT_RD]);
1252}
2 * Copyright (c) 1997, 1998, 1999, 2000-2003
3 * Bill Paul <wpaul@windriver.com>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
31 */
32
33#include <sys/cdefs.h>
34__FBSDID("$FreeBSD: head/sys/dev/usb/net/if_axe.c 226479 2011-10-17 19:51:38Z yongari $");
35
36/*
37 * ASIX Electronics AX88172/AX88178/AX88778 USB 2.0 ethernet driver.
38 * Used in the LinkSys USB200M and various other adapters.
39 *
40 * Manuals available from:
41 * http://www.asix.com.tw/datasheet/mac/Ax88172.PDF
42 * Note: you need the manual for the AX88170 chip (USB 1.x ethernet
43 * controller) to find the definitions for the RX control register.
44 * http://www.asix.com.tw/datasheet/mac/Ax88170.PDF
45 *
46 * Written by Bill Paul <wpaul@windriver.com>
47 * Senior Engineer
48 * Wind River Systems
49 */
50
51/*
52 * The AX88172 provides USB ethernet supports at 10 and 100Mbps.
53 * It uses an external PHY (reference designs use a RealTek chip),
54 * and has a 64-bit multicast hash filter. There is some information
55 * missing from the manual which one needs to know in order to make
56 * the chip function:
57 *
58 * - You must set bit 7 in the RX control register, otherwise the
59 * chip won't receive any packets.
60 * - You must initialize all 3 IPG registers, or you won't be able
61 * to send any packets.
62 *
63 * Note that this device appears to only support loading the station
64 * address via autload from the EEPROM (i.e. there's no way to manaully
65 * set it).
66 *
67 * (Adam Weinberger wanted me to name this driver if_gir.c.)
68 */
69
70/*
71 * Ax88178 and Ax88772 support backported from the OpenBSD driver.
72 * 2007/02/12, J.R. Oldroyd, fbsd@opal.com
73 *
74 * Manual here:
75 * http://www.asix.com.tw/FrootAttach/datasheet/AX88178_datasheet_Rev10.pdf
76 * http://www.asix.com.tw/FrootAttach/datasheet/AX88772_datasheet_Rev10.pdf
77 */
78
79#include <sys/stdint.h>
80#include <sys/stddef.h>
81#include <sys/param.h>
82#include <sys/queue.h>
83#include <sys/types.h>
84#include <sys/systm.h>
85#include <sys/kernel.h>
86#include <sys/bus.h>
87#include <sys/module.h>
88#include <sys/lock.h>
89#include <sys/mutex.h>
90#include <sys/condvar.h>
91#include <sys/sysctl.h>
92#include <sys/sx.h>
93#include <sys/unistd.h>
94#include <sys/callout.h>
95#include <sys/malloc.h>
96#include <sys/priv.h>
97
98#include <dev/usb/usb.h>
99#include <dev/usb/usbdi.h>
100#include <dev/usb/usbdi_util.h>
101#include "usbdevs.h"
102
103#define USB_DEBUG_VAR axe_debug
104#include <dev/usb/usb_debug.h>
105#include <dev/usb/usb_process.h>
106
107#include <dev/usb/net/usb_ethernet.h>
108#include <dev/usb/net/if_axereg.h>
109
110/*
111 * AXE_178_MAX_FRAME_BURST
112 * max frame burst size for Ax88178 and Ax88772
113 * 0 2048 bytes
114 * 1 4096 bytes
115 * 2 8192 bytes
116 * 3 16384 bytes
117 * use the largest your system can handle without USB stalling.
118 *
119 * NB: 88772 parts appear to generate lots of input errors with
120 * a 2K rx buffer and 8K is only slightly faster than 4K on an
121 * EHCI port on a T42 so change at your own risk.
122 */
123#define AXE_178_MAX_FRAME_BURST 1
124
125#ifdef USB_DEBUG
126static int axe_debug = 0;
127
128SYSCTL_NODE(_hw_usb, OID_AUTO, axe, CTLFLAG_RW, 0, "USB axe");
129SYSCTL_INT(_hw_usb_axe, OID_AUTO, debug, CTLFLAG_RW, &axe_debug, 0,
130 "Debug level");
131#endif
132
133/*
134 * Various supported device vendors/products.
135 */
136static const STRUCT_USB_HOST_ID axe_devs[] = {
137#define AXE_DEV(v,p,i) { USB_VPI(USB_VENDOR_##v, USB_PRODUCT_##v##_##p, i) }
138 AXE_DEV(ABOCOM, UF200, 0),
139 AXE_DEV(ACERCM, EP1427X2, 0),
140 AXE_DEV(APPLE, ETHERNET, AXE_FLAG_772),
141 AXE_DEV(ASIX, AX88172, 0),
142 AXE_DEV(ASIX, AX88178, AXE_FLAG_178),
143 AXE_DEV(ASIX, AX88772, AXE_FLAG_772),
144 AXE_DEV(ASIX, AX88772A, AXE_FLAG_772A),
145 AXE_DEV(ASIX, AX88772B, AXE_FLAG_772B),
146 AXE_DEV(ATEN, UC210T, 0),
147 AXE_DEV(BELKIN, F5D5055, AXE_FLAG_178),
148 AXE_DEV(BILLIONTON, USB2AR, 0),
149 AXE_DEV(CISCOLINKSYS, USB200MV2, AXE_FLAG_772A),
150 AXE_DEV(COREGA, FETHER_USB2_TX, 0),
151 AXE_DEV(DLINK, DUBE100, 0),
152 AXE_DEV(DLINK, DUBE100B1, AXE_FLAG_772),
153 AXE_DEV(GOODWAY, GWUSB2E, 0),
154 AXE_DEV(IODATA, ETGUS2, AXE_FLAG_178),
155 AXE_DEV(JVC, MP_PRX1, 0),
156 AXE_DEV(LINKSYS2, USB200M, 0),
157 AXE_DEV(LINKSYS4, USB1000, AXE_FLAG_178),
158 AXE_DEV(LOGITEC, LAN_GTJU2A, AXE_FLAG_178),
159 AXE_DEV(MELCO, LUAU2KTX, 0),
160 AXE_DEV(MELCO, LUA3U2AGT, AXE_FLAG_178),
161 AXE_DEV(NETGEAR, FA120, 0),
162 AXE_DEV(OQO, ETHER01PLUS, AXE_FLAG_772),
163 AXE_DEV(PLANEX3, GU1000T, AXE_FLAG_178),
164 AXE_DEV(SITECOM, LN029, 0),
165 AXE_DEV(SITECOMEU, LN028, AXE_FLAG_178),
166 AXE_DEV(SYSTEMTALKS, SGCX2UL, 0),
167#undef AXE_DEV
168};
169
170static device_probe_t axe_probe;
171static device_attach_t axe_attach;
172static device_detach_t axe_detach;
173
174static usb_callback_t axe_bulk_read_callback;
175static usb_callback_t axe_bulk_write_callback;
176
177static miibus_readreg_t axe_miibus_readreg;
178static miibus_writereg_t axe_miibus_writereg;
179static miibus_statchg_t axe_miibus_statchg;
180
181static uether_fn_t axe_attach_post;
182static uether_fn_t axe_init;
183static uether_fn_t axe_stop;
184static uether_fn_t axe_start;
185static uether_fn_t axe_tick;
186static uether_fn_t axe_setmulti;
187static uether_fn_t axe_setpromisc;
188
189static int axe_ifmedia_upd(struct ifnet *);
190static void axe_ifmedia_sts(struct ifnet *, struct ifmediareq *);
191static int axe_cmd(struct axe_softc *, int, int, int, void *);
192static void axe_ax88178_init(struct axe_softc *);
193static void axe_ax88772_init(struct axe_softc *);
194static void axe_ax88772_phywake(struct axe_softc *);
195static void axe_ax88772a_init(struct axe_softc *);
196static void axe_ax88772b_init(struct axe_softc *);
197static int axe_get_phyno(struct axe_softc *, int);
198
199static const struct usb_config axe_config[AXE_N_TRANSFER] = {
200
201 [AXE_BULK_DT_WR] = {
202 .type = UE_BULK,
203 .endpoint = UE_ADDR_ANY,
204 .direction = UE_DIR_OUT,
205 .frames = 16,
206 .bufsize = 16 * MCLBYTES,
207 .flags = {.pipe_bof = 1,.force_short_xfer = 1,},
208 .callback = axe_bulk_write_callback,
209 .timeout = 10000, /* 10 seconds */
210 },
211
212 [AXE_BULK_DT_RD] = {
213 .type = UE_BULK,
214 .endpoint = UE_ADDR_ANY,
215 .direction = UE_DIR_IN,
216 .bufsize = 16384, /* bytes */
217 .flags = {.pipe_bof = 1,.short_xfer_ok = 1,},
218 .callback = axe_bulk_read_callback,
219 .timeout = 0, /* no timeout */
220 },
221};
222
223static const struct ax88772b_mfb ax88772b_mfb_table[] = {
224 { 0x8000, 0x8001, 2048 },
225 { 0x8100, 0x8147, 4096},
226 { 0x8200, 0x81EB, 6144},
227 { 0x8300, 0x83D7, 8192},
228 { 0x8400, 0x851E, 16384},
229 { 0x8500, 0x8666, 20480},
230 { 0x8600, 0x87AE, 24576},
231 { 0x8700, 0x8A3D, 32768}
232};
233
234static device_method_t axe_methods[] = {
235 /* Device interface */
236 DEVMETHOD(device_probe, axe_probe),
237 DEVMETHOD(device_attach, axe_attach),
238 DEVMETHOD(device_detach, axe_detach),
239
240 /* bus interface */
241 DEVMETHOD(bus_print_child, bus_generic_print_child),
242
243 /* MII interface */
244 DEVMETHOD(miibus_readreg, axe_miibus_readreg),
245 DEVMETHOD(miibus_writereg, axe_miibus_writereg),
246 DEVMETHOD(miibus_statchg, axe_miibus_statchg),
247
248 {0, 0}
249};
250
251static driver_t axe_driver = {
252 .name = "axe",
253 .methods = axe_methods,
254 .size = sizeof(struct axe_softc),
255};
256
257static devclass_t axe_devclass;
258
259DRIVER_MODULE(axe, uhub, axe_driver, axe_devclass, NULL, 0);
260DRIVER_MODULE(miibus, axe, miibus_driver, miibus_devclass, 0, 0);
261MODULE_DEPEND(axe, uether, 1, 1, 1);
262MODULE_DEPEND(axe, usb, 1, 1, 1);
263MODULE_DEPEND(axe, ether, 1, 1, 1);
264MODULE_DEPEND(axe, miibus, 1, 1, 1);
265MODULE_VERSION(axe, 1);
266
267static const struct usb_ether_methods axe_ue_methods = {
268 .ue_attach_post = axe_attach_post,
269 .ue_start = axe_start,
270 .ue_init = axe_init,
271 .ue_stop = axe_stop,
272 .ue_tick = axe_tick,
273 .ue_setmulti = axe_setmulti,
274 .ue_setpromisc = axe_setpromisc,
275 .ue_mii_upd = axe_ifmedia_upd,
276 .ue_mii_sts = axe_ifmedia_sts,
277};
278
279static int
280axe_cmd(struct axe_softc *sc, int cmd, int index, int val, void *buf)
281{
282 struct usb_device_request req;
283 usb_error_t err;
284
285 AXE_LOCK_ASSERT(sc, MA_OWNED);
286
287 req.bmRequestType = (AXE_CMD_IS_WRITE(cmd) ?
288 UT_WRITE_VENDOR_DEVICE :
289 UT_READ_VENDOR_DEVICE);
290 req.bRequest = AXE_CMD_CMD(cmd);
291 USETW(req.wValue, val);
292 USETW(req.wIndex, index);
293 USETW(req.wLength, AXE_CMD_LEN(cmd));
294
295 err = uether_do_request(&sc->sc_ue, &req, buf, 1000);
296
297 return (err);
298}
299
300static int
301axe_miibus_readreg(device_t dev, int phy, int reg)
302{
303 struct axe_softc *sc = device_get_softc(dev);
304 uint16_t val;
305 int locked;
306
307 if (sc->sc_phyno != phy)
308 return (0);
309
310 locked = mtx_owned(&sc->sc_mtx);
311 if (!locked)
312 AXE_LOCK(sc);
313
314 axe_cmd(sc, AXE_CMD_MII_OPMODE_SW, 0, 0, NULL);
315 axe_cmd(sc, AXE_CMD_MII_READ_REG, reg, phy, &val);
316 axe_cmd(sc, AXE_CMD_MII_OPMODE_HW, 0, 0, NULL);
317
318 val = le16toh(val);
319 if (AXE_IS_772(sc) && reg == MII_BMSR) {
320 /*
321 * BMSR of AX88772 indicates that it supports extended
322 * capability but the extended status register is
323 * revered for embedded ethernet PHY. So clear the
324 * extended capability bit of BMSR.
325 */
326 val &= ~BMSR_EXTCAP;
327 }
328
329 if (!locked)
330 AXE_UNLOCK(sc);
331 return (val);
332}
333
334static int
335axe_miibus_writereg(device_t dev, int phy, int reg, int val)
336{
337 struct axe_softc *sc = device_get_softc(dev);
338 int locked;
339
340 val = htole32(val);
341
342 if (sc->sc_phyno != phy)
343 return (0);
344
345 locked = mtx_owned(&sc->sc_mtx);
346 if (!locked)
347 AXE_LOCK(sc);
348
349 axe_cmd(sc, AXE_CMD_MII_OPMODE_SW, 0, 0, NULL);
350 axe_cmd(sc, AXE_CMD_MII_WRITE_REG, reg, phy, &val);
351 axe_cmd(sc, AXE_CMD_MII_OPMODE_HW, 0, 0, NULL);
352
353 if (!locked)
354 AXE_UNLOCK(sc);
355 return (0);
356}
357
358static void
359axe_miibus_statchg(device_t dev)
360{
361 struct axe_softc *sc = device_get_softc(dev);
362 struct mii_data *mii = GET_MII(sc);
363 struct ifnet *ifp;
364 uint16_t val;
365 int err, locked;
366
367 locked = mtx_owned(&sc->sc_mtx);
368 if (!locked)
369 AXE_LOCK(sc);
370
371 ifp = uether_getifp(&sc->sc_ue);
372 if (mii == NULL || ifp == NULL ||
373 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
374 goto done;
375
376 sc->sc_flags &= ~AXE_FLAG_LINK;
377 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
378 (IFM_ACTIVE | IFM_AVALID)) {
379 switch (IFM_SUBTYPE(mii->mii_media_active)) {
380 case IFM_10_T:
381 case IFM_100_TX:
382 sc->sc_flags |= AXE_FLAG_LINK;
383 break;
384 case IFM_1000_T:
385 if ((sc->sc_flags & AXE_FLAG_178) == 0)
386 break;
387 sc->sc_flags |= AXE_FLAG_LINK;
388 break;
389 default:
390 break;
391 }
392 }
393
394 /* Lost link, do nothing. */
395 if ((sc->sc_flags & AXE_FLAG_LINK) == 0)
396 goto done;
397
398 val = 0;
399 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0)
400 val |= AXE_MEDIA_FULL_DUPLEX;
401 if (AXE_IS_178_FAMILY(sc)) {
402 val |= AXE_178_MEDIA_RX_EN | AXE_178_MEDIA_MAGIC;
403 if ((sc->sc_flags & AXE_FLAG_178) != 0)
404 val |= AXE_178_MEDIA_ENCK;
405 switch (IFM_SUBTYPE(mii->mii_media_active)) {
406 case IFM_1000_T:
407 val |= AXE_178_MEDIA_GMII | AXE_178_MEDIA_ENCK;
408 break;
409 case IFM_100_TX:
410 val |= AXE_178_MEDIA_100TX;
411 break;
412 case IFM_10_T:
413 /* doesn't need to be handled */
414 break;
415 }
416 }
417 err = axe_cmd(sc, AXE_CMD_WRITE_MEDIA, 0, val, NULL);
418 if (err)
419 device_printf(dev, "media change failed, error %d\n", err);
420done:
421 if (!locked)
422 AXE_UNLOCK(sc);
423}
424
425/*
426 * Set media options.
427 */
428static int
429axe_ifmedia_upd(struct ifnet *ifp)
430{
431 struct axe_softc *sc = ifp->if_softc;
432 struct mii_data *mii = GET_MII(sc);
433 struct mii_softc *miisc;
434 int error;
435
436 AXE_LOCK_ASSERT(sc, MA_OWNED);
437
438 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
439 PHY_RESET(miisc);
440 error = mii_mediachg(mii);
441 return (error);
442}
443
444/*
445 * Report current media status.
446 */
447static void
448axe_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
449{
450 struct axe_softc *sc = ifp->if_softc;
451 struct mii_data *mii = GET_MII(sc);
452
453 AXE_LOCK(sc);
454 mii_pollstat(mii);
455 ifmr->ifm_active = mii->mii_media_active;
456 ifmr->ifm_status = mii->mii_media_status;
457 AXE_UNLOCK(sc);
458}
459
460static void
461axe_setmulti(struct usb_ether *ue)
462{
463 struct axe_softc *sc = uether_getsc(ue);
464 struct ifnet *ifp = uether_getifp(ue);
465 struct ifmultiaddr *ifma;
466 uint32_t h = 0;
467 uint16_t rxmode;
468 uint8_t hashtbl[8] = { 0, 0, 0, 0, 0, 0, 0, 0 };
469
470 AXE_LOCK_ASSERT(sc, MA_OWNED);
471
472 axe_cmd(sc, AXE_CMD_RXCTL_READ, 0, 0, &rxmode);
473 rxmode = le16toh(rxmode);
474
475 if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) {
476 rxmode |= AXE_RXCMD_ALLMULTI;
477 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL);
478 return;
479 }
480 rxmode &= ~AXE_RXCMD_ALLMULTI;
481
482 if_maddr_rlock(ifp);
483 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link)
484 {
485 if (ifma->ifma_addr->sa_family != AF_LINK)
486 continue;
487 h = ether_crc32_be(LLADDR((struct sockaddr_dl *)
488 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26;
489 hashtbl[h / 8] |= 1 << (h % 8);
490 }
491 if_maddr_runlock(ifp);
492
493 axe_cmd(sc, AXE_CMD_WRITE_MCAST, 0, 0, (void *)&hashtbl);
494 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL);
495}
496
497static int
498axe_get_phyno(struct axe_softc *sc, int sel)
499{
500 int phyno;
501
502 switch (AXE_PHY_TYPE(sc->sc_phyaddrs[sel])) {
503 case PHY_TYPE_100_HOME:
504 case PHY_TYPE_GIG:
505 phyno = AXE_PHY_NO(sc->sc_phyaddrs[sel]);
506 break;
507 case PHY_TYPE_SPECIAL:
508 /* FALLTHROUGH */
509 case PHY_TYPE_RSVD:
510 /* FALLTHROUGH */
511 case PHY_TYPE_NON_SUP:
512 /* FALLTHROUGH */
513 default:
514 phyno = -1;
515 break;
516 }
517
518 return (phyno);
519}
520
521#define AXE_GPIO_WRITE(x, y) do { \
522 axe_cmd(sc, AXE_CMD_WRITE_GPIO, 0, (x), NULL); \
523 uether_pause(ue, (y)); \
524} while (0)
525
526static void
527axe_ax88178_init(struct axe_softc *sc)
528{
529 struct usb_ether *ue;
530 int gpio0, ledmode, phymode;
531 uint16_t eeprom, val;
532
533 ue = &sc->sc_ue;
534 axe_cmd(sc, AXE_CMD_SROM_WR_ENABLE, 0, 0, NULL);
535 /* XXX magic */
536 axe_cmd(sc, AXE_CMD_SROM_READ, 0, 0x0017, &eeprom);
537 eeprom = le16toh(eeprom);
538 axe_cmd(sc, AXE_CMD_SROM_WR_DISABLE, 0, 0, NULL);
539
540 /* if EEPROM is invalid we have to use to GPIO0 */
541 if (eeprom == 0xffff) {
542 phymode = AXE_PHY_MODE_MARVELL;
543 gpio0 = 1;
544 ledmode = 0;
545 } else {
546 phymode = eeprom & 0x7f;
547 gpio0 = (eeprom & 0x80) ? 0 : 1;
548 ledmode = eeprom >> 8;
549 }
550
551 if (bootverbose)
552 device_printf(sc->sc_ue.ue_dev,
553 "EEPROM data : 0x%04x, phymode : 0x%02x\n", eeprom,
554 phymode);
555 /* Program GPIOs depending on PHY hardware. */
556 switch (phymode) {
557 case AXE_PHY_MODE_MARVELL:
558 if (gpio0 == 1) {
559 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO0_EN,
560 hz / 32);
561 AXE_GPIO_WRITE(AXE_GPIO0_EN | AXE_GPIO2 | AXE_GPIO2_EN,
562 hz / 32);
563 AXE_GPIO_WRITE(AXE_GPIO0_EN | AXE_GPIO2_EN, hz / 4);
564 AXE_GPIO_WRITE(AXE_GPIO0_EN | AXE_GPIO2 | AXE_GPIO2_EN,
565 hz / 32);
566 } else {
567 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO1 |
568 AXE_GPIO1_EN, hz / 3);
569 if (ledmode == 1) {
570 AXE_GPIO_WRITE(AXE_GPIO1_EN, hz / 3);
571 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN,
572 hz / 3);
573 } else {
574 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN |
575 AXE_GPIO2 | AXE_GPIO2_EN, hz / 32);
576 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN |
577 AXE_GPIO2_EN, hz / 4);
578 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN |
579 AXE_GPIO2 | AXE_GPIO2_EN, hz / 32);
580 }
581 }
582 break;
583 case AXE_PHY_MODE_CICADA:
584 case AXE_PHY_MODE_CICADA_V2:
585 case AXE_PHY_MODE_CICADA_V2_ASIX:
586 if (gpio0 == 1)
587 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO0 |
588 AXE_GPIO0_EN, hz / 32);
589 else
590 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO1 |
591 AXE_GPIO1_EN, hz / 32);
592 break;
593 case AXE_PHY_MODE_AGERE:
594 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO1 |
595 AXE_GPIO1_EN, hz / 32);
596 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | AXE_GPIO2 |
597 AXE_GPIO2_EN, hz / 32);
598 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | AXE_GPIO2_EN, hz / 4);
599 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | AXE_GPIO2 |
600 AXE_GPIO2_EN, hz / 32);
601 break;
602 case AXE_PHY_MODE_REALTEK_8211CL:
603 case AXE_PHY_MODE_REALTEK_8211BN:
604 case AXE_PHY_MODE_REALTEK_8251CL:
605 val = gpio0 == 1 ? AXE_GPIO0 | AXE_GPIO0_EN :
606 AXE_GPIO1 | AXE_GPIO1_EN;
607 AXE_GPIO_WRITE(val, hz / 32);
608 AXE_GPIO_WRITE(val | AXE_GPIO2 | AXE_GPIO2_EN, hz / 32);
609 AXE_GPIO_WRITE(val | AXE_GPIO2_EN, hz / 4);
610 AXE_GPIO_WRITE(val | AXE_GPIO2 | AXE_GPIO2_EN, hz / 32);
611 if (phymode == AXE_PHY_MODE_REALTEK_8211CL) {
612 axe_miibus_writereg(ue->ue_dev, sc->sc_phyno,
613 0x1F, 0x0005);
614 axe_miibus_writereg(ue->ue_dev, sc->sc_phyno,
615 0x0C, 0x0000);
616 val = axe_miibus_readreg(ue->ue_dev, sc->sc_phyno,
617 0x0001);
618 axe_miibus_writereg(ue->ue_dev, sc->sc_phyno,
619 0x01, val | 0x0080);
620 axe_miibus_writereg(ue->ue_dev, sc->sc_phyno,
621 0x1F, 0x0000);
622 }
623 break;
624 default:
625 /* Unknown PHY model or no need to program GPIOs. */
626 break;
627 }
628
629 /* soft reset */
630 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_CLEAR, NULL);
631 uether_pause(ue, hz / 4);
632
633 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0,
634 AXE_SW_RESET_PRL | AXE_178_RESET_MAGIC, NULL);
635 uether_pause(ue, hz / 4);
636 /* Enable MII/GMII/RGMII interface to work with external PHY. */
637 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, 0, NULL);
638 uether_pause(ue, hz / 4);
639
640 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL);
641}
642
643static void
644axe_ax88772_init(struct axe_softc *sc)
645{
646 axe_cmd(sc, AXE_CMD_WRITE_GPIO, 0, 0x00b0, NULL);
647 uether_pause(&sc->sc_ue, hz / 16);
648
649 if (sc->sc_phyno == AXE_772_PHY_NO_EPHY) {
650 /* ask for the embedded PHY */
651 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, 0x01, NULL);
652 uether_pause(&sc->sc_ue, hz / 64);
653
654 /* power down and reset state, pin reset state */
655 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0,
656 AXE_SW_RESET_CLEAR, NULL);
657 uether_pause(&sc->sc_ue, hz / 16);
658
659 /* power down/reset state, pin operating state */
660 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0,
661 AXE_SW_RESET_IPPD | AXE_SW_RESET_PRL, NULL);
662 uether_pause(&sc->sc_ue, hz / 4);
663
664 /* power up, reset */
665 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_PRL, NULL);
666
667 /* power up, operating */
668 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0,
669 AXE_SW_RESET_IPRL | AXE_SW_RESET_PRL, NULL);
670 } else {
671 /* ask for external PHY */
672 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, 0x00, NULL);
673 uether_pause(&sc->sc_ue, hz / 64);
674
675 /* power down internal PHY */
676 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0,
677 AXE_SW_RESET_IPPD | AXE_SW_RESET_PRL, NULL);
678 }
679
680 uether_pause(&sc->sc_ue, hz / 4);
681 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL);
682}
683
684static void
685axe_ax88772_phywake(struct axe_softc *sc)
686{
687 struct usb_ether *ue;
688
689 ue = &sc->sc_ue;
690 if (sc->sc_phyno == AXE_772_PHY_NO_EPHY) {
691 /* Manually select internal(embedded) PHY - MAC mode. */
692 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, AXE_SW_PHY_SELECT_SS_ENB |
693 AXE_SW_PHY_SELECT_EMBEDDED | AXE_SW_PHY_SELECT_SS_MII,
694 NULL);
695 uether_pause(&sc->sc_ue, hz / 32);
696 } else {
697 /*
698 * Manually select external PHY - MAC mode.
699 * Reverse MII/RMII is for AX88772A PHY mode.
700 */
701 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, AXE_SW_PHY_SELECT_SS_ENB |
702 AXE_SW_PHY_SELECT_EXT | AXE_SW_PHY_SELECT_SS_MII, NULL);
703 uether_pause(&sc->sc_ue, hz / 32);
704 }
705 /* Take PHY out of power down. */
706 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_IPPD |
707 AXE_SW_RESET_IPRL, NULL);
708 uether_pause(&sc->sc_ue, hz / 4);
709 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_IPRL, NULL);
710 uether_pause(&sc->sc_ue, hz);
711 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_CLEAR, NULL);
712 uether_pause(&sc->sc_ue, hz / 32);
713 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_IPRL, NULL);
714 uether_pause(&sc->sc_ue, hz / 32);
715}
716
717static void
718axe_ax88772a_init(struct axe_softc *sc)
719{
720 struct usb_ether *ue;
721
722 ue = &sc->sc_ue;
723 /* Reload EEPROM. */
724 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM, hz / 32);
725 axe_ax88772_phywake(sc);
726 /* Stop MAC. */
727 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL);
728}
729
730static void
731axe_ax88772b_init(struct axe_softc *sc)
732{
733 struct usb_ether *ue;
734 uint16_t eeprom;
735 uint8_t *eaddr;
736 int i;
737
738 ue = &sc->sc_ue;
739 /* Reload EEPROM. */
740 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM, hz / 32);
741 /*
742 * Save PHY power saving configuration(high byte) and
743 * clear EEPROM checksum value(low byte).
744 */
745 axe_cmd(sc, AXE_CMD_SROM_READ, 0, AXE_EEPROM_772B_PHY_PWRCFG, &eeprom);
746 sc->sc_pwrcfg = le16toh(eeprom) & 0xFF00;
747
748 /*
749 * Auto-loaded default station address from internal ROM is
750 * 00:00:00:00:00:00 such that an explicit access to EEPROM
751 * is required to get real station address.
752 */
753 eaddr = ue->ue_eaddr;
754 for (i = 0; i < ETHER_ADDR_LEN / 2; i++) {
755 axe_cmd(sc, AXE_CMD_SROM_READ, 0, AXE_EEPROM_772B_NODE_ID + i,
756 &eeprom);
757 eeprom = le16toh(eeprom);
758 *eaddr++ = (uint8_t)(eeprom & 0xFF);
759 *eaddr++ = (uint8_t)((eeprom >> 8) & 0xFF);
760 }
761 /* Wakeup PHY. */
762 axe_ax88772_phywake(sc);
763 /* Stop MAC. */
764 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL);
765}
766
767#undef AXE_GPIO_WRITE
768
769static void
770axe_reset(struct axe_softc *sc)
771{
772 struct usb_config_descriptor *cd;
773 usb_error_t err;
774
775 cd = usbd_get_config_descriptor(sc->sc_ue.ue_udev);
776
777 err = usbd_req_set_config(sc->sc_ue.ue_udev, &sc->sc_mtx,
778 cd->bConfigurationValue);
779 if (err)
780 DPRINTF("reset failed (ignored)\n");
781
782 /* Wait a little while for the chip to get its brains in order. */
783 uether_pause(&sc->sc_ue, hz / 100);
784
785 /* Reinitialize controller to achieve full reset. */
786 if (sc->sc_flags & AXE_FLAG_178)
787 axe_ax88178_init(sc);
788 else if (sc->sc_flags & AXE_FLAG_772)
789 axe_ax88772_init(sc);
790 else if (sc->sc_flags & AXE_FLAG_772A)
791 axe_ax88772a_init(sc);
792 else if (sc->sc_flags & AXE_FLAG_772B)
793 axe_ax88772b_init(sc);
794}
795
796static void
797axe_attach_post(struct usb_ether *ue)
798{
799 struct axe_softc *sc = uether_getsc(ue);
800
801 /*
802 * Load PHY indexes first. Needed by axe_xxx_init().
803 */
804 axe_cmd(sc, AXE_CMD_READ_PHYID, 0, 0, sc->sc_phyaddrs);
805 if (bootverbose)
806 device_printf(sc->sc_ue.ue_dev, "PHYADDR 0x%02x:0x%02x\n",
807 sc->sc_phyaddrs[0], sc->sc_phyaddrs[1]);
808 sc->sc_phyno = axe_get_phyno(sc, AXE_PHY_SEL_PRI);
809 if (sc->sc_phyno == -1)
810 sc->sc_phyno = axe_get_phyno(sc, AXE_PHY_SEL_SEC);
811 if (sc->sc_phyno == -1) {
812 device_printf(sc->sc_ue.ue_dev,
813 "no valid PHY address found, assuming PHY address 0\n");
814 sc->sc_phyno = 0;
815 }
816
817 /* Initialize controller and get station address. */
818 if (sc->sc_flags & AXE_FLAG_178) {
819 axe_ax88178_init(sc);
820 sc->sc_tx_bufsz = 16 * 1024;
821 axe_cmd(sc, AXE_178_CMD_READ_NODEID, 0, 0, ue->ue_eaddr);
822 } else if (sc->sc_flags & AXE_FLAG_772) {
823 axe_ax88772_init(sc);
824 sc->sc_tx_bufsz = 8 * 1024;
825 axe_cmd(sc, AXE_178_CMD_READ_NODEID, 0, 0, ue->ue_eaddr);
826 } else if (sc->sc_flags & AXE_FLAG_772A) {
827 axe_ax88772a_init(sc);
828 sc->sc_tx_bufsz = 8 * 1024;
829 axe_cmd(sc, AXE_178_CMD_READ_NODEID, 0, 0, ue->ue_eaddr);
830 } else if (sc->sc_flags & AXE_FLAG_772B) {
831 axe_ax88772b_init(sc);
832 sc->sc_tx_bufsz = 8 * 1024;
833 } else
834 axe_cmd(sc, AXE_172_CMD_READ_NODEID, 0, 0, ue->ue_eaddr);
835
836 /*
837 * Fetch IPG values.
838 */
839 if (sc->sc_flags & (AXE_FLAG_772A | AXE_FLAG_772B)) {
840 /* Set IPG values. */
841 sc->sc_ipgs[0] = 0x15;
842 sc->sc_ipgs[1] = 0x16;
843 sc->sc_ipgs[2] = 0x1A;
844 } else
845 axe_cmd(sc, AXE_CMD_READ_IPG012, 0, 0, sc->sc_ipgs);
846}
847
848/*
849 * Probe for a AX88172 chip.
850 */
851static int
852axe_probe(device_t dev)
853{
854 struct usb_attach_arg *uaa = device_get_ivars(dev);
855
856 if (uaa->usb_mode != USB_MODE_HOST)
857 return (ENXIO);
858 if (uaa->info.bConfigIndex != AXE_CONFIG_IDX)
859 return (ENXIO);
860 if (uaa->info.bIfaceIndex != AXE_IFACE_IDX)
861 return (ENXIO);
862
863 return (usbd_lookup_id_by_uaa(axe_devs, sizeof(axe_devs), uaa));
864}
865
866/*
867 * Attach the interface. Allocate softc structures, do ifmedia
868 * setup and ethernet/BPF attach.
869 */
870static int
871axe_attach(device_t dev)
872{
873 struct usb_attach_arg *uaa = device_get_ivars(dev);
874 struct axe_softc *sc = device_get_softc(dev);
875 struct usb_ether *ue = &sc->sc_ue;
876 uint8_t iface_index;
877 int error;
878
879 sc->sc_flags = USB_GET_DRIVER_INFO(uaa);
880
881 device_set_usb_desc(dev);
882
883 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), NULL, MTX_DEF);
884
885 iface_index = AXE_IFACE_IDX;
886 error = usbd_transfer_setup(uaa->device, &iface_index, sc->sc_xfer,
887 axe_config, AXE_N_TRANSFER, sc, &sc->sc_mtx);
888 if (error) {
889 device_printf(dev, "allocating USB transfers failed\n");
890 goto detach;
891 }
892
893 ue->ue_sc = sc;
894 ue->ue_dev = dev;
895 ue->ue_udev = uaa->device;
896 ue->ue_mtx = &sc->sc_mtx;
897 ue->ue_methods = &axe_ue_methods;
898
899 error = uether_ifattach(ue);
900 if (error) {
901 device_printf(dev, "could not attach interface\n");
902 goto detach;
903 }
904 return (0); /* success */
905
906detach:
907 axe_detach(dev);
908 return (ENXIO); /* failure */
909}
910
911static int
912axe_detach(device_t dev)
913{
914 struct axe_softc *sc = device_get_softc(dev);
915 struct usb_ether *ue = &sc->sc_ue;
916
917 usbd_transfer_unsetup(sc->sc_xfer, AXE_N_TRANSFER);
918 uether_ifdetach(ue);
919 mtx_destroy(&sc->sc_mtx);
920
921 return (0);
922}
923
924#if (AXE_BULK_BUF_SIZE >= 0x10000)
925#error "Please update axe_bulk_read_callback()!"
926#endif
927
928static void
929axe_bulk_read_callback(struct usb_xfer *xfer, usb_error_t error)
930{
931 struct axe_softc *sc = usbd_xfer_softc(xfer);
932 struct usb_ether *ue = &sc->sc_ue;
933 struct ifnet *ifp = uether_getifp(ue);
934 struct axe_sframe_hdr hdr;
935 struct usb_page_cache *pc;
936 int err, pos, len;
937 int actlen;
938
939 usbd_xfer_status(xfer, &actlen, NULL, NULL, NULL);
940
941 switch (USB_GET_STATE(xfer)) {
942 case USB_ST_TRANSFERRED:
943 pos = 0;
944 len = 0;
945 err = 0;
946
947 pc = usbd_xfer_get_frame(xfer, 0);
948 if (AXE_IS_178_FAMILY(sc)) {
949 while (pos < actlen) {
950 if ((pos + sizeof(hdr)) > actlen) {
951 /* too little data */
952 err = EINVAL;
953 break;
954 }
955 usbd_copy_out(pc, pos, &hdr, sizeof(hdr));
956
957 if ((hdr.len ^ hdr.ilen) != 0xFFFF) {
958 /* we lost sync */
959 err = EINVAL;
960 break;
961 }
962 pos += sizeof(hdr);
963
964 len = le16toh(hdr.len);
965 if ((pos + len) > actlen) {
966 /* invalid length */
967 err = EINVAL;
968 break;
969 }
970 uether_rxbuf(ue, pc, pos, len);
971
972 pos += len + (len % 2);
973 }
974 } else
975 uether_rxbuf(ue, pc, 0, actlen);
976
977 if (err != 0)
978 ifp->if_ierrors++;
979
980 /* FALLTHROUGH */
981 case USB_ST_SETUP:
982tr_setup:
983 usbd_xfer_set_frame_len(xfer, 0, usbd_xfer_max_len(xfer));
984 usbd_transfer_submit(xfer);
985 uether_rxflush(ue);
986 return;
987
988 default: /* Error */
989 DPRINTF("bulk read error, %s\n", usbd_errstr(error));
990
991 if (error != USB_ERR_CANCELLED) {
992 /* try to clear stall first */
993 usbd_xfer_set_stall(xfer);
994 goto tr_setup;
995 }
996 return;
997
998 }
999}
1000
1001#if ((AXE_BULK_BUF_SIZE >= 0x10000) || (AXE_BULK_BUF_SIZE < (MCLBYTES+4)))
1002#error "Please update axe_bulk_write_callback()!"
1003#endif
1004
1005static void
1006axe_bulk_write_callback(struct usb_xfer *xfer, usb_error_t error)
1007{
1008 struct axe_softc *sc = usbd_xfer_softc(xfer);
1009 struct axe_sframe_hdr hdr;
1010 struct ifnet *ifp = uether_getifp(&sc->sc_ue);
1011 struct usb_page_cache *pc;
1012 struct mbuf *m;
1013 int nframes, pos;
1014
1015 switch (USB_GET_STATE(xfer)) {
1016 case USB_ST_TRANSFERRED:
1017 DPRINTFN(11, "transfer complete\n");
1018 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1019 /* FALLTHROUGH */
1020 case USB_ST_SETUP:
1021tr_setup:
1022 if ((sc->sc_flags & AXE_FLAG_LINK) == 0 ||
1023 (ifp->if_drv_flags & IFF_DRV_OACTIVE) != 0) {
1024 /*
1025 * Don't send anything if there is no link or
1026 * controller is busy.
1027 */
1028 return;
1029 }
1030
1031 for (nframes = 0; nframes < 16 &&
1032 !IFQ_DRV_IS_EMPTY(&ifp->if_snd); nframes++) {
1033 IFQ_DRV_DEQUEUE(&ifp->if_snd, m);
1034 if (m == NULL)
1035 break;
1036 usbd_xfer_set_frame_offset(xfer, nframes * MCLBYTES,
1037 nframes);
1038 pos = 0;
1039 pc = usbd_xfer_get_frame(xfer, nframes);
1040 if (AXE_IS_178_FAMILY(sc)) {
1041 hdr.len = htole16(m->m_pkthdr.len);
1042 hdr.ilen = ~hdr.len;
1043 usbd_copy_in(pc, pos, &hdr, sizeof(hdr));
1044 pos += sizeof(hdr);
1045 usbd_m_copy_in(pc, pos, m, 0, m->m_pkthdr.len);
1046 pos += m->m_pkthdr.len;
1047 if ((pos % 512) == 0) {
1048 hdr.len = 0;
1049 hdr.ilen = 0xffff;
1050 usbd_copy_in(pc, pos, &hdr,
1051 sizeof(hdr));
1052 pos += sizeof(hdr);
1053 }
1054 } else {
1055 usbd_m_copy_in(pc, pos, m, 0, m->m_pkthdr.len);
1056 pos += m->m_pkthdr.len;
1057 }
1058
1059 /*
1060 * XXX
1061 * Update TX packet counter here. This is not
1062 * correct way but it seems that there is no way
1063 * to know how many packets are sent at the end
1064 * of transfer because controller combines
1065 * multiple writes into single one if there is
1066 * room in TX buffer of controller.
1067 */
1068 ifp->if_opackets++;
1069
1070 /*
1071 * if there's a BPF listener, bounce a copy
1072 * of this frame to him:
1073 */
1074 BPF_MTAP(ifp, m);
1075
1076 m_freem(m);
1077
1078 /* Set frame length. */
1079 usbd_xfer_set_frame_len(xfer, nframes, pos);
1080 }
1081 if (nframes != 0) {
1082 usbd_xfer_set_frames(xfer, nframes);
1083 usbd_transfer_submit(xfer);
1084 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1085 }
1086 return;
1087 /* NOTREACHED */
1088 default: /* Error */
1089 DPRINTFN(11, "transfer error, %s\n",
1090 usbd_errstr(error));
1091
1092 ifp->if_oerrors++;
1093 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1094
1095 if (error != USB_ERR_CANCELLED) {
1096 /* try to clear stall first */
1097 usbd_xfer_set_stall(xfer);
1098 goto tr_setup;
1099 }
1100 return;
1101
1102 }
1103}
1104
1105static void
1106axe_tick(struct usb_ether *ue)
1107{
1108 struct axe_softc *sc = uether_getsc(ue);
1109 struct mii_data *mii = GET_MII(sc);
1110
1111 AXE_LOCK_ASSERT(sc, MA_OWNED);
1112
1113 mii_tick(mii);
1114 if ((sc->sc_flags & AXE_FLAG_LINK) == 0) {
1115 axe_miibus_statchg(ue->ue_dev);
1116 if ((sc->sc_flags & AXE_FLAG_LINK) != 0)
1117 axe_start(ue);
1118 }
1119}
1120
1121static void
1122axe_start(struct usb_ether *ue)
1123{
1124 struct axe_softc *sc = uether_getsc(ue);
1125
1126 /*
1127 * start the USB transfers, if not already started:
1128 */
1129 usbd_transfer_start(sc->sc_xfer[AXE_BULK_DT_RD]);
1130 usbd_transfer_start(sc->sc_xfer[AXE_BULK_DT_WR]);
1131}
1132
1133static void
1134axe_init(struct usb_ether *ue)
1135{
1136 struct axe_softc *sc = uether_getsc(ue);
1137 struct ifnet *ifp = uether_getifp(ue);
1138 uint16_t rxmode;
1139
1140 AXE_LOCK_ASSERT(sc, MA_OWNED);
1141
1142 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
1143 return;
1144
1145 /* Cancel pending I/O */
1146 axe_stop(ue);
1147
1148 axe_reset(sc);
1149
1150 /* Set MAC address. */
1151 if (AXE_IS_178_FAMILY(sc))
1152 axe_cmd(sc, AXE_178_CMD_WRITE_NODEID, 0, 0, IF_LLADDR(ifp));
1153 else
1154 axe_cmd(sc, AXE_172_CMD_WRITE_NODEID, 0, 0, IF_LLADDR(ifp));
1155
1156 /* Set transmitter IPG values */
1157 if (AXE_IS_178_FAMILY(sc))
1158 axe_cmd(sc, AXE_178_CMD_WRITE_IPG012, sc->sc_ipgs[2],
1159 (sc->sc_ipgs[1] << 8) | (sc->sc_ipgs[0]), NULL);
1160 else {
1161 axe_cmd(sc, AXE_172_CMD_WRITE_IPG0, 0, sc->sc_ipgs[0], NULL);
1162 axe_cmd(sc, AXE_172_CMD_WRITE_IPG1, 0, sc->sc_ipgs[1], NULL);
1163 axe_cmd(sc, AXE_172_CMD_WRITE_IPG2, 0, sc->sc_ipgs[2], NULL);
1164 }
1165
1166 /* AX88772B uses different maximum frame burst configuration. */
1167 if (sc->sc_flags & AXE_FLAG_772B)
1168 axe_cmd(sc, AXE_772B_CMD_RXCTL_WRITE_CFG,
1169 ax88772b_mfb_table[AX88772B_MFB_16K].threshold,
1170 ax88772b_mfb_table[AX88772B_MFB_16K].byte_cnt, NULL);
1171
1172 /* Enable receiver, set RX mode. */
1173 rxmode = (AXE_RXCMD_MULTICAST | AXE_RXCMD_ENABLE);
1174 if (AXE_IS_178_FAMILY(sc)) {
1175 if (sc->sc_flags & AXE_FLAG_772B) {
1176 /*
1177 * Select RX header format type 1. Aligning IP
1178 * header on 4 byte boundary is not needed
1179 * because we always copy the received frame in
1180 * RX handler.
1181 */
1182 rxmode |= AXE_772B_RXCMD_HDR_TYPE_1;
1183 } else {
1184 /*
1185 * Default Rx buffer size is too small to get
1186 * maximum performance.
1187 */
1188 rxmode |= AXE_178_RXCMD_MFB_16384;
1189 }
1190 } else {
1191 rxmode |= AXE_172_RXCMD_UNICAST;
1192 }
1193
1194 /* If we want promiscuous mode, set the allframes bit. */
1195 if (ifp->if_flags & IFF_PROMISC)
1196 rxmode |= AXE_RXCMD_PROMISC;
1197
1198 if (ifp->if_flags & IFF_BROADCAST)
1199 rxmode |= AXE_RXCMD_BROADCAST;
1200
1201 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL);
1202
1203 /* Load the multicast filter. */
1204 axe_setmulti(ue);
1205
1206 usbd_xfer_set_stall(sc->sc_xfer[AXE_BULK_DT_WR]);
1207
1208 ifp->if_drv_flags |= IFF_DRV_RUNNING;
1209 /* Switch to selected media. */
1210 axe_ifmedia_upd(ifp);
1211 axe_start(ue);
1212}
1213
1214static void
1215axe_setpromisc(struct usb_ether *ue)
1216{
1217 struct axe_softc *sc = uether_getsc(ue);
1218 struct ifnet *ifp = uether_getifp(ue);
1219 uint16_t rxmode;
1220
1221 axe_cmd(sc, AXE_CMD_RXCTL_READ, 0, 0, &rxmode);
1222
1223 rxmode = le16toh(rxmode);
1224
1225 if (ifp->if_flags & IFF_PROMISC) {
1226 rxmode |= AXE_RXCMD_PROMISC;
1227 } else {
1228 rxmode &= ~AXE_RXCMD_PROMISC;
1229 }
1230
1231 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL);
1232
1233 axe_setmulti(ue);
1234}
1235
1236static void
1237axe_stop(struct usb_ether *ue)
1238{
1239 struct axe_softc *sc = uether_getsc(ue);
1240 struct ifnet *ifp = uether_getifp(ue);
1241
1242 AXE_LOCK_ASSERT(sc, MA_OWNED);
1243
1244 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
1245 sc->sc_flags &= ~AXE_FLAG_LINK;
1246
1247 /*
1248 * stop all the transfers, if not already stopped:
1249 */
1250 usbd_transfer_stop(sc->sc_xfer[AXE_BULK_DT_WR]);
1251 usbd_transfer_stop(sc->sc_xfer[AXE_BULK_DT_RD]);
1252}