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if_auereg.h (192984) if_auereg.h (194228)
1/*-
2 * Copyright (c) 1997, 1998, 1999
3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

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24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
31 *
1/*-
2 * Copyright (c) 1997, 1998, 1999
3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

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24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 * $FreeBSD: head/sys/dev/usb/net/if_auereg.h 192984 2009-05-28 17:36:36Z thompsa $
32 * $FreeBSD: head/sys/dev/usb/net/if_auereg.h 194228 2009-06-15 01:02:43Z thompsa $
33 */
34
35/*
36 * Register definitions for ADMtek Pegasus AN986 USB to Ethernet
37 * chip. The Pegasus uses a total of four USB endpoints: the control
38 * endpoint (0), a bulk read endpoint for receiving packets (1),
39 * a bulk write endpoint for sending packets (2) and an interrupt
40 * endpoint for passing RX and TX status (3). Endpoint 0 is used

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50#define AUE_UR_WRITEREG 0xF1
51
52#define AUE_CONFIG_INDEX 0 /* config number 1 */
53#define AUE_IFACE_IDX 0
54
55/*
56 * Note that while the ADMtek technically has four endpoints, the control
57 * endpoint (endpoint 0) is regarded as special by the USB code and drivers
33 */
34
35/*
36 * Register definitions for ADMtek Pegasus AN986 USB to Ethernet
37 * chip. The Pegasus uses a total of four USB endpoints: the control
38 * endpoint (0), a bulk read endpoint for receiving packets (1),
39 * a bulk write endpoint for sending packets (2) and an interrupt
40 * endpoint for passing RX and TX status (3). Endpoint 0 is used

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50#define AUE_UR_WRITEREG 0xF1
51
52#define AUE_CONFIG_INDEX 0 /* config number 1 */
53#define AUE_IFACE_IDX 0
54
55/*
56 * Note that while the ADMtek technically has four endpoints, the control
57 * endpoint (endpoint 0) is regarded as special by the USB code and drivers
58 * don't have direct access to it (we access it using usb2_do_request()
58 * don't have direct access to it (we access it using usbd_do_request()
59 * when reading/writing registers. Consequently, our endpoint indexes
60 * don't match those in the ADMtek Pegasus manual: we consider the RX data
61 * endpoint to be index 0 and work up from there.
62 */
63enum {
64 AUE_BULK_DT_WR,
65 AUE_BULK_DT_RD,
66 AUE_INTR_DT_RD,

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178
179#define AUE_RXSTAT_MCAST 0x01
180#define AUE_RXSTAT_GIANT 0x02
181#define AUE_RXSTAT_RUNT 0x04
182#define AUE_RXSTAT_CRCERR 0x08
183#define AUE_RXSTAT_DRIBBLE 0x10
184#define AUE_RXSTAT_MASK 0x1E
185
59 * when reading/writing registers. Consequently, our endpoint indexes
60 * don't match those in the ADMtek Pegasus manual: we consider the RX data
61 * endpoint to be index 0 and work up from there.
62 */
63enum {
64 AUE_BULK_DT_WR,
65 AUE_BULK_DT_RD,
66 AUE_INTR_DT_RD,

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178
179#define AUE_RXSTAT_MCAST 0x01
180#define AUE_RXSTAT_GIANT 0x02
181#define AUE_RXSTAT_RUNT 0x04
182#define AUE_RXSTAT_CRCERR 0x08
183#define AUE_RXSTAT_DRIBBLE 0x10
184#define AUE_RXSTAT_MASK 0x1E
185
186#define GET_MII(sc) usb2_ether_getmii(&(sc)->sc_ue)
186#define GET_MII(sc) uether_getmii(&(sc)->sc_ue)
187
188struct aue_intrpkt {
189 uint8_t aue_txstat0;
190 uint8_t aue_txstat1;
191 uint8_t aue_rxstat;
192 uint8_t aue_rxlostpkt0;
193 uint8_t aue_rxlostpkt1;
194 uint8_t aue_wakeupstat;

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187
188struct aue_intrpkt {
189 uint8_t aue_txstat0;
190 uint8_t aue_txstat1;
191 uint8_t aue_rxstat;
192 uint8_t aue_rxlostpkt0;
193 uint8_t aue_rxlostpkt1;
194 uint8_t aue_wakeupstat;

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