| uhci.h (196219) | uhci.h (198151) |
|---|---|
| 1/* $FreeBSD: head/sys/dev/usb/controller/uhci.h 196219 2009-08-14 20:03:53Z jhb $ */ | 1/* $FreeBSD: head/sys/dev/usb/controller/uhci.h 198151 2009-10-15 20:07:08Z thompsa $ */ |
| 2/*- 3 * Copyright (c) 1998 The NetBSD Foundation, Inc. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to The NetBSD Foundation 7 * by Lennart Augustsson (lennart@augustsson.net) at 8 * Carlstedt Research & Technology. 9 * --- 26 unchanged lines hidden (view full) --- 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39#ifndef _UHCI_H_ 40#define _UHCI_H_ 41 42#define UHCI_MAX_DEVICES MIN(USB_MAX_DEVICES, 128) 43 | 2/*- 3 * Copyright (c) 1998 The NetBSD Foundation, Inc. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to The NetBSD Foundation 7 * by Lennart Augustsson (lennart@augustsson.net) at 8 * Carlstedt Research & Technology. 9 * --- 26 unchanged lines hidden (view full) --- 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39#ifndef _UHCI_H_ 40#define _UHCI_H_ 41 42#define UHCI_MAX_DEVICES MIN(USB_MAX_DEVICES, 128) 43 |
| 44/* PCI config registers */ 45#define PCI_USBREV 0x60 /* USB protocol revision */ 46#define PCI_USB_REV_MASK 0xff 47#define PCI_USB_REV_PRE_1_0 0x00 48#define PCI_USB_REV_1_0 0x10 49#define PCI_USB_REV_1_1 0x11 50#define PCI_LEGSUP 0xc0 /* Legacy Support register */ 51#define PCI_LEGSUP_USBPIRQDEN 0x2000 /* USB PIRQ D Enable */ 52#define PCI_CBIO 0x20 /* configuration base IO */ 53#define PCI_INTERFACE_UHCI 0x00 54 55/* UHCI registers */ 56#define UHCI_CMD 0x00 57#define UHCI_CMD_RS 0x0001 58#define UHCI_CMD_HCRESET 0x0002 59#define UHCI_CMD_GRESET 0x0004 60#define UHCI_CMD_EGSM 0x0008 61#define UHCI_CMD_FGR 0x0010 62#define UHCI_CMD_SWDBG 0x0020 63#define UHCI_CMD_CF 0x0040 64#define UHCI_CMD_MAXP 0x0080 65#define UHCI_STS 0x02 66#define UHCI_STS_USBINT 0x0001 67#define UHCI_STS_USBEI 0x0002 68#define UHCI_STS_RD 0x0004 69#define UHCI_STS_HSE 0x0008 70#define UHCI_STS_HCPE 0x0010 71#define UHCI_STS_HCH 0x0020 72#define UHCI_STS_ALLINTRS 0x003f 73#define UHCI_INTR 0x04 74#define UHCI_INTR_TOCRCIE 0x0001 75#define UHCI_INTR_RIE 0x0002 76#define UHCI_INTR_IOCE 0x0004 77#define UHCI_INTR_SPIE 0x0008 78#define UHCI_FRNUM 0x06 79#define UHCI_FRNUM_MASK 0x03ff 80#define UHCI_FLBASEADDR 0x08 81#define UHCI_SOF 0x0c 82#define UHCI_SOF_MASK 0x7f 83#define UHCI_PORTSC1 0x010 84#define UHCI_PORTSC2 0x012 85#define UHCI_PORTSC_CCS 0x0001 86#define UHCI_PORTSC_CSC 0x0002 87#define UHCI_PORTSC_PE 0x0004 88#define UHCI_PORTSC_POEDC 0x0008 89#define UHCI_PORTSC_LS 0x0030 90#define UHCI_PORTSC_LS_SHIFT 4 91#define UHCI_PORTSC_RD 0x0040 92#define UHCI_PORTSC_LSDA 0x0100 93#define UHCI_PORTSC_PR 0x0200 94#define UHCI_PORTSC_OCI 0x0400 95#define UHCI_PORTSC_OCIC 0x0800 96#define UHCI_PORTSC_SUSP 0x1000 97 98#define URWMASK(x) ((x) & (UHCI_PORTSC_SUSP | \ 99 UHCI_PORTSC_PR | UHCI_PORTSC_RD | \ 100 UHCI_PORTSC_PE)) 101 | |
| 102#define UHCI_FRAMELIST_COUNT 1024 /* units */ 103#define UHCI_FRAMELIST_ALIGN 4096 /* bytes */ 104 105/* Structures alignment (bytes) */ 106#define UHCI_TD_ALIGN 16 107#define UHCI_QH_ALIGN 16 108 109#if ((USB_PAGE_SIZE < UHCI_TD_ALIGN) || (UHCI_TD_ALIGN == 0) || \ 110 (USB_PAGE_SIZE < UHCI_QH_ALIGN) || (UHCI_QH_ALIGN == 0)) 111#error "Invalid USB page size!" 112#endif 113 114typedef uint32_t uhci_physaddr_t; 115 116#define UHCI_PTR_T 0x00000001 117#define UHCI_PTR_TD 0x00000000 118#define UHCI_PTR_QH 0x00000002 119#define UHCI_PTR_VF 0x00000004 120 | 44#define UHCI_FRAMELIST_COUNT 1024 /* units */ 45#define UHCI_FRAMELIST_ALIGN 4096 /* bytes */ 46 47/* Structures alignment (bytes) */ 48#define UHCI_TD_ALIGN 16 49#define UHCI_QH_ALIGN 16 50 51#if ((USB_PAGE_SIZE < UHCI_TD_ALIGN) || (UHCI_TD_ALIGN == 0) || \ 52 (USB_PAGE_SIZE < UHCI_QH_ALIGN) || (UHCI_QH_ALIGN == 0)) 53#error "Invalid USB page size!" 54#endif 55 56typedef uint32_t uhci_physaddr_t; 57 58#define UHCI_PTR_T 0x00000001 59#define UHCI_PTR_TD 0x00000000 60#define UHCI_PTR_QH 0x00000002 61#define UHCI_PTR_VF 0x00000004 62 |
| 121#define UHCI_QH_REMOVE_DELAY 5 /* us - QH remove delay */ 122 | |
| 123/* 124 * The Queue Heads (QH) and Transfer Descriptors (TD) are accessed by 125 * both the CPU and the USB-controller which run concurrently. Great 126 * care must be taken. When the data-structures are linked into the 127 * USB controller's frame list, the USB-controller "owns" the 128 * td_status and qh_elink fields, which will not be written by the 129 * CPU. 130 * --- 190 unchanged lines hidden --- | 63/* 64 * The Queue Heads (QH) and Transfer Descriptors (TD) are accessed by 65 * both the CPU and the USB-controller which run concurrently. Great 66 * care must be taken. When the data-structures are linked into the 67 * USB controller's frame list, the USB-controller "owns" the 68 * td_status and qh_elink fields, which will not be written by the 69 * CPU. 70 * --- 190 unchanged lines hidden --- |