1/*- 2 * Copyright (c) 2008 Hans Petter Selasky. All rights reserved. 3 * Copyright (c) 1998 The NetBSD Foundation, Inc. All rights reserved. 4 * Copyright (c) 1998 Lennart Augustsson. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28#include <sys/cdefs.h>
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29__FBSDID("$FreeBSD: head/sys/dev/usb2/controller/uhci2.c 184610 2008-11-04 02:31:03Z alfred $");
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29__FBSDID("$FreeBSD: head/sys/dev/usb2/controller/uhci2.c 184824 2008-11-10 20:54:31Z thompsa $"); |
30 31/* 32 * USB Universal Host Controller driver. 33 * Handles e.g. PIIX3 and PIIX4. 34 * 35 * UHCI spec: http://developer.intel.com/design/USB/UHCI11D.htm 36 * USB spec: http://www.usb.org/developers/docs/usbspec.zip 37 * PIIXn spec: ftp://download.intel.com/design/intarch/datashts/29055002.pdf 38 * ftp://download.intel.com/design/intarch/datashts/29056201.pdf 39 */ 40 41#include <dev/usb2/include/usb2_standard.h> 42#include <dev/usb2/include/usb2_mfunc.h> 43#include <dev/usb2/include/usb2_error.h> 44#include <dev/usb2/include/usb2_defs.h> 45 46#define USB_DEBUG_VAR uhcidebug 47#define usb2_config_td_cc uhci_config_copy 48#define usb2_config_td_softc uhci_softc 49 50#include <dev/usb2/core/usb2_core.h> 51#include <dev/usb2/core/usb2_debug.h> 52#include <dev/usb2/core/usb2_busdma.h> 53#include <dev/usb2/core/usb2_process.h> 54#include <dev/usb2/core/usb2_config_td.h> 55#include <dev/usb2/core/usb2_sw_transfer.h> 56#include <dev/usb2/core/usb2_transfer.h> 57#include <dev/usb2/core/usb2_device.h> 58#include <dev/usb2/core/usb2_hub.h> 59#include <dev/usb2/core/usb2_util.h> 60 61#include <dev/usb2/controller/usb2_controller.h> 62#include <dev/usb2/controller/usb2_bus.h> 63#include <dev/usb2/controller/uhci2.h> 64 65#define alt_next next 66#define UHCI_BUS2SC(bus) ((uhci_softc_t *)(((uint8_t *)(bus)) - \ 67 USB_P2U(&(((uhci_softc_t *)0)->sc_bus)))) 68 69#if USB_DEBUG 70static int uhcidebug = 0; 71static int uhcinoloop = 0; 72 73SYSCTL_NODE(_hw_usb2, OID_AUTO, uhci, CTLFLAG_RW, 0, "USB uhci"); 74SYSCTL_INT(_hw_usb2_uhci, OID_AUTO, debug, CTLFLAG_RW, 75 &uhcidebug, 0, "uhci debug level"); 76SYSCTL_INT(_hw_usb2_uhci, OID_AUTO, loop, CTLFLAG_RW, 77 &uhcinoloop, 0, "uhci noloop"); 78static void uhci_dumpregs(uhci_softc_t *sc); 79static void uhci_dump_tds(uhci_td_t *td); 80 81#endif 82 83#define UBARR(sc) bus_space_barrier((sc)->sc_io_tag, (sc)->sc_io_hdl, 0, (sc)->sc_io_size, \ 84 BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE) 85#define UWRITE1(sc, r, x) \ 86 do { UBARR(sc); bus_space_write_1((sc)->sc_io_tag, (sc)->sc_io_hdl, (r), (x)); \ 87 } while (/*CONSTCOND*/0) 88#define UWRITE2(sc, r, x) \ 89 do { UBARR(sc); bus_space_write_2((sc)->sc_io_tag, (sc)->sc_io_hdl, (r), (x)); \ 90 } while (/*CONSTCOND*/0) 91#define UWRITE4(sc, r, x) \ 92 do { UBARR(sc); bus_space_write_4((sc)->sc_io_tag, (sc)->sc_io_hdl, (r), (x)); \ 93 } while (/*CONSTCOND*/0) 94#define UREAD1(sc, r) (UBARR(sc), bus_space_read_1((sc)->sc_io_tag, (sc)->sc_io_hdl, (r))) 95#define UREAD2(sc, r) (UBARR(sc), bus_space_read_2((sc)->sc_io_tag, (sc)->sc_io_hdl, (r))) 96#define UREAD4(sc, r) (UBARR(sc), bus_space_read_4((sc)->sc_io_tag, (sc)->sc_io_hdl, (r))) 97 98#define UHCICMD(sc, cmd) UWRITE2(sc, UHCI_CMD, cmd) 99#define UHCISTS(sc) UREAD2(sc, UHCI_STS) 100 101#define UHCI_RESET_TIMEOUT 100 /* ms, reset timeout */ 102 103#define UHCI_INTR_ENDPT 1 104 105struct uhci_mem_layout { 106 107 struct usb2_page_search buf_res; 108 struct usb2_page_search fix_res; 109 110 struct usb2_page_cache *buf_pc; 111 struct usb2_page_cache *fix_pc; 112 113 uint32_t buf_offset; 114 115 uint16_t max_frame_size; 116}; 117 118struct uhci_std_temp { 119 120 struct uhci_mem_layout ml; 121 uhci_td_t *td; 122 uhci_td_t *td_next; 123 uint32_t average; 124 uint32_t td_status; 125 uint32_t td_token; 126 uint32_t len; 127 uint16_t max_frame_size; 128 uint8_t shortpkt; 129 uint8_t setup_alt_next; 130 uint8_t short_frames_ok; 131}; 132 133extern struct usb2_bus_methods uhci_bus_methods; 134extern struct usb2_pipe_methods uhci_device_bulk_methods; 135extern struct usb2_pipe_methods uhci_device_ctrl_methods; 136extern struct usb2_pipe_methods uhci_device_intr_methods; 137extern struct usb2_pipe_methods uhci_device_isoc_methods; 138extern struct usb2_pipe_methods uhci_root_ctrl_methods; 139extern struct usb2_pipe_methods uhci_root_intr_methods; 140 141static usb2_config_td_command_t uhci_root_ctrl_task; 142static void uhci_root_ctrl_poll(struct uhci_softc *sc); 143static void uhci_do_poll(struct usb2_bus *bus); 144static void uhci_device_done(struct usb2_xfer *xfer, usb2_error_t error); 145static void uhci_transfer_intr_enqueue(struct usb2_xfer *xfer); 146static void uhci_root_intr_check(void *arg); 147static void uhci_timeout(void *arg); 148static uint8_t uhci_check_transfer(struct usb2_xfer *xfer); 149 150void 151uhci_iterate_hw_softc(struct usb2_bus *bus, usb2_bus_mem_sub_cb_t *cb) 152{ 153 struct uhci_softc *sc = UHCI_BUS2SC(bus); 154 uint32_t i; 155 156 cb(bus, &sc->sc_hw.pframes_pc, &sc->sc_hw.pframes_pg, 157 sizeof(uint32_t) * UHCI_FRAMELIST_COUNT, UHCI_FRAMELIST_ALIGN); 158 159 cb(bus, &sc->sc_hw.ls_ctl_start_pc, &sc->sc_hw.ls_ctl_start_pg, 160 sizeof(uhci_qh_t), UHCI_QH_ALIGN); 161 162 cb(bus, &sc->sc_hw.fs_ctl_start_pc, &sc->sc_hw.fs_ctl_start_pg, 163 sizeof(uhci_qh_t), UHCI_QH_ALIGN); 164 165 cb(bus, &sc->sc_hw.bulk_start_pc, &sc->sc_hw.bulk_start_pg, 166 sizeof(uhci_qh_t), UHCI_QH_ALIGN); 167 168 cb(bus, &sc->sc_hw.last_qh_pc, &sc->sc_hw.last_qh_pg, 169 sizeof(uhci_qh_t), UHCI_QH_ALIGN); 170 171 cb(bus, &sc->sc_hw.last_td_pc, &sc->sc_hw.last_td_pg, 172 sizeof(uhci_td_t), UHCI_TD_ALIGN); 173 174 for (i = 0; i != UHCI_VFRAMELIST_COUNT; i++) { 175 cb(bus, sc->sc_hw.isoc_start_pc + i, 176 sc->sc_hw.isoc_start_pg + i, 177 sizeof(uhci_td_t), UHCI_TD_ALIGN); 178 } 179 180 for (i = 0; i != UHCI_IFRAMELIST_COUNT; i++) { 181 cb(bus, sc->sc_hw.intr_start_pc + i, 182 sc->sc_hw.intr_start_pg + i, 183 sizeof(uhci_qh_t), UHCI_QH_ALIGN); 184 } 185 return; 186} 187 188static void 189uhci_mem_layout_init(struct uhci_mem_layout *ml, struct usb2_xfer *xfer) 190{ 191 ml->buf_pc = xfer->frbuffers + 0; 192 ml->fix_pc = xfer->buf_fixup; 193 194 ml->buf_offset = 0; 195 196 ml->max_frame_size = xfer->max_frame_size; 197 198 return; 199} 200 201static void 202uhci_mem_layout_fixup(struct uhci_mem_layout *ml, struct uhci_td *td) 203{ 204 usb2_get_page(ml->buf_pc, ml->buf_offset, &ml->buf_res); 205 206 if (ml->buf_res.length < td->len) { 207 208 /* need to do a fixup */ 209 210 usb2_get_page(ml->fix_pc, 0, &ml->fix_res); 211 212 td->td_buffer = htole32(ml->fix_res.physaddr); 213 214 /* 215 * The UHCI driver cannot handle 216 * page crossings, so a fixup is 217 * needed: 218 * 219 * +----+----+ - - - 220 * | YYY|Y | 221 * +----+----+ - - - 222 * \ \ 223 * \ \ 224 * +----+ 225 * |YYYY| (fixup) 226 * +----+ 227 */ 228 229 if ((td->td_token & htole32(UHCI_TD_PID)) == 230 htole32(UHCI_TD_PID_IN)) { 231 td->fix_pc = ml->fix_pc; 232 usb2_pc_cpu_invalidate(ml->fix_pc); 233 234 } else { 235 td->fix_pc = NULL; 236 237 /* copy data to fixup location */ 238 239 usb2_copy_out(ml->buf_pc, ml->buf_offset, 240 ml->fix_res.buffer, td->len); 241 242 usb2_pc_cpu_flush(ml->fix_pc); 243 } 244 245 /* prepare next fixup */ 246 247 ml->fix_pc++; 248 249 } else { 250 251 td->td_buffer = htole32(ml->buf_res.physaddr); 252 td->fix_pc = NULL; 253 } 254 255 /* prepare next data location */ 256 257 ml->buf_offset += td->len; 258 259 return; 260} 261 262void 263uhci_reset(uhci_softc_t *sc) 264{ 265 struct usb2_page_search buf_res; 266 uint16_t n; 267
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268 mtx_assert(&sc->sc_bus.mtx, MA_OWNED);
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268 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); |
269 270 DPRINTF("resetting the HC\n"); 271 272 /* disable interrupts */ 273 274 UWRITE2(sc, UHCI_INTR, 0); 275 276 /* global reset */ 277 278 UHCICMD(sc, UHCI_CMD_GRESET); 279 280 /* wait */ 281
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282 usb2_pause_mtx(&sc->sc_bus.mtx,
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282 usb2_pause_mtx(&sc->sc_bus.bus_mtx, |
283 USB_BUS_RESET_DELAY); 284 285 /* terminate all transfers */ 286 287 UHCICMD(sc, UHCI_CMD_HCRESET); 288 289 /* the reset bit goes low when the controller is done */ 290 291 n = UHCI_RESET_TIMEOUT; 292 while (n--) { 293 /* wait one millisecond */ 294
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295 usb2_pause_mtx(&sc->sc_bus.mtx, 1);
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295 usb2_pause_mtx(&sc->sc_bus.bus_mtx, 1); |
296 297 if (!(UREAD2(sc, UHCI_CMD) & UHCI_CMD_HCRESET)) { 298 goto done_1; 299 } 300 } 301 302 device_printf(sc->sc_bus.bdev, 303 "controller did not reset\n"); 304 305done_1: 306 307 n = 10; 308 while (n--) { 309 /* wait one millisecond */ 310
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311 usb2_pause_mtx(&sc->sc_bus.mtx, 1);
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311 usb2_pause_mtx(&sc->sc_bus.bus_mtx, 1); |
312 313 /* check if HC is stopped */ 314 if (UREAD2(sc, UHCI_STS) & UHCI_STS_HCH) { 315 goto done_2; 316 } 317 } 318 319 device_printf(sc->sc_bus.bdev, 320 "controller did not stop\n"); 321 322done_2: 323 324 /* reload the configuration */ 325 usb2_get_page(&sc->sc_hw.pframes_pc, 0, &buf_res); 326 UWRITE4(sc, UHCI_FLBASEADDR, buf_res.physaddr); 327 UWRITE2(sc, UHCI_FRNUM, sc->sc_saved_frnum); 328 UWRITE1(sc, UHCI_SOF, sc->sc_saved_sof); 329 return; 330} 331 332static void 333uhci_start(uhci_softc_t *sc) 334{
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335 mtx_assert(&sc->sc_bus.mtx, MA_OWNED);
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335 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); |
336 337 DPRINTFN(2, "enabling\n"); 338 339 /* enable interrupts */ 340 341 UWRITE2(sc, UHCI_INTR, 342 (UHCI_INTR_TOCRCIE | 343 UHCI_INTR_RIE | 344 UHCI_INTR_IOCE | 345 UHCI_INTR_SPIE)); 346 347 /* 348 * assume 64 byte packets at frame end and start HC controller 349 */ 350 351 UHCICMD(sc, (UHCI_CMD_MAXP | UHCI_CMD_RS)); 352 353 uint8_t n = 10; 354 355 while (n--) { 356 /* wait one millisecond */ 357
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358 usb2_pause_mtx(&sc->sc_bus.mtx, 1);
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358 usb2_pause_mtx(&sc->sc_bus.bus_mtx, 1); |
359 360 /* check that controller has started */ 361 362 if (!(UREAD2(sc, UHCI_STS) & UHCI_STS_HCH)) { 363 goto done; 364 } 365 } 366 367 device_printf(sc->sc_bus.bdev, 368 "cannot start HC controller\n"); 369 370done: 371 return; 372} 373 374static struct uhci_qh * 375uhci_init_qh(struct usb2_page_cache *pc) 376{ 377 struct usb2_page_search buf_res; 378 struct uhci_qh *qh; 379 380 usb2_get_page(pc, 0, &buf_res); 381 382 qh = buf_res.buffer; 383 384 qh->qh_self = 385 htole32(buf_res.physaddr) | 386 htole32(UHCI_PTR_QH); 387 388 qh->page_cache = pc; 389 390 return (qh); 391} 392 393static struct uhci_td * 394uhci_init_td(struct usb2_page_cache *pc) 395{ 396 struct usb2_page_search buf_res; 397 struct uhci_td *td; 398 399 usb2_get_page(pc, 0, &buf_res); 400 401 td = buf_res.buffer; 402 403 td->td_self = 404 htole32(buf_res.physaddr) | 405 htole32(UHCI_PTR_TD); 406 407 td->page_cache = pc; 408 409 return (td); 410} 411 412usb2_error_t 413uhci_init(uhci_softc_t *sc) 414{ 415 uint16_t bit; 416 uint16_t x; 417 uint16_t y; 418
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419 mtx_lock(&sc->sc_bus.mtx);
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419 USB_BUS_LOCK(&sc->sc_bus); |
420 421 DPRINTF("start\n"); 422 423#if USB_DEBUG 424 if (uhcidebug > 2) { 425 uhci_dumpregs(sc); 426 } 427#endif 428 429 sc->sc_saved_sof = 0x40; /* default value */ 430 sc->sc_saved_frnum = 0; /* default frame number */ 431 432 /* 433 * Setup QH's 434 */ 435 sc->sc_ls_ctl_p_last = 436 uhci_init_qh(&sc->sc_hw.ls_ctl_start_pc); 437 438 sc->sc_fs_ctl_p_last = 439 uhci_init_qh(&sc->sc_hw.fs_ctl_start_pc); 440 441 sc->sc_bulk_p_last = 442 uhci_init_qh(&sc->sc_hw.bulk_start_pc); 443#if 0 444 sc->sc_reclaim_qh_p = 445 sc->sc_fs_ctl_p_last; 446#else 447 /* setup reclaim looping point */ 448 sc->sc_reclaim_qh_p = 449 sc->sc_bulk_p_last; 450#endif 451 452 sc->sc_last_qh_p = 453 uhci_init_qh(&sc->sc_hw.last_qh_pc); 454 455 sc->sc_last_td_p = 456 uhci_init_td(&sc->sc_hw.last_td_pc); 457 458 for (x = 0; x != UHCI_VFRAMELIST_COUNT; x++) { 459 sc->sc_isoc_p_last[x] = 460 uhci_init_td(sc->sc_hw.isoc_start_pc + x); 461 } 462 463 for (x = 0; x != UHCI_IFRAMELIST_COUNT; x++) { 464 sc->sc_intr_p_last[x] = 465 uhci_init_qh(sc->sc_hw.intr_start_pc + x); 466 } 467 468 /* 469 * the QHs are arranged to give poll intervals that are 470 * powers of 2 times 1ms 471 */ 472 bit = UHCI_IFRAMELIST_COUNT / 2; 473 while (bit) { 474 x = bit; 475 while (x & bit) { 476 uhci_qh_t *qh_x; 477 uhci_qh_t *qh_y; 478 479 y = (x ^ bit) | (bit / 2); 480 481 /* 482 * the next QH has half the poll interval 483 */ 484 qh_x = sc->sc_intr_p_last[x]; 485 qh_y = sc->sc_intr_p_last[y]; 486 487 qh_x->h_next = NULL; 488 qh_x->qh_h_next = qh_y->qh_self; 489 qh_x->e_next = NULL; 490 qh_x->qh_e_next = htole32(UHCI_PTR_T); 491 x++; 492 } 493 bit >>= 1; 494 } 495 496 if (1) { 497 uhci_qh_t *qh_ls; 498 uhci_qh_t *qh_intr; 499 500 qh_ls = sc->sc_ls_ctl_p_last; 501 qh_intr = sc->sc_intr_p_last[0]; 502 503 /* start QH for interrupt traffic */ 504 qh_intr->h_next = qh_ls; 505 qh_intr->qh_h_next = qh_ls->qh_self; 506 qh_intr->e_next = 0; 507 qh_intr->qh_e_next = htole32(UHCI_PTR_T); 508 } 509 for (x = 0; x != UHCI_VFRAMELIST_COUNT; x++) { 510 511 uhci_td_t *td_x; 512 uhci_qh_t *qh_intr; 513 514 td_x = sc->sc_isoc_p_last[x]; 515 qh_intr = sc->sc_intr_p_last[x | (UHCI_IFRAMELIST_COUNT / 2)]; 516 517 /* start TD for isochronous traffic */ 518 td_x->next = NULL; 519 td_x->td_next = qh_intr->qh_self; 520 td_x->td_status = htole32(UHCI_TD_IOS); 521 td_x->td_token = htole32(0); 522 td_x->td_buffer = htole32(0); 523 } 524 525 if (1) { 526 uhci_qh_t *qh_ls; 527 uhci_qh_t *qh_fs; 528 529 qh_ls = sc->sc_ls_ctl_p_last; 530 qh_fs = sc->sc_fs_ctl_p_last; 531 532 /* start QH where low speed control traffic will be queued */ 533 qh_ls->h_next = qh_fs; 534 qh_ls->qh_h_next = qh_fs->qh_self; 535 qh_ls->e_next = 0; 536 qh_ls->qh_e_next = htole32(UHCI_PTR_T); 537 } 538 if (1) { 539 uhci_qh_t *qh_ctl; 540 uhci_qh_t *qh_blk; 541 uhci_qh_t *qh_lst; 542 uhci_td_t *td_lst; 543 544 qh_ctl = sc->sc_fs_ctl_p_last; 545 qh_blk = sc->sc_bulk_p_last; 546 547 /* start QH where full speed control traffic will be queued */ 548 qh_ctl->h_next = qh_blk; 549 qh_ctl->qh_h_next = qh_blk->qh_self; 550 qh_ctl->e_next = 0; 551 qh_ctl->qh_e_next = htole32(UHCI_PTR_T); 552 553 qh_lst = sc->sc_last_qh_p; 554 555 /* start QH where bulk traffic will be queued */ 556 qh_blk->h_next = qh_lst; 557 qh_blk->qh_h_next = qh_lst->qh_self; 558 qh_blk->e_next = 0; 559 qh_blk->qh_e_next = htole32(UHCI_PTR_T); 560 561 td_lst = sc->sc_last_td_p; 562 563 /* end QH which is used for looping the QHs */ 564 qh_lst->h_next = 0; 565 qh_lst->qh_h_next = htole32(UHCI_PTR_T); /* end of QH chain */ 566 qh_lst->e_next = td_lst; 567 qh_lst->qh_e_next = td_lst->td_self; 568 569 /* 570 * end TD which hangs from the last QH, to avoid a bug in the PIIX 571 * that makes it run berserk otherwise 572 */ 573 td_lst->next = 0; 574 td_lst->td_next = htole32(UHCI_PTR_T); 575 td_lst->td_status = htole32(0); /* inactive */ 576 td_lst->td_token = htole32(0); 577 td_lst->td_buffer = htole32(0); 578 } 579 if (1) { 580 struct usb2_page_search buf_res; 581 uint32_t *pframes; 582 583 usb2_get_page(&sc->sc_hw.pframes_pc, 0, &buf_res); 584 585 pframes = buf_res.buffer; 586 587 588 /* 589 * Setup UHCI framelist 590 * 591 * Execution order: 592 * 593 * pframes -> full speed isochronous -> interrupt QH's -> low 594 * speed control -> full speed control -> bulk transfers 595 * 596 */ 597 598 for (x = 0; x != UHCI_FRAMELIST_COUNT; x++) { 599 pframes[x] = 600 sc->sc_isoc_p_last[x % UHCI_VFRAMELIST_COUNT]->td_self; 601 } 602 } 603 /* flush all cache into memory */ 604 605 usb2_bus_mem_flush_all(&sc->sc_bus, &uhci_iterate_hw_softc); 606 607 /* set up the bus struct */ 608 sc->sc_bus.methods = &uhci_bus_methods; 609 610 /* reset the controller */ 611 uhci_reset(sc); 612 613 /* start the controller */ 614 uhci_start(sc); 615
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616 mtx_unlock(&sc->sc_bus.mtx);
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616 USB_BUS_UNLOCK(&sc->sc_bus); |
617 618 /* catch lost interrupts */ 619 uhci_do_poll(&sc->sc_bus); 620 621 return (0); 622} 623 624/* NOTE: suspend/resume is called from 625 * interrupt context and cannot sleep! 626 */ 627 628void 629uhci_suspend(uhci_softc_t *sc) 630{
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631 mtx_lock(&sc->sc_bus.mtx);
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631 USB_BUS_LOCK(&sc->sc_bus); |
632 633#if USB_DEBUG 634 if (uhcidebug > 2) { 635 uhci_dumpregs(sc); 636 } 637#endif 638 /* save some state if BIOS doesn't */ 639 640 sc->sc_saved_frnum = UREAD2(sc, UHCI_FRNUM); 641 sc->sc_saved_sof = UREAD1(sc, UHCI_SOF); 642 643 /* stop the controller */ 644 645 uhci_reset(sc); 646 647 /* enter global suspend */ 648 649 UHCICMD(sc, UHCI_CMD_EGSM); 650
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651 usb2_pause_mtx(&sc->sc_bus.mtx, USB_RESUME_WAIT);
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651 usb2_pause_mtx(&sc->sc_bus.bus_mtx, USB_RESUME_WAIT); |
652
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653 mtx_unlock(&sc->sc_bus.mtx);
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653 USB_BUS_UNLOCK(&sc->sc_bus); |
654 return; 655} 656 657void 658uhci_resume(uhci_softc_t *sc) 659{
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660 mtx_lock(&sc->sc_bus.mtx);
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660 USB_BUS_LOCK(&sc->sc_bus); |
661 662 /* reset the controller */ 663 664 uhci_reset(sc); 665 666 /* force global resume */ 667 668 UHCICMD(sc, UHCI_CMD_FGR); 669
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670 usb2_pause_mtx(&sc->sc_bus.mtx,
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670 usb2_pause_mtx(&sc->sc_bus.bus_mtx, |
671 USB_RESUME_DELAY); 672 673 /* and start traffic again */ 674 675 uhci_start(sc); 676 677#if USB_DEBUG 678 if (uhcidebug > 2) { 679 uhci_dumpregs(sc); 680 } 681#endif 682
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683 mtx_unlock(&sc->sc_bus.mtx);
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683 USB_BUS_UNLOCK(&sc->sc_bus); |
684 685 /* catch lost interrupts */ 686 uhci_do_poll(&sc->sc_bus); 687 688 return; 689} 690 691#if USB_DEBUG 692static void 693uhci_dumpregs(uhci_softc_t *sc) 694{ 695 DPRINTFN(0, "%s regs: cmd=%04x, sts=%04x, intr=%04x, frnum=%04x, " 696 "flbase=%08x, sof=%04x, portsc1=%04x, portsc2=%04x\n", 697 device_get_nameunit(sc->sc_bus.bdev), 698 UREAD2(sc, UHCI_CMD), 699 UREAD2(sc, UHCI_STS), 700 UREAD2(sc, UHCI_INTR), 701 UREAD2(sc, UHCI_FRNUM), 702 UREAD4(sc, UHCI_FLBASEADDR), 703 UREAD1(sc, UHCI_SOF), 704 UREAD2(sc, UHCI_PORTSC1), 705 UREAD2(sc, UHCI_PORTSC2)); 706 return; 707} 708 709static uint8_t 710uhci_dump_td(uhci_td_t *p) 711{ 712 uint32_t td_next; 713 uint32_t td_status; 714 uint32_t td_token; 715 uint8_t temp; 716 717 usb2_pc_cpu_invalidate(p->page_cache); 718 719 td_next = le32toh(p->td_next); 720 td_status = le32toh(p->td_status); 721 td_token = le32toh(p->td_token); 722 723 /* 724 * Check whether the link pointer in this TD marks the link pointer 725 * as end of queue: 726 */ 727 temp = ((td_next & UHCI_PTR_T) || (td_next == 0)); 728 729 printf("TD(%p) at 0x%08x = link=0x%08x status=0x%08x " 730 "token=0x%08x buffer=0x%08x\n", 731 p, 732 le32toh(p->td_self), 733 td_next, 734 td_status, 735 td_token, 736 le32toh(p->td_buffer)); 737 738 printf("TD(%p) td_next=%s%s%s td_status=%s%s%s%s%s%s%s%s%s%s%s, errcnt=%d, actlen=%d pid=%02x," 739 "addr=%d,endpt=%d,D=%d,maxlen=%d\n", 740 p, 741 (td_next & 1) ? "-T" : "", 742 (td_next & 2) ? "-Q" : "", 743 (td_next & 4) ? "-VF" : "", 744 (td_status & UHCI_TD_BITSTUFF) ? "-BITSTUFF" : "", 745 (td_status & UHCI_TD_CRCTO) ? "-CRCTO" : "", 746 (td_status & UHCI_TD_NAK) ? "-NAK" : "", 747 (td_status & UHCI_TD_BABBLE) ? "-BABBLE" : "", 748 (td_status & UHCI_TD_DBUFFER) ? "-DBUFFER" : "", 749 (td_status & UHCI_TD_STALLED) ? "-STALLED" : "", 750 (td_status & UHCI_TD_ACTIVE) ? "-ACTIVE" : "", 751 (td_status & UHCI_TD_IOC) ? "-IOC" : "", 752 (td_status & UHCI_TD_IOS) ? "-IOS" : "", 753 (td_status & UHCI_TD_LS) ? "-LS" : "", 754 (td_status & UHCI_TD_SPD) ? "-SPD" : "", 755 UHCI_TD_GET_ERRCNT(td_status), 756 UHCI_TD_GET_ACTLEN(td_status), 757 UHCI_TD_GET_PID(td_token), 758 UHCI_TD_GET_DEVADDR(td_token), 759 UHCI_TD_GET_ENDPT(td_token), 760 UHCI_TD_GET_DT(td_token), 761 UHCI_TD_GET_MAXLEN(td_token)); 762 763 return (temp); 764} 765 766static uint8_t 767uhci_dump_qh(uhci_qh_t *sqh) 768{ 769 uint8_t temp; 770 uint32_t qh_h_next; 771 uint32_t qh_e_next; 772 773 usb2_pc_cpu_invalidate(sqh->page_cache); 774 775 qh_h_next = le32toh(sqh->qh_h_next); 776 qh_e_next = le32toh(sqh->qh_e_next); 777 778 DPRINTFN(0, "QH(%p) at 0x%08x: h_next=0x%08x e_next=0x%08x\n", sqh, 779 le32toh(sqh->qh_self), qh_h_next, qh_e_next); 780 781 temp = ((((sqh->h_next != NULL) && !(qh_h_next & UHCI_PTR_T)) ? 1 : 0) | 782 (((sqh->e_next != NULL) && !(qh_e_next & UHCI_PTR_T)) ? 2 : 0)); 783 784 return (temp); 785} 786 787static void 788uhci_dump_all(uhci_softc_t *sc) 789{ 790 uhci_dumpregs(sc); 791 uhci_dump_qh(sc->sc_ls_ctl_p_last); 792 uhci_dump_qh(sc->sc_fs_ctl_p_last); 793 uhci_dump_qh(sc->sc_bulk_p_last); 794 uhci_dump_qh(sc->sc_last_qh_p); 795 return; 796} 797 798static void 799uhci_dump_qhs(uhci_qh_t *sqh) 800{ 801 uint8_t temp; 802 803 temp = uhci_dump_qh(sqh); 804 805 /* 806 * uhci_dump_qhs displays all the QHs and TDs from the given QH 807 * onwards Traverses sideways first, then down. 808 * 809 * QH1 QH2 No QH TD2.1 TD2.2 TD1.1 etc. 810 * 811 * TD2.x being the TDs queued at QH2 and QH1 being referenced from QH1. 812 */ 813 814 if (temp & 1) 815 uhci_dump_qhs(sqh->h_next); 816 else 817 DPRINTF("No QH\n"); 818 819 if (temp & 2) 820 uhci_dump_tds(sqh->e_next); 821 else 822 DPRINTF("No TD\n"); 823 824 return; 825} 826 827static void 828uhci_dump_tds(uhci_td_t *td) 829{ 830 for (; 831 td != NULL; 832 td = td->obj_next) { 833 if (uhci_dump_td(td)) { 834 break; 835 } 836 } 837 return; 838} 839 840#endif 841 842/* 843 * Let the last QH loop back to the full speed control transfer QH. 844 * This is what intel calls "bandwidth reclamation" and improves 845 * USB performance a lot for some devices. 846 * If we are already looping, just count it. 847 */ 848static void 849uhci_add_loop(uhci_softc_t *sc) 850{ 851 struct uhci_qh *qh_lst; 852 struct uhci_qh *qh_rec; 853 854#if USB_DEBUG 855 if (uhcinoloop) { 856 return; 857 } 858#endif 859 if (++(sc->sc_loops) == 1) { 860 DPRINTFN(6, "add\n"); 861 862 qh_lst = sc->sc_last_qh_p; 863 qh_rec = sc->sc_reclaim_qh_p; 864 865 /* NOTE: we don't loop back the soft pointer */ 866 867 qh_lst->qh_h_next = qh_rec->qh_self; 868 usb2_pc_cpu_flush(qh_lst->page_cache); 869 } 870 return; 871} 872 873static void 874uhci_rem_loop(uhci_softc_t *sc) 875{ 876 struct uhci_qh *qh_lst; 877 878#if USB_DEBUG 879 if (uhcinoloop) { 880 return; 881 } 882#endif 883 if (--(sc->sc_loops) == 0) { 884 DPRINTFN(6, "remove\n"); 885 886 qh_lst = sc->sc_last_qh_p; 887 qh_lst->qh_h_next = htole32(UHCI_PTR_T); 888 usb2_pc_cpu_flush(qh_lst->page_cache); 889 } 890 return; 891} 892 893static void 894uhci_transfer_intr_enqueue(struct usb2_xfer *xfer) 895{ 896 /* check for early completion */ 897 if (uhci_check_transfer(xfer)) { 898 return; 899 } 900 /* put transfer on interrupt queue */ 901 usb2_transfer_enqueue(&xfer->udev->bus->intr_q, xfer); 902 903 /* start timeout, if any */ 904 if (xfer->timeout != 0) { 905 usb2_transfer_timeout_ms(xfer, &uhci_timeout, xfer->timeout); 906 } 907 return; 908} 909 910#define UHCI_APPEND_TD(std,last) (last) = _uhci_append_td(std,last) 911static uhci_td_t * 912_uhci_append_td(uhci_td_t *std, uhci_td_t *last) 913{ 914 DPRINTFN(11, "%p to %p\n", std, last); 915 916 /* (sc->sc_bus.mtx) must be locked */ 917 918 std->next = last->next; 919 std->td_next = last->td_next; 920 921 std->prev = last; 922 923 usb2_pc_cpu_flush(std->page_cache); 924 925 /* 926 * the last->next->prev is never followed: std->next->prev = std; 927 */ 928 last->next = std; 929 last->td_next = std->td_self; 930 931 usb2_pc_cpu_flush(last->page_cache); 932 933 return (std); 934} 935 936#define UHCI_APPEND_QH(sqh,td,last) (last) = _uhci_append_qh(sqh,td,last) 937static uhci_qh_t * 938_uhci_append_qh(uhci_qh_t *sqh, uhci_td_t *td, uhci_qh_t *last) 939{ 940 DPRINTFN(11, "%p to %p\n", sqh, last); 941 942 /* (sc->sc_bus.mtx) must be locked */ 943 944 sqh->e_next = td; 945 sqh->qh_e_next = td->td_self; 946 947 sqh->h_next = last->h_next; 948 sqh->qh_h_next = last->qh_h_next; 949 950 sqh->h_prev = last; 951 952 usb2_pc_cpu_flush(sqh->page_cache); 953 954 /* 955 * The "last->h_next->h_prev" is never followed: 956 * 957 * "sqh->h_next->h_prev" = sqh; 958 */ 959 960 last->h_next = sqh; 961 last->qh_h_next = sqh->qh_self; 962 963 usb2_pc_cpu_flush(last->page_cache); 964 965 return (sqh); 966} 967 968/**/ 969 970#define UHCI_REMOVE_TD(std,last) (last) = _uhci_remove_td(std,last) 971static uhci_td_t * 972_uhci_remove_td(uhci_td_t *std, uhci_td_t *last) 973{ 974 DPRINTFN(11, "%p from %p\n", std, last); 975 976 /* (sc->sc_bus.mtx) must be locked */ 977 978 std->prev->next = std->next; 979 std->prev->td_next = std->td_next; 980 981 usb2_pc_cpu_flush(std->prev->page_cache); 982 983 if (std->next) { 984 std->next->prev = std->prev; 985 usb2_pc_cpu_flush(std->next->page_cache); 986 } 987 return ((last == std) ? std->prev : last); 988} 989 990#define UHCI_REMOVE_QH(sqh,last) (last) = _uhci_remove_qh(sqh,last) 991static uhci_qh_t * 992_uhci_remove_qh(uhci_qh_t *sqh, uhci_qh_t *last) 993{ 994 DPRINTFN(11, "%p from %p\n", sqh, last); 995 996 /* (sc->sc_bus.mtx) must be locked */ 997 998 /* only remove if not removed from a queue */ 999 if (sqh->h_prev) { 1000 1001 sqh->h_prev->h_next = sqh->h_next; 1002 sqh->h_prev->qh_h_next = sqh->qh_h_next; 1003 1004 usb2_pc_cpu_flush(sqh->h_prev->page_cache); 1005 1006 if (sqh->h_next) { 1007 sqh->h_next->h_prev = sqh->h_prev; 1008 usb2_pc_cpu_flush(sqh->h_next->page_cache); 1009 } 1010 /* 1011 * set the Terminate-bit in the e_next of the QH, in case 1012 * the transferred packet was short so that the QH still 1013 * points at the last used TD 1014 */ 1015 sqh->qh_e_next = htole32(UHCI_PTR_T); 1016 1017 last = ((last == sqh) ? sqh->h_prev : last); 1018 1019 sqh->h_prev = 0; 1020 1021 usb2_pc_cpu_flush(sqh->page_cache); 1022 } 1023 return (last); 1024} 1025 1026static void 1027uhci_isoc_done(uhci_softc_t *sc, struct usb2_xfer *xfer) 1028{ 1029 struct usb2_page_search res; 1030 uint32_t nframes = xfer->nframes; 1031 uint32_t status; 1032 uint32_t offset = 0; 1033 uint32_t *plen = xfer->frlengths; 1034 uint16_t len = 0; 1035 uhci_td_t *td = xfer->td_transfer_first; 1036 uhci_td_t **pp_last = &sc->sc_isoc_p_last[xfer->qh_pos]; 1037 1038 DPRINTFN(13, "xfer=%p pipe=%p transfer done\n", 1039 xfer, xfer->pipe); 1040 1041 /* sync any DMA memory before doing fixups */ 1042 1043 usb2_bdma_post_sync(xfer); 1044 1045 while (nframes--) { 1046 if (td == NULL) { 1047 panic("%s:%d: out of TD's\n", 1048 __FUNCTION__, __LINE__); 1049 } 1050 if (pp_last >= &sc->sc_isoc_p_last[UHCI_VFRAMELIST_COUNT]) { 1051 pp_last = &sc->sc_isoc_p_last[0]; 1052 } 1053#if USB_DEBUG 1054 if (uhcidebug > 5) { 1055 DPRINTF("isoc TD\n"); 1056 uhci_dump_td(td); 1057 } 1058#endif 1059 usb2_pc_cpu_invalidate(td->page_cache); 1060 status = le32toh(td->td_status); 1061 1062 len = UHCI_TD_GET_ACTLEN(status); 1063 1064 if (len > *plen) { 1065 len = *plen; 1066 } 1067 if (td->fix_pc) { 1068 1069 usb2_get_page(td->fix_pc, 0, &res); 1070 1071 /* copy data from fixup location to real location */ 1072 1073 usb2_pc_cpu_invalidate(td->fix_pc); 1074 1075 usb2_copy_in(xfer->frbuffers, offset, 1076 res.buffer, len); 1077 } 1078 offset += *plen; 1079 1080 *plen = len; 1081 1082 /* remove TD from schedule */ 1083 UHCI_REMOVE_TD(td, *pp_last); 1084 1085 pp_last++; 1086 plen++; 1087 td = td->obj_next; 1088 } 1089 1090 xfer->aframes = xfer->nframes; 1091 1092 return; 1093} 1094 1095static usb2_error_t 1096uhci_non_isoc_done_sub(struct usb2_xfer *xfer) 1097{ 1098 struct usb2_page_search res; 1099 uhci_td_t *td; 1100 uhci_td_t *td_alt_next; 1101 uint32_t status; 1102 uint32_t token; 1103 uint16_t len; 1104 1105 td = xfer->td_transfer_cache; 1106 td_alt_next = td->alt_next; 1107 1108 if (xfer->aframes != xfer->nframes) { 1109 xfer->frlengths[xfer->aframes] = 0; 1110 } 1111 while (1) { 1112 1113 usb2_pc_cpu_invalidate(td->page_cache); 1114 status = le32toh(td->td_status); 1115 token = le32toh(td->td_token); 1116 1117 /* 1118 * Verify the status and add 1119 * up the actual length: 1120 */ 1121 1122 len = UHCI_TD_GET_ACTLEN(status); 1123 if (len > td->len) { 1124 /* should not happen */ 1125 DPRINTF("Invalid status length, " 1126 "0x%04x/0x%04x bytes\n", len, td->len); 1127 status |= UHCI_TD_STALLED; 1128 1129 } else if ((xfer->aframes != xfer->nframes) && (len > 0)) { 1130 1131 if (td->fix_pc) { 1132 1133 usb2_get_page(td->fix_pc, 0, &res); 1134 1135 /* 1136 * copy data from fixup location to real 1137 * location 1138 */ 1139 1140 usb2_pc_cpu_invalidate(td->fix_pc); 1141 1142 usb2_copy_in(xfer->frbuffers + xfer->aframes, 1143 xfer->frlengths[xfer->aframes], res.buffer, len); 1144 } 1145 /* update actual length */ 1146 1147 xfer->frlengths[xfer->aframes] += len; 1148 } 1149 /* Check for last transfer */ 1150 if (((void *)td) == xfer->td_transfer_last) { 1151 td = NULL; 1152 break; 1153 } 1154 if (status & UHCI_TD_STALLED) { 1155 /* the transfer is finished */ 1156 td = NULL; 1157 break; 1158 } 1159 /* Check for short transfer */ 1160 if (len != td->len) { 1161 if (xfer->flags_int.short_frames_ok) { 1162 /* follow alt next */ 1163 td = td->alt_next; 1164 } else { 1165 /* the transfer is finished */ 1166 td = NULL; 1167 } 1168 break; 1169 } 1170 td = td->obj_next; 1171 1172 if (td->alt_next != td_alt_next) { 1173 /* this USB frame is complete */ 1174 break; 1175 } 1176 } 1177 1178 /* update transfer cache */ 1179 1180 xfer->td_transfer_cache = td; 1181 1182 /* update data toggle */ 1183 1184 xfer->pipe->toggle_next = (token & UHCI_TD_SET_DT(1)) ? 0 : 1; 1185 1186#if USB_DEBUG 1187 if (status & UHCI_TD_ERROR) { 1188 DPRINTFN(11, "error, addr=%d, endpt=0x%02x, frame=0x%02x " 1189 "status=%s%s%s%s%s%s%s%s%s%s%s\n", 1190 xfer->address, xfer->endpoint, xfer->aframes, 1191 (status & UHCI_TD_BITSTUFF) ? "[BITSTUFF]" : "", 1192 (status & UHCI_TD_CRCTO) ? "[CRCTO]" : "", 1193 (status & UHCI_TD_NAK) ? "[NAK]" : "", 1194 (status & UHCI_TD_BABBLE) ? "[BABBLE]" : "", 1195 (status & UHCI_TD_DBUFFER) ? "[DBUFFER]" : "", 1196 (status & UHCI_TD_STALLED) ? "[STALLED]" : "", 1197 (status & UHCI_TD_ACTIVE) ? "[ACTIVE]" : "[NOT_ACTIVE]", 1198 (status & UHCI_TD_IOC) ? "[IOC]" : "", 1199 (status & UHCI_TD_IOS) ? "[IOS]" : "", 1200 (status & UHCI_TD_LS) ? "[LS]" : "", 1201 (status & UHCI_TD_SPD) ? "[SPD]" : ""); 1202 } 1203#endif 1204 return (status & UHCI_TD_STALLED) ? 1205 USB_ERR_STALLED : USB_ERR_NORMAL_COMPLETION; 1206} 1207 1208static void 1209uhci_non_isoc_done(struct usb2_xfer *xfer) 1210{ 1211 usb2_error_t err = 0; 1212 1213 DPRINTFN(13, "xfer=%p pipe=%p transfer done\n", 1214 xfer, xfer->pipe); 1215 1216#if USB_DEBUG 1217 if (uhcidebug > 10) { 1218 uhci_dump_tds(xfer->td_transfer_first); 1219 } 1220#endif 1221 1222 /* sync any DMA memory before doing fixups */ 1223 1224 usb2_bdma_post_sync(xfer); 1225 1226 /* reset scanner */ 1227 1228 xfer->td_transfer_cache = xfer->td_transfer_first; 1229 1230 if (xfer->flags_int.control_xfr) { 1231 if (xfer->flags_int.control_hdr) { 1232 1233 err = uhci_non_isoc_done_sub(xfer); 1234 } 1235 xfer->aframes = 1; 1236 1237 if (xfer->td_transfer_cache == NULL) { 1238 goto done; 1239 } 1240 } 1241 while (xfer->aframes != xfer->nframes) { 1242 1243 err = uhci_non_isoc_done_sub(xfer); 1244 xfer->aframes++; 1245 1246 if (xfer->td_transfer_cache == NULL) { 1247 goto done; 1248 } 1249 } 1250 1251 if (xfer->flags_int.control_xfr && 1252 !xfer->flags_int.control_act) { 1253 1254 err = uhci_non_isoc_done_sub(xfer); 1255 } 1256done: 1257 uhci_device_done(xfer, err); 1258 return; 1259} 1260 1261/*------------------------------------------------------------------------* 1262 * uhci_check_transfer_sub 1263 * 1264 * The main purpose of this function is to update the data-toggle 1265 * in case it is wrong. 1266 *------------------------------------------------------------------------*/ 1267static void 1268uhci_check_transfer_sub(struct usb2_xfer *xfer) 1269{ 1270 uhci_qh_t *qh; 1271 uhci_td_t *td; 1272 uhci_td_t *td_alt_next; 1273 1274 uint32_t td_token; 1275 uint32_t td_self; 1276 1277 td = xfer->td_transfer_cache; 1278 qh = xfer->qh_start[xfer->flags_int.curr_dma_set]; 1279 1280 td_token = td->obj_next->td_token; 1281 td = td->alt_next; 1282 xfer->td_transfer_cache = td; 1283 td_self = td->td_self; 1284 td_alt_next = td->alt_next; 1285 1286 if ((td->td_token ^ td_token) & htole32(UHCI_TD_SET_DT(1))) { 1287 1288 /* 1289 * The data toggle is wrong and 1290 * we need to switch it ! 1291 */ 1292 1293 while (1) { 1294 1295 td->td_token ^= htole32(UHCI_TD_SET_DT(1)); 1296 usb2_pc_cpu_flush(td->page_cache); 1297 1298 if (td == xfer->td_transfer_last) { 1299 /* last transfer */ 1300 break; 1301 } 1302 td = td->obj_next; 1303 1304 if (td->alt_next != td_alt_next) { 1305 /* next frame */ 1306 break; 1307 } 1308 } 1309 } 1310 /* update the QH */ 1311 qh->qh_e_next = td_self; 1312 usb2_pc_cpu_flush(qh->page_cache); 1313 1314 DPRINTFN(13, "xfer=%p following alt next\n", xfer); 1315 return; 1316} 1317 1318/*------------------------------------------------------------------------* 1319 * uhci_check_transfer 1320 * 1321 * Return values: 1322 * 0: USB transfer is not finished 1323 * Else: USB transfer is finished 1324 *------------------------------------------------------------------------*/ 1325static uint8_t 1326uhci_check_transfer(struct usb2_xfer *xfer) 1327{ 1328 uint32_t status; 1329 uint32_t token; 1330 uhci_td_t *td; 1331 1332 DPRINTFN(16, "xfer=%p checking transfer\n", xfer); 1333 1334 if (xfer->pipe->methods == &uhci_device_isoc_methods) { 1335 /* isochronous transfer */ 1336 1337 td = xfer->td_transfer_last; 1338 1339 usb2_pc_cpu_invalidate(td->page_cache); 1340 status = le32toh(td->td_status); 1341 1342 /* check also if the first is complete */ 1343 1344 td = xfer->td_transfer_first; 1345 1346 usb2_pc_cpu_invalidate(td->page_cache); 1347 status |= le32toh(td->td_status); 1348 1349 if (!(status & UHCI_TD_ACTIVE)) { 1350 uhci_device_done(xfer, USB_ERR_NORMAL_COMPLETION); 1351 goto transferred; 1352 } 1353 } else { 1354 /* non-isochronous transfer */ 1355 1356 /* 1357 * check whether there is an error somewhere 1358 * in the middle, or whether there was a short 1359 * packet (SPD and not ACTIVE) 1360 */ 1361 td = xfer->td_transfer_cache; 1362 1363 while (1) { 1364 usb2_pc_cpu_invalidate(td->page_cache); 1365 status = le32toh(td->td_status); 1366 token = le32toh(td->td_token); 1367 1368 /* 1369 * if there is an active TD the transfer isn't done 1370 */ 1371 if (status & UHCI_TD_ACTIVE) { 1372 /* update cache */ 1373 xfer->td_transfer_cache = td; 1374 goto done; 1375 } 1376 /* 1377 * last transfer descriptor makes the transfer done 1378 */ 1379 if (((void *)td) == xfer->td_transfer_last) { 1380 break; 1381 } 1382 /* 1383 * any kind of error makes the transfer done 1384 */ 1385 if (status & UHCI_TD_STALLED) { 1386 break; 1387 } 1388 /* 1389 * check if we reached the last packet 1390 * or if there is a short packet: 1391 */ 1392 if ((td->td_next == htole32(UHCI_PTR_T)) || 1393 (UHCI_TD_GET_ACTLEN(status) < td->len)) { 1394 1395 if (xfer->flags_int.short_frames_ok) { 1396 /* follow alt next */ 1397 if (td->alt_next) { 1398 /* update cache */ 1399 xfer->td_transfer_cache = td; 1400 uhci_check_transfer_sub(xfer); 1401 goto done; 1402 } 1403 } 1404 /* transfer is done */ 1405 break; 1406 } 1407 td = td->obj_next; 1408 } 1409 uhci_non_isoc_done(xfer); 1410 goto transferred; 1411 } 1412 1413done: 1414 DPRINTFN(13, "xfer=%p is still active\n", xfer); 1415 return (0); 1416 1417transferred: 1418 return (1); 1419} 1420 1421static void 1422uhci_interrupt_poll(uhci_softc_t *sc) 1423{ 1424 struct usb2_xfer *xfer; 1425 1426repeat: 1427 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 1428 /* 1429 * check if transfer is transferred 1430 */ 1431 if (uhci_check_transfer(xfer)) { 1432 /* queue has been modified */ 1433 goto repeat; 1434 } 1435 } 1436 return; 1437} 1438 1439/*------------------------------------------------------------------------* 1440 * uhci_interrupt - UHCI interrupt handler 1441 * 1442 * NOTE: Do not access "sc->sc_bus.bdev" inside the interrupt handler, 1443 * hence the interrupt handler will be setup before "sc->sc_bus.bdev" 1444 * is present ! 1445 *------------------------------------------------------------------------*/ 1446void 1447uhci_interrupt(uhci_softc_t *sc) 1448{ 1449 uint32_t status; 1450
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1451 mtx_lock(&sc->sc_bus.mtx);
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1451 USB_BUS_LOCK(&sc->sc_bus); |
1452 1453 DPRINTFN(16, "real interrupt\n"); 1454 1455#if USB_DEBUG 1456 if (uhcidebug > 15) { 1457 uhci_dumpregs(sc); 1458 } 1459#endif 1460 status = UREAD2(sc, UHCI_STS) & UHCI_STS_ALLINTRS; 1461 if (status == 0) { 1462 /* the interrupt was not for us */ 1463 goto done; 1464 } 1465 if (status & (UHCI_STS_RD | UHCI_STS_HSE | 1466 UHCI_STS_HCPE | UHCI_STS_HCH)) { 1467 1468 if (status & UHCI_STS_RD) { 1469#if USB_DEBUG 1470 printf("%s: resume detect\n", 1471 __FUNCTION__); 1472#endif 1473 } 1474 if (status & UHCI_STS_HSE) { 1475 printf("%s: host system error\n", 1476 __FUNCTION__); 1477 } 1478 if (status & UHCI_STS_HCPE) { 1479 printf("%s: host controller process error\n", 1480 __FUNCTION__); 1481 } 1482 if (status & UHCI_STS_HCH) { 1483 /* no acknowledge needed */ 1484 printf("%s: host controller halted\n", 1485 __FUNCTION__); 1486#if USB_DEBUG 1487 uhci_dump_all(sc); 1488#endif 1489 } 1490 } 1491 /* get acknowledge bits */ 1492 status &= (UHCI_STS_USBINT | 1493 UHCI_STS_USBEI | 1494 UHCI_STS_RD | 1495 UHCI_STS_HSE | 1496 UHCI_STS_HCPE); 1497 1498 if (status == 0) { 1499 /* nothing to acknowledge */ 1500 goto done; 1501 } 1502 /* acknowledge interrupts */ 1503 UWRITE2(sc, UHCI_STS, status); 1504 1505 /* poll all the USB transfers */ 1506 uhci_interrupt_poll(sc); 1507 1508done:
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1509 mtx_unlock(&sc->sc_bus.mtx);
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1509 USB_BUS_UNLOCK(&sc->sc_bus); |
1510 return; 1511} 1512 1513/* 1514 * called when a request does not complete 1515 */ 1516static void 1517uhci_timeout(void *arg) 1518{ 1519 struct usb2_xfer *xfer = arg; 1520 uhci_softc_t *sc = xfer->usb2_sc; 1521 1522 DPRINTF("xfer=%p\n", xfer); 1523
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1524 mtx_assert(&sc->sc_bus.mtx, MA_OWNED);
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1524 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); |
1525 1526 /* transfer is transferred */ 1527 uhci_device_done(xfer, USB_ERR_TIMEOUT); 1528
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1529 mtx_unlock(&sc->sc_bus.mtx);
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1529 USB_BUS_UNLOCK(&sc->sc_bus); |
1530 1531 return; 1532} 1533 1534static void 1535uhci_do_poll(struct usb2_bus *bus) 1536{ 1537 struct uhci_softc *sc = UHCI_BUS2SC(bus); 1538
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1539 mtx_lock(&sc->sc_bus.mtx);
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1539 USB_BUS_LOCK(&sc->sc_bus); |
1540 uhci_interrupt_poll(sc); 1541 uhci_root_ctrl_poll(sc);
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1542 mtx_unlock(&sc->sc_bus.mtx);
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1542 USB_BUS_UNLOCK(&sc->sc_bus); |
1543 return; 1544} 1545 1546static void 1547uhci_setup_standard_chain_sub(struct uhci_std_temp *temp) 1548{ 1549 uhci_td_t *td; 1550 uhci_td_t *td_next; 1551 uhci_td_t *td_alt_next; 1552 uint32_t average; 1553 uint32_t len_old; 1554 uint8_t shortpkt_old; 1555 uint8_t precompute; 1556 1557 td_alt_next = NULL; 1558 shortpkt_old = temp->shortpkt; 1559 len_old = temp->len; 1560 precompute = 1; 1561 1562 /* software is used to detect short incoming transfers */ 1563 1564 if ((temp->td_token & htole32(UHCI_TD_PID)) == htole32(UHCI_TD_PID_IN)) { 1565 temp->td_status |= htole32(UHCI_TD_SPD); 1566 } else { 1567 temp->td_status &= ~htole32(UHCI_TD_SPD); 1568 } 1569 1570 temp->ml.buf_offset = 0; 1571 1572restart: 1573 1574 temp->td_token &= ~htole32(UHCI_TD_SET_MAXLEN(0)); 1575 temp->td_token |= htole32(UHCI_TD_SET_MAXLEN(temp->average)); 1576 1577 td = temp->td; 1578 td_next = temp->td_next; 1579 1580 while (1) { 1581 1582 if (temp->len == 0) { 1583 1584 if (temp->shortpkt) { 1585 break; 1586 } 1587 /* send a Zero Length Packet, ZLP, last */ 1588 1589 temp->shortpkt = 1; 1590 temp->td_token |= htole32(UHCI_TD_SET_MAXLEN(0)); 1591 average = 0; 1592 1593 } else { 1594 1595 average = temp->average; 1596 1597 if (temp->len < average) { 1598 temp->shortpkt = 1; 1599 temp->td_token &= ~htole32(UHCI_TD_SET_MAXLEN(0)); 1600 temp->td_token |= htole32(UHCI_TD_SET_MAXLEN(temp->len)); 1601 average = temp->len; 1602 } 1603 } 1604 1605 if (td_next == NULL) { 1606 panic("%s: out of UHCI transfer descriptors!", __FUNCTION__); 1607 } 1608 /* get next TD */ 1609 1610 td = td_next; 1611 td_next = td->obj_next; 1612 1613 /* check if we are pre-computing */ 1614 1615 if (precompute) { 1616 1617 /* update remaining length */ 1618 1619 temp->len -= average; 1620 1621 continue; 1622 } 1623 /* fill out current TD */ 1624 1625 td->td_status = temp->td_status; 1626 td->td_token = temp->td_token; 1627 1628 /* update data toggle */ 1629 1630 temp->td_token ^= htole32(UHCI_TD_SET_DT(1)); 1631 1632 if (average == 0) { 1633 1634 td->len = 0; 1635 td->td_buffer = 0; 1636 td->fix_pc = NULL; 1637 1638 } else { 1639 1640 /* update remaining length */ 1641 1642 temp->len -= average; 1643 1644 td->len = average; 1645 1646 /* fill out buffer pointer and do fixup, if any */ 1647 1648 uhci_mem_layout_fixup(&temp->ml, td); 1649 } 1650 1651 td->alt_next = td_alt_next; 1652 1653 if ((td_next == td_alt_next) && temp->setup_alt_next) { 1654 /* we need to receive these frames one by one ! */ 1655 td->td_status |= htole32(UHCI_TD_IOC); 1656 td->td_next = htole32(UHCI_PTR_T); 1657 } else { 1658 if (td_next) { 1659 /* link the current TD with the next one */ 1660 td->td_next = td_next->td_self; 1661 } 1662 } 1663 1664 usb2_pc_cpu_flush(td->page_cache); 1665 } 1666 1667 if (precompute) { 1668 precompute = 0; 1669 1670 /* setup alt next pointer, if any */ 1671 if (temp->short_frames_ok) { 1672 if (temp->setup_alt_next) { 1673 td_alt_next = td_next; 1674 } 1675 } else { 1676 /* we use this field internally */ 1677 td_alt_next = td_next; 1678 } 1679 1680 /* restore */ 1681 temp->shortpkt = shortpkt_old; 1682 temp->len = len_old; 1683 goto restart; 1684 } 1685 temp->td = td; 1686 temp->td_next = td_next; 1687 1688 return; 1689} 1690 1691static uhci_td_t * 1692uhci_setup_standard_chain(struct usb2_xfer *xfer) 1693{ 1694 struct uhci_std_temp temp; 1695 uhci_td_t *td; 1696 uint32_t x; 1697 1698 DPRINTFN(9, "addr=%d endpt=%d sumlen=%d speed=%d\n", 1699 xfer->address, UE_GET_ADDR(xfer->endpoint), 1700 xfer->sumlen, usb2_get_speed(xfer->udev)); 1701 1702 temp.average = xfer->max_frame_size; 1703 temp.max_frame_size = xfer->max_frame_size; 1704 1705 /* toggle the DMA set we are using */ 1706 xfer->flags_int.curr_dma_set ^= 1; 1707 1708 /* get next DMA set */ 1709 td = xfer->td_start[xfer->flags_int.curr_dma_set]; 1710 xfer->td_transfer_first = td; 1711 xfer->td_transfer_cache = td; 1712 1713 temp.td = NULL; 1714 temp.td_next = td; 1715 temp.setup_alt_next = xfer->flags_int.short_frames_ok; 1716 temp.short_frames_ok = xfer->flags_int.short_frames_ok; 1717 1718 uhci_mem_layout_init(&temp.ml, xfer); 1719 1720 temp.td_status = 1721 htole32(UHCI_TD_ZERO_ACTLEN(UHCI_TD_SET_ERRCNT(3) | 1722 UHCI_TD_ACTIVE)); 1723 1724 if (xfer->udev->speed == USB_SPEED_LOW) { 1725 temp.td_status |= htole32(UHCI_TD_LS); 1726 } 1727 temp.td_token = 1728 htole32(UHCI_TD_SET_ENDPT(xfer->endpoint) | 1729 UHCI_TD_SET_DEVADDR(xfer->address)); 1730 1731 if (xfer->pipe->toggle_next) { 1732 /* DATA1 is next */ 1733 temp.td_token |= htole32(UHCI_TD_SET_DT(1)); 1734 } 1735 /* check if we should prepend a setup message */ 1736 1737 if (xfer->flags_int.control_xfr) { 1738 1739 if (xfer->flags_int.control_hdr) { 1740 1741 temp.td_token &= htole32(UHCI_TD_SET_DEVADDR(0x7F) | 1742 UHCI_TD_SET_ENDPT(0xF)); 1743 temp.td_token |= htole32(UHCI_TD_PID_SETUP | 1744 UHCI_TD_SET_DT(0)); 1745 1746 temp.len = xfer->frlengths[0]; 1747 temp.ml.buf_pc = xfer->frbuffers + 0; 1748 temp.shortpkt = temp.len ? 1 : 0; 1749 1750 uhci_setup_standard_chain_sub(&temp); 1751 } 1752 x = 1; 1753 } else { 1754 x = 0; 1755 } 1756 1757 while (x != xfer->nframes) { 1758 1759 /* DATA0 / DATA1 message */ 1760 1761 temp.len = xfer->frlengths[x]; 1762 temp.ml.buf_pc = xfer->frbuffers + x; 1763 1764 x++; 1765 1766 if (x == xfer->nframes) { 1767 temp.setup_alt_next = 0; 1768 } 1769 /* 1770 * Keep previous data toggle, 1771 * device address and endpoint number: 1772 */ 1773 1774 temp.td_token &= htole32(UHCI_TD_SET_DEVADDR(0x7F) | 1775 UHCI_TD_SET_ENDPT(0xF) | 1776 UHCI_TD_SET_DT(1)); 1777 1778 if (temp.len == 0) { 1779 1780 /* make sure that we send an USB packet */ 1781 1782 temp.shortpkt = 0; 1783 1784 } else { 1785 1786 /* regular data transfer */ 1787 1788 temp.shortpkt = (xfer->flags.force_short_xfer) ? 0 : 1; 1789 } 1790 1791 /* set endpoint direction */ 1792 1793 temp.td_token |= 1794 (UE_GET_DIR(xfer->endpoint) == UE_DIR_IN) ? 1795 htole32(UHCI_TD_PID_IN) : 1796 htole32(UHCI_TD_PID_OUT); 1797 1798 uhci_setup_standard_chain_sub(&temp); 1799 } 1800 1801 /* check if we should append a status stage */ 1802 1803 if (xfer->flags_int.control_xfr && 1804 !xfer->flags_int.control_act) { 1805 1806 /* 1807 * send a DATA1 message and reverse the current endpoint 1808 * direction 1809 */ 1810 1811 temp.td_token &= htole32(UHCI_TD_SET_DEVADDR(0x7F) | 1812 UHCI_TD_SET_ENDPT(0xF) | 1813 UHCI_TD_SET_DT(1)); 1814 temp.td_token |= 1815 (UE_GET_DIR(xfer->endpoint) == UE_DIR_OUT) ? 1816 htole32(UHCI_TD_PID_IN | UHCI_TD_SET_DT(1)) : 1817 htole32(UHCI_TD_PID_OUT | UHCI_TD_SET_DT(1)); 1818 1819 temp.len = 0; 1820 temp.ml.buf_pc = NULL; 1821 temp.shortpkt = 0; 1822 1823 uhci_setup_standard_chain_sub(&temp); 1824 } 1825 td = temp.td; 1826 1827 td->td_next = htole32(UHCI_PTR_T); 1828 1829 /* set interrupt bit */ 1830 1831 td->td_status |= htole32(UHCI_TD_IOC); 1832 1833 usb2_pc_cpu_flush(td->page_cache); 1834 1835 /* must have at least one frame! */ 1836 1837 xfer->td_transfer_last = td; 1838 1839#if USB_DEBUG 1840 if (uhcidebug > 8) { 1841 DPRINTF("nexttog=%d; data before transfer:\n", 1842 xfer->pipe->toggle_next); 1843 uhci_dump_tds(xfer->td_transfer_first); 1844 } 1845#endif 1846 return (xfer->td_transfer_first); 1847} 1848 1849/* NOTE: "done" can be run two times in a row, 1850 * from close and from interrupt 1851 */ 1852 1853static void 1854uhci_device_done(struct usb2_xfer *xfer, usb2_error_t error) 1855{ 1856 struct usb2_pipe_methods *methods = xfer->pipe->methods; 1857 uhci_softc_t *sc = xfer->usb2_sc; 1858 uhci_qh_t *qh; 1859
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1860 mtx_assert(&sc->sc_bus.mtx, MA_OWNED);
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1860 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); |
1861 1862 DPRINTFN(2, "xfer=%p, pipe=%p, error=%d\n", 1863 xfer, xfer->pipe, error); 1864 1865 qh = xfer->qh_start[xfer->flags_int.curr_dma_set]; 1866 if (qh) { 1867 usb2_pc_cpu_invalidate(qh->page_cache); 1868 1869 qh->e_next = 0; 1870 qh->qh_e_next = htole32(UHCI_PTR_T); 1871 1872 usb2_pc_cpu_flush(qh->page_cache); 1873 } 1874 if (xfer->flags_int.bandwidth_reclaimed) { 1875 xfer->flags_int.bandwidth_reclaimed = 0; 1876 uhci_rem_loop(sc); 1877 } 1878 if (methods == &uhci_device_bulk_methods) { 1879 UHCI_REMOVE_QH(qh, sc->sc_bulk_p_last); 1880 } 1881 if (methods == &uhci_device_ctrl_methods) { 1882 if (xfer->udev->speed == USB_SPEED_LOW) { 1883 UHCI_REMOVE_QH(qh, sc->sc_ls_ctl_p_last); 1884 } else { 1885 UHCI_REMOVE_QH(qh, sc->sc_fs_ctl_p_last); 1886 } 1887 } 1888 if (methods == &uhci_device_intr_methods) { 1889 UHCI_REMOVE_QH(qh, sc->sc_intr_p_last[xfer->qh_pos]); 1890 } 1891 /* 1892 * Only finish isochronous transfers once 1893 * which will update "xfer->frlengths". 1894 */ 1895 if (xfer->td_transfer_first && 1896 xfer->td_transfer_last) { 1897 if (methods == &uhci_device_isoc_methods) { 1898 uhci_isoc_done(sc, xfer); 1899 } 1900 xfer->td_transfer_first = NULL; 1901 xfer->td_transfer_last = NULL; 1902 } 1903 /* dequeue transfer and start next transfer */ 1904 usb2_transfer_done(xfer, error); 1905 return; 1906} 1907 1908/*------------------------------------------------------------------------* 1909 * uhci bulk support 1910 *------------------------------------------------------------------------*/ 1911static void 1912uhci_device_bulk_open(struct usb2_xfer *xfer) 1913{ 1914 return; 1915} 1916 1917static void 1918uhci_device_bulk_close(struct usb2_xfer *xfer) 1919{ 1920 uhci_device_done(xfer, USB_ERR_CANCELLED); 1921 return; 1922} 1923 1924static void 1925uhci_device_bulk_enter(struct usb2_xfer *xfer) 1926{ 1927 return; 1928} 1929 1930static void 1931uhci_device_bulk_start(struct usb2_xfer *xfer) 1932{ 1933 uhci_softc_t *sc = xfer->usb2_sc; 1934 uhci_td_t *td; 1935 uhci_qh_t *qh; 1936 1937 /* setup TD's */ 1938 td = uhci_setup_standard_chain(xfer); 1939 1940 /* setup QH */ 1941 qh = xfer->qh_start[xfer->flags_int.curr_dma_set]; 1942 1943 UHCI_APPEND_QH(qh, td, sc->sc_bulk_p_last); 1944 uhci_add_loop(sc); 1945 xfer->flags_int.bandwidth_reclaimed = 1; 1946 1947 /* put transfer on interrupt queue */ 1948 uhci_transfer_intr_enqueue(xfer); 1949 return; 1950} 1951 1952struct usb2_pipe_methods uhci_device_bulk_methods = 1953{ 1954 .open = uhci_device_bulk_open, 1955 .close = uhci_device_bulk_close, 1956 .enter = uhci_device_bulk_enter, 1957 .start = uhci_device_bulk_start, 1958 .enter_is_cancelable = 1, 1959 .start_is_cancelable = 1, 1960}; 1961 1962/*------------------------------------------------------------------------* 1963 * uhci control support 1964 *------------------------------------------------------------------------*/ 1965static void 1966uhci_device_ctrl_open(struct usb2_xfer *xfer) 1967{ 1968 return; 1969} 1970 1971static void 1972uhci_device_ctrl_close(struct usb2_xfer *xfer) 1973{ 1974 uhci_device_done(xfer, USB_ERR_CANCELLED); 1975 return; 1976} 1977 1978static void 1979uhci_device_ctrl_enter(struct usb2_xfer *xfer) 1980{ 1981 return; 1982} 1983 1984static void 1985uhci_device_ctrl_start(struct usb2_xfer *xfer) 1986{ 1987 uhci_softc_t *sc = xfer->usb2_sc; 1988 uhci_qh_t *qh; 1989 uhci_td_t *td; 1990 1991 /* setup TD's */ 1992 td = uhci_setup_standard_chain(xfer); 1993 1994 /* setup QH */ 1995 qh = xfer->qh_start[xfer->flags_int.curr_dma_set]; 1996 1997 /* 1998 * NOTE: some devices choke on bandwidth- reclamation for control 1999 * transfers 2000 */ 2001 if (xfer->udev->speed == USB_SPEED_LOW) { 2002 UHCI_APPEND_QH(qh, td, sc->sc_ls_ctl_p_last); 2003 } else { 2004 UHCI_APPEND_QH(qh, td, sc->sc_fs_ctl_p_last); 2005 } 2006 /* put transfer on interrupt queue */ 2007 uhci_transfer_intr_enqueue(xfer); 2008 return; 2009} 2010 2011struct usb2_pipe_methods uhci_device_ctrl_methods = 2012{ 2013 .open = uhci_device_ctrl_open, 2014 .close = uhci_device_ctrl_close, 2015 .enter = uhci_device_ctrl_enter, 2016 .start = uhci_device_ctrl_start, 2017 .enter_is_cancelable = 1, 2018 .start_is_cancelable = 1, 2019}; 2020 2021/*------------------------------------------------------------------------* 2022 * uhci interrupt support 2023 *------------------------------------------------------------------------*/ 2024static void 2025uhci_device_intr_open(struct usb2_xfer *xfer) 2026{ 2027 uhci_softc_t *sc = xfer->usb2_sc; 2028 uint16_t best; 2029 uint16_t bit; 2030 uint16_t x; 2031 2032 best = 0; 2033 bit = UHCI_IFRAMELIST_COUNT / 2; 2034 while (bit) { 2035 if (xfer->interval >= bit) { 2036 x = bit; 2037 best = bit; 2038 while (x & bit) { 2039 if (sc->sc_intr_stat[x] < 2040 sc->sc_intr_stat[best]) { 2041 best = x; 2042 } 2043 x++; 2044 } 2045 break; 2046 } 2047 bit >>= 1; 2048 } 2049 2050 sc->sc_intr_stat[best]++; 2051 xfer->qh_pos = best; 2052 2053 DPRINTFN(3, "best=%d interval=%d\n", 2054 best, xfer->interval); 2055 return; 2056} 2057 2058static void 2059uhci_device_intr_close(struct usb2_xfer *xfer) 2060{ 2061 uhci_softc_t *sc = xfer->usb2_sc; 2062 2063 sc->sc_intr_stat[xfer->qh_pos]--; 2064 2065 uhci_device_done(xfer, USB_ERR_CANCELLED); 2066 return; 2067} 2068 2069static void 2070uhci_device_intr_enter(struct usb2_xfer *xfer) 2071{ 2072 return; 2073} 2074 2075static void 2076uhci_device_intr_start(struct usb2_xfer *xfer) 2077{ 2078 uhci_softc_t *sc = xfer->usb2_sc; 2079 uhci_qh_t *qh; 2080 uhci_td_t *td; 2081 2082 /* setup TD's */ 2083 td = uhci_setup_standard_chain(xfer); 2084 2085 /* setup QH */ 2086 qh = xfer->qh_start[xfer->flags_int.curr_dma_set]; 2087 2088 /* enter QHs into the controller data structures */ 2089 UHCI_APPEND_QH(qh, td, sc->sc_intr_p_last[xfer->qh_pos]); 2090 2091 /* put transfer on interrupt queue */ 2092 uhci_transfer_intr_enqueue(xfer); 2093 return; 2094} 2095 2096struct usb2_pipe_methods uhci_device_intr_methods = 2097{ 2098 .open = uhci_device_intr_open, 2099 .close = uhci_device_intr_close, 2100 .enter = uhci_device_intr_enter, 2101 .start = uhci_device_intr_start, 2102 .enter_is_cancelable = 1, 2103 .start_is_cancelable = 1, 2104}; 2105 2106/*------------------------------------------------------------------------* 2107 * uhci isochronous support 2108 *------------------------------------------------------------------------*/ 2109static void 2110uhci_device_isoc_open(struct usb2_xfer *xfer) 2111{ 2112 uhci_td_t *td; 2113 uint32_t td_token; 2114 uint8_t ds; 2115 2116 td_token = 2117 (UE_GET_DIR(xfer->endpoint) == UE_DIR_IN) ? 2118 UHCI_TD_IN(0, xfer->endpoint, xfer->address, 0) : 2119 UHCI_TD_OUT(0, xfer->endpoint, xfer->address, 0); 2120 2121 td_token = htole32(td_token); 2122 2123 /* initialize all TD's */ 2124 2125 for (ds = 0; ds != 2; ds++) { 2126 2127 for (td = xfer->td_start[ds]; td; td = td->obj_next) { 2128 2129 /* mark TD as inactive */ 2130 td->td_status = htole32(UHCI_TD_IOS); 2131 td->td_token = td_token; 2132 2133 usb2_pc_cpu_flush(td->page_cache); 2134 } 2135 } 2136 return; 2137} 2138 2139static void 2140uhci_device_isoc_close(struct usb2_xfer *xfer) 2141{ 2142 uhci_device_done(xfer, USB_ERR_CANCELLED); 2143 return; 2144} 2145 2146static void 2147uhci_device_isoc_enter(struct usb2_xfer *xfer) 2148{ 2149 struct uhci_mem_layout ml; 2150 uhci_softc_t *sc = xfer->usb2_sc; 2151 uint32_t nframes; 2152 uint32_t temp; 2153 uint32_t *plen; 2154 2155#if USB_DEBUG 2156 uint8_t once = 1; 2157 2158#endif 2159 uhci_td_t *td; 2160 uhci_td_t *td_last = NULL; 2161 uhci_td_t **pp_last; 2162 2163 DPRINTFN(6, "xfer=%p next=%d nframes=%d\n", 2164 xfer, xfer->pipe->isoc_next, xfer->nframes); 2165 2166 nframes = UREAD2(sc, UHCI_FRNUM); 2167 2168 temp = (nframes - xfer->pipe->isoc_next) & 2169 (UHCI_VFRAMELIST_COUNT - 1); 2170 2171 if ((xfer->pipe->is_synced == 0) || 2172 (temp < xfer->nframes)) { 2173 /* 2174 * If there is data underflow or the pipe queue is empty we 2175 * schedule the transfer a few frames ahead of the current 2176 * frame position. Else two isochronous transfers might 2177 * overlap. 2178 */ 2179 xfer->pipe->isoc_next = (nframes + 3) & (UHCI_VFRAMELIST_COUNT - 1); 2180 xfer->pipe->is_synced = 1; 2181 DPRINTFN(3, "start next=%d\n", xfer->pipe->isoc_next); 2182 } 2183 /* 2184 * compute how many milliseconds the insertion is ahead of the 2185 * current frame position: 2186 */ 2187 temp = (xfer->pipe->isoc_next - nframes) & 2188 (UHCI_VFRAMELIST_COUNT - 1); 2189 2190 /* 2191 * pre-compute when the isochronous transfer will be finished: 2192 */ 2193 xfer->isoc_time_complete = 2194 usb2_isoc_time_expand(&sc->sc_bus, nframes) + temp + 2195 xfer->nframes; 2196 2197 /* get the real number of frames */ 2198 2199 nframes = xfer->nframes; 2200 2201 uhci_mem_layout_init(&ml, xfer); 2202 2203 plen = xfer->frlengths; 2204 2205 /* toggle the DMA set we are using */ 2206 xfer->flags_int.curr_dma_set ^= 1; 2207 2208 /* get next DMA set */ 2209 td = xfer->td_start[xfer->flags_int.curr_dma_set]; 2210 xfer->td_transfer_first = td; 2211 2212 pp_last = &sc->sc_isoc_p_last[xfer->pipe->isoc_next]; 2213 2214 /* store starting position */ 2215 2216 xfer->qh_pos = xfer->pipe->isoc_next; 2217 2218 while (nframes--) { 2219 if (td == NULL) { 2220 panic("%s:%d: out of TD's\n", 2221 __FUNCTION__, __LINE__); 2222 } 2223 if (pp_last >= &sc->sc_isoc_p_last[UHCI_VFRAMELIST_COUNT]) { 2224 pp_last = &sc->sc_isoc_p_last[0]; 2225 } 2226 if (*plen > xfer->max_frame_size) { 2227#if USB_DEBUG 2228 if (once) { 2229 once = 0; 2230 printf("%s: frame length(%d) exceeds %d " 2231 "bytes (frame truncated)\n", 2232 __FUNCTION__, *plen, 2233 xfer->max_frame_size); 2234 } 2235#endif 2236 *plen = xfer->max_frame_size; 2237 } 2238 /* reuse td_token from last transfer */ 2239 2240 td->td_token &= htole32(~UHCI_TD_MAXLEN_MASK); 2241 td->td_token |= htole32(UHCI_TD_SET_MAXLEN(*plen)); 2242 2243 td->len = *plen; 2244 2245 if (td->len == 0) { 2246 /* 2247 * Do not call "uhci_mem_layout_fixup()" when the 2248 * length is zero! 2249 */ 2250 td->td_buffer = 0; 2251 td->fix_pc = NULL; 2252 2253 } else { 2254 2255 /* fill out buffer pointer and do fixup, if any */ 2256 2257 uhci_mem_layout_fixup(&ml, td); 2258 2259 } 2260 2261 /* update status */ 2262 if (nframes == 0) { 2263 td->td_status = htole32 2264 (UHCI_TD_ZERO_ACTLEN 2265 (UHCI_TD_SET_ERRCNT(0) | 2266 UHCI_TD_ACTIVE | 2267 UHCI_TD_IOS | 2268 UHCI_TD_IOC)); 2269 } else { 2270 td->td_status = htole32 2271 (UHCI_TD_ZERO_ACTLEN 2272 (UHCI_TD_SET_ERRCNT(0) | 2273 UHCI_TD_ACTIVE | 2274 UHCI_TD_IOS)); 2275 } 2276 2277 usb2_pc_cpu_flush(td->page_cache); 2278 2279#if USB_DEBUG 2280 if (uhcidebug > 5) { 2281 DPRINTF("TD %d\n", nframes); 2282 uhci_dump_td(td); 2283 } 2284#endif 2285 /* insert TD into schedule */ 2286 UHCI_APPEND_TD(td, *pp_last); 2287 pp_last++; 2288 2289 plen++; 2290 td_last = td; 2291 td = td->obj_next; 2292 } 2293 2294 xfer->td_transfer_last = td_last; 2295 2296 /* update isoc_next */ 2297 xfer->pipe->isoc_next = (pp_last - &sc->sc_isoc_p_last[0]) & 2298 (UHCI_VFRAMELIST_COUNT - 1); 2299 2300 return; 2301} 2302 2303static void 2304uhci_device_isoc_start(struct usb2_xfer *xfer) 2305{ 2306 /* put transfer on interrupt queue */ 2307 uhci_transfer_intr_enqueue(xfer); 2308 return; 2309} 2310 2311struct usb2_pipe_methods uhci_device_isoc_methods = 2312{ 2313 .open = uhci_device_isoc_open, 2314 .close = uhci_device_isoc_close, 2315 .enter = uhci_device_isoc_enter, 2316 .start = uhci_device_isoc_start, 2317 .enter_is_cancelable = 1, 2318 .start_is_cancelable = 1, 2319}; 2320 2321/*------------------------------------------------------------------------* 2322 * uhci root control support 2323 *------------------------------------------------------------------------* 2324 * simulate a hardware hub by handling 2325 * all the necessary requests 2326 *------------------------------------------------------------------------*/ 2327 2328static void 2329uhci_root_ctrl_open(struct usb2_xfer *xfer) 2330{ 2331 return; 2332} 2333 2334static void 2335uhci_root_ctrl_close(struct usb2_xfer *xfer) 2336{ 2337 uhci_softc_t *sc = xfer->usb2_sc; 2338 2339 if (sc->sc_root_ctrl.xfer == xfer) { 2340 sc->sc_root_ctrl.xfer = NULL; 2341 } 2342 uhci_device_done(xfer, USB_ERR_CANCELLED); 2343 return; 2344} 2345 2346/* data structures and routines 2347 * to emulate the root hub: 2348 */ 2349 2350static const 2351struct usb2_device_descriptor uhci_devd = 2352{ 2353 sizeof(struct usb2_device_descriptor), 2354 UDESC_DEVICE, /* type */ 2355 {0x00, 0x01}, /* USB version */ 2356 UDCLASS_HUB, /* class */ 2357 UDSUBCLASS_HUB, /* subclass */ 2358 UDPROTO_FSHUB, /* protocol */ 2359 64, /* max packet */ 2360 {0}, {0}, {0x00, 0x01}, /* device id */ 2361 1, 2, 0, /* string indicies */ 2362 1 /* # of configurations */ 2363}; 2364 2365static const struct uhci_config_desc uhci_confd = { 2366 .confd = { 2367 .bLength = sizeof(struct usb2_config_descriptor), 2368 .bDescriptorType = UDESC_CONFIG, 2369 .wTotalLength[0] = sizeof(uhci_confd), 2370 .bNumInterface = 1, 2371 .bConfigurationValue = 1, 2372 .iConfiguration = 0, 2373 .bmAttributes = UC_SELF_POWERED, 2374 .bMaxPower = 0 /* max power */ 2375 }, 2376 2377 .ifcd = { 2378 .bLength = sizeof(struct usb2_interface_descriptor), 2379 .bDescriptorType = UDESC_INTERFACE, 2380 .bNumEndpoints = 1, 2381 .bInterfaceClass = UICLASS_HUB, 2382 .bInterfaceSubClass = UISUBCLASS_HUB, 2383 .bInterfaceProtocol = UIPROTO_FSHUB, 2384 }, 2385 2386 .endpd = { 2387 .bLength = sizeof(struct usb2_endpoint_descriptor), 2388 .bDescriptorType = UDESC_ENDPOINT, 2389 .bEndpointAddress = UE_DIR_IN | UHCI_INTR_ENDPT, 2390 .bmAttributes = UE_INTERRUPT, 2391 .wMaxPacketSize[0] = 8, /* max packet (63 ports) */ 2392 .bInterval = 255, 2393 }, 2394}; 2395 2396static const 2397struct usb2_hub_descriptor_min uhci_hubd_piix = 2398{ 2399 sizeof(uhci_hubd_piix), 2400 UDESC_HUB, 2401 2, 2402 {UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL, 0}, 2403 50, /* power on to power good */ 2404 0, 2405 {0x00}, /* both ports are removable */ 2406}; 2407 2408/* 2409 * The USB hub protocol requires that SET_FEATURE(PORT_RESET) also 2410 * enables the port, and also states that SET_FEATURE(PORT_ENABLE) 2411 * should not be used by the USB subsystem. As we cannot issue a 2412 * SET_FEATURE(PORT_ENABLE) externally, we must ensure that the port 2413 * will be enabled as part of the reset. 2414 * 2415 * On the VT83C572, the port cannot be successfully enabled until the 2416 * outstanding "port enable change" and "connection status change" 2417 * events have been reset. 2418 */ 2419static usb2_error_t 2420uhci_portreset(uhci_softc_t *sc, uint16_t index, uint8_t use_polling) 2421{ 2422 uint16_t port; 2423 uint16_t x; 2424 uint8_t lim; 2425 2426 if (index == 1) 2427 port = UHCI_PORTSC1; 2428 else if (index == 2) 2429 port = UHCI_PORTSC2; 2430 else 2431 return (USB_ERR_IOERROR); 2432 2433 x = URWMASK(UREAD2(sc, port)); 2434 UWRITE2(sc, port, x | UHCI_PORTSC_PR); 2435 2436 if (use_polling) { 2437 /* polling */ 2438 DELAY(USB_PORT_ROOT_RESET_DELAY * 1000); 2439 } else {
|
2440 usb2_pause_mtx(&sc->sc_bus.mtx,
|
2440 usb2_pause_mtx(&sc->sc_bus.bus_mtx, |
2441 USB_PORT_ROOT_RESET_DELAY); 2442 } 2443 2444 DPRINTFN(4, "uhci port %d reset, status0 = 0x%04x\n", 2445 index, UREAD2(sc, port)); 2446 2447 x = URWMASK(UREAD2(sc, port)); 2448 UWRITE2(sc, port, x & ~UHCI_PORTSC_PR); 2449 2450 if (use_polling) { 2451 /* polling */ 2452 DELAY(1000); 2453 } else {
|
2454 usb2_pause_mtx(&sc->sc_bus.mtx, 1);
|
2454 usb2_pause_mtx(&sc->sc_bus.bus_mtx, 1); |
2455 } 2456 2457 DPRINTFN(4, "uhci port %d reset, status1 = 0x%04x\n", 2458 index, UREAD2(sc, port)); 2459 2460 x = URWMASK(UREAD2(sc, port)); 2461 UWRITE2(sc, port, x | UHCI_PORTSC_PE); 2462 2463 for (lim = 0; lim < 12; lim++) { 2464 2465 if (use_polling) { 2466 /* polling */ 2467 DELAY(USB_PORT_RESET_DELAY * 1000); 2468 } else {
|
2469 usb2_pause_mtx(&sc->sc_bus.mtx,
|
2469 usb2_pause_mtx(&sc->sc_bus.bus_mtx, |
2470 USB_PORT_RESET_DELAY); 2471 } 2472 2473 x = UREAD2(sc, port); 2474 2475 DPRINTFN(4, "uhci port %d iteration %u, status = 0x%04x\n", 2476 index, lim, x); 2477 2478 if (!(x & UHCI_PORTSC_CCS)) { 2479 /* 2480 * No device is connected (or was disconnected 2481 * during reset). Consider the port reset. 2482 * The delay must be long enough to ensure on 2483 * the initial iteration that the device 2484 * connection will have been registered. 50ms 2485 * appears to be sufficient, but 20ms is not. 2486 */ 2487 DPRINTFN(4, "uhci port %d loop %u, device detached\n", 2488 index, lim); 2489 goto done; 2490 } 2491 if (x & (UHCI_PORTSC_POEDC | UHCI_PORTSC_CSC)) { 2492 /* 2493 * Port enabled changed and/or connection 2494 * status changed were set. Reset either or 2495 * both raised flags (by writing a 1 to that 2496 * bit), and wait again for state to settle. 2497 */ 2498 UWRITE2(sc, port, URWMASK(x) | 2499 (x & (UHCI_PORTSC_POEDC | UHCI_PORTSC_CSC))); 2500 continue; 2501 } 2502 if (x & UHCI_PORTSC_PE) { 2503 /* port is enabled */ 2504 goto done; 2505 } 2506 UWRITE2(sc, port, URWMASK(x) | UHCI_PORTSC_PE); 2507 } 2508 2509 DPRINTFN(2, "uhci port %d reset timed out\n", index); 2510 return (USB_ERR_TIMEOUT); 2511 2512done: 2513 DPRINTFN(4, "uhci port %d reset, status2 = 0x%04x\n", 2514 index, UREAD2(sc, port)); 2515 2516 sc->sc_isreset = 1; 2517 return (USB_ERR_NORMAL_COMPLETION); 2518} 2519 2520static void 2521uhci_root_ctrl_enter(struct usb2_xfer *xfer) 2522{ 2523 return; 2524} 2525 2526static void 2527uhci_root_ctrl_start(struct usb2_xfer *xfer) 2528{ 2529 uhci_softc_t *sc = xfer->usb2_sc; 2530 2531 DPRINTF("\n"); 2532 2533 sc->sc_root_ctrl.xfer = xfer; 2534 2535 usb2_config_td_queue_command 2536 (&sc->sc_config_td, NULL, &uhci_root_ctrl_task, 0, 0); 2537 2538 return; 2539} 2540 2541static void 2542uhci_root_ctrl_task(struct uhci_softc *sc, 2543 struct uhci_config_copy *cc, uint16_t refcount) 2544{ 2545 uhci_root_ctrl_poll(sc); 2546 return; 2547} 2548 2549static void 2550uhci_root_ctrl_done(struct usb2_xfer *xfer, 2551 struct usb2_sw_transfer *std) 2552{ 2553 uhci_softc_t *sc = xfer->usb2_sc; 2554 char *ptr; 2555 uint16_t x; 2556 uint16_t port; 2557 uint16_t value; 2558 uint16_t index; 2559 uint16_t status; 2560 uint16_t change; 2561 uint8_t use_polling; 2562
|
2563 mtx_assert(&sc->sc_bus.mtx, MA_OWNED);
|
2563 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); |
2564 2565 if (std->state != USB_SW_TR_SETUP) { 2566 if (std->state == USB_SW_TR_PRE_CALLBACK) { 2567 /* transfer transferred */ 2568 uhci_device_done(xfer, std->err); 2569 } 2570 goto done; 2571 } 2572 /* buffer reset */ 2573 std->ptr = sc->sc_hub_desc.temp; 2574 std->len = 0; 2575 2576 value = UGETW(std->req.wValue); 2577 index = UGETW(std->req.wIndex); 2578
|
2579 use_polling = mtx_owned(xfer->priv_mtx) ? 1 : 0;
|
2579 use_polling = mtx_owned(xfer->xfer_mtx) ? 1 : 0; |
2580 2581 DPRINTFN(3, "type=0x%02x request=0x%02x wLen=0x%04x " 2582 "wValue=0x%04x wIndex=0x%04x\n", 2583 std->req.bmRequestType, std->req.bRequest, 2584 UGETW(std->req.wLength), value, index); 2585 2586#define C(x,y) ((x) | ((y) << 8)) 2587 switch (C(std->req.bRequest, std->req.bmRequestType)) { 2588 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 2589 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 2590 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 2591 /* 2592 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 2593 * for the integrated root hub. 2594 */ 2595 break; 2596 case C(UR_GET_CONFIG, UT_READ_DEVICE): 2597 std->len = 1; 2598 sc->sc_hub_desc.temp[0] = sc->sc_conf; 2599 break; 2600 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2601 switch (value >> 8) { 2602 case UDESC_DEVICE: 2603 if ((value & 0xff) != 0) { 2604 std->err = USB_ERR_IOERROR; 2605 goto done; 2606 } 2607 std->len = sizeof(uhci_devd); 2608 sc->sc_hub_desc.devd = uhci_devd; 2609 break; 2610 2611 case UDESC_CONFIG: 2612 if ((value & 0xff) != 0) { 2613 std->err = USB_ERR_IOERROR; 2614 goto done; 2615 } 2616 std->len = sizeof(uhci_confd); 2617 std->ptr = USB_ADD_BYTES(&uhci_confd, 0); 2618 break; 2619 2620 case UDESC_STRING: 2621 switch (value & 0xff) { 2622 case 0: /* Language table */ 2623 ptr = "\001"; 2624 break; 2625 2626 case 1: /* Vendor */ 2627 ptr = sc->sc_vendor; 2628 break; 2629 2630 case 2: /* Product */ 2631 ptr = "UHCI root HUB"; 2632 break; 2633 2634 default: 2635 ptr = ""; 2636 break; 2637 } 2638 2639 std->len = usb2_make_str_desc 2640 (sc->sc_hub_desc.temp, 2641 sizeof(sc->sc_hub_desc.temp), 2642 ptr); 2643 break; 2644 2645 default: 2646 std->err = USB_ERR_IOERROR; 2647 goto done; 2648 } 2649 break; 2650 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 2651 std->len = 1; 2652 sc->sc_hub_desc.temp[0] = 0; 2653 break; 2654 case C(UR_GET_STATUS, UT_READ_DEVICE): 2655 std->len = 2; 2656 USETW(sc->sc_hub_desc.stat.wStatus, UDS_SELF_POWERED); 2657 break; 2658 case C(UR_GET_STATUS, UT_READ_INTERFACE): 2659 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 2660 std->len = 2; 2661 USETW(sc->sc_hub_desc.stat.wStatus, 0); 2662 break; 2663 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 2664 if (value >= USB_MAX_DEVICES) { 2665 std->err = USB_ERR_IOERROR; 2666 goto done; 2667 } 2668 sc->sc_addr = value; 2669 break; 2670 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 2671 if ((value != 0) && (value != 1)) { 2672 std->err = USB_ERR_IOERROR; 2673 goto done; 2674 } 2675 sc->sc_conf = value; 2676 break; 2677 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 2678 break; 2679 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 2680 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 2681 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 2682 std->err = USB_ERR_IOERROR; 2683 goto done; 2684 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 2685 break; 2686 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 2687 break; 2688 /* Hub requests */ 2689 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2690 break; 2691 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2692 DPRINTFN(4, "UR_CLEAR_PORT_FEATURE " 2693 "port=%d feature=%d\n", 2694 index, value); 2695 if (index == 1) 2696 port = UHCI_PORTSC1; 2697 else if (index == 2) 2698 port = UHCI_PORTSC2; 2699 else { 2700 std->err = USB_ERR_IOERROR; 2701 goto done; 2702 } 2703 switch (value) { 2704 case UHF_PORT_ENABLE: 2705 x = URWMASK(UREAD2(sc, port)); 2706 UWRITE2(sc, port, x & ~UHCI_PORTSC_PE); 2707 break; 2708 case UHF_PORT_SUSPEND: 2709 x = URWMASK(UREAD2(sc, port)); 2710 UWRITE2(sc, port, x & ~UHCI_PORTSC_SUSP); 2711 break; 2712 case UHF_PORT_RESET: 2713 x = URWMASK(UREAD2(sc, port)); 2714 UWRITE2(sc, port, x & ~UHCI_PORTSC_PR); 2715 break; 2716 case UHF_C_PORT_CONNECTION: 2717 x = URWMASK(UREAD2(sc, port)); 2718 UWRITE2(sc, port, x | UHCI_PORTSC_CSC); 2719 break; 2720 case UHF_C_PORT_ENABLE: 2721 x = URWMASK(UREAD2(sc, port)); 2722 UWRITE2(sc, port, x | UHCI_PORTSC_POEDC); 2723 break; 2724 case UHF_C_PORT_OVER_CURRENT: 2725 x = URWMASK(UREAD2(sc, port)); 2726 UWRITE2(sc, port, x | UHCI_PORTSC_OCIC); 2727 break; 2728 case UHF_C_PORT_RESET: 2729 sc->sc_isreset = 0; 2730 std->err = USB_ERR_NORMAL_COMPLETION; 2731 goto done; 2732 case UHF_PORT_CONNECTION: 2733 case UHF_PORT_OVER_CURRENT: 2734 case UHF_PORT_POWER: 2735 case UHF_PORT_LOW_SPEED: 2736 case UHF_C_PORT_SUSPEND: 2737 default: 2738 std->err = USB_ERR_IOERROR; 2739 goto done; 2740 } 2741 break; 2742 case C(UR_GET_BUS_STATE, UT_READ_CLASS_OTHER): 2743 if (index == 1) 2744 port = UHCI_PORTSC1; 2745 else if (index == 2) 2746 port = UHCI_PORTSC2; 2747 else { 2748 std->err = USB_ERR_IOERROR; 2749 goto done; 2750 } 2751 std->len = 1; 2752 sc->sc_hub_desc.temp[0] = 2753 ((UREAD2(sc, port) & UHCI_PORTSC_LS) >> 2754 UHCI_PORTSC_LS_SHIFT); 2755 break; 2756 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2757 if ((value & 0xff) != 0) { 2758 std->err = USB_ERR_IOERROR; 2759 goto done; 2760 } 2761 std->len = sizeof(uhci_hubd_piix); 2762 std->ptr = USB_ADD_BYTES(&uhci_hubd_piix, 0); 2763 break; 2764 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2765 std->len = 16; 2766 bzero(sc->sc_hub_desc.temp, 16); 2767 break; 2768 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2769 if (index == 1) 2770 port = UHCI_PORTSC1; 2771 else if (index == 2) 2772 port = UHCI_PORTSC2; 2773 else { 2774 std->err = USB_ERR_IOERROR; 2775 goto done; 2776 } 2777 x = UREAD2(sc, port); 2778 status = change = 0; 2779 if (x & UHCI_PORTSC_CCS) 2780 status |= UPS_CURRENT_CONNECT_STATUS; 2781 if (x & UHCI_PORTSC_CSC) 2782 change |= UPS_C_CONNECT_STATUS; 2783 if (x & UHCI_PORTSC_PE) 2784 status |= UPS_PORT_ENABLED; 2785 if (x & UHCI_PORTSC_POEDC) 2786 change |= UPS_C_PORT_ENABLED; 2787 if (x & UHCI_PORTSC_OCI) 2788 status |= UPS_OVERCURRENT_INDICATOR; 2789 if (x & UHCI_PORTSC_OCIC) 2790 change |= UPS_C_OVERCURRENT_INDICATOR; 2791 if (x & UHCI_PORTSC_SUSP) 2792 status |= UPS_SUSPEND; 2793 if (x & UHCI_PORTSC_LSDA) 2794 status |= UPS_LOW_SPEED; 2795 status |= UPS_PORT_POWER; 2796 if (sc->sc_isreset) 2797 change |= UPS_C_PORT_RESET; 2798 USETW(sc->sc_hub_desc.ps.wPortStatus, status); 2799 USETW(sc->sc_hub_desc.ps.wPortChange, change); 2800 std->len = sizeof(sc->sc_hub_desc.ps); 2801 break; 2802 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2803 std->err = USB_ERR_IOERROR; 2804 goto done; 2805 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2806 break; 2807 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2808 if (index == 1) 2809 port = UHCI_PORTSC1; 2810 else if (index == 2) 2811 port = UHCI_PORTSC2; 2812 else { 2813 std->err = USB_ERR_IOERROR; 2814 goto done; 2815 } 2816 switch (value) { 2817 case UHF_PORT_ENABLE: 2818 x = URWMASK(UREAD2(sc, port)); 2819 UWRITE2(sc, port, x | UHCI_PORTSC_PE); 2820 break; 2821 case UHF_PORT_SUSPEND: 2822 x = URWMASK(UREAD2(sc, port)); 2823 UWRITE2(sc, port, x | UHCI_PORTSC_SUSP); 2824 break; 2825 case UHF_PORT_RESET: 2826 std->err = uhci_portreset(sc, index, use_polling); 2827 goto done; 2828 case UHF_PORT_POWER: 2829 /* pretend we turned on power */ 2830 std->err = USB_ERR_NORMAL_COMPLETION; 2831 goto done; 2832 case UHF_C_PORT_CONNECTION: 2833 case UHF_C_PORT_ENABLE: 2834 case UHF_C_PORT_OVER_CURRENT: 2835 case UHF_PORT_CONNECTION: 2836 case UHF_PORT_OVER_CURRENT: 2837 case UHF_PORT_LOW_SPEED: 2838 case UHF_C_PORT_SUSPEND: 2839 case UHF_C_PORT_RESET: 2840 default: 2841 std->err = USB_ERR_IOERROR; 2842 goto done; 2843 } 2844 break; 2845 default: 2846 std->err = USB_ERR_IOERROR; 2847 goto done; 2848 } 2849done: 2850 return; 2851} 2852 2853static void 2854uhci_root_ctrl_poll(struct uhci_softc *sc) 2855{ 2856 usb2_sw_transfer(&sc->sc_root_ctrl, 2857 &uhci_root_ctrl_done); 2858 return; 2859} 2860 2861struct usb2_pipe_methods uhci_root_ctrl_methods = 2862{ 2863 .open = uhci_root_ctrl_open, 2864 .close = uhci_root_ctrl_close, 2865 .enter = uhci_root_ctrl_enter, 2866 .start = uhci_root_ctrl_start, 2867 .enter_is_cancelable = 1, 2868 .start_is_cancelable = 0, 2869}; 2870 2871/*------------------------------------------------------------------------* 2872 * uhci root interrupt support 2873 *------------------------------------------------------------------------*/ 2874static void 2875uhci_root_intr_open(struct usb2_xfer *xfer) 2876{ 2877 return; 2878} 2879 2880static void 2881uhci_root_intr_close(struct usb2_xfer *xfer) 2882{ 2883 uhci_softc_t *sc = xfer->usb2_sc; 2884 2885 if (sc->sc_root_intr.xfer == xfer) { 2886 sc->sc_root_intr.xfer = NULL; 2887 } 2888 uhci_device_done(xfer, USB_ERR_CANCELLED); 2889 return; 2890} 2891 2892static void 2893uhci_root_intr_enter(struct usb2_xfer *xfer) 2894{ 2895 return; 2896} 2897 2898static void 2899uhci_root_intr_start(struct usb2_xfer *xfer) 2900{ 2901 uhci_softc_t *sc = xfer->usb2_sc; 2902 2903 sc->sc_root_intr.xfer = xfer; 2904 2905 usb2_transfer_timeout_ms(xfer, 2906 &uhci_root_intr_check, xfer->interval); 2907 return; 2908} 2909 2910static void 2911uhci_root_intr_done(struct usb2_xfer *xfer, 2912 struct usb2_sw_transfer *std) 2913{ 2914 uhci_softc_t *sc = xfer->usb2_sc; 2915
|
2916 mtx_assert(&sc->sc_bus.mtx, MA_OWNED);
|
2916 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); |
2917 2918 if (std->state != USB_SW_TR_PRE_DATA) { 2919 if (std->state == USB_SW_TR_PRE_CALLBACK) { 2920 /* transfer is transferred */ 2921 uhci_device_done(xfer, std->err); 2922 } 2923 goto done; 2924 } 2925 /* setup buffer */ 2926 std->ptr = sc->sc_hub_idata; 2927 std->len = sizeof(sc->sc_hub_idata); 2928done: 2929 return; 2930} 2931 2932/* 2933 * this routine is executed periodically and simulates interrupts 2934 * from the root controller interrupt pipe for port status change 2935 */ 2936static void 2937uhci_root_intr_check(void *arg) 2938{ 2939 struct usb2_xfer *xfer = arg; 2940 uhci_softc_t *sc = xfer->usb2_sc; 2941 2942 DPRINTFN(21, "\n"); 2943
|
2944 mtx_assert(&sc->sc_bus.mtx, MA_OWNED);
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2944 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); |
2945 2946 sc->sc_hub_idata[0] = 0; 2947 2948 if (UREAD2(sc, UHCI_PORTSC1) & (UHCI_PORTSC_CSC | UHCI_PORTSC_OCIC)) { 2949 sc->sc_hub_idata[0] |= 1 << 1; 2950 } 2951 if (UREAD2(sc, UHCI_PORTSC2) & (UHCI_PORTSC_CSC | UHCI_PORTSC_OCIC)) { 2952 sc->sc_hub_idata[0] |= 1 << 2; 2953 } 2954 if ((sc->sc_hub_idata[0] == 0) || !(UREAD2(sc, UHCI_CMD) & UHCI_CMD_RS)) { 2955 /* 2956 * no change or controller not running, try again in a while 2957 */ 2958 uhci_root_intr_start(xfer); 2959 } else { 2960 usb2_sw_transfer(&sc->sc_root_intr, 2961 &uhci_root_intr_done); 2962 }
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2963 mtx_unlock(&sc->sc_bus.mtx);
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2963 USB_BUS_UNLOCK(&sc->sc_bus); |
2964 return; 2965} 2966 2967struct usb2_pipe_methods uhci_root_intr_methods = 2968{ 2969 .open = uhci_root_intr_open, 2970 .close = uhci_root_intr_close, 2971 .enter = uhci_root_intr_enter, 2972 .start = uhci_root_intr_start, 2973 .enter_is_cancelable = 1, 2974 .start_is_cancelable = 1, 2975}; 2976 2977static void 2978uhci_xfer_setup(struct usb2_setup_params *parm) 2979{ 2980 struct usb2_page_search page_info; 2981 struct usb2_page_cache *pc; 2982 uhci_softc_t *sc; 2983 struct usb2_xfer *xfer; 2984 void *last_obj; 2985 uint32_t ntd; 2986 uint32_t nqh; 2987 uint32_t nfixup; 2988 uint32_t n; 2989 uint16_t align; 2990 2991 sc = UHCI_BUS2SC(parm->udev->bus); 2992 xfer = parm->curr_xfer; 2993 2994 /* 2995 * setup xfer 2996 */ 2997 xfer->usb2_sc = sc; 2998 2999 parm->hc_max_packet_size = 0x500; 3000 parm->hc_max_packet_count = 1; 3001 parm->hc_max_frame_size = 0x500; 3002 3003 /* 3004 * compute ntd and nqh 3005 */ 3006 if (parm->methods == &uhci_device_ctrl_methods) { 3007 xfer->flags_int.bdma_enable = 1; 3008 xfer->flags_int.bdma_no_post_sync = 1; 3009 3010 usb2_transfer_setup_sub(parm); 3011 3012 /* see EHCI HC driver for proof of "ntd" formula */ 3013 3014 nqh = 1; 3015 ntd = ((2 * xfer->nframes) + 1 /* STATUS */ 3016 + (xfer->max_data_length / xfer->max_frame_size)); 3017 3018 } else if (parm->methods == &uhci_device_bulk_methods) { 3019 xfer->flags_int.bdma_enable = 1; 3020 xfer->flags_int.bdma_no_post_sync = 1; 3021 3022 usb2_transfer_setup_sub(parm); 3023 3024 nqh = 1; 3025 ntd = ((2 * xfer->nframes) 3026 + (xfer->max_data_length / xfer->max_frame_size)); 3027 3028 } else if (parm->methods == &uhci_device_intr_methods) { 3029 xfer->flags_int.bdma_enable = 1; 3030 xfer->flags_int.bdma_no_post_sync = 1; 3031 3032 usb2_transfer_setup_sub(parm); 3033 3034 nqh = 1; 3035 ntd = ((2 * xfer->nframes) 3036 + (xfer->max_data_length / xfer->max_frame_size)); 3037 3038 } else if (parm->methods == &uhci_device_isoc_methods) { 3039 xfer->flags_int.bdma_enable = 1; 3040 xfer->flags_int.bdma_no_post_sync = 1; 3041 3042 usb2_transfer_setup_sub(parm); 3043 3044 nqh = 0; 3045 ntd = xfer->nframes; 3046 3047 } else { 3048 3049 usb2_transfer_setup_sub(parm); 3050 3051 nqh = 0; 3052 ntd = 0; 3053 } 3054 3055 if (parm->err) { 3056 return; 3057 } 3058 /* 3059 * NOTE: the UHCI controller requires that 3060 * every packet must be contiguous on 3061 * the same USB memory page ! 3062 */ 3063 nfixup = (parm->bufsize / USB_PAGE_SIZE) + 1; 3064 3065 /* 3066 * Compute a suitable power of two alignment 3067 * for our "max_frame_size" fixup buffer(s): 3068 */ 3069 align = xfer->max_frame_size; 3070 n = 0; 3071 while (align) { 3072 align >>= 1; 3073 n++; 3074 } 3075 3076 /* check for power of two */ 3077 if (!(xfer->max_frame_size & 3078 (xfer->max_frame_size - 1))) { 3079 n--; 3080 } 3081 /* 3082 * We don't allow alignments of 3083 * less than 8 bytes: 3084 * 3085 * NOTE: Allocating using an aligment 3086 * of 1 byte has special meaning! 3087 */ 3088 if (n < 3) { 3089 n = 3; 3090 } 3091 align = (1 << n); 3092 3093 if (usb2_transfer_setup_sub_malloc( 3094 parm, &pc, xfer->max_frame_size, 3095 align, nfixup)) { 3096 parm->err = USB_ERR_NOMEM; 3097 return; 3098 } 3099 xfer->buf_fixup = pc; 3100 3101alloc_dma_set: 3102 3103 if (parm->err) { 3104 return; 3105 } 3106 last_obj = NULL; 3107 3108 if (usb2_transfer_setup_sub_malloc( 3109 parm, &pc, sizeof(uhci_td_t), 3110 UHCI_TD_ALIGN, ntd)) { 3111 parm->err = USB_ERR_NOMEM; 3112 return; 3113 } 3114 if (parm->buf) { 3115 for (n = 0; n != ntd; n++) { 3116 uhci_td_t *td; 3117 3118 usb2_get_page(pc + n, 0, &page_info); 3119 3120 td = page_info.buffer; 3121 3122 /* init TD */ 3123 if ((parm->methods == &uhci_device_bulk_methods) || 3124 (parm->methods == &uhci_device_ctrl_methods) || 3125 (parm->methods == &uhci_device_intr_methods)) { 3126 /* set depth first bit */ 3127 td->td_self = htole32(page_info.physaddr | 3128 UHCI_PTR_TD | UHCI_PTR_VF); 3129 } else { 3130 td->td_self = htole32(page_info.physaddr | 3131 UHCI_PTR_TD); 3132 } 3133 3134 td->obj_next = last_obj; 3135 td->page_cache = pc + n; 3136 3137 last_obj = td; 3138 3139 usb2_pc_cpu_flush(pc + n); 3140 } 3141 } 3142 xfer->td_start[xfer->flags_int.curr_dma_set] = last_obj; 3143 3144 last_obj = NULL; 3145 3146 if (usb2_transfer_setup_sub_malloc( 3147 parm, &pc, sizeof(uhci_qh_t), 3148 UHCI_QH_ALIGN, nqh)) { 3149 parm->err = USB_ERR_NOMEM; 3150 return; 3151 } 3152 if (parm->buf) { 3153 for (n = 0; n != nqh; n++) { 3154 uhci_qh_t *qh; 3155 3156 usb2_get_page(pc + n, 0, &page_info); 3157 3158 qh = page_info.buffer; 3159 3160 /* init QH */ 3161 qh->qh_self = htole32(page_info.physaddr | UHCI_PTR_QH); 3162 qh->obj_next = last_obj; 3163 qh->page_cache = pc + n; 3164 3165 last_obj = qh; 3166 3167 usb2_pc_cpu_flush(pc + n); 3168 } 3169 } 3170 xfer->qh_start[xfer->flags_int.curr_dma_set] = last_obj; 3171 3172 if (!xfer->flags_int.curr_dma_set) { 3173 xfer->flags_int.curr_dma_set = 1; 3174 goto alloc_dma_set; 3175 } 3176 return; 3177} 3178 3179static void 3180uhci_pipe_init(struct usb2_device *udev, struct usb2_endpoint_descriptor *edesc, 3181 struct usb2_pipe *pipe) 3182{ 3183 uhci_softc_t *sc = UHCI_BUS2SC(udev->bus); 3184 3185 DPRINTFN(2, "pipe=%p, addr=%d, endpt=%d, mode=%d (%d)\n", 3186 pipe, udev->address, 3187 edesc->bEndpointAddress, udev->flags.usb2_mode, 3188 sc->sc_addr); 3189 3190 if (udev->flags.usb2_mode != USB_MODE_HOST) { 3191 /* not supported */ 3192 return; 3193 } 3194 if (udev->device_index == sc->sc_addr) { 3195 switch (edesc->bEndpointAddress) { 3196 case USB_CONTROL_ENDPOINT: 3197 pipe->methods = &uhci_root_ctrl_methods; 3198 break; 3199 case UE_DIR_IN | UHCI_INTR_ENDPT: 3200 pipe->methods = &uhci_root_intr_methods; 3201 break; 3202 default: 3203 /* do nothing */ 3204 break; 3205 } 3206 } else { 3207 switch (edesc->bmAttributes & UE_XFERTYPE) { 3208 case UE_CONTROL: 3209 pipe->methods = &uhci_device_ctrl_methods; 3210 break; 3211 case UE_INTERRUPT: 3212 pipe->methods = &uhci_device_intr_methods; 3213 break; 3214 case UE_ISOCHRONOUS: 3215 if (udev->speed == USB_SPEED_FULL) { 3216 pipe->methods = &uhci_device_isoc_methods; 3217 } 3218 break; 3219 case UE_BULK: 3220 if (udev->speed != USB_SPEED_LOW) { 3221 pipe->methods = &uhci_device_bulk_methods; 3222 } 3223 break; 3224 default: 3225 /* do nothing */ 3226 break; 3227 } 3228 } 3229 return; 3230} 3231 3232static void 3233uhci_xfer_unsetup(struct usb2_xfer *xfer) 3234{ 3235 return; 3236} 3237 3238static void 3239uhci_get_dma_delay(struct usb2_bus *bus, uint32_t *pus) 3240{ 3241 /* 3242 * Wait until hardware has finished any possible use of the 3243 * transfer descriptor(s) and QH 3244 */ 3245 *pus = (1125); /* microseconds */ 3246 return; 3247} 3248 3249struct usb2_bus_methods uhci_bus_methods = 3250{ 3251 .pipe_init = uhci_pipe_init, 3252 .xfer_setup = uhci_xfer_setup, 3253 .xfer_unsetup = uhci_xfer_unsetup, 3254 .do_poll = uhci_do_poll, 3255 .get_dma_delay = uhci_get_dma_delay, 3256};
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