1/*-
2 * Copyright (c) 2008 Hans Petter Selasky. All rights reserved.
3 * Copyright (c) 1998 The NetBSD Foundation, Inc. All rights reserved.
4 * Copyright (c) 1998 Lennart Augustsson. All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 */
27
28#include <sys/cdefs.h>
29__FBSDID("$FreeBSD: head/sys/dev/usb2/controller/ohci2.c 184610 2008-11-04 02:31:03Z alfred $");
30
31/*
32 * USB Open Host Controller driver.
33 *
34 * OHCI spec: http://www.compaq.com/productinfo/development/openhci.html
35 * USB spec: http://www.usb.org/developers/docs/usbspec.zip
36 */
37
38#include <dev/usb2/include/usb2_standard.h>
39#include <dev/usb2/include/usb2_mfunc.h>
40#include <dev/usb2/include/usb2_error.h>
41#include <dev/usb2/include/usb2_defs.h>
42
43#define USB_DEBUG_VAR ohcidebug
44#define usb2_config_td_cc ohci_config_copy
45#define usb2_config_td_softc ohci_softc
46
47#include <dev/usb2/core/usb2_core.h>
48#include <dev/usb2/core/usb2_debug.h>
49#include <dev/usb2/core/usb2_busdma.h>
50#include <dev/usb2/core/usb2_process.h>
51#include <dev/usb2/core/usb2_config_td.h>
52#include <dev/usb2/core/usb2_sw_transfer.h>
53#include <dev/usb2/core/usb2_transfer.h>
54#include <dev/usb2/core/usb2_device.h>
55#include <dev/usb2/core/usb2_hub.h>
56#include <dev/usb2/core/usb2_util.h>
57
58#include <dev/usb2/controller/usb2_controller.h>
59#include <dev/usb2/controller/usb2_bus.h>
60#include <dev/usb2/controller/ohci2.h>
61
62#define OHCI_BUS2SC(bus) ((ohci_softc_t *)(((uint8_t *)(bus)) - \
63 USB_P2U(&(((ohci_softc_t *)0)->sc_bus))))
64
65#if USB_DEBUG
66static int ohcidebug = 0;
67
68SYSCTL_NODE(_hw_usb2, OID_AUTO, ohci, CTLFLAG_RW, 0, "USB ohci");
69SYSCTL_INT(_hw_usb2_ohci, OID_AUTO, debug, CTLFLAG_RW,
70 &ohcidebug, 0, "ohci debug level");
71static void ohci_dumpregs(ohci_softc_t *);
72static void ohci_dump_tds(ohci_td_t *);
73static uint8_t ohci_dump_td(ohci_td_t *);
74static void ohci_dump_ed(ohci_ed_t *);
75static uint8_t ohci_dump_itd(ohci_itd_t *);
76static void ohci_dump_itds(ohci_itd_t *);
77
78#endif
79
80#define OBARR(sc) bus_space_barrier((sc)->sc_io_tag, (sc)->sc_io_hdl, 0, (sc)->sc_io_size, \
81 BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE)
82#define OWRITE1(sc, r, x) \
83 do { OBARR(sc); bus_space_write_1((sc)->sc_io_tag, (sc)->sc_io_hdl, (r), (x)); } while (0)
84#define OWRITE2(sc, r, x) \
85 do { OBARR(sc); bus_space_write_2((sc)->sc_io_tag, (sc)->sc_io_hdl, (r), (x)); } while (0)
86#define OWRITE4(sc, r, x) \
87 do { OBARR(sc); bus_space_write_4((sc)->sc_io_tag, (sc)->sc_io_hdl, (r), (x)); } while (0)
88#define OREAD1(sc, r) (OBARR(sc), bus_space_read_1((sc)->sc_io_tag, (sc)->sc_io_hdl, (r)))
89#define OREAD2(sc, r) (OBARR(sc), bus_space_read_2((sc)->sc_io_tag, (sc)->sc_io_hdl, (r)))
90#define OREAD4(sc, r) (OBARR(sc), bus_space_read_4((sc)->sc_io_tag, (sc)->sc_io_hdl, (r)))
91
92#define OHCI_INTR_ENDPT 1
93
94extern struct usb2_bus_methods ohci_bus_methods;
95extern struct usb2_pipe_methods ohci_device_bulk_methods;
96extern struct usb2_pipe_methods ohci_device_ctrl_methods;
97extern struct usb2_pipe_methods ohci_device_intr_methods;
98extern struct usb2_pipe_methods ohci_device_isoc_methods;
99extern struct usb2_pipe_methods ohci_root_ctrl_methods;
100extern struct usb2_pipe_methods ohci_root_intr_methods;
101
102static usb2_config_td_command_t ohci_root_ctrl_task;
103static void ohci_root_ctrl_poll(struct ohci_softc *sc);
104static void ohci_do_poll(struct usb2_bus *bus);
105static void ohci_device_done(struct usb2_xfer *xfer, usb2_error_t error);
106
107static usb2_sw_transfer_func_t ohci_root_intr_done;
108static usb2_sw_transfer_func_t ohci_root_ctrl_done;
109static void ohci_timeout(void *arg);
110static uint8_t ohci_check_transfer(struct usb2_xfer *xfer);
111
112struct ohci_std_temp {
113 struct usb2_page_cache *pc;
114 ohci_td_t *td;
115 ohci_td_t *td_next;
116 uint32_t average;
117 uint32_t td_flags;
118 uint32_t len;
119 uint16_t max_frame_size;
120 uint8_t shortpkt;
121 uint8_t setup_alt_next;
122 uint8_t short_frames_ok;
123};
124
125static struct ohci_hcca *
126ohci_get_hcca(ohci_softc_t *sc)
127{
128 usb2_pc_cpu_invalidate(&sc->sc_hw.hcca_pc);
129 return (sc->sc_hcca_p);
130}
131
132void
133ohci_iterate_hw_softc(struct usb2_bus *bus, usb2_bus_mem_sub_cb_t *cb)
134{
135 struct ohci_softc *sc = OHCI_BUS2SC(bus);
136 uint32_t i;
137
138 cb(bus, &sc->sc_hw.hcca_pc, &sc->sc_hw.hcca_pg,
139 sizeof(ohci_hcca_t), OHCI_HCCA_ALIGN);
140
141 cb(bus, &sc->sc_hw.ctrl_start_pc, &sc->sc_hw.ctrl_start_pg,
142 sizeof(ohci_ed_t), OHCI_ED_ALIGN);
143
144 cb(bus, &sc->sc_hw.bulk_start_pc, &sc->sc_hw.bulk_start_pg,
145 sizeof(ohci_ed_t), OHCI_ED_ALIGN);
146
147 cb(bus, &sc->sc_hw.isoc_start_pc, &sc->sc_hw.isoc_start_pg,
148 sizeof(ohci_ed_t), OHCI_ED_ALIGN);
149
150 for (i = 0; i != OHCI_NO_EDS; i++) {
151 cb(bus, sc->sc_hw.intr_start_pc + i, sc->sc_hw.intr_start_pg + i,
152 sizeof(ohci_ed_t), OHCI_ED_ALIGN);
153 }
154 return;
155}
156
157static usb2_error_t
158ohci_controller_init(ohci_softc_t *sc)
159{
160 struct usb2_page_search buf_res;
161 uint32_t i;
162 uint32_t ctl;
163 uint32_t ival;
164 uint32_t hcr;
165 uint32_t fm;
166 uint32_t per;
167 uint32_t desca;
168
169 /* Determine in what context we are running. */
170 ctl = OREAD4(sc, OHCI_CONTROL);
171 if (ctl & OHCI_IR) {
172 /* SMM active, request change */
173 DPRINTF("SMM active, request owner change\n");
174 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_OCR);
175 for (i = 0; (i < 100) && (ctl & OHCI_IR); i++) {
176 usb2_pause_mtx(&sc->sc_bus.mtx, 1);
177 ctl = OREAD4(sc, OHCI_CONTROL);
178 }
179 if (ctl & OHCI_IR) {
180 device_printf(sc->sc_bus.bdev,
181 "SMM does not respond, resetting\n");
182 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET);
183 goto reset;
184 }
185 } else {
186 DPRINTF("cold started\n");
187reset:
188 /* controller was cold started */
189 usb2_pause_mtx(&sc->sc_bus.mtx,
190 USB_BUS_RESET_DELAY);
191 }
192
193 /*
194 * This reset should not be necessary according to the OHCI spec, but
195 * without it some controllers do not start.
196 */
197 DPRINTF("%s: resetting\n", device_get_nameunit(sc->sc_bus.bdev));
198 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET);
199
200 usb2_pause_mtx(&sc->sc_bus.mtx,
201 USB_BUS_RESET_DELAY);
202
203 /* we now own the host controller and the bus has been reset */
204 ival = OHCI_GET_IVAL(OREAD4(sc, OHCI_FM_INTERVAL));
205
206 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_HCR); /* Reset HC */
207 /* nominal time for a reset is 10 us */
208 for (i = 0; i < 10; i++) {
209 DELAY(10);
210 hcr = OREAD4(sc, OHCI_COMMAND_STATUS) & OHCI_HCR;
211 if (!hcr) {
212 break;
213 }
214 }
215 if (hcr) {
216 device_printf(sc->sc_bus.bdev, "reset timeout\n");
217 return (USB_ERR_IOERROR);
218 }
219#if USB_DEBUG
220 if (ohcidebug > 15) {
221 ohci_dumpregs(sc);
222 }
223#endif
224
225 /* The controller is now in SUSPEND state, we have 2ms to finish. */
226
227 /* set up HC registers */
228 usb2_get_page(&sc->sc_hw.hcca_pc, 0, &buf_res);
229 OWRITE4(sc, OHCI_HCCA, buf_res.physaddr);
230
231 usb2_get_page(&sc->sc_hw.ctrl_start_pc, 0, &buf_res);
232 OWRITE4(sc, OHCI_CONTROL_HEAD_ED, buf_res.physaddr);
233
234 usb2_get_page(&sc->sc_hw.bulk_start_pc, 0, &buf_res);
235 OWRITE4(sc, OHCI_BULK_HEAD_ED, buf_res.physaddr);
236
237 /* disable all interrupts and then switch on all desired interrupts */
238 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS);
239 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, sc->sc_eintrs | OHCI_MIE);
240 /* switch on desired functional features */
241 ctl = OREAD4(sc, OHCI_CONTROL);
242 ctl &= ~(OHCI_CBSR_MASK | OHCI_LES | OHCI_HCFS_MASK | OHCI_IR);
243 ctl |= OHCI_PLE | OHCI_IE | OHCI_CLE | OHCI_BLE |
244 OHCI_RATIO_1_4 | OHCI_HCFS_OPERATIONAL;
245 /* And finally start it! */
246 OWRITE4(sc, OHCI_CONTROL, ctl);
247
248 /*
249 * The controller is now OPERATIONAL. Set a some final
250 * registers that should be set earlier, but that the
251 * controller ignores when in the SUSPEND state.
252 */
253 fm = (OREAD4(sc, OHCI_FM_INTERVAL) & OHCI_FIT) ^ OHCI_FIT;
254 fm |= OHCI_FSMPS(ival) | ival;
255 OWRITE4(sc, OHCI_FM_INTERVAL, fm);
256 per = OHCI_PERIODIC(ival); /* 90% periodic */
257 OWRITE4(sc, OHCI_PERIODIC_START, per);
258
259 /* Fiddle the No OverCurrent Protection bit to avoid chip bug. */
260 desca = OREAD4(sc, OHCI_RH_DESCRIPTOR_A);
261 OWRITE4(sc, OHCI_RH_DESCRIPTOR_A, desca | OHCI_NOCP);
262 OWRITE4(sc, OHCI_RH_STATUS, OHCI_LPSC); /* Enable port power */
263 usb2_pause_mtx(&sc->sc_bus.mtx,
264 OHCI_ENABLE_POWER_DELAY);
265 OWRITE4(sc, OHCI_RH_DESCRIPTOR_A, desca);
266
267 /*
268 * The AMD756 requires a delay before re-reading the register,
269 * otherwise it will occasionally report 0 ports.
270 */
271 sc->sc_noport = 0;
272 for (i = 0; (i < 10) && (sc->sc_noport == 0); i++) {
273 usb2_pause_mtx(&sc->sc_bus.mtx,
274 OHCI_READ_DESC_DELAY);
275 sc->sc_noport = OHCI_GET_NDP(OREAD4(sc, OHCI_RH_DESCRIPTOR_A));
276 }
277
278#if USB_DEBUG
279 if (ohcidebug > 5) {
280 ohci_dumpregs(sc);
281 }
282#endif
283 return (USB_ERR_NORMAL_COMPLETION);
284}
285
286static struct ohci_ed *
287ohci_init_ed(struct usb2_page_cache *pc)
288{
289 struct usb2_page_search buf_res;
290 struct ohci_ed *ed;
291
292 usb2_get_page(pc, 0, &buf_res);
293
294 ed = buf_res.buffer;
295
296 ed->ed_self = htole32(buf_res.physaddr);
297 ed->ed_flags = htole32(OHCI_ED_SKIP);
298 ed->page_cache = pc;
299
300 return (ed);
301}
302
303usb2_error_t
304ohci_init(ohci_softc_t *sc)
305{
306 struct usb2_page_search buf_res;
307 uint16_t i;
308 uint16_t bit;
309 uint16_t x;
310 uint16_t y;
311
312 mtx_lock(&sc->sc_bus.mtx);
313
314 DPRINTF("start\n");
315
316 sc->sc_eintrs = OHCI_NORMAL_INTRS;
317
318 /*
319 * Setup all ED's
320 */
321
322 sc->sc_ctrl_p_last =
323 ohci_init_ed(&sc->sc_hw.ctrl_start_pc);
324
325 sc->sc_bulk_p_last =
326 ohci_init_ed(&sc->sc_hw.bulk_start_pc);
327
328 sc->sc_isoc_p_last =
329 ohci_init_ed(&sc->sc_hw.isoc_start_pc);
330
331 for (i = 0; i != OHCI_NO_EDS; i++) {
332 sc->sc_intr_p_last[i] =
333 ohci_init_ed(sc->sc_hw.intr_start_pc + i);
334 }
335
336 /*
337 * the QHs are arranged to give poll intervals that are
338 * powers of 2 times 1ms
339 */
340 bit = OHCI_NO_EDS / 2;
341 while (bit) {
342 x = bit;
343 while (x & bit) {
344 ohci_ed_t *ed_x;
345 ohci_ed_t *ed_y;
346
347 y = (x ^ bit) | (bit / 2);
348
349 /*
350 * the next QH has half the poll interval
351 */
352 ed_x = sc->sc_intr_p_last[x];
353 ed_y = sc->sc_intr_p_last[y];
354
355 ed_x->next = NULL;
356 ed_x->ed_next = ed_y->ed_self;
357
358 x++;
359 }
360 bit >>= 1;
361 }
362
363 if (1) {
364
365 ohci_ed_t *ed_int;
366 ohci_ed_t *ed_isc;
367
368 ed_int = sc->sc_intr_p_last[0];
369 ed_isc = sc->sc_isoc_p_last;
370
371 /* the last (1ms) QH */
372 ed_int->next = ed_isc;
373 ed_int->ed_next = ed_isc->ed_self;
374 }
375 usb2_get_page(&sc->sc_hw.hcca_pc, 0, &buf_res);
376
377 sc->sc_hcca_p = buf_res.buffer;
378
379 /*
380 * Fill HCCA interrupt table. The bit reversal is to get
381 * the tree set up properly to spread the interrupts.
382 */
383 for (i = 0; i != OHCI_NO_INTRS; i++) {
384 sc->sc_hcca_p->hcca_interrupt_table[i] =
385 sc->sc_intr_p_last[i | (OHCI_NO_EDS / 2)]->ed_self;
386 }
387 /* flush all cache into memory */
388
389 usb2_bus_mem_flush_all(&sc->sc_bus, &ohci_iterate_hw_softc);
390
391 /* set up the bus struct */
392 sc->sc_bus.methods = &ohci_bus_methods;
393
394 usb2_callout_init_mtx(&sc->sc_tmo_rhsc, &sc->sc_bus.mtx,
395 CALLOUT_RETURNUNLOCKED);
396
397#if USB_DEBUG
398 if (ohcidebug > 15) {
399 for (i = 0; i != OHCI_NO_EDS; i++) {
400 printf("ed#%d ", i);
401 ohci_dump_ed(sc->sc_intr_p_last[i]);
402 }
403 printf("iso ");
404 ohci_dump_ed(sc->sc_isoc_p_last);
405 }
406#endif
407
408 sc->sc_bus.usbrev = USB_REV_1_0;
409
410 if (ohci_controller_init(sc)) {
411 mtx_unlock(&sc->sc_bus.mtx);
412 return (USB_ERR_INVAL);
413 } else {
414 mtx_unlock(&sc->sc_bus.mtx);
415 /* catch any lost interrupts */
416 ohci_do_poll(&sc->sc_bus);
417 return (USB_ERR_NORMAL_COMPLETION);
418 }
419}
420
421/*
422 * shut down the controller when the system is going down
423 */
424void
425ohci_detach(struct ohci_softc *sc)
426{
427 mtx_lock(&sc->sc_bus.mtx);
428
429 usb2_callout_stop(&sc->sc_tmo_rhsc);
430
431 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS);
432 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET);
433
434 /* XXX let stray task complete */
435 usb2_pause_mtx(&sc->sc_bus.mtx, 50);
436
437 mtx_unlock(&sc->sc_bus.mtx);
438
439 usb2_callout_drain(&sc->sc_tmo_rhsc);
440
441 return;
442}
443
444/* NOTE: suspend/resume is called from
445 * interrupt context and cannot sleep!
446 */
447void
448ohci_suspend(ohci_softc_t *sc)
449{
450 uint32_t ctl;
451
452 mtx_lock(&sc->sc_bus.mtx);
453
454#if USB_DEBUG
455 DPRINTF("\n");
456 if (ohcidebug > 2) {
457 ohci_dumpregs(sc);
458 }
459#endif
460
461 ctl = OREAD4(sc, OHCI_CONTROL) & ~OHCI_HCFS_MASK;
462 if (sc->sc_control == 0) {
463 /*
464 * Preserve register values, in case that APM BIOS
465 * does not recover them.
466 */
467 sc->sc_control = ctl;
468 sc->sc_intre = OREAD4(sc, OHCI_INTERRUPT_ENABLE);
469 }
470 ctl |= OHCI_HCFS_SUSPEND;
471 OWRITE4(sc, OHCI_CONTROL, ctl);
472
473 usb2_pause_mtx(&sc->sc_bus.mtx,
474 USB_RESUME_WAIT);
475
476 mtx_unlock(&sc->sc_bus.mtx);
477 return;
478}
479
480void
481ohci_resume(ohci_softc_t *sc)
482{
483 uint32_t ctl;
484
485 mtx_lock(&sc->sc_bus.mtx);
486
487#if USB_DEBUG
488 DPRINTF("\n");
489 if (ohcidebug > 2) {
490 ohci_dumpregs(sc);
491 }
492#endif
493 /* some broken BIOSes never initialize the Controller chip */
494 ohci_controller_init(sc);
495
496 if (sc->sc_intre) {
497 OWRITE4(sc, OHCI_INTERRUPT_ENABLE,
498 sc->sc_intre & (OHCI_ALL_INTRS | OHCI_MIE));
499 }
500 if (sc->sc_control)
501 ctl = sc->sc_control;
502 else
503 ctl = OREAD4(sc, OHCI_CONTROL);
504 ctl |= OHCI_HCFS_RESUME;
505 OWRITE4(sc, OHCI_CONTROL, ctl);
506 usb2_pause_mtx(&sc->sc_bus.mtx, USB_RESUME_DELAY);
507 ctl = (ctl & ~OHCI_HCFS_MASK) | OHCI_HCFS_OPERATIONAL;
508 OWRITE4(sc, OHCI_CONTROL, ctl);
509 usb2_pause_mtx(&sc->sc_bus.mtx, USB_RESUME_RECOVERY);
510 sc->sc_control = sc->sc_intre = 0;
511
512 mtx_unlock(&sc->sc_bus.mtx);
513
514 /* catch any lost interrupts */
515 ohci_do_poll(&sc->sc_bus);
516
517 return;
518}
519
520#if USB_DEBUG
521static void
522ohci_dumpregs(ohci_softc_t *sc)
523{
524 struct ohci_hcca *hcca;
525
526 DPRINTF("ohci_dumpregs: rev=0x%08x control=0x%08x command=0x%08x\n",
527 OREAD4(sc, OHCI_REVISION),
528 OREAD4(sc, OHCI_CONTROL),
529 OREAD4(sc, OHCI_COMMAND_STATUS));
530 DPRINTF(" intrstat=0x%08x intre=0x%08x intrd=0x%08x\n",
531 OREAD4(sc, OHCI_INTERRUPT_STATUS),
532 OREAD4(sc, OHCI_INTERRUPT_ENABLE),
533 OREAD4(sc, OHCI_INTERRUPT_DISABLE));
534 DPRINTF(" hcca=0x%08x percur=0x%08x ctrlhd=0x%08x\n",
535 OREAD4(sc, OHCI_HCCA),
536 OREAD4(sc, OHCI_PERIOD_CURRENT_ED),
537 OREAD4(sc, OHCI_CONTROL_HEAD_ED));
538 DPRINTF(" ctrlcur=0x%08x bulkhd=0x%08x bulkcur=0x%08x\n",
539 OREAD4(sc, OHCI_CONTROL_CURRENT_ED),
540 OREAD4(sc, OHCI_BULK_HEAD_ED),
541 OREAD4(sc, OHCI_BULK_CURRENT_ED));
542 DPRINTF(" done=0x%08x fmival=0x%08x fmrem=0x%08x\n",
543 OREAD4(sc, OHCI_DONE_HEAD),
544 OREAD4(sc, OHCI_FM_INTERVAL),
545 OREAD4(sc, OHCI_FM_REMAINING));
546 DPRINTF(" fmnum=0x%08x perst=0x%08x lsthrs=0x%08x\n",
547 OREAD4(sc, OHCI_FM_NUMBER),
548 OREAD4(sc, OHCI_PERIODIC_START),
549 OREAD4(sc, OHCI_LS_THRESHOLD));
550 DPRINTF(" desca=0x%08x descb=0x%08x stat=0x%08x\n",
551 OREAD4(sc, OHCI_RH_DESCRIPTOR_A),
552 OREAD4(sc, OHCI_RH_DESCRIPTOR_B),
553 OREAD4(sc, OHCI_RH_STATUS));
554 DPRINTF(" port1=0x%08x port2=0x%08x\n",
555 OREAD4(sc, OHCI_RH_PORT_STATUS(1)),
556 OREAD4(sc, OHCI_RH_PORT_STATUS(2)));
557
558 hcca = ohci_get_hcca(sc);
559
560 DPRINTF(" HCCA: frame_number=0x%04x done_head=0x%08x\n",
561 le32toh(hcca->hcca_frame_number),
562 le32toh(hcca->hcca_done_head));
563 return;
564}
565static void
566ohci_dump_tds(ohci_td_t *std)
567{
568 for (; std; std = std->obj_next) {
569 if (ohci_dump_td(std)) {
570 break;
571 }
572 }
573 return;
574}
575
576static uint8_t
577ohci_dump_td(ohci_td_t *std)
578{
579 uint32_t td_flags;
580 uint8_t temp;
581
582 usb2_pc_cpu_invalidate(std->page_cache);
583
584 td_flags = le32toh(std->td_flags);
585 temp = (std->td_next == 0);
586
587 printf("TD(%p) at 0x%08x: %s%s%s%s%s delay=%d ec=%d "
588 "cc=%d\ncbp=0x%08x next=0x%08x be=0x%08x\n",
589 std, le32toh(std->td_self),
590 (td_flags & OHCI_TD_R) ? "-R" : "",
591 (td_flags & OHCI_TD_OUT) ? "-OUT" : "",
592 (td_flags & OHCI_TD_IN) ? "-IN" : "",
593 ((td_flags & OHCI_TD_TOGGLE_MASK) == OHCI_TD_TOGGLE_1) ? "-TOG1" : "",
594 ((td_flags & OHCI_TD_TOGGLE_MASK) == OHCI_TD_TOGGLE_0) ? "-TOG0" : "",
595 OHCI_TD_GET_DI(td_flags),
596 OHCI_TD_GET_EC(td_flags),
597 OHCI_TD_GET_CC(td_flags),
598 le32toh(std->td_cbp),
599 le32toh(std->td_next),
600 le32toh(std->td_be));
601
602 return (temp);
603}
604
605static uint8_t
606ohci_dump_itd(ohci_itd_t *sitd)
607{
608 uint32_t itd_flags;
609 uint16_t i;
610 uint8_t temp;
611
612 usb2_pc_cpu_invalidate(sitd->page_cache);
613
614 itd_flags = le32toh(sitd->itd_flags);
615 temp = (sitd->itd_next == 0);
616
617 printf("ITD(%p) at 0x%08x: sf=%d di=%d fc=%d cc=%d\n"
618 "bp0=0x%08x next=0x%08x be=0x%08x\n",
619 sitd, le32toh(sitd->itd_self),
620 OHCI_ITD_GET_SF(itd_flags),
621 OHCI_ITD_GET_DI(itd_flags),
622 OHCI_ITD_GET_FC(itd_flags),
623 OHCI_ITD_GET_CC(itd_flags),
624 le32toh(sitd->itd_bp0),
625 le32toh(sitd->itd_next),
626 le32toh(sitd->itd_be));
627 for (i = 0; i < OHCI_ITD_NOFFSET; i++) {
628 printf("offs[%d]=0x%04x ", i,
629 (uint32_t)le16toh(sitd->itd_offset[i]));
630 }
631 printf("\n");
632
633 return (temp);
634}
635
636static void
637ohci_dump_itds(ohci_itd_t *sitd)
638{
639 for (; sitd; sitd = sitd->obj_next) {
640 if (ohci_dump_itd(sitd)) {
641 break;
642 }
643 }
644 return;
645}
646
647static void
648ohci_dump_ed(ohci_ed_t *sed)
649{
650 uint32_t ed_flags;
651 uint32_t ed_headp;
652
653 usb2_pc_cpu_invalidate(sed->page_cache);
654
655 ed_flags = le32toh(sed->ed_flags);
656 ed_headp = le32toh(sed->ed_headp);
657
658 printf("ED(%p) at 0x%08x: addr=%d endpt=%d maxp=%d flags=%s%s%s%s%s\n"
659 "tailp=0x%08x headflags=%s%s headp=0x%08x nexted=0x%08x\n",
660 sed, le32toh(sed->ed_self),
661 OHCI_ED_GET_FA(ed_flags),
662 OHCI_ED_GET_EN(ed_flags),
663 OHCI_ED_GET_MAXP(ed_flags),
664 (ed_flags & OHCI_ED_DIR_OUT) ? "-OUT" : "",
665 (ed_flags & OHCI_ED_DIR_IN) ? "-IN" : "",
666 (ed_flags & OHCI_ED_SPEED) ? "-LOWSPEED" : "",
667 (ed_flags & OHCI_ED_SKIP) ? "-SKIP" : "",
668 (ed_flags & OHCI_ED_FORMAT_ISO) ? "-ISO" : "",
669 le32toh(sed->ed_tailp),
670 (ed_headp & OHCI_HALTED) ? "-HALTED" : "",
671 (ed_headp & OHCI_TOGGLECARRY) ? "-CARRY" : "",
672 le32toh(sed->ed_headp),
673 le32toh(sed->ed_next));
674 return;
675}
676
677#endif
678
679static void
680ohci_transfer_intr_enqueue(struct usb2_xfer *xfer)
681{
682 /* check for early completion */
683 if (ohci_check_transfer(xfer)) {
684 return;
685 }
686 /* put transfer on interrupt queue */
687 usb2_transfer_enqueue(&xfer->udev->bus->intr_q, xfer);
688
689 /* start timeout, if any */
690 if (xfer->timeout != 0) {
691 usb2_transfer_timeout_ms(xfer, &ohci_timeout, xfer->timeout);
692 }
693 return;
694}
695
696#define OHCI_APPEND_QH(sed,td_self,last) (last) = _ohci_append_qh(sed,td_self,last)
697static ohci_ed_t *
698_ohci_append_qh(ohci_ed_t *sed, uint32_t td_self, ohci_ed_t *last)
699{
700 DPRINTFN(11, "%p to %p\n", sed, last);
701
702 /* (sc->sc_bus.mtx) must be locked */
703
704 sed->next = last->next;
705 sed->ed_next = last->ed_next;
706 sed->ed_tailp = 0;
707 sed->ed_headp = td_self;
708
709 sed->prev = last;
710
711 usb2_pc_cpu_flush(sed->page_cache);
712
713 /*
714 * the last->next->prev is never followed: sed->next->prev = sed;
715 */
716
717 last->next = sed;
718 last->ed_next = sed->ed_self;
719
720 usb2_pc_cpu_flush(last->page_cache);
721
722 return (sed);
723}
724
725#define OHCI_REMOVE_QH(sed,last) (last) = _ohci_remove_qh(sed,last)
726static ohci_ed_t *
727_ohci_remove_qh(ohci_ed_t *sed, ohci_ed_t *last)
728{
729 DPRINTFN(11, "%p from %p\n", sed, last);
730
731 /* (sc->sc_bus.mtx) must be locked */
732
733 /* only remove if not removed from a queue */
734 if (sed->prev) {
735
736 sed->prev->next = sed->next;
737 sed->prev->ed_next = sed->ed_next;
738
739 usb2_pc_cpu_flush(sed->prev->page_cache);
740
741 if (sed->next) {
742 sed->next->prev = sed->prev;
743 usb2_pc_cpu_flush(sed->next->page_cache);
744 }
745 /*
746 * terminate transfer in case the transferred packet was
747 * short so that the ED still points at the last used TD
748 */
749 sed->ed_flags |= htole32(OHCI_ED_SKIP);
750 sed->ed_headp = sed->ed_tailp;
751
752 last = ((last == sed) ? sed->prev : last);
753
754 sed->prev = 0;
755
756 usb2_pc_cpu_flush(sed->page_cache);
757 }
758 return (last);
759}
760
761static void
762ohci_isoc_done(struct usb2_xfer *xfer)
763{
764 uint8_t nframes;
765 uint32_t *plen = xfer->frlengths;
766 volatile uint16_t *olen;
767 uint16_t len = 0;
768 ohci_itd_t *td = xfer->td_transfer_first;
769
770 while (1) {
771 if (td == NULL) {
772 panic("%s:%d: out of TD's\n",
773 __FUNCTION__, __LINE__);
774 }
775#if USB_DEBUG
776 if (ohcidebug > 5) {
777 DPRINTF("isoc TD\n");
778 ohci_dump_itd(td);
779 }
780#endif
781 usb2_pc_cpu_invalidate(td->page_cache);
782
783 nframes = td->frames;
784 olen = &td->itd_offset[0];
785
786 if (nframes > 8) {
787 nframes = 8;
788 }
789 while (nframes--) {
790 len = le16toh(*olen);
791
792 if ((len >> 12) == OHCI_CC_NOT_ACCESSED) {
793 len = 0;
794 } else {
795 len &= ((1 << 12) - 1);
796 }
797
798 if (len > *plen) {
799 len = 0;/* invalid length */
800 }
801 *plen = len;
802 plen++;
803 olen++;
804 }
805
806 if (((void *)td) == xfer->td_transfer_last) {
807 break;
808 }
809 td = td->obj_next;
810 }
811
812 xfer->aframes = xfer->nframes;
813 ohci_device_done(xfer, USB_ERR_NORMAL_COMPLETION);
814 return;
815}
816
817#if USB_DEBUG
818static const char *const
819 ohci_cc_strs[] =
820{
821 "NO_ERROR",
822 "CRC",
823 "BIT_STUFFING",
824 "DATA_TOGGLE_MISMATCH",
825
826 "STALL",
827 "DEVICE_NOT_RESPONDING",
828 "PID_CHECK_FAILURE",
829 "UNEXPECTED_PID",
830
831 "DATA_OVERRUN",
832 "DATA_UNDERRUN",
833 "BUFFER_OVERRUN",
834 "BUFFER_UNDERRUN",
835
836 "reserved",
837 "reserved",
838 "NOT_ACCESSED",
839 "NOT_ACCESSED"
840};
841
842#endif
843
844static usb2_error_t
845ohci_non_isoc_done_sub(struct usb2_xfer *xfer)
846{
847 ohci_td_t *td;
848 ohci_td_t *td_alt_next;
849 uint32_t temp;
850 uint32_t phy_start;
851 uint32_t phy_end;
852 uint32_t td_flags;
853 uint16_t cc;
854
855 td = xfer->td_transfer_cache;
856 td_alt_next = td->alt_next;
857 td_flags = 0;
858
859 while (1) {
860
861 usb2_pc_cpu_invalidate(td->page_cache);
862 phy_start = le32toh(td->td_cbp);
863 td_flags = le32toh(td->td_flags);
864 cc = OHCI_TD_GET_CC(td_flags);
865
866 if (phy_start) {
867 /*
868 * short transfer - compute the number of remaining
869 * bytes in the hardware buffer:
870 */
871 phy_end = le32toh(td->td_be);
872 temp = (OHCI_PAGE(phy_start ^ phy_end) ?
873 (OHCI_PAGE_SIZE + 1) : 0x0001);
874 temp += OHCI_PAGE_OFFSET(phy_end);
875 temp -= OHCI_PAGE_OFFSET(phy_start);
876
877 if (temp > td->len) {
878 /* guard against corruption */
879 cc = OHCI_CC_STALL;
880 } else if (xfer->aframes != xfer->nframes) {
881 /*
882 * subtract remaining length from
883 * "frlengths[]"
884 */
885 xfer->frlengths[xfer->aframes] -= temp;
886 }
887 }
888 /* Check for last transfer */
889 if (((void *)td) == xfer->td_transfer_last) {
890 td = NULL;
891 break;
892 }
893 /* Check transfer status */
894 if (cc) {
895 /* the transfer is finished */
896 td = NULL;
897 break;
898 }
899 /* Check for short transfer */
900 if (phy_start) {
901 if (xfer->flags_int.short_frames_ok) {
902 /* follow alt next */
903 td = td->alt_next;
904 } else {
905 /* the transfer is finished */
906 td = NULL;
907 }
908 break;
909 }
910 td = td->obj_next;
911
912 if (td->alt_next != td_alt_next) {
913 /* this USB frame is complete */
914 break;
915 }
916 }
917
918 /* update transfer cache */
919
920 xfer->td_transfer_cache = td;
921
922 DPRINTFN(16, "error cc=%d (%s)\n",
923 cc, ohci_cc_strs[cc]);
924
925 return ((cc == 0) ? USB_ERR_NORMAL_COMPLETION :
926 (cc == OHCI_CC_STALL) ? USB_ERR_STALLED : USB_ERR_IOERROR);
927}
928
929static void
930ohci_non_isoc_done(struct usb2_xfer *xfer)
931{
932 usb2_error_t err = 0;
933
934 DPRINTFN(13, "xfer=%p pipe=%p transfer done\n",
935 xfer, xfer->pipe);
936
937#if USB_DEBUG
938 if (ohcidebug > 10) {
939 ohci_dump_tds(xfer->td_transfer_first);
940 }
941#endif
942
943 /* reset scanner */
944
945 xfer->td_transfer_cache = xfer->td_transfer_first;
946
947 if (xfer->flags_int.control_xfr) {
948
949 if (xfer->flags_int.control_hdr) {
950
951 err = ohci_non_isoc_done_sub(xfer);
952 }
953 xfer->aframes = 1;
954
955 if (xfer->td_transfer_cache == NULL) {
956 goto done;
957 }
958 }
959 while (xfer->aframes != xfer->nframes) {
960
961 err = ohci_non_isoc_done_sub(xfer);
962 xfer->aframes++;
963
964 if (xfer->td_transfer_cache == NULL) {
965 goto done;
966 }
967 }
968
969 if (xfer->flags_int.control_xfr &&
970 !xfer->flags_int.control_act) {
971
972 err = ohci_non_isoc_done_sub(xfer);
973 }
974done:
975 ohci_device_done(xfer, err);
976 return;
977}
978
979/*------------------------------------------------------------------------*
980 * ohci_check_transfer_sub
981 *------------------------------------------------------------------------*/
982static void
983ohci_check_transfer_sub(struct usb2_xfer *xfer)
984{
985 ohci_td_t *td;
986 ohci_ed_t *ed;
987 uint32_t phy_start;
988 uint32_t td_flags;
989 uint32_t td_next;
990 uint16_t cc;
991
992 td = xfer->td_transfer_cache;
993
994 while (1) {
995
996 usb2_pc_cpu_invalidate(td->page_cache);
997 phy_start = le32toh(td->td_cbp);
998 td_flags = le32toh(td->td_flags);
999 td_next = le32toh(td->td_next);
1000
1001 /* Check for last transfer */
1002 if (((void *)td) == xfer->td_transfer_last) {
1003 /* the transfer is finished */
1004 td = NULL;
1005 break;
1006 }
1007 /* Check transfer status */
1008 cc = OHCI_TD_GET_CC(td_flags);
1009 if (cc) {
1010 /* the transfer is finished */
1011 td = NULL;
1012 break;
1013 }
1014 /*
1015 * Check if we reached the last packet
1016 * or if there is a short packet:
1017 */
1018
1019 if (((td_next & (~0xF)) == OHCI_TD_NEXT_END) || phy_start) {
1020 /* follow alt next */
1021 td = td->alt_next;
1022 break;
1023 }
1024 td = td->obj_next;
1025 }
1026
1027 /* update transfer cache */
1028
1029 xfer->td_transfer_cache = td;
1030
1031 if (td) {
1032
1033 ed = xfer->qh_start[xfer->flags_int.curr_dma_set];
1034
1035 ed->ed_headp = td->td_self;
1036 usb2_pc_cpu_flush(ed->page_cache);
1037
1038 DPRINTFN(13, "xfer=%p following alt next\n", xfer);
1039 }
1040 return;
1041}
1042
1043/*------------------------------------------------------------------------*
1044 * ohci_check_transfer
1045 *
1046 * Return values:
1047 * 0: USB transfer is not finished
1048 * Else: USB transfer is finished
1049 *------------------------------------------------------------------------*/
1050static uint8_t
1051ohci_check_transfer(struct usb2_xfer *xfer)
1052{
1053 ohci_ed_t *ed;
1054 uint32_t ed_flags;
1055 uint32_t ed_headp;
1056 uint32_t ed_tailp;
1057
1058 DPRINTFN(13, "xfer=%p checking transfer\n", xfer);
1059
1060 ed = xfer->qh_start[xfer->flags_int.curr_dma_set];
1061
1062 usb2_pc_cpu_invalidate(ed->page_cache);
1063 ed_flags = le32toh(ed->ed_flags);
1064 ed_headp = le32toh(ed->ed_headp);
1065 ed_tailp = le32toh(ed->ed_tailp);
1066
1067 if ((ed_flags & OHCI_ED_SKIP) ||
1068 (ed_headp & OHCI_HALTED) ||
1069 (((ed_headp ^ ed_tailp) & (~0xF)) == 0)) {
1070 if (xfer->pipe->methods == &ohci_device_isoc_methods) {
1071 /* isochronous transfer */
1072 ohci_isoc_done(xfer);
1073 } else {
1074 if (xfer->flags_int.short_frames_ok) {
1075 ohci_check_transfer_sub(xfer);
1076 if (xfer->td_transfer_cache) {
1077 /* not finished yet */
1078 return (0);
1079 }
1080 }
1081 /* store data-toggle */
1082 if (ed_headp & OHCI_TOGGLECARRY) {
1083 xfer->pipe->toggle_next = 1;
1084 } else {
1085 xfer->pipe->toggle_next = 0;
1086 }
1087
1088 /* non-isochronous transfer */
1089 ohci_non_isoc_done(xfer);
1090 }
1091 return (1);
1092 }
1093 DPRINTFN(13, "xfer=%p is still active\n", xfer);
1094 return (0);
1095}
1096
1097static void
1098ohci_rhsc_enable(ohci_softc_t *sc)
1099{
1100 DPRINTFN(5, "\n");
1101
1102 mtx_assert(&sc->sc_bus.mtx, MA_OWNED);
1103
1104 sc->sc_eintrs |= OHCI_RHSC;
1105 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_RHSC);
1106
1107 /* acknowledge any RHSC interrupt */
1108 OWRITE4(sc, OHCI_INTERRUPT_STATUS, OHCI_RHSC);
1109
1110 usb2_sw_transfer(&sc->sc_root_intr,
1111 &ohci_root_intr_done);
1112
1113 mtx_unlock(&sc->sc_bus.mtx);
1114 return;
1115}
1116
1117static void
1118ohci_interrupt_poll(ohci_softc_t *sc)
1119{
1120 struct usb2_xfer *xfer;
1121
1122repeat:
1123 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
1124 /*
1125 * check if transfer is transferred
1126 */
1127 if (ohci_check_transfer(xfer)) {
1128 /* queue has been modified */
1129 goto repeat;
1130 }
1131 }
1132 return;
1133}
1134
1135/*------------------------------------------------------------------------*
1136 * ohci_interrupt - OHCI interrupt handler
1137 *
1138 * NOTE: Do not access "sc->sc_bus.bdev" inside the interrupt handler,
1139 * hence the interrupt handler will be setup before "sc->sc_bus.bdev"
1140 * is present !
1141 *------------------------------------------------------------------------*/
1142void
1143ohci_interrupt(ohci_softc_t *sc)
1144{
1145 struct ohci_hcca *hcca;
1146 uint32_t status;
1147 uint32_t done;
1148
1149 mtx_lock(&sc->sc_bus.mtx);
1150
1151 hcca = ohci_get_hcca(sc);
1152
1153 DPRINTFN(16, "real interrupt\n");
1154
1155#if USB_DEBUG
1156 if (ohcidebug > 15) {
1157 ohci_dumpregs(sc);
1158 }
1159#endif
1160
1161 done = le32toh(hcca->hcca_done_head);
1162
1163 /*
1164 * The LSb of done is used to inform the HC Driver that an interrupt
1165 * condition exists for both the Done list and for another event
1166 * recorded in HcInterruptStatus. On an interrupt from the HC, the
1167 * HC Driver checks the HccaDoneHead Value. If this value is 0, then
1168 * the interrupt was caused by other than the HccaDoneHead update
1169 * and the HcInterruptStatus register needs to be accessed to
1170 * determine that exact interrupt cause. If HccaDoneHead is nonzero,
1171 * then a Done list update interrupt is indicated and if the LSb of
1172 * done is nonzero, then an additional interrupt event is indicated
1173 * and HcInterruptStatus should be checked to determine its cause.
1174 */
1175 if (done != 0) {
1176 status = 0;
1177
1178 if (done & ~OHCI_DONE_INTRS) {
1179 status |= OHCI_WDH;
1180 }
1181 if (done & OHCI_DONE_INTRS) {
1182 status |= OREAD4(sc, OHCI_INTERRUPT_STATUS);
1183 }
1184 hcca->hcca_done_head = 0;
1185
1186 usb2_pc_cpu_flush(&sc->sc_hw.hcca_pc);
1187 } else {
1188 status = OREAD4(sc, OHCI_INTERRUPT_STATUS) & ~OHCI_WDH;
1189 }
1190
1191 status &= ~OHCI_MIE;
1192 if (status == 0) {
1193 /*
1194 * nothing to be done (PCI shared
1195 * interrupt)
1196 */
1197 goto done;
1198 }
1199 OWRITE4(sc, OHCI_INTERRUPT_STATUS, status); /* Acknowledge */
1200
1201 status &= sc->sc_eintrs;
1202 if (status == 0) {
1203 goto done;
1204 }
1205 if (status & (OHCI_SO | OHCI_RD | OHCI_UE | OHCI_RHSC)) {
1206#if 0
1207 if (status & OHCI_SO) {
1208 /* XXX do what */
1209 }
1210#endif
1211 if (status & OHCI_RD) {
1212 printf("%s: resume detect\n", __FUNCTION__);
1213 /* XXX process resume detect */
1214 }
1215 if (status & OHCI_UE) {
1216 printf("%s: unrecoverable error, "
1217 "controller halted\n", __FUNCTION__);
1218 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET);
1219 /* XXX what else */
1220 }
1221 if (status & OHCI_RHSC) {
1222 /*
1223 * Disable RHSC interrupt for now, because it will be
1224 * on until the port has been reset.
1225 */
1226 sc->sc_eintrs &= ~OHCI_RHSC;
1227 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_RHSC);
1228
1229 usb2_sw_transfer(&sc->sc_root_intr,
1230 &ohci_root_intr_done);
1231
1232 /* do not allow RHSC interrupts > 1 per second */
1233 usb2_callout_reset(&sc->sc_tmo_rhsc, hz,
1234 (void *)&ohci_rhsc_enable, sc);
1235 }
1236 }
1237 status &= ~(OHCI_RHSC | OHCI_WDH | OHCI_SO);
1238 if (status != 0) {
1239 /* Block unprocessed interrupts. XXX */
1240 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, status);
1241 sc->sc_eintrs &= ~status;
1242 printf("%s: blocking intrs 0x%x\n",
1243 __FUNCTION__, status);
1244 }
1245 /* poll all the USB transfers */
1246 ohci_interrupt_poll(sc);
1247
1248done:
1249 mtx_unlock(&sc->sc_bus.mtx);
1250 return;
1251}
1252
1253/*
1254 * called when a request does not complete
1255 */
1256static void
1257ohci_timeout(void *arg)
1258{
1259 struct usb2_xfer *xfer = arg;
1260 ohci_softc_t *sc = xfer->usb2_sc;
1261
1262 DPRINTF("xfer=%p\n", xfer);
1263
1264 mtx_assert(&sc->sc_bus.mtx, MA_OWNED);
1265
1266 /* transfer is transferred */
1267 ohci_device_done(xfer, USB_ERR_TIMEOUT);
1268
1269 mtx_unlock(&sc->sc_bus.mtx);
1270
1271 return;
1272}
1273
1274static void
1275ohci_do_poll(struct usb2_bus *bus)
1276{
1277 struct ohci_softc *sc = OHCI_BUS2SC(bus);
1278
1279 mtx_lock(&sc->sc_bus.mtx);
1280 ohci_interrupt_poll(sc);
1281 ohci_root_ctrl_poll(sc);
1282 mtx_unlock(&sc->sc_bus.mtx);
1283 return;
1284}
1285
1286static void
1287ohci_setup_standard_chain_sub(struct ohci_std_temp *temp)
1288{
1289 struct usb2_page_search buf_res;
1290 ohci_td_t *td;
1291 ohci_td_t *td_next;
1292 ohci_td_t *td_alt_next;
1293 uint32_t buf_offset;
1294 uint32_t average;
1295 uint32_t len_old;
1296 uint8_t shortpkt_old;
1297 uint8_t precompute;
1298
1299 td_alt_next = NULL;
1300 buf_offset = 0;
1301 shortpkt_old = temp->shortpkt;
1302 len_old = temp->len;
1303 precompute = 1;
1304
1305 /* software is used to detect short incoming transfers */
1306
1307 if ((temp->td_flags & htole32(OHCI_TD_DP_MASK)) == htole32(OHCI_TD_IN)) {
1308 temp->td_flags |= htole32(OHCI_TD_R);
1309 } else {
1310 temp->td_flags &= ~htole32(OHCI_TD_R);
1311 }
1312
1313restart:
1314
1315 td = temp->td;
1316 td_next = temp->td_next;
1317
1318 while (1) {
1319
1320 if (temp->len == 0) {
1321
1322 if (temp->shortpkt) {
1323 break;
1324 }
1325 /* send a Zero Length Packet, ZLP, last */
1326
1327 temp->shortpkt = 1;
1328 average = 0;
1329
1330 } else {
1331
1332 average = temp->average;
1333
1334 if (temp->len < average) {
1335 if (temp->len % temp->max_frame_size) {
1336 temp->shortpkt = 1;
1337 }
1338 average = temp->len;
1339 }
1340 }
1341
1342 if (td_next == NULL) {
1343 panic("%s: out of OHCI transfer descriptors!", __FUNCTION__);
1344 }
1345 /* get next TD */
1346
1347 td = td_next;
1348 td_next = td->obj_next;
1349
1350 /* check if we are pre-computing */
1351
1352 if (precompute) {
1353
1354 /* update remaining length */
1355
1356 temp->len -= average;
1357
1358 continue;
1359 }
1360 /* fill out current TD */
1361 td->td_flags = temp->td_flags;
1362
1363 /* the next TD uses TOGGLE_CARRY */
1364 temp->td_flags &= ~htole32(OHCI_TD_TOGGLE_MASK);
1365
1366 if (average == 0) {
1367
1368 td->td_cbp = 0;
1369 td->td_be = ~0;
1370 td->len = 0;
1371
1372 } else {
1373
1374 usb2_get_page(temp->pc, buf_offset, &buf_res);
1375 td->td_cbp = htole32(buf_res.physaddr);
1376 buf_offset += (average - 1);
1377
1378 usb2_get_page(temp->pc, buf_offset, &buf_res);
1379 td->td_be = htole32(buf_res.physaddr);
1380 buf_offset++;
1381
1382 td->len = average;
1383
1384 /* update remaining length */
1385
1386 temp->len -= average;
1387 }
1388
1389 if ((td_next == td_alt_next) && temp->setup_alt_next) {
1390 /* we need to receive these frames one by one ! */
1391 td->td_flags &= htole32(~OHCI_TD_INTR_MASK);
1392 td->td_flags |= htole32(OHCI_TD_SET_DI(1));
1393 td->td_next = htole32(OHCI_TD_NEXT_END);
1394 } else {
1395 if (td_next) {
1396 /* link the current TD with the next one */
1397 td->td_next = td_next->td_self;
1398 }
1399 }
1400
1401 td->alt_next = td_alt_next;
1402
1403 usb2_pc_cpu_flush(td->page_cache);
1404 }
1405
1406 if (precompute) {
1407 precompute = 0;
1408
1409 /* setup alt next pointer, if any */
1410 if (temp->short_frames_ok) {
1411 if (temp->setup_alt_next) {
1412 td_alt_next = td_next;
1413 }
1414 } else {
1415 /* we use this field internally */
1416 td_alt_next = td_next;
1417 }
1418
1419 /* restore */
1420 temp->shortpkt = shortpkt_old;
1421 temp->len = len_old;
1422 goto restart;
1423 }
1424 temp->td = td;
1425 temp->td_next = td_next;
1426
1427 return;
1428}
1429
1430static void
1431ohci_setup_standard_chain(struct usb2_xfer *xfer, ohci_ed_t **ed_last)
1432{
1433 struct ohci_std_temp temp;
1434 struct usb2_pipe_methods *methods;
1435 ohci_ed_t *ed;
1436 ohci_td_t *td;
1437 uint32_t ed_flags;
1438 uint32_t x;
1439
1440 DPRINTFN(9, "addr=%d endpt=%d sumlen=%d speed=%d\n",
1441 xfer->address, UE_GET_ADDR(xfer->endpoint),
1442 xfer->sumlen, usb2_get_speed(xfer->udev));
1443
1444 temp.average = xfer->max_usb2_frame_size;
1445 temp.max_frame_size = xfer->max_frame_size;
1446
1447 /* toggle the DMA set we are using */
1448 xfer->flags_int.curr_dma_set ^= 1;
1449
1450 /* get next DMA set */
1451 td = xfer->td_start[xfer->flags_int.curr_dma_set];
1452
1453 xfer->td_transfer_first = td;
1454 xfer->td_transfer_cache = td;
1455
1456 temp.td = NULL;
1457 temp.td_next = td;
1458 temp.setup_alt_next = xfer->flags_int.short_frames_ok;
1459 temp.short_frames_ok = xfer->flags_int.short_frames_ok;
1460
1461 methods = xfer->pipe->methods;
1462
1463 /* check if we should prepend a setup message */
1464
1465 if (xfer->flags_int.control_xfr) {
1466 if (xfer->flags_int.control_hdr) {
1467
1468 temp.td_flags = htole32(OHCI_TD_SETUP | OHCI_TD_NOCC |
1469 OHCI_TD_TOGGLE_0 | OHCI_TD_NOINTR);
1470
1471 temp.len = xfer->frlengths[0];
1472 temp.pc = xfer->frbuffers + 0;
1473 temp.shortpkt = temp.len ? 1 : 0;
1474
1475 ohci_setup_standard_chain_sub(&temp);
1476
1477 /*
1478 * XXX assume that the setup message is
1479 * contained within one USB packet:
1480 */
1481 xfer->pipe->toggle_next = 1;
1482 }
1483 x = 1;
1484 } else {
1485 x = 0;
1486 }
1487 temp.td_flags = htole32(OHCI_TD_NOCC | OHCI_TD_NOINTR);
1488
1489 /* set data toggle */
1490
1491 if (xfer->pipe->toggle_next) {
1492 temp.td_flags |= htole32(OHCI_TD_TOGGLE_1);
1493 } else {
1494 temp.td_flags |= htole32(OHCI_TD_TOGGLE_0);
1495 }
1496
1497 /* set endpoint direction */
1498
1499 if (UE_GET_DIR(xfer->endpoint) == UE_DIR_IN) {
1500 temp.td_flags |= htole32(OHCI_TD_IN);
1501 } else {
1502 temp.td_flags |= htole32(OHCI_TD_OUT);
1503 }
1504
1505 while (x != xfer->nframes) {
1506
1507 /* DATA0 / DATA1 message */
1508
1509 temp.len = xfer->frlengths[x];
1510 temp.pc = xfer->frbuffers + x;
1511
1512 x++;
1513
1514 if (x == xfer->nframes) {
1515 temp.setup_alt_next = 0;
1516 }
1517 if (temp.len == 0) {
1518
1519 /* make sure that we send an USB packet */
1520
1521 temp.shortpkt = 0;
1522
1523 } else {
1524
1525 /* regular data transfer */
1526
1527 temp.shortpkt = (xfer->flags.force_short_xfer) ? 0 : 1;
1528 }
1529
1530 ohci_setup_standard_chain_sub(&temp);
1531 }
1532
1533 /* check if we should append a status stage */
1534
1535 if (xfer->flags_int.control_xfr &&
1536 !xfer->flags_int.control_act) {
1537
1538 /*
1539 * Send a DATA1 message and invert the current endpoint
1540 * direction.
1541 */
1542
1543 /* set endpoint direction and data toggle */
1544
1545 if (UE_GET_DIR(xfer->endpoint) == UE_DIR_IN) {
1546 temp.td_flags = htole32(OHCI_TD_OUT |
1547 OHCI_TD_NOCC | OHCI_TD_TOGGLE_1 | OHCI_TD_SET_DI(1));
1548 } else {
1549 temp.td_flags = htole32(OHCI_TD_IN |
1550 OHCI_TD_NOCC | OHCI_TD_TOGGLE_1 | OHCI_TD_SET_DI(1));
1551 }
1552
1553 temp.len = 0;
1554 temp.pc = NULL;
1555 temp.shortpkt = 0;
1556
1557 ohci_setup_standard_chain_sub(&temp);
1558 }
1559 td = temp.td;
1560
1561 td->td_next = htole32(OHCI_TD_NEXT_END);
1562 td->td_flags &= ~htole32(OHCI_TD_INTR_MASK);
1563 td->td_flags |= htole32(OHCI_TD_SET_DI(1));
1564
1565 usb2_pc_cpu_flush(td->page_cache);
1566
1567 /* must have at least one frame! */
1568
1569 xfer->td_transfer_last = td;
1570
1571#if USB_DEBUG
1572 if (ohcidebug > 8) {
1573 DPRINTF("nexttog=%d; data before transfer:\n",
1574 xfer->pipe->toggle_next);
1575 ohci_dump_tds(xfer->td_transfer_first);
1576 }
1577#endif
1578
1579 ed = xfer->qh_start[xfer->flags_int.curr_dma_set];
1580
1581 ed_flags = (OHCI_ED_SET_FA(xfer->address) |
1582 OHCI_ED_SET_EN(UE_GET_ADDR(xfer->endpoint)) |
1583 OHCI_ED_SET_MAXP(xfer->max_frame_size));
1584
1585 ed_flags |= (OHCI_ED_FORMAT_GEN | OHCI_ED_DIR_TD);
1586
1587 if (xfer->udev->speed == USB_SPEED_LOW) {
1588 ed_flags |= OHCI_ED_SPEED;
1589 }
1590 ed->ed_flags = htole32(ed_flags);
1591
1592 usb2_pc_cpu_flush(ed->page_cache);
1593
1594 td = xfer->td_transfer_first;
1595
1596 OHCI_APPEND_QH(ed, td->td_self, *ed_last);
1597
1598 if (methods == &ohci_device_bulk_methods) {
1599 ohci_softc_t *sc = xfer->usb2_sc;
1600
1601 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_BLF);
1602 }
1603 if (methods == &ohci_device_ctrl_methods) {
1604 ohci_softc_t *sc = xfer->usb2_sc;
1605
1606 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF);
1607 }
1608 return;
1609}
1610
1611static void
1612ohci_root_intr_done(struct usb2_xfer *xfer,
1613 struct usb2_sw_transfer *std)
1614{
1615 ohci_softc_t *sc = xfer->usb2_sc;
1616 uint32_t hstatus;
1617 uint16_t i;
1618 uint16_t m;
1619
1620 mtx_assert(&sc->sc_bus.mtx, MA_OWNED);
1621
1622 if (std->state != USB_SW_TR_PRE_DATA) {
1623 if (std->state == USB_SW_TR_PRE_CALLBACK) {
1624 /* transfer transferred */
1625 ohci_device_done(xfer, std->err);
1626 }
1627 goto done;
1628 }
1629 /* setup buffer */
1630 std->ptr = sc->sc_hub_idata;
1631 std->len = sizeof(sc->sc_hub_idata);
1632
1633 /* clear any old interrupt data */
1634 bzero(sc->sc_hub_idata, sizeof(sc->sc_hub_idata));
1635
1636 hstatus = OREAD4(sc, OHCI_RH_STATUS);
1637 DPRINTF("sc=%p xfer=%p hstatus=0x%08x\n",
1638 sc, xfer, hstatus);
1639
1640 /* set bits */
1641 m = (sc->sc_noport + 1);
1642 if (m > (8 * sizeof(sc->sc_hub_idata))) {
1643 m = (8 * sizeof(sc->sc_hub_idata));
1644 }
1645 for (i = 1; i < m; i++) {
1646 /* pick out CHANGE bits from the status register */
1647 if (OREAD4(sc, OHCI_RH_PORT_STATUS(i)) >> 16) {
1648 sc->sc_hub_idata[i / 8] |= 1 << (i % 8);
1649 DPRINTF("port %d changed\n", i);
1650 }
1651 }
1652done:
1653 return;
1654}
1655
1656/* NOTE: "done" can be run two times in a row,
1657 * from close and from interrupt
1658 */
1659static void
1660ohci_device_done(struct usb2_xfer *xfer, usb2_error_t error)
1661{
1662 struct usb2_pipe_methods *methods = xfer->pipe->methods;
1663 ohci_softc_t *sc = xfer->usb2_sc;
1664 ohci_ed_t *ed;
1665
1666 mtx_assert(&sc->sc_bus.mtx, MA_OWNED);
1667
1668
1669 DPRINTFN(2, "xfer=%p, pipe=%p, error=%d\n",
1670 xfer, xfer->pipe, error);
1671
1672 ed = xfer->qh_start[xfer->flags_int.curr_dma_set];
1673 if (ed) {
1674 usb2_pc_cpu_invalidate(ed->page_cache);
1675 }
1676 if (methods == &ohci_device_bulk_methods) {
1677 OHCI_REMOVE_QH(ed, sc->sc_bulk_p_last);
1678 }
1679 if (methods == &ohci_device_ctrl_methods) {
1680 OHCI_REMOVE_QH(ed, sc->sc_ctrl_p_last);
1681 }
1682 if (methods == &ohci_device_intr_methods) {
1683 OHCI_REMOVE_QH(ed, sc->sc_intr_p_last[xfer->qh_pos]);
1684 }
1685 if (methods == &ohci_device_isoc_methods) {
1686 OHCI_REMOVE_QH(ed, sc->sc_isoc_p_last);
1687 }
1688 xfer->td_transfer_first = NULL;
1689 xfer->td_transfer_last = NULL;
1690
1691 /* dequeue transfer and start next transfer */
1692 usb2_transfer_done(xfer, error);
1693 return;
1694}
1695
1696/*------------------------------------------------------------------------*
1697 * ohci bulk support
1698 *------------------------------------------------------------------------*/
1699static void
1700ohci_device_bulk_open(struct usb2_xfer *xfer)
1701{
1702 return;
1703}
1704
1705static void
1706ohci_device_bulk_close(struct usb2_xfer *xfer)
1707{
1708 ohci_device_done(xfer, USB_ERR_CANCELLED);
1709 return;
1710}
1711
1712static void
1713ohci_device_bulk_enter(struct usb2_xfer *xfer)
1714{
1715 return;
1716}
1717
1718static void
1719ohci_device_bulk_start(struct usb2_xfer *xfer)
1720{
1721 ohci_softc_t *sc = xfer->usb2_sc;
1722
1723 /* setup TD's and QH */
1724 ohci_setup_standard_chain(xfer, &sc->sc_bulk_p_last);
1725
1726 /* put transfer on interrupt queue */
1727 ohci_transfer_intr_enqueue(xfer);
1728 return;
1729}
1730
1731struct usb2_pipe_methods ohci_device_bulk_methods =
1732{
1733 .open = ohci_device_bulk_open,
1734 .close = ohci_device_bulk_close,
1735 .enter = ohci_device_bulk_enter,
1736 .start = ohci_device_bulk_start,
1737 .enter_is_cancelable = 1,
1738 .start_is_cancelable = 1,
1739};
1740
1741/*------------------------------------------------------------------------*
1742 * ohci control support
1743 *------------------------------------------------------------------------*/
1744static void
1745ohci_device_ctrl_open(struct usb2_xfer *xfer)
1746{
1747 return;
1748}
1749
1750static void
1751ohci_device_ctrl_close(struct usb2_xfer *xfer)
1752{
1753 ohci_device_done(xfer, USB_ERR_CANCELLED);
1754 return;
1755}
1756
1757static void
1758ohci_device_ctrl_enter(struct usb2_xfer *xfer)
1759{
1760 return;
1761}
1762
1763static void
1764ohci_device_ctrl_start(struct usb2_xfer *xfer)
1765{
1766 ohci_softc_t *sc = xfer->usb2_sc;
1767
1768 /* setup TD's and QH */
1769 ohci_setup_standard_chain(xfer, &sc->sc_ctrl_p_last);
1770
1771 /* put transfer on interrupt queue */
1772 ohci_transfer_intr_enqueue(xfer);
1773 return;
1774}
1775
1776struct usb2_pipe_methods ohci_device_ctrl_methods =
1777{
1778 .open = ohci_device_ctrl_open,
1779 .close = ohci_device_ctrl_close,
1780 .enter = ohci_device_ctrl_enter,
1781 .start = ohci_device_ctrl_start,
1782 .enter_is_cancelable = 1,
1783 .start_is_cancelable = 1,
1784};
1785
1786/*------------------------------------------------------------------------*
1787 * ohci interrupt support
1788 *------------------------------------------------------------------------*/
1789static void
1790ohci_device_intr_open(struct usb2_xfer *xfer)
1791{
1792 ohci_softc_t *sc = xfer->usb2_sc;
1793 uint16_t best;
1794 uint16_t bit;
1795 uint16_t x;
1796
1797 best = 0;
1798 bit = OHCI_NO_EDS / 2;
1799 while (bit) {
1800 if (xfer->interval >= bit) {
1801 x = bit;
1802 best = bit;
1803 while (x & bit) {
1804 if (sc->sc_intr_stat[x] <
1805 sc->sc_intr_stat[best]) {
1806 best = x;
1807 }
1808 x++;
1809 }
1810 break;
1811 }
1812 bit >>= 1;
1813 }
1814
1815 sc->sc_intr_stat[best]++;
1816 xfer->qh_pos = best;
1817
1818 DPRINTFN(3, "best=%d interval=%d\n",
1819 best, xfer->interval);
1820 return;
1821}
1822
1823static void
1824ohci_device_intr_close(struct usb2_xfer *xfer)
1825{
1826 ohci_softc_t *sc = xfer->usb2_sc;
1827
1828 sc->sc_intr_stat[xfer->qh_pos]--;
1829
1830 ohci_device_done(xfer, USB_ERR_CANCELLED);
1831 return;
1832}
1833
1834static void
1835ohci_device_intr_enter(struct usb2_xfer *xfer)
1836{
1837 return;
1838}
1839
1840static void
1841ohci_device_intr_start(struct usb2_xfer *xfer)
1842{
1843 ohci_softc_t *sc = xfer->usb2_sc;
1844
1845 /* setup TD's and QH */
1846 ohci_setup_standard_chain(xfer, &sc->sc_intr_p_last[xfer->qh_pos]);
1847
1848 /* put transfer on interrupt queue */
1849 ohci_transfer_intr_enqueue(xfer);
1850 return;
1851}
1852
1853struct usb2_pipe_methods ohci_device_intr_methods =
1854{
1855 .open = ohci_device_intr_open,
1856 .close = ohci_device_intr_close,
1857 .enter = ohci_device_intr_enter,
1858 .start = ohci_device_intr_start,
1859 .enter_is_cancelable = 1,
1860 .start_is_cancelable = 1,
1861};
1862
1863/*------------------------------------------------------------------------*
1864 * ohci isochronous support
1865 *------------------------------------------------------------------------*/
1866static void
1867ohci_device_isoc_open(struct usb2_xfer *xfer)
1868{
1869 return;
1870}
1871
1872static void
1873ohci_device_isoc_close(struct usb2_xfer *xfer)
1874{
1875 /**/
1876 ohci_device_done(xfer, USB_ERR_CANCELLED);
1877 return;
1878}
1879
1880static void
1881ohci_device_isoc_enter(struct usb2_xfer *xfer)
1882{
1883 struct usb2_page_search buf_res;
1884 ohci_softc_t *sc = xfer->usb2_sc;
1885 struct ohci_hcca *hcca;
1886 uint32_t buf_offset;
1887 uint32_t nframes;
1888 uint32_t ed_flags;
1889 uint32_t *plen;
1890 uint16_t itd_offset[OHCI_ITD_NOFFSET];
1891 uint16_t length;
1892 uint8_t ncur;
1893 ohci_itd_t *td;
1894 ohci_itd_t *td_last = NULL;
1895 ohci_ed_t *ed;
1896
1897 hcca = ohci_get_hcca(sc);
1898
1899 nframes = le32toh(hcca->hcca_frame_number);
1900
1901 DPRINTFN(6, "xfer=%p isoc_next=%u nframes=%u hcca_fn=%u\n",
1902 xfer, xfer->pipe->isoc_next, xfer->nframes, nframes);
1903
1904 if ((xfer->pipe->is_synced == 0) ||
1905 (((nframes - xfer->pipe->isoc_next) & 0xFFFF) < xfer->nframes) ||
1906 (((xfer->pipe->isoc_next - nframes) & 0xFFFF) >= 128)) {
1907 /*
1908 * If there is data underflow or the pipe queue is empty we
1909 * schedule the transfer a few frames ahead of the current
1910 * frame position. Else two isochronous transfers might
1911 * overlap.
1912 */
1913 xfer->pipe->isoc_next = (nframes + 3) & 0xFFFF;
1914 xfer->pipe->is_synced = 1;
1915 DPRINTFN(3, "start next=%d\n", xfer->pipe->isoc_next);
1916 }
1917 /*
1918 * compute how many milliseconds the insertion is ahead of the
1919 * current frame position:
1920 */
1921 buf_offset = ((xfer->pipe->isoc_next - nframes) & 0xFFFF);
1922
1923 /*
1924 * pre-compute when the isochronous transfer will be finished:
1925 */
1926 xfer->isoc_time_complete =
1927 (usb2_isoc_time_expand(&sc->sc_bus, nframes) + buf_offset +
1928 xfer->nframes);
1929
1930 /* get the real number of frames */
1931
1932 nframes = xfer->nframes;
1933
1934 buf_offset = 0;
1935
1936 plen = xfer->frlengths;
1937
1938 /* toggle the DMA set we are using */
1939 xfer->flags_int.curr_dma_set ^= 1;
1940
1941 /* get next DMA set */
1942 td = xfer->td_start[xfer->flags_int.curr_dma_set];
1943
1944 xfer->td_transfer_first = td;
1945
1946 ncur = 0;
1947 length = 0;
1948
1949 while (nframes--) {
1950 if (td == NULL) {
1951 panic("%s:%d: out of TD's\n",
1952 __FUNCTION__, __LINE__);
1953 }
1954 itd_offset[ncur] = length;
1955 buf_offset += *plen;
1956 length += *plen;
1957 plen++;
1958 ncur++;
1959
1960 if ( /* check if the ITD is full */
1961 (ncur == OHCI_ITD_NOFFSET) ||
1962 /* check if we have put more than 4K into the ITD */
1963 (length & 0xF000) ||
1964 /* check if it is the last frame */
1965 (nframes == 0)) {
1966
1967 /* fill current ITD */
1968 td->itd_flags = htole32(
1969 OHCI_ITD_NOCC |
1970 OHCI_ITD_SET_SF(xfer->pipe->isoc_next) |
1971 OHCI_ITD_NOINTR |
1972 OHCI_ITD_SET_FC(ncur));
1973
1974 td->frames = ncur;
1975 xfer->pipe->isoc_next += ncur;
1976
1977 if (length == 0) {
1978 /* all zero */
1979 td->itd_bp0 = 0;
1980 td->itd_be = ~0;
1981
1982 while (ncur--) {
1983 td->itd_offset[ncur] =
1984 htole16(OHCI_ITD_MK_OFFS(0));
1985 }
1986 } else {
1987 usb2_get_page(xfer->frbuffers, buf_offset - length, &buf_res);
1988 length = OHCI_PAGE_MASK(buf_res.physaddr);
1989 buf_res.physaddr =
1990 OHCI_PAGE(buf_res.physaddr);
1991 td->itd_bp0 = htole32(buf_res.physaddr);
1992 usb2_get_page(xfer->frbuffers, buf_offset - 1, &buf_res);
1993 td->itd_be = htole32(buf_res.physaddr);
1994
1995 while (ncur--) {
1996 itd_offset[ncur] += length;
1997 itd_offset[ncur] =
1998 OHCI_ITD_MK_OFFS(itd_offset[ncur]);
1999 td->itd_offset[ncur] =
2000 htole16(itd_offset[ncur]);
2001 }
2002 }
2003 ncur = 0;
2004 length = 0;
2005 td_last = td;
2006 td = td->obj_next;
2007
2008 if (td) {
2009 /* link the last TD with the next one */
2010 td_last->itd_next = td->itd_self;
2011 }
2012 usb2_pc_cpu_flush(td_last->page_cache);
2013 }
2014 }
2015
2016 /* update the last TD */
2017 td_last->itd_flags &= ~htole32(OHCI_ITD_NOINTR);
2018 td_last->itd_flags |= htole32(OHCI_ITD_SET_DI(0));
2019 td_last->itd_next = 0;
2020
2021 usb2_pc_cpu_flush(td_last->page_cache);
2022
2023 xfer->td_transfer_last = td_last;
2024
2025#if USB_DEBUG
2026 if (ohcidebug > 8) {
2027 DPRINTF("data before transfer:\n");
2028 ohci_dump_itds(xfer->td_transfer_first);
2029 }
2030#endif
2031 ed = xfer->qh_start[xfer->flags_int.curr_dma_set];
2032
2033 if (UE_GET_DIR(xfer->endpoint) == UE_DIR_IN)
2034 ed_flags = (OHCI_ED_DIR_IN | OHCI_ED_FORMAT_ISO);
2035 else
2036 ed_flags = (OHCI_ED_DIR_OUT | OHCI_ED_FORMAT_ISO);
2037
2038 ed_flags |= (OHCI_ED_SET_FA(xfer->address) |
2039 OHCI_ED_SET_EN(UE_GET_ADDR(xfer->endpoint)) |
2040 OHCI_ED_SET_MAXP(xfer->max_frame_size));
2041
2042 if (xfer->udev->speed == USB_SPEED_LOW) {
2043 ed_flags |= OHCI_ED_SPEED;
2044 }
2045 ed->ed_flags = htole32(ed_flags);
2046
2047 usb2_pc_cpu_flush(ed->page_cache);
2048
2049 td = xfer->td_transfer_first;
2050
2051 OHCI_APPEND_QH(ed, td->itd_self, sc->sc_isoc_p_last);
2052 return;
2053}
2054
2055static void
2056ohci_device_isoc_start(struct usb2_xfer *xfer)
2057{
2058 /* put transfer on interrupt queue */
2059 ohci_transfer_intr_enqueue(xfer);
2060 return;
2061}
2062
2063struct usb2_pipe_methods ohci_device_isoc_methods =
2064{
2065 .open = ohci_device_isoc_open,
2066 .close = ohci_device_isoc_close,
2067 .enter = ohci_device_isoc_enter,
2068 .start = ohci_device_isoc_start,
2069 .enter_is_cancelable = 1,
2070 .start_is_cancelable = 1,
2071};
2072
2073/*------------------------------------------------------------------------*
2074 * ohci root control support
2075 *------------------------------------------------------------------------*
2076 * simulate a hardware hub by handling
2077 * all the necessary requests
2078 *------------------------------------------------------------------------*/
2079
2080static void
2081ohci_root_ctrl_open(struct usb2_xfer *xfer)
2082{
2083 return;
2084}
2085
2086static void
2087ohci_root_ctrl_close(struct usb2_xfer *xfer)
2088{
2089 ohci_softc_t *sc = xfer->usb2_sc;
2090
2091 if (sc->sc_root_ctrl.xfer == xfer) {
2092 sc->sc_root_ctrl.xfer = NULL;
2093 }
2094 ohci_device_done(xfer, USB_ERR_CANCELLED);
2095 return;
2096}
2097
2098/* data structures and routines
2099 * to emulate the root hub:
2100 */
2101static const
2102struct usb2_device_descriptor ohci_devd =
2103{
2104 sizeof(struct usb2_device_descriptor),
2105 UDESC_DEVICE, /* type */
2106 {0x00, 0x01}, /* USB version */
2107 UDCLASS_HUB, /* class */
2108 UDSUBCLASS_HUB, /* subclass */
2109 UDPROTO_FSHUB, /* protocol */
2110 64, /* max packet */
2111 {0}, {0}, {0x00, 0x01}, /* device id */
2112 1, 2, 0, /* string indicies */
2113 1 /* # of configurations */
2114};
2115
2116static const
2117struct ohci_config_desc ohci_confd =
2118{
2119 .confd = {
2120 .bLength = sizeof(struct usb2_config_descriptor),
2121 .bDescriptorType = UDESC_CONFIG,
2122 .wTotalLength[0] = sizeof(ohci_confd),
2123 .bNumInterface = 1,
2124 .bConfigurationValue = 1,
2125 .iConfiguration = 0,
2126 .bmAttributes = UC_SELF_POWERED,
2127 .bMaxPower = 0, /* max power */
2128 },
2129
2130 .ifcd = {
2131 .bLength = sizeof(struct usb2_interface_descriptor),
2132 .bDescriptorType = UDESC_INTERFACE,
2133 .bNumEndpoints = 1,
2134 .bInterfaceClass = UICLASS_HUB,
2135 .bInterfaceSubClass = UISUBCLASS_HUB,
2136 .bInterfaceProtocol = UIPROTO_FSHUB,
2137 },
2138
2139 .endpd = {
2140 .bLength = sizeof(struct usb2_endpoint_descriptor),
2141 .bDescriptorType = UDESC_ENDPOINT,
2142 .bEndpointAddress = UE_DIR_IN | OHCI_INTR_ENDPT,
2143 .bmAttributes = UE_INTERRUPT,
2144 .wMaxPacketSize[0] = 32,/* max packet (255 ports) */
2145 .bInterval = 255,
2146 },
2147};
2148
2149static const
2150struct usb2_hub_descriptor ohci_hubd =
2151{
2152 0, /* dynamic length */
2153 UDESC_HUB,
2154 0,
2155 {0, 0},
2156 0,
2157 0,
2158 {0},
2159};
2160
2161static void
2162ohci_root_ctrl_enter(struct usb2_xfer *xfer)
2163{
2164 return;
2165}
2166
2167static void
2168ohci_root_ctrl_start(struct usb2_xfer *xfer)
2169{
2170 ohci_softc_t *sc = xfer->usb2_sc;
2171
2172 sc->sc_root_ctrl.xfer = xfer;
2173
2174 usb2_config_td_queue_command
2175 (&sc->sc_config_td, NULL, &ohci_root_ctrl_task, 0, 0);
2176
2177 return;
2178}
2179
2180static void
2181ohci_root_ctrl_task(struct ohci_softc *sc,
2182 struct ohci_config_copy *cc, uint16_t refcount)
2183{
2184 ohci_root_ctrl_poll(sc);
2185 return;
2186}
2187
2188static void
2189ohci_root_ctrl_done(struct usb2_xfer *xfer,
2190 struct usb2_sw_transfer *std)
2191{
2192 ohci_softc_t *sc = xfer->usb2_sc;
2193 char *ptr;
2194 uint32_t port;
2195 uint32_t v;
2196 uint16_t value;
2197 uint16_t index;
2198 uint8_t l;
2199 uint8_t use_polling;
2200
2201 mtx_assert(&sc->sc_bus.mtx, MA_OWNED);
2202
2203 if (std->state != USB_SW_TR_SETUP) {
2204 if (std->state == USB_SW_TR_PRE_CALLBACK) {
2205 /* transfer transferred */
2206 ohci_device_done(xfer, std->err);
2207 }
2208 goto done;
2209 }
2210 /* buffer reset */
2211 std->ptr = sc->sc_hub_desc.temp;
2212 std->len = 0;
2213
2214 value = UGETW(std->req.wValue);
2215 index = UGETW(std->req.wIndex);
2216
2217 use_polling = mtx_owned(xfer->priv_mtx) ? 1 : 0;
2218
2219 DPRINTFN(3, "type=0x%02x request=0x%02x wLen=0x%04x "
2220 "wValue=0x%04x wIndex=0x%04x\n",
2221 std->req.bmRequestType, std->req.bRequest,
2222 UGETW(std->req.wLength), value, index);
2223
2224#define C(x,y) ((x) | ((y) << 8))
2225 switch (C(std->req.bRequest, std->req.bmRequestType)) {
2226 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE):
2227 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE):
2228 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT):
2229 /*
2230 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops
2231 * for the integrated root hub.
2232 */
2233 break;
2234 case C(UR_GET_CONFIG, UT_READ_DEVICE):
2235 std->len = 1;
2236 sc->sc_hub_desc.temp[0] = sc->sc_conf;
2237 break;
2238 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE):
2239 switch (value >> 8) {
2240 case UDESC_DEVICE:
2241 if ((value & 0xff) != 0) {
2242 std->err = USB_ERR_IOERROR;
2243 goto done;
2244 }
2245 std->len = sizeof(ohci_devd);
2246 sc->sc_hub_desc.devd = ohci_devd;
2247 break;
2248
2249 case UDESC_CONFIG:
2250 if ((value & 0xff) != 0) {
2251 std->err = USB_ERR_IOERROR;
2252 goto done;
2253 }
2254 std->len = sizeof(ohci_confd);
2255 std->ptr = USB_ADD_BYTES(&ohci_confd, 0);
2256 break;
2257
2258 case UDESC_STRING:
2259 switch (value & 0xff) {
2260 case 0: /* Language table */
2261 ptr = "\001";
2262 break;
2263
2264 case 1: /* Vendor */
2265 ptr = sc->sc_vendor;
2266 break;
2267
2268 case 2: /* Product */
2269 ptr = "OHCI root HUB";
2270 break;
2271
2272 default:
2273 ptr = "";
2274 break;
2275 }
2276
2277 std->len = usb2_make_str_desc
2278 (sc->sc_hub_desc.temp,
2279 sizeof(sc->sc_hub_desc.temp),
2280 ptr);
2281 break;
2282
2283 default:
2284 std->err = USB_ERR_IOERROR;
2285 goto done;
2286 }
2287 break;
2288 case C(UR_GET_INTERFACE, UT_READ_INTERFACE):
2289 std->len = 1;
2290 sc->sc_hub_desc.temp[0] = 0;
2291 break;
2292 case C(UR_GET_STATUS, UT_READ_DEVICE):
2293 std->len = 2;
2294 USETW(sc->sc_hub_desc.stat.wStatus, UDS_SELF_POWERED);
2295 break;
2296 case C(UR_GET_STATUS, UT_READ_INTERFACE):
2297 case C(UR_GET_STATUS, UT_READ_ENDPOINT):
2298 std->len = 2;
2299 USETW(sc->sc_hub_desc.stat.wStatus, 0);
2300 break;
2301 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE):
2302 if (value >= USB_MAX_DEVICES) {
2303 std->err = USB_ERR_IOERROR;
2304 goto done;
2305 }
2306 sc->sc_addr = value;
2307 break;
2308 case C(UR_SET_CONFIG, UT_WRITE_DEVICE):
2309 if ((value != 0) && (value != 1)) {
2310 std->err = USB_ERR_IOERROR;
2311 goto done;
2312 }
2313 sc->sc_conf = value;
2314 break;
2315 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE):
2316 break;
2317 case C(UR_SET_FEATURE, UT_WRITE_DEVICE):
2318 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE):
2319 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT):
2320 std->err = USB_ERR_IOERROR;
2321 goto done;
2322 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE):
2323 break;
2324 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT):
2325 break;
2326 /* Hub requests */
2327 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE):
2328 break;
2329 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER):
2330 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE "
2331 "port=%d feature=%d\n",
2332 index, value);
2333 if ((index < 1) ||
2334 (index > sc->sc_noport)) {
2335 std->err = USB_ERR_IOERROR;
2336 goto done;
2337 }
2338 port = OHCI_RH_PORT_STATUS(index);
2339 switch (value) {
2340 case UHF_PORT_ENABLE:
2341 OWRITE4(sc, port, UPS_CURRENT_CONNECT_STATUS);
2342 break;
2343 case UHF_PORT_SUSPEND:
2344 OWRITE4(sc, port, UPS_OVERCURRENT_INDICATOR);
2345 break;
2346 case UHF_PORT_POWER:
2347 /* Yes, writing to the LOW_SPEED bit clears power. */
2348 OWRITE4(sc, port, UPS_LOW_SPEED);
2349 break;
2350 case UHF_C_PORT_CONNECTION:
2351 OWRITE4(sc, port, UPS_C_CONNECT_STATUS << 16);
2352 break;
2353 case UHF_C_PORT_ENABLE:
2354 OWRITE4(sc, port, UPS_C_PORT_ENABLED << 16);
2355 break;
2356 case UHF_C_PORT_SUSPEND:
2357 OWRITE4(sc, port, UPS_C_SUSPEND << 16);
2358 break;
2359 case UHF_C_PORT_OVER_CURRENT:
2360 OWRITE4(sc, port, UPS_C_OVERCURRENT_INDICATOR << 16);
2361 break;
2362 case UHF_C_PORT_RESET:
2363 OWRITE4(sc, port, UPS_C_PORT_RESET << 16);
2364 break;
2365 default:
2366 std->err = USB_ERR_IOERROR;
2367 goto done;
2368 }
2369 switch (value) {
2370 case UHF_C_PORT_CONNECTION:
2371 case UHF_C_PORT_ENABLE:
2372 case UHF_C_PORT_SUSPEND:
2373 case UHF_C_PORT_OVER_CURRENT:
2374 case UHF_C_PORT_RESET:
2375 /* enable RHSC interrupt if condition is cleared. */
2376 if ((OREAD4(sc, port) >> 16) == 0) {
2377 ohci_rhsc_enable(sc);
2378 mtx_lock(&sc->sc_bus.mtx);
2379 }
2380 break;
2381 default:
2382 break;
2383 }
2384 break;
2385 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE):
2386 if ((value & 0xff) != 0) {
2387 std->err = USB_ERR_IOERROR;
2388 goto done;
2389 }
2390 v = OREAD4(sc, OHCI_RH_DESCRIPTOR_A);
2391
2392 sc->sc_hub_desc.hubd = ohci_hubd;
2393 sc->sc_hub_desc.hubd.bNbrPorts = sc->sc_noport;
2394 USETW(sc->sc_hub_desc.hubd.wHubCharacteristics,
2395 (v & OHCI_NPS ? UHD_PWR_NO_SWITCH :
2396 v & OHCI_PSM ? UHD_PWR_GANGED : UHD_PWR_INDIVIDUAL)
2397 /* XXX overcurrent */
2398 );
2399 sc->sc_hub_desc.hubd.bPwrOn2PwrGood = OHCI_GET_POTPGT(v);
2400 v = OREAD4(sc, OHCI_RH_DESCRIPTOR_B);
2401
2402 for (l = 0; l < sc->sc_noport; l++) {
2403 if (v & 1) {
2404 sc->sc_hub_desc.hubd.DeviceRemovable[l / 8] |= (1 << (l % 8));
2405 }
2406 v >>= 1;
2407 }
2408 sc->sc_hub_desc.hubd.bDescLength =
2409 8 + ((sc->sc_noport + 7) / 8);
2410 std->len = sc->sc_hub_desc.hubd.bDescLength;
2411 break;
2412
2413 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE):
2414 std->len = 16;
2415 bzero(sc->sc_hub_desc.temp, 16);
2416 break;
2417 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER):
2418 DPRINTFN(9, "get port status i=%d\n",
2419 index);
2420 if ((index < 1) ||
2421 (index > sc->sc_noport)) {
2422 std->err = USB_ERR_IOERROR;
2423 goto done;
2424 }
2425 v = OREAD4(sc, OHCI_RH_PORT_STATUS(index));
2426 DPRINTFN(9, "port status=0x%04x\n", v);
2427 USETW(sc->sc_hub_desc.ps.wPortStatus, v);
2428 USETW(sc->sc_hub_desc.ps.wPortChange, v >> 16);
2429 std->len = sizeof(sc->sc_hub_desc.ps);
2430 break;
2431 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE):
2432 std->err = USB_ERR_IOERROR;
2433 goto done;
2434 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE):
2435 break;
2436 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER):
2437 if ((index < 1) ||
2438 (index > sc->sc_noport)) {
2439 std->err = USB_ERR_IOERROR;
2440 goto done;
2441 }
2442 port = OHCI_RH_PORT_STATUS(index);
2443 switch (value) {
2444 case UHF_PORT_ENABLE:
2445 OWRITE4(sc, port, UPS_PORT_ENABLED);
2446 break;
2447 case UHF_PORT_SUSPEND:
2448 OWRITE4(sc, port, UPS_SUSPEND);
2449 break;
2450 case UHF_PORT_RESET:
2451 DPRINTFN(6, "reset port %d\n", index);
2452 OWRITE4(sc, port, UPS_RESET);
2453 for (v = 0;; v++) {
2454 if (v < 12) {
2455 if (use_polling) {
2456 /* polling */
2457 DELAY(USB_PORT_ROOT_RESET_DELAY * 1000);
2458 } else {
2459 usb2_pause_mtx(&sc->sc_bus.mtx,
2460 USB_PORT_ROOT_RESET_DELAY);
2461 }
2462
2463 if ((OREAD4(sc, port) & UPS_RESET) == 0) {
2464 break;
2465 }
2466 } else {
2467 std->err = USB_ERR_TIMEOUT;
2468 goto done;
2469 }
2470 }
2471 DPRINTFN(9, "ohci port %d reset, status = 0x%04x\n",
2472 index, OREAD4(sc, port));
2473 break;
2474 case UHF_PORT_POWER:
2475 DPRINTFN(3, "set port power %d\n", index);
2476 OWRITE4(sc, port, UPS_PORT_POWER);
2477 break;
2478 default:
2479 std->err = USB_ERR_IOERROR;
2480 goto done;
2481 }
2482 break;
2483 default:
2484 std->err = USB_ERR_IOERROR;
2485 goto done;
2486 }
2487done:
2488 return;
2489}
2490
2491static void
2492ohci_root_ctrl_poll(struct ohci_softc *sc)
2493{
2494 usb2_sw_transfer(&sc->sc_root_ctrl,
2495 &ohci_root_ctrl_done);
2496 return;
2497}
2498
2499struct usb2_pipe_methods ohci_root_ctrl_methods =
2500{
2501 .open = ohci_root_ctrl_open,
2502 .close = ohci_root_ctrl_close,
2503 .enter = ohci_root_ctrl_enter,
2504 .start = ohci_root_ctrl_start,
2505 .enter_is_cancelable = 1,
2506 .start_is_cancelable = 0,
2507};
2508
2509/*------------------------------------------------------------------------*
2510 * ohci root interrupt support
2511 *------------------------------------------------------------------------*/
2512static void
2513ohci_root_intr_open(struct usb2_xfer *xfer)
2514{
2515 return;
2516}
2517
2518static void
2519ohci_root_intr_close(struct usb2_xfer *xfer)
2520{
2521 ohci_softc_t *sc = xfer->usb2_sc;
2522
2523 if (sc->sc_root_intr.xfer == xfer) {
2524 sc->sc_root_intr.xfer = NULL;
2525 }
2526 ohci_device_done(xfer, USB_ERR_CANCELLED);
2527 return;
2528}
2529
2530static void
2531ohci_root_intr_enter(struct usb2_xfer *xfer)
2532{
2533 return;
2534}
2535
2536static void
2537ohci_root_intr_start(struct usb2_xfer *xfer)
2538{
2539 ohci_softc_t *sc = xfer->usb2_sc;
2540
2541 sc->sc_root_intr.xfer = xfer;
2542 return;
2543}
2544
2545struct usb2_pipe_methods ohci_root_intr_methods =
2546{
2547 .open = ohci_root_intr_open,
2548 .close = ohci_root_intr_close,
2549 .enter = ohci_root_intr_enter,
2550 .start = ohci_root_intr_start,
2551 .enter_is_cancelable = 1,
2552 .start_is_cancelable = 1,
2553};
2554
2555static void
2556ohci_xfer_setup(struct usb2_setup_params *parm)
2557{
2558 struct usb2_page_search page_info;
2559 struct usb2_page_cache *pc;
2560 ohci_softc_t *sc;
2561 struct usb2_xfer *xfer;
2562 void *last_obj;
2563 uint32_t ntd;
2564 uint32_t nitd;
2565 uint32_t nqh;
2566 uint32_t n;
2567
2568 sc = OHCI_BUS2SC(parm->udev->bus);
2569 xfer = parm->curr_xfer;
2570
2571 /*
2572 * setup xfer
2573 */
2574 xfer->usb2_sc = sc;
2575
2576 parm->hc_max_packet_size = 0x500;
2577 parm->hc_max_packet_count = 1;
2578 parm->hc_max_frame_size = OHCI_PAGE_SIZE;
2579
2580 /*
2581 * calculate ntd and nqh
2582 */
2583 if (parm->methods == &ohci_device_ctrl_methods) {
2584 xfer->flags_int.bdma_enable = 1;
2585
2586 usb2_transfer_setup_sub(parm);
2587
2588 nitd = 0;
2589 ntd = ((2 * xfer->nframes) + 1 /* STATUS */
2590 + (xfer->max_data_length / xfer->max_usb2_frame_size));
2591 nqh = 1;
2592
2593 } else if (parm->methods == &ohci_device_bulk_methods) {
2594 xfer->flags_int.bdma_enable = 1;
2595
2596 usb2_transfer_setup_sub(parm);
2597
2598 nitd = 0;
2599 ntd = ((2 * xfer->nframes)
2600 + (xfer->max_data_length / xfer->max_usb2_frame_size));
2601 nqh = 1;
2602
2603 } else if (parm->methods == &ohci_device_intr_methods) {
2604 xfer->flags_int.bdma_enable = 1;
2605
2606 usb2_transfer_setup_sub(parm);
2607
2608 nitd = 0;
2609 ntd = ((2 * xfer->nframes)
2610 + (xfer->max_data_length / xfer->max_usb2_frame_size));
2611 nqh = 1;
2612
2613 } else if (parm->methods == &ohci_device_isoc_methods) {
2614 xfer->flags_int.bdma_enable = 1;
2615
2616 usb2_transfer_setup_sub(parm);
2617
2618 nitd = ((xfer->max_data_length / OHCI_PAGE_SIZE) +
2619 ((xfer->nframes + OHCI_ITD_NOFFSET - 1) / OHCI_ITD_NOFFSET) +
2620 1 /* EXTRA */ );
2621 ntd = 0;
2622 nqh = 1;
2623
2624 } else {
2625
2626 usb2_transfer_setup_sub(parm);
2627
2628 nitd = 0;
2629 ntd = 0;
2630 nqh = 0;
2631 }
2632
2633alloc_dma_set:
2634
2635 if (parm->err) {
2636 return;
2637 }
2638 last_obj = NULL;
2639
2640 if (usb2_transfer_setup_sub_malloc(
2641 parm, &pc, sizeof(ohci_td_t),
2642 OHCI_TD_ALIGN, ntd)) {
2643 parm->err = USB_ERR_NOMEM;
2644 return;
2645 }
2646 if (parm->buf) {
2647 for (n = 0; n != ntd; n++) {
2648 ohci_td_t *td;
2649
2650 usb2_get_page(pc + n, 0, &page_info);
2651
2652 td = page_info.buffer;
2653
2654 /* init TD */
2655 td->td_self = htole32(page_info.physaddr);
2656 td->obj_next = last_obj;
2657 td->page_cache = pc + n;
2658
2659 last_obj = td;
2660
2661 usb2_pc_cpu_flush(pc + n);
2662 }
2663 }
2664 if (usb2_transfer_setup_sub_malloc(
2665 parm, &pc, sizeof(ohci_itd_t),
2666 OHCI_ITD_ALIGN, nitd)) {
2667 parm->err = USB_ERR_NOMEM;
2668 return;
2669 }
2670 if (parm->buf) {
2671 for (n = 0; n != nitd; n++) {
2672 ohci_itd_t *itd;
2673
2674 usb2_get_page(pc + n, 0, &page_info);
2675
2676 itd = page_info.buffer;
2677
2678 /* init TD */
2679 itd->itd_self = htole32(page_info.physaddr);
2680 itd->obj_next = last_obj;
2681 itd->page_cache = pc + n;
2682
2683 last_obj = itd;
2684
2685 usb2_pc_cpu_flush(pc + n);
2686 }
2687 }
2688 xfer->td_start[xfer->flags_int.curr_dma_set] = last_obj;
2689
2690 last_obj = NULL;
2691
2692 if (usb2_transfer_setup_sub_malloc(
2693 parm, &pc, sizeof(ohci_ed_t),
2694 OHCI_ED_ALIGN, nqh)) {
2695 parm->err = USB_ERR_NOMEM;
2696 return;
2697 }
2698 if (parm->buf) {
2699 for (n = 0; n != nqh; n++) {
2700 ohci_ed_t *ed;
2701
2702 usb2_get_page(pc + n, 0, &page_info);
2703
2704 ed = page_info.buffer;
2705
2706 /* init QH */
2707 ed->ed_self = htole32(page_info.physaddr);
2708 ed->obj_next = last_obj;
2709 ed->page_cache = pc + n;
2710
2711 last_obj = ed;
2712
2713 usb2_pc_cpu_flush(pc + n);
2714 }
2715 }
2716 xfer->qh_start[xfer->flags_int.curr_dma_set] = last_obj;
2717
2718 if (!xfer->flags_int.curr_dma_set) {
2719 xfer->flags_int.curr_dma_set = 1;
2720 goto alloc_dma_set;
2721 }
2722 return;
2723}
2724
2725static void
2726ohci_pipe_init(struct usb2_device *udev, struct usb2_endpoint_descriptor *edesc,
2727 struct usb2_pipe *pipe)
2728{
2729 ohci_softc_t *sc = OHCI_BUS2SC(udev->bus);
2730
2731 DPRINTFN(2, "pipe=%p, addr=%d, endpt=%d, mode=%d (%d)\n",
2732 pipe, udev->address,
2733 edesc->bEndpointAddress, udev->flags.usb2_mode,
2734 sc->sc_addr);
2735
2736 if (udev->flags.usb2_mode != USB_MODE_HOST) {
2737 /* not supported */
2738 return;
2739 }
2740 if (udev->device_index == sc->sc_addr) {
2741 switch (edesc->bEndpointAddress) {
2742 case USB_CONTROL_ENDPOINT:
2743 pipe->methods = &ohci_root_ctrl_methods;
2744 break;
2745 case UE_DIR_IN | OHCI_INTR_ENDPT:
2746 pipe->methods = &ohci_root_intr_methods;
2747 break;
2748 default:
2749 /* do nothing */
2750 break;
2751 }
2752 } else {
2753 switch (edesc->bmAttributes & UE_XFERTYPE) {
2754 case UE_CONTROL:
2755 pipe->methods = &ohci_device_ctrl_methods;
2756 break;
2757 case UE_INTERRUPT:
2758 pipe->methods = &ohci_device_intr_methods;
2759 break;
2760 case UE_ISOCHRONOUS:
2761 if (udev->speed == USB_SPEED_FULL) {
2762 pipe->methods = &ohci_device_isoc_methods;
2763 }
2764 break;
2765 case UE_BULK:
2766 if (udev->speed != USB_SPEED_LOW) {
2767 pipe->methods = &ohci_device_bulk_methods;
2768 }
2769 break;
2770 default:
2771 /* do nothing */
2772 break;
2773 }
2774 }
2775 return;
2776}
2777
2778static void
2779ohci_xfer_unsetup(struct usb2_xfer *xfer)
2780{
2781 return;
2782}
2783
2784static void
2785ohci_get_dma_delay(struct usb2_bus *bus, uint32_t *pus)
2786{
2787 /*
2788 * Wait until hardware has finished any possible use of the
2789 * transfer descriptor(s) and QH
2790 */
2791 *pus = (1125); /* microseconds */
2792 return;
2793}
2794
2795struct usb2_bus_methods ohci_bus_methods =
2796{
2797 .pipe_init = ohci_pipe_init,
2798 .xfer_setup = ohci_xfer_setup,
2799 .xfer_unsetup = ohci_xfer_unsetup,
2800 .do_poll = ohci_do_poll,
2801 .get_dma_delay = ohci_get_dma_delay,
2802};