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ehci.c (193644) ehci.c (194228)
1/*-
2 * Copyright (c) 2008 Hans Petter Selasky. All rights reserved.
3 * Copyright (c) 2004 The NetBSD Foundation, Inc. All rights reserved.
4 * Copyright (c) 2004 Lennart Augustsson. All rights reserved.
5 * Copyright (c) 2004 Charles M. Hannum. All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29/*
30 * USB Enhanced Host Controller Driver, a.k.a. USB 2.0 controller.
31 *
32 * The EHCI 0.96 spec can be found at
33 * http://developer.intel.com/technology/usb/download/ehci-r096.pdf
34 * The EHCI 1.0 spec can be found at
35 * http://developer.intel.com/technology/usb/download/ehci-r10.pdf
36 * and the USB 2.0 spec at
37 * http://www.usb.org/developers/docs/usb_20.zip
38 *
39 */
40
41/*
42 * TODO:
43 * 1) command failures are not recovered correctly
44 */
45
46#include <sys/cdefs.h>
1/*-
2 * Copyright (c) 2008 Hans Petter Selasky. All rights reserved.
3 * Copyright (c) 2004 The NetBSD Foundation, Inc. All rights reserved.
4 * Copyright (c) 2004 Lennart Augustsson. All rights reserved.
5 * Copyright (c) 2004 Charles M. Hannum. All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29/*
30 * USB Enhanced Host Controller Driver, a.k.a. USB 2.0 controller.
31 *
32 * The EHCI 0.96 spec can be found at
33 * http://developer.intel.com/technology/usb/download/ehci-r096.pdf
34 * The EHCI 1.0 spec can be found at
35 * http://developer.intel.com/technology/usb/download/ehci-r10.pdf
36 * and the USB 2.0 spec at
37 * http://www.usb.org/developers/docs/usb_20.zip
38 *
39 */
40
41/*
42 * TODO:
43 * 1) command failures are not recovered correctly
44 */
45
46#include <sys/cdefs.h>
47__FBSDID("$FreeBSD: head/sys/dev/usb/controller/ehci.c 193644 2009-06-07 19:41:11Z thompsa $");
47__FBSDID("$FreeBSD: head/sys/dev/usb/controller/ehci.c 194228 2009-06-15 01:02:43Z thompsa $");
48
49#include <dev/usb/usb.h>
50#include <dev/usb/usb_mfunc.h>
51#include <dev/usb/usb_error.h>
52
53#define USB_DEBUG_VAR ehcidebug
54
55#include <dev/usb/usb_core.h>
56#include <dev/usb/usb_debug.h>
57#include <dev/usb/usb_busdma.h>
58#include <dev/usb/usb_process.h>
59#include <dev/usb/usb_transfer.h>
60#include <dev/usb/usb_device.h>
61#include <dev/usb/usb_hub.h>
62#include <dev/usb/usb_util.h>
63
64#include <dev/usb/usb_controller.h>
65#include <dev/usb/usb_bus.h>
66#include <dev/usb/controller/ehci.h>
67
68#define EHCI_BUS2SC(bus) \
69 ((ehci_softc_t *)(((uint8_t *)(bus)) - \
70 ((uint8_t *)&(((ehci_softc_t *)0)->sc_bus))))
71
72#if USB_DEBUG
73static int ehcidebug = 0;
74static int ehcinohighspeed = 0;
75
76SYSCTL_NODE(_hw_usb, OID_AUTO, ehci, CTLFLAG_RW, 0, "USB ehci");
77SYSCTL_INT(_hw_usb_ehci, OID_AUTO, debug, CTLFLAG_RW,
78 &ehcidebug, 0, "Debug level");
79SYSCTL_INT(_hw_usb_ehci, OID_AUTO, no_hs, CTLFLAG_RW,
80 &ehcinohighspeed, 0, "Disable High Speed USB");
81
82static void ehci_dump_regs(ehci_softc_t *sc);
83static void ehci_dump_sqh(ehci_softc_t *sc, ehci_qh_t *sqh);
84
85#endif
86
87#define EHCI_INTR_ENDPT 1
88
89extern struct usb_bus_methods ehci_bus_methods;
90extern struct usb_pipe_methods ehci_device_bulk_methods;
91extern struct usb_pipe_methods ehci_device_ctrl_methods;
92extern struct usb_pipe_methods ehci_device_intr_methods;
93extern struct usb_pipe_methods ehci_device_isoc_fs_methods;
94extern struct usb_pipe_methods ehci_device_isoc_hs_methods;
95
96static void ehci_do_poll(struct usb_bus *bus);
97static void ehci_device_done(struct usb_xfer *xfer, usb_error_t error);
98static uint8_t ehci_check_transfer(struct usb_xfer *xfer);
99static void ehci_timeout(void *arg);
100static void ehci_root_intr(ehci_softc_t *sc);
101
102struct ehci_std_temp {
103 ehci_softc_t *sc;
104 struct usb_page_cache *pc;
105 ehci_qtd_t *td;
106 ehci_qtd_t *td_next;
107 uint32_t average;
108 uint32_t qtd_status;
109 uint32_t len;
110 uint16_t max_frame_size;
111 uint8_t shortpkt;
112 uint8_t auto_data_toggle;
113 uint8_t setup_alt_next;
114 uint8_t last_frame;
115};
116
117void
118ehci_iterate_hw_softc(struct usb_bus *bus, usb_bus_mem_sub_cb_t *cb)
119{
120 ehci_softc_t *sc = EHCI_BUS2SC(bus);
121 uint32_t i;
122
123 cb(bus, &sc->sc_hw.pframes_pc, &sc->sc_hw.pframes_pg,
124 sizeof(uint32_t) * EHCI_FRAMELIST_COUNT, EHCI_FRAMELIST_ALIGN);
125
126 cb(bus, &sc->sc_hw.async_start_pc, &sc->sc_hw.async_start_pg,
127 sizeof(ehci_qh_t), EHCI_QH_ALIGN);
128
129 for (i = 0; i != EHCI_VIRTUAL_FRAMELIST_COUNT; i++) {
130 cb(bus, sc->sc_hw.intr_start_pc + i,
131 sc->sc_hw.intr_start_pg + i,
132 sizeof(ehci_qh_t), EHCI_QH_ALIGN);
133 }
134
135 for (i = 0; i != EHCI_VIRTUAL_FRAMELIST_COUNT; i++) {
136 cb(bus, sc->sc_hw.isoc_hs_start_pc + i,
137 sc->sc_hw.isoc_hs_start_pg + i,
138 sizeof(ehci_itd_t), EHCI_ITD_ALIGN);
139 }
140
141 for (i = 0; i != EHCI_VIRTUAL_FRAMELIST_COUNT; i++) {
142 cb(bus, sc->sc_hw.isoc_fs_start_pc + i,
143 sc->sc_hw.isoc_fs_start_pg + i,
144 sizeof(ehci_sitd_t), EHCI_SITD_ALIGN);
145 }
146}
147
148usb_error_t
149ehci_reset(ehci_softc_t *sc)
150{
151 uint32_t hcr;
152 int i;
153
154 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET);
155 for (i = 0; i < 100; i++) {
48
49#include <dev/usb/usb.h>
50#include <dev/usb/usb_mfunc.h>
51#include <dev/usb/usb_error.h>
52
53#define USB_DEBUG_VAR ehcidebug
54
55#include <dev/usb/usb_core.h>
56#include <dev/usb/usb_debug.h>
57#include <dev/usb/usb_busdma.h>
58#include <dev/usb/usb_process.h>
59#include <dev/usb/usb_transfer.h>
60#include <dev/usb/usb_device.h>
61#include <dev/usb/usb_hub.h>
62#include <dev/usb/usb_util.h>
63
64#include <dev/usb/usb_controller.h>
65#include <dev/usb/usb_bus.h>
66#include <dev/usb/controller/ehci.h>
67
68#define EHCI_BUS2SC(bus) \
69 ((ehci_softc_t *)(((uint8_t *)(bus)) - \
70 ((uint8_t *)&(((ehci_softc_t *)0)->sc_bus))))
71
72#if USB_DEBUG
73static int ehcidebug = 0;
74static int ehcinohighspeed = 0;
75
76SYSCTL_NODE(_hw_usb, OID_AUTO, ehci, CTLFLAG_RW, 0, "USB ehci");
77SYSCTL_INT(_hw_usb_ehci, OID_AUTO, debug, CTLFLAG_RW,
78 &ehcidebug, 0, "Debug level");
79SYSCTL_INT(_hw_usb_ehci, OID_AUTO, no_hs, CTLFLAG_RW,
80 &ehcinohighspeed, 0, "Disable High Speed USB");
81
82static void ehci_dump_regs(ehci_softc_t *sc);
83static void ehci_dump_sqh(ehci_softc_t *sc, ehci_qh_t *sqh);
84
85#endif
86
87#define EHCI_INTR_ENDPT 1
88
89extern struct usb_bus_methods ehci_bus_methods;
90extern struct usb_pipe_methods ehci_device_bulk_methods;
91extern struct usb_pipe_methods ehci_device_ctrl_methods;
92extern struct usb_pipe_methods ehci_device_intr_methods;
93extern struct usb_pipe_methods ehci_device_isoc_fs_methods;
94extern struct usb_pipe_methods ehci_device_isoc_hs_methods;
95
96static void ehci_do_poll(struct usb_bus *bus);
97static void ehci_device_done(struct usb_xfer *xfer, usb_error_t error);
98static uint8_t ehci_check_transfer(struct usb_xfer *xfer);
99static void ehci_timeout(void *arg);
100static void ehci_root_intr(ehci_softc_t *sc);
101
102struct ehci_std_temp {
103 ehci_softc_t *sc;
104 struct usb_page_cache *pc;
105 ehci_qtd_t *td;
106 ehci_qtd_t *td_next;
107 uint32_t average;
108 uint32_t qtd_status;
109 uint32_t len;
110 uint16_t max_frame_size;
111 uint8_t shortpkt;
112 uint8_t auto_data_toggle;
113 uint8_t setup_alt_next;
114 uint8_t last_frame;
115};
116
117void
118ehci_iterate_hw_softc(struct usb_bus *bus, usb_bus_mem_sub_cb_t *cb)
119{
120 ehci_softc_t *sc = EHCI_BUS2SC(bus);
121 uint32_t i;
122
123 cb(bus, &sc->sc_hw.pframes_pc, &sc->sc_hw.pframes_pg,
124 sizeof(uint32_t) * EHCI_FRAMELIST_COUNT, EHCI_FRAMELIST_ALIGN);
125
126 cb(bus, &sc->sc_hw.async_start_pc, &sc->sc_hw.async_start_pg,
127 sizeof(ehci_qh_t), EHCI_QH_ALIGN);
128
129 for (i = 0; i != EHCI_VIRTUAL_FRAMELIST_COUNT; i++) {
130 cb(bus, sc->sc_hw.intr_start_pc + i,
131 sc->sc_hw.intr_start_pg + i,
132 sizeof(ehci_qh_t), EHCI_QH_ALIGN);
133 }
134
135 for (i = 0; i != EHCI_VIRTUAL_FRAMELIST_COUNT; i++) {
136 cb(bus, sc->sc_hw.isoc_hs_start_pc + i,
137 sc->sc_hw.isoc_hs_start_pg + i,
138 sizeof(ehci_itd_t), EHCI_ITD_ALIGN);
139 }
140
141 for (i = 0; i != EHCI_VIRTUAL_FRAMELIST_COUNT; i++) {
142 cb(bus, sc->sc_hw.isoc_fs_start_pc + i,
143 sc->sc_hw.isoc_fs_start_pg + i,
144 sizeof(ehci_sitd_t), EHCI_SITD_ALIGN);
145 }
146}
147
148usb_error_t
149ehci_reset(ehci_softc_t *sc)
150{
151 uint32_t hcr;
152 int i;
153
154 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET);
155 for (i = 0; i < 100; i++) {
156 usb2_pause_mtx(NULL, hz / 1000);
156 usb_pause_mtx(NULL, hz / 1000);
157 hcr = EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_HCRESET;
158 if (!hcr) {
159 if (sc->sc_flags & (EHCI_SCFLG_SETMODE | EHCI_SCFLG_BIGEMMIO)) {
160 /*
161 * Force USBMODE as requested. Controllers
162 * may have multiple operating modes.
163 */
164 uint32_t usbmode = EOREAD4(sc, EHCI_USBMODE);
165 if (sc->sc_flags & EHCI_SCFLG_SETMODE) {
166 usbmode = (usbmode &~ EHCI_UM_CM) | EHCI_UM_CM_HOST;
167 device_printf(sc->sc_bus.bdev,
168 "set host controller mode\n");
169 }
170 if (sc->sc_flags & EHCI_SCFLG_BIGEMMIO) {
171 usbmode = (usbmode &~ EHCI_UM_ES) | EHCI_UM_ES_BE;
172 device_printf(sc->sc_bus.bdev,
173 "set big-endian mode\n");
174 }
175 EOWRITE4(sc, EHCI_USBMODE, usbmode);
176 }
177 return (0);
178 }
179 }
180 device_printf(sc->sc_bus.bdev, "reset timeout\n");
181 return (USB_ERR_IOERROR);
182}
183
184static usb_error_t
185ehci_hcreset(ehci_softc_t *sc)
186{
187 uint32_t hcr;
188 int i;
189
190 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */
191 for (i = 0; i < 100; i++) {
157 hcr = EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_HCRESET;
158 if (!hcr) {
159 if (sc->sc_flags & (EHCI_SCFLG_SETMODE | EHCI_SCFLG_BIGEMMIO)) {
160 /*
161 * Force USBMODE as requested. Controllers
162 * may have multiple operating modes.
163 */
164 uint32_t usbmode = EOREAD4(sc, EHCI_USBMODE);
165 if (sc->sc_flags & EHCI_SCFLG_SETMODE) {
166 usbmode = (usbmode &~ EHCI_UM_CM) | EHCI_UM_CM_HOST;
167 device_printf(sc->sc_bus.bdev,
168 "set host controller mode\n");
169 }
170 if (sc->sc_flags & EHCI_SCFLG_BIGEMMIO) {
171 usbmode = (usbmode &~ EHCI_UM_ES) | EHCI_UM_ES_BE;
172 device_printf(sc->sc_bus.bdev,
173 "set big-endian mode\n");
174 }
175 EOWRITE4(sc, EHCI_USBMODE, usbmode);
176 }
177 return (0);
178 }
179 }
180 device_printf(sc->sc_bus.bdev, "reset timeout\n");
181 return (USB_ERR_IOERROR);
182}
183
184static usb_error_t
185ehci_hcreset(ehci_softc_t *sc)
186{
187 uint32_t hcr;
188 int i;
189
190 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */
191 for (i = 0; i < 100; i++) {
192 usb2_pause_mtx(NULL, hz / 1000);
192 usb_pause_mtx(NULL, hz / 1000);
193 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH;
194 if (hcr)
195 break;
196 }
197 if (!hcr)
198 /*
199 * Fall through and try reset anyway even though
200 * Table 2-9 in the EHCI spec says this will result
201 * in undefined behavior.
202 */
203 device_printf(sc->sc_bus.bdev, "stop timeout\n");
204
205 return ehci_reset(sc);
206}
207
208usb_error_t
209ehci_init(ehci_softc_t *sc)
210{
211 struct usb_page_search buf_res;
212 uint32_t version;
213 uint32_t sparams;
214 uint32_t cparams;
215 uint32_t hcr;
216 uint16_t i;
217 uint16_t x;
218 uint16_t y;
219 uint16_t bit;
220 usb_error_t err = 0;
221
222 DPRINTF("start\n");
223
193 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH;
194 if (hcr)
195 break;
196 }
197 if (!hcr)
198 /*
199 * Fall through and try reset anyway even though
200 * Table 2-9 in the EHCI spec says this will result
201 * in undefined behavior.
202 */
203 device_printf(sc->sc_bus.bdev, "stop timeout\n");
204
205 return ehci_reset(sc);
206}
207
208usb_error_t
209ehci_init(ehci_softc_t *sc)
210{
211 struct usb_page_search buf_res;
212 uint32_t version;
213 uint32_t sparams;
214 uint32_t cparams;
215 uint32_t hcr;
216 uint16_t i;
217 uint16_t x;
218 uint16_t y;
219 uint16_t bit;
220 usb_error_t err = 0;
221
222 DPRINTF("start\n");
223
224 usb2_callout_init_mtx(&sc->sc_tmo_pcd, &sc->sc_bus.bus_mtx, 0);
224 usb_callout_init_mtx(&sc->sc_tmo_pcd, &sc->sc_bus.bus_mtx, 0);
225
226#if USB_DEBUG
227 if (ehcidebug > 2) {
228 ehci_dump_regs(sc);
229 }
230#endif
231
232 sc->sc_offs = EREAD1(sc, EHCI_CAPLENGTH);
233
234 version = EREAD2(sc, EHCI_HCIVERSION);
235 device_printf(sc->sc_bus.bdev, "EHCI version %x.%x\n",
236 version >> 8, version & 0xff);
237
238 sparams = EREAD4(sc, EHCI_HCSPARAMS);
239 DPRINTF("sparams=0x%x\n", sparams);
240
241 sc->sc_noport = EHCI_HCS_N_PORTS(sparams);
242 cparams = EREAD4(sc, EHCI_HCCPARAMS);
243 DPRINTF("cparams=0x%x\n", cparams);
244
245 if (EHCI_HCC_64BIT(cparams)) {
246 DPRINTF("HCC uses 64-bit structures\n");
247
248 /* MUST clear segment register if 64 bit capable */
249 EWRITE4(sc, EHCI_CTRLDSSEGMENT, 0);
250 }
251 sc->sc_bus.usbrev = USB_REV_2_0;
252
253 /* Reset the controller */
254 DPRINTF("%s: resetting\n", device_get_nameunit(sc->sc_bus.bdev));
255
256 err = ehci_hcreset(sc);
257 if (err) {
258 device_printf(sc->sc_bus.bdev, "reset timeout\n");
259 return (err);
260 }
261 /*
262 * use current frame-list-size selection 0: 1024*4 bytes 1: 512*4
263 * bytes 2: 256*4 bytes 3: unknown
264 */
265 if (EHCI_CMD_FLS(EOREAD4(sc, EHCI_USBCMD)) == 3) {
266 device_printf(sc->sc_bus.bdev, "invalid frame-list-size\n");
267 return (USB_ERR_IOERROR);
268 }
269 /* set up the bus struct */
270 sc->sc_bus.methods = &ehci_bus_methods;
271
272 sc->sc_eintrs = EHCI_NORMAL_INTRS;
273
274 for (i = 0; i < EHCI_VIRTUAL_FRAMELIST_COUNT; i++) {
275 ehci_qh_t *qh;
276
225
226#if USB_DEBUG
227 if (ehcidebug > 2) {
228 ehci_dump_regs(sc);
229 }
230#endif
231
232 sc->sc_offs = EREAD1(sc, EHCI_CAPLENGTH);
233
234 version = EREAD2(sc, EHCI_HCIVERSION);
235 device_printf(sc->sc_bus.bdev, "EHCI version %x.%x\n",
236 version >> 8, version & 0xff);
237
238 sparams = EREAD4(sc, EHCI_HCSPARAMS);
239 DPRINTF("sparams=0x%x\n", sparams);
240
241 sc->sc_noport = EHCI_HCS_N_PORTS(sparams);
242 cparams = EREAD4(sc, EHCI_HCCPARAMS);
243 DPRINTF("cparams=0x%x\n", cparams);
244
245 if (EHCI_HCC_64BIT(cparams)) {
246 DPRINTF("HCC uses 64-bit structures\n");
247
248 /* MUST clear segment register if 64 bit capable */
249 EWRITE4(sc, EHCI_CTRLDSSEGMENT, 0);
250 }
251 sc->sc_bus.usbrev = USB_REV_2_0;
252
253 /* Reset the controller */
254 DPRINTF("%s: resetting\n", device_get_nameunit(sc->sc_bus.bdev));
255
256 err = ehci_hcreset(sc);
257 if (err) {
258 device_printf(sc->sc_bus.bdev, "reset timeout\n");
259 return (err);
260 }
261 /*
262 * use current frame-list-size selection 0: 1024*4 bytes 1: 512*4
263 * bytes 2: 256*4 bytes 3: unknown
264 */
265 if (EHCI_CMD_FLS(EOREAD4(sc, EHCI_USBCMD)) == 3) {
266 device_printf(sc->sc_bus.bdev, "invalid frame-list-size\n");
267 return (USB_ERR_IOERROR);
268 }
269 /* set up the bus struct */
270 sc->sc_bus.methods = &ehci_bus_methods;
271
272 sc->sc_eintrs = EHCI_NORMAL_INTRS;
273
274 for (i = 0; i < EHCI_VIRTUAL_FRAMELIST_COUNT; i++) {
275 ehci_qh_t *qh;
276
277 usb2_get_page(sc->sc_hw.intr_start_pc + i, 0, &buf_res);
277 usbd_get_page(sc->sc_hw.intr_start_pc + i, 0, &buf_res);
278
279 qh = buf_res.buffer;
280
281 /* initialize page cache pointer */
282
283 qh->page_cache = sc->sc_hw.intr_start_pc + i;
284
285 /* store a pointer to queue head */
286
287 sc->sc_intr_p_last[i] = qh;
288
289 qh->qh_self =
290 htohc32(sc, buf_res.physaddr) |
291 htohc32(sc, EHCI_LINK_QH);
292
293 qh->qh_endp =
294 htohc32(sc, EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH));
295 qh->qh_endphub =
296 htohc32(sc, EHCI_QH_SET_MULT(1));
297 qh->qh_curqtd = 0;
298
299 qh->qh_qtd.qtd_next =
300 htohc32(sc, EHCI_LINK_TERMINATE);
301 qh->qh_qtd.qtd_altnext =
302 htohc32(sc, EHCI_LINK_TERMINATE);
303 qh->qh_qtd.qtd_status =
304 htohc32(sc, EHCI_QTD_HALTED);
305 }
306
307 /*
308 * the QHs are arranged to give poll intervals that are
309 * powers of 2 times 1ms
310 */
311 bit = EHCI_VIRTUAL_FRAMELIST_COUNT / 2;
312 while (bit) {
313 x = bit;
314 while (x & bit) {
315 ehci_qh_t *qh_x;
316 ehci_qh_t *qh_y;
317
318 y = (x ^ bit) | (bit / 2);
319
320 qh_x = sc->sc_intr_p_last[x];
321 qh_y = sc->sc_intr_p_last[y];
322
323 /*
324 * the next QH has half the poll interval
325 */
326 qh_x->qh_link = qh_y->qh_self;
327
328 x++;
329 }
330 bit >>= 1;
331 }
332
333 if (1) {
334 ehci_qh_t *qh;
335
336 qh = sc->sc_intr_p_last[0];
337
338 /* the last (1ms) QH terminates */
339 qh->qh_link = htohc32(sc, EHCI_LINK_TERMINATE);
340 }
341 for (i = 0; i < EHCI_VIRTUAL_FRAMELIST_COUNT; i++) {
342 ehci_sitd_t *sitd;
343 ehci_itd_t *itd;
344
278
279 qh = buf_res.buffer;
280
281 /* initialize page cache pointer */
282
283 qh->page_cache = sc->sc_hw.intr_start_pc + i;
284
285 /* store a pointer to queue head */
286
287 sc->sc_intr_p_last[i] = qh;
288
289 qh->qh_self =
290 htohc32(sc, buf_res.physaddr) |
291 htohc32(sc, EHCI_LINK_QH);
292
293 qh->qh_endp =
294 htohc32(sc, EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH));
295 qh->qh_endphub =
296 htohc32(sc, EHCI_QH_SET_MULT(1));
297 qh->qh_curqtd = 0;
298
299 qh->qh_qtd.qtd_next =
300 htohc32(sc, EHCI_LINK_TERMINATE);
301 qh->qh_qtd.qtd_altnext =
302 htohc32(sc, EHCI_LINK_TERMINATE);
303 qh->qh_qtd.qtd_status =
304 htohc32(sc, EHCI_QTD_HALTED);
305 }
306
307 /*
308 * the QHs are arranged to give poll intervals that are
309 * powers of 2 times 1ms
310 */
311 bit = EHCI_VIRTUAL_FRAMELIST_COUNT / 2;
312 while (bit) {
313 x = bit;
314 while (x & bit) {
315 ehci_qh_t *qh_x;
316 ehci_qh_t *qh_y;
317
318 y = (x ^ bit) | (bit / 2);
319
320 qh_x = sc->sc_intr_p_last[x];
321 qh_y = sc->sc_intr_p_last[y];
322
323 /*
324 * the next QH has half the poll interval
325 */
326 qh_x->qh_link = qh_y->qh_self;
327
328 x++;
329 }
330 bit >>= 1;
331 }
332
333 if (1) {
334 ehci_qh_t *qh;
335
336 qh = sc->sc_intr_p_last[0];
337
338 /* the last (1ms) QH terminates */
339 qh->qh_link = htohc32(sc, EHCI_LINK_TERMINATE);
340 }
341 for (i = 0; i < EHCI_VIRTUAL_FRAMELIST_COUNT; i++) {
342 ehci_sitd_t *sitd;
343 ehci_itd_t *itd;
344
345 usb2_get_page(sc->sc_hw.isoc_fs_start_pc + i, 0, &buf_res);
345 usbd_get_page(sc->sc_hw.isoc_fs_start_pc + i, 0, &buf_res);
346
347 sitd = buf_res.buffer;
348
349 /* initialize page cache pointer */
350
351 sitd->page_cache = sc->sc_hw.isoc_fs_start_pc + i;
352
353 /* store a pointer to the transfer descriptor */
354
355 sc->sc_isoc_fs_p_last[i] = sitd;
356
357 /* initialize full speed isochronous */
358
359 sitd->sitd_self =
360 htohc32(sc, buf_res.physaddr) |
361 htohc32(sc, EHCI_LINK_SITD);
362
363 sitd->sitd_back =
364 htohc32(sc, EHCI_LINK_TERMINATE);
365
366 sitd->sitd_next =
367 sc->sc_intr_p_last[i | (EHCI_VIRTUAL_FRAMELIST_COUNT / 2)]->qh_self;
368
369
346
347 sitd = buf_res.buffer;
348
349 /* initialize page cache pointer */
350
351 sitd->page_cache = sc->sc_hw.isoc_fs_start_pc + i;
352
353 /* store a pointer to the transfer descriptor */
354
355 sc->sc_isoc_fs_p_last[i] = sitd;
356
357 /* initialize full speed isochronous */
358
359 sitd->sitd_self =
360 htohc32(sc, buf_res.physaddr) |
361 htohc32(sc, EHCI_LINK_SITD);
362
363 sitd->sitd_back =
364 htohc32(sc, EHCI_LINK_TERMINATE);
365
366 sitd->sitd_next =
367 sc->sc_intr_p_last[i | (EHCI_VIRTUAL_FRAMELIST_COUNT / 2)]->qh_self;
368
369
370 usb2_get_page(sc->sc_hw.isoc_hs_start_pc + i, 0, &buf_res);
370 usbd_get_page(sc->sc_hw.isoc_hs_start_pc + i, 0, &buf_res);
371
372 itd = buf_res.buffer;
373
374 /* initialize page cache pointer */
375
376 itd->page_cache = sc->sc_hw.isoc_hs_start_pc + i;
377
378 /* store a pointer to the transfer descriptor */
379
380 sc->sc_isoc_hs_p_last[i] = itd;
381
382 /* initialize high speed isochronous */
383
384 itd->itd_self =
385 htohc32(sc, buf_res.physaddr) |
386 htohc32(sc, EHCI_LINK_ITD);
387
388 itd->itd_next =
389 sitd->sitd_self;
390 }
391
371
372 itd = buf_res.buffer;
373
374 /* initialize page cache pointer */
375
376 itd->page_cache = sc->sc_hw.isoc_hs_start_pc + i;
377
378 /* store a pointer to the transfer descriptor */
379
380 sc->sc_isoc_hs_p_last[i] = itd;
381
382 /* initialize high speed isochronous */
383
384 itd->itd_self =
385 htohc32(sc, buf_res.physaddr) |
386 htohc32(sc, EHCI_LINK_ITD);
387
388 itd->itd_next =
389 sitd->sitd_self;
390 }
391
392 usb2_get_page(&sc->sc_hw.pframes_pc, 0, &buf_res);
392 usbd_get_page(&sc->sc_hw.pframes_pc, 0, &buf_res);
393
394 if (1) {
395 uint32_t *pframes;
396
397 pframes = buf_res.buffer;
398
399 /*
400 * execution order:
401 * pframes -> high speed isochronous ->
402 * full speed isochronous -> interrupt QH's
403 */
404 for (i = 0; i < EHCI_FRAMELIST_COUNT; i++) {
405 pframes[i] = sc->sc_isoc_hs_p_last
406 [i & (EHCI_VIRTUAL_FRAMELIST_COUNT - 1)]->itd_self;
407 }
408 }
409 /* setup sync list pointer */
410 EOWRITE4(sc, EHCI_PERIODICLISTBASE, buf_res.physaddr);
411
393
394 if (1) {
395 uint32_t *pframes;
396
397 pframes = buf_res.buffer;
398
399 /*
400 * execution order:
401 * pframes -> high speed isochronous ->
402 * full speed isochronous -> interrupt QH's
403 */
404 for (i = 0; i < EHCI_FRAMELIST_COUNT; i++) {
405 pframes[i] = sc->sc_isoc_hs_p_last
406 [i & (EHCI_VIRTUAL_FRAMELIST_COUNT - 1)]->itd_self;
407 }
408 }
409 /* setup sync list pointer */
410 EOWRITE4(sc, EHCI_PERIODICLISTBASE, buf_res.physaddr);
411
412 usb2_get_page(&sc->sc_hw.async_start_pc, 0, &buf_res);
412 usbd_get_page(&sc->sc_hw.async_start_pc, 0, &buf_res);
413
414 if (1) {
415
416 ehci_qh_t *qh;
417
418 qh = buf_res.buffer;
419
420 /* initialize page cache pointer */
421
422 qh->page_cache = &sc->sc_hw.async_start_pc;
423
424 /* store a pointer to the queue head */
425
426 sc->sc_async_p_last = qh;
427
428 /* init dummy QH that starts the async list */
429
430 qh->qh_self =
431 htohc32(sc, buf_res.physaddr) |
432 htohc32(sc, EHCI_LINK_QH);
433
434 /* fill the QH */
435 qh->qh_endp =
436 htohc32(sc, EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH) | EHCI_QH_HRECL);
437 qh->qh_endphub = htohc32(sc, EHCI_QH_SET_MULT(1));
438 qh->qh_link = qh->qh_self;
439 qh->qh_curqtd = 0;
440
441 /* fill the overlay qTD */
442 qh->qh_qtd.qtd_next = htohc32(sc, EHCI_LINK_TERMINATE);
443 qh->qh_qtd.qtd_altnext = htohc32(sc, EHCI_LINK_TERMINATE);
444 qh->qh_qtd.qtd_status = htohc32(sc, EHCI_QTD_HALTED);
445 }
446 /* flush all cache into memory */
447
413
414 if (1) {
415
416 ehci_qh_t *qh;
417
418 qh = buf_res.buffer;
419
420 /* initialize page cache pointer */
421
422 qh->page_cache = &sc->sc_hw.async_start_pc;
423
424 /* store a pointer to the queue head */
425
426 sc->sc_async_p_last = qh;
427
428 /* init dummy QH that starts the async list */
429
430 qh->qh_self =
431 htohc32(sc, buf_res.physaddr) |
432 htohc32(sc, EHCI_LINK_QH);
433
434 /* fill the QH */
435 qh->qh_endp =
436 htohc32(sc, EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH) | EHCI_QH_HRECL);
437 qh->qh_endphub = htohc32(sc, EHCI_QH_SET_MULT(1));
438 qh->qh_link = qh->qh_self;
439 qh->qh_curqtd = 0;
440
441 /* fill the overlay qTD */
442 qh->qh_qtd.qtd_next = htohc32(sc, EHCI_LINK_TERMINATE);
443 qh->qh_qtd.qtd_altnext = htohc32(sc, EHCI_LINK_TERMINATE);
444 qh->qh_qtd.qtd_status = htohc32(sc, EHCI_QTD_HALTED);
445 }
446 /* flush all cache into memory */
447
448 usb2_bus_mem_flush_all(&sc->sc_bus, &ehci_iterate_hw_softc);
448 usb_bus_mem_flush_all(&sc->sc_bus, &ehci_iterate_hw_softc);
449
450#if USB_DEBUG
451 if (ehcidebug) {
452 ehci_dump_sqh(sc, sc->sc_async_p_last);
453 }
454#endif
455
456 /* setup async list pointer */
457 EOWRITE4(sc, EHCI_ASYNCLISTADDR, buf_res.physaddr | EHCI_LINK_QH);
458
459
460 /* enable interrupts */
461 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs);
462
463 /* turn on controller */
464 EOWRITE4(sc, EHCI_USBCMD,
465 EHCI_CMD_ITC_1 | /* 1 microframes interrupt delay */
466 (EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_FLS_M) |
467 EHCI_CMD_ASE |
468 EHCI_CMD_PSE |
469 EHCI_CMD_RS);
470
471 /* Take over port ownership */
472 EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF);
473
474 for (i = 0; i < 100; i++) {
449
450#if USB_DEBUG
451 if (ehcidebug) {
452 ehci_dump_sqh(sc, sc->sc_async_p_last);
453 }
454#endif
455
456 /* setup async list pointer */
457 EOWRITE4(sc, EHCI_ASYNCLISTADDR, buf_res.physaddr | EHCI_LINK_QH);
458
459
460 /* enable interrupts */
461 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs);
462
463 /* turn on controller */
464 EOWRITE4(sc, EHCI_USBCMD,
465 EHCI_CMD_ITC_1 | /* 1 microframes interrupt delay */
466 (EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_FLS_M) |
467 EHCI_CMD_ASE |
468 EHCI_CMD_PSE |
469 EHCI_CMD_RS);
470
471 /* Take over port ownership */
472 EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF);
473
474 for (i = 0; i < 100; i++) {
475 usb2_pause_mtx(NULL, hz / 1000);
475 usb_pause_mtx(NULL, hz / 1000);
476 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH;
477 if (!hcr) {
478 break;
479 }
480 }
481 if (hcr) {
482 device_printf(sc->sc_bus.bdev, "run timeout\n");
483 return (USB_ERR_IOERROR);
484 }
485
486 if (!err) {
487 /* catch any lost interrupts */
488 ehci_do_poll(&sc->sc_bus);
489 }
490 return (err);
491}
492
493/*
494 * shut down the controller when the system is going down
495 */
496void
497ehci_detach(ehci_softc_t *sc)
498{
499 USB_BUS_LOCK(&sc->sc_bus);
500
476 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH;
477 if (!hcr) {
478 break;
479 }
480 }
481 if (hcr) {
482 device_printf(sc->sc_bus.bdev, "run timeout\n");
483 return (USB_ERR_IOERROR);
484 }
485
486 if (!err) {
487 /* catch any lost interrupts */
488 ehci_do_poll(&sc->sc_bus);
489 }
490 return (err);
491}
492
493/*
494 * shut down the controller when the system is going down
495 */
496void
497ehci_detach(ehci_softc_t *sc)
498{
499 USB_BUS_LOCK(&sc->sc_bus);
500
501 usb2_callout_stop(&sc->sc_tmo_pcd);
501 usb_callout_stop(&sc->sc_tmo_pcd);
502
503 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs);
504 USB_BUS_UNLOCK(&sc->sc_bus);
505
506 if (ehci_hcreset(sc)) {
507 DPRINTF("reset failed!\n");
508 }
509
510 /* XXX let stray task complete */
502
503 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs);
504 USB_BUS_UNLOCK(&sc->sc_bus);
505
506 if (ehci_hcreset(sc)) {
507 DPRINTF("reset failed!\n");
508 }
509
510 /* XXX let stray task complete */
511 usb2_pause_mtx(NULL, hz / 20);
511 usb_pause_mtx(NULL, hz / 20);
512
512
513 usb2_callout_drain(&sc->sc_tmo_pcd);
513 usb_callout_drain(&sc->sc_tmo_pcd);
514}
515
516void
517ehci_suspend(ehci_softc_t *sc)
518{
519 uint32_t cmd;
520 uint32_t hcr;
521 uint8_t i;
522
523 USB_BUS_LOCK(&sc->sc_bus);
524
525 for (i = 1; i <= sc->sc_noport; i++) {
526 cmd = EOREAD4(sc, EHCI_PORTSC(i));
527 if (((cmd & EHCI_PS_PO) == 0) &&
528 ((cmd & EHCI_PS_PE) == EHCI_PS_PE)) {
529 EOWRITE4(sc, EHCI_PORTSC(i),
530 cmd | EHCI_PS_SUSP);
531 }
532 }
533
534 sc->sc_cmd = EOREAD4(sc, EHCI_USBCMD);
535
536 cmd = sc->sc_cmd & ~(EHCI_CMD_ASE | EHCI_CMD_PSE);
537 EOWRITE4(sc, EHCI_USBCMD, cmd);
538
539 for (i = 0; i < 100; i++) {
540 hcr = EOREAD4(sc, EHCI_USBSTS) &
541 (EHCI_STS_ASS | EHCI_STS_PSS);
542
543 if (hcr == 0) {
544 break;
545 }
514}
515
516void
517ehci_suspend(ehci_softc_t *sc)
518{
519 uint32_t cmd;
520 uint32_t hcr;
521 uint8_t i;
522
523 USB_BUS_LOCK(&sc->sc_bus);
524
525 for (i = 1; i <= sc->sc_noport; i++) {
526 cmd = EOREAD4(sc, EHCI_PORTSC(i));
527 if (((cmd & EHCI_PS_PO) == 0) &&
528 ((cmd & EHCI_PS_PE) == EHCI_PS_PE)) {
529 EOWRITE4(sc, EHCI_PORTSC(i),
530 cmd | EHCI_PS_SUSP);
531 }
532 }
533
534 sc->sc_cmd = EOREAD4(sc, EHCI_USBCMD);
535
536 cmd = sc->sc_cmd & ~(EHCI_CMD_ASE | EHCI_CMD_PSE);
537 EOWRITE4(sc, EHCI_USBCMD, cmd);
538
539 for (i = 0; i < 100; i++) {
540 hcr = EOREAD4(sc, EHCI_USBSTS) &
541 (EHCI_STS_ASS | EHCI_STS_PSS);
542
543 if (hcr == 0) {
544 break;
545 }
546 usb2_pause_mtx(&sc->sc_bus.bus_mtx, hz / 1000);
546 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 1000);
547 }
548
549 if (hcr != 0) {
550 device_printf(sc->sc_bus.bdev, "reset timeout\n");
551 }
552 cmd &= ~EHCI_CMD_RS;
553 EOWRITE4(sc, EHCI_USBCMD, cmd);
554
555 for (i = 0; i < 100; i++) {
556 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH;
557 if (hcr == EHCI_STS_HCH) {
558 break;
559 }
547 }
548
549 if (hcr != 0) {
550 device_printf(sc->sc_bus.bdev, "reset timeout\n");
551 }
552 cmd &= ~EHCI_CMD_RS;
553 EOWRITE4(sc, EHCI_USBCMD, cmd);
554
555 for (i = 0; i < 100; i++) {
556 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH;
557 if (hcr == EHCI_STS_HCH) {
558 break;
559 }
560 usb2_pause_mtx(&sc->sc_bus.bus_mtx, hz / 1000);
560 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 1000);
561 }
562
563 if (hcr != EHCI_STS_HCH) {
564 device_printf(sc->sc_bus.bdev,
565 "config timeout\n");
566 }
567 USB_BUS_UNLOCK(&sc->sc_bus);
568}
569
570void
571ehci_resume(ehci_softc_t *sc)
572{
573 struct usb_page_search buf_res;
574 uint32_t cmd;
575 uint32_t hcr;
576 uint8_t i;
577
578 USB_BUS_LOCK(&sc->sc_bus);
579
580 /* restore things in case the bios doesn't */
581 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0);
582
561 }
562
563 if (hcr != EHCI_STS_HCH) {
564 device_printf(sc->sc_bus.bdev,
565 "config timeout\n");
566 }
567 USB_BUS_UNLOCK(&sc->sc_bus);
568}
569
570void
571ehci_resume(ehci_softc_t *sc)
572{
573 struct usb_page_search buf_res;
574 uint32_t cmd;
575 uint32_t hcr;
576 uint8_t i;
577
578 USB_BUS_LOCK(&sc->sc_bus);
579
580 /* restore things in case the bios doesn't */
581 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0);
582
583 usb2_get_page(&sc->sc_hw.pframes_pc, 0, &buf_res);
583 usbd_get_page(&sc->sc_hw.pframes_pc, 0, &buf_res);
584 EOWRITE4(sc, EHCI_PERIODICLISTBASE, buf_res.physaddr);
585
584 EOWRITE4(sc, EHCI_PERIODICLISTBASE, buf_res.physaddr);
585
586 usb2_get_page(&sc->sc_hw.async_start_pc, 0, &buf_res);
586 usbd_get_page(&sc->sc_hw.async_start_pc, 0, &buf_res);
587 EOWRITE4(sc, EHCI_ASYNCLISTADDR, buf_res.physaddr | EHCI_LINK_QH);
588
589 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs);
590
591 hcr = 0;
592 for (i = 1; i <= sc->sc_noport; i++) {
593 cmd = EOREAD4(sc, EHCI_PORTSC(i));
594 if (((cmd & EHCI_PS_PO) == 0) &&
595 ((cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP)) {
596 EOWRITE4(sc, EHCI_PORTSC(i),
597 cmd | EHCI_PS_FPR);
598 hcr = 1;
599 }
600 }
601
602 if (hcr) {
587 EOWRITE4(sc, EHCI_ASYNCLISTADDR, buf_res.physaddr | EHCI_LINK_QH);
588
589 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs);
590
591 hcr = 0;
592 for (i = 1; i <= sc->sc_noport; i++) {
593 cmd = EOREAD4(sc, EHCI_PORTSC(i));
594 if (((cmd & EHCI_PS_PO) == 0) &&
595 ((cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP)) {
596 EOWRITE4(sc, EHCI_PORTSC(i),
597 cmd | EHCI_PS_FPR);
598 hcr = 1;
599 }
600 }
601
602 if (hcr) {
603 usb2_pause_mtx(&sc->sc_bus.bus_mtx,
603 usb_pause_mtx(&sc->sc_bus.bus_mtx,
604 USB_MS_TO_TICKS(USB_RESUME_WAIT));
605
606 for (i = 1; i <= sc->sc_noport; i++) {
607 cmd = EOREAD4(sc, EHCI_PORTSC(i));
608 if (((cmd & EHCI_PS_PO) == 0) &&
609 ((cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP)) {
610 EOWRITE4(sc, EHCI_PORTSC(i),
611 cmd & ~EHCI_PS_FPR);
612 }
613 }
614 }
615 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd);
616
617 for (i = 0; i < 100; i++) {
618 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH;
619 if (hcr != EHCI_STS_HCH) {
620 break;
621 }
604 USB_MS_TO_TICKS(USB_RESUME_WAIT));
605
606 for (i = 1; i <= sc->sc_noport; i++) {
607 cmd = EOREAD4(sc, EHCI_PORTSC(i));
608 if (((cmd & EHCI_PS_PO) == 0) &&
609 ((cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP)) {
610 EOWRITE4(sc, EHCI_PORTSC(i),
611 cmd & ~EHCI_PS_FPR);
612 }
613 }
614 }
615 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd);
616
617 for (i = 0; i < 100; i++) {
618 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH;
619 if (hcr != EHCI_STS_HCH) {
620 break;
621 }
622 usb2_pause_mtx(&sc->sc_bus.bus_mtx, hz / 1000);
622 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 1000);
623 }
624 if (hcr == EHCI_STS_HCH) {
625 device_printf(sc->sc_bus.bdev, "config timeout\n");
626 }
627
628 USB_BUS_UNLOCK(&sc->sc_bus);
629
623 }
624 if (hcr == EHCI_STS_HCH) {
625 device_printf(sc->sc_bus.bdev, "config timeout\n");
626 }
627
628 USB_BUS_UNLOCK(&sc->sc_bus);
629
630 usb2_pause_mtx(NULL,
630 usb_pause_mtx(NULL,
631 USB_MS_TO_TICKS(USB_RESUME_WAIT));
632
633 /* catch any lost interrupts */
634 ehci_do_poll(&sc->sc_bus);
635}
636
637void
638ehci_shutdown(ehci_softc_t *sc)
639{
640 DPRINTF("stopping the HC\n");
641
642 if (ehci_hcreset(sc)) {
643 DPRINTF("reset failed!\n");
644 }
645}
646
647#if USB_DEBUG
648static void
649ehci_dump_regs(ehci_softc_t *sc)
650{
651 uint32_t i;
652
653 i = EOREAD4(sc, EHCI_USBCMD);
654 printf("cmd=0x%08x\n", i);
655
656 if (i & EHCI_CMD_ITC_1)
657 printf(" EHCI_CMD_ITC_1\n");
658 if (i & EHCI_CMD_ITC_2)
659 printf(" EHCI_CMD_ITC_2\n");
660 if (i & EHCI_CMD_ITC_4)
661 printf(" EHCI_CMD_ITC_4\n");
662 if (i & EHCI_CMD_ITC_8)
663 printf(" EHCI_CMD_ITC_8\n");
664 if (i & EHCI_CMD_ITC_16)
665 printf(" EHCI_CMD_ITC_16\n");
666 if (i & EHCI_CMD_ITC_32)
667 printf(" EHCI_CMD_ITC_32\n");
668 if (i & EHCI_CMD_ITC_64)
669 printf(" EHCI_CMD_ITC_64\n");
670 if (i & EHCI_CMD_ASPME)
671 printf(" EHCI_CMD_ASPME\n");
672 if (i & EHCI_CMD_ASPMC)
673 printf(" EHCI_CMD_ASPMC\n");
674 if (i & EHCI_CMD_LHCR)
675 printf(" EHCI_CMD_LHCR\n");
676 if (i & EHCI_CMD_IAAD)
677 printf(" EHCI_CMD_IAAD\n");
678 if (i & EHCI_CMD_ASE)
679 printf(" EHCI_CMD_ASE\n");
680 if (i & EHCI_CMD_PSE)
681 printf(" EHCI_CMD_PSE\n");
682 if (i & EHCI_CMD_FLS_M)
683 printf(" EHCI_CMD_FLS_M\n");
684 if (i & EHCI_CMD_HCRESET)
685 printf(" EHCI_CMD_HCRESET\n");
686 if (i & EHCI_CMD_RS)
687 printf(" EHCI_CMD_RS\n");
688
689 i = EOREAD4(sc, EHCI_USBSTS);
690
691 printf("sts=0x%08x\n", i);
692
693 if (i & EHCI_STS_ASS)
694 printf(" EHCI_STS_ASS\n");
695 if (i & EHCI_STS_PSS)
696 printf(" EHCI_STS_PSS\n");
697 if (i & EHCI_STS_REC)
698 printf(" EHCI_STS_REC\n");
699 if (i & EHCI_STS_HCH)
700 printf(" EHCI_STS_HCH\n");
701 if (i & EHCI_STS_IAA)
702 printf(" EHCI_STS_IAA\n");
703 if (i & EHCI_STS_HSE)
704 printf(" EHCI_STS_HSE\n");
705 if (i & EHCI_STS_FLR)
706 printf(" EHCI_STS_FLR\n");
707 if (i & EHCI_STS_PCD)
708 printf(" EHCI_STS_PCD\n");
709 if (i & EHCI_STS_ERRINT)
710 printf(" EHCI_STS_ERRINT\n");
711 if (i & EHCI_STS_INT)
712 printf(" EHCI_STS_INT\n");
713
714 printf("ien=0x%08x\n",
715 EOREAD4(sc, EHCI_USBINTR));
716 printf("frindex=0x%08x ctrdsegm=0x%08x periodic=0x%08x async=0x%08x\n",
717 EOREAD4(sc, EHCI_FRINDEX),
718 EOREAD4(sc, EHCI_CTRLDSSEGMENT),
719 EOREAD4(sc, EHCI_PERIODICLISTBASE),
720 EOREAD4(sc, EHCI_ASYNCLISTADDR));
721 for (i = 1; i <= sc->sc_noport; i++) {
722 printf("port %d status=0x%08x\n", i,
723 EOREAD4(sc, EHCI_PORTSC(i)));
724 }
725}
726
727static void
728ehci_dump_link(ehci_softc_t *sc, uint32_t link, int type)
729{
730 link = hc32toh(sc, link);
731 printf("0x%08x", link);
732 if (link & EHCI_LINK_TERMINATE)
733 printf("<T>");
734 else {
735 printf("<");
736 if (type) {
737 switch (EHCI_LINK_TYPE(link)) {
738 case EHCI_LINK_ITD:
739 printf("ITD");
740 break;
741 case EHCI_LINK_QH:
742 printf("QH");
743 break;
744 case EHCI_LINK_SITD:
745 printf("SITD");
746 break;
747 case EHCI_LINK_FSTN:
748 printf("FSTN");
749 break;
750 }
751 }
752 printf(">");
753 }
754}
755
756static void
757ehci_dump_qtd(ehci_softc_t *sc, ehci_qtd_t *qtd)
758{
759 uint32_t s;
760
761 printf(" next=");
762 ehci_dump_link(sc, qtd->qtd_next, 0);
763 printf(" altnext=");
764 ehci_dump_link(sc, qtd->qtd_altnext, 0);
765 printf("\n");
766 s = hc32toh(sc, qtd->qtd_status);
767 printf(" status=0x%08x: toggle=%d bytes=0x%x ioc=%d c_page=0x%x\n",
768 s, EHCI_QTD_GET_TOGGLE(s), EHCI_QTD_GET_BYTES(s),
769 EHCI_QTD_GET_IOC(s), EHCI_QTD_GET_C_PAGE(s));
770 printf(" cerr=%d pid=%d stat=%s%s%s%s%s%s%s%s\n",
771 EHCI_QTD_GET_CERR(s), EHCI_QTD_GET_PID(s),
772 (s & EHCI_QTD_ACTIVE) ? "ACTIVE" : "NOT_ACTIVE",
773 (s & EHCI_QTD_HALTED) ? "-HALTED" : "",
774 (s & EHCI_QTD_BUFERR) ? "-BUFERR" : "",
775 (s & EHCI_QTD_BABBLE) ? "-BABBLE" : "",
776 (s & EHCI_QTD_XACTERR) ? "-XACTERR" : "",
777 (s & EHCI_QTD_MISSEDMICRO) ? "-MISSED" : "",
778 (s & EHCI_QTD_SPLITXSTATE) ? "-SPLIT" : "",
779 (s & EHCI_QTD_PINGSTATE) ? "-PING" : "");
780
781 for (s = 0; s < 5; s++) {
782 printf(" buffer[%d]=0x%08x\n", s,
783 hc32toh(sc, qtd->qtd_buffer[s]));
784 }
785 for (s = 0; s < 5; s++) {
786 printf(" buffer_hi[%d]=0x%08x\n", s,
787 hc32toh(sc, qtd->qtd_buffer_hi[s]));
788 }
789}
790
791static uint8_t
792ehci_dump_sqtd(ehci_softc_t *sc, ehci_qtd_t *sqtd)
793{
794 uint8_t temp;
795
631 USB_MS_TO_TICKS(USB_RESUME_WAIT));
632
633 /* catch any lost interrupts */
634 ehci_do_poll(&sc->sc_bus);
635}
636
637void
638ehci_shutdown(ehci_softc_t *sc)
639{
640 DPRINTF("stopping the HC\n");
641
642 if (ehci_hcreset(sc)) {
643 DPRINTF("reset failed!\n");
644 }
645}
646
647#if USB_DEBUG
648static void
649ehci_dump_regs(ehci_softc_t *sc)
650{
651 uint32_t i;
652
653 i = EOREAD4(sc, EHCI_USBCMD);
654 printf("cmd=0x%08x\n", i);
655
656 if (i & EHCI_CMD_ITC_1)
657 printf(" EHCI_CMD_ITC_1\n");
658 if (i & EHCI_CMD_ITC_2)
659 printf(" EHCI_CMD_ITC_2\n");
660 if (i & EHCI_CMD_ITC_4)
661 printf(" EHCI_CMD_ITC_4\n");
662 if (i & EHCI_CMD_ITC_8)
663 printf(" EHCI_CMD_ITC_8\n");
664 if (i & EHCI_CMD_ITC_16)
665 printf(" EHCI_CMD_ITC_16\n");
666 if (i & EHCI_CMD_ITC_32)
667 printf(" EHCI_CMD_ITC_32\n");
668 if (i & EHCI_CMD_ITC_64)
669 printf(" EHCI_CMD_ITC_64\n");
670 if (i & EHCI_CMD_ASPME)
671 printf(" EHCI_CMD_ASPME\n");
672 if (i & EHCI_CMD_ASPMC)
673 printf(" EHCI_CMD_ASPMC\n");
674 if (i & EHCI_CMD_LHCR)
675 printf(" EHCI_CMD_LHCR\n");
676 if (i & EHCI_CMD_IAAD)
677 printf(" EHCI_CMD_IAAD\n");
678 if (i & EHCI_CMD_ASE)
679 printf(" EHCI_CMD_ASE\n");
680 if (i & EHCI_CMD_PSE)
681 printf(" EHCI_CMD_PSE\n");
682 if (i & EHCI_CMD_FLS_M)
683 printf(" EHCI_CMD_FLS_M\n");
684 if (i & EHCI_CMD_HCRESET)
685 printf(" EHCI_CMD_HCRESET\n");
686 if (i & EHCI_CMD_RS)
687 printf(" EHCI_CMD_RS\n");
688
689 i = EOREAD4(sc, EHCI_USBSTS);
690
691 printf("sts=0x%08x\n", i);
692
693 if (i & EHCI_STS_ASS)
694 printf(" EHCI_STS_ASS\n");
695 if (i & EHCI_STS_PSS)
696 printf(" EHCI_STS_PSS\n");
697 if (i & EHCI_STS_REC)
698 printf(" EHCI_STS_REC\n");
699 if (i & EHCI_STS_HCH)
700 printf(" EHCI_STS_HCH\n");
701 if (i & EHCI_STS_IAA)
702 printf(" EHCI_STS_IAA\n");
703 if (i & EHCI_STS_HSE)
704 printf(" EHCI_STS_HSE\n");
705 if (i & EHCI_STS_FLR)
706 printf(" EHCI_STS_FLR\n");
707 if (i & EHCI_STS_PCD)
708 printf(" EHCI_STS_PCD\n");
709 if (i & EHCI_STS_ERRINT)
710 printf(" EHCI_STS_ERRINT\n");
711 if (i & EHCI_STS_INT)
712 printf(" EHCI_STS_INT\n");
713
714 printf("ien=0x%08x\n",
715 EOREAD4(sc, EHCI_USBINTR));
716 printf("frindex=0x%08x ctrdsegm=0x%08x periodic=0x%08x async=0x%08x\n",
717 EOREAD4(sc, EHCI_FRINDEX),
718 EOREAD4(sc, EHCI_CTRLDSSEGMENT),
719 EOREAD4(sc, EHCI_PERIODICLISTBASE),
720 EOREAD4(sc, EHCI_ASYNCLISTADDR));
721 for (i = 1; i <= sc->sc_noport; i++) {
722 printf("port %d status=0x%08x\n", i,
723 EOREAD4(sc, EHCI_PORTSC(i)));
724 }
725}
726
727static void
728ehci_dump_link(ehci_softc_t *sc, uint32_t link, int type)
729{
730 link = hc32toh(sc, link);
731 printf("0x%08x", link);
732 if (link & EHCI_LINK_TERMINATE)
733 printf("<T>");
734 else {
735 printf("<");
736 if (type) {
737 switch (EHCI_LINK_TYPE(link)) {
738 case EHCI_LINK_ITD:
739 printf("ITD");
740 break;
741 case EHCI_LINK_QH:
742 printf("QH");
743 break;
744 case EHCI_LINK_SITD:
745 printf("SITD");
746 break;
747 case EHCI_LINK_FSTN:
748 printf("FSTN");
749 break;
750 }
751 }
752 printf(">");
753 }
754}
755
756static void
757ehci_dump_qtd(ehci_softc_t *sc, ehci_qtd_t *qtd)
758{
759 uint32_t s;
760
761 printf(" next=");
762 ehci_dump_link(sc, qtd->qtd_next, 0);
763 printf(" altnext=");
764 ehci_dump_link(sc, qtd->qtd_altnext, 0);
765 printf("\n");
766 s = hc32toh(sc, qtd->qtd_status);
767 printf(" status=0x%08x: toggle=%d bytes=0x%x ioc=%d c_page=0x%x\n",
768 s, EHCI_QTD_GET_TOGGLE(s), EHCI_QTD_GET_BYTES(s),
769 EHCI_QTD_GET_IOC(s), EHCI_QTD_GET_C_PAGE(s));
770 printf(" cerr=%d pid=%d stat=%s%s%s%s%s%s%s%s\n",
771 EHCI_QTD_GET_CERR(s), EHCI_QTD_GET_PID(s),
772 (s & EHCI_QTD_ACTIVE) ? "ACTIVE" : "NOT_ACTIVE",
773 (s & EHCI_QTD_HALTED) ? "-HALTED" : "",
774 (s & EHCI_QTD_BUFERR) ? "-BUFERR" : "",
775 (s & EHCI_QTD_BABBLE) ? "-BABBLE" : "",
776 (s & EHCI_QTD_XACTERR) ? "-XACTERR" : "",
777 (s & EHCI_QTD_MISSEDMICRO) ? "-MISSED" : "",
778 (s & EHCI_QTD_SPLITXSTATE) ? "-SPLIT" : "",
779 (s & EHCI_QTD_PINGSTATE) ? "-PING" : "");
780
781 for (s = 0; s < 5; s++) {
782 printf(" buffer[%d]=0x%08x\n", s,
783 hc32toh(sc, qtd->qtd_buffer[s]));
784 }
785 for (s = 0; s < 5; s++) {
786 printf(" buffer_hi[%d]=0x%08x\n", s,
787 hc32toh(sc, qtd->qtd_buffer_hi[s]));
788 }
789}
790
791static uint8_t
792ehci_dump_sqtd(ehci_softc_t *sc, ehci_qtd_t *sqtd)
793{
794 uint8_t temp;
795
796 usb2_pc_cpu_invalidate(sqtd->page_cache);
796 usb_pc_cpu_invalidate(sqtd->page_cache);
797 printf("QTD(%p) at 0x%08x:\n", sqtd, hc32toh(sc, sqtd->qtd_self));
798 ehci_dump_qtd(sc, sqtd);
799 temp = (sqtd->qtd_next & htohc32(sc, EHCI_LINK_TERMINATE)) ? 1 : 0;
800 return (temp);
801}
802
803static void
804ehci_dump_sqtds(ehci_softc_t *sc, ehci_qtd_t *sqtd)
805{
806 uint16_t i;
807 uint8_t stop;
808
809 stop = 0;
810 for (i = 0; sqtd && (i < 20) && !stop; sqtd = sqtd->obj_next, i++) {
811 stop = ehci_dump_sqtd(sc, sqtd);
812 }
813 if (sqtd) {
814 printf("dump aborted, too many TDs\n");
815 }
816}
817
818static void
819ehci_dump_sqh(ehci_softc_t *sc, ehci_qh_t *qh)
820{
821 uint32_t endp;
822 uint32_t endphub;
823
797 printf("QTD(%p) at 0x%08x:\n", sqtd, hc32toh(sc, sqtd->qtd_self));
798 ehci_dump_qtd(sc, sqtd);
799 temp = (sqtd->qtd_next & htohc32(sc, EHCI_LINK_TERMINATE)) ? 1 : 0;
800 return (temp);
801}
802
803static void
804ehci_dump_sqtds(ehci_softc_t *sc, ehci_qtd_t *sqtd)
805{
806 uint16_t i;
807 uint8_t stop;
808
809 stop = 0;
810 for (i = 0; sqtd && (i < 20) && !stop; sqtd = sqtd->obj_next, i++) {
811 stop = ehci_dump_sqtd(sc, sqtd);
812 }
813 if (sqtd) {
814 printf("dump aborted, too many TDs\n");
815 }
816}
817
818static void
819ehci_dump_sqh(ehci_softc_t *sc, ehci_qh_t *qh)
820{
821 uint32_t endp;
822 uint32_t endphub;
823
824 usb2_pc_cpu_invalidate(qh->page_cache);
824 usb_pc_cpu_invalidate(qh->page_cache);
825 printf("QH(%p) at 0x%08x:\n", qh, hc32toh(sc, qh->qh_self) & ~0x1F);
826 printf(" link=");
827 ehci_dump_link(sc, qh->qh_link, 1);
828 printf("\n");
829 endp = hc32toh(sc, qh->qh_endp);
830 printf(" endp=0x%08x\n", endp);
831 printf(" addr=0x%02x inact=%d endpt=%d eps=%d dtc=%d hrecl=%d\n",
832 EHCI_QH_GET_ADDR(endp), EHCI_QH_GET_INACT(endp),
833 EHCI_QH_GET_ENDPT(endp), EHCI_QH_GET_EPS(endp),
834 EHCI_QH_GET_DTC(endp), EHCI_QH_GET_HRECL(endp));
835 printf(" mpl=0x%x ctl=%d nrl=%d\n",
836 EHCI_QH_GET_MPL(endp), EHCI_QH_GET_CTL(endp),
837 EHCI_QH_GET_NRL(endp));
838 endphub = hc32toh(sc, qh->qh_endphub);
839 printf(" endphub=0x%08x\n", endphub);
840 printf(" smask=0x%02x cmask=0x%02x huba=0x%02x port=%d mult=%d\n",
841 EHCI_QH_GET_SMASK(endphub), EHCI_QH_GET_CMASK(endphub),
842 EHCI_QH_GET_HUBA(endphub), EHCI_QH_GET_PORT(endphub),
843 EHCI_QH_GET_MULT(endphub));
844 printf(" curqtd=");
845 ehci_dump_link(sc, qh->qh_curqtd, 0);
846 printf("\n");
847 printf("Overlay qTD:\n");
848 ehci_dump_qtd(sc, (void *)&qh->qh_qtd);
849}
850
851static void
852ehci_dump_sitd(ehci_softc_t *sc, ehci_sitd_t *sitd)
853{
825 printf("QH(%p) at 0x%08x:\n", qh, hc32toh(sc, qh->qh_self) & ~0x1F);
826 printf(" link=");
827 ehci_dump_link(sc, qh->qh_link, 1);
828 printf("\n");
829 endp = hc32toh(sc, qh->qh_endp);
830 printf(" endp=0x%08x\n", endp);
831 printf(" addr=0x%02x inact=%d endpt=%d eps=%d dtc=%d hrecl=%d\n",
832 EHCI_QH_GET_ADDR(endp), EHCI_QH_GET_INACT(endp),
833 EHCI_QH_GET_ENDPT(endp), EHCI_QH_GET_EPS(endp),
834 EHCI_QH_GET_DTC(endp), EHCI_QH_GET_HRECL(endp));
835 printf(" mpl=0x%x ctl=%d nrl=%d\n",
836 EHCI_QH_GET_MPL(endp), EHCI_QH_GET_CTL(endp),
837 EHCI_QH_GET_NRL(endp));
838 endphub = hc32toh(sc, qh->qh_endphub);
839 printf(" endphub=0x%08x\n", endphub);
840 printf(" smask=0x%02x cmask=0x%02x huba=0x%02x port=%d mult=%d\n",
841 EHCI_QH_GET_SMASK(endphub), EHCI_QH_GET_CMASK(endphub),
842 EHCI_QH_GET_HUBA(endphub), EHCI_QH_GET_PORT(endphub),
843 EHCI_QH_GET_MULT(endphub));
844 printf(" curqtd=");
845 ehci_dump_link(sc, qh->qh_curqtd, 0);
846 printf("\n");
847 printf("Overlay qTD:\n");
848 ehci_dump_qtd(sc, (void *)&qh->qh_qtd);
849}
850
851static void
852ehci_dump_sitd(ehci_softc_t *sc, ehci_sitd_t *sitd)
853{
854 usb2_pc_cpu_invalidate(sitd->page_cache);
854 usb_pc_cpu_invalidate(sitd->page_cache);
855 printf("SITD(%p) at 0x%08x\n", sitd, hc32toh(sc, sitd->sitd_self) & ~0x1F);
856 printf(" next=0x%08x\n", hc32toh(sc, sitd->sitd_next));
857 printf(" portaddr=0x%08x dir=%s addr=%d endpt=0x%x port=0x%x huba=0x%x\n",
858 hc32toh(sc, sitd->sitd_portaddr),
859 (sitd->sitd_portaddr & htohc32(sc, EHCI_SITD_SET_DIR_IN))
860 ? "in" : "out",
861 EHCI_SITD_GET_ADDR(hc32toh(sc, sitd->sitd_portaddr)),
862 EHCI_SITD_GET_ENDPT(hc32toh(sc, sitd->sitd_portaddr)),
863 EHCI_SITD_GET_PORT(hc32toh(sc, sitd->sitd_portaddr)),
864 EHCI_SITD_GET_HUBA(hc32toh(sc, sitd->sitd_portaddr)));
865 printf(" mask=0x%08x\n", hc32toh(sc, sitd->sitd_mask));
866 printf(" status=0x%08x <%s> len=0x%x\n", hc32toh(sc, sitd->sitd_status),
867 (sitd->sitd_status & htohc32(sc, EHCI_SITD_ACTIVE)) ? "ACTIVE" : "",
868 EHCI_SITD_GET_LEN(hc32toh(sc, sitd->sitd_status)));
869 printf(" back=0x%08x, bp=0x%08x,0x%08x,0x%08x,0x%08x\n",
870 hc32toh(sc, sitd->sitd_back),
871 hc32toh(sc, sitd->sitd_bp[0]),
872 hc32toh(sc, sitd->sitd_bp[1]),
873 hc32toh(sc, sitd->sitd_bp_hi[0]),
874 hc32toh(sc, sitd->sitd_bp_hi[1]));
875}
876
877static void
878ehci_dump_itd(ehci_softc_t *sc, ehci_itd_t *itd)
879{
855 printf("SITD(%p) at 0x%08x\n", sitd, hc32toh(sc, sitd->sitd_self) & ~0x1F);
856 printf(" next=0x%08x\n", hc32toh(sc, sitd->sitd_next));
857 printf(" portaddr=0x%08x dir=%s addr=%d endpt=0x%x port=0x%x huba=0x%x\n",
858 hc32toh(sc, sitd->sitd_portaddr),
859 (sitd->sitd_portaddr & htohc32(sc, EHCI_SITD_SET_DIR_IN))
860 ? "in" : "out",
861 EHCI_SITD_GET_ADDR(hc32toh(sc, sitd->sitd_portaddr)),
862 EHCI_SITD_GET_ENDPT(hc32toh(sc, sitd->sitd_portaddr)),
863 EHCI_SITD_GET_PORT(hc32toh(sc, sitd->sitd_portaddr)),
864 EHCI_SITD_GET_HUBA(hc32toh(sc, sitd->sitd_portaddr)));
865 printf(" mask=0x%08x\n", hc32toh(sc, sitd->sitd_mask));
866 printf(" status=0x%08x <%s> len=0x%x\n", hc32toh(sc, sitd->sitd_status),
867 (sitd->sitd_status & htohc32(sc, EHCI_SITD_ACTIVE)) ? "ACTIVE" : "",
868 EHCI_SITD_GET_LEN(hc32toh(sc, sitd->sitd_status)));
869 printf(" back=0x%08x, bp=0x%08x,0x%08x,0x%08x,0x%08x\n",
870 hc32toh(sc, sitd->sitd_back),
871 hc32toh(sc, sitd->sitd_bp[0]),
872 hc32toh(sc, sitd->sitd_bp[1]),
873 hc32toh(sc, sitd->sitd_bp_hi[0]),
874 hc32toh(sc, sitd->sitd_bp_hi[1]));
875}
876
877static void
878ehci_dump_itd(ehci_softc_t *sc, ehci_itd_t *itd)
879{
880 usb2_pc_cpu_invalidate(itd->page_cache);
880 usb_pc_cpu_invalidate(itd->page_cache);
881 printf("ITD(%p) at 0x%08x\n", itd, hc32toh(sc, itd->itd_self) & ~0x1F);
882 printf(" next=0x%08x\n", hc32toh(sc, itd->itd_next));
883 printf(" status[0]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[0]),
884 (itd->itd_status[0] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : "");
885 printf(" status[1]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[1]),
886 (itd->itd_status[1] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : "");
887 printf(" status[2]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[2]),
888 (itd->itd_status[2] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : "");
889 printf(" status[3]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[3]),
890 (itd->itd_status[3] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : "");
891 printf(" status[4]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[4]),
892 (itd->itd_status[4] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : "");
893 printf(" status[5]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[5]),
894 (itd->itd_status[5] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : "");
895 printf(" status[6]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[6]),
896 (itd->itd_status[6] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : "");
897 printf(" status[7]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[7]),
898 (itd->itd_status[7] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : "");
899 printf(" bp[0]=0x%08x\n", hc32toh(sc, itd->itd_bp[0]));
900 printf(" addr=0x%02x; endpt=0x%01x\n",
901 EHCI_ITD_GET_ADDR(hc32toh(sc, itd->itd_bp[0])),
902 EHCI_ITD_GET_ENDPT(hc32toh(sc, itd->itd_bp[0])));
903 printf(" bp[1]=0x%08x\n", hc32toh(sc, itd->itd_bp[1]));
904 printf(" dir=%s; mpl=0x%02x\n",
905 (hc32toh(sc, itd->itd_bp[1]) & EHCI_ITD_SET_DIR_IN) ? "in" : "out",
906 EHCI_ITD_GET_MPL(hc32toh(sc, itd->itd_bp[1])));
907 printf(" bp[2..6]=0x%08x,0x%08x,0x%08x,0x%08x,0x%08x\n",
908 hc32toh(sc, itd->itd_bp[2]),
909 hc32toh(sc, itd->itd_bp[3]),
910 hc32toh(sc, itd->itd_bp[4]),
911 hc32toh(sc, itd->itd_bp[5]),
912 hc32toh(sc, itd->itd_bp[6]));
913 printf(" bp_hi=0x%08x,0x%08x,0x%08x,0x%08x,\n"
914 " 0x%08x,0x%08x,0x%08x\n",
915 hc32toh(sc, itd->itd_bp_hi[0]),
916 hc32toh(sc, itd->itd_bp_hi[1]),
917 hc32toh(sc, itd->itd_bp_hi[2]),
918 hc32toh(sc, itd->itd_bp_hi[3]),
919 hc32toh(sc, itd->itd_bp_hi[4]),
920 hc32toh(sc, itd->itd_bp_hi[5]),
921 hc32toh(sc, itd->itd_bp_hi[6]));
922}
923
924static void
925ehci_dump_isoc(ehci_softc_t *sc)
926{
927 ehci_itd_t *itd;
928 ehci_sitd_t *sitd;
929 uint16_t max = 1000;
930 uint16_t pos;
931
932 pos = (EOREAD4(sc, EHCI_FRINDEX) / 8) &
933 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1);
934
935 printf("%s: isochronous dump from frame 0x%03x:\n",
936 __FUNCTION__, pos);
937
938 itd = sc->sc_isoc_hs_p_last[pos];
939 sitd = sc->sc_isoc_fs_p_last[pos];
940
941 while (itd && max && max--) {
942 ehci_dump_itd(sc, itd);
943 itd = itd->prev;
944 }
945
946 while (sitd && max && max--) {
947 ehci_dump_sitd(sc, sitd);
948 sitd = sitd->prev;
949 }
950}
951
952#endif
953
954static void
955ehci_transfer_intr_enqueue(struct usb_xfer *xfer)
956{
957 /* check for early completion */
958 if (ehci_check_transfer(xfer)) {
959 return;
960 }
961 /* put transfer on interrupt queue */
881 printf("ITD(%p) at 0x%08x\n", itd, hc32toh(sc, itd->itd_self) & ~0x1F);
882 printf(" next=0x%08x\n", hc32toh(sc, itd->itd_next));
883 printf(" status[0]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[0]),
884 (itd->itd_status[0] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : "");
885 printf(" status[1]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[1]),
886 (itd->itd_status[1] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : "");
887 printf(" status[2]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[2]),
888 (itd->itd_status[2] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : "");
889 printf(" status[3]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[3]),
890 (itd->itd_status[3] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : "");
891 printf(" status[4]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[4]),
892 (itd->itd_status[4] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : "");
893 printf(" status[5]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[5]),
894 (itd->itd_status[5] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : "");
895 printf(" status[6]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[6]),
896 (itd->itd_status[6] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : "");
897 printf(" status[7]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[7]),
898 (itd->itd_status[7] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : "");
899 printf(" bp[0]=0x%08x\n", hc32toh(sc, itd->itd_bp[0]));
900 printf(" addr=0x%02x; endpt=0x%01x\n",
901 EHCI_ITD_GET_ADDR(hc32toh(sc, itd->itd_bp[0])),
902 EHCI_ITD_GET_ENDPT(hc32toh(sc, itd->itd_bp[0])));
903 printf(" bp[1]=0x%08x\n", hc32toh(sc, itd->itd_bp[1]));
904 printf(" dir=%s; mpl=0x%02x\n",
905 (hc32toh(sc, itd->itd_bp[1]) & EHCI_ITD_SET_DIR_IN) ? "in" : "out",
906 EHCI_ITD_GET_MPL(hc32toh(sc, itd->itd_bp[1])));
907 printf(" bp[2..6]=0x%08x,0x%08x,0x%08x,0x%08x,0x%08x\n",
908 hc32toh(sc, itd->itd_bp[2]),
909 hc32toh(sc, itd->itd_bp[3]),
910 hc32toh(sc, itd->itd_bp[4]),
911 hc32toh(sc, itd->itd_bp[5]),
912 hc32toh(sc, itd->itd_bp[6]));
913 printf(" bp_hi=0x%08x,0x%08x,0x%08x,0x%08x,\n"
914 " 0x%08x,0x%08x,0x%08x\n",
915 hc32toh(sc, itd->itd_bp_hi[0]),
916 hc32toh(sc, itd->itd_bp_hi[1]),
917 hc32toh(sc, itd->itd_bp_hi[2]),
918 hc32toh(sc, itd->itd_bp_hi[3]),
919 hc32toh(sc, itd->itd_bp_hi[4]),
920 hc32toh(sc, itd->itd_bp_hi[5]),
921 hc32toh(sc, itd->itd_bp_hi[6]));
922}
923
924static void
925ehci_dump_isoc(ehci_softc_t *sc)
926{
927 ehci_itd_t *itd;
928 ehci_sitd_t *sitd;
929 uint16_t max = 1000;
930 uint16_t pos;
931
932 pos = (EOREAD4(sc, EHCI_FRINDEX) / 8) &
933 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1);
934
935 printf("%s: isochronous dump from frame 0x%03x:\n",
936 __FUNCTION__, pos);
937
938 itd = sc->sc_isoc_hs_p_last[pos];
939 sitd = sc->sc_isoc_fs_p_last[pos];
940
941 while (itd && max && max--) {
942 ehci_dump_itd(sc, itd);
943 itd = itd->prev;
944 }
945
946 while (sitd && max && max--) {
947 ehci_dump_sitd(sc, sitd);
948 sitd = sitd->prev;
949 }
950}
951
952#endif
953
954static void
955ehci_transfer_intr_enqueue(struct usb_xfer *xfer)
956{
957 /* check for early completion */
958 if (ehci_check_transfer(xfer)) {
959 return;
960 }
961 /* put transfer on interrupt queue */
962 usb2_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer);
962 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer);
963
964 /* start timeout, if any */
965 if (xfer->timeout != 0) {
963
964 /* start timeout, if any */
965 if (xfer->timeout != 0) {
966 usb2_transfer_timeout_ms(xfer, &ehci_timeout, xfer->timeout);
966 usbd_transfer_timeout_ms(xfer, &ehci_timeout, xfer->timeout);
967 }
968}
969
970#define EHCI_APPEND_FS_TD(std,last) (last) = _ehci_append_fs_td(std,last)
971static ehci_sitd_t *
972_ehci_append_fs_td(ehci_sitd_t *std, ehci_sitd_t *last)
973{
974 DPRINTFN(11, "%p to %p\n", std, last);
975
976 /* (sc->sc_bus.mtx) must be locked */
977
978 std->next = last->next;
979 std->sitd_next = last->sitd_next;
980
981 std->prev = last;
982
967 }
968}
969
970#define EHCI_APPEND_FS_TD(std,last) (last) = _ehci_append_fs_td(std,last)
971static ehci_sitd_t *
972_ehci_append_fs_td(ehci_sitd_t *std, ehci_sitd_t *last)
973{
974 DPRINTFN(11, "%p to %p\n", std, last);
975
976 /* (sc->sc_bus.mtx) must be locked */
977
978 std->next = last->next;
979 std->sitd_next = last->sitd_next;
980
981 std->prev = last;
982
983 usb2_pc_cpu_flush(std->page_cache);
983 usb_pc_cpu_flush(std->page_cache);
984
985 /*
986 * the last->next->prev is never followed: std->next->prev = std;
987 */
988 last->next = std;
989 last->sitd_next = std->sitd_self;
990
984
985 /*
986 * the last->next->prev is never followed: std->next->prev = std;
987 */
988 last->next = std;
989 last->sitd_next = std->sitd_self;
990
991 usb2_pc_cpu_flush(last->page_cache);
991 usb_pc_cpu_flush(last->page_cache);
992
993 return (std);
994}
995
996#define EHCI_APPEND_HS_TD(std,last) (last) = _ehci_append_hs_td(std,last)
997static ehci_itd_t *
998_ehci_append_hs_td(ehci_itd_t *std, ehci_itd_t *last)
999{
1000 DPRINTFN(11, "%p to %p\n", std, last);
1001
1002 /* (sc->sc_bus.mtx) must be locked */
1003
1004 std->next = last->next;
1005 std->itd_next = last->itd_next;
1006
1007 std->prev = last;
1008
992
993 return (std);
994}
995
996#define EHCI_APPEND_HS_TD(std,last) (last) = _ehci_append_hs_td(std,last)
997static ehci_itd_t *
998_ehci_append_hs_td(ehci_itd_t *std, ehci_itd_t *last)
999{
1000 DPRINTFN(11, "%p to %p\n", std, last);
1001
1002 /* (sc->sc_bus.mtx) must be locked */
1003
1004 std->next = last->next;
1005 std->itd_next = last->itd_next;
1006
1007 std->prev = last;
1008
1009 usb2_pc_cpu_flush(std->page_cache);
1009 usb_pc_cpu_flush(std->page_cache);
1010
1011 /*
1012 * the last->next->prev is never followed: std->next->prev = std;
1013 */
1014 last->next = std;
1015 last->itd_next = std->itd_self;
1016
1010
1011 /*
1012 * the last->next->prev is never followed: std->next->prev = std;
1013 */
1014 last->next = std;
1015 last->itd_next = std->itd_self;
1016
1017 usb2_pc_cpu_flush(last->page_cache);
1017 usb_pc_cpu_flush(last->page_cache);
1018
1019 return (std);
1020}
1021
1022#define EHCI_APPEND_QH(sqh,last) (last) = _ehci_append_qh(sqh,last)
1023static ehci_qh_t *
1024_ehci_append_qh(ehci_qh_t *sqh, ehci_qh_t *last)
1025{
1026 DPRINTFN(11, "%p to %p\n", sqh, last);
1027
1028 if (sqh->prev != NULL) {
1029 /* should not happen */
1030 DPRINTFN(0, "QH already linked!\n");
1031 return (last);
1032 }
1033 /* (sc->sc_bus.mtx) must be locked */
1034
1035 sqh->next = last->next;
1036 sqh->qh_link = last->qh_link;
1037
1038 sqh->prev = last;
1039
1018
1019 return (std);
1020}
1021
1022#define EHCI_APPEND_QH(sqh,last) (last) = _ehci_append_qh(sqh,last)
1023static ehci_qh_t *
1024_ehci_append_qh(ehci_qh_t *sqh, ehci_qh_t *last)
1025{
1026 DPRINTFN(11, "%p to %p\n", sqh, last);
1027
1028 if (sqh->prev != NULL) {
1029 /* should not happen */
1030 DPRINTFN(0, "QH already linked!\n");
1031 return (last);
1032 }
1033 /* (sc->sc_bus.mtx) must be locked */
1034
1035 sqh->next = last->next;
1036 sqh->qh_link = last->qh_link;
1037
1038 sqh->prev = last;
1039
1040 usb2_pc_cpu_flush(sqh->page_cache);
1040 usb_pc_cpu_flush(sqh->page_cache);
1041
1042 /*
1043 * the last->next->prev is never followed: sqh->next->prev = sqh;
1044 */
1045
1046 last->next = sqh;
1047 last->qh_link = sqh->qh_self;
1048
1041
1042 /*
1043 * the last->next->prev is never followed: sqh->next->prev = sqh;
1044 */
1045
1046 last->next = sqh;
1047 last->qh_link = sqh->qh_self;
1048
1049 usb2_pc_cpu_flush(last->page_cache);
1049 usb_pc_cpu_flush(last->page_cache);
1050
1051 return (sqh);
1052}
1053
1054#define EHCI_REMOVE_FS_TD(std,last) (last) = _ehci_remove_fs_td(std,last)
1055static ehci_sitd_t *
1056_ehci_remove_fs_td(ehci_sitd_t *std, ehci_sitd_t *last)
1057{
1058 DPRINTFN(11, "%p from %p\n", std, last);
1059
1060 /* (sc->sc_bus.mtx) must be locked */
1061
1062 std->prev->next = std->next;
1063 std->prev->sitd_next = std->sitd_next;
1064
1050
1051 return (sqh);
1052}
1053
1054#define EHCI_REMOVE_FS_TD(std,last) (last) = _ehci_remove_fs_td(std,last)
1055static ehci_sitd_t *
1056_ehci_remove_fs_td(ehci_sitd_t *std, ehci_sitd_t *last)
1057{
1058 DPRINTFN(11, "%p from %p\n", std, last);
1059
1060 /* (sc->sc_bus.mtx) must be locked */
1061
1062 std->prev->next = std->next;
1063 std->prev->sitd_next = std->sitd_next;
1064
1065 usb2_pc_cpu_flush(std->prev->page_cache);
1065 usb_pc_cpu_flush(std->prev->page_cache);
1066
1067 if (std->next) {
1068 std->next->prev = std->prev;
1066
1067 if (std->next) {
1068 std->next->prev = std->prev;
1069 usb2_pc_cpu_flush(std->next->page_cache);
1069 usb_pc_cpu_flush(std->next->page_cache);
1070 }
1071 return ((last == std) ? std->prev : last);
1072}
1073
1074#define EHCI_REMOVE_HS_TD(std,last) (last) = _ehci_remove_hs_td(std,last)
1075static ehci_itd_t *
1076_ehci_remove_hs_td(ehci_itd_t *std, ehci_itd_t *last)
1077{
1078 DPRINTFN(11, "%p from %p\n", std, last);
1079
1080 /* (sc->sc_bus.mtx) must be locked */
1081
1082 std->prev->next = std->next;
1083 std->prev->itd_next = std->itd_next;
1084
1070 }
1071 return ((last == std) ? std->prev : last);
1072}
1073
1074#define EHCI_REMOVE_HS_TD(std,last) (last) = _ehci_remove_hs_td(std,last)
1075static ehci_itd_t *
1076_ehci_remove_hs_td(ehci_itd_t *std, ehci_itd_t *last)
1077{
1078 DPRINTFN(11, "%p from %p\n", std, last);
1079
1080 /* (sc->sc_bus.mtx) must be locked */
1081
1082 std->prev->next = std->next;
1083 std->prev->itd_next = std->itd_next;
1084
1085 usb2_pc_cpu_flush(std->prev->page_cache);
1085 usb_pc_cpu_flush(std->prev->page_cache);
1086
1087 if (std->next) {
1088 std->next->prev = std->prev;
1086
1087 if (std->next) {
1088 std->next->prev = std->prev;
1089 usb2_pc_cpu_flush(std->next->page_cache);
1089 usb_pc_cpu_flush(std->next->page_cache);
1090 }
1091 return ((last == std) ? std->prev : last);
1092}
1093
1094#define EHCI_REMOVE_QH(sqh,last) (last) = _ehci_remove_qh(sqh,last)
1095static ehci_qh_t *
1096_ehci_remove_qh(ehci_qh_t *sqh, ehci_qh_t *last)
1097{
1098 DPRINTFN(11, "%p from %p\n", sqh, last);
1099
1100 /* (sc->sc_bus.mtx) must be locked */
1101
1102 /* only remove if not removed from a queue */
1103 if (sqh->prev) {
1104
1105 sqh->prev->next = sqh->next;
1106 sqh->prev->qh_link = sqh->qh_link;
1107
1090 }
1091 return ((last == std) ? std->prev : last);
1092}
1093
1094#define EHCI_REMOVE_QH(sqh,last) (last) = _ehci_remove_qh(sqh,last)
1095static ehci_qh_t *
1096_ehci_remove_qh(ehci_qh_t *sqh, ehci_qh_t *last)
1097{
1098 DPRINTFN(11, "%p from %p\n", sqh, last);
1099
1100 /* (sc->sc_bus.mtx) must be locked */
1101
1102 /* only remove if not removed from a queue */
1103 if (sqh->prev) {
1104
1105 sqh->prev->next = sqh->next;
1106 sqh->prev->qh_link = sqh->qh_link;
1107
1108 usb2_pc_cpu_flush(sqh->prev->page_cache);
1108 usb_pc_cpu_flush(sqh->prev->page_cache);
1109
1110 if (sqh->next) {
1111 sqh->next->prev = sqh->prev;
1109
1110 if (sqh->next) {
1111 sqh->next->prev = sqh->prev;
1112 usb2_pc_cpu_flush(sqh->next->page_cache);
1112 usb_pc_cpu_flush(sqh->next->page_cache);
1113 }
1114 last = ((last == sqh) ? sqh->prev : last);
1115
1116 sqh->prev = 0;
1117
1113 }
1114 last = ((last == sqh) ? sqh->prev : last);
1115
1116 sqh->prev = 0;
1117
1118 usb2_pc_cpu_flush(sqh->page_cache);
1118 usb_pc_cpu_flush(sqh->page_cache);
1119 }
1120 return (last);
1121}
1122
1123static usb_error_t
1124ehci_non_isoc_done_sub(struct usb_xfer *xfer)
1125{
1126 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
1127 ehci_qtd_t *td;
1128 ehci_qtd_t *td_alt_next;
1129 uint32_t status;
1130 uint16_t len;
1131
1132 td = xfer->td_transfer_cache;
1133 td_alt_next = td->alt_next;
1134
1135 if (xfer->aframes != xfer->nframes) {
1136 xfer->frlengths[xfer->aframes] = 0;
1137 }
1138 while (1) {
1139
1119 }
1120 return (last);
1121}
1122
1123static usb_error_t
1124ehci_non_isoc_done_sub(struct usb_xfer *xfer)
1125{
1126 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
1127 ehci_qtd_t *td;
1128 ehci_qtd_t *td_alt_next;
1129 uint32_t status;
1130 uint16_t len;
1131
1132 td = xfer->td_transfer_cache;
1133 td_alt_next = td->alt_next;
1134
1135 if (xfer->aframes != xfer->nframes) {
1136 xfer->frlengths[xfer->aframes] = 0;
1137 }
1138 while (1) {
1139
1140 usb2_pc_cpu_invalidate(td->page_cache);
1140 usb_pc_cpu_invalidate(td->page_cache);
1141 status = hc32toh(sc, td->qtd_status);
1142
1143 len = EHCI_QTD_GET_BYTES(status);
1144
1145 /*
1146 * Verify the status length and
1147 * add the length to "frlengths[]":
1148 */
1149 if (len > td->len) {
1150 /* should not happen */
1151 DPRINTF("Invalid status length, "
1152 "0x%04x/0x%04x bytes\n", len, td->len);
1153 status |= EHCI_QTD_HALTED;
1154 } else if (xfer->aframes != xfer->nframes) {
1155 xfer->frlengths[xfer->aframes] += td->len - len;
1156 }
1157 /* Check for last transfer */
1158 if (((void *)td) == xfer->td_transfer_last) {
1159 td = NULL;
1160 break;
1161 }
1162 /* Check for transfer error */
1163 if (status & EHCI_QTD_HALTED) {
1164 /* the transfer is finished */
1165 td = NULL;
1166 break;
1167 }
1168 /* Check for short transfer */
1169 if (len > 0) {
1170 if (xfer->flags_int.short_frames_ok) {
1171 /* follow alt next */
1172 td = td->alt_next;
1173 } else {
1174 /* the transfer is finished */
1175 td = NULL;
1176 }
1177 break;
1178 }
1179 td = td->obj_next;
1180
1181 if (td->alt_next != td_alt_next) {
1182 /* this USB frame is complete */
1183 break;
1184 }
1185 }
1186
1187 /* update transfer cache */
1188
1189 xfer->td_transfer_cache = td;
1190
1191 /* update data toggle */
1192
1193 xfer->endpoint->toggle_next =
1194 (status & EHCI_QTD_TOGGLE_MASK) ? 1 : 0;
1195
1196#if USB_DEBUG
1197 if (status & EHCI_QTD_STATERRS) {
1198 DPRINTFN(11, "error, addr=%d, endpt=0x%02x, frame=0x%02x"
1199 "status=%s%s%s%s%s%s%s%s\n",
1200 xfer->address, xfer->endpointno, xfer->aframes,
1201 (status & EHCI_QTD_ACTIVE) ? "[ACTIVE]" : "[NOT_ACTIVE]",
1202 (status & EHCI_QTD_HALTED) ? "[HALTED]" : "",
1203 (status & EHCI_QTD_BUFERR) ? "[BUFERR]" : "",
1204 (status & EHCI_QTD_BABBLE) ? "[BABBLE]" : "",
1205 (status & EHCI_QTD_XACTERR) ? "[XACTERR]" : "",
1206 (status & EHCI_QTD_MISSEDMICRO) ? "[MISSED]" : "",
1207 (status & EHCI_QTD_SPLITXSTATE) ? "[SPLIT]" : "",
1208 (status & EHCI_QTD_PINGSTATE) ? "[PING]" : "");
1209 }
1210#endif
1211
1212 return ((status & EHCI_QTD_HALTED) ?
1213 USB_ERR_STALLED : USB_ERR_NORMAL_COMPLETION);
1214}
1215
1216static void
1217ehci_non_isoc_done(struct usb_xfer *xfer)
1218{
1219 usb_error_t err = 0;
1220
1221 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n",
1222 xfer, xfer->endpoint);
1223
1224#if USB_DEBUG
1225 if (ehcidebug > 10) {
1226 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
1227
1228 ehci_dump_sqtds(sc, xfer->td_transfer_first);
1229 }
1230#endif
1231
1232 /* reset scanner */
1233
1234 xfer->td_transfer_cache = xfer->td_transfer_first;
1235
1236 if (xfer->flags_int.control_xfr) {
1237
1238 if (xfer->flags_int.control_hdr) {
1239
1240 err = ehci_non_isoc_done_sub(xfer);
1241 }
1242 xfer->aframes = 1;
1243
1244 if (xfer->td_transfer_cache == NULL) {
1245 goto done;
1246 }
1247 }
1248 while (xfer->aframes != xfer->nframes) {
1249
1250 err = ehci_non_isoc_done_sub(xfer);
1251 xfer->aframes++;
1252
1253 if (xfer->td_transfer_cache == NULL) {
1254 goto done;
1255 }
1256 }
1257
1258 if (xfer->flags_int.control_xfr &&
1259 !xfer->flags_int.control_act) {
1260
1261 err = ehci_non_isoc_done_sub(xfer);
1262 }
1263done:
1264 ehci_device_done(xfer, err);
1265}
1266
1267/*------------------------------------------------------------------------*
1268 * ehci_check_transfer
1269 *
1270 * Return values:
1271 * 0: USB transfer is not finished
1272 * Else: USB transfer is finished
1273 *------------------------------------------------------------------------*/
1274static uint8_t
1275ehci_check_transfer(struct usb_xfer *xfer)
1276{
1277 struct usb_pipe_methods *methods = xfer->endpoint->methods;
1278 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
1279
1280 uint32_t status;
1281
1282 DPRINTFN(13, "xfer=%p checking transfer\n", xfer);
1283
1284 if (methods == &ehci_device_isoc_fs_methods) {
1285 ehci_sitd_t *td;
1286
1287 /* isochronous full speed transfer */
1288
1289 td = xfer->td_transfer_last;
1141 status = hc32toh(sc, td->qtd_status);
1142
1143 len = EHCI_QTD_GET_BYTES(status);
1144
1145 /*
1146 * Verify the status length and
1147 * add the length to "frlengths[]":
1148 */
1149 if (len > td->len) {
1150 /* should not happen */
1151 DPRINTF("Invalid status length, "
1152 "0x%04x/0x%04x bytes\n", len, td->len);
1153 status |= EHCI_QTD_HALTED;
1154 } else if (xfer->aframes != xfer->nframes) {
1155 xfer->frlengths[xfer->aframes] += td->len - len;
1156 }
1157 /* Check for last transfer */
1158 if (((void *)td) == xfer->td_transfer_last) {
1159 td = NULL;
1160 break;
1161 }
1162 /* Check for transfer error */
1163 if (status & EHCI_QTD_HALTED) {
1164 /* the transfer is finished */
1165 td = NULL;
1166 break;
1167 }
1168 /* Check for short transfer */
1169 if (len > 0) {
1170 if (xfer->flags_int.short_frames_ok) {
1171 /* follow alt next */
1172 td = td->alt_next;
1173 } else {
1174 /* the transfer is finished */
1175 td = NULL;
1176 }
1177 break;
1178 }
1179 td = td->obj_next;
1180
1181 if (td->alt_next != td_alt_next) {
1182 /* this USB frame is complete */
1183 break;
1184 }
1185 }
1186
1187 /* update transfer cache */
1188
1189 xfer->td_transfer_cache = td;
1190
1191 /* update data toggle */
1192
1193 xfer->endpoint->toggle_next =
1194 (status & EHCI_QTD_TOGGLE_MASK) ? 1 : 0;
1195
1196#if USB_DEBUG
1197 if (status & EHCI_QTD_STATERRS) {
1198 DPRINTFN(11, "error, addr=%d, endpt=0x%02x, frame=0x%02x"
1199 "status=%s%s%s%s%s%s%s%s\n",
1200 xfer->address, xfer->endpointno, xfer->aframes,
1201 (status & EHCI_QTD_ACTIVE) ? "[ACTIVE]" : "[NOT_ACTIVE]",
1202 (status & EHCI_QTD_HALTED) ? "[HALTED]" : "",
1203 (status & EHCI_QTD_BUFERR) ? "[BUFERR]" : "",
1204 (status & EHCI_QTD_BABBLE) ? "[BABBLE]" : "",
1205 (status & EHCI_QTD_XACTERR) ? "[XACTERR]" : "",
1206 (status & EHCI_QTD_MISSEDMICRO) ? "[MISSED]" : "",
1207 (status & EHCI_QTD_SPLITXSTATE) ? "[SPLIT]" : "",
1208 (status & EHCI_QTD_PINGSTATE) ? "[PING]" : "");
1209 }
1210#endif
1211
1212 return ((status & EHCI_QTD_HALTED) ?
1213 USB_ERR_STALLED : USB_ERR_NORMAL_COMPLETION);
1214}
1215
1216static void
1217ehci_non_isoc_done(struct usb_xfer *xfer)
1218{
1219 usb_error_t err = 0;
1220
1221 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n",
1222 xfer, xfer->endpoint);
1223
1224#if USB_DEBUG
1225 if (ehcidebug > 10) {
1226 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
1227
1228 ehci_dump_sqtds(sc, xfer->td_transfer_first);
1229 }
1230#endif
1231
1232 /* reset scanner */
1233
1234 xfer->td_transfer_cache = xfer->td_transfer_first;
1235
1236 if (xfer->flags_int.control_xfr) {
1237
1238 if (xfer->flags_int.control_hdr) {
1239
1240 err = ehci_non_isoc_done_sub(xfer);
1241 }
1242 xfer->aframes = 1;
1243
1244 if (xfer->td_transfer_cache == NULL) {
1245 goto done;
1246 }
1247 }
1248 while (xfer->aframes != xfer->nframes) {
1249
1250 err = ehci_non_isoc_done_sub(xfer);
1251 xfer->aframes++;
1252
1253 if (xfer->td_transfer_cache == NULL) {
1254 goto done;
1255 }
1256 }
1257
1258 if (xfer->flags_int.control_xfr &&
1259 !xfer->flags_int.control_act) {
1260
1261 err = ehci_non_isoc_done_sub(xfer);
1262 }
1263done:
1264 ehci_device_done(xfer, err);
1265}
1266
1267/*------------------------------------------------------------------------*
1268 * ehci_check_transfer
1269 *
1270 * Return values:
1271 * 0: USB transfer is not finished
1272 * Else: USB transfer is finished
1273 *------------------------------------------------------------------------*/
1274static uint8_t
1275ehci_check_transfer(struct usb_xfer *xfer)
1276{
1277 struct usb_pipe_methods *methods = xfer->endpoint->methods;
1278 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
1279
1280 uint32_t status;
1281
1282 DPRINTFN(13, "xfer=%p checking transfer\n", xfer);
1283
1284 if (methods == &ehci_device_isoc_fs_methods) {
1285 ehci_sitd_t *td;
1286
1287 /* isochronous full speed transfer */
1288
1289 td = xfer->td_transfer_last;
1290 usb2_pc_cpu_invalidate(td->page_cache);
1290 usb_pc_cpu_invalidate(td->page_cache);
1291 status = hc32toh(sc, td->sitd_status);
1292
1293 /* also check if first is complete */
1294
1295 td = xfer->td_transfer_first;
1291 status = hc32toh(sc, td->sitd_status);
1292
1293 /* also check if first is complete */
1294
1295 td = xfer->td_transfer_first;
1296 usb2_pc_cpu_invalidate(td->page_cache);
1296 usb_pc_cpu_invalidate(td->page_cache);
1297 status |= hc32toh(sc, td->sitd_status);
1298
1299 if (!(status & EHCI_SITD_ACTIVE)) {
1300 ehci_device_done(xfer, USB_ERR_NORMAL_COMPLETION);
1301 goto transferred;
1302 }
1303 } else if (methods == &ehci_device_isoc_hs_methods) {
1304 ehci_itd_t *td;
1305
1306 /* isochronous high speed transfer */
1307
1308 td = xfer->td_transfer_last;
1297 status |= hc32toh(sc, td->sitd_status);
1298
1299 if (!(status & EHCI_SITD_ACTIVE)) {
1300 ehci_device_done(xfer, USB_ERR_NORMAL_COMPLETION);
1301 goto transferred;
1302 }
1303 } else if (methods == &ehci_device_isoc_hs_methods) {
1304 ehci_itd_t *td;
1305
1306 /* isochronous high speed transfer */
1307
1308 td = xfer->td_transfer_last;
1309 usb2_pc_cpu_invalidate(td->page_cache);
1309 usb_pc_cpu_invalidate(td->page_cache);
1310 status =
1311 td->itd_status[0] | td->itd_status[1] |
1312 td->itd_status[2] | td->itd_status[3] |
1313 td->itd_status[4] | td->itd_status[5] |
1314 td->itd_status[6] | td->itd_status[7];
1315
1316 /* also check first transfer */
1317 td = xfer->td_transfer_first;
1310 status =
1311 td->itd_status[0] | td->itd_status[1] |
1312 td->itd_status[2] | td->itd_status[3] |
1313 td->itd_status[4] | td->itd_status[5] |
1314 td->itd_status[6] | td->itd_status[7];
1315
1316 /* also check first transfer */
1317 td = xfer->td_transfer_first;
1318 usb2_pc_cpu_invalidate(td->page_cache);
1318 usb_pc_cpu_invalidate(td->page_cache);
1319 status |=
1320 td->itd_status[0] | td->itd_status[1] |
1321 td->itd_status[2] | td->itd_status[3] |
1322 td->itd_status[4] | td->itd_status[5] |
1323 td->itd_status[6] | td->itd_status[7];
1324
1325 /* if no transactions are active we continue */
1326 if (!(status & htohc32(sc, EHCI_ITD_ACTIVE))) {
1327 ehci_device_done(xfer, USB_ERR_NORMAL_COMPLETION);
1328 goto transferred;
1329 }
1330 } else {
1331 ehci_qtd_t *td;
1332
1333 /* non-isochronous transfer */
1334
1335 /*
1336 * check whether there is an error somewhere in the middle,
1337 * or whether there was a short packet (SPD and not ACTIVE)
1338 */
1339 td = xfer->td_transfer_cache;
1340
1341 while (1) {
1319 status |=
1320 td->itd_status[0] | td->itd_status[1] |
1321 td->itd_status[2] | td->itd_status[3] |
1322 td->itd_status[4] | td->itd_status[5] |
1323 td->itd_status[6] | td->itd_status[7];
1324
1325 /* if no transactions are active we continue */
1326 if (!(status & htohc32(sc, EHCI_ITD_ACTIVE))) {
1327 ehci_device_done(xfer, USB_ERR_NORMAL_COMPLETION);
1328 goto transferred;
1329 }
1330 } else {
1331 ehci_qtd_t *td;
1332
1333 /* non-isochronous transfer */
1334
1335 /*
1336 * check whether there is an error somewhere in the middle,
1337 * or whether there was a short packet (SPD and not ACTIVE)
1338 */
1339 td = xfer->td_transfer_cache;
1340
1341 while (1) {
1342 usb2_pc_cpu_invalidate(td->page_cache);
1342 usb_pc_cpu_invalidate(td->page_cache);
1343 status = hc32toh(sc, td->qtd_status);
1344
1345 /*
1346 * if there is an active TD the transfer isn't done
1347 */
1348 if (status & EHCI_QTD_ACTIVE) {
1349 /* update cache */
1350 xfer->td_transfer_cache = td;
1351 goto done;
1352 }
1353 /*
1354 * last transfer descriptor makes the transfer done
1355 */
1356 if (((void *)td) == xfer->td_transfer_last) {
1357 break;
1358 }
1359 /*
1360 * any kind of error makes the transfer done
1361 */
1362 if (status & EHCI_QTD_HALTED) {
1363 break;
1364 }
1365 /*
1366 * if there is no alternate next transfer, a short
1367 * packet also makes the transfer done
1368 */
1369 if (EHCI_QTD_GET_BYTES(status)) {
1370 if (xfer->flags_int.short_frames_ok) {
1371 /* follow alt next */
1372 if (td->alt_next) {
1373 td = td->alt_next;
1374 continue;
1375 }
1376 }
1377 /* transfer is done */
1378 break;
1379 }
1380 td = td->obj_next;
1381 }
1382 ehci_non_isoc_done(xfer);
1383 goto transferred;
1384 }
1385
1386done:
1387 DPRINTFN(13, "xfer=%p is still active\n", xfer);
1388 return (0);
1389
1390transferred:
1391 return (1);
1392}
1393
1394static void
1395ehci_pcd_enable(ehci_softc_t *sc)
1396{
1397 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
1398
1399 sc->sc_eintrs |= EHCI_STS_PCD;
1400 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs);
1401
1402 /* acknowledge any PCD interrupt */
1403 EOWRITE4(sc, EHCI_USBSTS, EHCI_STS_PCD);
1404
1405 ehci_root_intr(sc);
1406}
1407
1408static void
1409ehci_interrupt_poll(ehci_softc_t *sc)
1410{
1411 struct usb_xfer *xfer;
1412
1413repeat:
1414 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
1415 /*
1416 * check if transfer is transferred
1417 */
1418 if (ehci_check_transfer(xfer)) {
1419 /* queue has been modified */
1420 goto repeat;
1421 }
1422 }
1423}
1424
1425/*------------------------------------------------------------------------*
1426 * ehci_interrupt - EHCI interrupt handler
1427 *
1428 * NOTE: Do not access "sc->sc_bus.bdev" inside the interrupt handler,
1429 * hence the interrupt handler will be setup before "sc->sc_bus.bdev"
1430 * is present !
1431 *------------------------------------------------------------------------*/
1432void
1433ehci_interrupt(ehci_softc_t *sc)
1434{
1435 uint32_t status;
1436
1437 USB_BUS_LOCK(&sc->sc_bus);
1438
1439 DPRINTFN(16, "real interrupt\n");
1440
1441#if USB_DEBUG
1442 if (ehcidebug > 15) {
1443 ehci_dump_regs(sc);
1444 }
1445#endif
1446
1447 status = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS));
1448 if (status == 0) {
1449 /* the interrupt was not for us */
1450 goto done;
1451 }
1452 if (!(status & sc->sc_eintrs)) {
1453 goto done;
1454 }
1455 EOWRITE4(sc, EHCI_USBSTS, status); /* acknowledge */
1456
1457 status &= sc->sc_eintrs;
1458
1459 if (status & EHCI_STS_HSE) {
1460 printf("%s: unrecoverable error, "
1461 "controller halted\n", __FUNCTION__);
1462#if USB_DEBUG
1463 ehci_dump_regs(sc);
1464 ehci_dump_isoc(sc);
1465#endif
1466 }
1467 if (status & EHCI_STS_PCD) {
1468 /*
1469 * Disable PCD interrupt for now, because it will be
1470 * on until the port has been reset.
1471 */
1472 sc->sc_eintrs &= ~EHCI_STS_PCD;
1473 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs);
1474
1475 ehci_root_intr(sc);
1476
1477 /* do not allow RHSC interrupts > 1 per second */
1343 status = hc32toh(sc, td->qtd_status);
1344
1345 /*
1346 * if there is an active TD the transfer isn't done
1347 */
1348 if (status & EHCI_QTD_ACTIVE) {
1349 /* update cache */
1350 xfer->td_transfer_cache = td;
1351 goto done;
1352 }
1353 /*
1354 * last transfer descriptor makes the transfer done
1355 */
1356 if (((void *)td) == xfer->td_transfer_last) {
1357 break;
1358 }
1359 /*
1360 * any kind of error makes the transfer done
1361 */
1362 if (status & EHCI_QTD_HALTED) {
1363 break;
1364 }
1365 /*
1366 * if there is no alternate next transfer, a short
1367 * packet also makes the transfer done
1368 */
1369 if (EHCI_QTD_GET_BYTES(status)) {
1370 if (xfer->flags_int.short_frames_ok) {
1371 /* follow alt next */
1372 if (td->alt_next) {
1373 td = td->alt_next;
1374 continue;
1375 }
1376 }
1377 /* transfer is done */
1378 break;
1379 }
1380 td = td->obj_next;
1381 }
1382 ehci_non_isoc_done(xfer);
1383 goto transferred;
1384 }
1385
1386done:
1387 DPRINTFN(13, "xfer=%p is still active\n", xfer);
1388 return (0);
1389
1390transferred:
1391 return (1);
1392}
1393
1394static void
1395ehci_pcd_enable(ehci_softc_t *sc)
1396{
1397 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
1398
1399 sc->sc_eintrs |= EHCI_STS_PCD;
1400 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs);
1401
1402 /* acknowledge any PCD interrupt */
1403 EOWRITE4(sc, EHCI_USBSTS, EHCI_STS_PCD);
1404
1405 ehci_root_intr(sc);
1406}
1407
1408static void
1409ehci_interrupt_poll(ehci_softc_t *sc)
1410{
1411 struct usb_xfer *xfer;
1412
1413repeat:
1414 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
1415 /*
1416 * check if transfer is transferred
1417 */
1418 if (ehci_check_transfer(xfer)) {
1419 /* queue has been modified */
1420 goto repeat;
1421 }
1422 }
1423}
1424
1425/*------------------------------------------------------------------------*
1426 * ehci_interrupt - EHCI interrupt handler
1427 *
1428 * NOTE: Do not access "sc->sc_bus.bdev" inside the interrupt handler,
1429 * hence the interrupt handler will be setup before "sc->sc_bus.bdev"
1430 * is present !
1431 *------------------------------------------------------------------------*/
1432void
1433ehci_interrupt(ehci_softc_t *sc)
1434{
1435 uint32_t status;
1436
1437 USB_BUS_LOCK(&sc->sc_bus);
1438
1439 DPRINTFN(16, "real interrupt\n");
1440
1441#if USB_DEBUG
1442 if (ehcidebug > 15) {
1443 ehci_dump_regs(sc);
1444 }
1445#endif
1446
1447 status = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS));
1448 if (status == 0) {
1449 /* the interrupt was not for us */
1450 goto done;
1451 }
1452 if (!(status & sc->sc_eintrs)) {
1453 goto done;
1454 }
1455 EOWRITE4(sc, EHCI_USBSTS, status); /* acknowledge */
1456
1457 status &= sc->sc_eintrs;
1458
1459 if (status & EHCI_STS_HSE) {
1460 printf("%s: unrecoverable error, "
1461 "controller halted\n", __FUNCTION__);
1462#if USB_DEBUG
1463 ehci_dump_regs(sc);
1464 ehci_dump_isoc(sc);
1465#endif
1466 }
1467 if (status & EHCI_STS_PCD) {
1468 /*
1469 * Disable PCD interrupt for now, because it will be
1470 * on until the port has been reset.
1471 */
1472 sc->sc_eintrs &= ~EHCI_STS_PCD;
1473 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs);
1474
1475 ehci_root_intr(sc);
1476
1477 /* do not allow RHSC interrupts > 1 per second */
1478 usb2_callout_reset(&sc->sc_tmo_pcd, hz,
1478 usb_callout_reset(&sc->sc_tmo_pcd, hz,
1479 (void *)&ehci_pcd_enable, sc);
1480 }
1481 status &= ~(EHCI_STS_INT | EHCI_STS_ERRINT | EHCI_STS_PCD | EHCI_STS_IAA);
1482
1483 if (status != 0) {
1484 /* block unprocessed interrupts */
1485 sc->sc_eintrs &= ~status;
1486 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs);
1487 printf("%s: blocking interrupts 0x%x\n", __FUNCTION__, status);
1488 }
1489 /* poll all the USB transfers */
1490 ehci_interrupt_poll(sc);
1491
1492done:
1493 USB_BUS_UNLOCK(&sc->sc_bus);
1494}
1495
1496/*
1497 * called when a request does not complete
1498 */
1499static void
1500ehci_timeout(void *arg)
1501{
1502 struct usb_xfer *xfer = arg;
1503
1504 DPRINTF("xfer=%p\n", xfer);
1505
1506 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED);
1507
1508 /* transfer is transferred */
1509 ehci_device_done(xfer, USB_ERR_TIMEOUT);
1510}
1511
1512static void
1513ehci_do_poll(struct usb_bus *bus)
1514{
1515 ehci_softc_t *sc = EHCI_BUS2SC(bus);
1516
1517 USB_BUS_LOCK(&sc->sc_bus);
1518 ehci_interrupt_poll(sc);
1519 USB_BUS_UNLOCK(&sc->sc_bus);
1520}
1521
1522static void
1523ehci_setup_standard_chain_sub(struct ehci_std_temp *temp)
1524{
1525 struct usb_page_search buf_res;
1526 ehci_qtd_t *td;
1527 ehci_qtd_t *td_next;
1528 ehci_qtd_t *td_alt_next;
1529 uint32_t qtd_altnext;
1530 uint32_t buf_offset;
1531 uint32_t average;
1532 uint32_t len_old;
1533 uint32_t terminate;
1534 uint8_t shortpkt_old;
1535 uint8_t precompute;
1536
1537 terminate = htohc32(temp->sc, EHCI_LINK_TERMINATE);
1538 qtd_altnext = terminate;
1539 td_alt_next = NULL;
1540 buf_offset = 0;
1541 shortpkt_old = temp->shortpkt;
1542 len_old = temp->len;
1543 precompute = 1;
1544
1545restart:
1546
1547 td = temp->td;
1548 td_next = temp->td_next;
1549
1550 while (1) {
1551
1552 if (temp->len == 0) {
1553
1554 if (temp->shortpkt) {
1555 break;
1556 }
1557 /* send a Zero Length Packet, ZLP, last */
1558
1559 temp->shortpkt = 1;
1560 average = 0;
1561
1562 } else {
1563
1564 average = temp->average;
1565
1566 if (temp->len < average) {
1567 if (temp->len % temp->max_frame_size) {
1568 temp->shortpkt = 1;
1569 }
1570 average = temp->len;
1571 }
1572 }
1573
1574 if (td_next == NULL) {
1575 panic("%s: out of EHCI transfer descriptors!", __FUNCTION__);
1576 }
1577 /* get next TD */
1578
1579 td = td_next;
1580 td_next = td->obj_next;
1581
1582 /* check if we are pre-computing */
1583
1584 if (precompute) {
1585
1586 /* update remaining length */
1587
1588 temp->len -= average;
1589
1590 continue;
1591 }
1592 /* fill out current TD */
1593
1594 td->qtd_status =
1595 temp->qtd_status |
1596 htohc32(temp->sc, EHCI_QTD_SET_BYTES(average));
1597
1598 if (average == 0) {
1599
1600 if (temp->auto_data_toggle == 0) {
1601
1602 /* update data toggle, ZLP case */
1603
1604 temp->qtd_status ^=
1605 htohc32(temp->sc, EHCI_QTD_TOGGLE_MASK);
1606 }
1607 td->len = 0;
1608
1609 td->qtd_buffer[0] = 0;
1610 td->qtd_buffer_hi[0] = 0;
1611
1612 td->qtd_buffer[1] = 0;
1613 td->qtd_buffer_hi[1] = 0;
1614
1615 } else {
1616
1617 uint8_t x;
1618
1619 if (temp->auto_data_toggle == 0) {
1620
1621 /* update data toggle */
1622
1623 if (((average + temp->max_frame_size - 1) /
1624 temp->max_frame_size) & 1) {
1625 temp->qtd_status ^=
1626 htohc32(temp->sc, EHCI_QTD_TOGGLE_MASK);
1627 }
1628 }
1629 td->len = average;
1630
1631 /* update remaining length */
1632
1633 temp->len -= average;
1634
1635 /* fill out buffer pointers */
1636
1479 (void *)&ehci_pcd_enable, sc);
1480 }
1481 status &= ~(EHCI_STS_INT | EHCI_STS_ERRINT | EHCI_STS_PCD | EHCI_STS_IAA);
1482
1483 if (status != 0) {
1484 /* block unprocessed interrupts */
1485 sc->sc_eintrs &= ~status;
1486 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs);
1487 printf("%s: blocking interrupts 0x%x\n", __FUNCTION__, status);
1488 }
1489 /* poll all the USB transfers */
1490 ehci_interrupt_poll(sc);
1491
1492done:
1493 USB_BUS_UNLOCK(&sc->sc_bus);
1494}
1495
1496/*
1497 * called when a request does not complete
1498 */
1499static void
1500ehci_timeout(void *arg)
1501{
1502 struct usb_xfer *xfer = arg;
1503
1504 DPRINTF("xfer=%p\n", xfer);
1505
1506 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED);
1507
1508 /* transfer is transferred */
1509 ehci_device_done(xfer, USB_ERR_TIMEOUT);
1510}
1511
1512static void
1513ehci_do_poll(struct usb_bus *bus)
1514{
1515 ehci_softc_t *sc = EHCI_BUS2SC(bus);
1516
1517 USB_BUS_LOCK(&sc->sc_bus);
1518 ehci_interrupt_poll(sc);
1519 USB_BUS_UNLOCK(&sc->sc_bus);
1520}
1521
1522static void
1523ehci_setup_standard_chain_sub(struct ehci_std_temp *temp)
1524{
1525 struct usb_page_search buf_res;
1526 ehci_qtd_t *td;
1527 ehci_qtd_t *td_next;
1528 ehci_qtd_t *td_alt_next;
1529 uint32_t qtd_altnext;
1530 uint32_t buf_offset;
1531 uint32_t average;
1532 uint32_t len_old;
1533 uint32_t terminate;
1534 uint8_t shortpkt_old;
1535 uint8_t precompute;
1536
1537 terminate = htohc32(temp->sc, EHCI_LINK_TERMINATE);
1538 qtd_altnext = terminate;
1539 td_alt_next = NULL;
1540 buf_offset = 0;
1541 shortpkt_old = temp->shortpkt;
1542 len_old = temp->len;
1543 precompute = 1;
1544
1545restart:
1546
1547 td = temp->td;
1548 td_next = temp->td_next;
1549
1550 while (1) {
1551
1552 if (temp->len == 0) {
1553
1554 if (temp->shortpkt) {
1555 break;
1556 }
1557 /* send a Zero Length Packet, ZLP, last */
1558
1559 temp->shortpkt = 1;
1560 average = 0;
1561
1562 } else {
1563
1564 average = temp->average;
1565
1566 if (temp->len < average) {
1567 if (temp->len % temp->max_frame_size) {
1568 temp->shortpkt = 1;
1569 }
1570 average = temp->len;
1571 }
1572 }
1573
1574 if (td_next == NULL) {
1575 panic("%s: out of EHCI transfer descriptors!", __FUNCTION__);
1576 }
1577 /* get next TD */
1578
1579 td = td_next;
1580 td_next = td->obj_next;
1581
1582 /* check if we are pre-computing */
1583
1584 if (precompute) {
1585
1586 /* update remaining length */
1587
1588 temp->len -= average;
1589
1590 continue;
1591 }
1592 /* fill out current TD */
1593
1594 td->qtd_status =
1595 temp->qtd_status |
1596 htohc32(temp->sc, EHCI_QTD_SET_BYTES(average));
1597
1598 if (average == 0) {
1599
1600 if (temp->auto_data_toggle == 0) {
1601
1602 /* update data toggle, ZLP case */
1603
1604 temp->qtd_status ^=
1605 htohc32(temp->sc, EHCI_QTD_TOGGLE_MASK);
1606 }
1607 td->len = 0;
1608
1609 td->qtd_buffer[0] = 0;
1610 td->qtd_buffer_hi[0] = 0;
1611
1612 td->qtd_buffer[1] = 0;
1613 td->qtd_buffer_hi[1] = 0;
1614
1615 } else {
1616
1617 uint8_t x;
1618
1619 if (temp->auto_data_toggle == 0) {
1620
1621 /* update data toggle */
1622
1623 if (((average + temp->max_frame_size - 1) /
1624 temp->max_frame_size) & 1) {
1625 temp->qtd_status ^=
1626 htohc32(temp->sc, EHCI_QTD_TOGGLE_MASK);
1627 }
1628 }
1629 td->len = average;
1630
1631 /* update remaining length */
1632
1633 temp->len -= average;
1634
1635 /* fill out buffer pointers */
1636
1637 usb2_get_page(temp->pc, buf_offset, &buf_res);
1637 usbd_get_page(temp->pc, buf_offset, &buf_res);
1638 td->qtd_buffer[0] =
1639 htohc32(temp->sc, buf_res.physaddr);
1640 td->qtd_buffer_hi[0] = 0;
1641
1642 x = 1;
1643
1644 while (average > EHCI_PAGE_SIZE) {
1645 average -= EHCI_PAGE_SIZE;
1646 buf_offset += EHCI_PAGE_SIZE;
1638 td->qtd_buffer[0] =
1639 htohc32(temp->sc, buf_res.physaddr);
1640 td->qtd_buffer_hi[0] = 0;
1641
1642 x = 1;
1643
1644 while (average > EHCI_PAGE_SIZE) {
1645 average -= EHCI_PAGE_SIZE;
1646 buf_offset += EHCI_PAGE_SIZE;
1647 usb2_get_page(temp->pc, buf_offset, &buf_res);
1647 usbd_get_page(temp->pc, buf_offset, &buf_res);
1648 td->qtd_buffer[x] =
1649 htohc32(temp->sc,
1650 buf_res.physaddr & (~0xFFF));
1651 td->qtd_buffer_hi[x] = 0;
1652 x++;
1653 }
1654
1655 /*
1656 * NOTE: The "average" variable is never zero after
1657 * exiting the loop above !
1658 *
1659 * NOTE: We have to subtract one from the offset to
1660 * ensure that we are computing the physical address
1661 * of a valid page !
1662 */
1663 buf_offset += average;
1648 td->qtd_buffer[x] =
1649 htohc32(temp->sc,
1650 buf_res.physaddr & (~0xFFF));
1651 td->qtd_buffer_hi[x] = 0;
1652 x++;
1653 }
1654
1655 /*
1656 * NOTE: The "average" variable is never zero after
1657 * exiting the loop above !
1658 *
1659 * NOTE: We have to subtract one from the offset to
1660 * ensure that we are computing the physical address
1661 * of a valid page !
1662 */
1663 buf_offset += average;
1664 usb2_get_page(temp->pc, buf_offset - 1, &buf_res);
1664 usbd_get_page(temp->pc, buf_offset - 1, &buf_res);
1665 td->qtd_buffer[x] =
1666 htohc32(temp->sc,
1667 buf_res.physaddr & (~0xFFF));
1668 td->qtd_buffer_hi[x] = 0;
1669 }
1670
1671 if (td_next) {
1672 /* link the current TD with the next one */
1673 td->qtd_next = td_next->qtd_self;
1674 }
1675 td->qtd_altnext = qtd_altnext;
1676 td->alt_next = td_alt_next;
1677
1665 td->qtd_buffer[x] =
1666 htohc32(temp->sc,
1667 buf_res.physaddr & (~0xFFF));
1668 td->qtd_buffer_hi[x] = 0;
1669 }
1670
1671 if (td_next) {
1672 /* link the current TD with the next one */
1673 td->qtd_next = td_next->qtd_self;
1674 }
1675 td->qtd_altnext = qtd_altnext;
1676 td->alt_next = td_alt_next;
1677
1678 usb2_pc_cpu_flush(td->page_cache);
1678 usb_pc_cpu_flush(td->page_cache);
1679 }
1680
1681 if (precompute) {
1682 precompute = 0;
1683
1684 /* setup alt next pointer, if any */
1685 if (temp->last_frame) {
1686 td_alt_next = NULL;
1687 qtd_altnext = terminate;
1688 } else {
1689 /* we use this field internally */
1690 td_alt_next = td_next;
1691 if (temp->setup_alt_next) {
1692 qtd_altnext = td_next->qtd_self;
1693 } else {
1694 qtd_altnext = terminate;
1695 }
1696 }
1697
1698 /* restore */
1699 temp->shortpkt = shortpkt_old;
1700 temp->len = len_old;
1701 goto restart;
1702 }
1703 temp->td = td;
1704 temp->td_next = td_next;
1705}
1706
1707static void
1708ehci_setup_standard_chain(struct usb_xfer *xfer, ehci_qh_t **qh_last)
1709{
1710 struct ehci_std_temp temp;
1711 struct usb_pipe_methods *methods;
1712 ehci_qh_t *qh;
1713 ehci_qtd_t *td;
1714 uint32_t qh_endp;
1715 uint32_t qh_endphub;
1716 uint32_t x;
1717
1718 DPRINTFN(9, "addr=%d endpt=%d sumlen=%d speed=%d\n",
1719 xfer->address, UE_GET_ADDR(xfer->endpointno),
1679 }
1680
1681 if (precompute) {
1682 precompute = 0;
1683
1684 /* setup alt next pointer, if any */
1685 if (temp->last_frame) {
1686 td_alt_next = NULL;
1687 qtd_altnext = terminate;
1688 } else {
1689 /* we use this field internally */
1690 td_alt_next = td_next;
1691 if (temp->setup_alt_next) {
1692 qtd_altnext = td_next->qtd_self;
1693 } else {
1694 qtd_altnext = terminate;
1695 }
1696 }
1697
1698 /* restore */
1699 temp->shortpkt = shortpkt_old;
1700 temp->len = len_old;
1701 goto restart;
1702 }
1703 temp->td = td;
1704 temp->td_next = td_next;
1705}
1706
1707static void
1708ehci_setup_standard_chain(struct usb_xfer *xfer, ehci_qh_t **qh_last)
1709{
1710 struct ehci_std_temp temp;
1711 struct usb_pipe_methods *methods;
1712 ehci_qh_t *qh;
1713 ehci_qtd_t *td;
1714 uint32_t qh_endp;
1715 uint32_t qh_endphub;
1716 uint32_t x;
1717
1718 DPRINTFN(9, "addr=%d endpt=%d sumlen=%d speed=%d\n",
1719 xfer->address, UE_GET_ADDR(xfer->endpointno),
1720 xfer->sumlen, usb2_get_speed(xfer->xroot->udev));
1720 xfer->sumlen, usbd_get_speed(xfer->xroot->udev));
1721
1722 temp.average = xfer->max_hc_frame_size;
1723 temp.max_frame_size = xfer->max_frame_size;
1724 temp.sc = EHCI_BUS2SC(xfer->xroot->bus);
1725
1726 /* toggle the DMA set we are using */
1727 xfer->flags_int.curr_dma_set ^= 1;
1728
1729 /* get next DMA set */
1730 td = xfer->td_start[xfer->flags_int.curr_dma_set];
1731
1732 xfer->td_transfer_first = td;
1733 xfer->td_transfer_cache = td;
1734
1735 temp.td = NULL;
1736 temp.td_next = td;
1737 temp.qtd_status = 0;
1738 temp.last_frame = 0;
1739 temp.setup_alt_next = xfer->flags_int.short_frames_ok;
1740
1741 if (xfer->flags_int.control_xfr) {
1742 if (xfer->endpoint->toggle_next) {
1743 /* DATA1 is next */
1744 temp.qtd_status |=
1745 htohc32(temp.sc, EHCI_QTD_SET_TOGGLE(1));
1746 }
1747 temp.auto_data_toggle = 0;
1748 } else {
1749 temp.auto_data_toggle = 1;
1750 }
1751
1721
1722 temp.average = xfer->max_hc_frame_size;
1723 temp.max_frame_size = xfer->max_frame_size;
1724 temp.sc = EHCI_BUS2SC(xfer->xroot->bus);
1725
1726 /* toggle the DMA set we are using */
1727 xfer->flags_int.curr_dma_set ^= 1;
1728
1729 /* get next DMA set */
1730 td = xfer->td_start[xfer->flags_int.curr_dma_set];
1731
1732 xfer->td_transfer_first = td;
1733 xfer->td_transfer_cache = td;
1734
1735 temp.td = NULL;
1736 temp.td_next = td;
1737 temp.qtd_status = 0;
1738 temp.last_frame = 0;
1739 temp.setup_alt_next = xfer->flags_int.short_frames_ok;
1740
1741 if (xfer->flags_int.control_xfr) {
1742 if (xfer->endpoint->toggle_next) {
1743 /* DATA1 is next */
1744 temp.qtd_status |=
1745 htohc32(temp.sc, EHCI_QTD_SET_TOGGLE(1));
1746 }
1747 temp.auto_data_toggle = 0;
1748 } else {
1749 temp.auto_data_toggle = 1;
1750 }
1751
1752 if (usb2_get_speed(xfer->xroot->udev) != USB_SPEED_HIGH) {
1752 if (usbd_get_speed(xfer->xroot->udev) != USB_SPEED_HIGH) {
1753 /* max 3 retries */
1754 temp.qtd_status |=
1755 htohc32(temp.sc, EHCI_QTD_SET_CERR(3));
1756 }
1757 /* check if we should prepend a setup message */
1758
1759 if (xfer->flags_int.control_xfr) {
1760 if (xfer->flags_int.control_hdr) {
1761
1762 temp.qtd_status &=
1763 htohc32(temp.sc, EHCI_QTD_SET_CERR(3));
1764 temp.qtd_status |= htohc32(temp.sc,
1765 EHCI_QTD_ACTIVE |
1766 EHCI_QTD_SET_PID(EHCI_QTD_PID_SETUP) |
1767 EHCI_QTD_SET_TOGGLE(0));
1768
1769 temp.len = xfer->frlengths[0];
1770 temp.pc = xfer->frbuffers + 0;
1771 temp.shortpkt = temp.len ? 1 : 0;
1772 /* check for last frame */
1773 if (xfer->nframes == 1) {
1774 /* no STATUS stage yet, SETUP is last */
1775 if (xfer->flags_int.control_act) {
1776 temp.last_frame = 1;
1777 temp.setup_alt_next = 0;
1778 }
1779 }
1780 ehci_setup_standard_chain_sub(&temp);
1781 }
1782 x = 1;
1783 } else {
1784 x = 0;
1785 }
1786
1787 while (x != xfer->nframes) {
1788
1789 /* DATA0 / DATA1 message */
1790
1791 temp.len = xfer->frlengths[x];
1792 temp.pc = xfer->frbuffers + x;
1793
1794 x++;
1795
1796 if (x == xfer->nframes) {
1797 if (xfer->flags_int.control_xfr) {
1798 /* no STATUS stage yet, DATA is last */
1799 if (xfer->flags_int.control_act) {
1800 temp.last_frame = 1;
1801 temp.setup_alt_next = 0;
1802 }
1803 } else {
1804 temp.last_frame = 1;
1805 temp.setup_alt_next = 0;
1806 }
1807 }
1808 /* keep previous data toggle and error count */
1809
1810 temp.qtd_status &=
1811 htohc32(temp.sc, EHCI_QTD_SET_CERR(3) |
1812 EHCI_QTD_SET_TOGGLE(1));
1813
1814 if (temp.len == 0) {
1815
1816 /* make sure that we send an USB packet */
1817
1818 temp.shortpkt = 0;
1819
1820 } else {
1821
1822 /* regular data transfer */
1823
1824 temp.shortpkt = (xfer->flags.force_short_xfer) ? 0 : 1;
1825 }
1826
1827 /* set endpoint direction */
1828
1829 temp.qtd_status |=
1830 (UE_GET_DIR(xfer->endpointno) == UE_DIR_IN) ?
1831 htohc32(temp.sc, EHCI_QTD_ACTIVE |
1832 EHCI_QTD_SET_PID(EHCI_QTD_PID_IN)) :
1833 htohc32(temp.sc, EHCI_QTD_ACTIVE |
1834 EHCI_QTD_SET_PID(EHCI_QTD_PID_OUT));
1835
1836 ehci_setup_standard_chain_sub(&temp);
1837 }
1838
1839 /* check if we should append a status stage */
1840
1841 if (xfer->flags_int.control_xfr &&
1842 !xfer->flags_int.control_act) {
1843
1844 /*
1845 * Send a DATA1 message and invert the current endpoint
1846 * direction.
1847 */
1848
1849 temp.qtd_status &= htohc32(temp.sc, EHCI_QTD_SET_CERR(3) |
1850 EHCI_QTD_SET_TOGGLE(1));
1851 temp.qtd_status |=
1852 (UE_GET_DIR(xfer->endpointno) == UE_DIR_OUT) ?
1853 htohc32(temp.sc, EHCI_QTD_ACTIVE |
1854 EHCI_QTD_SET_PID(EHCI_QTD_PID_IN) |
1855 EHCI_QTD_SET_TOGGLE(1)) :
1856 htohc32(temp.sc, EHCI_QTD_ACTIVE |
1857 EHCI_QTD_SET_PID(EHCI_QTD_PID_OUT) |
1858 EHCI_QTD_SET_TOGGLE(1));
1859
1860 temp.len = 0;
1861 temp.pc = NULL;
1862 temp.shortpkt = 0;
1863 temp.last_frame = 1;
1864 temp.setup_alt_next = 0;
1865
1866 ehci_setup_standard_chain_sub(&temp);
1867 }
1868 td = temp.td;
1869
1870 /* the last TD terminates the transfer: */
1871 td->qtd_next = htohc32(temp.sc, EHCI_LINK_TERMINATE);
1872 td->qtd_altnext = htohc32(temp.sc, EHCI_LINK_TERMINATE);
1873 td->qtd_status |= htohc32(temp.sc, EHCI_QTD_IOC);
1874
1753 /* max 3 retries */
1754 temp.qtd_status |=
1755 htohc32(temp.sc, EHCI_QTD_SET_CERR(3));
1756 }
1757 /* check if we should prepend a setup message */
1758
1759 if (xfer->flags_int.control_xfr) {
1760 if (xfer->flags_int.control_hdr) {
1761
1762 temp.qtd_status &=
1763 htohc32(temp.sc, EHCI_QTD_SET_CERR(3));
1764 temp.qtd_status |= htohc32(temp.sc,
1765 EHCI_QTD_ACTIVE |
1766 EHCI_QTD_SET_PID(EHCI_QTD_PID_SETUP) |
1767 EHCI_QTD_SET_TOGGLE(0));
1768
1769 temp.len = xfer->frlengths[0];
1770 temp.pc = xfer->frbuffers + 0;
1771 temp.shortpkt = temp.len ? 1 : 0;
1772 /* check for last frame */
1773 if (xfer->nframes == 1) {
1774 /* no STATUS stage yet, SETUP is last */
1775 if (xfer->flags_int.control_act) {
1776 temp.last_frame = 1;
1777 temp.setup_alt_next = 0;
1778 }
1779 }
1780 ehci_setup_standard_chain_sub(&temp);
1781 }
1782 x = 1;
1783 } else {
1784 x = 0;
1785 }
1786
1787 while (x != xfer->nframes) {
1788
1789 /* DATA0 / DATA1 message */
1790
1791 temp.len = xfer->frlengths[x];
1792 temp.pc = xfer->frbuffers + x;
1793
1794 x++;
1795
1796 if (x == xfer->nframes) {
1797 if (xfer->flags_int.control_xfr) {
1798 /* no STATUS stage yet, DATA is last */
1799 if (xfer->flags_int.control_act) {
1800 temp.last_frame = 1;
1801 temp.setup_alt_next = 0;
1802 }
1803 } else {
1804 temp.last_frame = 1;
1805 temp.setup_alt_next = 0;
1806 }
1807 }
1808 /* keep previous data toggle and error count */
1809
1810 temp.qtd_status &=
1811 htohc32(temp.sc, EHCI_QTD_SET_CERR(3) |
1812 EHCI_QTD_SET_TOGGLE(1));
1813
1814 if (temp.len == 0) {
1815
1816 /* make sure that we send an USB packet */
1817
1818 temp.shortpkt = 0;
1819
1820 } else {
1821
1822 /* regular data transfer */
1823
1824 temp.shortpkt = (xfer->flags.force_short_xfer) ? 0 : 1;
1825 }
1826
1827 /* set endpoint direction */
1828
1829 temp.qtd_status |=
1830 (UE_GET_DIR(xfer->endpointno) == UE_DIR_IN) ?
1831 htohc32(temp.sc, EHCI_QTD_ACTIVE |
1832 EHCI_QTD_SET_PID(EHCI_QTD_PID_IN)) :
1833 htohc32(temp.sc, EHCI_QTD_ACTIVE |
1834 EHCI_QTD_SET_PID(EHCI_QTD_PID_OUT));
1835
1836 ehci_setup_standard_chain_sub(&temp);
1837 }
1838
1839 /* check if we should append a status stage */
1840
1841 if (xfer->flags_int.control_xfr &&
1842 !xfer->flags_int.control_act) {
1843
1844 /*
1845 * Send a DATA1 message and invert the current endpoint
1846 * direction.
1847 */
1848
1849 temp.qtd_status &= htohc32(temp.sc, EHCI_QTD_SET_CERR(3) |
1850 EHCI_QTD_SET_TOGGLE(1));
1851 temp.qtd_status |=
1852 (UE_GET_DIR(xfer->endpointno) == UE_DIR_OUT) ?
1853 htohc32(temp.sc, EHCI_QTD_ACTIVE |
1854 EHCI_QTD_SET_PID(EHCI_QTD_PID_IN) |
1855 EHCI_QTD_SET_TOGGLE(1)) :
1856 htohc32(temp.sc, EHCI_QTD_ACTIVE |
1857 EHCI_QTD_SET_PID(EHCI_QTD_PID_OUT) |
1858 EHCI_QTD_SET_TOGGLE(1));
1859
1860 temp.len = 0;
1861 temp.pc = NULL;
1862 temp.shortpkt = 0;
1863 temp.last_frame = 1;
1864 temp.setup_alt_next = 0;
1865
1866 ehci_setup_standard_chain_sub(&temp);
1867 }
1868 td = temp.td;
1869
1870 /* the last TD terminates the transfer: */
1871 td->qtd_next = htohc32(temp.sc, EHCI_LINK_TERMINATE);
1872 td->qtd_altnext = htohc32(temp.sc, EHCI_LINK_TERMINATE);
1873 td->qtd_status |= htohc32(temp.sc, EHCI_QTD_IOC);
1874
1875 usb2_pc_cpu_flush(td->page_cache);
1875 usb_pc_cpu_flush(td->page_cache);
1876
1877 /* must have at least one frame! */
1878
1879 xfer->td_transfer_last = td;
1880
1881#if USB_DEBUG
1882 if (ehcidebug > 8) {
1883 DPRINTF("nexttog=%d; data before transfer:\n",
1884 xfer->endpoint->toggle_next);
1885 ehci_dump_sqtds(temp.sc,
1886 xfer->td_transfer_first);
1887 }
1888#endif
1889
1890 methods = xfer->endpoint->methods;
1891
1892 qh = xfer->qh_start[xfer->flags_int.curr_dma_set];
1893
1894 /* the "qh_link" field is filled when the QH is added */
1895
1896 qh_endp =
1897 (EHCI_QH_SET_ADDR(xfer->address) |
1898 EHCI_QH_SET_ENDPT(UE_GET_ADDR(xfer->endpointno)) |
1899 EHCI_QH_SET_MPL(xfer->max_packet_size));
1900
1876
1877 /* must have at least one frame! */
1878
1879 xfer->td_transfer_last = td;
1880
1881#if USB_DEBUG
1882 if (ehcidebug > 8) {
1883 DPRINTF("nexttog=%d; data before transfer:\n",
1884 xfer->endpoint->toggle_next);
1885 ehci_dump_sqtds(temp.sc,
1886 xfer->td_transfer_first);
1887 }
1888#endif
1889
1890 methods = xfer->endpoint->methods;
1891
1892 qh = xfer->qh_start[xfer->flags_int.curr_dma_set];
1893
1894 /* the "qh_link" field is filled when the QH is added */
1895
1896 qh_endp =
1897 (EHCI_QH_SET_ADDR(xfer->address) |
1898 EHCI_QH_SET_ENDPT(UE_GET_ADDR(xfer->endpointno)) |
1899 EHCI_QH_SET_MPL(xfer->max_packet_size));
1900
1901 if (usb2_get_speed(xfer->xroot->udev) == USB_SPEED_HIGH) {
1901 if (usbd_get_speed(xfer->xroot->udev) == USB_SPEED_HIGH) {
1902 qh_endp |= (EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH) |
1903 EHCI_QH_DTC);
1904 if (methods != &ehci_device_intr_methods)
1905 qh_endp |= EHCI_QH_SET_NRL(8);
1906 } else {
1907
1902 qh_endp |= (EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH) |
1903 EHCI_QH_DTC);
1904 if (methods != &ehci_device_intr_methods)
1905 qh_endp |= EHCI_QH_SET_NRL(8);
1906 } else {
1907
1908 if (usb2_get_speed(xfer->xroot->udev) == USB_SPEED_FULL) {
1908 if (usbd_get_speed(xfer->xroot->udev) == USB_SPEED_FULL) {
1909 qh_endp |= (EHCI_QH_SET_EPS(EHCI_QH_SPEED_FULL) |
1910 EHCI_QH_DTC);
1911 } else {
1912 qh_endp |= (EHCI_QH_SET_EPS(EHCI_QH_SPEED_LOW) |
1913 EHCI_QH_DTC);
1914 }
1915
1916 if (methods == &ehci_device_ctrl_methods) {
1917 qh_endp |= EHCI_QH_CTL;
1918 }
1919 if (methods != &ehci_device_intr_methods) {
1920 /* Only try one time per microframe! */
1921 qh_endp |= EHCI_QH_SET_NRL(1);
1922 }
1923 }
1924
1925 qh->qh_endp = htohc32(temp.sc, qh_endp);
1926
1927 qh_endphub =
1928 (EHCI_QH_SET_MULT(xfer->max_packet_count & 3) |
1909 qh_endp |= (EHCI_QH_SET_EPS(EHCI_QH_SPEED_FULL) |
1910 EHCI_QH_DTC);
1911 } else {
1912 qh_endp |= (EHCI_QH_SET_EPS(EHCI_QH_SPEED_LOW) |
1913 EHCI_QH_DTC);
1914 }
1915
1916 if (methods == &ehci_device_ctrl_methods) {
1917 qh_endp |= EHCI_QH_CTL;
1918 }
1919 if (methods != &ehci_device_intr_methods) {
1920 /* Only try one time per microframe! */
1921 qh_endp |= EHCI_QH_SET_NRL(1);
1922 }
1923 }
1924
1925 qh->qh_endp = htohc32(temp.sc, qh_endp);
1926
1927 qh_endphub =
1928 (EHCI_QH_SET_MULT(xfer->max_packet_count & 3) |
1929 EHCI_QH_SET_CMASK(xfer->usb2_cmask) |
1930 EHCI_QH_SET_SMASK(xfer->usb2_smask) |
1929 EHCI_QH_SET_CMASK(xfer->usb_cmask) |
1930 EHCI_QH_SET_SMASK(xfer->usb_smask) |
1931 EHCI_QH_SET_HUBA(xfer->xroot->udev->hs_hub_addr) |
1932 EHCI_QH_SET_PORT(xfer->xroot->udev->hs_port_no));
1933
1934 qh->qh_endphub = htohc32(temp.sc, qh_endphub);
1935 qh->qh_curqtd = htohc32(temp.sc, 0);
1936
1937 /* fill the overlay qTD */
1938 qh->qh_qtd.qtd_status = htohc32(temp.sc, 0);
1939
1940 if (temp.auto_data_toggle) {
1941
1942 /* let the hardware compute the data toggle */
1943
1944 qh->qh_endp &= htohc32(temp.sc, ~EHCI_QH_DTC);
1945
1946 if (xfer->endpoint->toggle_next) {
1947 /* DATA1 is next */
1948 qh->qh_qtd.qtd_status |=
1949 htohc32(temp.sc, EHCI_QTD_SET_TOGGLE(1));
1950 }
1951 }
1952 td = xfer->td_transfer_first;
1953
1954 qh->qh_qtd.qtd_next = td->qtd_self;
1955 qh->qh_qtd.qtd_altnext =
1956 htohc32(temp.sc, EHCI_LINK_TERMINATE);
1957
1931 EHCI_QH_SET_HUBA(xfer->xroot->udev->hs_hub_addr) |
1932 EHCI_QH_SET_PORT(xfer->xroot->udev->hs_port_no));
1933
1934 qh->qh_endphub = htohc32(temp.sc, qh_endphub);
1935 qh->qh_curqtd = htohc32(temp.sc, 0);
1936
1937 /* fill the overlay qTD */
1938 qh->qh_qtd.qtd_status = htohc32(temp.sc, 0);
1939
1940 if (temp.auto_data_toggle) {
1941
1942 /* let the hardware compute the data toggle */
1943
1944 qh->qh_endp &= htohc32(temp.sc, ~EHCI_QH_DTC);
1945
1946 if (xfer->endpoint->toggle_next) {
1947 /* DATA1 is next */
1948 qh->qh_qtd.qtd_status |=
1949 htohc32(temp.sc, EHCI_QTD_SET_TOGGLE(1));
1950 }
1951 }
1952 td = xfer->td_transfer_first;
1953
1954 qh->qh_qtd.qtd_next = td->qtd_self;
1955 qh->qh_qtd.qtd_altnext =
1956 htohc32(temp.sc, EHCI_LINK_TERMINATE);
1957
1958 usb2_pc_cpu_flush(qh->page_cache);
1958 usb_pc_cpu_flush(qh->page_cache);
1959
1960 if (xfer->xroot->udev->flags.self_suspended == 0) {
1961 EHCI_APPEND_QH(qh, *qh_last);
1962 }
1963}
1964
1965static void
1966ehci_root_intr(ehci_softc_t *sc)
1967{
1968 uint16_t i;
1969 uint16_t m;
1970
1971 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
1972
1973 /* clear any old interrupt data */
1974 memset(sc->sc_hub_idata, 0, sizeof(sc->sc_hub_idata));
1975
1976 /* set bits */
1977 m = (sc->sc_noport + 1);
1978 if (m > (8 * sizeof(sc->sc_hub_idata))) {
1979 m = (8 * sizeof(sc->sc_hub_idata));
1980 }
1981 for (i = 1; i < m; i++) {
1982 /* pick out CHANGE bits from the status register */
1983 if (EOREAD4(sc, EHCI_PORTSC(i)) & EHCI_PS_CLEAR) {
1984 sc->sc_hub_idata[i / 8] |= 1 << (i % 8);
1985 DPRINTF("port %d changed\n", i);
1986 }
1987 }
1988 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata,
1989 sizeof(sc->sc_hub_idata));
1990}
1991
1992static void
1993ehci_isoc_fs_done(ehci_softc_t *sc, struct usb_xfer *xfer)
1994{
1995 uint32_t nframes = xfer->nframes;
1996 uint32_t status;
1997 uint32_t *plen = xfer->frlengths;
1998 uint16_t len = 0;
1999 ehci_sitd_t *td = xfer->td_transfer_first;
2000 ehci_sitd_t **pp_last = &sc->sc_isoc_fs_p_last[xfer->qh_pos];
2001
2002 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n",
2003 xfer, xfer->endpoint);
2004
2005 while (nframes--) {
2006 if (td == NULL) {
2007 panic("%s:%d: out of TD's\n",
2008 __FUNCTION__, __LINE__);
2009 }
2010 if (pp_last >= &sc->sc_isoc_fs_p_last[EHCI_VIRTUAL_FRAMELIST_COUNT]) {
2011 pp_last = &sc->sc_isoc_fs_p_last[0];
2012 }
2013#if USB_DEBUG
2014 if (ehcidebug > 15) {
2015 DPRINTF("isoc FS-TD\n");
2016 ehci_dump_sitd(sc, td);
2017 }
2018#endif
1959
1960 if (xfer->xroot->udev->flags.self_suspended == 0) {
1961 EHCI_APPEND_QH(qh, *qh_last);
1962 }
1963}
1964
1965static void
1966ehci_root_intr(ehci_softc_t *sc)
1967{
1968 uint16_t i;
1969 uint16_t m;
1970
1971 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
1972
1973 /* clear any old interrupt data */
1974 memset(sc->sc_hub_idata, 0, sizeof(sc->sc_hub_idata));
1975
1976 /* set bits */
1977 m = (sc->sc_noport + 1);
1978 if (m > (8 * sizeof(sc->sc_hub_idata))) {
1979 m = (8 * sizeof(sc->sc_hub_idata));
1980 }
1981 for (i = 1; i < m; i++) {
1982 /* pick out CHANGE bits from the status register */
1983 if (EOREAD4(sc, EHCI_PORTSC(i)) & EHCI_PS_CLEAR) {
1984 sc->sc_hub_idata[i / 8] |= 1 << (i % 8);
1985 DPRINTF("port %d changed\n", i);
1986 }
1987 }
1988 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata,
1989 sizeof(sc->sc_hub_idata));
1990}
1991
1992static void
1993ehci_isoc_fs_done(ehci_softc_t *sc, struct usb_xfer *xfer)
1994{
1995 uint32_t nframes = xfer->nframes;
1996 uint32_t status;
1997 uint32_t *plen = xfer->frlengths;
1998 uint16_t len = 0;
1999 ehci_sitd_t *td = xfer->td_transfer_first;
2000 ehci_sitd_t **pp_last = &sc->sc_isoc_fs_p_last[xfer->qh_pos];
2001
2002 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n",
2003 xfer, xfer->endpoint);
2004
2005 while (nframes--) {
2006 if (td == NULL) {
2007 panic("%s:%d: out of TD's\n",
2008 __FUNCTION__, __LINE__);
2009 }
2010 if (pp_last >= &sc->sc_isoc_fs_p_last[EHCI_VIRTUAL_FRAMELIST_COUNT]) {
2011 pp_last = &sc->sc_isoc_fs_p_last[0];
2012 }
2013#if USB_DEBUG
2014 if (ehcidebug > 15) {
2015 DPRINTF("isoc FS-TD\n");
2016 ehci_dump_sitd(sc, td);
2017 }
2018#endif
2019 usb2_pc_cpu_invalidate(td->page_cache);
2019 usb_pc_cpu_invalidate(td->page_cache);
2020 status = hc32toh(sc, td->sitd_status);
2021
2022 len = EHCI_SITD_GET_LEN(status);
2023
2024 DPRINTFN(2, "status=0x%08x, rem=%u\n", status, len);
2025
2026 if (*plen >= len) {
2027 len = *plen - len;
2028 } else {
2029 len = 0;
2030 }
2031
2032 *plen = len;
2033
2034 /* remove FS-TD from schedule */
2035 EHCI_REMOVE_FS_TD(td, *pp_last);
2036
2037 pp_last++;
2038 plen++;
2039 td = td->obj_next;
2040 }
2041
2042 xfer->aframes = xfer->nframes;
2043}
2044
2045static void
2046ehci_isoc_hs_done(ehci_softc_t *sc, struct usb_xfer *xfer)
2047{
2048 uint32_t nframes = xfer->nframes;
2049 uint32_t status;
2050 uint32_t *plen = xfer->frlengths;
2051 uint16_t len = 0;
2052 uint8_t td_no = 0;
2053 ehci_itd_t *td = xfer->td_transfer_first;
2054 ehci_itd_t **pp_last = &sc->sc_isoc_hs_p_last[xfer->qh_pos];
2055
2056 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n",
2057 xfer, xfer->endpoint);
2058
2059 while (nframes--) {
2060 if (td == NULL) {
2061 panic("%s:%d: out of TD's\n",
2062 __FUNCTION__, __LINE__);
2063 }
2064 if (pp_last >= &sc->sc_isoc_hs_p_last[EHCI_VIRTUAL_FRAMELIST_COUNT]) {
2065 pp_last = &sc->sc_isoc_hs_p_last[0];
2066 }
2067#if USB_DEBUG
2068 if (ehcidebug > 15) {
2069 DPRINTF("isoc HS-TD\n");
2070 ehci_dump_itd(sc, td);
2071 }
2072#endif
2073
2020 status = hc32toh(sc, td->sitd_status);
2021
2022 len = EHCI_SITD_GET_LEN(status);
2023
2024 DPRINTFN(2, "status=0x%08x, rem=%u\n", status, len);
2025
2026 if (*plen >= len) {
2027 len = *plen - len;
2028 } else {
2029 len = 0;
2030 }
2031
2032 *plen = len;
2033
2034 /* remove FS-TD from schedule */
2035 EHCI_REMOVE_FS_TD(td, *pp_last);
2036
2037 pp_last++;
2038 plen++;
2039 td = td->obj_next;
2040 }
2041
2042 xfer->aframes = xfer->nframes;
2043}
2044
2045static void
2046ehci_isoc_hs_done(ehci_softc_t *sc, struct usb_xfer *xfer)
2047{
2048 uint32_t nframes = xfer->nframes;
2049 uint32_t status;
2050 uint32_t *plen = xfer->frlengths;
2051 uint16_t len = 0;
2052 uint8_t td_no = 0;
2053 ehci_itd_t *td = xfer->td_transfer_first;
2054 ehci_itd_t **pp_last = &sc->sc_isoc_hs_p_last[xfer->qh_pos];
2055
2056 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n",
2057 xfer, xfer->endpoint);
2058
2059 while (nframes--) {
2060 if (td == NULL) {
2061 panic("%s:%d: out of TD's\n",
2062 __FUNCTION__, __LINE__);
2063 }
2064 if (pp_last >= &sc->sc_isoc_hs_p_last[EHCI_VIRTUAL_FRAMELIST_COUNT]) {
2065 pp_last = &sc->sc_isoc_hs_p_last[0];
2066 }
2067#if USB_DEBUG
2068 if (ehcidebug > 15) {
2069 DPRINTF("isoc HS-TD\n");
2070 ehci_dump_itd(sc, td);
2071 }
2072#endif
2073
2074 usb2_pc_cpu_invalidate(td->page_cache);
2074 usb_pc_cpu_invalidate(td->page_cache);
2075 status = hc32toh(sc, td->itd_status[td_no]);
2076
2077 len = EHCI_ITD_GET_LEN(status);
2078
2079 DPRINTFN(2, "status=0x%08x, len=%u\n", status, len);
2080
2081 if (*plen >= len) {
2082 /*
2083 * The length is valid. NOTE: The complete
2084 * length is written back into the status
2085 * field, and not the remainder like with
2086 * other transfer descriptor types.
2087 */
2088 } else {
2089 /* Invalid length - truncate */
2090 len = 0;
2091 }
2092
2093 *plen = len;
2094
2095 plen++;
2096 td_no++;
2097
2098 if ((td_no == 8) || (nframes == 0)) {
2099 /* remove HS-TD from schedule */
2100 EHCI_REMOVE_HS_TD(td, *pp_last);
2101 pp_last++;
2102
2103 td_no = 0;
2104 td = td->obj_next;
2105 }
2106 }
2107 xfer->aframes = xfer->nframes;
2108}
2109
2110/* NOTE: "done" can be run two times in a row,
2111 * from close and from interrupt
2112 */
2113static void
2114ehci_device_done(struct usb_xfer *xfer, usb_error_t error)
2115{
2116 struct usb_pipe_methods *methods = xfer->endpoint->methods;
2117 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
2118
2119 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
2120
2121 DPRINTFN(2, "xfer=%p, endpoint=%p, error=%d\n",
2122 xfer, xfer->endpoint, error);
2123
2124 if ((methods == &ehci_device_bulk_methods) ||
2125 (methods == &ehci_device_ctrl_methods)) {
2126#if USB_DEBUG
2127 if (ehcidebug > 8) {
2128 DPRINTF("nexttog=%d; data after transfer:\n",
2129 xfer->endpoint->toggle_next);
2130 ehci_dump_sqtds(sc,
2131 xfer->td_transfer_first);
2132 }
2133#endif
2134
2135 EHCI_REMOVE_QH(xfer->qh_start[xfer->flags_int.curr_dma_set],
2136 sc->sc_async_p_last);
2137 }
2138 if (methods == &ehci_device_intr_methods) {
2139 EHCI_REMOVE_QH(xfer->qh_start[xfer->flags_int.curr_dma_set],
2140 sc->sc_intr_p_last[xfer->qh_pos]);
2141 }
2142 /*
2143 * Only finish isochronous transfers once which will update
2144 * "xfer->frlengths".
2145 */
2146 if (xfer->td_transfer_first &&
2147 xfer->td_transfer_last) {
2148 if (methods == &ehci_device_isoc_fs_methods) {
2149 ehci_isoc_fs_done(sc, xfer);
2150 }
2151 if (methods == &ehci_device_isoc_hs_methods) {
2152 ehci_isoc_hs_done(sc, xfer);
2153 }
2154 xfer->td_transfer_first = NULL;
2155 xfer->td_transfer_last = NULL;
2156 }
2157 /* dequeue transfer and start next transfer */
2075 status = hc32toh(sc, td->itd_status[td_no]);
2076
2077 len = EHCI_ITD_GET_LEN(status);
2078
2079 DPRINTFN(2, "status=0x%08x, len=%u\n", status, len);
2080
2081 if (*plen >= len) {
2082 /*
2083 * The length is valid. NOTE: The complete
2084 * length is written back into the status
2085 * field, and not the remainder like with
2086 * other transfer descriptor types.
2087 */
2088 } else {
2089 /* Invalid length - truncate */
2090 len = 0;
2091 }
2092
2093 *plen = len;
2094
2095 plen++;
2096 td_no++;
2097
2098 if ((td_no == 8) || (nframes == 0)) {
2099 /* remove HS-TD from schedule */
2100 EHCI_REMOVE_HS_TD(td, *pp_last);
2101 pp_last++;
2102
2103 td_no = 0;
2104 td = td->obj_next;
2105 }
2106 }
2107 xfer->aframes = xfer->nframes;
2108}
2109
2110/* NOTE: "done" can be run two times in a row,
2111 * from close and from interrupt
2112 */
2113static void
2114ehci_device_done(struct usb_xfer *xfer, usb_error_t error)
2115{
2116 struct usb_pipe_methods *methods = xfer->endpoint->methods;
2117 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
2118
2119 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
2120
2121 DPRINTFN(2, "xfer=%p, endpoint=%p, error=%d\n",
2122 xfer, xfer->endpoint, error);
2123
2124 if ((methods == &ehci_device_bulk_methods) ||
2125 (methods == &ehci_device_ctrl_methods)) {
2126#if USB_DEBUG
2127 if (ehcidebug > 8) {
2128 DPRINTF("nexttog=%d; data after transfer:\n",
2129 xfer->endpoint->toggle_next);
2130 ehci_dump_sqtds(sc,
2131 xfer->td_transfer_first);
2132 }
2133#endif
2134
2135 EHCI_REMOVE_QH(xfer->qh_start[xfer->flags_int.curr_dma_set],
2136 sc->sc_async_p_last);
2137 }
2138 if (methods == &ehci_device_intr_methods) {
2139 EHCI_REMOVE_QH(xfer->qh_start[xfer->flags_int.curr_dma_set],
2140 sc->sc_intr_p_last[xfer->qh_pos]);
2141 }
2142 /*
2143 * Only finish isochronous transfers once which will update
2144 * "xfer->frlengths".
2145 */
2146 if (xfer->td_transfer_first &&
2147 xfer->td_transfer_last) {
2148 if (methods == &ehci_device_isoc_fs_methods) {
2149 ehci_isoc_fs_done(sc, xfer);
2150 }
2151 if (methods == &ehci_device_isoc_hs_methods) {
2152 ehci_isoc_hs_done(sc, xfer);
2153 }
2154 xfer->td_transfer_first = NULL;
2155 xfer->td_transfer_last = NULL;
2156 }
2157 /* dequeue transfer and start next transfer */
2158 usb2_transfer_done(xfer, error);
2158 usbd_transfer_done(xfer, error);
2159}
2160
2161/*------------------------------------------------------------------------*
2162 * ehci bulk support
2163 *------------------------------------------------------------------------*/
2164static void
2165ehci_device_bulk_open(struct usb_xfer *xfer)
2166{
2167 return;
2168}
2169
2170static void
2171ehci_device_bulk_close(struct usb_xfer *xfer)
2172{
2173 ehci_device_done(xfer, USB_ERR_CANCELLED);
2174}
2175
2176static void
2177ehci_device_bulk_enter(struct usb_xfer *xfer)
2178{
2179 return;
2180}
2181
2182static void
2183ehci_device_bulk_start(struct usb_xfer *xfer)
2184{
2185 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
2186 uint32_t temp;
2187
2188 /* setup TD's and QH */
2189 ehci_setup_standard_chain(xfer, &sc->sc_async_p_last);
2190
2191 /* put transfer on interrupt queue */
2192 ehci_transfer_intr_enqueue(xfer);
2193
2194 /* XXX Performance quirk: Some Host Controllers have a too low
2195 * interrupt rate. Issue an IAAD to stimulate the Host
2196 * Controller after queueing the BULK transfer.
2197 */
2198 temp = EOREAD4(sc, EHCI_USBCMD);
2199 if (!(temp & EHCI_CMD_IAAD))
2200 EOWRITE4(sc, EHCI_USBCMD, temp | EHCI_CMD_IAAD);
2201}
2202
2203struct usb_pipe_methods ehci_device_bulk_methods =
2204{
2205 .open = ehci_device_bulk_open,
2206 .close = ehci_device_bulk_close,
2207 .enter = ehci_device_bulk_enter,
2208 .start = ehci_device_bulk_start,
2209};
2210
2211/*------------------------------------------------------------------------*
2212 * ehci control support
2213 *------------------------------------------------------------------------*/
2214static void
2215ehci_device_ctrl_open(struct usb_xfer *xfer)
2216{
2217 return;
2218}
2219
2220static void
2221ehci_device_ctrl_close(struct usb_xfer *xfer)
2222{
2223 ehci_device_done(xfer, USB_ERR_CANCELLED);
2224}
2225
2226static void
2227ehci_device_ctrl_enter(struct usb_xfer *xfer)
2228{
2229 return;
2230}
2231
2232static void
2233ehci_device_ctrl_start(struct usb_xfer *xfer)
2234{
2235 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
2236
2237 /* setup TD's and QH */
2238 ehci_setup_standard_chain(xfer, &sc->sc_async_p_last);
2239
2240 /* put transfer on interrupt queue */
2241 ehci_transfer_intr_enqueue(xfer);
2242}
2243
2244struct usb_pipe_methods ehci_device_ctrl_methods =
2245{
2246 .open = ehci_device_ctrl_open,
2247 .close = ehci_device_ctrl_close,
2248 .enter = ehci_device_ctrl_enter,
2249 .start = ehci_device_ctrl_start,
2250};
2251
2252/*------------------------------------------------------------------------*
2253 * ehci interrupt support
2254 *------------------------------------------------------------------------*/
2255static void
2256ehci_device_intr_open(struct usb_xfer *xfer)
2257{
2258 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
2259 uint16_t best;
2260 uint16_t bit;
2261 uint16_t x;
2262 uint8_t slot;
2263
2264 /* Allocate a microframe slot first: */
2265
2159}
2160
2161/*------------------------------------------------------------------------*
2162 * ehci bulk support
2163 *------------------------------------------------------------------------*/
2164static void
2165ehci_device_bulk_open(struct usb_xfer *xfer)
2166{
2167 return;
2168}
2169
2170static void
2171ehci_device_bulk_close(struct usb_xfer *xfer)
2172{
2173 ehci_device_done(xfer, USB_ERR_CANCELLED);
2174}
2175
2176static void
2177ehci_device_bulk_enter(struct usb_xfer *xfer)
2178{
2179 return;
2180}
2181
2182static void
2183ehci_device_bulk_start(struct usb_xfer *xfer)
2184{
2185 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
2186 uint32_t temp;
2187
2188 /* setup TD's and QH */
2189 ehci_setup_standard_chain(xfer, &sc->sc_async_p_last);
2190
2191 /* put transfer on interrupt queue */
2192 ehci_transfer_intr_enqueue(xfer);
2193
2194 /* XXX Performance quirk: Some Host Controllers have a too low
2195 * interrupt rate. Issue an IAAD to stimulate the Host
2196 * Controller after queueing the BULK transfer.
2197 */
2198 temp = EOREAD4(sc, EHCI_USBCMD);
2199 if (!(temp & EHCI_CMD_IAAD))
2200 EOWRITE4(sc, EHCI_USBCMD, temp | EHCI_CMD_IAAD);
2201}
2202
2203struct usb_pipe_methods ehci_device_bulk_methods =
2204{
2205 .open = ehci_device_bulk_open,
2206 .close = ehci_device_bulk_close,
2207 .enter = ehci_device_bulk_enter,
2208 .start = ehci_device_bulk_start,
2209};
2210
2211/*------------------------------------------------------------------------*
2212 * ehci control support
2213 *------------------------------------------------------------------------*/
2214static void
2215ehci_device_ctrl_open(struct usb_xfer *xfer)
2216{
2217 return;
2218}
2219
2220static void
2221ehci_device_ctrl_close(struct usb_xfer *xfer)
2222{
2223 ehci_device_done(xfer, USB_ERR_CANCELLED);
2224}
2225
2226static void
2227ehci_device_ctrl_enter(struct usb_xfer *xfer)
2228{
2229 return;
2230}
2231
2232static void
2233ehci_device_ctrl_start(struct usb_xfer *xfer)
2234{
2235 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
2236
2237 /* setup TD's and QH */
2238 ehci_setup_standard_chain(xfer, &sc->sc_async_p_last);
2239
2240 /* put transfer on interrupt queue */
2241 ehci_transfer_intr_enqueue(xfer);
2242}
2243
2244struct usb_pipe_methods ehci_device_ctrl_methods =
2245{
2246 .open = ehci_device_ctrl_open,
2247 .close = ehci_device_ctrl_close,
2248 .enter = ehci_device_ctrl_enter,
2249 .start = ehci_device_ctrl_start,
2250};
2251
2252/*------------------------------------------------------------------------*
2253 * ehci interrupt support
2254 *------------------------------------------------------------------------*/
2255static void
2256ehci_device_intr_open(struct usb_xfer *xfer)
2257{
2258 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
2259 uint16_t best;
2260 uint16_t bit;
2261 uint16_t x;
2262 uint8_t slot;
2263
2264 /* Allocate a microframe slot first: */
2265
2266 slot = usb2_intr_schedule_adjust
2266 slot = usb_intr_schedule_adjust
2267 (xfer->xroot->udev, xfer->max_frame_size, USB_HS_MICRO_FRAMES_MAX);
2268
2267 (xfer->xroot->udev, xfer->max_frame_size, USB_HS_MICRO_FRAMES_MAX);
2268
2269 if (usb2_get_speed(xfer->xroot->udev) == USB_SPEED_HIGH) {
2270 xfer->usb2_uframe = slot;
2271 xfer->usb2_smask = (1 << slot) & 0xFF;
2272 xfer->usb2_cmask = 0;
2269 if (usbd_get_speed(xfer->xroot->udev) == USB_SPEED_HIGH) {
2270 xfer->usb_uframe = slot;
2271 xfer->usb_smask = (1 << slot) & 0xFF;
2272 xfer->usb_cmask = 0;
2273 } else {
2273 } else {
2274 xfer->usb2_uframe = slot;
2275 xfer->usb2_smask = (1 << slot) & 0x3F;
2276 xfer->usb2_cmask = (-(4 << slot)) & 0xFE;
2274 xfer->usb_uframe = slot;
2275 xfer->usb_smask = (1 << slot) & 0x3F;
2276 xfer->usb_cmask = (-(4 << slot)) & 0xFE;
2277 }
2278
2279 /*
2280 * Find the best QH position corresponding to the given interval:
2281 */
2282
2283 best = 0;
2284 bit = EHCI_VIRTUAL_FRAMELIST_COUNT / 2;
2285 while (bit) {
2286 if (xfer->interval >= bit) {
2287 x = bit;
2288 best = bit;
2289 while (x & bit) {
2290 if (sc->sc_intr_stat[x] <
2291 sc->sc_intr_stat[best]) {
2292 best = x;
2293 }
2294 x++;
2295 }
2296 break;
2297 }
2298 bit >>= 1;
2299 }
2300
2301 sc->sc_intr_stat[best]++;
2302 xfer->qh_pos = best;
2303
2304 DPRINTFN(3, "best=%d interval=%d\n",
2305 best, xfer->interval);
2306}
2307
2308static void
2309ehci_device_intr_close(struct usb_xfer *xfer)
2310{
2311 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
2312 uint8_t slot;
2313
2277 }
2278
2279 /*
2280 * Find the best QH position corresponding to the given interval:
2281 */
2282
2283 best = 0;
2284 bit = EHCI_VIRTUAL_FRAMELIST_COUNT / 2;
2285 while (bit) {
2286 if (xfer->interval >= bit) {
2287 x = bit;
2288 best = bit;
2289 while (x & bit) {
2290 if (sc->sc_intr_stat[x] <
2291 sc->sc_intr_stat[best]) {
2292 best = x;
2293 }
2294 x++;
2295 }
2296 break;
2297 }
2298 bit >>= 1;
2299 }
2300
2301 sc->sc_intr_stat[best]++;
2302 xfer->qh_pos = best;
2303
2304 DPRINTFN(3, "best=%d interval=%d\n",
2305 best, xfer->interval);
2306}
2307
2308static void
2309ehci_device_intr_close(struct usb_xfer *xfer)
2310{
2311 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
2312 uint8_t slot;
2313
2314 slot = usb2_intr_schedule_adjust
2315 (xfer->xroot->udev, -(xfer->max_frame_size), xfer->usb2_uframe);
2314 slot = usb_intr_schedule_adjust
2315 (xfer->xroot->udev, -(xfer->max_frame_size), xfer->usb_uframe);
2316
2317 sc->sc_intr_stat[xfer->qh_pos]--;
2318
2319 ehci_device_done(xfer, USB_ERR_CANCELLED);
2320}
2321
2322static void
2323ehci_device_intr_enter(struct usb_xfer *xfer)
2324{
2325 return;
2326}
2327
2328static void
2329ehci_device_intr_start(struct usb_xfer *xfer)
2330{
2331 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
2332
2333 /* setup TD's and QH */
2334 ehci_setup_standard_chain(xfer, &sc->sc_intr_p_last[xfer->qh_pos]);
2335
2336 /* put transfer on interrupt queue */
2337 ehci_transfer_intr_enqueue(xfer);
2338}
2339
2340struct usb_pipe_methods ehci_device_intr_methods =
2341{
2342 .open = ehci_device_intr_open,
2343 .close = ehci_device_intr_close,
2344 .enter = ehci_device_intr_enter,
2345 .start = ehci_device_intr_start,
2346};
2347
2348/*------------------------------------------------------------------------*
2349 * ehci full speed isochronous support
2350 *------------------------------------------------------------------------*/
2351static void
2352ehci_device_isoc_fs_open(struct usb_xfer *xfer)
2353{
2354 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
2355 ehci_sitd_t *td;
2356 uint32_t sitd_portaddr;
2357 uint8_t ds;
2358
2359 sitd_portaddr =
2360 EHCI_SITD_SET_ADDR(xfer->address) |
2361 EHCI_SITD_SET_ENDPT(UE_GET_ADDR(xfer->endpointno)) |
2362 EHCI_SITD_SET_HUBA(xfer->xroot->udev->hs_hub_addr) |
2363 EHCI_SITD_SET_PORT(xfer->xroot->udev->hs_port_no);
2364
2365 if (UE_GET_DIR(xfer->endpointno) == UE_DIR_IN) {
2366 sitd_portaddr |= EHCI_SITD_SET_DIR_IN;
2367 }
2368 sitd_portaddr = htohc32(sc, sitd_portaddr);
2369
2370 /* initialize all TD's */
2371
2372 for (ds = 0; ds != 2; ds++) {
2373
2374 for (td = xfer->td_start[ds]; td; td = td->obj_next) {
2375
2376 td->sitd_portaddr = sitd_portaddr;
2377
2378 /*
2379 * TODO: make some kind of automatic
2380 * SMASK/CMASK selection based on micro-frame
2381 * usage
2382 *
2383 * micro-frame usage (8 microframes per 1ms)
2384 */
2385 td->sitd_back = htohc32(sc, EHCI_LINK_TERMINATE);
2386
2316
2317 sc->sc_intr_stat[xfer->qh_pos]--;
2318
2319 ehci_device_done(xfer, USB_ERR_CANCELLED);
2320}
2321
2322static void
2323ehci_device_intr_enter(struct usb_xfer *xfer)
2324{
2325 return;
2326}
2327
2328static void
2329ehci_device_intr_start(struct usb_xfer *xfer)
2330{
2331 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
2332
2333 /* setup TD's and QH */
2334 ehci_setup_standard_chain(xfer, &sc->sc_intr_p_last[xfer->qh_pos]);
2335
2336 /* put transfer on interrupt queue */
2337 ehci_transfer_intr_enqueue(xfer);
2338}
2339
2340struct usb_pipe_methods ehci_device_intr_methods =
2341{
2342 .open = ehci_device_intr_open,
2343 .close = ehci_device_intr_close,
2344 .enter = ehci_device_intr_enter,
2345 .start = ehci_device_intr_start,
2346};
2347
2348/*------------------------------------------------------------------------*
2349 * ehci full speed isochronous support
2350 *------------------------------------------------------------------------*/
2351static void
2352ehci_device_isoc_fs_open(struct usb_xfer *xfer)
2353{
2354 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
2355 ehci_sitd_t *td;
2356 uint32_t sitd_portaddr;
2357 uint8_t ds;
2358
2359 sitd_portaddr =
2360 EHCI_SITD_SET_ADDR(xfer->address) |
2361 EHCI_SITD_SET_ENDPT(UE_GET_ADDR(xfer->endpointno)) |
2362 EHCI_SITD_SET_HUBA(xfer->xroot->udev->hs_hub_addr) |
2363 EHCI_SITD_SET_PORT(xfer->xroot->udev->hs_port_no);
2364
2365 if (UE_GET_DIR(xfer->endpointno) == UE_DIR_IN) {
2366 sitd_portaddr |= EHCI_SITD_SET_DIR_IN;
2367 }
2368 sitd_portaddr = htohc32(sc, sitd_portaddr);
2369
2370 /* initialize all TD's */
2371
2372 for (ds = 0; ds != 2; ds++) {
2373
2374 for (td = xfer->td_start[ds]; td; td = td->obj_next) {
2375
2376 td->sitd_portaddr = sitd_portaddr;
2377
2378 /*
2379 * TODO: make some kind of automatic
2380 * SMASK/CMASK selection based on micro-frame
2381 * usage
2382 *
2383 * micro-frame usage (8 microframes per 1ms)
2384 */
2385 td->sitd_back = htohc32(sc, EHCI_LINK_TERMINATE);
2386
2387 usb2_pc_cpu_flush(td->page_cache);
2387 usb_pc_cpu_flush(td->page_cache);
2388 }
2389 }
2390}
2391
2392static void
2393ehci_device_isoc_fs_close(struct usb_xfer *xfer)
2394{
2395 ehci_device_done(xfer, USB_ERR_CANCELLED);
2396}
2397
2398static void
2399ehci_device_isoc_fs_enter(struct usb_xfer *xfer)
2400{
2401 struct usb_page_search buf_res;
2402 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
2403 struct usb_fs_isoc_schedule *fss_start;
2404 struct usb_fs_isoc_schedule *fss_end;
2405 struct usb_fs_isoc_schedule *fss;
2406 ehci_sitd_t *td;
2407 ehci_sitd_t *td_last = NULL;
2408 ehci_sitd_t **pp_last;
2409 uint32_t *plen;
2410 uint32_t buf_offset;
2411 uint32_t nframes;
2412 uint32_t temp;
2413 uint32_t sitd_mask;
2414 uint16_t tlen;
2415 uint8_t sa;
2416 uint8_t sb;
2417 uint8_t error;
2418
2419#if USB_DEBUG
2420 uint8_t once = 1;
2421
2422#endif
2423
2424 DPRINTFN(6, "xfer=%p next=%d nframes=%d\n",
2425 xfer, xfer->endpoint->isoc_next, xfer->nframes);
2426
2427 /* get the current frame index */
2428
2429 nframes = EOREAD4(sc, EHCI_FRINDEX) / 8;
2430
2431 /*
2432 * check if the frame index is within the window where the frames
2433 * will be inserted
2434 */
2435 buf_offset = (nframes - xfer->endpoint->isoc_next) &
2436 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1);
2437
2438 if ((xfer->endpoint->is_synced == 0) ||
2439 (buf_offset < xfer->nframes)) {
2440 /*
2441 * If there is data underflow or the pipe queue is empty we
2442 * schedule the transfer a few frames ahead of the current
2443 * frame position. Else two isochronous transfers might
2444 * overlap.
2445 */
2446 xfer->endpoint->isoc_next = (nframes + 3) &
2447 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1);
2448 xfer->endpoint->is_synced = 1;
2449 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next);
2450 }
2451 /*
2452 * compute how many milliseconds the insertion is ahead of the
2453 * current frame position:
2454 */
2455 buf_offset = (xfer->endpoint->isoc_next - nframes) &
2456 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1);
2457
2458 /*
2459 * pre-compute when the isochronous transfer will be finished:
2460 */
2461 xfer->isoc_time_complete =
2388 }
2389 }
2390}
2391
2392static void
2393ehci_device_isoc_fs_close(struct usb_xfer *xfer)
2394{
2395 ehci_device_done(xfer, USB_ERR_CANCELLED);
2396}
2397
2398static void
2399ehci_device_isoc_fs_enter(struct usb_xfer *xfer)
2400{
2401 struct usb_page_search buf_res;
2402 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
2403 struct usb_fs_isoc_schedule *fss_start;
2404 struct usb_fs_isoc_schedule *fss_end;
2405 struct usb_fs_isoc_schedule *fss;
2406 ehci_sitd_t *td;
2407 ehci_sitd_t *td_last = NULL;
2408 ehci_sitd_t **pp_last;
2409 uint32_t *plen;
2410 uint32_t buf_offset;
2411 uint32_t nframes;
2412 uint32_t temp;
2413 uint32_t sitd_mask;
2414 uint16_t tlen;
2415 uint8_t sa;
2416 uint8_t sb;
2417 uint8_t error;
2418
2419#if USB_DEBUG
2420 uint8_t once = 1;
2421
2422#endif
2423
2424 DPRINTFN(6, "xfer=%p next=%d nframes=%d\n",
2425 xfer, xfer->endpoint->isoc_next, xfer->nframes);
2426
2427 /* get the current frame index */
2428
2429 nframes = EOREAD4(sc, EHCI_FRINDEX) / 8;
2430
2431 /*
2432 * check if the frame index is within the window where the frames
2433 * will be inserted
2434 */
2435 buf_offset = (nframes - xfer->endpoint->isoc_next) &
2436 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1);
2437
2438 if ((xfer->endpoint->is_synced == 0) ||
2439 (buf_offset < xfer->nframes)) {
2440 /*
2441 * If there is data underflow or the pipe queue is empty we
2442 * schedule the transfer a few frames ahead of the current
2443 * frame position. Else two isochronous transfers might
2444 * overlap.
2445 */
2446 xfer->endpoint->isoc_next = (nframes + 3) &
2447 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1);
2448 xfer->endpoint->is_synced = 1;
2449 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next);
2450 }
2451 /*
2452 * compute how many milliseconds the insertion is ahead of the
2453 * current frame position:
2454 */
2455 buf_offset = (xfer->endpoint->isoc_next - nframes) &
2456 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1);
2457
2458 /*
2459 * pre-compute when the isochronous transfer will be finished:
2460 */
2461 xfer->isoc_time_complete =
2462 usb2_fs_isoc_schedule_isoc_time_expand
2462 usbd_fs_isoc_schedule_isoc_time_expand
2463 (xfer->xroot->udev, &fss_start, &fss_end, nframes) + buf_offset +
2464 xfer->nframes;
2465
2466 /* get the real number of frames */
2467
2468 nframes = xfer->nframes;
2469
2470 buf_offset = 0;
2471
2472 plen = xfer->frlengths;
2473
2474 /* toggle the DMA set we are using */
2475 xfer->flags_int.curr_dma_set ^= 1;
2476
2477 /* get next DMA set */
2478 td = xfer->td_start[xfer->flags_int.curr_dma_set];
2479 xfer->td_transfer_first = td;
2480
2481 pp_last = &sc->sc_isoc_fs_p_last[xfer->endpoint->isoc_next];
2482
2483 /* store starting position */
2484
2485 xfer->qh_pos = xfer->endpoint->isoc_next;
2486
2487 fss = fss_start + (xfer->qh_pos % USB_ISOC_TIME_MAX);
2488
2489 while (nframes--) {
2490 if (td == NULL) {
2491 panic("%s:%d: out of TD's\n",
2492 __FUNCTION__, __LINE__);
2493 }
2494 if (pp_last >= &sc->sc_isoc_fs_p_last[EHCI_VIRTUAL_FRAMELIST_COUNT]) {
2495 pp_last = &sc->sc_isoc_fs_p_last[0];
2496 }
2497 if (fss >= fss_end) {
2498 fss = fss_start;
2499 }
2500 /* reuse sitd_portaddr and sitd_back from last transfer */
2501
2502 if (*plen > xfer->max_frame_size) {
2503#if USB_DEBUG
2504 if (once) {
2505 once = 0;
2506 printf("%s: frame length(%d) exceeds %d "
2507 "bytes (frame truncated)\n",
2508 __FUNCTION__, *plen,
2509 xfer->max_frame_size);
2510 }
2511#endif
2512 *plen = xfer->max_frame_size;
2513 }
2514 /*
2515 * We currently don't care if the ISOCHRONOUS schedule is
2516 * full!
2517 */
2463 (xfer->xroot->udev, &fss_start, &fss_end, nframes) + buf_offset +
2464 xfer->nframes;
2465
2466 /* get the real number of frames */
2467
2468 nframes = xfer->nframes;
2469
2470 buf_offset = 0;
2471
2472 plen = xfer->frlengths;
2473
2474 /* toggle the DMA set we are using */
2475 xfer->flags_int.curr_dma_set ^= 1;
2476
2477 /* get next DMA set */
2478 td = xfer->td_start[xfer->flags_int.curr_dma_set];
2479 xfer->td_transfer_first = td;
2480
2481 pp_last = &sc->sc_isoc_fs_p_last[xfer->endpoint->isoc_next];
2482
2483 /* store starting position */
2484
2485 xfer->qh_pos = xfer->endpoint->isoc_next;
2486
2487 fss = fss_start + (xfer->qh_pos % USB_ISOC_TIME_MAX);
2488
2489 while (nframes--) {
2490 if (td == NULL) {
2491 panic("%s:%d: out of TD's\n",
2492 __FUNCTION__, __LINE__);
2493 }
2494 if (pp_last >= &sc->sc_isoc_fs_p_last[EHCI_VIRTUAL_FRAMELIST_COUNT]) {
2495 pp_last = &sc->sc_isoc_fs_p_last[0];
2496 }
2497 if (fss >= fss_end) {
2498 fss = fss_start;
2499 }
2500 /* reuse sitd_portaddr and sitd_back from last transfer */
2501
2502 if (*plen > xfer->max_frame_size) {
2503#if USB_DEBUG
2504 if (once) {
2505 once = 0;
2506 printf("%s: frame length(%d) exceeds %d "
2507 "bytes (frame truncated)\n",
2508 __FUNCTION__, *plen,
2509 xfer->max_frame_size);
2510 }
2511#endif
2512 *plen = xfer->max_frame_size;
2513 }
2514 /*
2515 * We currently don't care if the ISOCHRONOUS schedule is
2516 * full!
2517 */
2518 error = usb2_fs_isoc_schedule_alloc(fss, &sa, *plen);
2518 error = usbd_fs_isoc_schedule_alloc(fss, &sa, *plen);
2519 if (error) {
2520 /*
2521 * The FULL speed schedule is FULL! Set length
2522 * to zero.
2523 */
2524 *plen = 0;
2525 }
2526 if (*plen) {
2527 /*
2519 if (error) {
2520 /*
2521 * The FULL speed schedule is FULL! Set length
2522 * to zero.
2523 */
2524 *plen = 0;
2525 }
2526 if (*plen) {
2527 /*
2528 * only call "usb2_get_page()" when we have a
2528 * only call "usbd_get_page()" when we have a
2529 * non-zero length
2530 */
2529 * non-zero length
2530 */
2531 usb2_get_page(xfer->frbuffers, buf_offset, &buf_res);
2531 usbd_get_page(xfer->frbuffers, buf_offset, &buf_res);
2532 td->sitd_bp[0] = htohc32(sc, buf_res.physaddr);
2533 buf_offset += *plen;
2534 /*
2535 * NOTE: We need to subtract one from the offset so
2536 * that we are on a valid page!
2537 */
2532 td->sitd_bp[0] = htohc32(sc, buf_res.physaddr);
2533 buf_offset += *plen;
2534 /*
2535 * NOTE: We need to subtract one from the offset so
2536 * that we are on a valid page!
2537 */
2538 usb2_get_page(xfer->frbuffers, buf_offset - 1,
2538 usbd_get_page(xfer->frbuffers, buf_offset - 1,
2539 &buf_res);
2540 temp = buf_res.physaddr & ~0xFFF;
2541 } else {
2542 td->sitd_bp[0] = 0;
2543 temp = 0;
2544 }
2545
2546 if (UE_GET_DIR(xfer->endpointno) == UE_DIR_OUT) {
2547 tlen = *plen;
2548 if (tlen <= 188) {
2549 temp |= 1; /* T-count = 1, TP = ALL */
2550 tlen = 1;
2551 } else {
2552 tlen += 187;
2553 tlen /= 188;
2554 temp |= tlen; /* T-count = [1..6] */
2555 temp |= 8; /* TP = Begin */
2556 }
2557
2558 tlen += sa;
2559
2560 if (tlen >= 8) {
2561 sb = 0;
2562 } else {
2563 sb = (1 << tlen);
2564 }
2565
2566 sa = (1 << sa);
2567 sa = (sb - sa) & 0x3F;
2568 sb = 0;
2569 } else {
2570 sb = (-(4 << sa)) & 0xFE;
2571 sa = (1 << sa) & 0x3F;
2572 }
2573
2574 sitd_mask = (EHCI_SITD_SET_SMASK(sa) |
2575 EHCI_SITD_SET_CMASK(sb));
2576
2577 td->sitd_bp[1] = htohc32(sc, temp);
2578
2579 td->sitd_mask = htohc32(sc, sitd_mask);
2580
2581 if (nframes == 0) {
2582 td->sitd_status = htohc32(sc,
2583 EHCI_SITD_IOC |
2584 EHCI_SITD_ACTIVE |
2585 EHCI_SITD_SET_LEN(*plen));
2586 } else {
2587 td->sitd_status = htohc32(sc,
2588 EHCI_SITD_ACTIVE |
2589 EHCI_SITD_SET_LEN(*plen));
2590 }
2539 &buf_res);
2540 temp = buf_res.physaddr & ~0xFFF;
2541 } else {
2542 td->sitd_bp[0] = 0;
2543 temp = 0;
2544 }
2545
2546 if (UE_GET_DIR(xfer->endpointno) == UE_DIR_OUT) {
2547 tlen = *plen;
2548 if (tlen <= 188) {
2549 temp |= 1; /* T-count = 1, TP = ALL */
2550 tlen = 1;
2551 } else {
2552 tlen += 187;
2553 tlen /= 188;
2554 temp |= tlen; /* T-count = [1..6] */
2555 temp |= 8; /* TP = Begin */
2556 }
2557
2558 tlen += sa;
2559
2560 if (tlen >= 8) {
2561 sb = 0;
2562 } else {
2563 sb = (1 << tlen);
2564 }
2565
2566 sa = (1 << sa);
2567 sa = (sb - sa) & 0x3F;
2568 sb = 0;
2569 } else {
2570 sb = (-(4 << sa)) & 0xFE;
2571 sa = (1 << sa) & 0x3F;
2572 }
2573
2574 sitd_mask = (EHCI_SITD_SET_SMASK(sa) |
2575 EHCI_SITD_SET_CMASK(sb));
2576
2577 td->sitd_bp[1] = htohc32(sc, temp);
2578
2579 td->sitd_mask = htohc32(sc, sitd_mask);
2580
2581 if (nframes == 0) {
2582 td->sitd_status = htohc32(sc,
2583 EHCI_SITD_IOC |
2584 EHCI_SITD_ACTIVE |
2585 EHCI_SITD_SET_LEN(*plen));
2586 } else {
2587 td->sitd_status = htohc32(sc,
2588 EHCI_SITD_ACTIVE |
2589 EHCI_SITD_SET_LEN(*plen));
2590 }
2591 usb2_pc_cpu_flush(td->page_cache);
2591 usb_pc_cpu_flush(td->page_cache);
2592
2593#if USB_DEBUG
2594 if (ehcidebug > 15) {
2595 DPRINTF("FS-TD %d\n", nframes);
2596 ehci_dump_sitd(sc, td);
2597 }
2598#endif
2599 /* insert TD into schedule */
2600 EHCI_APPEND_FS_TD(td, *pp_last);
2601 pp_last++;
2602
2603 plen++;
2604 fss++;
2605 td_last = td;
2606 td = td->obj_next;
2607 }
2608
2609 xfer->td_transfer_last = td_last;
2610
2611 /* update isoc_next */
2612 xfer->endpoint->isoc_next = (pp_last - &sc->sc_isoc_fs_p_last[0]) &
2613 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1);
2614}
2615
2616static void
2617ehci_device_isoc_fs_start(struct usb_xfer *xfer)
2618{
2619 /* put transfer on interrupt queue */
2620 ehci_transfer_intr_enqueue(xfer);
2621}
2622
2623struct usb_pipe_methods ehci_device_isoc_fs_methods =
2624{
2625 .open = ehci_device_isoc_fs_open,
2626 .close = ehci_device_isoc_fs_close,
2627 .enter = ehci_device_isoc_fs_enter,
2628 .start = ehci_device_isoc_fs_start,
2629};
2630
2631/*------------------------------------------------------------------------*
2632 * ehci high speed isochronous support
2633 *------------------------------------------------------------------------*/
2634static void
2635ehci_device_isoc_hs_open(struct usb_xfer *xfer)
2636{
2637 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
2638 ehci_itd_t *td;
2639 uint32_t temp;
2640 uint8_t ds;
2641
2642 /* initialize all TD's */
2643
2644 for (ds = 0; ds != 2; ds++) {
2645
2646 for (td = xfer->td_start[ds]; td; td = td->obj_next) {
2647
2648 /* set TD inactive */
2649 td->itd_status[0] = 0;
2650 td->itd_status[1] = 0;
2651 td->itd_status[2] = 0;
2652 td->itd_status[3] = 0;
2653 td->itd_status[4] = 0;
2654 td->itd_status[5] = 0;
2655 td->itd_status[6] = 0;
2656 td->itd_status[7] = 0;
2657
2658 /* set endpoint and address */
2659 td->itd_bp[0] = htohc32(sc,
2660 EHCI_ITD_SET_ADDR(xfer->address) |
2661 EHCI_ITD_SET_ENDPT(UE_GET_ADDR(xfer->endpointno)));
2662
2663 temp =
2664 EHCI_ITD_SET_MPL(xfer->max_packet_size & 0x7FF);
2665
2666 /* set direction */
2667 if (UE_GET_DIR(xfer->endpointno) == UE_DIR_IN) {
2668 temp |= EHCI_ITD_SET_DIR_IN;
2669 }
2670 /* set maximum packet size */
2671 td->itd_bp[1] = htohc32(sc, temp);
2672
2673 /* set transfer multiplier */
2674 td->itd_bp[2] = htohc32(sc, xfer->max_packet_count & 3);
2675
2592
2593#if USB_DEBUG
2594 if (ehcidebug > 15) {
2595 DPRINTF("FS-TD %d\n", nframes);
2596 ehci_dump_sitd(sc, td);
2597 }
2598#endif
2599 /* insert TD into schedule */
2600 EHCI_APPEND_FS_TD(td, *pp_last);
2601 pp_last++;
2602
2603 plen++;
2604 fss++;
2605 td_last = td;
2606 td = td->obj_next;
2607 }
2608
2609 xfer->td_transfer_last = td_last;
2610
2611 /* update isoc_next */
2612 xfer->endpoint->isoc_next = (pp_last - &sc->sc_isoc_fs_p_last[0]) &
2613 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1);
2614}
2615
2616static void
2617ehci_device_isoc_fs_start(struct usb_xfer *xfer)
2618{
2619 /* put transfer on interrupt queue */
2620 ehci_transfer_intr_enqueue(xfer);
2621}
2622
2623struct usb_pipe_methods ehci_device_isoc_fs_methods =
2624{
2625 .open = ehci_device_isoc_fs_open,
2626 .close = ehci_device_isoc_fs_close,
2627 .enter = ehci_device_isoc_fs_enter,
2628 .start = ehci_device_isoc_fs_start,
2629};
2630
2631/*------------------------------------------------------------------------*
2632 * ehci high speed isochronous support
2633 *------------------------------------------------------------------------*/
2634static void
2635ehci_device_isoc_hs_open(struct usb_xfer *xfer)
2636{
2637 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
2638 ehci_itd_t *td;
2639 uint32_t temp;
2640 uint8_t ds;
2641
2642 /* initialize all TD's */
2643
2644 for (ds = 0; ds != 2; ds++) {
2645
2646 for (td = xfer->td_start[ds]; td; td = td->obj_next) {
2647
2648 /* set TD inactive */
2649 td->itd_status[0] = 0;
2650 td->itd_status[1] = 0;
2651 td->itd_status[2] = 0;
2652 td->itd_status[3] = 0;
2653 td->itd_status[4] = 0;
2654 td->itd_status[5] = 0;
2655 td->itd_status[6] = 0;
2656 td->itd_status[7] = 0;
2657
2658 /* set endpoint and address */
2659 td->itd_bp[0] = htohc32(sc,
2660 EHCI_ITD_SET_ADDR(xfer->address) |
2661 EHCI_ITD_SET_ENDPT(UE_GET_ADDR(xfer->endpointno)));
2662
2663 temp =
2664 EHCI_ITD_SET_MPL(xfer->max_packet_size & 0x7FF);
2665
2666 /* set direction */
2667 if (UE_GET_DIR(xfer->endpointno) == UE_DIR_IN) {
2668 temp |= EHCI_ITD_SET_DIR_IN;
2669 }
2670 /* set maximum packet size */
2671 td->itd_bp[1] = htohc32(sc, temp);
2672
2673 /* set transfer multiplier */
2674 td->itd_bp[2] = htohc32(sc, xfer->max_packet_count & 3);
2675
2676 usb2_pc_cpu_flush(td->page_cache);
2676 usb_pc_cpu_flush(td->page_cache);
2677 }
2678 }
2679}
2680
2681static void
2682ehci_device_isoc_hs_close(struct usb_xfer *xfer)
2683{
2684 ehci_device_done(xfer, USB_ERR_CANCELLED);
2685}
2686
2687static void
2688ehci_device_isoc_hs_enter(struct usb_xfer *xfer)
2689{
2690 struct usb_page_search buf_res;
2691 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
2692 ehci_itd_t *td;
2693 ehci_itd_t *td_last = NULL;
2694 ehci_itd_t **pp_last;
2695 bus_size_t page_addr;
2696 uint32_t *plen;
2697 uint32_t status;
2698 uint32_t buf_offset;
2699 uint32_t nframes;
2700 uint32_t itd_offset[8 + 1];
2701 uint8_t x;
2702 uint8_t td_no;
2703 uint8_t page_no;
2704
2705#if USB_DEBUG
2706 uint8_t once = 1;
2707
2708#endif
2709
2710 DPRINTFN(6, "xfer=%p next=%d nframes=%d\n",
2711 xfer, xfer->endpoint->isoc_next, xfer->nframes);
2712
2713 /* get the current frame index */
2714
2715 nframes = EOREAD4(sc, EHCI_FRINDEX) / 8;
2716
2717 /*
2718 * check if the frame index is within the window where the frames
2719 * will be inserted
2720 */
2721 buf_offset = (nframes - xfer->endpoint->isoc_next) &
2722 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1);
2723
2724 if ((xfer->endpoint->is_synced == 0) ||
2725 (buf_offset < ((xfer->nframes + 7) / 8))) {
2726 /*
2727 * If there is data underflow or the pipe queue is empty we
2728 * schedule the transfer a few frames ahead of the current
2729 * frame position. Else two isochronous transfers might
2730 * overlap.
2731 */
2732 xfer->endpoint->isoc_next = (nframes + 3) &
2733 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1);
2734 xfer->endpoint->is_synced = 1;
2735 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next);
2736 }
2737 /*
2738 * compute how many milliseconds the insertion is ahead of the
2739 * current frame position:
2740 */
2741 buf_offset = (xfer->endpoint->isoc_next - nframes) &
2742 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1);
2743
2744 /*
2745 * pre-compute when the isochronous transfer will be finished:
2746 */
2747 xfer->isoc_time_complete =
2677 }
2678 }
2679}
2680
2681static void
2682ehci_device_isoc_hs_close(struct usb_xfer *xfer)
2683{
2684 ehci_device_done(xfer, USB_ERR_CANCELLED);
2685}
2686
2687static void
2688ehci_device_isoc_hs_enter(struct usb_xfer *xfer)
2689{
2690 struct usb_page_search buf_res;
2691 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
2692 ehci_itd_t *td;
2693 ehci_itd_t *td_last = NULL;
2694 ehci_itd_t **pp_last;
2695 bus_size_t page_addr;
2696 uint32_t *plen;
2697 uint32_t status;
2698 uint32_t buf_offset;
2699 uint32_t nframes;
2700 uint32_t itd_offset[8 + 1];
2701 uint8_t x;
2702 uint8_t td_no;
2703 uint8_t page_no;
2704
2705#if USB_DEBUG
2706 uint8_t once = 1;
2707
2708#endif
2709
2710 DPRINTFN(6, "xfer=%p next=%d nframes=%d\n",
2711 xfer, xfer->endpoint->isoc_next, xfer->nframes);
2712
2713 /* get the current frame index */
2714
2715 nframes = EOREAD4(sc, EHCI_FRINDEX) / 8;
2716
2717 /*
2718 * check if the frame index is within the window where the frames
2719 * will be inserted
2720 */
2721 buf_offset = (nframes - xfer->endpoint->isoc_next) &
2722 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1);
2723
2724 if ((xfer->endpoint->is_synced == 0) ||
2725 (buf_offset < ((xfer->nframes + 7) / 8))) {
2726 /*
2727 * If there is data underflow or the pipe queue is empty we
2728 * schedule the transfer a few frames ahead of the current
2729 * frame position. Else two isochronous transfers might
2730 * overlap.
2731 */
2732 xfer->endpoint->isoc_next = (nframes + 3) &
2733 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1);
2734 xfer->endpoint->is_synced = 1;
2735 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next);
2736 }
2737 /*
2738 * compute how many milliseconds the insertion is ahead of the
2739 * current frame position:
2740 */
2741 buf_offset = (xfer->endpoint->isoc_next - nframes) &
2742 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1);
2743
2744 /*
2745 * pre-compute when the isochronous transfer will be finished:
2746 */
2747 xfer->isoc_time_complete =
2748 usb2_isoc_time_expand(&sc->sc_bus, nframes) + buf_offset +
2748 usb_isoc_time_expand(&sc->sc_bus, nframes) + buf_offset +
2749 ((xfer->nframes + 7) / 8);
2750
2751 /* get the real number of frames */
2752
2753 nframes = xfer->nframes;
2754
2755 buf_offset = 0;
2756 td_no = 0;
2757
2758 plen = xfer->frlengths;
2759
2760 /* toggle the DMA set we are using */
2761 xfer->flags_int.curr_dma_set ^= 1;
2762
2763 /* get next DMA set */
2764 td = xfer->td_start[xfer->flags_int.curr_dma_set];
2765 xfer->td_transfer_first = td;
2766
2767 pp_last = &sc->sc_isoc_hs_p_last[xfer->endpoint->isoc_next];
2768
2769 /* store starting position */
2770
2771 xfer->qh_pos = xfer->endpoint->isoc_next;
2772
2773 while (nframes--) {
2774 if (td == NULL) {
2775 panic("%s:%d: out of TD's\n",
2776 __FUNCTION__, __LINE__);
2777 }
2778 if (pp_last >= &sc->sc_isoc_hs_p_last[EHCI_VIRTUAL_FRAMELIST_COUNT]) {
2779 pp_last = &sc->sc_isoc_hs_p_last[0];
2780 }
2781 /* range check */
2782 if (*plen > xfer->max_frame_size) {
2783#if USB_DEBUG
2784 if (once) {
2785 once = 0;
2786 printf("%s: frame length(%d) exceeds %d bytes "
2787 "(frame truncated)\n",
2788 __FUNCTION__, *plen, xfer->max_frame_size);
2789 }
2790#endif
2791 *plen = xfer->max_frame_size;
2792 }
2793 status = (EHCI_ITD_SET_LEN(*plen) |
2794 EHCI_ITD_ACTIVE |
2795 EHCI_ITD_SET_PG(0));
2796 td->itd_status[td_no] = htohc32(sc, status);
2797 itd_offset[td_no] = buf_offset;
2798 buf_offset += *plen;
2799 plen++;
2800 td_no++;
2801
2802 if ((td_no == 8) || (nframes == 0)) {
2803
2804 /* the rest of the transfers are not active, if any */
2805 for (x = td_no; x != 8; x++) {
2806 td->itd_status[x] = 0; /* not active */
2807 }
2808
2809 /* check if there is any data to be transferred */
2810 if (itd_offset[0] != buf_offset) {
2811 page_no = 0;
2812 itd_offset[td_no] = buf_offset;
2813
2814 /* get first page offset */
2749 ((xfer->nframes + 7) / 8);
2750
2751 /* get the real number of frames */
2752
2753 nframes = xfer->nframes;
2754
2755 buf_offset = 0;
2756 td_no = 0;
2757
2758 plen = xfer->frlengths;
2759
2760 /* toggle the DMA set we are using */
2761 xfer->flags_int.curr_dma_set ^= 1;
2762
2763 /* get next DMA set */
2764 td = xfer->td_start[xfer->flags_int.curr_dma_set];
2765 xfer->td_transfer_first = td;
2766
2767 pp_last = &sc->sc_isoc_hs_p_last[xfer->endpoint->isoc_next];
2768
2769 /* store starting position */
2770
2771 xfer->qh_pos = xfer->endpoint->isoc_next;
2772
2773 while (nframes--) {
2774 if (td == NULL) {
2775 panic("%s:%d: out of TD's\n",
2776 __FUNCTION__, __LINE__);
2777 }
2778 if (pp_last >= &sc->sc_isoc_hs_p_last[EHCI_VIRTUAL_FRAMELIST_COUNT]) {
2779 pp_last = &sc->sc_isoc_hs_p_last[0];
2780 }
2781 /* range check */
2782 if (*plen > xfer->max_frame_size) {
2783#if USB_DEBUG
2784 if (once) {
2785 once = 0;
2786 printf("%s: frame length(%d) exceeds %d bytes "
2787 "(frame truncated)\n",
2788 __FUNCTION__, *plen, xfer->max_frame_size);
2789 }
2790#endif
2791 *plen = xfer->max_frame_size;
2792 }
2793 status = (EHCI_ITD_SET_LEN(*plen) |
2794 EHCI_ITD_ACTIVE |
2795 EHCI_ITD_SET_PG(0));
2796 td->itd_status[td_no] = htohc32(sc, status);
2797 itd_offset[td_no] = buf_offset;
2798 buf_offset += *plen;
2799 plen++;
2800 td_no++;
2801
2802 if ((td_no == 8) || (nframes == 0)) {
2803
2804 /* the rest of the transfers are not active, if any */
2805 for (x = td_no; x != 8; x++) {
2806 td->itd_status[x] = 0; /* not active */
2807 }
2808
2809 /* check if there is any data to be transferred */
2810 if (itd_offset[0] != buf_offset) {
2811 page_no = 0;
2812 itd_offset[td_no] = buf_offset;
2813
2814 /* get first page offset */
2815 usb2_get_page(xfer->frbuffers, itd_offset[0], &buf_res);
2815 usbd_get_page(xfer->frbuffers, itd_offset[0], &buf_res);
2816 /* get page address */
2817 page_addr = buf_res.physaddr & ~0xFFF;
2818 /* update page address */
2819 td->itd_bp[0] &= htohc32(sc, 0xFFF);
2820 td->itd_bp[0] |= htohc32(sc, page_addr);
2821
2822 for (x = 0; x != td_no; x++) {
2823 /* set page number and page offset */
2824 status = (EHCI_ITD_SET_PG(page_no) |
2825 (buf_res.physaddr & 0xFFF));
2826 td->itd_status[x] |= htohc32(sc, status);
2827
2828 /* get next page offset */
2829 if (itd_offset[x + 1] == buf_offset) {
2830 /*
2831 * We subtract one so that
2832 * we don't go off the last
2833 * page!
2834 */
2816 /* get page address */
2817 page_addr = buf_res.physaddr & ~0xFFF;
2818 /* update page address */
2819 td->itd_bp[0] &= htohc32(sc, 0xFFF);
2820 td->itd_bp[0] |= htohc32(sc, page_addr);
2821
2822 for (x = 0; x != td_no; x++) {
2823 /* set page number and page offset */
2824 status = (EHCI_ITD_SET_PG(page_no) |
2825 (buf_res.physaddr & 0xFFF));
2826 td->itd_status[x] |= htohc32(sc, status);
2827
2828 /* get next page offset */
2829 if (itd_offset[x + 1] == buf_offset) {
2830 /*
2831 * We subtract one so that
2832 * we don't go off the last
2833 * page!
2834 */
2835 usb2_get_page(xfer->frbuffers, buf_offset - 1, &buf_res);
2835 usbd_get_page(xfer->frbuffers, buf_offset - 1, &buf_res);
2836 } else {
2836 } else {
2837 usb2_get_page(xfer->frbuffers, itd_offset[x + 1], &buf_res);
2837 usbd_get_page(xfer->frbuffers, itd_offset[x + 1], &buf_res);
2838 }
2839
2840 /* check if we need a new page */
2841 if ((buf_res.physaddr ^ page_addr) & ~0xFFF) {
2842 /* new page needed */
2843 page_addr = buf_res.physaddr & ~0xFFF;
2844 if (page_no == 6) {
2845 panic("%s: too many pages\n", __FUNCTION__);
2846 }
2847 page_no++;
2848 /* update page address */
2849 td->itd_bp[page_no] &= htohc32(sc, 0xFFF);
2850 td->itd_bp[page_no] |= htohc32(sc, page_addr);
2851 }
2852 }
2853 }
2854 /* set IOC bit if we are complete */
2855 if (nframes == 0) {
2856 td->itd_status[7] |= htohc32(sc, EHCI_ITD_IOC);
2857 }
2838 }
2839
2840 /* check if we need a new page */
2841 if ((buf_res.physaddr ^ page_addr) & ~0xFFF) {
2842 /* new page needed */
2843 page_addr = buf_res.physaddr & ~0xFFF;
2844 if (page_no == 6) {
2845 panic("%s: too many pages\n", __FUNCTION__);
2846 }
2847 page_no++;
2848 /* update page address */
2849 td->itd_bp[page_no] &= htohc32(sc, 0xFFF);
2850 td->itd_bp[page_no] |= htohc32(sc, page_addr);
2851 }
2852 }
2853 }
2854 /* set IOC bit if we are complete */
2855 if (nframes == 0) {
2856 td->itd_status[7] |= htohc32(sc, EHCI_ITD_IOC);
2857 }
2858 usb2_pc_cpu_flush(td->page_cache);
2858 usb_pc_cpu_flush(td->page_cache);
2859#if USB_DEBUG
2860 if (ehcidebug > 15) {
2861 DPRINTF("HS-TD %d\n", nframes);
2862 ehci_dump_itd(sc, td);
2863 }
2864#endif
2865 /* insert TD into schedule */
2866 EHCI_APPEND_HS_TD(td, *pp_last);
2867 pp_last++;
2868
2869 td_no = 0;
2870 td_last = td;
2871 td = td->obj_next;
2872 }
2873 }
2874
2875 xfer->td_transfer_last = td_last;
2876
2877 /* update isoc_next */
2878 xfer->endpoint->isoc_next = (pp_last - &sc->sc_isoc_hs_p_last[0]) &
2879 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1);
2880}
2881
2882static void
2883ehci_device_isoc_hs_start(struct usb_xfer *xfer)
2884{
2885 /* put transfer on interrupt queue */
2886 ehci_transfer_intr_enqueue(xfer);
2887}
2888
2889struct usb_pipe_methods ehci_device_isoc_hs_methods =
2890{
2891 .open = ehci_device_isoc_hs_open,
2892 .close = ehci_device_isoc_hs_close,
2893 .enter = ehci_device_isoc_hs_enter,
2894 .start = ehci_device_isoc_hs_start,
2895};
2896
2897/*------------------------------------------------------------------------*
2898 * ehci root control support
2899 *------------------------------------------------------------------------*
2900 * Simulate a hardware hub by handling all the necessary requests.
2901 *------------------------------------------------------------------------*/
2902
2903static const
2904struct usb_device_descriptor ehci_devd =
2905{
2906 sizeof(struct usb_device_descriptor),
2907 UDESC_DEVICE, /* type */
2908 {0x00, 0x02}, /* USB version */
2909 UDCLASS_HUB, /* class */
2910 UDSUBCLASS_HUB, /* subclass */
2911 UDPROTO_HSHUBSTT, /* protocol */
2912 64, /* max packet */
2913 {0}, {0}, {0x00, 0x01}, /* device id */
2914 1, 2, 0, /* string indicies */
2915 1 /* # of configurations */
2916};
2917
2918static const
2919struct usb_device_qualifier ehci_odevd =
2920{
2921 sizeof(struct usb_device_qualifier),
2922 UDESC_DEVICE_QUALIFIER, /* type */
2923 {0x00, 0x02}, /* USB version */
2924 UDCLASS_HUB, /* class */
2925 UDSUBCLASS_HUB, /* subclass */
2926 UDPROTO_FSHUB, /* protocol */
2927 0, /* max packet */
2928 0, /* # of configurations */
2929 0
2930};
2931
2932static const struct ehci_config_desc ehci_confd = {
2933 .confd = {
2934 .bLength = sizeof(struct usb_config_descriptor),
2935 .bDescriptorType = UDESC_CONFIG,
2936 .wTotalLength[0] = sizeof(ehci_confd),
2937 .bNumInterface = 1,
2938 .bConfigurationValue = 1,
2939 .iConfiguration = 0,
2940 .bmAttributes = UC_SELF_POWERED,
2941 .bMaxPower = 0 /* max power */
2942 },
2943 .ifcd = {
2944 .bLength = sizeof(struct usb_interface_descriptor),
2945 .bDescriptorType = UDESC_INTERFACE,
2946 .bNumEndpoints = 1,
2947 .bInterfaceClass = UICLASS_HUB,
2948 .bInterfaceSubClass = UISUBCLASS_HUB,
2949 .bInterfaceProtocol = UIPROTO_HSHUBSTT,
2950 0
2951 },
2952 .endpd = {
2953 .bLength = sizeof(struct usb_endpoint_descriptor),
2954 .bDescriptorType = UDESC_ENDPOINT,
2955 .bEndpointAddress = UE_DIR_IN | EHCI_INTR_ENDPT,
2956 .bmAttributes = UE_INTERRUPT,
2957 .wMaxPacketSize[0] = 8, /* max packet (63 ports) */
2958 .bInterval = 255,
2959 },
2960};
2961
2962static const
2963struct usb_hub_descriptor ehci_hubd =
2964{
2965 0, /* dynamic length */
2966 UDESC_HUB,
2967 0,
2968 {0, 0},
2969 0,
2970 0,
2971 {0},
2972};
2973
2974static void
2975ehci_disown(ehci_softc_t *sc, uint16_t index, uint8_t lowspeed)
2976{
2977 uint32_t port;
2978 uint32_t v;
2979
2980 DPRINTF("index=%d lowspeed=%d\n", index, lowspeed);
2981
2982 port = EHCI_PORTSC(index);
2983 v = EOREAD4(sc, port) & ~EHCI_PS_CLEAR;
2984 EOWRITE4(sc, port, v | EHCI_PS_PO);
2985}
2986
2987static usb_error_t
2988ehci_roothub_exec(struct usb_device *udev,
2989 struct usb_device_request *req, const void **pptr, uint16_t *plength)
2990{
2991 ehci_softc_t *sc = EHCI_BUS2SC(udev->bus);
2992 const char *str_ptr;
2993 const void *ptr;
2994 uint32_t port;
2995 uint32_t v;
2996 uint16_t len;
2997 uint16_t i;
2998 uint16_t value;
2999 uint16_t index;
3000 uint8_t l;
3001 usb_error_t err;
3002
3003 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
3004
3005 /* buffer reset */
3006 ptr = (const void *)&sc->sc_hub_desc;
3007 len = 0;
3008 err = 0;
3009
3010 value = UGETW(req->wValue);
3011 index = UGETW(req->wIndex);
3012
3013 DPRINTFN(3, "type=0x%02x request=0x%02x wLen=0x%04x "
3014 "wValue=0x%04x wIndex=0x%04x\n",
3015 req->bmRequestType, req->bRequest,
3016 UGETW(req->wLength), value, index);
3017
3018#define C(x,y) ((x) | ((y) << 8))
3019 switch (C(req->bRequest, req->bmRequestType)) {
3020 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE):
3021 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE):
3022 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT):
3023 /*
3024 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops
3025 * for the integrated root hub.
3026 */
3027 break;
3028 case C(UR_GET_CONFIG, UT_READ_DEVICE):
3029 len = 1;
3030 sc->sc_hub_desc.temp[0] = sc->sc_conf;
3031 break;
3032 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE):
3033 switch (value >> 8) {
3034 case UDESC_DEVICE:
3035 if ((value & 0xff) != 0) {
3036 err = USB_ERR_IOERROR;
3037 goto done;
3038 }
3039 len = sizeof(ehci_devd);
3040 ptr = (const void *)&ehci_devd;
3041 break;
3042 /*
3043 * We can't really operate at another speed,
3044 * but the specification says we need this
3045 * descriptor:
3046 */
3047 case UDESC_DEVICE_QUALIFIER:
3048 if ((value & 0xff) != 0) {
3049 err = USB_ERR_IOERROR;
3050 goto done;
3051 }
3052 len = sizeof(ehci_odevd);
3053 ptr = (const void *)&ehci_odevd;
3054 break;
3055
3056 case UDESC_CONFIG:
3057 if ((value & 0xff) != 0) {
3058 err = USB_ERR_IOERROR;
3059 goto done;
3060 }
3061 len = sizeof(ehci_confd);
3062 ptr = (const void *)&ehci_confd;
3063 break;
3064
3065 case UDESC_STRING:
3066 switch (value & 0xff) {
3067 case 0: /* Language table */
3068 str_ptr = "\001";
3069 break;
3070
3071 case 1: /* Vendor */
3072 str_ptr = sc->sc_vendor;
3073 break;
3074
3075 case 2: /* Product */
3076 str_ptr = "EHCI root HUB";
3077 break;
3078
3079 default:
3080 str_ptr = "";
3081 break;
3082 }
3083
2859#if USB_DEBUG
2860 if (ehcidebug > 15) {
2861 DPRINTF("HS-TD %d\n", nframes);
2862 ehci_dump_itd(sc, td);
2863 }
2864#endif
2865 /* insert TD into schedule */
2866 EHCI_APPEND_HS_TD(td, *pp_last);
2867 pp_last++;
2868
2869 td_no = 0;
2870 td_last = td;
2871 td = td->obj_next;
2872 }
2873 }
2874
2875 xfer->td_transfer_last = td_last;
2876
2877 /* update isoc_next */
2878 xfer->endpoint->isoc_next = (pp_last - &sc->sc_isoc_hs_p_last[0]) &
2879 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1);
2880}
2881
2882static void
2883ehci_device_isoc_hs_start(struct usb_xfer *xfer)
2884{
2885 /* put transfer on interrupt queue */
2886 ehci_transfer_intr_enqueue(xfer);
2887}
2888
2889struct usb_pipe_methods ehci_device_isoc_hs_methods =
2890{
2891 .open = ehci_device_isoc_hs_open,
2892 .close = ehci_device_isoc_hs_close,
2893 .enter = ehci_device_isoc_hs_enter,
2894 .start = ehci_device_isoc_hs_start,
2895};
2896
2897/*------------------------------------------------------------------------*
2898 * ehci root control support
2899 *------------------------------------------------------------------------*
2900 * Simulate a hardware hub by handling all the necessary requests.
2901 *------------------------------------------------------------------------*/
2902
2903static const
2904struct usb_device_descriptor ehci_devd =
2905{
2906 sizeof(struct usb_device_descriptor),
2907 UDESC_DEVICE, /* type */
2908 {0x00, 0x02}, /* USB version */
2909 UDCLASS_HUB, /* class */
2910 UDSUBCLASS_HUB, /* subclass */
2911 UDPROTO_HSHUBSTT, /* protocol */
2912 64, /* max packet */
2913 {0}, {0}, {0x00, 0x01}, /* device id */
2914 1, 2, 0, /* string indicies */
2915 1 /* # of configurations */
2916};
2917
2918static const
2919struct usb_device_qualifier ehci_odevd =
2920{
2921 sizeof(struct usb_device_qualifier),
2922 UDESC_DEVICE_QUALIFIER, /* type */
2923 {0x00, 0x02}, /* USB version */
2924 UDCLASS_HUB, /* class */
2925 UDSUBCLASS_HUB, /* subclass */
2926 UDPROTO_FSHUB, /* protocol */
2927 0, /* max packet */
2928 0, /* # of configurations */
2929 0
2930};
2931
2932static const struct ehci_config_desc ehci_confd = {
2933 .confd = {
2934 .bLength = sizeof(struct usb_config_descriptor),
2935 .bDescriptorType = UDESC_CONFIG,
2936 .wTotalLength[0] = sizeof(ehci_confd),
2937 .bNumInterface = 1,
2938 .bConfigurationValue = 1,
2939 .iConfiguration = 0,
2940 .bmAttributes = UC_SELF_POWERED,
2941 .bMaxPower = 0 /* max power */
2942 },
2943 .ifcd = {
2944 .bLength = sizeof(struct usb_interface_descriptor),
2945 .bDescriptorType = UDESC_INTERFACE,
2946 .bNumEndpoints = 1,
2947 .bInterfaceClass = UICLASS_HUB,
2948 .bInterfaceSubClass = UISUBCLASS_HUB,
2949 .bInterfaceProtocol = UIPROTO_HSHUBSTT,
2950 0
2951 },
2952 .endpd = {
2953 .bLength = sizeof(struct usb_endpoint_descriptor),
2954 .bDescriptorType = UDESC_ENDPOINT,
2955 .bEndpointAddress = UE_DIR_IN | EHCI_INTR_ENDPT,
2956 .bmAttributes = UE_INTERRUPT,
2957 .wMaxPacketSize[0] = 8, /* max packet (63 ports) */
2958 .bInterval = 255,
2959 },
2960};
2961
2962static const
2963struct usb_hub_descriptor ehci_hubd =
2964{
2965 0, /* dynamic length */
2966 UDESC_HUB,
2967 0,
2968 {0, 0},
2969 0,
2970 0,
2971 {0},
2972};
2973
2974static void
2975ehci_disown(ehci_softc_t *sc, uint16_t index, uint8_t lowspeed)
2976{
2977 uint32_t port;
2978 uint32_t v;
2979
2980 DPRINTF("index=%d lowspeed=%d\n", index, lowspeed);
2981
2982 port = EHCI_PORTSC(index);
2983 v = EOREAD4(sc, port) & ~EHCI_PS_CLEAR;
2984 EOWRITE4(sc, port, v | EHCI_PS_PO);
2985}
2986
2987static usb_error_t
2988ehci_roothub_exec(struct usb_device *udev,
2989 struct usb_device_request *req, const void **pptr, uint16_t *plength)
2990{
2991 ehci_softc_t *sc = EHCI_BUS2SC(udev->bus);
2992 const char *str_ptr;
2993 const void *ptr;
2994 uint32_t port;
2995 uint32_t v;
2996 uint16_t len;
2997 uint16_t i;
2998 uint16_t value;
2999 uint16_t index;
3000 uint8_t l;
3001 usb_error_t err;
3002
3003 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
3004
3005 /* buffer reset */
3006 ptr = (const void *)&sc->sc_hub_desc;
3007 len = 0;
3008 err = 0;
3009
3010 value = UGETW(req->wValue);
3011 index = UGETW(req->wIndex);
3012
3013 DPRINTFN(3, "type=0x%02x request=0x%02x wLen=0x%04x "
3014 "wValue=0x%04x wIndex=0x%04x\n",
3015 req->bmRequestType, req->bRequest,
3016 UGETW(req->wLength), value, index);
3017
3018#define C(x,y) ((x) | ((y) << 8))
3019 switch (C(req->bRequest, req->bmRequestType)) {
3020 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE):
3021 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE):
3022 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT):
3023 /*
3024 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops
3025 * for the integrated root hub.
3026 */
3027 break;
3028 case C(UR_GET_CONFIG, UT_READ_DEVICE):
3029 len = 1;
3030 sc->sc_hub_desc.temp[0] = sc->sc_conf;
3031 break;
3032 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE):
3033 switch (value >> 8) {
3034 case UDESC_DEVICE:
3035 if ((value & 0xff) != 0) {
3036 err = USB_ERR_IOERROR;
3037 goto done;
3038 }
3039 len = sizeof(ehci_devd);
3040 ptr = (const void *)&ehci_devd;
3041 break;
3042 /*
3043 * We can't really operate at another speed,
3044 * but the specification says we need this
3045 * descriptor:
3046 */
3047 case UDESC_DEVICE_QUALIFIER:
3048 if ((value & 0xff) != 0) {
3049 err = USB_ERR_IOERROR;
3050 goto done;
3051 }
3052 len = sizeof(ehci_odevd);
3053 ptr = (const void *)&ehci_odevd;
3054 break;
3055
3056 case UDESC_CONFIG:
3057 if ((value & 0xff) != 0) {
3058 err = USB_ERR_IOERROR;
3059 goto done;
3060 }
3061 len = sizeof(ehci_confd);
3062 ptr = (const void *)&ehci_confd;
3063 break;
3064
3065 case UDESC_STRING:
3066 switch (value & 0xff) {
3067 case 0: /* Language table */
3068 str_ptr = "\001";
3069 break;
3070
3071 case 1: /* Vendor */
3072 str_ptr = sc->sc_vendor;
3073 break;
3074
3075 case 2: /* Product */
3076 str_ptr = "EHCI root HUB";
3077 break;
3078
3079 default:
3080 str_ptr = "";
3081 break;
3082 }
3083
3084 len = usb2_make_str_desc(
3084 len = usb_make_str_desc(
3085 sc->sc_hub_desc.temp,
3086 sizeof(sc->sc_hub_desc.temp),
3087 str_ptr);
3088 break;
3089 default:
3090 err = USB_ERR_IOERROR;
3091 goto done;
3092 }
3093 break;
3094 case C(UR_GET_INTERFACE, UT_READ_INTERFACE):
3095 len = 1;
3096 sc->sc_hub_desc.temp[0] = 0;
3097 break;
3098 case C(UR_GET_STATUS, UT_READ_DEVICE):
3099 len = 2;
3100 USETW(sc->sc_hub_desc.stat.wStatus, UDS_SELF_POWERED);
3101 break;
3102 case C(UR_GET_STATUS, UT_READ_INTERFACE):
3103 case C(UR_GET_STATUS, UT_READ_ENDPOINT):
3104 len = 2;
3105 USETW(sc->sc_hub_desc.stat.wStatus, 0);
3106 break;
3107 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE):
3108 if (value >= EHCI_MAX_DEVICES) {
3109 err = USB_ERR_IOERROR;
3110 goto done;
3111 }
3112 sc->sc_addr = value;
3113 break;
3114 case C(UR_SET_CONFIG, UT_WRITE_DEVICE):
3115 if ((value != 0) && (value != 1)) {
3116 err = USB_ERR_IOERROR;
3117 goto done;
3118 }
3119 sc->sc_conf = value;
3120 break;
3121 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE):
3122 break;
3123 case C(UR_SET_FEATURE, UT_WRITE_DEVICE):
3124 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE):
3125 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT):
3126 err = USB_ERR_IOERROR;
3127 goto done;
3128 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE):
3129 break;
3130 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT):
3131 break;
3132 /* Hub requests */
3133 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE):
3134 break;
3135 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER):
3136 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE\n");
3137
3138 if ((index < 1) ||
3139 (index > sc->sc_noport)) {
3140 err = USB_ERR_IOERROR;
3141 goto done;
3142 }
3143 port = EHCI_PORTSC(index);
3144 v = EOREAD4(sc, port) & ~EHCI_PS_CLEAR;
3145 switch (value) {
3146 case UHF_PORT_ENABLE:
3147 EOWRITE4(sc, port, v & ~EHCI_PS_PE);
3148 break;
3149 case UHF_PORT_SUSPEND:
3150 if ((v & EHCI_PS_SUSP) && (!(v & EHCI_PS_FPR))) {
3151
3152 /*
3153 * waking up a High Speed device is rather
3154 * complicated if
3155 */
3156 EOWRITE4(sc, port, v | EHCI_PS_FPR);
3157 }
3158 /* wait 20ms for resume sequence to complete */
3085 sc->sc_hub_desc.temp,
3086 sizeof(sc->sc_hub_desc.temp),
3087 str_ptr);
3088 break;
3089 default:
3090 err = USB_ERR_IOERROR;
3091 goto done;
3092 }
3093 break;
3094 case C(UR_GET_INTERFACE, UT_READ_INTERFACE):
3095 len = 1;
3096 sc->sc_hub_desc.temp[0] = 0;
3097 break;
3098 case C(UR_GET_STATUS, UT_READ_DEVICE):
3099 len = 2;
3100 USETW(sc->sc_hub_desc.stat.wStatus, UDS_SELF_POWERED);
3101 break;
3102 case C(UR_GET_STATUS, UT_READ_INTERFACE):
3103 case C(UR_GET_STATUS, UT_READ_ENDPOINT):
3104 len = 2;
3105 USETW(sc->sc_hub_desc.stat.wStatus, 0);
3106 break;
3107 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE):
3108 if (value >= EHCI_MAX_DEVICES) {
3109 err = USB_ERR_IOERROR;
3110 goto done;
3111 }
3112 sc->sc_addr = value;
3113 break;
3114 case C(UR_SET_CONFIG, UT_WRITE_DEVICE):
3115 if ((value != 0) && (value != 1)) {
3116 err = USB_ERR_IOERROR;
3117 goto done;
3118 }
3119 sc->sc_conf = value;
3120 break;
3121 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE):
3122 break;
3123 case C(UR_SET_FEATURE, UT_WRITE_DEVICE):
3124 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE):
3125 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT):
3126 err = USB_ERR_IOERROR;
3127 goto done;
3128 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE):
3129 break;
3130 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT):
3131 break;
3132 /* Hub requests */
3133 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE):
3134 break;
3135 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER):
3136 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE\n");
3137
3138 if ((index < 1) ||
3139 (index > sc->sc_noport)) {
3140 err = USB_ERR_IOERROR;
3141 goto done;
3142 }
3143 port = EHCI_PORTSC(index);
3144 v = EOREAD4(sc, port) & ~EHCI_PS_CLEAR;
3145 switch (value) {
3146 case UHF_PORT_ENABLE:
3147 EOWRITE4(sc, port, v & ~EHCI_PS_PE);
3148 break;
3149 case UHF_PORT_SUSPEND:
3150 if ((v & EHCI_PS_SUSP) && (!(v & EHCI_PS_FPR))) {
3151
3152 /*
3153 * waking up a High Speed device is rather
3154 * complicated if
3155 */
3156 EOWRITE4(sc, port, v | EHCI_PS_FPR);
3157 }
3158 /* wait 20ms for resume sequence to complete */
3159 usb2_pause_mtx(&sc->sc_bus.bus_mtx, hz / 50);
3159 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 50);
3160
3161 EOWRITE4(sc, port, v & ~(EHCI_PS_SUSP |
3162 EHCI_PS_FPR | (3 << 10) /* High Speed */ ));
3163
3164 /* 4ms settle time */
3160
3161 EOWRITE4(sc, port, v & ~(EHCI_PS_SUSP |
3162 EHCI_PS_FPR | (3 << 10) /* High Speed */ ));
3163
3164 /* 4ms settle time */
3165 usb2_pause_mtx(&sc->sc_bus.bus_mtx, hz / 250);
3165 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 250);
3166 break;
3167 case UHF_PORT_POWER:
3168 EOWRITE4(sc, port, v & ~EHCI_PS_PP);
3169 break;
3170 case UHF_PORT_TEST:
3171 DPRINTFN(3, "clear port test "
3172 "%d\n", index);
3173 break;
3174 case UHF_PORT_INDICATOR:
3175 DPRINTFN(3, "clear port ind "
3176 "%d\n", index);
3177 EOWRITE4(sc, port, v & ~EHCI_PS_PIC);
3178 break;
3179 case UHF_C_PORT_CONNECTION:
3180 EOWRITE4(sc, port, v | EHCI_PS_CSC);
3181 break;
3182 case UHF_C_PORT_ENABLE:
3183 EOWRITE4(sc, port, v | EHCI_PS_PEC);
3184 break;
3185 case UHF_C_PORT_SUSPEND:
3186 EOWRITE4(sc, port, v | EHCI_PS_SUSP);
3187 break;
3188 case UHF_C_PORT_OVER_CURRENT:
3189 EOWRITE4(sc, port, v | EHCI_PS_OCC);
3190 break;
3191 case UHF_C_PORT_RESET:
3192 sc->sc_isreset = 0;
3193 break;
3194 default:
3195 err = USB_ERR_IOERROR;
3196 goto done;
3197 }
3198 break;
3199 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE):
3200 if ((value & 0xff) != 0) {
3201 err = USB_ERR_IOERROR;
3202 goto done;
3203 }
3204 v = EOREAD4(sc, EHCI_HCSPARAMS);
3205
3206 sc->sc_hub_desc.hubd = ehci_hubd;
3207 sc->sc_hub_desc.hubd.bNbrPorts = sc->sc_noport;
3208 USETW(sc->sc_hub_desc.hubd.wHubCharacteristics,
3209 (EHCI_HCS_PPC(v) ? UHD_PWR_INDIVIDUAL : UHD_PWR_NO_SWITCH) |
3210 (EHCI_HCS_P_INDICATOR(EREAD4(sc, EHCI_HCSPARAMS)) ?
3211 UHD_PORT_IND : 0));
3212 /* XXX can't find out? */
3213 sc->sc_hub_desc.hubd.bPwrOn2PwrGood = 200;
3214 for (l = 0; l < sc->sc_noport; l++) {
3215 /* XXX can't find out? */
3216 sc->sc_hub_desc.hubd.DeviceRemovable[l / 8] &= ~(1 << (l % 8));
3217 }
3218 sc->sc_hub_desc.hubd.bDescLength =
3219 8 + ((sc->sc_noport + 7) / 8);
3220 len = sc->sc_hub_desc.hubd.bDescLength;
3221 break;
3222 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE):
3223 len = 16;
3224 bzero(sc->sc_hub_desc.temp, 16);
3225 break;
3226 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER):
3227 DPRINTFN(9, "get port status i=%d\n",
3228 index);
3229 if ((index < 1) ||
3230 (index > sc->sc_noport)) {
3231 err = USB_ERR_IOERROR;
3232 goto done;
3233 }
3234 v = EOREAD4(sc, EHCI_PORTSC(index));
3235 DPRINTFN(9, "port status=0x%04x\n", v);
3236 if (sc->sc_flags & (EHCI_SCFLG_FORCESPEED | EHCI_SCFLG_TT)) {
3237 if ((v & 0xc000000) == 0x8000000)
3238 i = UPS_HIGH_SPEED;
3239 else if ((v & 0xc000000) == 0x4000000)
3240 i = UPS_LOW_SPEED;
3241 else
3242 i = 0;
3243 } else {
3244 i = UPS_HIGH_SPEED;
3245 }
3246 if (v & EHCI_PS_CS)
3247 i |= UPS_CURRENT_CONNECT_STATUS;
3248 if (v & EHCI_PS_PE)
3249 i |= UPS_PORT_ENABLED;
3250 if ((v & EHCI_PS_SUSP) && !(v & EHCI_PS_FPR))
3251 i |= UPS_SUSPEND;
3252 if (v & EHCI_PS_OCA)
3253 i |= UPS_OVERCURRENT_INDICATOR;
3254 if (v & EHCI_PS_PR)
3255 i |= UPS_RESET;
3256 if (v & EHCI_PS_PP)
3257 i |= UPS_PORT_POWER;
3258 USETW(sc->sc_hub_desc.ps.wPortStatus, i);
3259 i = 0;
3260 if (v & EHCI_PS_CSC)
3261 i |= UPS_C_CONNECT_STATUS;
3262 if (v & EHCI_PS_PEC)
3263 i |= UPS_C_PORT_ENABLED;
3264 if (v & EHCI_PS_OCC)
3265 i |= UPS_C_OVERCURRENT_INDICATOR;
3266 if (v & EHCI_PS_FPR)
3267 i |= UPS_C_SUSPEND;
3268 if (sc->sc_isreset)
3269 i |= UPS_C_PORT_RESET;
3270 USETW(sc->sc_hub_desc.ps.wPortChange, i);
3271 len = sizeof(sc->sc_hub_desc.ps);
3272 break;
3273 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE):
3274 err = USB_ERR_IOERROR;
3275 goto done;
3276 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE):
3277 break;
3278 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER):
3279 if ((index < 1) ||
3280 (index > sc->sc_noport)) {
3281 err = USB_ERR_IOERROR;
3282 goto done;
3283 }
3284 port = EHCI_PORTSC(index);
3285 v = EOREAD4(sc, port) & ~EHCI_PS_CLEAR;
3286 switch (value) {
3287 case UHF_PORT_ENABLE:
3288 EOWRITE4(sc, port, v | EHCI_PS_PE);
3289 break;
3290 case UHF_PORT_SUSPEND:
3291 EOWRITE4(sc, port, v | EHCI_PS_SUSP);
3292 break;
3293 case UHF_PORT_RESET:
3294 DPRINTFN(6, "reset port %d\n", index);
3295#if USB_DEBUG
3296 if (ehcinohighspeed) {
3297 /*
3298 * Connect USB device to companion
3299 * controller.
3300 */
3301 ehci_disown(sc, index, 1);
3302 break;
3303 }
3304#endif
3305 if (EHCI_PS_IS_LOWSPEED(v) &&
3306 (sc->sc_flags & EHCI_SCFLG_TT) == 0) {
3307 /* Low speed device, give up ownership. */
3308 ehci_disown(sc, index, 1);
3309 break;
3310 }
3311 /* Start reset sequence. */
3312 v &= ~(EHCI_PS_PE | EHCI_PS_PR);
3313 EOWRITE4(sc, port, v | EHCI_PS_PR);
3314
3315 /* Wait for reset to complete. */
3166 break;
3167 case UHF_PORT_POWER:
3168 EOWRITE4(sc, port, v & ~EHCI_PS_PP);
3169 break;
3170 case UHF_PORT_TEST:
3171 DPRINTFN(3, "clear port test "
3172 "%d\n", index);
3173 break;
3174 case UHF_PORT_INDICATOR:
3175 DPRINTFN(3, "clear port ind "
3176 "%d\n", index);
3177 EOWRITE4(sc, port, v & ~EHCI_PS_PIC);
3178 break;
3179 case UHF_C_PORT_CONNECTION:
3180 EOWRITE4(sc, port, v | EHCI_PS_CSC);
3181 break;
3182 case UHF_C_PORT_ENABLE:
3183 EOWRITE4(sc, port, v | EHCI_PS_PEC);
3184 break;
3185 case UHF_C_PORT_SUSPEND:
3186 EOWRITE4(sc, port, v | EHCI_PS_SUSP);
3187 break;
3188 case UHF_C_PORT_OVER_CURRENT:
3189 EOWRITE4(sc, port, v | EHCI_PS_OCC);
3190 break;
3191 case UHF_C_PORT_RESET:
3192 sc->sc_isreset = 0;
3193 break;
3194 default:
3195 err = USB_ERR_IOERROR;
3196 goto done;
3197 }
3198 break;
3199 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE):
3200 if ((value & 0xff) != 0) {
3201 err = USB_ERR_IOERROR;
3202 goto done;
3203 }
3204 v = EOREAD4(sc, EHCI_HCSPARAMS);
3205
3206 sc->sc_hub_desc.hubd = ehci_hubd;
3207 sc->sc_hub_desc.hubd.bNbrPorts = sc->sc_noport;
3208 USETW(sc->sc_hub_desc.hubd.wHubCharacteristics,
3209 (EHCI_HCS_PPC(v) ? UHD_PWR_INDIVIDUAL : UHD_PWR_NO_SWITCH) |
3210 (EHCI_HCS_P_INDICATOR(EREAD4(sc, EHCI_HCSPARAMS)) ?
3211 UHD_PORT_IND : 0));
3212 /* XXX can't find out? */
3213 sc->sc_hub_desc.hubd.bPwrOn2PwrGood = 200;
3214 for (l = 0; l < sc->sc_noport; l++) {
3215 /* XXX can't find out? */
3216 sc->sc_hub_desc.hubd.DeviceRemovable[l / 8] &= ~(1 << (l % 8));
3217 }
3218 sc->sc_hub_desc.hubd.bDescLength =
3219 8 + ((sc->sc_noport + 7) / 8);
3220 len = sc->sc_hub_desc.hubd.bDescLength;
3221 break;
3222 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE):
3223 len = 16;
3224 bzero(sc->sc_hub_desc.temp, 16);
3225 break;
3226 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER):
3227 DPRINTFN(9, "get port status i=%d\n",
3228 index);
3229 if ((index < 1) ||
3230 (index > sc->sc_noport)) {
3231 err = USB_ERR_IOERROR;
3232 goto done;
3233 }
3234 v = EOREAD4(sc, EHCI_PORTSC(index));
3235 DPRINTFN(9, "port status=0x%04x\n", v);
3236 if (sc->sc_flags & (EHCI_SCFLG_FORCESPEED | EHCI_SCFLG_TT)) {
3237 if ((v & 0xc000000) == 0x8000000)
3238 i = UPS_HIGH_SPEED;
3239 else if ((v & 0xc000000) == 0x4000000)
3240 i = UPS_LOW_SPEED;
3241 else
3242 i = 0;
3243 } else {
3244 i = UPS_HIGH_SPEED;
3245 }
3246 if (v & EHCI_PS_CS)
3247 i |= UPS_CURRENT_CONNECT_STATUS;
3248 if (v & EHCI_PS_PE)
3249 i |= UPS_PORT_ENABLED;
3250 if ((v & EHCI_PS_SUSP) && !(v & EHCI_PS_FPR))
3251 i |= UPS_SUSPEND;
3252 if (v & EHCI_PS_OCA)
3253 i |= UPS_OVERCURRENT_INDICATOR;
3254 if (v & EHCI_PS_PR)
3255 i |= UPS_RESET;
3256 if (v & EHCI_PS_PP)
3257 i |= UPS_PORT_POWER;
3258 USETW(sc->sc_hub_desc.ps.wPortStatus, i);
3259 i = 0;
3260 if (v & EHCI_PS_CSC)
3261 i |= UPS_C_CONNECT_STATUS;
3262 if (v & EHCI_PS_PEC)
3263 i |= UPS_C_PORT_ENABLED;
3264 if (v & EHCI_PS_OCC)
3265 i |= UPS_C_OVERCURRENT_INDICATOR;
3266 if (v & EHCI_PS_FPR)
3267 i |= UPS_C_SUSPEND;
3268 if (sc->sc_isreset)
3269 i |= UPS_C_PORT_RESET;
3270 USETW(sc->sc_hub_desc.ps.wPortChange, i);
3271 len = sizeof(sc->sc_hub_desc.ps);
3272 break;
3273 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE):
3274 err = USB_ERR_IOERROR;
3275 goto done;
3276 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE):
3277 break;
3278 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER):
3279 if ((index < 1) ||
3280 (index > sc->sc_noport)) {
3281 err = USB_ERR_IOERROR;
3282 goto done;
3283 }
3284 port = EHCI_PORTSC(index);
3285 v = EOREAD4(sc, port) & ~EHCI_PS_CLEAR;
3286 switch (value) {
3287 case UHF_PORT_ENABLE:
3288 EOWRITE4(sc, port, v | EHCI_PS_PE);
3289 break;
3290 case UHF_PORT_SUSPEND:
3291 EOWRITE4(sc, port, v | EHCI_PS_SUSP);
3292 break;
3293 case UHF_PORT_RESET:
3294 DPRINTFN(6, "reset port %d\n", index);
3295#if USB_DEBUG
3296 if (ehcinohighspeed) {
3297 /*
3298 * Connect USB device to companion
3299 * controller.
3300 */
3301 ehci_disown(sc, index, 1);
3302 break;
3303 }
3304#endif
3305 if (EHCI_PS_IS_LOWSPEED(v) &&
3306 (sc->sc_flags & EHCI_SCFLG_TT) == 0) {
3307 /* Low speed device, give up ownership. */
3308 ehci_disown(sc, index, 1);
3309 break;
3310 }
3311 /* Start reset sequence. */
3312 v &= ~(EHCI_PS_PE | EHCI_PS_PR);
3313 EOWRITE4(sc, port, v | EHCI_PS_PR);
3314
3315 /* Wait for reset to complete. */
3316 usb2_pause_mtx(&sc->sc_bus.bus_mtx,
3316 usb_pause_mtx(&sc->sc_bus.bus_mtx,
3317 USB_MS_TO_TICKS(USB_PORT_ROOT_RESET_DELAY));
3318
3319 /* Terminate reset sequence. */
3320 if (!(sc->sc_flags & EHCI_SCFLG_NORESTERM))
3321 EOWRITE4(sc, port, v);
3322
3323 /* Wait for HC to complete reset. */
3317 USB_MS_TO_TICKS(USB_PORT_ROOT_RESET_DELAY));
3318
3319 /* Terminate reset sequence. */
3320 if (!(sc->sc_flags & EHCI_SCFLG_NORESTERM))
3321 EOWRITE4(sc, port, v);
3322
3323 /* Wait for HC to complete reset. */
3324 usb2_pause_mtx(&sc->sc_bus.bus_mtx,
3324 usb_pause_mtx(&sc->sc_bus.bus_mtx,
3325 USB_MS_TO_TICKS(EHCI_PORT_RESET_COMPLETE));
3326
3327 v = EOREAD4(sc, port);
3328 DPRINTF("ehci after reset, status=0x%08x\n", v);
3329 if (v & EHCI_PS_PR) {
3330 device_printf(sc->sc_bus.bdev,
3331 "port reset timeout\n");
3332 err = USB_ERR_TIMEOUT;
3333 goto done;
3334 }
3335 if (!(v & EHCI_PS_PE) &&
3336 (sc->sc_flags & EHCI_SCFLG_TT) == 0) {
3337 /* Not a high speed device, give up ownership.*/
3338 ehci_disown(sc, index, 0);
3339 break;
3340 }
3341 sc->sc_isreset = 1;
3342 DPRINTF("ehci port %d reset, status = 0x%08x\n",
3343 index, v);
3344 break;
3345
3346 case UHF_PORT_POWER:
3347 DPRINTFN(3, "set port power %d\n", index);
3348 EOWRITE4(sc, port, v | EHCI_PS_PP);
3349 break;
3350
3351 case UHF_PORT_TEST:
3352 DPRINTFN(3, "set port test %d\n", index);
3353 break;
3354
3355 case UHF_PORT_INDICATOR:
3356 DPRINTFN(3, "set port ind %d\n", index);
3357 EOWRITE4(sc, port, v | EHCI_PS_PIC);
3358 break;
3359
3360 default:
3361 err = USB_ERR_IOERROR;
3362 goto done;
3363 }
3364 break;
3365 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER):
3366 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER):
3367 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER):
3368 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER):
3369 break;
3370 default:
3371 err = USB_ERR_IOERROR;
3372 goto done;
3373 }
3374done:
3375 *plength = len;
3376 *pptr = ptr;
3377 return (err);
3378}
3379
3380static void
3381ehci_xfer_setup(struct usb_setup_params *parm)
3382{
3383 struct usb_page_search page_info;
3384 struct usb_page_cache *pc;
3385 ehci_softc_t *sc;
3386 struct usb_xfer *xfer;
3387 void *last_obj;
3388 uint32_t nqtd;
3389 uint32_t nqh;
3390 uint32_t nsitd;
3391 uint32_t nitd;
3392 uint32_t n;
3393
3394 sc = EHCI_BUS2SC(parm->udev->bus);
3395 xfer = parm->curr_xfer;
3396
3397 nqtd = 0;
3398 nqh = 0;
3399 nsitd = 0;
3400 nitd = 0;
3401
3402 /*
3403 * compute maximum number of some structures
3404 */
3405 if (parm->methods == &ehci_device_ctrl_methods) {
3406
3407 /*
3408 * The proof for the "nqtd" formula is illustrated like
3409 * this:
3410 *
3411 * +------------------------------------+
3412 * | |
3413 * | |remainder -> |
3414 * | +-----+---+ |
3415 * | | xxx | x | frm 0 |
3416 * | +-----+---++ |
3417 * | | xxx | xx | frm 1 |
3418 * | +-----+----+ |
3419 * | ... |
3420 * +------------------------------------+
3421 *
3422 * "xxx" means a completely full USB transfer descriptor
3423 *
3424 * "x" and "xx" means a short USB packet
3425 *
3426 * For the remainder of an USB transfer modulo
3427 * "max_data_length" we need two USB transfer descriptors.
3428 * One to transfer the remaining data and one to finalise
3429 * with a zero length packet in case the "force_short_xfer"
3430 * flag is set. We only need two USB transfer descriptors in
3431 * the case where the transfer length of the first one is a
3432 * factor of "max_frame_size". The rest of the needed USB
3433 * transfer descriptors is given by the buffer size divided
3434 * by the maximum data payload.
3435 */
3436 parm->hc_max_packet_size = 0x400;
3437 parm->hc_max_packet_count = 1;
3438 parm->hc_max_frame_size = EHCI_QTD_PAYLOAD_MAX;
3439 xfer->flags_int.bdma_enable = 1;
3440
3325 USB_MS_TO_TICKS(EHCI_PORT_RESET_COMPLETE));
3326
3327 v = EOREAD4(sc, port);
3328 DPRINTF("ehci after reset, status=0x%08x\n", v);
3329 if (v & EHCI_PS_PR) {
3330 device_printf(sc->sc_bus.bdev,
3331 "port reset timeout\n");
3332 err = USB_ERR_TIMEOUT;
3333 goto done;
3334 }
3335 if (!(v & EHCI_PS_PE) &&
3336 (sc->sc_flags & EHCI_SCFLG_TT) == 0) {
3337 /* Not a high speed device, give up ownership.*/
3338 ehci_disown(sc, index, 0);
3339 break;
3340 }
3341 sc->sc_isreset = 1;
3342 DPRINTF("ehci port %d reset, status = 0x%08x\n",
3343 index, v);
3344 break;
3345
3346 case UHF_PORT_POWER:
3347 DPRINTFN(3, "set port power %d\n", index);
3348 EOWRITE4(sc, port, v | EHCI_PS_PP);
3349 break;
3350
3351 case UHF_PORT_TEST:
3352 DPRINTFN(3, "set port test %d\n", index);
3353 break;
3354
3355 case UHF_PORT_INDICATOR:
3356 DPRINTFN(3, "set port ind %d\n", index);
3357 EOWRITE4(sc, port, v | EHCI_PS_PIC);
3358 break;
3359
3360 default:
3361 err = USB_ERR_IOERROR;
3362 goto done;
3363 }
3364 break;
3365 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER):
3366 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER):
3367 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER):
3368 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER):
3369 break;
3370 default:
3371 err = USB_ERR_IOERROR;
3372 goto done;
3373 }
3374done:
3375 *plength = len;
3376 *pptr = ptr;
3377 return (err);
3378}
3379
3380static void
3381ehci_xfer_setup(struct usb_setup_params *parm)
3382{
3383 struct usb_page_search page_info;
3384 struct usb_page_cache *pc;
3385 ehci_softc_t *sc;
3386 struct usb_xfer *xfer;
3387 void *last_obj;
3388 uint32_t nqtd;
3389 uint32_t nqh;
3390 uint32_t nsitd;
3391 uint32_t nitd;
3392 uint32_t n;
3393
3394 sc = EHCI_BUS2SC(parm->udev->bus);
3395 xfer = parm->curr_xfer;
3396
3397 nqtd = 0;
3398 nqh = 0;
3399 nsitd = 0;
3400 nitd = 0;
3401
3402 /*
3403 * compute maximum number of some structures
3404 */
3405 if (parm->methods == &ehci_device_ctrl_methods) {
3406
3407 /*
3408 * The proof for the "nqtd" formula is illustrated like
3409 * this:
3410 *
3411 * +------------------------------------+
3412 * | |
3413 * | |remainder -> |
3414 * | +-----+---+ |
3415 * | | xxx | x | frm 0 |
3416 * | +-----+---++ |
3417 * | | xxx | xx | frm 1 |
3418 * | +-----+----+ |
3419 * | ... |
3420 * +------------------------------------+
3421 *
3422 * "xxx" means a completely full USB transfer descriptor
3423 *
3424 * "x" and "xx" means a short USB packet
3425 *
3426 * For the remainder of an USB transfer modulo
3427 * "max_data_length" we need two USB transfer descriptors.
3428 * One to transfer the remaining data and one to finalise
3429 * with a zero length packet in case the "force_short_xfer"
3430 * flag is set. We only need two USB transfer descriptors in
3431 * the case where the transfer length of the first one is a
3432 * factor of "max_frame_size". The rest of the needed USB
3433 * transfer descriptors is given by the buffer size divided
3434 * by the maximum data payload.
3435 */
3436 parm->hc_max_packet_size = 0x400;
3437 parm->hc_max_packet_count = 1;
3438 parm->hc_max_frame_size = EHCI_QTD_PAYLOAD_MAX;
3439 xfer->flags_int.bdma_enable = 1;
3440
3441 usb2_transfer_setup_sub(parm);
3441 usbd_transfer_setup_sub(parm);
3442
3443 nqh = 1;
3444 nqtd = ((2 * xfer->nframes) + 1 /* STATUS */
3445 + (xfer->max_data_length / xfer->max_hc_frame_size));
3446
3447 } else if (parm->methods == &ehci_device_bulk_methods) {
3448
3449 parm->hc_max_packet_size = 0x400;
3450 parm->hc_max_packet_count = 1;
3451 parm->hc_max_frame_size = EHCI_QTD_PAYLOAD_MAX;
3452 xfer->flags_int.bdma_enable = 1;
3453
3442
3443 nqh = 1;
3444 nqtd = ((2 * xfer->nframes) + 1 /* STATUS */
3445 + (xfer->max_data_length / xfer->max_hc_frame_size));
3446
3447 } else if (parm->methods == &ehci_device_bulk_methods) {
3448
3449 parm->hc_max_packet_size = 0x400;
3450 parm->hc_max_packet_count = 1;
3451 parm->hc_max_frame_size = EHCI_QTD_PAYLOAD_MAX;
3452 xfer->flags_int.bdma_enable = 1;
3453
3454 usb2_transfer_setup_sub(parm);
3454 usbd_transfer_setup_sub(parm);
3455
3456 nqh = 1;
3457 nqtd = ((2 * xfer->nframes)
3458 + (xfer->max_data_length / xfer->max_hc_frame_size));
3459
3460 } else if (parm->methods == &ehci_device_intr_methods) {
3461
3462 if (parm->speed == USB_SPEED_HIGH) {
3463 parm->hc_max_packet_size = 0x400;
3464 parm->hc_max_packet_count = 3;
3465 } else if (parm->speed == USB_SPEED_FULL) {
3466 parm->hc_max_packet_size = USB_FS_BYTES_PER_HS_UFRAME;
3467 parm->hc_max_packet_count = 1;
3468 } else {
3469 parm->hc_max_packet_size = USB_FS_BYTES_PER_HS_UFRAME / 8;
3470 parm->hc_max_packet_count = 1;
3471 }
3472
3473 parm->hc_max_frame_size = EHCI_QTD_PAYLOAD_MAX;
3474 xfer->flags_int.bdma_enable = 1;
3475
3455
3456 nqh = 1;
3457 nqtd = ((2 * xfer->nframes)
3458 + (xfer->max_data_length / xfer->max_hc_frame_size));
3459
3460 } else if (parm->methods == &ehci_device_intr_methods) {
3461
3462 if (parm->speed == USB_SPEED_HIGH) {
3463 parm->hc_max_packet_size = 0x400;
3464 parm->hc_max_packet_count = 3;
3465 } else if (parm->speed == USB_SPEED_FULL) {
3466 parm->hc_max_packet_size = USB_FS_BYTES_PER_HS_UFRAME;
3467 parm->hc_max_packet_count = 1;
3468 } else {
3469 parm->hc_max_packet_size = USB_FS_BYTES_PER_HS_UFRAME / 8;
3470 parm->hc_max_packet_count = 1;
3471 }
3472
3473 parm->hc_max_frame_size = EHCI_QTD_PAYLOAD_MAX;
3474 xfer->flags_int.bdma_enable = 1;
3475
3476 usb2_transfer_setup_sub(parm);
3476 usbd_transfer_setup_sub(parm);
3477
3478 nqh = 1;
3479 nqtd = ((2 * xfer->nframes)
3480 + (xfer->max_data_length / xfer->max_hc_frame_size));
3481
3482 } else if (parm->methods == &ehci_device_isoc_fs_methods) {
3483
3484 parm->hc_max_packet_size = 0x3FF;
3485 parm->hc_max_packet_count = 1;
3486 parm->hc_max_frame_size = 0x3FF;
3487 xfer->flags_int.bdma_enable = 1;
3488
3477
3478 nqh = 1;
3479 nqtd = ((2 * xfer->nframes)
3480 + (xfer->max_data_length / xfer->max_hc_frame_size));
3481
3482 } else if (parm->methods == &ehci_device_isoc_fs_methods) {
3483
3484 parm->hc_max_packet_size = 0x3FF;
3485 parm->hc_max_packet_count = 1;
3486 parm->hc_max_frame_size = 0x3FF;
3487 xfer->flags_int.bdma_enable = 1;
3488
3489 usb2_transfer_setup_sub(parm);
3489 usbd_transfer_setup_sub(parm);
3490
3491 nsitd = xfer->nframes;
3492
3493 } else if (parm->methods == &ehci_device_isoc_hs_methods) {
3494
3495 parm->hc_max_packet_size = 0x400;
3496 parm->hc_max_packet_count = 3;
3497 parm->hc_max_frame_size = 0xC00;
3498 xfer->flags_int.bdma_enable = 1;
3499
3490
3491 nsitd = xfer->nframes;
3492
3493 } else if (parm->methods == &ehci_device_isoc_hs_methods) {
3494
3495 parm->hc_max_packet_size = 0x400;
3496 parm->hc_max_packet_count = 3;
3497 parm->hc_max_frame_size = 0xC00;
3498 xfer->flags_int.bdma_enable = 1;
3499
3500 usb2_transfer_setup_sub(parm);
3500 usbd_transfer_setup_sub(parm);
3501
3502 nitd = (xfer->nframes + 7) / 8;
3503
3504 } else {
3505
3506 parm->hc_max_packet_size = 0x400;
3507 parm->hc_max_packet_count = 1;
3508 parm->hc_max_frame_size = 0x400;
3509
3501
3502 nitd = (xfer->nframes + 7) / 8;
3503
3504 } else {
3505
3506 parm->hc_max_packet_size = 0x400;
3507 parm->hc_max_packet_count = 1;
3508 parm->hc_max_frame_size = 0x400;
3509
3510 usb2_transfer_setup_sub(parm);
3510 usbd_transfer_setup_sub(parm);
3511 }
3512
3513alloc_dma_set:
3514
3515 if (parm->err) {
3516 return;
3517 }
3518 /*
3519 * Allocate queue heads and transfer descriptors
3520 */
3521 last_obj = NULL;
3522
3511 }
3512
3513alloc_dma_set:
3514
3515 if (parm->err) {
3516 return;
3517 }
3518 /*
3519 * Allocate queue heads and transfer descriptors
3520 */
3521 last_obj = NULL;
3522
3523 if (usb2_transfer_setup_sub_malloc(
3523 if (usbd_transfer_setup_sub_malloc(
3524 parm, &pc, sizeof(ehci_itd_t),
3525 EHCI_ITD_ALIGN, nitd)) {
3526 parm->err = USB_ERR_NOMEM;
3527 return;
3528 }
3529 if (parm->buf) {
3530 for (n = 0; n != nitd; n++) {
3531 ehci_itd_t *td;
3532
3524 parm, &pc, sizeof(ehci_itd_t),
3525 EHCI_ITD_ALIGN, nitd)) {
3526 parm->err = USB_ERR_NOMEM;
3527 return;
3528 }
3529 if (parm->buf) {
3530 for (n = 0; n != nitd; n++) {
3531 ehci_itd_t *td;
3532
3533 usb2_get_page(pc + n, 0, &page_info);
3533 usbd_get_page(pc + n, 0, &page_info);
3534
3535 td = page_info.buffer;
3536
3537 /* init TD */
3538 td->itd_self = htohc32(sc, page_info.physaddr | EHCI_LINK_ITD);
3539 td->obj_next = last_obj;
3540 td->page_cache = pc + n;
3541
3542 last_obj = td;
3543
3534
3535 td = page_info.buffer;
3536
3537 /* init TD */
3538 td->itd_self = htohc32(sc, page_info.physaddr | EHCI_LINK_ITD);
3539 td->obj_next = last_obj;
3540 td->page_cache = pc + n;
3541
3542 last_obj = td;
3543
3544 usb2_pc_cpu_flush(pc + n);
3544 usb_pc_cpu_flush(pc + n);
3545 }
3546 }
3545 }
3546 }
3547 if (usb2_transfer_setup_sub_malloc(
3547 if (usbd_transfer_setup_sub_malloc(
3548 parm, &pc, sizeof(ehci_sitd_t),
3549 EHCI_SITD_ALIGN, nsitd)) {
3550 parm->err = USB_ERR_NOMEM;
3551 return;
3552 }
3553 if (parm->buf) {
3554 for (n = 0; n != nsitd; n++) {
3555 ehci_sitd_t *td;
3556
3548 parm, &pc, sizeof(ehci_sitd_t),
3549 EHCI_SITD_ALIGN, nsitd)) {
3550 parm->err = USB_ERR_NOMEM;
3551 return;
3552 }
3553 if (parm->buf) {
3554 for (n = 0; n != nsitd; n++) {
3555 ehci_sitd_t *td;
3556
3557 usb2_get_page(pc + n, 0, &page_info);
3557 usbd_get_page(pc + n, 0, &page_info);
3558
3559 td = page_info.buffer;
3560
3561 /* init TD */
3562 td->sitd_self = htohc32(sc, page_info.physaddr | EHCI_LINK_SITD);
3563 td->obj_next = last_obj;
3564 td->page_cache = pc + n;
3565
3566 last_obj = td;
3567
3558
3559 td = page_info.buffer;
3560
3561 /* init TD */
3562 td->sitd_self = htohc32(sc, page_info.physaddr | EHCI_LINK_SITD);
3563 td->obj_next = last_obj;
3564 td->page_cache = pc + n;
3565
3566 last_obj = td;
3567
3568 usb2_pc_cpu_flush(pc + n);
3568 usb_pc_cpu_flush(pc + n);
3569 }
3570 }
3569 }
3570 }
3571 if (usb2_transfer_setup_sub_malloc(
3571 if (usbd_transfer_setup_sub_malloc(
3572 parm, &pc, sizeof(ehci_qtd_t),
3573 EHCI_QTD_ALIGN, nqtd)) {
3574 parm->err = USB_ERR_NOMEM;
3575 return;
3576 }
3577 if (parm->buf) {
3578 for (n = 0; n != nqtd; n++) {
3579 ehci_qtd_t *qtd;
3580
3572 parm, &pc, sizeof(ehci_qtd_t),
3573 EHCI_QTD_ALIGN, nqtd)) {
3574 parm->err = USB_ERR_NOMEM;
3575 return;
3576 }
3577 if (parm->buf) {
3578 for (n = 0; n != nqtd; n++) {
3579 ehci_qtd_t *qtd;
3580
3581 usb2_get_page(pc + n, 0, &page_info);
3581 usbd_get_page(pc + n, 0, &page_info);
3582
3583 qtd = page_info.buffer;
3584
3585 /* init TD */
3586 qtd->qtd_self = htohc32(sc, page_info.physaddr);
3587 qtd->obj_next = last_obj;
3588 qtd->page_cache = pc + n;
3589
3590 last_obj = qtd;
3591
3582
3583 qtd = page_info.buffer;
3584
3585 /* init TD */
3586 qtd->qtd_self = htohc32(sc, page_info.physaddr);
3587 qtd->obj_next = last_obj;
3588 qtd->page_cache = pc + n;
3589
3590 last_obj = qtd;
3591
3592 usb2_pc_cpu_flush(pc + n);
3592 usb_pc_cpu_flush(pc + n);
3593 }
3594 }
3595 xfer->td_start[xfer->flags_int.curr_dma_set] = last_obj;
3596
3597 last_obj = NULL;
3598
3593 }
3594 }
3595 xfer->td_start[xfer->flags_int.curr_dma_set] = last_obj;
3596
3597 last_obj = NULL;
3598
3599 if (usb2_transfer_setup_sub_malloc(
3599 if (usbd_transfer_setup_sub_malloc(
3600 parm, &pc, sizeof(ehci_qh_t),
3601 EHCI_QH_ALIGN, nqh)) {
3602 parm->err = USB_ERR_NOMEM;
3603 return;
3604 }
3605 if (parm->buf) {
3606 for (n = 0; n != nqh; n++) {
3607 ehci_qh_t *qh;
3608
3600 parm, &pc, sizeof(ehci_qh_t),
3601 EHCI_QH_ALIGN, nqh)) {
3602 parm->err = USB_ERR_NOMEM;
3603 return;
3604 }
3605 if (parm->buf) {
3606 for (n = 0; n != nqh; n++) {
3607 ehci_qh_t *qh;
3608
3609 usb2_get_page(pc + n, 0, &page_info);
3609 usbd_get_page(pc + n, 0, &page_info);
3610
3611 qh = page_info.buffer;
3612
3613 /* init QH */
3614 qh->qh_self = htohc32(sc, page_info.physaddr | EHCI_LINK_QH);
3615 qh->obj_next = last_obj;
3616 qh->page_cache = pc + n;
3617
3618 last_obj = qh;
3619
3610
3611 qh = page_info.buffer;
3612
3613 /* init QH */
3614 qh->qh_self = htohc32(sc, page_info.physaddr | EHCI_LINK_QH);
3615 qh->obj_next = last_obj;
3616 qh->page_cache = pc + n;
3617
3618 last_obj = qh;
3619
3620 usb2_pc_cpu_flush(pc + n);
3620 usb_pc_cpu_flush(pc + n);
3621 }
3622 }
3623 xfer->qh_start[xfer->flags_int.curr_dma_set] = last_obj;
3624
3625 if (!xfer->flags_int.curr_dma_set) {
3626 xfer->flags_int.curr_dma_set = 1;
3627 goto alloc_dma_set;
3628 }
3629}
3630
3631static void
3632ehci_xfer_unsetup(struct usb_xfer *xfer)
3633{
3634 return;
3635}
3636
3637static void
3638ehci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc,
3639 struct usb_endpoint *ep)
3640{
3641 ehci_softc_t *sc = EHCI_BUS2SC(udev->bus);
3642
3643 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d (%d)\n",
3644 ep, udev->address,
3645 edesc->bEndpointAddress, udev->flags.usb_mode,
3646 sc->sc_addr);
3647
3648 if (udev->flags.usb_mode != USB_MODE_HOST) {
3649 /* not supported */
3650 return;
3651 }
3652 if (udev->device_index != sc->sc_addr) {
3653
3654 if ((udev->speed != USB_SPEED_HIGH) &&
3655 ((udev->hs_hub_addr == 0) ||
3656 (udev->hs_port_no == 0) ||
3657 (udev->parent_hs_hub == NULL) ||
3658 (udev->parent_hs_hub->hub == NULL))) {
3659 /* We need a transaction translator */
3660 goto done;
3661 }
3662 switch (edesc->bmAttributes & UE_XFERTYPE) {
3663 case UE_CONTROL:
3664 ep->methods = &ehci_device_ctrl_methods;
3665 break;
3666 case UE_INTERRUPT:
3667 ep->methods = &ehci_device_intr_methods;
3668 break;
3669 case UE_ISOCHRONOUS:
3670 if (udev->speed == USB_SPEED_HIGH) {
3671 ep->methods = &ehci_device_isoc_hs_methods;
3672 } else if (udev->speed == USB_SPEED_FULL) {
3673 ep->methods = &ehci_device_isoc_fs_methods;
3674 }
3675 break;
3676 case UE_BULK:
3677 if (udev->speed != USB_SPEED_LOW) {
3678 ep->methods = &ehci_device_bulk_methods;
3679 }
3680 break;
3681 default:
3682 /* do nothing */
3683 break;
3684 }
3685 }
3686done:
3687 return;
3688}
3689
3690static void
3691ehci_get_dma_delay(struct usb_bus *bus, uint32_t *pus)
3692{
3693 /*
3694 * Wait until the hardware has finished any possible use of
3695 * the transfer descriptor(s) and QH
3696 */
3697 *pus = (188); /* microseconds */
3698}
3699
3700static void
3701ehci_device_resume(struct usb_device *udev)
3702{
3703 ehci_softc_t *sc = EHCI_BUS2SC(udev->bus);
3704 struct usb_xfer *xfer;
3705 struct usb_pipe_methods *methods;
3706
3707 DPRINTF("\n");
3708
3709 USB_BUS_LOCK(udev->bus);
3710
3711 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
3712
3713 if (xfer->xroot->udev == udev) {
3714
3715 methods = xfer->endpoint->methods;
3716
3717 if ((methods == &ehci_device_bulk_methods) ||
3718 (methods == &ehci_device_ctrl_methods)) {
3719 EHCI_APPEND_QH(xfer->qh_start[xfer->flags_int.curr_dma_set],
3720 sc->sc_async_p_last);
3721 }
3722 if (methods == &ehci_device_intr_methods) {
3723 EHCI_APPEND_QH(xfer->qh_start[xfer->flags_int.curr_dma_set],
3724 sc->sc_intr_p_last[xfer->qh_pos]);
3725 }
3726 }
3727 }
3728
3729 USB_BUS_UNLOCK(udev->bus);
3730
3731 return;
3732}
3733
3734static void
3735ehci_device_suspend(struct usb_device *udev)
3736{
3737 ehci_softc_t *sc = EHCI_BUS2SC(udev->bus);
3738 struct usb_xfer *xfer;
3739 struct usb_pipe_methods *methods;
3740
3741 DPRINTF("\n");
3742
3743 USB_BUS_LOCK(udev->bus);
3744
3745 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
3746
3747 if (xfer->xroot->udev == udev) {
3748
3749 methods = xfer->endpoint->methods;
3750
3751 if ((methods == &ehci_device_bulk_methods) ||
3752 (methods == &ehci_device_ctrl_methods)) {
3753 EHCI_REMOVE_QH(xfer->qh_start[xfer->flags_int.curr_dma_set],
3754 sc->sc_async_p_last);
3755 }
3756 if (methods == &ehci_device_intr_methods) {
3757 EHCI_REMOVE_QH(xfer->qh_start[xfer->flags_int.curr_dma_set],
3758 sc->sc_intr_p_last[xfer->qh_pos]);
3759 }
3760 }
3761 }
3762
3763 USB_BUS_UNLOCK(udev->bus);
3764
3765 return;
3766}
3767
3768static void
3769ehci_set_hw_power(struct usb_bus *bus)
3770{
3771 ehci_softc_t *sc = EHCI_BUS2SC(bus);
3772 uint32_t temp;
3773 uint32_t flags;
3774
3775 DPRINTF("\n");
3776
3777 USB_BUS_LOCK(bus);
3778
3779 flags = bus->hw_power_state;
3780
3781 temp = EOREAD4(sc, EHCI_USBCMD);
3782
3783 temp &= ~(EHCI_CMD_ASE | EHCI_CMD_PSE);
3784
3785 if (flags & (USB_HW_POWER_CONTROL |
3786 USB_HW_POWER_BULK)) {
3787 DPRINTF("Async is active\n");
3788 temp |= EHCI_CMD_ASE;
3789 }
3790 if (flags & (USB_HW_POWER_INTERRUPT |
3791 USB_HW_POWER_ISOC)) {
3792 DPRINTF("Periodic is active\n");
3793 temp |= EHCI_CMD_PSE;
3794 }
3795 EOWRITE4(sc, EHCI_USBCMD, temp);
3796
3797 USB_BUS_UNLOCK(bus);
3798
3799 return;
3800}
3801
3802struct usb_bus_methods ehci_bus_methods =
3803{
3804 .endpoint_init = ehci_ep_init,
3805 .xfer_setup = ehci_xfer_setup,
3806 .xfer_unsetup = ehci_xfer_unsetup,
3807 .get_dma_delay = ehci_get_dma_delay,
3808 .device_resume = ehci_device_resume,
3809 .device_suspend = ehci_device_suspend,
3810 .set_hw_power = ehci_set_hw_power,
3811 .roothub_exec = ehci_roothub_exec,
3812};
3621 }
3622 }
3623 xfer->qh_start[xfer->flags_int.curr_dma_set] = last_obj;
3624
3625 if (!xfer->flags_int.curr_dma_set) {
3626 xfer->flags_int.curr_dma_set = 1;
3627 goto alloc_dma_set;
3628 }
3629}
3630
3631static void
3632ehci_xfer_unsetup(struct usb_xfer *xfer)
3633{
3634 return;
3635}
3636
3637static void
3638ehci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc,
3639 struct usb_endpoint *ep)
3640{
3641 ehci_softc_t *sc = EHCI_BUS2SC(udev->bus);
3642
3643 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d (%d)\n",
3644 ep, udev->address,
3645 edesc->bEndpointAddress, udev->flags.usb_mode,
3646 sc->sc_addr);
3647
3648 if (udev->flags.usb_mode != USB_MODE_HOST) {
3649 /* not supported */
3650 return;
3651 }
3652 if (udev->device_index != sc->sc_addr) {
3653
3654 if ((udev->speed != USB_SPEED_HIGH) &&
3655 ((udev->hs_hub_addr == 0) ||
3656 (udev->hs_port_no == 0) ||
3657 (udev->parent_hs_hub == NULL) ||
3658 (udev->parent_hs_hub->hub == NULL))) {
3659 /* We need a transaction translator */
3660 goto done;
3661 }
3662 switch (edesc->bmAttributes & UE_XFERTYPE) {
3663 case UE_CONTROL:
3664 ep->methods = &ehci_device_ctrl_methods;
3665 break;
3666 case UE_INTERRUPT:
3667 ep->methods = &ehci_device_intr_methods;
3668 break;
3669 case UE_ISOCHRONOUS:
3670 if (udev->speed == USB_SPEED_HIGH) {
3671 ep->methods = &ehci_device_isoc_hs_methods;
3672 } else if (udev->speed == USB_SPEED_FULL) {
3673 ep->methods = &ehci_device_isoc_fs_methods;
3674 }
3675 break;
3676 case UE_BULK:
3677 if (udev->speed != USB_SPEED_LOW) {
3678 ep->methods = &ehci_device_bulk_methods;
3679 }
3680 break;
3681 default:
3682 /* do nothing */
3683 break;
3684 }
3685 }
3686done:
3687 return;
3688}
3689
3690static void
3691ehci_get_dma_delay(struct usb_bus *bus, uint32_t *pus)
3692{
3693 /*
3694 * Wait until the hardware has finished any possible use of
3695 * the transfer descriptor(s) and QH
3696 */
3697 *pus = (188); /* microseconds */
3698}
3699
3700static void
3701ehci_device_resume(struct usb_device *udev)
3702{
3703 ehci_softc_t *sc = EHCI_BUS2SC(udev->bus);
3704 struct usb_xfer *xfer;
3705 struct usb_pipe_methods *methods;
3706
3707 DPRINTF("\n");
3708
3709 USB_BUS_LOCK(udev->bus);
3710
3711 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
3712
3713 if (xfer->xroot->udev == udev) {
3714
3715 methods = xfer->endpoint->methods;
3716
3717 if ((methods == &ehci_device_bulk_methods) ||
3718 (methods == &ehci_device_ctrl_methods)) {
3719 EHCI_APPEND_QH(xfer->qh_start[xfer->flags_int.curr_dma_set],
3720 sc->sc_async_p_last);
3721 }
3722 if (methods == &ehci_device_intr_methods) {
3723 EHCI_APPEND_QH(xfer->qh_start[xfer->flags_int.curr_dma_set],
3724 sc->sc_intr_p_last[xfer->qh_pos]);
3725 }
3726 }
3727 }
3728
3729 USB_BUS_UNLOCK(udev->bus);
3730
3731 return;
3732}
3733
3734static void
3735ehci_device_suspend(struct usb_device *udev)
3736{
3737 ehci_softc_t *sc = EHCI_BUS2SC(udev->bus);
3738 struct usb_xfer *xfer;
3739 struct usb_pipe_methods *methods;
3740
3741 DPRINTF("\n");
3742
3743 USB_BUS_LOCK(udev->bus);
3744
3745 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
3746
3747 if (xfer->xroot->udev == udev) {
3748
3749 methods = xfer->endpoint->methods;
3750
3751 if ((methods == &ehci_device_bulk_methods) ||
3752 (methods == &ehci_device_ctrl_methods)) {
3753 EHCI_REMOVE_QH(xfer->qh_start[xfer->flags_int.curr_dma_set],
3754 sc->sc_async_p_last);
3755 }
3756 if (methods == &ehci_device_intr_methods) {
3757 EHCI_REMOVE_QH(xfer->qh_start[xfer->flags_int.curr_dma_set],
3758 sc->sc_intr_p_last[xfer->qh_pos]);
3759 }
3760 }
3761 }
3762
3763 USB_BUS_UNLOCK(udev->bus);
3764
3765 return;
3766}
3767
3768static void
3769ehci_set_hw_power(struct usb_bus *bus)
3770{
3771 ehci_softc_t *sc = EHCI_BUS2SC(bus);
3772 uint32_t temp;
3773 uint32_t flags;
3774
3775 DPRINTF("\n");
3776
3777 USB_BUS_LOCK(bus);
3778
3779 flags = bus->hw_power_state;
3780
3781 temp = EOREAD4(sc, EHCI_USBCMD);
3782
3783 temp &= ~(EHCI_CMD_ASE | EHCI_CMD_PSE);
3784
3785 if (flags & (USB_HW_POWER_CONTROL |
3786 USB_HW_POWER_BULK)) {
3787 DPRINTF("Async is active\n");
3788 temp |= EHCI_CMD_ASE;
3789 }
3790 if (flags & (USB_HW_POWER_INTERRUPT |
3791 USB_HW_POWER_ISOC)) {
3792 DPRINTF("Periodic is active\n");
3793 temp |= EHCI_CMD_PSE;
3794 }
3795 EOWRITE4(sc, EHCI_USBCMD, temp);
3796
3797 USB_BUS_UNLOCK(bus);
3798
3799 return;
3800}
3801
3802struct usb_bus_methods ehci_bus_methods =
3803{
3804 .endpoint_init = ehci_ep_init,
3805 .xfer_setup = ehci_xfer_setup,
3806 .xfer_unsetup = ehci_xfer_unsetup,
3807 .get_dma_delay = ehci_get_dma_delay,
3808 .device_resume = ehci_device_resume,
3809 .device_suspend = ehci_device_suspend,
3810 .set_hw_power = ehci_set_hw_power,
3811 .roothub_exec = ehci_roothub_exec,
3812};