1/*-
2 * Copyright (c) 2008 Hans Petter Selasky. All rights reserved.
3 * Copyright (c) 2004 The NetBSD Foundation, Inc. All rights reserved.
4 * Copyright (c) 2004 Lennart Augustsson. All rights reserved.
5 * Copyright (c) 2004 Charles M. Hannum. All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29/*
30 * USB Enhanced Host Controller Driver, a.k.a. USB 2.0 controller.
31 *
32 * The EHCI 0.96 spec can be found at
33 * http://developer.intel.com/technology/usb/download/ehci-r096.pdf
34 * The EHCI 1.0 spec can be found at
35 * http://developer.intel.com/technology/usb/download/ehci-r10.pdf
36 * and the USB 2.0 spec at
37 * http://www.usb.org/developers/docs/usb_20.zip
38 *
39 */
40
41/*
42 * TODO:
43 * 1) command failures are not recovered correctly
44 */
45
46#include <sys/cdefs.h>
47__FBSDID("$FreeBSD: head/sys/dev/usb/controller/ehci.c 241082 2012-10-01 05:42:43Z hselasky $");
48
49#include <sys/stdint.h>
50#include <sys/stddef.h>
51#include <sys/param.h>
52#include <sys/queue.h>
53#include <sys/types.h>
54#include <sys/systm.h>
55#include <sys/kernel.h>
56#include <sys/bus.h>
57#include <sys/module.h>
58#include <sys/lock.h>
59#include <sys/mutex.h>
60#include <sys/condvar.h>
61#include <sys/sysctl.h>
62#include <sys/sx.h>
63#include <sys/unistd.h>
64#include <sys/callout.h>
65#include <sys/malloc.h>
66#include <sys/priv.h>
67
68#include <dev/usb/usb.h>
69#include <dev/usb/usbdi.h>
70
71#define USB_DEBUG_VAR ehcidebug
72
73#include <dev/usb/usb_core.h>
74#include <dev/usb/usb_debug.h>
75#include <dev/usb/usb_busdma.h>
76#include <dev/usb/usb_process.h>
77#include <dev/usb/usb_transfer.h>
78#include <dev/usb/usb_device.h>
79#include <dev/usb/usb_hub.h>
80#include <dev/usb/usb_util.h>
81
82#include <dev/usb/usb_controller.h>
83#include <dev/usb/usb_bus.h>
84#include <dev/usb/controller/ehci.h>
85#include <dev/usb/controller/ehcireg.h>
86
87#define EHCI_BUS2SC(bus) \
88 ((ehci_softc_t *)(((uint8_t *)(bus)) - \
89 ((uint8_t *)&(((ehci_softc_t *)0)->sc_bus))))
90
91#ifdef USB_DEBUG
92static int ehcidebug = 0;
93static int ehcinohighspeed = 0;
94static int ehciiaadbug = 0;
95static int ehcilostintrbug = 0;
96
97static SYSCTL_NODE(_hw_usb, OID_AUTO, ehci, CTLFLAG_RW, 0, "USB ehci");
98SYSCTL_INT(_hw_usb_ehci, OID_AUTO, debug, CTLFLAG_RW,
99 &ehcidebug, 0, "Debug level");
100SYSCTL_INT(_hw_usb_ehci, OID_AUTO, no_hs, CTLFLAG_RW,
101 &ehcinohighspeed, 0, "Disable High Speed USB");
102SYSCTL_INT(_hw_usb_ehci, OID_AUTO, iaadbug, CTLFLAG_RW,
103 &ehciiaadbug, 0, "Enable doorbell bug workaround");
104SYSCTL_INT(_hw_usb_ehci, OID_AUTO, lostintrbug, CTLFLAG_RW,
105 &ehcilostintrbug, 0, "Enable lost interrupt bug workaround");
106
107TUNABLE_INT("hw.usb.ehci.debug", &ehcidebug);
108TUNABLE_INT("hw.usb.ehci.no_hs", &ehcinohighspeed);
109TUNABLE_INT("hw.usb.ehci.iaadbug", &ehciiaadbug);
110TUNABLE_INT("hw.usb.ehci.lostintrbug", &ehcilostintrbug);
111
112static void ehci_dump_regs(ehci_softc_t *sc);
113static void ehci_dump_sqh(ehci_softc_t *sc, ehci_qh_t *sqh);
114
115#endif
116
117#define EHCI_INTR_ENDPT 1
118
119extern struct usb_bus_methods ehci_bus_methods;
120extern struct usb_pipe_methods ehci_device_bulk_methods;
121extern struct usb_pipe_methods ehci_device_ctrl_methods;
122extern struct usb_pipe_methods ehci_device_intr_methods;
123extern struct usb_pipe_methods ehci_device_isoc_fs_methods;
124extern struct usb_pipe_methods ehci_device_isoc_hs_methods;
125
126static void ehci_do_poll(struct usb_bus *);
127static void ehci_device_done(struct usb_xfer *, usb_error_t);
128static uint8_t ehci_check_transfer(struct usb_xfer *);
129static void ehci_timeout(void *);
130static void ehci_poll_timeout(void *);
131
132static void ehci_root_intr(ehci_softc_t *sc);
133
134struct ehci_std_temp {
135 ehci_softc_t *sc;
136 struct usb_page_cache *pc;
137 ehci_qtd_t *td;
138 ehci_qtd_t *td_next;
139 uint32_t average;
140 uint32_t qtd_status;
141 uint32_t len;
142 uint16_t max_frame_size;
143 uint8_t shortpkt;
144 uint8_t auto_data_toggle;
145 uint8_t setup_alt_next;
146 uint8_t last_frame;
147};
148
149void
150ehci_iterate_hw_softc(struct usb_bus *bus, usb_bus_mem_sub_cb_t *cb)
151{
152 ehci_softc_t *sc = EHCI_BUS2SC(bus);
153 uint32_t i;
154
155 cb(bus, &sc->sc_hw.pframes_pc, &sc->sc_hw.pframes_pg,
156 sizeof(uint32_t) * EHCI_FRAMELIST_COUNT, EHCI_FRAMELIST_ALIGN);
157
158 cb(bus, &sc->sc_hw.terminate_pc, &sc->sc_hw.terminate_pg,
159 sizeof(struct ehci_qh_sub), EHCI_QH_ALIGN);
160
161 cb(bus, &sc->sc_hw.async_start_pc, &sc->sc_hw.async_start_pg,
162 sizeof(ehci_qh_t), EHCI_QH_ALIGN);
163
164 for (i = 0; i != EHCI_VIRTUAL_FRAMELIST_COUNT; i++) {
165 cb(bus, sc->sc_hw.intr_start_pc + i,
166 sc->sc_hw.intr_start_pg + i,
167 sizeof(ehci_qh_t), EHCI_QH_ALIGN);
168 }
169
170 for (i = 0; i != EHCI_VIRTUAL_FRAMELIST_COUNT; i++) {
171 cb(bus, sc->sc_hw.isoc_hs_start_pc + i,
172 sc->sc_hw.isoc_hs_start_pg + i,
173 sizeof(ehci_itd_t), EHCI_ITD_ALIGN);
174 }
175
176 for (i = 0; i != EHCI_VIRTUAL_FRAMELIST_COUNT; i++) {
177 cb(bus, sc->sc_hw.isoc_fs_start_pc + i,
178 sc->sc_hw.isoc_fs_start_pg + i,
179 sizeof(ehci_sitd_t), EHCI_SITD_ALIGN);
180 }
181}
182
183usb_error_t
184ehci_reset(ehci_softc_t *sc)
185{
186 uint32_t hcr;
187 int i;
188
189 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET);
190 for (i = 0; i < 100; i++) {
191 usb_pause_mtx(NULL, hz / 128);
192 hcr = EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_HCRESET;
193 if (!hcr) {
194 if (sc->sc_flags & (EHCI_SCFLG_SETMODE | EHCI_SCFLG_BIGEMMIO)) {
195 /*
196 * Force USBMODE as requested. Controllers
197 * may have multiple operating modes.
198 */
199 uint32_t usbmode = EOREAD4(sc, EHCI_USBMODE);
200 if (sc->sc_flags & EHCI_SCFLG_SETMODE) {
201 usbmode = (usbmode &~ EHCI_UM_CM) | EHCI_UM_CM_HOST;
202 device_printf(sc->sc_bus.bdev,
203 "set host controller mode\n");
204 }
205 if (sc->sc_flags & EHCI_SCFLG_BIGEMMIO) {
206 usbmode = (usbmode &~ EHCI_UM_ES) | EHCI_UM_ES_BE;
207 device_printf(sc->sc_bus.bdev,
208 "set big-endian mode\n");
209 }
210 EOWRITE4(sc, EHCI_USBMODE, usbmode);
211 }
212 return (0);
213 }
214 }
215 device_printf(sc->sc_bus.bdev, "Reset timeout\n");
216 return (USB_ERR_IOERROR);
217}
218
219static usb_error_t
220ehci_hcreset(ehci_softc_t *sc)
221{
222 uint32_t hcr;
223 int i;
224
225 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */
226 for (i = 0; i < 100; i++) {
227 usb_pause_mtx(NULL, hz / 128);
228 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH;
229 if (hcr)
230 break;
231 }
232 if (!hcr)
233 /*
234 * Fall through and try reset anyway even though
235 * Table 2-9 in the EHCI spec says this will result
236 * in undefined behavior.
237 */
238 device_printf(sc->sc_bus.bdev, "stop timeout\n");
239
240 return (ehci_reset(sc));
241}
242
243static int
244ehci_init_sub(struct ehci_softc *sc)
245{
246 struct usb_page_search buf_res;
247 uint32_t cparams;
248 uint32_t hcr;
249 uint8_t i;
250
251 cparams = EREAD4(sc, EHCI_HCCPARAMS);
252
253 DPRINTF("cparams=0x%x\n", cparams);
254
255 if (EHCI_HCC_64BIT(cparams)) {
256 DPRINTF("HCC uses 64-bit structures\n");
257
258 /* MUST clear segment register if 64 bit capable */
259 EWRITE4(sc, EHCI_CTRLDSSEGMENT, 0);
260 }
261
262 usbd_get_page(&sc->sc_hw.pframes_pc, 0, &buf_res);
263 EOWRITE4(sc, EHCI_PERIODICLISTBASE, buf_res.physaddr);
264
265 usbd_get_page(&sc->sc_hw.async_start_pc, 0, &buf_res);
266 EOWRITE4(sc, EHCI_ASYNCLISTADDR, buf_res.physaddr | EHCI_LINK_QH);
267
268 /* enable interrupts */
269 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs);
270
271 /* turn on controller */
272 EOWRITE4(sc, EHCI_USBCMD,
273 EHCI_CMD_ITC_1 | /* 1 microframes interrupt delay */
274 (EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_FLS_M) |
275 EHCI_CMD_ASE |
276 EHCI_CMD_PSE |
277 EHCI_CMD_RS);
278
279 /* Take over port ownership */
280 EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF);
281
282 for (i = 0; i < 100; i++) {
283 usb_pause_mtx(NULL, hz / 128);
284 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH;
285 if (!hcr) {
286 break;
287 }
288 }
289 if (hcr) {
290 device_printf(sc->sc_bus.bdev, "Run timeout\n");
291 return (USB_ERR_IOERROR);
292 }
293 return (USB_ERR_NORMAL_COMPLETION);
294}
295
296usb_error_t
297ehci_init(ehci_softc_t *sc)
298{
299 struct usb_page_search buf_res;
300 uint32_t version;
301 uint32_t sparams;
302 uint16_t i;
303 uint16_t x;
304 uint16_t y;
305 uint16_t bit;
306 usb_error_t err = 0;
307
308 DPRINTF("start\n");
309
310 usb_callout_init_mtx(&sc->sc_tmo_pcd, &sc->sc_bus.bus_mtx, 0);
311 usb_callout_init_mtx(&sc->sc_tmo_poll, &sc->sc_bus.bus_mtx, 0);
312
313 sc->sc_offs = EHCI_CAPLENGTH(EREAD4(sc, EHCI_CAPLEN_HCIVERSION));
314
315#ifdef USB_DEBUG
316 if (ehciiaadbug)
317 sc->sc_flags |= EHCI_SCFLG_IAADBUG;
318 if (ehcilostintrbug)
319 sc->sc_flags |= EHCI_SCFLG_LOSTINTRBUG;
320 if (ehcidebug > 2) {
321 ehci_dump_regs(sc);
322 }
323#endif
324
325 version = EHCI_HCIVERSION(EREAD4(sc, EHCI_CAPLEN_HCIVERSION));
326 device_printf(sc->sc_bus.bdev, "EHCI version %x.%x\n",
327 version >> 8, version & 0xff);
328
329 sparams = EREAD4(sc, EHCI_HCSPARAMS);
330 DPRINTF("sparams=0x%x\n", sparams);
331
332 sc->sc_noport = EHCI_HCS_N_PORTS(sparams);
333 sc->sc_bus.usbrev = USB_REV_2_0;
334
335 /* Reset the controller */
336 DPRINTF("%s: resetting\n", device_get_nameunit(sc->sc_bus.bdev));
337
338 err = ehci_hcreset(sc);
339 if (err) {
340 device_printf(sc->sc_bus.bdev, "reset timeout\n");
341 return (err);
342 }
343 /*
344 * use current frame-list-size selection 0: 1024*4 bytes 1: 512*4
345 * bytes 2: 256*4 bytes 3: unknown
346 */
347 if (EHCI_CMD_FLS(EOREAD4(sc, EHCI_USBCMD)) == 3) {
348 device_printf(sc->sc_bus.bdev, "invalid frame-list-size\n");
349 return (USB_ERR_IOERROR);
350 }
351 /* set up the bus struct */
352 sc->sc_bus.methods = &ehci_bus_methods;
353
354 sc->sc_eintrs = EHCI_NORMAL_INTRS;
355
356 if (1) {
357 struct ehci_qh_sub *qh;
358
359 usbd_get_page(&sc->sc_hw.terminate_pc, 0, &buf_res);
360
361 qh = buf_res.buffer;
362
363 sc->sc_terminate_self = htohc32(sc, buf_res.physaddr);
364
365 /* init terminate TD */
366 qh->qtd_next =
367 htohc32(sc, EHCI_LINK_TERMINATE);
368 qh->qtd_altnext =
369 htohc32(sc, EHCI_LINK_TERMINATE);
370 qh->qtd_status =
371 htohc32(sc, EHCI_QTD_HALTED);
372 }
373
374 for (i = 0; i < EHCI_VIRTUAL_FRAMELIST_COUNT; i++) {
375 ehci_qh_t *qh;
376
377 usbd_get_page(sc->sc_hw.intr_start_pc + i, 0, &buf_res);
378
379 qh = buf_res.buffer;
380
381 /* initialize page cache pointer */
382
383 qh->page_cache = sc->sc_hw.intr_start_pc + i;
384
385 /* store a pointer to queue head */
386
387 sc->sc_intr_p_last[i] = qh;
388
389 qh->qh_self =
390 htohc32(sc, buf_res.physaddr) |
391 htohc32(sc, EHCI_LINK_QH);
392
393 qh->qh_endp =
394 htohc32(sc, EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH));
395 qh->qh_endphub =
396 htohc32(sc, EHCI_QH_SET_MULT(1));
397 qh->qh_curqtd = 0;
398
399 qh->qh_qtd.qtd_next =
400 htohc32(sc, EHCI_LINK_TERMINATE);
401 qh->qh_qtd.qtd_altnext =
402 htohc32(sc, EHCI_LINK_TERMINATE);
403 qh->qh_qtd.qtd_status =
404 htohc32(sc, EHCI_QTD_HALTED);
405 }
406
407 /*
408 * the QHs are arranged to give poll intervals that are
409 * powers of 2 times 1ms
410 */
411 bit = EHCI_VIRTUAL_FRAMELIST_COUNT / 2;
412 while (bit) {
413 x = bit;
414 while (x & bit) {
415 ehci_qh_t *qh_x;
416 ehci_qh_t *qh_y;
417
418 y = (x ^ bit) | (bit / 2);
419
420 qh_x = sc->sc_intr_p_last[x];
421 qh_y = sc->sc_intr_p_last[y];
422
423 /*
424 * the next QH has half the poll interval
425 */
426 qh_x->qh_link = qh_y->qh_self;
427
428 x++;
429 }
430 bit >>= 1;
431 }
432
433 if (1) {
434 ehci_qh_t *qh;
435
436 qh = sc->sc_intr_p_last[0];
437
438 /* the last (1ms) QH terminates */
439 qh->qh_link = htohc32(sc, EHCI_LINK_TERMINATE);
440 }
441 for (i = 0; i < EHCI_VIRTUAL_FRAMELIST_COUNT; i++) {
442 ehci_sitd_t *sitd;
443 ehci_itd_t *itd;
444
445 usbd_get_page(sc->sc_hw.isoc_fs_start_pc + i, 0, &buf_res);
446
447 sitd = buf_res.buffer;
448
449 /* initialize page cache pointer */
450
451 sitd->page_cache = sc->sc_hw.isoc_fs_start_pc + i;
452
453 /* store a pointer to the transfer descriptor */
454
455 sc->sc_isoc_fs_p_last[i] = sitd;
456
457 /* initialize full speed isochronous */
458
459 sitd->sitd_self =
460 htohc32(sc, buf_res.physaddr) |
461 htohc32(sc, EHCI_LINK_SITD);
462
463 sitd->sitd_back =
464 htohc32(sc, EHCI_LINK_TERMINATE);
465
466 sitd->sitd_next =
467 sc->sc_intr_p_last[i | (EHCI_VIRTUAL_FRAMELIST_COUNT / 2)]->qh_self;
468
469
470 usbd_get_page(sc->sc_hw.isoc_hs_start_pc + i, 0, &buf_res);
471
472 itd = buf_res.buffer;
473
474 /* initialize page cache pointer */
475
476 itd->page_cache = sc->sc_hw.isoc_hs_start_pc + i;
477
478 /* store a pointer to the transfer descriptor */
479
480 sc->sc_isoc_hs_p_last[i] = itd;
481
482 /* initialize high speed isochronous */
483
484 itd->itd_self =
485 htohc32(sc, buf_res.physaddr) |
486 htohc32(sc, EHCI_LINK_ITD);
487
488 itd->itd_next =
489 sitd->sitd_self;
490 }
491
492 usbd_get_page(&sc->sc_hw.pframes_pc, 0, &buf_res);
493
494 if (1) {
495 uint32_t *pframes;
496
497 pframes = buf_res.buffer;
498
499 /*
500 * execution order:
501 * pframes -> high speed isochronous ->
502 * full speed isochronous -> interrupt QH's
503 */
504 for (i = 0; i < EHCI_FRAMELIST_COUNT; i++) {
505 pframes[i] = sc->sc_isoc_hs_p_last
506 [i & (EHCI_VIRTUAL_FRAMELIST_COUNT - 1)]->itd_self;
507 }
508 }
509 usbd_get_page(&sc->sc_hw.async_start_pc, 0, &buf_res);
510
511 if (1) {
512
513 ehci_qh_t *qh;
514
515 qh = buf_res.buffer;
516
517 /* initialize page cache pointer */
518
519 qh->page_cache = &sc->sc_hw.async_start_pc;
520
521 /* store a pointer to the queue head */
522
523 sc->sc_async_p_last = qh;
524
525 /* init dummy QH that starts the async list */
526
527 qh->qh_self =
528 htohc32(sc, buf_res.physaddr) |
529 htohc32(sc, EHCI_LINK_QH);
530
531 /* fill the QH */
532 qh->qh_endp =
533 htohc32(sc, EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH) | EHCI_QH_HRECL);
534 qh->qh_endphub = htohc32(sc, EHCI_QH_SET_MULT(1));
535 qh->qh_link = qh->qh_self;
536 qh->qh_curqtd = 0;
537
538 /* fill the overlay qTD */
539 qh->qh_qtd.qtd_next = htohc32(sc, EHCI_LINK_TERMINATE);
540 qh->qh_qtd.qtd_altnext = htohc32(sc, EHCI_LINK_TERMINATE);
541 qh->qh_qtd.qtd_status = htohc32(sc, EHCI_QTD_HALTED);
542 }
543 /* flush all cache into memory */
544
545 usb_bus_mem_flush_all(&sc->sc_bus, &ehci_iterate_hw_softc);
546
547#ifdef USB_DEBUG
548 if (ehcidebug) {
549 ehci_dump_sqh(sc, sc->sc_async_p_last);
550 }
551#endif
552
553 /* finial setup */
554 err = ehci_init_sub(sc);
555
556 if (!err) {
557 /* catch any lost interrupts */
558 ehci_do_poll(&sc->sc_bus);
559 }
560 return (err);
561}
562
563/*
564 * shut down the controller when the system is going down
565 */
566void
567ehci_detach(ehci_softc_t *sc)
568{
569 USB_BUS_LOCK(&sc->sc_bus);
570
571 usb_callout_stop(&sc->sc_tmo_pcd);
572 usb_callout_stop(&sc->sc_tmo_poll);
573
574 EOWRITE4(sc, EHCI_USBINTR, 0);
575 USB_BUS_UNLOCK(&sc->sc_bus);
576
577 if (ehci_hcreset(sc)) {
578 DPRINTF("reset failed!\n");
579 }
580
581 /* XXX let stray task complete */
582 usb_pause_mtx(NULL, hz / 20);
583
584 usb_callout_drain(&sc->sc_tmo_pcd);
585 usb_callout_drain(&sc->sc_tmo_poll);
586}
587
588static void
589ehci_suspend(ehci_softc_t *sc)
590{
591 DPRINTF("stopping the HC\n");
592
593 /* reset HC */
594 ehci_hcreset(sc);
595}
596
597static void
598ehci_resume(ehci_softc_t *sc)
599{
600 /* reset HC */
601 ehci_hcreset(sc);
602
603 /* setup HC */
604 ehci_init_sub(sc);
605
606 /* catch any lost interrupts */
607 ehci_do_poll(&sc->sc_bus);
608}
609
610#ifdef USB_DEBUG
611static void
612ehci_dump_regs(ehci_softc_t *sc)
613{
614 uint32_t i;
615
616 i = EOREAD4(sc, EHCI_USBCMD);
617 printf("cmd=0x%08x\n", i);
618
619 if (i & EHCI_CMD_ITC_1)
620 printf(" EHCI_CMD_ITC_1\n");
621 if (i & EHCI_CMD_ITC_2)
622 printf(" EHCI_CMD_ITC_2\n");
623 if (i & EHCI_CMD_ITC_4)
624 printf(" EHCI_CMD_ITC_4\n");
625 if (i & EHCI_CMD_ITC_8)
626 printf(" EHCI_CMD_ITC_8\n");
627 if (i & EHCI_CMD_ITC_16)
628 printf(" EHCI_CMD_ITC_16\n");
629 if (i & EHCI_CMD_ITC_32)
630 printf(" EHCI_CMD_ITC_32\n");
631 if (i & EHCI_CMD_ITC_64)
632 printf(" EHCI_CMD_ITC_64\n");
633 if (i & EHCI_CMD_ASPME)
634 printf(" EHCI_CMD_ASPME\n");
635 if (i & EHCI_CMD_ASPMC)
636 printf(" EHCI_CMD_ASPMC\n");
637 if (i & EHCI_CMD_LHCR)
638 printf(" EHCI_CMD_LHCR\n");
639 if (i & EHCI_CMD_IAAD)
640 printf(" EHCI_CMD_IAAD\n");
641 if (i & EHCI_CMD_ASE)
642 printf(" EHCI_CMD_ASE\n");
643 if (i & EHCI_CMD_PSE)
644 printf(" EHCI_CMD_PSE\n");
645 if (i & EHCI_CMD_FLS_M)
646 printf(" EHCI_CMD_FLS_M\n");
647 if (i & EHCI_CMD_HCRESET)
648 printf(" EHCI_CMD_HCRESET\n");
649 if (i & EHCI_CMD_RS)
650 printf(" EHCI_CMD_RS\n");
651
652 i = EOREAD4(sc, EHCI_USBSTS);
653
654 printf("sts=0x%08x\n", i);
655
656 if (i & EHCI_STS_ASS)
657 printf(" EHCI_STS_ASS\n");
658 if (i & EHCI_STS_PSS)
659 printf(" EHCI_STS_PSS\n");
660 if (i & EHCI_STS_REC)
661 printf(" EHCI_STS_REC\n");
662 if (i & EHCI_STS_HCH)
663 printf(" EHCI_STS_HCH\n");
664 if (i & EHCI_STS_IAA)
665 printf(" EHCI_STS_IAA\n");
666 if (i & EHCI_STS_HSE)
667 printf(" EHCI_STS_HSE\n");
668 if (i & EHCI_STS_FLR)
669 printf(" EHCI_STS_FLR\n");
670 if (i & EHCI_STS_PCD)
671 printf(" EHCI_STS_PCD\n");
672 if (i & EHCI_STS_ERRINT)
673 printf(" EHCI_STS_ERRINT\n");
674 if (i & EHCI_STS_INT)
675 printf(" EHCI_STS_INT\n");
676
677 printf("ien=0x%08x\n",
678 EOREAD4(sc, EHCI_USBINTR));
679 printf("frindex=0x%08x ctrdsegm=0x%08x periodic=0x%08x async=0x%08x\n",
680 EOREAD4(sc, EHCI_FRINDEX),
681 EOREAD4(sc, EHCI_CTRLDSSEGMENT),
682 EOREAD4(sc, EHCI_PERIODICLISTBASE),
683 EOREAD4(sc, EHCI_ASYNCLISTADDR));
684 for (i = 1; i <= sc->sc_noport; i++) {
685 printf("port %d status=0x%08x\n", i,
686 EOREAD4(sc, EHCI_PORTSC(i)));
687 }
688}
689
690static void
691ehci_dump_link(ehci_softc_t *sc, uint32_t link, int type)
692{
693 link = hc32toh(sc, link);
694 printf("0x%08x", link);
695 if (link & EHCI_LINK_TERMINATE)
696 printf("<T>");
697 else {
698 printf("<");
699 if (type) {
700 switch (EHCI_LINK_TYPE(link)) {
701 case EHCI_LINK_ITD:
702 printf("ITD");
703 break;
704 case EHCI_LINK_QH:
705 printf("QH");
706 break;
707 case EHCI_LINK_SITD:
708 printf("SITD");
709 break;
710 case EHCI_LINK_FSTN:
711 printf("FSTN");
712 break;
713 }
714 }
715 printf(">");
716 }
717}
718
719static void
720ehci_dump_qtd(ehci_softc_t *sc, ehci_qtd_t *qtd)
721{
722 uint32_t s;
723
724 printf(" next=");
725 ehci_dump_link(sc, qtd->qtd_next, 0);
726 printf(" altnext=");
727 ehci_dump_link(sc, qtd->qtd_altnext, 0);
728 printf("\n");
729 s = hc32toh(sc, qtd->qtd_status);
730 printf(" status=0x%08x: toggle=%d bytes=0x%x ioc=%d c_page=0x%x\n",
731 s, EHCI_QTD_GET_TOGGLE(s), EHCI_QTD_GET_BYTES(s),
732 EHCI_QTD_GET_IOC(s), EHCI_QTD_GET_C_PAGE(s));
733 printf(" cerr=%d pid=%d stat=%s%s%s%s%s%s%s%s\n",
734 EHCI_QTD_GET_CERR(s), EHCI_QTD_GET_PID(s),
735 (s & EHCI_QTD_ACTIVE) ? "ACTIVE" : "NOT_ACTIVE",
736 (s & EHCI_QTD_HALTED) ? "-HALTED" : "",
737 (s & EHCI_QTD_BUFERR) ? "-BUFERR" : "",
738 (s & EHCI_QTD_BABBLE) ? "-BABBLE" : "",
739 (s & EHCI_QTD_XACTERR) ? "-XACTERR" : "",
740 (s & EHCI_QTD_MISSEDMICRO) ? "-MISSED" : "",
741 (s & EHCI_QTD_SPLITXSTATE) ? "-SPLIT" : "",
742 (s & EHCI_QTD_PINGSTATE) ? "-PING" : "");
743
744 for (s = 0; s < 5; s++) {
745 printf(" buffer[%d]=0x%08x\n", s,
746 hc32toh(sc, qtd->qtd_buffer[s]));
747 }
748 for (s = 0; s < 5; s++) {
749 printf(" buffer_hi[%d]=0x%08x\n", s,
750 hc32toh(sc, qtd->qtd_buffer_hi[s]));
751 }
752}
753
754static uint8_t
755ehci_dump_sqtd(ehci_softc_t *sc, ehci_qtd_t *sqtd)
756{
757 uint8_t temp;
758
759 usb_pc_cpu_invalidate(sqtd->page_cache);
760 printf("QTD(%p) at 0x%08x:\n", sqtd, hc32toh(sc, sqtd->qtd_self));
761 ehci_dump_qtd(sc, sqtd);
762 temp = (sqtd->qtd_next & htohc32(sc, EHCI_LINK_TERMINATE)) ? 1 : 0;
763 return (temp);
764}
765
766static void
767ehci_dump_sqtds(ehci_softc_t *sc, ehci_qtd_t *sqtd)
768{
769 uint16_t i;
770 uint8_t stop;
771
772 stop = 0;
773 for (i = 0; sqtd && (i < 20) && !stop; sqtd = sqtd->obj_next, i++) {
774 stop = ehci_dump_sqtd(sc, sqtd);
775 }
776 if (sqtd) {
777 printf("dump aborted, too many TDs\n");
778 }
779}
780
781static void
782ehci_dump_sqh(ehci_softc_t *sc, ehci_qh_t *qh)
783{
784 uint32_t endp;
785 uint32_t endphub;
786
787 usb_pc_cpu_invalidate(qh->page_cache);
788 printf("QH(%p) at 0x%08x:\n", qh, hc32toh(sc, qh->qh_self) & ~0x1F);
789 printf(" link=");
790 ehci_dump_link(sc, qh->qh_link, 1);
791 printf("\n");
792 endp = hc32toh(sc, qh->qh_endp);
793 printf(" endp=0x%08x\n", endp);
794 printf(" addr=0x%02x inact=%d endpt=%d eps=%d dtc=%d hrecl=%d\n",
795 EHCI_QH_GET_ADDR(endp), EHCI_QH_GET_INACT(endp),
796 EHCI_QH_GET_ENDPT(endp), EHCI_QH_GET_EPS(endp),
797 EHCI_QH_GET_DTC(endp), EHCI_QH_GET_HRECL(endp));
798 printf(" mpl=0x%x ctl=%d nrl=%d\n",
799 EHCI_QH_GET_MPL(endp), EHCI_QH_GET_CTL(endp),
800 EHCI_QH_GET_NRL(endp));
801 endphub = hc32toh(sc, qh->qh_endphub);
802 printf(" endphub=0x%08x\n", endphub);
803 printf(" smask=0x%02x cmask=0x%02x huba=0x%02x port=%d mult=%d\n",
804 EHCI_QH_GET_SMASK(endphub), EHCI_QH_GET_CMASK(endphub),
805 EHCI_QH_GET_HUBA(endphub), EHCI_QH_GET_PORT(endphub),
806 EHCI_QH_GET_MULT(endphub));
807 printf(" curqtd=");
808 ehci_dump_link(sc, qh->qh_curqtd, 0);
809 printf("\n");
810 printf("Overlay qTD:\n");
811 ehci_dump_qtd(sc, (void *)&qh->qh_qtd);
812}
813
814static void
815ehci_dump_sitd(ehci_softc_t *sc, ehci_sitd_t *sitd)
816{
817 usb_pc_cpu_invalidate(sitd->page_cache);
818 printf("SITD(%p) at 0x%08x\n", sitd, hc32toh(sc, sitd->sitd_self) & ~0x1F);
819 printf(" next=0x%08x\n", hc32toh(sc, sitd->sitd_next));
820 printf(" portaddr=0x%08x dir=%s addr=%d endpt=0x%x port=0x%x huba=0x%x\n",
821 hc32toh(sc, sitd->sitd_portaddr),
822 (sitd->sitd_portaddr & htohc32(sc, EHCI_SITD_SET_DIR_IN))
823 ? "in" : "out",
824 EHCI_SITD_GET_ADDR(hc32toh(sc, sitd->sitd_portaddr)),
825 EHCI_SITD_GET_ENDPT(hc32toh(sc, sitd->sitd_portaddr)),
826 EHCI_SITD_GET_PORT(hc32toh(sc, sitd->sitd_portaddr)),
827 EHCI_SITD_GET_HUBA(hc32toh(sc, sitd->sitd_portaddr)));
828 printf(" mask=0x%08x\n", hc32toh(sc, sitd->sitd_mask));
829 printf(" status=0x%08x <%s> len=0x%x\n", hc32toh(sc, sitd->sitd_status),
830 (sitd->sitd_status & htohc32(sc, EHCI_SITD_ACTIVE)) ? "ACTIVE" : "",
831 EHCI_SITD_GET_LEN(hc32toh(sc, sitd->sitd_status)));
832 printf(" back=0x%08x, bp=0x%08x,0x%08x,0x%08x,0x%08x\n",
833 hc32toh(sc, sitd->sitd_back),
834 hc32toh(sc, sitd->sitd_bp[0]),
835 hc32toh(sc, sitd->sitd_bp[1]),
836 hc32toh(sc, sitd->sitd_bp_hi[0]),
837 hc32toh(sc, sitd->sitd_bp_hi[1]));
838}
839
840static void
841ehci_dump_itd(ehci_softc_t *sc, ehci_itd_t *itd)
842{
843 usb_pc_cpu_invalidate(itd->page_cache);
844 printf("ITD(%p) at 0x%08x\n", itd, hc32toh(sc, itd->itd_self) & ~0x1F);
845 printf(" next=0x%08x\n", hc32toh(sc, itd->itd_next));
846 printf(" status[0]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[0]),
847 (itd->itd_status[0] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : "");
848 printf(" status[1]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[1]),
849 (itd->itd_status[1] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : "");
850 printf(" status[2]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[2]),
851 (itd->itd_status[2] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : "");
852 printf(" status[3]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[3]),
853 (itd->itd_status[3] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : "");
854 printf(" status[4]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[4]),
855 (itd->itd_status[4] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : "");
856 printf(" status[5]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[5]),
857 (itd->itd_status[5] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : "");
858 printf(" status[6]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[6]),
859 (itd->itd_status[6] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : "");
860 printf(" status[7]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[7]),
861 (itd->itd_status[7] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : "");
862 printf(" bp[0]=0x%08x\n", hc32toh(sc, itd->itd_bp[0]));
863 printf(" addr=0x%02x; endpt=0x%01x\n",
864 EHCI_ITD_GET_ADDR(hc32toh(sc, itd->itd_bp[0])),
865 EHCI_ITD_GET_ENDPT(hc32toh(sc, itd->itd_bp[0])));
866 printf(" bp[1]=0x%08x\n", hc32toh(sc, itd->itd_bp[1]));
867 printf(" dir=%s; mpl=0x%02x\n",
868 (hc32toh(sc, itd->itd_bp[1]) & EHCI_ITD_SET_DIR_IN) ? "in" : "out",
869 EHCI_ITD_GET_MPL(hc32toh(sc, itd->itd_bp[1])));
870 printf(" bp[2..6]=0x%08x,0x%08x,0x%08x,0x%08x,0x%08x\n",
871 hc32toh(sc, itd->itd_bp[2]),
872 hc32toh(sc, itd->itd_bp[3]),
873 hc32toh(sc, itd->itd_bp[4]),
874 hc32toh(sc, itd->itd_bp[5]),
875 hc32toh(sc, itd->itd_bp[6]));
876 printf(" bp_hi=0x%08x,0x%08x,0x%08x,0x%08x,\n"
877 " 0x%08x,0x%08x,0x%08x\n",
878 hc32toh(sc, itd->itd_bp_hi[0]),
879 hc32toh(sc, itd->itd_bp_hi[1]),
880 hc32toh(sc, itd->itd_bp_hi[2]),
881 hc32toh(sc, itd->itd_bp_hi[3]),
882 hc32toh(sc, itd->itd_bp_hi[4]),
883 hc32toh(sc, itd->itd_bp_hi[5]),
884 hc32toh(sc, itd->itd_bp_hi[6]));
885}
886
887static void
888ehci_dump_isoc(ehci_softc_t *sc)
889{
890 ehci_itd_t *itd;
891 ehci_sitd_t *sitd;
892 uint16_t max = 1000;
893 uint16_t pos;
894
895 pos = (EOREAD4(sc, EHCI_FRINDEX) / 8) &
896 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1);
897
898 printf("%s: isochronous dump from frame 0x%03x:\n",
899 __FUNCTION__, pos);
900
901 itd = sc->sc_isoc_hs_p_last[pos];
902 sitd = sc->sc_isoc_fs_p_last[pos];
903
904 while (itd && max && max--) {
905 ehci_dump_itd(sc, itd);
906 itd = itd->prev;
907 }
908
909 while (sitd && max && max--) {
910 ehci_dump_sitd(sc, sitd);
911 sitd = sitd->prev;
912 }
913}
914
915#endif
916
917static void
918ehci_transfer_intr_enqueue(struct usb_xfer *xfer)
919{
920 /* check for early completion */
921 if (ehci_check_transfer(xfer)) {
922 return;
923 }
924 /* put transfer on interrupt queue */
925 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer);
926
927 /* start timeout, if any */
928 if (xfer->timeout != 0) {
929 usbd_transfer_timeout_ms(xfer, &ehci_timeout, xfer->timeout);
930 }
931}
932
933#define EHCI_APPEND_FS_TD(std,last) (last) = _ehci_append_fs_td(std,last)
934static ehci_sitd_t *
935_ehci_append_fs_td(ehci_sitd_t *std, ehci_sitd_t *last)
936{
937 DPRINTFN(11, "%p to %p\n", std, last);
938
939 /* (sc->sc_bus.mtx) must be locked */
940
941 std->next = last->next;
942 std->sitd_next = last->sitd_next;
943
944 std->prev = last;
945
946 usb_pc_cpu_flush(std->page_cache);
947
948 /*
949 * the last->next->prev is never followed: std->next->prev = std;
950 */
951 last->next = std;
952 last->sitd_next = std->sitd_self;
953
954 usb_pc_cpu_flush(last->page_cache);
955
956 return (std);
957}
958
959#define EHCI_APPEND_HS_TD(std,last) (last) = _ehci_append_hs_td(std,last)
960static ehci_itd_t *
961_ehci_append_hs_td(ehci_itd_t *std, ehci_itd_t *last)
962{
963 DPRINTFN(11, "%p to %p\n", std, last);
964
965 /* (sc->sc_bus.mtx) must be locked */
966
967 std->next = last->next;
968 std->itd_next = last->itd_next;
969
970 std->prev = last;
971
972 usb_pc_cpu_flush(std->page_cache);
973
974 /*
975 * the last->next->prev is never followed: std->next->prev = std;
976 */
977 last->next = std;
978 last->itd_next = std->itd_self;
979
980 usb_pc_cpu_flush(last->page_cache);
981
982 return (std);
983}
984
985#define EHCI_APPEND_QH(sqh,last) (last) = _ehci_append_qh(sqh,last)
986static ehci_qh_t *
987_ehci_append_qh(ehci_qh_t *sqh, ehci_qh_t *last)
988{
989 DPRINTFN(11, "%p to %p\n", sqh, last);
990
991 if (sqh->prev != NULL) {
992 /* should not happen */
993 DPRINTFN(0, "QH already linked!\n");
994 return (last);
995 }
996 /* (sc->sc_bus.mtx) must be locked */
997
998 sqh->next = last->next;
999 sqh->qh_link = last->qh_link;
1000
1001 sqh->prev = last;
1002
1003 usb_pc_cpu_flush(sqh->page_cache);
1004
1005 /*
1006 * the last->next->prev is never followed: sqh->next->prev = sqh;
1007 */
1008
1009 last->next = sqh;
1010 last->qh_link = sqh->qh_self;
1011
1012 usb_pc_cpu_flush(last->page_cache);
1013
1014 return (sqh);
1015}
1016
1017#define EHCI_REMOVE_FS_TD(std,last) (last) = _ehci_remove_fs_td(std,last)
1018static ehci_sitd_t *
1019_ehci_remove_fs_td(ehci_sitd_t *std, ehci_sitd_t *last)
1020{
1021 DPRINTFN(11, "%p from %p\n", std, last);
1022
1023 /* (sc->sc_bus.mtx) must be locked */
1024
1025 std->prev->next = std->next;
1026 std->prev->sitd_next = std->sitd_next;
1027
1028 usb_pc_cpu_flush(std->prev->page_cache);
1029
1030 if (std->next) {
1031 std->next->prev = std->prev;
1032 usb_pc_cpu_flush(std->next->page_cache);
1033 }
1034 return ((last == std) ? std->prev : last);
1035}
1036
1037#define EHCI_REMOVE_HS_TD(std,last) (last) = _ehci_remove_hs_td(std,last)
1038static ehci_itd_t *
1039_ehci_remove_hs_td(ehci_itd_t *std, ehci_itd_t *last)
1040{
1041 DPRINTFN(11, "%p from %p\n", std, last);
1042
1043 /* (sc->sc_bus.mtx) must be locked */
1044
1045 std->prev->next = std->next;
1046 std->prev->itd_next = std->itd_next;
1047
1048 usb_pc_cpu_flush(std->prev->page_cache);
1049
1050 if (std->next) {
1051 std->next->prev = std->prev;
1052 usb_pc_cpu_flush(std->next->page_cache);
1053 }
1054 return ((last == std) ? std->prev : last);
1055}
1056
1057#define EHCI_REMOVE_QH(sqh,last) (last) = _ehci_remove_qh(sqh,last)
1058static ehci_qh_t *
1059_ehci_remove_qh(ehci_qh_t *sqh, ehci_qh_t *last)
1060{
1061 DPRINTFN(11, "%p from %p\n", sqh, last);
1062
1063 /* (sc->sc_bus.mtx) must be locked */
1064
1065 /* only remove if not removed from a queue */
1066 if (sqh->prev) {
1067
1068 sqh->prev->next = sqh->next;
1069 sqh->prev->qh_link = sqh->qh_link;
1070
1071 usb_pc_cpu_flush(sqh->prev->page_cache);
1072
1073 if (sqh->next) {
1074 sqh->next->prev = sqh->prev;
1075 usb_pc_cpu_flush(sqh->next->page_cache);
1076 }
1077 last = ((last == sqh) ? sqh->prev : last);
1078
1079 sqh->prev = 0;
1080
1081 usb_pc_cpu_flush(sqh->page_cache);
1082 }
1083 return (last);
1084}
1085
1086static void
1087ehci_data_toggle_update(struct usb_xfer *xfer, uint16_t actlen, uint16_t xlen)
1088{
1089 uint16_t rem;
1090 uint8_t dt;
1091
1092 /* count number of full packets */
1093 dt = (actlen / xfer->max_packet_size) & 1;
1094
1095 /* compute remainder */
1096 rem = actlen % xfer->max_packet_size;
1097
1098 if (rem > 0)
1099 dt ^= 1; /* short packet at the end */
1100 else if (actlen != xlen)
1101 dt ^= 1; /* zero length packet at the end */
1102 else if (xlen == 0)
1103 dt ^= 1; /* zero length transfer */
1104
1105 xfer->endpoint->toggle_next ^= dt;
1106}
1107
1108static usb_error_t
1109ehci_non_isoc_done_sub(struct usb_xfer *xfer)
1110{
1111 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
1112 ehci_qtd_t *td;
1113 ehci_qtd_t *td_alt_next;
1114 uint32_t status;
1115 uint16_t len;
1116
1117 td = xfer->td_transfer_cache;
1118 td_alt_next = td->alt_next;
1119
1120 if (xfer->aframes != xfer->nframes) {
1121 usbd_xfer_set_frame_len(xfer, xfer->aframes, 0);
1122 }
1123 while (1) {
1124
1125 usb_pc_cpu_invalidate(td->page_cache);
1126 status = hc32toh(sc, td->qtd_status);
1127
1128 len = EHCI_QTD_GET_BYTES(status);
1129
1130 /*
1131 * Verify the status length and
1132 * add the length to "frlengths[]":
1133 */
1134 if (len > td->len) {
1135 /* should not happen */
1136 DPRINTF("Invalid status length, "
1137 "0x%04x/0x%04x bytes\n", len, td->len);
1138 status |= EHCI_QTD_HALTED;
1139 } else if (xfer->aframes != xfer->nframes) {
1140 xfer->frlengths[xfer->aframes] += td->len - len;
1141 /* manually update data toggle */
1142 ehci_data_toggle_update(xfer, td->len - len, td->len);
1143 }
1144
1145 /* Check for last transfer */
1146 if (((void *)td) == xfer->td_transfer_last) {
1147 td = NULL;
1148 break;
1149 }
1150 /* Check for transfer error */
1151 if (status & EHCI_QTD_HALTED) {
1152 /* the transfer is finished */
1153 td = NULL;
1154 break;
1155 }
1156 /* Check for short transfer */
1157 if (len > 0) {
1158 if (xfer->flags_int.short_frames_ok) {
1159 /* follow alt next */
1160 td = td->alt_next;
1161 } else {
1162 /* the transfer is finished */
1163 td = NULL;
1164 }
1165 break;
1166 }
1167 td = td->obj_next;
1168
1169 if (td->alt_next != td_alt_next) {
1170 /* this USB frame is complete */
1171 break;
1172 }
1173 }
1174
1175 /* update transfer cache */
1176
1177 xfer->td_transfer_cache = td;
1178
1179#ifdef USB_DEBUG
1180 if (status & EHCI_QTD_STATERRS) {
1181 DPRINTFN(11, "error, addr=%d, endpt=0x%02x, frame=0x%02x"
1182 "status=%s%s%s%s%s%s%s%s\n",
1183 xfer->address, xfer->endpointno, xfer->aframes,
1184 (status & EHCI_QTD_ACTIVE) ? "[ACTIVE]" : "[NOT_ACTIVE]",
1185 (status & EHCI_QTD_HALTED) ? "[HALTED]" : "",
1186 (status & EHCI_QTD_BUFERR) ? "[BUFERR]" : "",
1187 (status & EHCI_QTD_BABBLE) ? "[BABBLE]" : "",
1188 (status & EHCI_QTD_XACTERR) ? "[XACTERR]" : "",
1189 (status & EHCI_QTD_MISSEDMICRO) ? "[MISSED]" : "",
1190 (status & EHCI_QTD_SPLITXSTATE) ? "[SPLIT]" : "",
1191 (status & EHCI_QTD_PINGSTATE) ? "[PING]" : "");
1192 }
1193#endif
1194
1195 return ((status & EHCI_QTD_HALTED) ?
1196 USB_ERR_STALLED : USB_ERR_NORMAL_COMPLETION);
1197}
1198
1199static void
1200ehci_non_isoc_done(struct usb_xfer *xfer)
1201{
1202 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
1203 ehci_qh_t *qh;
1204 uint32_t status;
1205 usb_error_t err = 0;
1206
1207 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n",
1208 xfer, xfer->endpoint);
1209
1210#ifdef USB_DEBUG
1211 if (ehcidebug > 10) {
1212 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
1213
1214 ehci_dump_sqtds(sc, xfer->td_transfer_first);
1215 }
1216#endif
1217
1218 /* extract data toggle directly from the QH's overlay area */
1219
1220 qh = xfer->qh_start[xfer->flags_int.curr_dma_set];
1221
1222 usb_pc_cpu_invalidate(qh->page_cache);
1223
1224 status = hc32toh(sc, qh->qh_qtd.qtd_status);
1225
1226 /* reset scanner */
1227
1228 xfer->td_transfer_cache = xfer->td_transfer_first;
1229
1230 if (xfer->flags_int.control_xfr) {
1231
1232 if (xfer->flags_int.control_hdr) {
1233
1234 err = ehci_non_isoc_done_sub(xfer);
1235 }
1236 xfer->aframes = 1;
1237
1238 if (xfer->td_transfer_cache == NULL) {
1239 goto done;
1240 }
1241 }
1242 while (xfer->aframes != xfer->nframes) {
1243
1244 err = ehci_non_isoc_done_sub(xfer);
1245 xfer->aframes++;
1246
1247 if (xfer->td_transfer_cache == NULL) {
1248 goto done;
1249 }
1250 }
1251
1252 if (xfer->flags_int.control_xfr &&
1253 !xfer->flags_int.control_act) {
1254
1255 err = ehci_non_isoc_done_sub(xfer);
1256 }
1257done:
1258 ehci_device_done(xfer, err);
1259}
1260
1261/*------------------------------------------------------------------------*
1262 * ehci_check_transfer
1263 *
1264 * Return values:
1265 * 0: USB transfer is not finished
1266 * Else: USB transfer is finished
1267 *------------------------------------------------------------------------*/
1268static uint8_t
1269ehci_check_transfer(struct usb_xfer *xfer)
1270{
1271 struct usb_pipe_methods *methods = xfer->endpoint->methods;
1272 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
1273
1274 uint32_t status;
1275
1276 DPRINTFN(13, "xfer=%p checking transfer\n", xfer);
1277
1278 if (methods == &ehci_device_isoc_fs_methods) {
1279 ehci_sitd_t *td;
1280
1281 /* isochronous full speed transfer */
1282
1283 td = xfer->td_transfer_last;
1284 usb_pc_cpu_invalidate(td->page_cache);
1285 status = hc32toh(sc, td->sitd_status);
1286
1287 /* also check if first is complete */
1288
1289 td = xfer->td_transfer_first;
1290 usb_pc_cpu_invalidate(td->page_cache);
1291 status |= hc32toh(sc, td->sitd_status);
1292
1293 if (!(status & EHCI_SITD_ACTIVE)) {
1294 ehci_device_done(xfer, USB_ERR_NORMAL_COMPLETION);
1295 goto transferred;
1296 }
1297 } else if (methods == &ehci_device_isoc_hs_methods) {
1298 ehci_itd_t *td;
1299
1300 /* isochronous high speed transfer */
1301
1302 /* check last transfer */
1303 td = xfer->td_transfer_last;
1304 usb_pc_cpu_invalidate(td->page_cache);
1305 status = td->itd_status[0];
1306 status |= td->itd_status[1];
1307 status |= td->itd_status[2];
1308 status |= td->itd_status[3];
1309 status |= td->itd_status[4];
1310 status |= td->itd_status[5];
1311 status |= td->itd_status[6];
1312 status |= td->itd_status[7];
1313
1314 /* also check first transfer */
1315 td = xfer->td_transfer_first;
1316 usb_pc_cpu_invalidate(td->page_cache);
1317 status |= td->itd_status[0];
1318 status |= td->itd_status[1];
1319 status |= td->itd_status[2];
1320 status |= td->itd_status[3];
1321 status |= td->itd_status[4];
1322 status |= td->itd_status[5];
1323 status |= td->itd_status[6];
1324 status |= td->itd_status[7];
1325
1326 /* if no transactions are active we continue */
1327 if (!(status & htohc32(sc, EHCI_ITD_ACTIVE))) {
1328 ehci_device_done(xfer, USB_ERR_NORMAL_COMPLETION);
1329 goto transferred;
1330 }
1331 } else {
1332 ehci_qtd_t *td;
1333 ehci_qh_t *qh;
1334
1335 /* non-isochronous transfer */
1336
1337 /*
1338 * check whether there is an error somewhere in the middle,
1339 * or whether there was a short packet (SPD and not ACTIVE)
1340 */
1341 td = xfer->td_transfer_cache;
1342
1343 qh = xfer->qh_start[xfer->flags_int.curr_dma_set];
1344
1345 usb_pc_cpu_invalidate(qh->page_cache);
1346
1347 status = hc32toh(sc, qh->qh_qtd.qtd_status);
1348 if (status & EHCI_QTD_ACTIVE) {
1349 /* transfer is pending */
1350 goto done;
1351 }
1352
1353 while (1) {
1354 usb_pc_cpu_invalidate(td->page_cache);
1355 status = hc32toh(sc, td->qtd_status);
1356
1357 /*
1358 * Check if there is an active TD which
1359 * indicates that the transfer isn't done.
1360 */
1361 if (status & EHCI_QTD_ACTIVE) {
1362 /* update cache */
1363 xfer->td_transfer_cache = td;
1364 goto done;
1365 }
1366 /*
1367 * last transfer descriptor makes the transfer done
1368 */
1369 if (((void *)td) == xfer->td_transfer_last) {
1370 break;
1371 }
1372 /*
1373 * any kind of error makes the transfer done
1374 */
1375 if (status & EHCI_QTD_HALTED) {
1376 break;
1377 }
1378 /*
1379 * if there is no alternate next transfer, a short
1380 * packet also makes the transfer done
1381 */
1382 if (EHCI_QTD_GET_BYTES(status)) {
1383 if (xfer->flags_int.short_frames_ok) {
1384 /* follow alt next */
1385 if (td->alt_next) {
1386 td = td->alt_next;
1387 continue;
1388 }
1389 }
1390 /* transfer is done */
1391 break;
1392 }
1393 td = td->obj_next;
1394 }
1395 ehci_non_isoc_done(xfer);
1396 goto transferred;
1397 }
1398
1399done:
1400 DPRINTFN(13, "xfer=%p is still active\n", xfer);
1401 return (0);
1402
1403transferred:
1404 return (1);
1405}
1406
1407static void
1408ehci_pcd_enable(ehci_softc_t *sc)
1409{
1410 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
1411
1412 sc->sc_eintrs |= EHCI_STS_PCD;
1413 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs);
1414
1415 /* acknowledge any PCD interrupt */
1416 EOWRITE4(sc, EHCI_USBSTS, EHCI_STS_PCD);
1417
1418 ehci_root_intr(sc);
1419}
1420
1421static void
1422ehci_interrupt_poll(ehci_softc_t *sc)
1423{
1424 struct usb_xfer *xfer;
1425
1426repeat:
1427 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
1428 /*
1429 * check if transfer is transferred
1430 */
1431 if (ehci_check_transfer(xfer)) {
1432 /* queue has been modified */
1433 goto repeat;
1434 }
1435 }
1436}
1437
1438/*
1439 * Some EHCI chips from VIA / ATI seem to trigger interrupts before
1440 * writing back the qTD status, or miss signalling occasionally under
1441 * heavy load. If the host machine is too fast, we can miss
1442 * transaction completion - when we scan the active list the
1443 * transaction still seems to be active. This generally exhibits
1444 * itself as a umass stall that never recovers.
1445 *
1446 * We work around this behaviour by setting up this callback after any
1447 * softintr that completes with transactions still pending, giving us
1448 * another chance to check for completion after the writeback has
1449 * taken place.
1450 */
1451static void
1452ehci_poll_timeout(void *arg)
1453{
1454 ehci_softc_t *sc = arg;
1455
1456 DPRINTFN(3, "\n");
1457 ehci_interrupt_poll(sc);
1458}
1459
1460/*------------------------------------------------------------------------*
1461 * ehci_interrupt - EHCI interrupt handler
1462 *
1463 * NOTE: Do not access "sc->sc_bus.bdev" inside the interrupt handler,
1464 * hence the interrupt handler will be setup before "sc->sc_bus.bdev"
1465 * is present !
1466 *------------------------------------------------------------------------*/
1467void
1468ehci_interrupt(ehci_softc_t *sc)
1469{
1470 uint32_t status;
1471
1472 USB_BUS_LOCK(&sc->sc_bus);
1473
1474 DPRINTFN(16, "real interrupt\n");
1475
1476#ifdef USB_DEBUG
1477 if (ehcidebug > 15) {
1478 ehci_dump_regs(sc);
1479 }
1480#endif
1481
1482 status = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS));
1483 if (status == 0) {
1484 /* the interrupt was not for us */
1485 goto done;
1486 }
1487 if (!(status & sc->sc_eintrs)) {
1488 goto done;
1489 }
1490 EOWRITE4(sc, EHCI_USBSTS, status); /* acknowledge */
1491
1492 status &= sc->sc_eintrs;
1493
1494 if (status & EHCI_STS_HSE) {
1495 printf("%s: unrecoverable error, "
1496 "controller halted\n", __FUNCTION__);
1497#ifdef USB_DEBUG
1498 ehci_dump_regs(sc);
1499 ehci_dump_isoc(sc);
1500#endif
1501 }
1502 if (status & EHCI_STS_PCD) {
1503 /*
1504 * Disable PCD interrupt for now, because it will be
1505 * on until the port has been reset.
1506 */
1507 sc->sc_eintrs &= ~EHCI_STS_PCD;
1508 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs);
1509
1510 ehci_root_intr(sc);
1511
1512 /* do not allow RHSC interrupts > 1 per second */
1513 usb_callout_reset(&sc->sc_tmo_pcd, hz,
1514 (void *)&ehci_pcd_enable, sc);
1515 }
1516 status &= ~(EHCI_STS_INT | EHCI_STS_ERRINT | EHCI_STS_PCD | EHCI_STS_IAA);
1517
1518 if (status != 0) {
1519 /* block unprocessed interrupts */
1520 sc->sc_eintrs &= ~status;
1521 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs);
1522 printf("%s: blocking interrupts 0x%x\n", __FUNCTION__, status);
1523 }
1524 /* poll all the USB transfers */
1525 ehci_interrupt_poll(sc);
1526
1527 if (sc->sc_flags & EHCI_SCFLG_LOSTINTRBUG) {
1528 usb_callout_reset(&sc->sc_tmo_poll, hz / 128,
1529 (void *)&ehci_poll_timeout, sc);
1530 }
1531
1532done:
1533 USB_BUS_UNLOCK(&sc->sc_bus);
1534}
1535
1536/*
1537 * called when a request does not complete
1538 */
1539static void
1540ehci_timeout(void *arg)
1541{
1542 struct usb_xfer *xfer = arg;
1543
1544 DPRINTF("xfer=%p\n", xfer);
1545
1546 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED);
1547
1548 /* transfer is transferred */
1549 ehci_device_done(xfer, USB_ERR_TIMEOUT);
1550}
1551
1552static void
1553ehci_do_poll(struct usb_bus *bus)
1554{
1555 ehci_softc_t *sc = EHCI_BUS2SC(bus);
1556
1557 USB_BUS_LOCK(&sc->sc_bus);
1558 ehci_interrupt_poll(sc);
1559 USB_BUS_UNLOCK(&sc->sc_bus);
1560}
1561
1562static void
1563ehci_setup_standard_chain_sub(struct ehci_std_temp *temp)
1564{
1565 struct usb_page_search buf_res;
1566 ehci_qtd_t *td;
1567 ehci_qtd_t *td_next;
1568 ehci_qtd_t *td_alt_next;
1569 uint32_t buf_offset;
1570 uint32_t average;
1571 uint32_t len_old;
1572 uint32_t terminate;
1573 uint32_t qtd_altnext;
1574 uint8_t shortpkt_old;
1575 uint8_t precompute;
1576
1577 terminate = temp->sc->sc_terminate_self;
1578 qtd_altnext = temp->sc->sc_terminate_self;
1579 td_alt_next = NULL;
1580 buf_offset = 0;
1581 shortpkt_old = temp->shortpkt;
1582 len_old = temp->len;
1583 precompute = 1;
1584
1585restart:
1586
1587 td = temp->td;
1588 td_next = temp->td_next;
1589
1590 while (1) {
1591
1592 if (temp->len == 0) {
1593
1594 if (temp->shortpkt) {
1595 break;
1596 }
1597 /* send a Zero Length Packet, ZLP, last */
1598
1599 temp->shortpkt = 1;
1600 average = 0;
1601
1602 } else {
1603
1604 average = temp->average;
1605
1606 if (temp->len < average) {
1607 if (temp->len % temp->max_frame_size) {
1608 temp->shortpkt = 1;
1609 }
1610 average = temp->len;
1611 }
1612 }
1613
1614 if (td_next == NULL) {
1615 panic("%s: out of EHCI transfer descriptors!", __FUNCTION__);
1616 }
1617 /* get next TD */
1618
1619 td = td_next;
1620 td_next = td->obj_next;
1621
1622 /* check if we are pre-computing */
1623
1624 if (precompute) {
1625
1626 /* update remaining length */
1627
1628 temp->len -= average;
1629
1630 continue;
1631 }
1632 /* fill out current TD */
1633
1634 td->qtd_status =
1635 temp->qtd_status |
1636 htohc32(temp->sc, EHCI_QTD_IOC |
1637 EHCI_QTD_SET_BYTES(average));
1638
1639 if (average == 0) {
1640
1641 if (temp->auto_data_toggle == 0) {
1642
1643 /* update data toggle, ZLP case */
1644
1645 temp->qtd_status ^=
1646 htohc32(temp->sc, EHCI_QTD_TOGGLE_MASK);
1647 }
1648 td->len = 0;
1649
1650 td->qtd_buffer[0] = 0;
1651 td->qtd_buffer_hi[0] = 0;
1652
1653 td->qtd_buffer[1] = 0;
1654 td->qtd_buffer_hi[1] = 0;
1655
1656 } else {
1657
1658 uint8_t x;
1659
1660 if (temp->auto_data_toggle == 0) {
1661
1662 /* update data toggle */
1663
1664 if (((average + temp->max_frame_size - 1) /
1665 temp->max_frame_size) & 1) {
1666 temp->qtd_status ^=
1667 htohc32(temp->sc, EHCI_QTD_TOGGLE_MASK);
1668 }
1669 }
1670 td->len = average;
1671
1672 /* update remaining length */
1673
1674 temp->len -= average;
1675
1676 /* fill out buffer pointers */
1677
1678 usbd_get_page(temp->pc, buf_offset, &buf_res);
1679 td->qtd_buffer[0] =
1680 htohc32(temp->sc, buf_res.physaddr);
1681 td->qtd_buffer_hi[0] = 0;
1682
1683 x = 1;
1684
1685 while (average > EHCI_PAGE_SIZE) {
1686 average -= EHCI_PAGE_SIZE;
1687 buf_offset += EHCI_PAGE_SIZE;
1688 usbd_get_page(temp->pc, buf_offset, &buf_res);
1689 td->qtd_buffer[x] =
1690 htohc32(temp->sc,
1691 buf_res.physaddr & (~0xFFF));
1692 td->qtd_buffer_hi[x] = 0;
1693 x++;
1694 }
1695
1696 /*
1697 * NOTE: The "average" variable is never zero after
1698 * exiting the loop above !
1699 *
1700 * NOTE: We have to subtract one from the offset to
1701 * ensure that we are computing the physical address
1702 * of a valid page !
1703 */
1704 buf_offset += average;
1705 usbd_get_page(temp->pc, buf_offset - 1, &buf_res);
1706 td->qtd_buffer[x] =
1707 htohc32(temp->sc,
1708 buf_res.physaddr & (~0xFFF));
1709 td->qtd_buffer_hi[x] = 0;
1710 }
1711
1712 if (td_next) {
1713 /* link the current TD with the next one */
1714 td->qtd_next = td_next->qtd_self;
1715 }
1716 td->qtd_altnext = qtd_altnext;
1717 td->alt_next = td_alt_next;
1718
1719 usb_pc_cpu_flush(td->page_cache);
1720 }
1721
1722 if (precompute) {
1723 precompute = 0;
1724
1725 /* setup alt next pointer, if any */
1726 if (temp->last_frame) {
1727 td_alt_next = NULL;
1728 qtd_altnext = terminate;
1729 } else {
1730 /* we use this field internally */
1731 td_alt_next = td_next;
1732 if (temp->setup_alt_next) {
1733 qtd_altnext = td_next->qtd_self;
1734 } else {
1735 qtd_altnext = terminate;
1736 }
1737 }
1738
1739 /* restore */
1740 temp->shortpkt = shortpkt_old;
1741 temp->len = len_old;
1742 goto restart;
1743 }
1744 temp->td = td;
1745 temp->td_next = td_next;
1746}
1747
1748static void
1749ehci_setup_standard_chain(struct usb_xfer *xfer, ehci_qh_t **qh_last)
1750{
1751 struct ehci_std_temp temp;
1752 struct usb_pipe_methods *methods;
1753 ehci_qh_t *qh;
1754 ehci_qtd_t *td;
1755 uint32_t qh_endp;
1756 uint32_t qh_endphub;
1757 uint32_t x;
1758
1759 DPRINTFN(9, "addr=%d endpt=%d sumlen=%d speed=%d\n",
1760 xfer->address, UE_GET_ADDR(xfer->endpointno),
1761 xfer->sumlen, usbd_get_speed(xfer->xroot->udev));
1762
1763 temp.average = xfer->max_hc_frame_size;
1764 temp.max_frame_size = xfer->max_frame_size;
1765 temp.sc = EHCI_BUS2SC(xfer->xroot->bus);
1766
1767 /* toggle the DMA set we are using */
1768 xfer->flags_int.curr_dma_set ^= 1;
1769
1770 /* get next DMA set */
1771 td = xfer->td_start[xfer->flags_int.curr_dma_set];
1772
1773 xfer->td_transfer_first = td;
1774 xfer->td_transfer_cache = td;
1775
1776 temp.td = NULL;
1777 temp.td_next = td;
1778 temp.qtd_status = 0;
1779 temp.last_frame = 0;
1780 temp.setup_alt_next = xfer->flags_int.short_frames_ok;
1781
1782 if (xfer->flags_int.control_xfr) {
1783 if (xfer->endpoint->toggle_next) {
1784 /* DATA1 is next */
1785 temp.qtd_status |=
1786 htohc32(temp.sc, EHCI_QTD_SET_TOGGLE(1));
1787 }
1788 temp.auto_data_toggle = 0;
1789 } else {
1790 temp.auto_data_toggle = 1;
1791 }
1792
1793 if ((xfer->xroot->udev->parent_hs_hub != NULL) ||
1794 (xfer->xroot->udev->address != 0)) {
1795 /* max 3 retries */
1796 temp.qtd_status |=
1797 htohc32(temp.sc, EHCI_QTD_SET_CERR(3));
1798 }
1799 /* check if we should prepend a setup message */
1800
1801 if (xfer->flags_int.control_xfr) {
1802 if (xfer->flags_int.control_hdr) {
1803
1804 xfer->endpoint->toggle_next = 0;
1805
1806 temp.qtd_status &=
1807 htohc32(temp.sc, EHCI_QTD_SET_CERR(3));
1808 temp.qtd_status |= htohc32(temp.sc,
1809 EHCI_QTD_ACTIVE |
1810 EHCI_QTD_SET_PID(EHCI_QTD_PID_SETUP) |
1811 EHCI_QTD_SET_TOGGLE(0));
1812
1813 temp.len = xfer->frlengths[0];
1814 temp.pc = xfer->frbuffers + 0;
1815 temp.shortpkt = temp.len ? 1 : 0;
1816 /* check for last frame */
1817 if (xfer->nframes == 1) {
1818 /* no STATUS stage yet, SETUP is last */
1819 if (xfer->flags_int.control_act) {
1820 temp.last_frame = 1;
1821 temp.setup_alt_next = 0;
1822 }
1823 }
1824 ehci_setup_standard_chain_sub(&temp);
1825 }
1826 x = 1;
1827 } else {
1828 x = 0;
1829 }
1830
1831 while (x != xfer->nframes) {
1832
1833 /* DATA0 / DATA1 message */
1834
1835 temp.len = xfer->frlengths[x];
1836 temp.pc = xfer->frbuffers + x;
1837
1838 x++;
1839
1840 if (x == xfer->nframes) {
1841 if (xfer->flags_int.control_xfr) {
1842 /* no STATUS stage yet, DATA is last */
1843 if (xfer->flags_int.control_act) {
1844 temp.last_frame = 1;
1845 temp.setup_alt_next = 0;
1846 }
1847 } else {
1848 temp.last_frame = 1;
1849 temp.setup_alt_next = 0;
1850 }
1851 }
1852 /* keep previous data toggle and error count */
1853
1854 temp.qtd_status &=
1855 htohc32(temp.sc, EHCI_QTD_SET_CERR(3) |
1856 EHCI_QTD_SET_TOGGLE(1));
1857
1858 if (temp.len == 0) {
1859
1860 /* make sure that we send an USB packet */
1861
1862 temp.shortpkt = 0;
1863
1864 } else {
1865
1866 /* regular data transfer */
1867
1868 temp.shortpkt = (xfer->flags.force_short_xfer) ? 0 : 1;
1869 }
1870
1871 /* set endpoint direction */
1872
1873 temp.qtd_status |=
1874 (UE_GET_DIR(xfer->endpointno) == UE_DIR_IN) ?
1875 htohc32(temp.sc, EHCI_QTD_ACTIVE |
1876 EHCI_QTD_SET_PID(EHCI_QTD_PID_IN)) :
1877 htohc32(temp.sc, EHCI_QTD_ACTIVE |
1878 EHCI_QTD_SET_PID(EHCI_QTD_PID_OUT));
1879
1880 ehci_setup_standard_chain_sub(&temp);
1881 }
1882
1883 /* check if we should append a status stage */
1884
1885 if (xfer->flags_int.control_xfr &&
1886 !xfer->flags_int.control_act) {
1887
1888 /*
1889 * Send a DATA1 message and invert the current endpoint
1890 * direction.
1891 */
1892
1893 temp.qtd_status &= htohc32(temp.sc, EHCI_QTD_SET_CERR(3) |
1894 EHCI_QTD_SET_TOGGLE(1));
1895 temp.qtd_status |=
1896 (UE_GET_DIR(xfer->endpointno) == UE_DIR_OUT) ?
1897 htohc32(temp.sc, EHCI_QTD_ACTIVE |
1898 EHCI_QTD_SET_PID(EHCI_QTD_PID_IN) |
1899 EHCI_QTD_SET_TOGGLE(1)) :
1900 htohc32(temp.sc, EHCI_QTD_ACTIVE |
1901 EHCI_QTD_SET_PID(EHCI_QTD_PID_OUT) |
1902 EHCI_QTD_SET_TOGGLE(1));
1903
1904 temp.len = 0;
1905 temp.pc = NULL;
1906 temp.shortpkt = 0;
1907 temp.last_frame = 1;
1908 temp.setup_alt_next = 0;
1909
1910 ehci_setup_standard_chain_sub(&temp);
1911 }
1912 td = temp.td;
1913
1914 /* the last TD terminates the transfer: */
1915 td->qtd_next = htohc32(temp.sc, EHCI_LINK_TERMINATE);
1916 td->qtd_altnext = htohc32(temp.sc, EHCI_LINK_TERMINATE);
1917
1918 usb_pc_cpu_flush(td->page_cache);
1919
1920 /* must have at least one frame! */
1921
1922 xfer->td_transfer_last = td;
1923
1924#ifdef USB_DEBUG
1925 if (ehcidebug > 8) {
1926 DPRINTF("nexttog=%d; data before transfer:\n",
1927 xfer->endpoint->toggle_next);
1928 ehci_dump_sqtds(temp.sc,
1929 xfer->td_transfer_first);
1930 }
1931#endif
1932
1933 methods = xfer->endpoint->methods;
1934
1935 qh = xfer->qh_start[xfer->flags_int.curr_dma_set];
1936
1937 /* the "qh_link" field is filled when the QH is added */
1938
1939 qh_endp =
1940 (EHCI_QH_SET_ADDR(xfer->address) |
1941 EHCI_QH_SET_ENDPT(UE_GET_ADDR(xfer->endpointno)) |
1942 EHCI_QH_SET_MPL(xfer->max_packet_size));
1943
1944 if (usbd_get_speed(xfer->xroot->udev) == USB_SPEED_HIGH) {
1945 qh_endp |= EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH);
1946 if (methods != &ehci_device_intr_methods)
1947 qh_endp |= EHCI_QH_SET_NRL(8);
1948 } else {
1949
1950 if (usbd_get_speed(xfer->xroot->udev) == USB_SPEED_FULL) {
1951 qh_endp |= EHCI_QH_SET_EPS(EHCI_QH_SPEED_FULL);
1952 } else {
1953 qh_endp |= EHCI_QH_SET_EPS(EHCI_QH_SPEED_LOW);
1954 }
1955
1956 if (methods == &ehci_device_ctrl_methods) {
1957 qh_endp |= EHCI_QH_CTL;
1958 }
1959 if (methods != &ehci_device_intr_methods) {
1960 /* Only try one time per microframe! */
1961 qh_endp |= EHCI_QH_SET_NRL(1);
1962 }
1963 }
1964
1965 if (temp.auto_data_toggle == 0) {
1966 /* software computes the data toggle */
1967 qh_endp |= EHCI_QH_DTC;
1968 }
1969
1970 qh->qh_endp = htohc32(temp.sc, qh_endp);
1971
1972 qh_endphub =
1973 (EHCI_QH_SET_MULT(xfer->max_packet_count & 3) |
1974 EHCI_QH_SET_CMASK(xfer->endpoint->usb_cmask) |
1975 EHCI_QH_SET_SMASK(xfer->endpoint->usb_smask) |
1976 EHCI_QH_SET_HUBA(xfer->xroot->udev->hs_hub_addr) |
1977 EHCI_QH_SET_PORT(xfer->xroot->udev->hs_port_no));
1978
1979 qh->qh_endphub = htohc32(temp.sc, qh_endphub);
1980 qh->qh_curqtd = 0;
1981
1982 /* fill the overlay qTD */
1983
1984 if (temp.auto_data_toggle && xfer->endpoint->toggle_next) {
1985 /* DATA1 is next */
1986 qh->qh_qtd.qtd_status = htohc32(temp.sc, EHCI_QTD_SET_TOGGLE(1));
1987 } else {
1988 qh->qh_qtd.qtd_status = 0;
1989 }
1990
1991 td = xfer->td_transfer_first;
1992
1993 qh->qh_qtd.qtd_next = td->qtd_self;
1994 qh->qh_qtd.qtd_altnext =
1995 htohc32(temp.sc, EHCI_LINK_TERMINATE);
1996
1997 usb_pc_cpu_flush(qh->page_cache);
1998
1999 if (xfer->xroot->udev->flags.self_suspended == 0) {
2000 EHCI_APPEND_QH(qh, *qh_last);
2001 }
2002}
2003
2004static void
2005ehci_root_intr(ehci_softc_t *sc)
2006{
2007 uint16_t i;
2008 uint16_t m;
2009
2010 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
2011
2012 /* clear any old interrupt data */
2013 memset(sc->sc_hub_idata, 0, sizeof(sc->sc_hub_idata));
2014
2015 /* set bits */
2016 m = (sc->sc_noport + 1);
2017 if (m > (8 * sizeof(sc->sc_hub_idata))) {
2018 m = (8 * sizeof(sc->sc_hub_idata));
2019 }
2020 for (i = 1; i < m; i++) {
2021 /* pick out CHANGE bits from the status register */
2022 if (EOREAD4(sc, EHCI_PORTSC(i)) & EHCI_PS_CLEAR) {
2023 sc->sc_hub_idata[i / 8] |= 1 << (i % 8);
2024 DPRINTF("port %d changed\n", i);
2025 }
2026 }
2027 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata,
2028 sizeof(sc->sc_hub_idata));
2029}
2030
2031static void
2032ehci_isoc_fs_done(ehci_softc_t *sc, struct usb_xfer *xfer)
2033{
2034 uint32_t nframes = xfer->nframes;
2035 uint32_t status;
2036 uint32_t *plen = xfer->frlengths;
2037 uint16_t len = 0;
2038 ehci_sitd_t *td = xfer->td_transfer_first;
2039 ehci_sitd_t **pp_last = &sc->sc_isoc_fs_p_last[xfer->qh_pos];
2040
2041 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n",
2042 xfer, xfer->endpoint);
2043
2044 while (nframes--) {
2045 if (td == NULL) {
2046 panic("%s:%d: out of TD's\n",
2047 __FUNCTION__, __LINE__);
2048 }
2049 if (pp_last >= &sc->sc_isoc_fs_p_last[EHCI_VIRTUAL_FRAMELIST_COUNT]) {
2050 pp_last = &sc->sc_isoc_fs_p_last[0];
2051 }
2052#ifdef USB_DEBUG
2053 if (ehcidebug > 15) {
2054 DPRINTF("isoc FS-TD\n");
2055 ehci_dump_sitd(sc, td);
2056 }
2057#endif
2058 usb_pc_cpu_invalidate(td->page_cache);
2059 status = hc32toh(sc, td->sitd_status);
2060
2061 len = EHCI_SITD_GET_LEN(status);
2062
2063 DPRINTFN(2, "status=0x%08x, rem=%u\n", status, len);
2064
2065 if (*plen >= len) {
2066 len = *plen - len;
2067 } else {
2068 len = 0;
2069 }
2070
2071 *plen = len;
2072
2073 /* remove FS-TD from schedule */
2074 EHCI_REMOVE_FS_TD(td, *pp_last);
2075
2076 pp_last++;
2077 plen++;
2078 td = td->obj_next;
2079 }
2080
2081 xfer->aframes = xfer->nframes;
2082}
2083
2084static void
2085ehci_isoc_hs_done(ehci_softc_t *sc, struct usb_xfer *xfer)
2086{
2087 uint32_t nframes = xfer->nframes;
2088 uint32_t status;
2089 uint32_t *plen = xfer->frlengths;
2090 uint16_t len = 0;
2091 uint8_t td_no = 0;
2092 ehci_itd_t *td = xfer->td_transfer_first;
2093 ehci_itd_t **pp_last = &sc->sc_isoc_hs_p_last[xfer->qh_pos];
2094
2095 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n",
2096 xfer, xfer->endpoint);
2097
2098 while (nframes) {
2099 if (td == NULL) {
2100 panic("%s:%d: out of TD's\n",
2101 __FUNCTION__, __LINE__);
2102 }
2103 if (pp_last >= &sc->sc_isoc_hs_p_last[EHCI_VIRTUAL_FRAMELIST_COUNT]) {
2104 pp_last = &sc->sc_isoc_hs_p_last[0];
2105 }
2106#ifdef USB_DEBUG
2107 if (ehcidebug > 15) {
2108 DPRINTF("isoc HS-TD\n");
2109 ehci_dump_itd(sc, td);
2110 }
2111#endif
2112
2113 usb_pc_cpu_invalidate(td->page_cache);
2114 status = hc32toh(sc, td->itd_status[td_no]);
2115
2116 len = EHCI_ITD_GET_LEN(status);
2117
2118 DPRINTFN(2, "status=0x%08x, len=%u\n", status, len);
2119
2120 if (xfer->endpoint->usb_smask & (1 << td_no)) {
2121
2122 if (*plen >= len) {
2123 /*
2124 * The length is valid. NOTE: The
2125 * complete length is written back
2126 * into the status field, and not the
2127 * remainder like with other transfer
2128 * descriptor types.
2129 */
2130 } else {
2131 /* Invalid length - truncate */
2132 len = 0;
2133 }
2134
2135 *plen = len;
2136 plen++;
2137 nframes--;
2138 }
2139
2140 td_no++;
2141
2142 if ((td_no == 8) || (nframes == 0)) {
2143 /* remove HS-TD from schedule */
2144 EHCI_REMOVE_HS_TD(td, *pp_last);
2145 pp_last++;
2146
2147 td_no = 0;
2148 td = td->obj_next;
2149 }
2150 }
2151 xfer->aframes = xfer->nframes;
2152}
2153
2154/* NOTE: "done" can be run two times in a row,
2155 * from close and from interrupt
2156 */
2157static void
2158ehci_device_done(struct usb_xfer *xfer, usb_error_t error)
2159{
2160 struct usb_pipe_methods *methods = xfer->endpoint->methods;
2161 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
2162
2163 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
2164
2165 DPRINTFN(2, "xfer=%p, endpoint=%p, error=%d\n",
2166 xfer, xfer->endpoint, error);
2167
2168 if ((methods == &ehci_device_bulk_methods) ||
2169 (methods == &ehci_device_ctrl_methods)) {
2170#ifdef USB_DEBUG
2171 if (ehcidebug > 8) {
2172 DPRINTF("nexttog=%d; data after transfer:\n",
2173 xfer->endpoint->toggle_next);
2174 ehci_dump_sqtds(sc,
2175 xfer->td_transfer_first);
2176 }
2177#endif
2178
2179 EHCI_REMOVE_QH(xfer->qh_start[xfer->flags_int.curr_dma_set],
2180 sc->sc_async_p_last);
2181 }
2182 if (methods == &ehci_device_intr_methods) {
2183 EHCI_REMOVE_QH(xfer->qh_start[xfer->flags_int.curr_dma_set],
2184 sc->sc_intr_p_last[xfer->qh_pos]);
2185 }
2186 /*
2187 * Only finish isochronous transfers once which will update
2188 * "xfer->frlengths".
2189 */
2190 if (xfer->td_transfer_first &&
2191 xfer->td_transfer_last) {
2192 if (methods == &ehci_device_isoc_fs_methods) {
2193 ehci_isoc_fs_done(sc, xfer);
2194 }
2195 if (methods == &ehci_device_isoc_hs_methods) {
2196 ehci_isoc_hs_done(sc, xfer);
2197 }
2198 xfer->td_transfer_first = NULL;
2199 xfer->td_transfer_last = NULL;
2200 }
2201 /* dequeue transfer and start next transfer */
2202 usbd_transfer_done(xfer, error);
2203}
2204
2205/*------------------------------------------------------------------------*
2206 * ehci bulk support
2207 *------------------------------------------------------------------------*/
2208static void
2209ehci_device_bulk_open(struct usb_xfer *xfer)
2210{
2211 return;
2212}
2213
2214static void
2215ehci_device_bulk_close(struct usb_xfer *xfer)
2216{
2217 ehci_device_done(xfer, USB_ERR_CANCELLED);
2218}
2219
2220static void
2221ehci_device_bulk_enter(struct usb_xfer *xfer)
2222{
2223 return;
2224}
2225
2226static void
2227ehci_device_bulk_start(struct usb_xfer *xfer)
2228{
2229 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
2230 uint32_t temp;
2231
2232 /* setup TD's and QH */
2233 ehci_setup_standard_chain(xfer, &sc->sc_async_p_last);
2234
2235 /* put transfer on interrupt queue */
2236 ehci_transfer_intr_enqueue(xfer);
2237
2238 /*
2239 * XXX Certain nVidia chipsets choke when using the IAAD
2240 * feature too frequently.
2241 */
2242 if (sc->sc_flags & EHCI_SCFLG_IAADBUG)
2243 return;
2244
2245 /* XXX Performance quirk: Some Host Controllers have a too low
2246 * interrupt rate. Issue an IAAD to stimulate the Host
2247 * Controller after queueing the BULK transfer.
2248 */
2249 temp = EOREAD4(sc, EHCI_USBCMD);
2250 if (!(temp & EHCI_CMD_IAAD))
2251 EOWRITE4(sc, EHCI_USBCMD, temp | EHCI_CMD_IAAD);
2252}
2253
2254struct usb_pipe_methods ehci_device_bulk_methods =
2255{
2256 .open = ehci_device_bulk_open,
2257 .close = ehci_device_bulk_close,
2258 .enter = ehci_device_bulk_enter,
2259 .start = ehci_device_bulk_start,
2260};
2261
2262/*------------------------------------------------------------------------*
2263 * ehci control support
2264 *------------------------------------------------------------------------*/
2265static void
2266ehci_device_ctrl_open(struct usb_xfer *xfer)
2267{
2268 return;
2269}
2270
2271static void
2272ehci_device_ctrl_close(struct usb_xfer *xfer)
2273{
2274 ehci_device_done(xfer, USB_ERR_CANCELLED);
2275}
2276
2277static void
2278ehci_device_ctrl_enter(struct usb_xfer *xfer)
2279{
2280 return;
2281}
2282
2283static void
2284ehci_device_ctrl_start(struct usb_xfer *xfer)
2285{
2286 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
2287
2288 /* setup TD's and QH */
2289 ehci_setup_standard_chain(xfer, &sc->sc_async_p_last);
2290
2291 /* put transfer on interrupt queue */
2292 ehci_transfer_intr_enqueue(xfer);
2293}
2294
2295struct usb_pipe_methods ehci_device_ctrl_methods =
2296{
2297 .open = ehci_device_ctrl_open,
2298 .close = ehci_device_ctrl_close,
2299 .enter = ehci_device_ctrl_enter,
2300 .start = ehci_device_ctrl_start,
2301};
2302
2303/*------------------------------------------------------------------------*
2304 * ehci interrupt support
2305 *------------------------------------------------------------------------*/
2306static void
2307ehci_device_intr_open(struct usb_xfer *xfer)
2308{
2309 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
2310 uint16_t best;
2311 uint16_t bit;
2312 uint16_t x;
2313
2314 usb_hs_bandwidth_alloc(xfer);
2315
2316 /*
2317 * Find the best QH position corresponding to the given interval:
2318 */
2319
2320 best = 0;
2321 bit = EHCI_VIRTUAL_FRAMELIST_COUNT / 2;
2322 while (bit) {
2323 if (xfer->interval >= bit) {
2324 x = bit;
2325 best = bit;
2326 while (x & bit) {
2327 if (sc->sc_intr_stat[x] <
2328 sc->sc_intr_stat[best]) {
2329 best = x;
2330 }
2331 x++;
2332 }
2333 break;
2334 }
2335 bit >>= 1;
2336 }
2337
2338 sc->sc_intr_stat[best]++;
2339 xfer->qh_pos = best;
2340
2341 DPRINTFN(3, "best=%d interval=%d\n",
2342 best, xfer->interval);
2343}
2344
2345static void
2346ehci_device_intr_close(struct usb_xfer *xfer)
2347{
2348 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
2349
2350 sc->sc_intr_stat[xfer->qh_pos]--;
2351
2352 ehci_device_done(xfer, USB_ERR_CANCELLED);
2353
2354 /* bandwidth must be freed after device done */
2355 usb_hs_bandwidth_free(xfer);
2356}
2357
2358static void
2359ehci_device_intr_enter(struct usb_xfer *xfer)
2360{
2361 return;
2362}
2363
2364static void
2365ehci_device_intr_start(struct usb_xfer *xfer)
2366{
2367 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
2368
2369 /* setup TD's and QH */
2370 ehci_setup_standard_chain(xfer, &sc->sc_intr_p_last[xfer->qh_pos]);
2371
2372 /* put transfer on interrupt queue */
2373 ehci_transfer_intr_enqueue(xfer);
2374}
2375
2376struct usb_pipe_methods ehci_device_intr_methods =
2377{
2378 .open = ehci_device_intr_open,
2379 .close = ehci_device_intr_close,
2380 .enter = ehci_device_intr_enter,
2381 .start = ehci_device_intr_start,
2382};
2383
2384/*------------------------------------------------------------------------*
2385 * ehci full speed isochronous support
2386 *------------------------------------------------------------------------*/
2387static void
2388ehci_device_isoc_fs_open(struct usb_xfer *xfer)
2389{
2390 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
2391 ehci_sitd_t *td;
2392 uint32_t sitd_portaddr;
2393 uint8_t ds;
2394
2395 sitd_portaddr =
2396 EHCI_SITD_SET_ADDR(xfer->address) |
2397 EHCI_SITD_SET_ENDPT(UE_GET_ADDR(xfer->endpointno)) |
2398 EHCI_SITD_SET_HUBA(xfer->xroot->udev->hs_hub_addr) |
2399 EHCI_SITD_SET_PORT(xfer->xroot->udev->hs_port_no);
2400
2401 if (UE_GET_DIR(xfer->endpointno) == UE_DIR_IN)
2402 sitd_portaddr |= EHCI_SITD_SET_DIR_IN;
2403
2404 sitd_portaddr = htohc32(sc, sitd_portaddr);
2405
2406 /* initialize all TD's */
2407
2408 for (ds = 0; ds != 2; ds++) {
2409
2410 for (td = xfer->td_start[ds]; td; td = td->obj_next) {
2411
2412 td->sitd_portaddr = sitd_portaddr;
2413
2414 /*
2415 * TODO: make some kind of automatic
2416 * SMASK/CMASK selection based on micro-frame
2417 * usage
2418 *
2419 * micro-frame usage (8 microframes per 1ms)
2420 */
2421 td->sitd_back = htohc32(sc, EHCI_LINK_TERMINATE);
2422
2423 usb_pc_cpu_flush(td->page_cache);
2424 }
2425 }
2426}
2427
2428static void
2429ehci_device_isoc_fs_close(struct usb_xfer *xfer)
2430{
2431 ehci_device_done(xfer, USB_ERR_CANCELLED);
2432}
2433
2434static void
2435ehci_device_isoc_fs_enter(struct usb_xfer *xfer)
2436{
2437 struct usb_page_search buf_res;
2438 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
2439 ehci_sitd_t *td;
2440 ehci_sitd_t *td_last = NULL;
2441 ehci_sitd_t **pp_last;
2442 uint32_t *plen;
2443 uint32_t buf_offset;
2444 uint32_t nframes;
2445 uint32_t temp;
2446 uint32_t sitd_mask;
2447 uint16_t tlen;
2448 uint8_t sa;
2449 uint8_t sb;
2450
2451#ifdef USB_DEBUG
2452 uint8_t once = 1;
2453
2454#endif
2455
2456 DPRINTFN(6, "xfer=%p next=%d nframes=%d\n",
2457 xfer, xfer->endpoint->isoc_next, xfer->nframes);
2458
2459 /* get the current frame index */
2460
2461 nframes = EOREAD4(sc, EHCI_FRINDEX) / 8;
2462
2463 /*
2464 * check if the frame index is within the window where the frames
2465 * will be inserted
2466 */
2467 buf_offset = (nframes - xfer->endpoint->isoc_next) &
2468 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1);
2469
2470 if ((xfer->endpoint->is_synced == 0) ||
2471 (buf_offset < xfer->nframes)) {
2472 /*
2473 * If there is data underflow or the pipe queue is empty we
2474 * schedule the transfer a few frames ahead of the current
2475 * frame position. Else two isochronous transfers might
2476 * overlap.
2477 */
2478 xfer->endpoint->isoc_next = (nframes + 3) &
2479 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1);
2480 xfer->endpoint->is_synced = 1;
2481 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next);
2482 }
2483 /*
2484 * compute how many milliseconds the insertion is ahead of the
2485 * current frame position:
2486 */
2487 buf_offset = (xfer->endpoint->isoc_next - nframes) &
2488 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1);
2489
2490 /*
2491 * pre-compute when the isochronous transfer will be finished:
2492 */
2493 xfer->isoc_time_complete =
2494 usb_isoc_time_expand(&sc->sc_bus, nframes) +
2495 buf_offset + xfer->nframes;
2496
2497 /* get the real number of frames */
2498
2499 nframes = xfer->nframes;
2500
2501 buf_offset = 0;
2502
2503 plen = xfer->frlengths;
2504
2505 /* toggle the DMA set we are using */
2506 xfer->flags_int.curr_dma_set ^= 1;
2507
2508 /* get next DMA set */
2509 td = xfer->td_start[xfer->flags_int.curr_dma_set];
2510 xfer->td_transfer_first = td;
2511
2512 pp_last = &sc->sc_isoc_fs_p_last[xfer->endpoint->isoc_next];
2513
2514 /* store starting position */
2515
2516 xfer->qh_pos = xfer->endpoint->isoc_next;
2517
2518 while (nframes--) {
2519 if (td == NULL) {
2520 panic("%s:%d: out of TD's\n",
2521 __FUNCTION__, __LINE__);
2522 }
2523 if (pp_last >= &sc->sc_isoc_fs_p_last[EHCI_VIRTUAL_FRAMELIST_COUNT])
2524 pp_last = &sc->sc_isoc_fs_p_last[0];
2525
2526 /* reuse sitd_portaddr and sitd_back from last transfer */
2527
2528 if (*plen > xfer->max_frame_size) {
2529#ifdef USB_DEBUG
2530 if (once) {
2531 once = 0;
2532 printf("%s: frame length(%d) exceeds %d "
2533 "bytes (frame truncated)\n",
2534 __FUNCTION__, *plen,
2535 xfer->max_frame_size);
2536 }
2537#endif
2538 *plen = xfer->max_frame_size;
2539 }
2540
2541 /* allocate a slot */
2542
2543 sa = usbd_fs_isoc_schedule_alloc_slot(xfer,
2544 xfer->isoc_time_complete - nframes - 1);
2545
2546 if (sa == 255) {
2547 /*
2548 * Schedule is FULL, set length to zero:
2549 */
2550
2551 *plen = 0;
2552 sa = USB_FS_ISOC_UFRAME_MAX - 1;
2553 }
2554 if (*plen) {
2555 /*
2556 * only call "usbd_get_page()" when we have a
2557 * non-zero length
2558 */
2559 usbd_get_page(xfer->frbuffers, buf_offset, &buf_res);
2560 td->sitd_bp[0] = htohc32(sc, buf_res.physaddr);
2561 buf_offset += *plen;
2562 /*
2563 * NOTE: We need to subtract one from the offset so
2564 * that we are on a valid page!
2565 */
2566 usbd_get_page(xfer->frbuffers, buf_offset - 1,
2567 &buf_res);
2568 temp = buf_res.physaddr & ~0xFFF;
2569 } else {
2570 td->sitd_bp[0] = 0;
2571 temp = 0;
2572 }
2573
2574 if (UE_GET_DIR(xfer->endpointno) == UE_DIR_OUT) {
2575 tlen = *plen;
2576 if (tlen <= 188) {
2577 temp |= 1; /* T-count = 1, TP = ALL */
2578 tlen = 1;
2579 } else {
2580 tlen += 187;
2581 tlen /= 188;
2582 temp |= tlen; /* T-count = [1..6] */
2583 temp |= 8; /* TP = Begin */
2584 }
2585
2586 tlen += sa;
2587
2588 if (tlen >= 8) {
2589 sb = 0;
2590 } else {
2591 sb = (1 << tlen);
2592 }
2593
2594 sa = (1 << sa);
2595 sa = (sb - sa) & 0x3F;
2596 sb = 0;
2597 } else {
2598 sb = (-(4 << sa)) & 0xFE;
2599 sa = (1 << sa) & 0x3F;
2600 }
2601
2602 sitd_mask = (EHCI_SITD_SET_SMASK(sa) |
2603 EHCI_SITD_SET_CMASK(sb));
2604
2605 td->sitd_bp[1] = htohc32(sc, temp);
2606
2607 td->sitd_mask = htohc32(sc, sitd_mask);
2608
2609 if (nframes == 0) {
2610 td->sitd_status = htohc32(sc,
2611 EHCI_SITD_IOC |
2612 EHCI_SITD_ACTIVE |
2613 EHCI_SITD_SET_LEN(*plen));
2614 } else {
2615 td->sitd_status = htohc32(sc,
2616 EHCI_SITD_ACTIVE |
2617 EHCI_SITD_SET_LEN(*plen));
2618 }
2619 usb_pc_cpu_flush(td->page_cache);
2620
2621#ifdef USB_DEBUG
2622 if (ehcidebug > 15) {
2623 DPRINTF("FS-TD %d\n", nframes);
2624 ehci_dump_sitd(sc, td);
2625 }
2626#endif
2627 /* insert TD into schedule */
2628 EHCI_APPEND_FS_TD(td, *pp_last);
2629 pp_last++;
2630
2631 plen++;
2632 td_last = td;
2633 td = td->obj_next;
2634 }
2635
2636 xfer->td_transfer_last = td_last;
2637
2638 /* update isoc_next */
2639 xfer->endpoint->isoc_next = (pp_last - &sc->sc_isoc_fs_p_last[0]) &
2640 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1);
2641
2642 /*
2643 * We don't allow cancelling of the SPLIT transaction USB FULL
2644 * speed transfer, because it disturbs the bandwidth
2645 * computation algorithm.
2646 */
2647 xfer->flags_int.can_cancel_immed = 0;
2648}
2649
2650static void
2651ehci_device_isoc_fs_start(struct usb_xfer *xfer)
2652{
2653 /*
2654 * We don't allow cancelling of the SPLIT transaction USB FULL
2655 * speed transfer, because it disturbs the bandwidth
2656 * computation algorithm.
2657 */
2658 xfer->flags_int.can_cancel_immed = 0;
2659
2660 /* set a default timeout */
2661 if (xfer->timeout == 0)
2662 xfer->timeout = 500; /* ms */
2663
2664 /* put transfer on interrupt queue */
2665 ehci_transfer_intr_enqueue(xfer);
2666}
2667
2668struct usb_pipe_methods ehci_device_isoc_fs_methods =
2669{
2670 .open = ehci_device_isoc_fs_open,
2671 .close = ehci_device_isoc_fs_close,
2672 .enter = ehci_device_isoc_fs_enter,
2673 .start = ehci_device_isoc_fs_start,
2674};
2675
2676/*------------------------------------------------------------------------*
2677 * ehci high speed isochronous support
2678 *------------------------------------------------------------------------*/
2679static void
2680ehci_device_isoc_hs_open(struct usb_xfer *xfer)
2681{
2682 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
2683 ehci_itd_t *td;
2684 uint32_t temp;
2685 uint8_t ds;
2686
2687 usb_hs_bandwidth_alloc(xfer);
2688
2689 /* initialize all TD's */
2690
2691 for (ds = 0; ds != 2; ds++) {
2692
2693 for (td = xfer->td_start[ds]; td; td = td->obj_next) {
2694
2695 /* set TD inactive */
2696 td->itd_status[0] = 0;
2697 td->itd_status[1] = 0;
2698 td->itd_status[2] = 0;
2699 td->itd_status[3] = 0;
2700 td->itd_status[4] = 0;
2701 td->itd_status[5] = 0;
2702 td->itd_status[6] = 0;
2703 td->itd_status[7] = 0;
2704
2705 /* set endpoint and address */
2706 td->itd_bp[0] = htohc32(sc,
2707 EHCI_ITD_SET_ADDR(xfer->address) |
2708 EHCI_ITD_SET_ENDPT(UE_GET_ADDR(xfer->endpointno)));
2709
2710 temp =
2711 EHCI_ITD_SET_MPL(xfer->max_packet_size & 0x7FF);
2712
2713 /* set direction */
2714 if (UE_GET_DIR(xfer->endpointno) == UE_DIR_IN) {
2715 temp |= EHCI_ITD_SET_DIR_IN;
2716 }
2717 /* set maximum packet size */
2718 td->itd_bp[1] = htohc32(sc, temp);
2719
2720 /* set transfer multiplier */
2721 td->itd_bp[2] = htohc32(sc, xfer->max_packet_count & 3);
2722
2723 usb_pc_cpu_flush(td->page_cache);
2724 }
2725 }
2726}
2727
2728static void
2729ehci_device_isoc_hs_close(struct usb_xfer *xfer)
2730{
2731 ehci_device_done(xfer, USB_ERR_CANCELLED);
2732
2733 /* bandwidth must be freed after device done */
2734 usb_hs_bandwidth_free(xfer);
2735}
2736
2737static void
2738ehci_device_isoc_hs_enter(struct usb_xfer *xfer)
2739{
2740 struct usb_page_search buf_res;
2741 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
2742 ehci_itd_t *td;
2743 ehci_itd_t *td_last = NULL;
2744 ehci_itd_t **pp_last;
2745 bus_size_t page_addr;
2746 uint32_t *plen;
2747 uint32_t status;
2748 uint32_t buf_offset;
2749 uint32_t nframes;
2750 uint32_t itd_offset[8 + 1];
2751 uint8_t x;
2752 uint8_t td_no;
2753 uint8_t page_no;
2754 uint8_t shift = usbd_xfer_get_fps_shift(xfer);
2755
2756#ifdef USB_DEBUG
2757 uint8_t once = 1;
2758
2759#endif
2760
2761 DPRINTFN(6, "xfer=%p next=%d nframes=%d shift=%d\n",
2762 xfer, xfer->endpoint->isoc_next, xfer->nframes, (int)shift);
2763
2764 /* get the current frame index */
2765
2766 nframes = EOREAD4(sc, EHCI_FRINDEX) / 8;
2767
2768 /*
2769 * check if the frame index is within the window where the frames
2770 * will be inserted
2771 */
2772 buf_offset = (nframes - xfer->endpoint->isoc_next) &
2773 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1);
2774
2775 if ((xfer->endpoint->is_synced == 0) ||
2776 (buf_offset < (((xfer->nframes << shift) + 7) / 8))) {
2777 /*
2778 * If there is data underflow or the pipe queue is empty we
2779 * schedule the transfer a few frames ahead of the current
2780 * frame position. Else two isochronous transfers might
2781 * overlap.
2782 */
2783 xfer->endpoint->isoc_next = (nframes + 3) &
2784 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1);
2785 xfer->endpoint->is_synced = 1;
2786 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next);
2787 }
2788 /*
2789 * compute how many milliseconds the insertion is ahead of the
2790 * current frame position:
2791 */
2792 buf_offset = (xfer->endpoint->isoc_next - nframes) &
2793 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1);
2794
2795 /*
2796 * pre-compute when the isochronous transfer will be finished:
2797 */
2798 xfer->isoc_time_complete =
2799 usb_isoc_time_expand(&sc->sc_bus, nframes) + buf_offset +
2800 (((xfer->nframes << shift) + 7) / 8);
2801
2802 /* get the real number of frames */
2803
2804 nframes = xfer->nframes;
2805
2806 buf_offset = 0;
2807 td_no = 0;
2808
2809 plen = xfer->frlengths;
2810
2811 /* toggle the DMA set we are using */
2812 xfer->flags_int.curr_dma_set ^= 1;
2813
2814 /* get next DMA set */
2815 td = xfer->td_start[xfer->flags_int.curr_dma_set];
2816 xfer->td_transfer_first = td;
2817
2818 pp_last = &sc->sc_isoc_hs_p_last[xfer->endpoint->isoc_next];
2819
2820 /* store starting position */
2821
2822 xfer->qh_pos = xfer->endpoint->isoc_next;
2823
2824 while (nframes) {
2825 if (td == NULL) {
2826 panic("%s:%d: out of TD's\n",
2827 __FUNCTION__, __LINE__);
2828 }
2829 if (pp_last >= &sc->sc_isoc_hs_p_last[EHCI_VIRTUAL_FRAMELIST_COUNT]) {
2830 pp_last = &sc->sc_isoc_hs_p_last[0];
2831 }
2832 /* range check */
2833 if (*plen > xfer->max_frame_size) {
2834#ifdef USB_DEBUG
2835 if (once) {
2836 once = 0;
2837 printf("%s: frame length(%d) exceeds %d bytes "
2838 "(frame truncated)\n",
2839 __FUNCTION__, *plen, xfer->max_frame_size);
2840 }
2841#endif
2842 *plen = xfer->max_frame_size;
2843 }
2844
2845 if (xfer->endpoint->usb_smask & (1 << td_no)) {
2846 status = (EHCI_ITD_SET_LEN(*plen) |
2847 EHCI_ITD_ACTIVE |
2848 EHCI_ITD_SET_PG(0));
2849 td->itd_status[td_no] = htohc32(sc, status);
2850 itd_offset[td_no] = buf_offset;
2851 buf_offset += *plen;
2852 plen++;
2853 nframes --;
2854 } else {
2855 td->itd_status[td_no] = 0; /* not active */
2856 itd_offset[td_no] = buf_offset;
2857 }
2858
2859 td_no++;
2860
2861 if ((td_no == 8) || (nframes == 0)) {
2862
2863 /* the rest of the transfers are not active, if any */
2864 for (x = td_no; x != 8; x++) {
2865 td->itd_status[x] = 0; /* not active */
2866 }
2867
2868 /* check if there is any data to be transferred */
2869 if (itd_offset[0] != buf_offset) {
2870 page_no = 0;
2871 itd_offset[td_no] = buf_offset;
2872
2873 /* get first page offset */
2874 usbd_get_page(xfer->frbuffers, itd_offset[0], &buf_res);
2875 /* get page address */
2876 page_addr = buf_res.physaddr & ~0xFFF;
2877 /* update page address */
2878 td->itd_bp[0] &= htohc32(sc, 0xFFF);
2879 td->itd_bp[0] |= htohc32(sc, page_addr);
2880
2881 for (x = 0; x != td_no; x++) {
2882 /* set page number and page offset */
2883 status = (EHCI_ITD_SET_PG(page_no) |
2884 (buf_res.physaddr & 0xFFF));
2885 td->itd_status[x] |= htohc32(sc, status);
2886
2887 /* get next page offset */
2888 if (itd_offset[x + 1] == buf_offset) {
2889 /*
2890 * We subtract one so that
2891 * we don't go off the last
2892 * page!
2893 */
2894 usbd_get_page(xfer->frbuffers, buf_offset - 1, &buf_res);
2895 } else {
2896 usbd_get_page(xfer->frbuffers, itd_offset[x + 1], &buf_res);
2897 }
2898
2899 /* check if we need a new page */
2900 if ((buf_res.physaddr ^ page_addr) & ~0xFFF) {
2901 /* new page needed */
2902 page_addr = buf_res.physaddr & ~0xFFF;
2903 if (page_no == 6) {
2904 panic("%s: too many pages\n", __FUNCTION__);
2905 }
2906 page_no++;
2907 /* update page address */
2908 td->itd_bp[page_no] &= htohc32(sc, 0xFFF);
2909 td->itd_bp[page_no] |= htohc32(sc, page_addr);
2910 }
2911 }
2912 }
2913 /* set IOC bit if we are complete */
2914 if (nframes == 0) {
2915 td->itd_status[td_no - 1] |= htohc32(sc, EHCI_ITD_IOC);
2916 }
2917 usb_pc_cpu_flush(td->page_cache);
2918#ifdef USB_DEBUG
2919 if (ehcidebug > 15) {
2920 DPRINTF("HS-TD %d\n", nframes);
2921 ehci_dump_itd(sc, td);
2922 }
2923#endif
2924 /* insert TD into schedule */
2925 EHCI_APPEND_HS_TD(td, *pp_last);
2926 pp_last++;
2927
2928 td_no = 0;
2929 td_last = td;
2930 td = td->obj_next;
2931 }
2932 }
2933
2934 xfer->td_transfer_last = td_last;
2935
2936 /* update isoc_next */
2937 xfer->endpoint->isoc_next = (pp_last - &sc->sc_isoc_hs_p_last[0]) &
2938 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1);
2939}
2940
2941static void
2942ehci_device_isoc_hs_start(struct usb_xfer *xfer)
2943{
2944 /* put transfer on interrupt queue */
2945 ehci_transfer_intr_enqueue(xfer);
2946}
2947
2948struct usb_pipe_methods ehci_device_isoc_hs_methods =
2949{
2950 .open = ehci_device_isoc_hs_open,
2951 .close = ehci_device_isoc_hs_close,
2952 .enter = ehci_device_isoc_hs_enter,
2953 .start = ehci_device_isoc_hs_start,
2954};
2955
2956/*------------------------------------------------------------------------*
2957 * ehci root control support
2958 *------------------------------------------------------------------------*
2959 * Simulate a hardware hub by handling all the necessary requests.
2960 *------------------------------------------------------------------------*/
2961
2962static const
2963struct usb_device_descriptor ehci_devd =
2964{
2965 sizeof(struct usb_device_descriptor),
2966 UDESC_DEVICE, /* type */
2967 {0x00, 0x02}, /* USB version */
2968 UDCLASS_HUB, /* class */
2969 UDSUBCLASS_HUB, /* subclass */
2970 UDPROTO_HSHUBSTT, /* protocol */
2971 64, /* max packet */
2972 {0}, {0}, {0x00, 0x01}, /* device id */
2973 1, 2, 0, /* string indicies */
2974 1 /* # of configurations */
2975};
2976
2977static const
2978struct usb_device_qualifier ehci_odevd =
2979{
2980 sizeof(struct usb_device_qualifier),
2981 UDESC_DEVICE_QUALIFIER, /* type */
2982 {0x00, 0x02}, /* USB version */
2983 UDCLASS_HUB, /* class */
2984 UDSUBCLASS_HUB, /* subclass */
2985 UDPROTO_FSHUB, /* protocol */
2986 0, /* max packet */
2987 0, /* # of configurations */
2988 0
2989};
2990
2991static const struct ehci_config_desc ehci_confd = {
2992 .confd = {
2993 .bLength = sizeof(struct usb_config_descriptor),
2994 .bDescriptorType = UDESC_CONFIG,
2995 .wTotalLength[0] = sizeof(ehci_confd),
2996 .bNumInterface = 1,
2997 .bConfigurationValue = 1,
2998 .iConfiguration = 0,
2999 .bmAttributes = UC_SELF_POWERED,
3000 .bMaxPower = 0 /* max power */
3001 },
3002 .ifcd = {
3003 .bLength = sizeof(struct usb_interface_descriptor),
3004 .bDescriptorType = UDESC_INTERFACE,
3005 .bNumEndpoints = 1,
3006 .bInterfaceClass = UICLASS_HUB,
3007 .bInterfaceSubClass = UISUBCLASS_HUB,
3008 .bInterfaceProtocol = 0,
3009 },
3010 .endpd = {
3011 .bLength = sizeof(struct usb_endpoint_descriptor),
3012 .bDescriptorType = UDESC_ENDPOINT,
3013 .bEndpointAddress = UE_DIR_IN | EHCI_INTR_ENDPT,
3014 .bmAttributes = UE_INTERRUPT,
3015 .wMaxPacketSize[0] = 8, /* max packet (63 ports) */
3016 .bInterval = 255,
3017 },
3018};
3019
3020static const
3021struct usb_hub_descriptor ehci_hubd =
3022{
3023 .bDescLength = 0, /* dynamic length */
3024 .bDescriptorType = UDESC_HUB,
3025};
3026
3027static void
3028ehci_disown(ehci_softc_t *sc, uint16_t index, uint8_t lowspeed)
3029{
3030 uint32_t port;
3031 uint32_t v;
3032
3033 DPRINTF("index=%d lowspeed=%d\n", index, lowspeed);
3034
3035 port = EHCI_PORTSC(index);
3036 v = EOREAD4(sc, port) & ~EHCI_PS_CLEAR;
3037 EOWRITE4(sc, port, v | EHCI_PS_PO);
3038}
3039
3040static usb_error_t
3041ehci_roothub_exec(struct usb_device *udev,
3042 struct usb_device_request *req, const void **pptr, uint16_t *plength)
3043{
3044 ehci_softc_t *sc = EHCI_BUS2SC(udev->bus);
3045 const char *str_ptr;
3046 const void *ptr;
3047 uint32_t port;
3048 uint32_t v;
3049 uint16_t len;
3050 uint16_t i;
3051 uint16_t value;
3052 uint16_t index;
3053 usb_error_t err;
3054
3055 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
3056
3057 /* buffer reset */
3058 ptr = (const void *)&sc->sc_hub_desc;
3059 len = 0;
3060 err = 0;
3061
3062 value = UGETW(req->wValue);
3063 index = UGETW(req->wIndex);
3064
3065 DPRINTFN(3, "type=0x%02x request=0x%02x wLen=0x%04x "
3066 "wValue=0x%04x wIndex=0x%04x\n",
3067 req->bmRequestType, req->bRequest,
3068 UGETW(req->wLength), value, index);
3069
3070#define C(x,y) ((x) | ((y) << 8))
3071 switch (C(req->bRequest, req->bmRequestType)) {
3072 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE):
3073 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE):
3074 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT):
3075 /*
3076 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops
3077 * for the integrated root hub.
3078 */
3079 break;
3080 case C(UR_GET_CONFIG, UT_READ_DEVICE):
3081 len = 1;
3082 sc->sc_hub_desc.temp[0] = sc->sc_conf;
3083 break;
3084 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE):
3085 switch (value >> 8) {
3086 case UDESC_DEVICE:
3087 if ((value & 0xff) != 0) {
3088 err = USB_ERR_IOERROR;
3089 goto done;
3090 }
3091 len = sizeof(ehci_devd);
3092 ptr = (const void *)&ehci_devd;
3093 break;
3094 /*
3095 * We can't really operate at another speed,
3096 * but the specification says we need this
3097 * descriptor:
3098 */
3099 case UDESC_DEVICE_QUALIFIER:
3100 if ((value & 0xff) != 0) {
3101 err = USB_ERR_IOERROR;
3102 goto done;
3103 }
3104 len = sizeof(ehci_odevd);
3105 ptr = (const void *)&ehci_odevd;
3106 break;
3107
3108 case UDESC_CONFIG:
3109 if ((value & 0xff) != 0) {
3110 err = USB_ERR_IOERROR;
3111 goto done;
3112 }
3113 len = sizeof(ehci_confd);
3114 ptr = (const void *)&ehci_confd;
3115 break;
3116
3117 case UDESC_STRING:
3118 switch (value & 0xff) {
3119 case 0: /* Language table */
3120 str_ptr = "\001";
3121 break;
3122
3123 case 1: /* Vendor */
3124 str_ptr = sc->sc_vendor;
3125 break;
3126
3127 case 2: /* Product */
3128 str_ptr = "EHCI root HUB";
3129 break;
3130
3131 default:
3132 str_ptr = "";
3133 break;
3134 }
3135
3136 len = usb_make_str_desc(
3137 sc->sc_hub_desc.temp,
3138 sizeof(sc->sc_hub_desc.temp),
3139 str_ptr);
3140 break;
3141 default:
3142 err = USB_ERR_IOERROR;
3143 goto done;
3144 }
3145 break;
3146 case C(UR_GET_INTERFACE, UT_READ_INTERFACE):
3147 len = 1;
3148 sc->sc_hub_desc.temp[0] = 0;
3149 break;
3150 case C(UR_GET_STATUS, UT_READ_DEVICE):
3151 len = 2;
3152 USETW(sc->sc_hub_desc.stat.wStatus, UDS_SELF_POWERED);
3153 break;
3154 case C(UR_GET_STATUS, UT_READ_INTERFACE):
3155 case C(UR_GET_STATUS, UT_READ_ENDPOINT):
3156 len = 2;
3157 USETW(sc->sc_hub_desc.stat.wStatus, 0);
3158 break;
3159 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE):
3160 if (value >= EHCI_MAX_DEVICES) {
3161 err = USB_ERR_IOERROR;
3162 goto done;
3163 }
3164 sc->sc_addr = value;
3165 break;
3166 case C(UR_SET_CONFIG, UT_WRITE_DEVICE):
3167 if ((value != 0) && (value != 1)) {
3168 err = USB_ERR_IOERROR;
3169 goto done;
3170 }
3171 sc->sc_conf = value;
3172 break;
3173 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE):
3174 break;
3175 case C(UR_SET_FEATURE, UT_WRITE_DEVICE):
3176 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE):
3177 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT):
3178 err = USB_ERR_IOERROR;
3179 goto done;
3180 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE):
3181 break;
3182 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT):
3183 break;
3184 /* Hub requests */
3185 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE):
3186 break;
3187 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER):
3188 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE\n");
3189
3190 if ((index < 1) ||
3191 (index > sc->sc_noport)) {
3192 err = USB_ERR_IOERROR;
3193 goto done;
3194 }
3195 port = EHCI_PORTSC(index);
3196 v = EOREAD4(sc, port) & ~EHCI_PS_CLEAR;
3197 switch (value) {
3198 case UHF_PORT_ENABLE:
3199 EOWRITE4(sc, port, v & ~EHCI_PS_PE);
3200 break;
3201 case UHF_PORT_SUSPEND:
3202 if ((v & EHCI_PS_SUSP) && (!(v & EHCI_PS_FPR))) {
3203
3204 /*
3205 * waking up a High Speed device is rather
3206 * complicated if
3207 */
3208 EOWRITE4(sc, port, v | EHCI_PS_FPR);
3209 }
3210 /* wait 20ms for resume sequence to complete */
3211 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 50);
3212
3213 EOWRITE4(sc, port, v & ~(EHCI_PS_SUSP |
3214 EHCI_PS_FPR | (3 << 10) /* High Speed */ ));
3215
3216 /* 4ms settle time */
3217 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 250);
3218 break;
3219 case UHF_PORT_POWER:
3220 EOWRITE4(sc, port, v & ~EHCI_PS_PP);
3221 break;
3222 case UHF_PORT_TEST:
3223 DPRINTFN(3, "clear port test "
3224 "%d\n", index);
3225 break;
3226 case UHF_PORT_INDICATOR:
3227 DPRINTFN(3, "clear port ind "
3228 "%d\n", index);
3229 EOWRITE4(sc, port, v & ~EHCI_PS_PIC);
3230 break;
3231 case UHF_C_PORT_CONNECTION:
3232 EOWRITE4(sc, port, v | EHCI_PS_CSC);
3233 break;
3234 case UHF_C_PORT_ENABLE:
3235 EOWRITE4(sc, port, v | EHCI_PS_PEC);
3236 break;
3237 case UHF_C_PORT_SUSPEND:
3238 EOWRITE4(sc, port, v | EHCI_PS_SUSP);
3239 break;
3240 case UHF_C_PORT_OVER_CURRENT:
3241 EOWRITE4(sc, port, v | EHCI_PS_OCC);
3242 break;
3243 case UHF_C_PORT_RESET:
3244 sc->sc_isreset = 0;
3245 break;
3246 default:
3247 err = USB_ERR_IOERROR;
3248 goto done;
3249 }
3250 break;
3251 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE):
3252 if ((value & 0xff) != 0) {
3253 err = USB_ERR_IOERROR;
3254 goto done;
3255 }
3256 v = EREAD4(sc, EHCI_HCSPARAMS);
3257
3258 sc->sc_hub_desc.hubd = ehci_hubd;
3259 sc->sc_hub_desc.hubd.bNbrPorts = sc->sc_noport;
3260
3261 if (EHCI_HCS_PPC(v))
3262 i = UHD_PWR_INDIVIDUAL;
3263 else
3264 i = UHD_PWR_NO_SWITCH;
3265
3266 if (EHCI_HCS_P_INDICATOR(v))
3267 i |= UHD_PORT_IND;
3268
3269 USETW(sc->sc_hub_desc.hubd.wHubCharacteristics, i);
3270 /* XXX can't find out? */
3271 sc->sc_hub_desc.hubd.bPwrOn2PwrGood = 200;
3272 /* XXX don't know if ports are removable or not */
3273 sc->sc_hub_desc.hubd.bDescLength =
3274 8 + ((sc->sc_noport + 7) / 8);
3275 len = sc->sc_hub_desc.hubd.bDescLength;
3276 break;
3277 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE):
3278 len = 16;
3279 memset(sc->sc_hub_desc.temp, 0, 16);
3280 break;
3281 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER):
3282 DPRINTFN(9, "get port status i=%d\n",
3283 index);
3284 if ((index < 1) ||
3285 (index > sc->sc_noport)) {
3286 err = USB_ERR_IOERROR;
3287 goto done;
3288 }
3289 v = EOREAD4(sc, EHCI_PORTSC(index));
3290 DPRINTFN(9, "port status=0x%04x\n", v);
3291 if (sc->sc_flags & (EHCI_SCFLG_FORCESPEED | EHCI_SCFLG_TT)) {
3292 if ((v & 0xc000000) == 0x8000000)
3293 i = UPS_HIGH_SPEED;
3294 else if ((v & 0xc000000) == 0x4000000)
3295 i = UPS_LOW_SPEED;
3296 else
3297 i = 0;
3298 } else {
3299 i = UPS_HIGH_SPEED;
3300 }
3301 if (v & EHCI_PS_CS)
3302 i |= UPS_CURRENT_CONNECT_STATUS;
3303 if (v & EHCI_PS_PE)
3304 i |= UPS_PORT_ENABLED;
3305 if ((v & EHCI_PS_SUSP) && !(v & EHCI_PS_FPR))
3306 i |= UPS_SUSPEND;
3307 if (v & EHCI_PS_OCA)
3308 i |= UPS_OVERCURRENT_INDICATOR;
3309 if (v & EHCI_PS_PR)
3310 i |= UPS_RESET;
3311 if (v & EHCI_PS_PP)
3312 i |= UPS_PORT_POWER;
3313 USETW(sc->sc_hub_desc.ps.wPortStatus, i);
3314 i = 0;
3315 if (v & EHCI_PS_CSC)
3316 i |= UPS_C_CONNECT_STATUS;
3317 if (v & EHCI_PS_PEC)
3318 i |= UPS_C_PORT_ENABLED;
3319 if (v & EHCI_PS_OCC)
3320 i |= UPS_C_OVERCURRENT_INDICATOR;
3321 if (v & EHCI_PS_FPR)
3322 i |= UPS_C_SUSPEND;
3323 if (sc->sc_isreset)
3324 i |= UPS_C_PORT_RESET;
3325 USETW(sc->sc_hub_desc.ps.wPortChange, i);
3326 len = sizeof(sc->sc_hub_desc.ps);
3327 break;
3328 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE):
3329 err = USB_ERR_IOERROR;
3330 goto done;
3331 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE):
3332 break;
3333 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER):
3334 if ((index < 1) ||
3335 (index > sc->sc_noport)) {
3336 err = USB_ERR_IOERROR;
3337 goto done;
3338 }
3339 port = EHCI_PORTSC(index);
3340 v = EOREAD4(sc, port) & ~EHCI_PS_CLEAR;
3341 switch (value) {
3342 case UHF_PORT_ENABLE:
3343 EOWRITE4(sc, port, v | EHCI_PS_PE);
3344 break;
3345 case UHF_PORT_SUSPEND:
3346 EOWRITE4(sc, port, v | EHCI_PS_SUSP);
3347 break;
3348 case UHF_PORT_RESET:
3349 DPRINTFN(6, "reset port %d\n", index);
3350#ifdef USB_DEBUG
3351 if (ehcinohighspeed) {
3352 /*
3353 * Connect USB device to companion
3354 * controller.
3355 */
3356 ehci_disown(sc, index, 1);
3357 break;
3358 }
3359#endif
3360 if (EHCI_PS_IS_LOWSPEED(v) &&
3361 (sc->sc_flags & EHCI_SCFLG_TT) == 0) {
3362 /* Low speed device, give up ownership. */
3363 ehci_disown(sc, index, 1);
3364 break;
3365 }
3366 /* Start reset sequence. */
3367 v &= ~(EHCI_PS_PE | EHCI_PS_PR);
3368 EOWRITE4(sc, port, v | EHCI_PS_PR);
3369
3370 /* Wait for reset to complete. */
3371 usb_pause_mtx(&sc->sc_bus.bus_mtx,
3372 USB_MS_TO_TICKS(USB_PORT_ROOT_RESET_DELAY));
3373
3374 /* Terminate reset sequence. */
3375 if (!(sc->sc_flags & EHCI_SCFLG_NORESTERM))
3376 EOWRITE4(sc, port, v);
3377
3378 /* Wait for HC to complete reset. */
3379 usb_pause_mtx(&sc->sc_bus.bus_mtx,
3380 USB_MS_TO_TICKS(EHCI_PORT_RESET_COMPLETE));
3381
3382 v = EOREAD4(sc, port);
3383 DPRINTF("ehci after reset, status=0x%08x\n", v);
3384 if (v & EHCI_PS_PR) {
3385 device_printf(sc->sc_bus.bdev,
3386 "port reset timeout\n");
3387 err = USB_ERR_TIMEOUT;
3388 goto done;
3389 }
3390 if (!(v & EHCI_PS_PE) &&
3391 (sc->sc_flags & EHCI_SCFLG_TT) == 0) {
3392 /* Not a high speed device, give up ownership.*/
3393 ehci_disown(sc, index, 0);
3394 break;
3395 }
3396 sc->sc_isreset = 1;
3397 DPRINTF("ehci port %d reset, status = 0x%08x\n",
3398 index, v);
3399 break;
3400
3401 case UHF_PORT_POWER:
3402 DPRINTFN(3, "set port power %d\n", index);
3403 EOWRITE4(sc, port, v | EHCI_PS_PP);
3404 break;
3405
3406 case UHF_PORT_TEST:
3407 DPRINTFN(3, "set port test %d\n", index);
3408 break;
3409
3410 case UHF_PORT_INDICATOR:
3411 DPRINTFN(3, "set port ind %d\n", index);
3412 EOWRITE4(sc, port, v | EHCI_PS_PIC);
3413 break;
3414
3415 default:
3416 err = USB_ERR_IOERROR;
3417 goto done;
3418 }
3419 break;
3420 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER):
3421 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER):
3422 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER):
3423 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER):
3424 break;
3425 default:
3426 err = USB_ERR_IOERROR;
3427 goto done;
3428 }
3429done:
3430 *plength = len;
3431 *pptr = ptr;
3432 return (err);
3433}
3434
3435static void
3436ehci_xfer_setup(struct usb_setup_params *parm)
3437{
3438 struct usb_page_search page_info;
3439 struct usb_page_cache *pc;
3440 ehci_softc_t *sc;
3441 struct usb_xfer *xfer;
3442 void *last_obj;
3443 uint32_t nqtd;
3444 uint32_t nqh;
3445 uint32_t nsitd;
3446 uint32_t nitd;
3447 uint32_t n;
3448
3449 sc = EHCI_BUS2SC(parm->udev->bus);
3450 xfer = parm->curr_xfer;
3451
3452 nqtd = 0;
3453 nqh = 0;
3454 nsitd = 0;
3455 nitd = 0;
3456
3457 /*
3458 * compute maximum number of some structures
3459 */
3460 if (parm->methods == &ehci_device_ctrl_methods) {
3461
3462 /*
3463 * The proof for the "nqtd" formula is illustrated like
3464 * this:
3465 *
3466 * +------------------------------------+
3467 * | |
3468 * | |remainder -> |
3469 * | +-----+---+ |
3470 * | | xxx | x | frm 0 |
3471 * | +-----+---++ |
3472 * | | xxx | xx | frm 1 |
3473 * | +-----+----+ |
3474 * | ... |
3475 * +------------------------------------+
3476 *
3477 * "xxx" means a completely full USB transfer descriptor
3478 *
3479 * "x" and "xx" means a short USB packet
3480 *
3481 * For the remainder of an USB transfer modulo
3482 * "max_data_length" we need two USB transfer descriptors.
3483 * One to transfer the remaining data and one to finalise
3484 * with a zero length packet in case the "force_short_xfer"
3485 * flag is set. We only need two USB transfer descriptors in
3486 * the case where the transfer length of the first one is a
3487 * factor of "max_frame_size". The rest of the needed USB
3488 * transfer descriptors is given by the buffer size divided
3489 * by the maximum data payload.
3490 */
3491 parm->hc_max_packet_size = 0x400;
3492 parm->hc_max_packet_count = 1;
3493 parm->hc_max_frame_size = EHCI_QTD_PAYLOAD_MAX;
3494 xfer->flags_int.bdma_enable = 1;
3495
3496 usbd_transfer_setup_sub(parm);
3497
3498 nqh = 1;
3499 nqtd = ((2 * xfer->nframes) + 1 /* STATUS */
3500 + (xfer->max_data_length / xfer->max_hc_frame_size));
3501
3502 } else if (parm->methods == &ehci_device_bulk_methods) {
3503
3504 parm->hc_max_packet_size = 0x400;
3505 parm->hc_max_packet_count = 1;
3506 parm->hc_max_frame_size = EHCI_QTD_PAYLOAD_MAX;
3507 xfer->flags_int.bdma_enable = 1;
3508
3509 usbd_transfer_setup_sub(parm);
3510
3511 nqh = 1;
3512 nqtd = ((2 * xfer->nframes)
3513 + (xfer->max_data_length / xfer->max_hc_frame_size));
3514
3515 } else if (parm->methods == &ehci_device_intr_methods) {
3516
3517 if (parm->speed == USB_SPEED_HIGH) {
3518 parm->hc_max_packet_size = 0x400;
3519 parm->hc_max_packet_count = 3;
3520 } else if (parm->speed == USB_SPEED_FULL) {
3521 parm->hc_max_packet_size = USB_FS_BYTES_PER_HS_UFRAME;
3522 parm->hc_max_packet_count = 1;
3523 } else {
3524 parm->hc_max_packet_size = USB_FS_BYTES_PER_HS_UFRAME / 8;
3525 parm->hc_max_packet_count = 1;
3526 }
3527
3528 parm->hc_max_frame_size = EHCI_QTD_PAYLOAD_MAX;
3529 xfer->flags_int.bdma_enable = 1;
3530
3531 usbd_transfer_setup_sub(parm);
3532
3533 nqh = 1;
3534 nqtd = ((2 * xfer->nframes)
3535 + (xfer->max_data_length / xfer->max_hc_frame_size));
3536
3537 } else if (parm->methods == &ehci_device_isoc_fs_methods) {
3538
3539 parm->hc_max_packet_size = 0x3FF;
3540 parm->hc_max_packet_count = 1;
3541 parm->hc_max_frame_size = 0x3FF;
3542 xfer->flags_int.bdma_enable = 1;
3543
3544 usbd_transfer_setup_sub(parm);
3545
3546 nsitd = xfer->nframes;
3547
3548 } else if (parm->methods == &ehci_device_isoc_hs_methods) {
3549
3550 parm->hc_max_packet_size = 0x400;
3551 parm->hc_max_packet_count = 3;
3552 parm->hc_max_frame_size = 0xC00;
3553 xfer->flags_int.bdma_enable = 1;
3554
3555 usbd_transfer_setup_sub(parm);
3556
3557 nitd = ((xfer->nframes + 7) / 8) <<
3558 usbd_xfer_get_fps_shift(xfer);
3559
3560 } else {
3561
3562 parm->hc_max_packet_size = 0x400;
3563 parm->hc_max_packet_count = 1;
3564 parm->hc_max_frame_size = 0x400;
3565
3566 usbd_transfer_setup_sub(parm);
3567 }
3568
3569alloc_dma_set:
3570
3571 if (parm->err) {
3572 return;
3573 }
3574 /*
3575 * Allocate queue heads and transfer descriptors
3576 */
3577 last_obj = NULL;
3578
3579 if (usbd_transfer_setup_sub_malloc(
3580 parm, &pc, sizeof(ehci_itd_t),
3581 EHCI_ITD_ALIGN, nitd)) {
3582 parm->err = USB_ERR_NOMEM;
3583 return;
3584 }
3585 if (parm->buf) {
3586 for (n = 0; n != nitd; n++) {
3587 ehci_itd_t *td;
3588
3589 usbd_get_page(pc + n, 0, &page_info);
3590
3591 td = page_info.buffer;
3592
3593 /* init TD */
3594 td->itd_self = htohc32(sc, page_info.physaddr | EHCI_LINK_ITD);
3595 td->obj_next = last_obj;
3596 td->page_cache = pc + n;
3597
3598 last_obj = td;
3599
3600 usb_pc_cpu_flush(pc + n);
3601 }
3602 }
3603 if (usbd_transfer_setup_sub_malloc(
3604 parm, &pc, sizeof(ehci_sitd_t),
3605 EHCI_SITD_ALIGN, nsitd)) {
3606 parm->err = USB_ERR_NOMEM;
3607 return;
3608 }
3609 if (parm->buf) {
3610 for (n = 0; n != nsitd; n++) {
3611 ehci_sitd_t *td;
3612
3613 usbd_get_page(pc + n, 0, &page_info);
3614
3615 td = page_info.buffer;
3616
3617 /* init TD */
3618 td->sitd_self = htohc32(sc, page_info.physaddr | EHCI_LINK_SITD);
3619 td->obj_next = last_obj;
3620 td->page_cache = pc + n;
3621
3622 last_obj = td;
3623
3624 usb_pc_cpu_flush(pc + n);
3625 }
3626 }
3627 if (usbd_transfer_setup_sub_malloc(
3628 parm, &pc, sizeof(ehci_qtd_t),
3629 EHCI_QTD_ALIGN, nqtd)) {
3630 parm->err = USB_ERR_NOMEM;
3631 return;
3632 }
3633 if (parm->buf) {
3634 for (n = 0; n != nqtd; n++) {
3635 ehci_qtd_t *qtd;
3636
3637 usbd_get_page(pc + n, 0, &page_info);
3638
3639 qtd = page_info.buffer;
3640
3641 /* init TD */
3642 qtd->qtd_self = htohc32(sc, page_info.physaddr);
3643 qtd->obj_next = last_obj;
3644 qtd->page_cache = pc + n;
3645
3646 last_obj = qtd;
3647
3648 usb_pc_cpu_flush(pc + n);
3649 }
3650 }
3651 xfer->td_start[xfer->flags_int.curr_dma_set] = last_obj;
3652
3653 last_obj = NULL;
3654
3655 if (usbd_transfer_setup_sub_malloc(
3656 parm, &pc, sizeof(ehci_qh_t),
3657 EHCI_QH_ALIGN, nqh)) {
3658 parm->err = USB_ERR_NOMEM;
3659 return;
3660 }
3661 if (parm->buf) {
3662 for (n = 0; n != nqh; n++) {
3663 ehci_qh_t *qh;
3664
3665 usbd_get_page(pc + n, 0, &page_info);
3666
3667 qh = page_info.buffer;
3668
3669 /* init QH */
3670 qh->qh_self = htohc32(sc, page_info.physaddr | EHCI_LINK_QH);
3671 qh->obj_next = last_obj;
3672 qh->page_cache = pc + n;
3673
3674 last_obj = qh;
3675
3676 usb_pc_cpu_flush(pc + n);
3677 }
3678 }
3679 xfer->qh_start[xfer->flags_int.curr_dma_set] = last_obj;
3680
3681 if (!xfer->flags_int.curr_dma_set) {
3682 xfer->flags_int.curr_dma_set = 1;
3683 goto alloc_dma_set;
3684 }
3685}
3686
3687static void
3688ehci_xfer_unsetup(struct usb_xfer *xfer)
3689{
3690 return;
3691}
3692
3693static void
3694ehci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc,
3695 struct usb_endpoint *ep)
3696{
3697 ehci_softc_t *sc = EHCI_BUS2SC(udev->bus);
3698
3699 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d (%d)\n",
3700 ep, udev->address,
3701 edesc->bEndpointAddress, udev->flags.usb_mode,
3702 sc->sc_addr);
3703
3704 if (udev->device_index != sc->sc_addr) {
3705
3706 if ((udev->speed != USB_SPEED_HIGH) &&
3707 ((udev->hs_hub_addr == 0) ||
3708 (udev->hs_port_no == 0) ||
3709 (udev->parent_hs_hub == NULL) ||
3710 (udev->parent_hs_hub->hub == NULL))) {
3711 /* We need a transaction translator */
3712 goto done;
3713 }
3714 switch (edesc->bmAttributes & UE_XFERTYPE) {
3715 case UE_CONTROL:
3716 ep->methods = &ehci_device_ctrl_methods;
3717 break;
3718 case UE_INTERRUPT:
3719 ep->methods = &ehci_device_intr_methods;
3720 break;
3721 case UE_ISOCHRONOUS:
3722 if (udev->speed == USB_SPEED_HIGH) {
3723 ep->methods = &ehci_device_isoc_hs_methods;
3724 } else if (udev->speed == USB_SPEED_FULL) {
3725 ep->methods = &ehci_device_isoc_fs_methods;
3726 }
3727 break;
3728 case UE_BULK:
3729 ep->methods = &ehci_device_bulk_methods;
3730 break;
3731 default:
3732 /* do nothing */
3733 break;
3734 }
3735 }
3736done:
3737 return;
3738}
3739
3740static void
3741ehci_get_dma_delay(struct usb_device *udev, uint32_t *pus)
3742{
3743 /*
3744 * Wait until the hardware has finished any possible use of
3745 * the transfer descriptor(s) and QH
3746 */
3747 *pus = (188); /* microseconds */
3748}
3749
3750static void
3751ehci_device_resume(struct usb_device *udev)
3752{
3753 ehci_softc_t *sc = EHCI_BUS2SC(udev->bus);
3754 struct usb_xfer *xfer;
3755 struct usb_pipe_methods *methods;
3756
3757 DPRINTF("\n");
3758
3759 USB_BUS_LOCK(udev->bus);
3760
3761 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
3762
3763 if (xfer->xroot->udev == udev) {
3764
3765 methods = xfer->endpoint->methods;
3766
3767 if ((methods == &ehci_device_bulk_methods) ||
3768 (methods == &ehci_device_ctrl_methods)) {
3769 EHCI_APPEND_QH(xfer->qh_start[xfer->flags_int.curr_dma_set],
3770 sc->sc_async_p_last);
3771 }
3772 if (methods == &ehci_device_intr_methods) {
3773 EHCI_APPEND_QH(xfer->qh_start[xfer->flags_int.curr_dma_set],
3774 sc->sc_intr_p_last[xfer->qh_pos]);
3775 }
3776 }
3777 }
3778
3779 USB_BUS_UNLOCK(udev->bus);
3780
3781 return;
3782}
3783
3784static void
3785ehci_device_suspend(struct usb_device *udev)
3786{
3787 ehci_softc_t *sc = EHCI_BUS2SC(udev->bus);
3788 struct usb_xfer *xfer;
3789 struct usb_pipe_methods *methods;
3790
3791 DPRINTF("\n");
3792
3793 USB_BUS_LOCK(udev->bus);
3794
3795 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
3796
3797 if (xfer->xroot->udev == udev) {
3798
3799 methods = xfer->endpoint->methods;
3800
3801 if ((methods == &ehci_device_bulk_methods) ||
3802 (methods == &ehci_device_ctrl_methods)) {
3803 EHCI_REMOVE_QH(xfer->qh_start[xfer->flags_int.curr_dma_set],
3804 sc->sc_async_p_last);
3805 }
3806 if (methods == &ehci_device_intr_methods) {
3807 EHCI_REMOVE_QH(xfer->qh_start[xfer->flags_int.curr_dma_set],
3808 sc->sc_intr_p_last[xfer->qh_pos]);
3809 }
3810 }
3811 }
3812
3813 USB_BUS_UNLOCK(udev->bus);
3814}
3815
3816static void
3817ehci_set_hw_power_sleep(struct usb_bus *bus, uint32_t state)
3818{
3819 struct ehci_softc *sc = EHCI_BUS2SC(bus);
3820
3821 switch (state) {
3822 case USB_HW_POWER_SUSPEND:
3823 case USB_HW_POWER_SHUTDOWN:
3824 ehci_suspend(sc);
3825 break;
3826 case USB_HW_POWER_RESUME:
3827 ehci_resume(sc);
3828 break;
3829 default:
3830 break;
3831 }
3832}
3833
3834static void
3835ehci_set_hw_power(struct usb_bus *bus)
3836{
3837 ehci_softc_t *sc = EHCI_BUS2SC(bus);
3838 uint32_t temp;
3839 uint32_t flags;
3840
3841 DPRINTF("\n");
3842
3843 USB_BUS_LOCK(bus);
3844
3845 flags = bus->hw_power_state;
3846
3847 temp = EOREAD4(sc, EHCI_USBCMD);
3848
3849 temp &= ~(EHCI_CMD_ASE | EHCI_CMD_PSE);
3850
3851 if (flags & (USB_HW_POWER_CONTROL |
3852 USB_HW_POWER_BULK)) {
3853 DPRINTF("Async is active\n");
3854 temp |= EHCI_CMD_ASE;
3855 }
3856 if (flags & (USB_HW_POWER_INTERRUPT |
3857 USB_HW_POWER_ISOC)) {
3858 DPRINTF("Periodic is active\n");
3859 temp |= EHCI_CMD_PSE;
3860 }
3861 EOWRITE4(sc, EHCI_USBCMD, temp);
3862
3863 USB_BUS_UNLOCK(bus);
3864
3865 return;
3866}
3867
3868struct usb_bus_methods ehci_bus_methods =
3869{
3870 .endpoint_init = ehci_ep_init,
3871 .xfer_setup = ehci_xfer_setup,
3872 .xfer_unsetup = ehci_xfer_unsetup,
3873 .get_dma_delay = ehci_get_dma_delay,
3874 .device_resume = ehci_device_resume,
3875 .device_suspend = ehci_device_suspend,
3876 .set_hw_power = ehci_set_hw_power,
3877 .set_hw_power_sleep = ehci_set_hw_power_sleep,
3878 .roothub_exec = ehci_roothub_exec,
3879 .xfer_poll = ehci_do_poll,
3880};