1#include <sys/cdefs.h>
| 1#include <sys/cdefs.h>
|
2__FBSDID("$FreeBSD: head/sys/dev/usb/controller/avr32dci.c 193644 2009-06-07 19:41:11Z thompsa $");
| 2__FBSDID("$FreeBSD: head/sys/dev/usb/controller/avr32dci.c 194228 2009-06-15 01:02:43Z thompsa $");
|
3
4/*-
5 * Copyright (c) 2009 Hans Petter Selasky. All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29/*
30 * This file contains the driver for the AVR32 series USB Device
31 * Controller
32 */
33
34/*
35 * NOTE: When the chip detects BUS-reset it will also reset the
36 * endpoints, Function-address and more.
37 */
38
39#include <dev/usb/usb.h>
40#include <dev/usb/usb_mfunc.h>
41#include <dev/usb/usb_error.h>
42
43#define USB_DEBUG_VAR avr32dci_debug
44
45#include <dev/usb/usb_core.h>
46#include <dev/usb/usb_debug.h>
47#include <dev/usb/usb_busdma.h>
48#include <dev/usb/usb_process.h>
49#include <dev/usb/usb_transfer.h>
50#include <dev/usb/usb_device.h>
51#include <dev/usb/usb_hub.h>
52#include <dev/usb/usb_util.h>
53
54#include <dev/usb/usb_controller.h>
55#include <dev/usb/usb_bus.h>
56#include <dev/usb/controller/avr32dci.h>
57
58#define AVR32_BUS2SC(bus) \
59 ((struct avr32dci_softc *)(((uint8_t *)(bus)) - \
60 ((uint8_t *)&(((struct avr32dci_softc *)0)->sc_bus))))
61
62#define AVR32_PC2SC(pc) \
63 AVR32_BUS2SC(USB_DMATAG_TO_XROOT((pc)->tag_parent)->bus)
64
65#if USB_DEBUG
66static int avr32dci_debug = 0;
67
68SYSCTL_NODE(_hw_usb, OID_AUTO, avr32dci, CTLFLAG_RW, 0, "USB AVR32 DCI");
69SYSCTL_INT(_hw_usb_avr32dci, OID_AUTO, debug, CTLFLAG_RW,
70 &avr32dci_debug, 0, "AVR32 DCI debug level");
71#endif
72
73#define AVR32_INTR_ENDPT 1
74
75/* prototypes */
76
77struct usb_bus_methods avr32dci_bus_methods;
78struct usb_pipe_methods avr32dci_device_non_isoc_methods;
79struct usb_pipe_methods avr32dci_device_isoc_fs_methods;
80
81static avr32dci_cmd_t avr32dci_setup_rx;
82static avr32dci_cmd_t avr32dci_data_rx;
83static avr32dci_cmd_t avr32dci_data_tx;
84static avr32dci_cmd_t avr32dci_data_tx_sync;
85static void avr32dci_device_done(struct usb_xfer *, usb_error_t);
86static void avr32dci_do_poll(struct usb_bus *);
87static void avr32dci_standard_done(struct usb_xfer *);
88static void avr32dci_root_intr(struct avr32dci_softc *sc);
89
90/*
91 * Here is a list of what the chip supports:
92 */
93static const struct usb_hw_ep_profile
94 avr32dci_ep_profile[4] = {
95
96 [0] = {
97 .max_in_frame_size = 64,
98 .max_out_frame_size = 64,
99 .is_simplex = 1,
100 .support_control = 1,
101 },
102
103 [1] = {
104 .max_in_frame_size = 512,
105 .max_out_frame_size = 512,
106 .is_simplex = 1,
107 .support_bulk = 1,
108 .support_interrupt = 1,
109 .support_isochronous = 1,
110 .support_in = 1,
111 .support_out = 1,
112 },
113
114 [2] = {
115 .max_in_frame_size = 64,
116 .max_out_frame_size = 64,
117 .is_simplex = 1,
118 .support_bulk = 1,
119 .support_interrupt = 1,
120 .support_in = 1,
121 .support_out = 1,
122 },
123
124 [3] = {
125 .max_in_frame_size = 1024,
126 .max_out_frame_size = 1024,
127 .is_simplex = 1,
128 .support_bulk = 1,
129 .support_interrupt = 1,
130 .support_isochronous = 1,
131 .support_in = 1,
132 .support_out = 1,
133 },
134};
135
136static void
137avr32dci_get_hw_ep_profile(struct usb_device *udev,
138 const struct usb_hw_ep_profile **ppf, uint8_t ep_addr)
139{
140 if (ep_addr == 0)
141 *ppf = avr32dci_ep_profile;
142 else if (ep_addr < 3)
143 *ppf = avr32dci_ep_profile + 1;
144 else if (ep_addr < 5)
145 *ppf = avr32dci_ep_profile + 2;
146 else if (ep_addr < 7)
147 *ppf = avr32dci_ep_profile + 3;
148 else
149 *ppf = NULL;
150}
151
152static void
153avr32dci_mod_ctrl(struct avr32dci_softc *sc, uint32_t set, uint32_t clear)
154{
155 uint32_t temp;
156
157 temp = AVR32_READ_4(sc, AVR32_CTRL);
158 temp |= set;
159 temp &= ~clear;
160 AVR32_WRITE_4(sc, AVR32_CTRL, temp);
161}
162
163static void
164avr32dci_mod_ien(struct avr32dci_softc *sc, uint32_t set, uint32_t clear)
165{
166 uint32_t temp;
167
168 temp = AVR32_READ_4(sc, AVR32_IEN);
169 temp |= set;
170 temp &= ~clear;
171 AVR32_WRITE_4(sc, AVR32_IEN, temp);
172}
173
174static void
175avr32dci_clocks_on(struct avr32dci_softc *sc)
176{
177 if (sc->sc_flags.clocks_off &&
178 sc->sc_flags.port_powered) {
179
180 DPRINTFN(5, "\n");
181
182 /* turn on clocks */
183 (sc->sc_clocks_on) (&sc->sc_bus);
184
185 avr32dci_mod_ctrl(sc, AVR32_CTRL_DEV_EN_USBA, 0);
186
187 sc->sc_flags.clocks_off = 0;
188 }
189}
190
191static void
192avr32dci_clocks_off(struct avr32dci_softc *sc)
193{
194 if (!sc->sc_flags.clocks_off) {
195
196 DPRINTFN(5, "\n");
197
198 avr32dci_mod_ctrl(sc, 0, AVR32_CTRL_DEV_EN_USBA);
199
200 /* turn clocks off */
201 (sc->sc_clocks_off) (&sc->sc_bus);
202
203 sc->sc_flags.clocks_off = 1;
204 }
205}
206
207static void
208avr32dci_pull_up(struct avr32dci_softc *sc)
209{
210 /* pullup D+, if possible */
211
212 if (!sc->sc_flags.d_pulled_up &&
213 sc->sc_flags.port_powered) {
214 sc->sc_flags.d_pulled_up = 1;
215 avr32dci_mod_ctrl(sc, 0, AVR32_CTRL_DEV_DETACH);
216 }
217}
218
219static void
220avr32dci_pull_down(struct avr32dci_softc *sc)
221{
222 /* pulldown D+, if possible */
223
224 if (sc->sc_flags.d_pulled_up) {
225 sc->sc_flags.d_pulled_up = 0;
226 avr32dci_mod_ctrl(sc, AVR32_CTRL_DEV_DETACH, 0);
227 }
228}
229
230static void
231avr32dci_wakeup_peer(struct avr32dci_softc *sc)
232{
233 if (!sc->sc_flags.status_suspend) {
234 return;
235 }
236 avr32dci_mod_ctrl(sc, AVR32_CTRL_DEV_REWAKEUP, 0);
237
238 /* wait 8 milliseconds */
239 /* Wait for reset to complete. */
| 3
4/*-
5 * Copyright (c) 2009 Hans Petter Selasky. All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29/*
30 * This file contains the driver for the AVR32 series USB Device
31 * Controller
32 */
33
34/*
35 * NOTE: When the chip detects BUS-reset it will also reset the
36 * endpoints, Function-address and more.
37 */
38
39#include <dev/usb/usb.h>
40#include <dev/usb/usb_mfunc.h>
41#include <dev/usb/usb_error.h>
42
43#define USB_DEBUG_VAR avr32dci_debug
44
45#include <dev/usb/usb_core.h>
46#include <dev/usb/usb_debug.h>
47#include <dev/usb/usb_busdma.h>
48#include <dev/usb/usb_process.h>
49#include <dev/usb/usb_transfer.h>
50#include <dev/usb/usb_device.h>
51#include <dev/usb/usb_hub.h>
52#include <dev/usb/usb_util.h>
53
54#include <dev/usb/usb_controller.h>
55#include <dev/usb/usb_bus.h>
56#include <dev/usb/controller/avr32dci.h>
57
58#define AVR32_BUS2SC(bus) \
59 ((struct avr32dci_softc *)(((uint8_t *)(bus)) - \
60 ((uint8_t *)&(((struct avr32dci_softc *)0)->sc_bus))))
61
62#define AVR32_PC2SC(pc) \
63 AVR32_BUS2SC(USB_DMATAG_TO_XROOT((pc)->tag_parent)->bus)
64
65#if USB_DEBUG
66static int avr32dci_debug = 0;
67
68SYSCTL_NODE(_hw_usb, OID_AUTO, avr32dci, CTLFLAG_RW, 0, "USB AVR32 DCI");
69SYSCTL_INT(_hw_usb_avr32dci, OID_AUTO, debug, CTLFLAG_RW,
70 &avr32dci_debug, 0, "AVR32 DCI debug level");
71#endif
72
73#define AVR32_INTR_ENDPT 1
74
75/* prototypes */
76
77struct usb_bus_methods avr32dci_bus_methods;
78struct usb_pipe_methods avr32dci_device_non_isoc_methods;
79struct usb_pipe_methods avr32dci_device_isoc_fs_methods;
80
81static avr32dci_cmd_t avr32dci_setup_rx;
82static avr32dci_cmd_t avr32dci_data_rx;
83static avr32dci_cmd_t avr32dci_data_tx;
84static avr32dci_cmd_t avr32dci_data_tx_sync;
85static void avr32dci_device_done(struct usb_xfer *, usb_error_t);
86static void avr32dci_do_poll(struct usb_bus *);
87static void avr32dci_standard_done(struct usb_xfer *);
88static void avr32dci_root_intr(struct avr32dci_softc *sc);
89
90/*
91 * Here is a list of what the chip supports:
92 */
93static const struct usb_hw_ep_profile
94 avr32dci_ep_profile[4] = {
95
96 [0] = {
97 .max_in_frame_size = 64,
98 .max_out_frame_size = 64,
99 .is_simplex = 1,
100 .support_control = 1,
101 },
102
103 [1] = {
104 .max_in_frame_size = 512,
105 .max_out_frame_size = 512,
106 .is_simplex = 1,
107 .support_bulk = 1,
108 .support_interrupt = 1,
109 .support_isochronous = 1,
110 .support_in = 1,
111 .support_out = 1,
112 },
113
114 [2] = {
115 .max_in_frame_size = 64,
116 .max_out_frame_size = 64,
117 .is_simplex = 1,
118 .support_bulk = 1,
119 .support_interrupt = 1,
120 .support_in = 1,
121 .support_out = 1,
122 },
123
124 [3] = {
125 .max_in_frame_size = 1024,
126 .max_out_frame_size = 1024,
127 .is_simplex = 1,
128 .support_bulk = 1,
129 .support_interrupt = 1,
130 .support_isochronous = 1,
131 .support_in = 1,
132 .support_out = 1,
133 },
134};
135
136static void
137avr32dci_get_hw_ep_profile(struct usb_device *udev,
138 const struct usb_hw_ep_profile **ppf, uint8_t ep_addr)
139{
140 if (ep_addr == 0)
141 *ppf = avr32dci_ep_profile;
142 else if (ep_addr < 3)
143 *ppf = avr32dci_ep_profile + 1;
144 else if (ep_addr < 5)
145 *ppf = avr32dci_ep_profile + 2;
146 else if (ep_addr < 7)
147 *ppf = avr32dci_ep_profile + 3;
148 else
149 *ppf = NULL;
150}
151
152static void
153avr32dci_mod_ctrl(struct avr32dci_softc *sc, uint32_t set, uint32_t clear)
154{
155 uint32_t temp;
156
157 temp = AVR32_READ_4(sc, AVR32_CTRL);
158 temp |= set;
159 temp &= ~clear;
160 AVR32_WRITE_4(sc, AVR32_CTRL, temp);
161}
162
163static void
164avr32dci_mod_ien(struct avr32dci_softc *sc, uint32_t set, uint32_t clear)
165{
166 uint32_t temp;
167
168 temp = AVR32_READ_4(sc, AVR32_IEN);
169 temp |= set;
170 temp &= ~clear;
171 AVR32_WRITE_4(sc, AVR32_IEN, temp);
172}
173
174static void
175avr32dci_clocks_on(struct avr32dci_softc *sc)
176{
177 if (sc->sc_flags.clocks_off &&
178 sc->sc_flags.port_powered) {
179
180 DPRINTFN(5, "\n");
181
182 /* turn on clocks */
183 (sc->sc_clocks_on) (&sc->sc_bus);
184
185 avr32dci_mod_ctrl(sc, AVR32_CTRL_DEV_EN_USBA, 0);
186
187 sc->sc_flags.clocks_off = 0;
188 }
189}
190
191static void
192avr32dci_clocks_off(struct avr32dci_softc *sc)
193{
194 if (!sc->sc_flags.clocks_off) {
195
196 DPRINTFN(5, "\n");
197
198 avr32dci_mod_ctrl(sc, 0, AVR32_CTRL_DEV_EN_USBA);
199
200 /* turn clocks off */
201 (sc->sc_clocks_off) (&sc->sc_bus);
202
203 sc->sc_flags.clocks_off = 1;
204 }
205}
206
207static void
208avr32dci_pull_up(struct avr32dci_softc *sc)
209{
210 /* pullup D+, if possible */
211
212 if (!sc->sc_flags.d_pulled_up &&
213 sc->sc_flags.port_powered) {
214 sc->sc_flags.d_pulled_up = 1;
215 avr32dci_mod_ctrl(sc, 0, AVR32_CTRL_DEV_DETACH);
216 }
217}
218
219static void
220avr32dci_pull_down(struct avr32dci_softc *sc)
221{
222 /* pulldown D+, if possible */
223
224 if (sc->sc_flags.d_pulled_up) {
225 sc->sc_flags.d_pulled_up = 0;
226 avr32dci_mod_ctrl(sc, AVR32_CTRL_DEV_DETACH, 0);
227 }
228}
229
230static void
231avr32dci_wakeup_peer(struct avr32dci_softc *sc)
232{
233 if (!sc->sc_flags.status_suspend) {
234 return;
235 }
236 avr32dci_mod_ctrl(sc, AVR32_CTRL_DEV_REWAKEUP, 0);
237
238 /* wait 8 milliseconds */
239 /* Wait for reset to complete. */
|
240 usb2_pause_mtx(&sc->sc_bus.bus_mtx, hz / 125);
| 240 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 125);
|
241
242 /* hardware should have cleared RMWKUP bit */
243}
244
245static void
246avr32dci_set_address(struct avr32dci_softc *sc, uint8_t addr)
247{
248 DPRINTFN(5, "addr=%d\n", addr);
249
250 avr32dci_mod_ctrl(sc, AVR32_UDADDR_ADDEN | addr, 0);
251}
252
253static uint8_t
254avr32dci_setup_rx(struct avr32dci_td *td)
255{
256 struct avr32dci_softc *sc;
257 struct usb_device_request req;
258 uint16_t count;
259 uint32_t temp;
260
261 /* get pointer to softc */
262 sc = AVR32_PC2SC(td->pc);
263
264 /* check endpoint status */
265 temp = AVR32_READ_4(sc, AVR32_EPTSTA(td->ep_no));
266
267 DPRINTFN(5, "EPTSTA(%u)=0x%08x\n", td->ep_no, temp);
268
269 if (!(temp & AVR32_EPTSTA_RX_SETUP)) {
270 goto not_complete;
271 }
272 /* clear did stall */
273 td->did_stall = 0;
274 /* get the packet byte count */
275 count = AVR32_EPTSTA_BYTE_COUNT(temp);
276
277 /* verify data length */
278 if (count != td->remainder) {
279 DPRINTFN(0, "Invalid SETUP packet "
280 "length, %d bytes\n", count);
281 goto not_complete;
282 }
283 if (count != sizeof(req)) {
284 DPRINTFN(0, "Unsupported SETUP packet "
285 "length, %d bytes\n", count);
286 goto not_complete;
287 }
288 /* receive data */
289 memcpy(&req, sc->physdata, sizeof(req));
290
291 /* copy data into real buffer */
| 241
242 /* hardware should have cleared RMWKUP bit */
243}
244
245static void
246avr32dci_set_address(struct avr32dci_softc *sc, uint8_t addr)
247{
248 DPRINTFN(5, "addr=%d\n", addr);
249
250 avr32dci_mod_ctrl(sc, AVR32_UDADDR_ADDEN | addr, 0);
251}
252
253static uint8_t
254avr32dci_setup_rx(struct avr32dci_td *td)
255{
256 struct avr32dci_softc *sc;
257 struct usb_device_request req;
258 uint16_t count;
259 uint32_t temp;
260
261 /* get pointer to softc */
262 sc = AVR32_PC2SC(td->pc);
263
264 /* check endpoint status */
265 temp = AVR32_READ_4(sc, AVR32_EPTSTA(td->ep_no));
266
267 DPRINTFN(5, "EPTSTA(%u)=0x%08x\n", td->ep_no, temp);
268
269 if (!(temp & AVR32_EPTSTA_RX_SETUP)) {
270 goto not_complete;
271 }
272 /* clear did stall */
273 td->did_stall = 0;
274 /* get the packet byte count */
275 count = AVR32_EPTSTA_BYTE_COUNT(temp);
276
277 /* verify data length */
278 if (count != td->remainder) {
279 DPRINTFN(0, "Invalid SETUP packet "
280 "length, %d bytes\n", count);
281 goto not_complete;
282 }
283 if (count != sizeof(req)) {
284 DPRINTFN(0, "Unsupported SETUP packet "
285 "length, %d bytes\n", count);
286 goto not_complete;
287 }
288 /* receive data */
289 memcpy(&req, sc->physdata, sizeof(req));
290
291 /* copy data into real buffer */
|
292 usb2_copy_in(td->pc, 0, &req, sizeof(req));
| 292 usbd_copy_in(td->pc, 0, &req, sizeof(req));
|
293
294 td->offset = sizeof(req);
295 td->remainder = 0;
296
297 /* sneak peek the set address */
298 if ((req.bmRequestType == UT_WRITE_DEVICE) &&
299 (req.bRequest == UR_SET_ADDRESS)) {
300 sc->sc_dv_addr = req.wValue[0] & 0x7F;
301 /* must write address before ZLP */
302 avr32dci_mod_ctrl(sc, 0, AVR32_CTRL_DEV_FADDR_EN |
303 AVR32_CTRL_DEV_ADDR);
304 avr32dci_mod_ctrl(sc, sc->sc_dv_addr, 0);
305 } else {
306 sc->sc_dv_addr = 0xFF;
307 }
308
309 /* clear SETUP packet interrupt */
310 AVR32_WRITE_4(sc, AVR32_EPTCLRSTA(td->ep_no), AVR32_EPTSTA_RX_SETUP);
311 return (0); /* complete */
312
313not_complete:
314 if (temp & AVR32_EPTSTA_RX_SETUP) {
315 /* clear SETUP packet interrupt */
316 AVR32_WRITE_4(sc, AVR32_EPTCLRSTA(td->ep_no), AVR32_EPTSTA_RX_SETUP);
317 }
318 /* abort any ongoing transfer */
319 if (!td->did_stall) {
320 DPRINTFN(5, "stalling\n");
321 AVR32_WRITE_4(sc, AVR32_EPTSETSTA(td->ep_no),
322 AVR32_EPTSTA_FRCESTALL);
323 td->did_stall = 1;
324 }
325 return (1); /* not complete */
326}
327
328static uint8_t
329avr32dci_data_rx(struct avr32dci_td *td)
330{
331 struct avr32dci_softc *sc;
332 struct usb_page_search buf_res;
333 uint16_t count;
334 uint32_t temp;
335 uint8_t to;
336 uint8_t got_short;
337
338 to = 4; /* don't loop forever! */
339 got_short = 0;
340
341 /* get pointer to softc */
342 sc = AVR32_PC2SC(td->pc);
343
344repeat:
345 /* check if any of the FIFO banks have data */
346 /* check endpoint status */
347 temp = AVR32_READ_4(sc, AVR32_EPTSTA(td->ep_no));
348
349 DPRINTFN(5, "EPTSTA(%u)=0x%08x\n", td->ep_no, temp);
350
351 if (temp & AVR32_EPTSTA_RX_SETUP) {
352 if (td->remainder == 0) {
353 /*
354 * We are actually complete and have
355 * received the next SETUP
356 */
357 DPRINTFN(5, "faking complete\n");
358 return (0); /* complete */
359 }
360 /*
361 * USB Host Aborted the transfer.
362 */
363 td->error = 1;
364 return (0); /* complete */
365 }
366 /* check status */
367 if (!(temp & AVR32_EPTSTA_RX_BK_RDY)) {
368 /* no data */
369 goto not_complete;
370 }
371 /* get the packet byte count */
372 count = AVR32_EPTSTA_BYTE_COUNT(temp);
373
374 /* verify the packet byte count */
375 if (count != td->max_packet_size) {
376 if (count < td->max_packet_size) {
377 /* we have a short packet */
378 td->short_pkt = 1;
379 got_short = 1;
380 } else {
381 /* invalid USB packet */
382 td->error = 1;
383 return (0); /* we are complete */
384 }
385 }
386 /* verify the packet byte count */
387 if (count > td->remainder) {
388 /* invalid USB packet */
389 td->error = 1;
390 return (0); /* we are complete */
391 }
392 while (count > 0) {
| 293
294 td->offset = sizeof(req);
295 td->remainder = 0;
296
297 /* sneak peek the set address */
298 if ((req.bmRequestType == UT_WRITE_DEVICE) &&
299 (req.bRequest == UR_SET_ADDRESS)) {
300 sc->sc_dv_addr = req.wValue[0] & 0x7F;
301 /* must write address before ZLP */
302 avr32dci_mod_ctrl(sc, 0, AVR32_CTRL_DEV_FADDR_EN |
303 AVR32_CTRL_DEV_ADDR);
304 avr32dci_mod_ctrl(sc, sc->sc_dv_addr, 0);
305 } else {
306 sc->sc_dv_addr = 0xFF;
307 }
308
309 /* clear SETUP packet interrupt */
310 AVR32_WRITE_4(sc, AVR32_EPTCLRSTA(td->ep_no), AVR32_EPTSTA_RX_SETUP);
311 return (0); /* complete */
312
313not_complete:
314 if (temp & AVR32_EPTSTA_RX_SETUP) {
315 /* clear SETUP packet interrupt */
316 AVR32_WRITE_4(sc, AVR32_EPTCLRSTA(td->ep_no), AVR32_EPTSTA_RX_SETUP);
317 }
318 /* abort any ongoing transfer */
319 if (!td->did_stall) {
320 DPRINTFN(5, "stalling\n");
321 AVR32_WRITE_4(sc, AVR32_EPTSETSTA(td->ep_no),
322 AVR32_EPTSTA_FRCESTALL);
323 td->did_stall = 1;
324 }
325 return (1); /* not complete */
326}
327
328static uint8_t
329avr32dci_data_rx(struct avr32dci_td *td)
330{
331 struct avr32dci_softc *sc;
332 struct usb_page_search buf_res;
333 uint16_t count;
334 uint32_t temp;
335 uint8_t to;
336 uint8_t got_short;
337
338 to = 4; /* don't loop forever! */
339 got_short = 0;
340
341 /* get pointer to softc */
342 sc = AVR32_PC2SC(td->pc);
343
344repeat:
345 /* check if any of the FIFO banks have data */
346 /* check endpoint status */
347 temp = AVR32_READ_4(sc, AVR32_EPTSTA(td->ep_no));
348
349 DPRINTFN(5, "EPTSTA(%u)=0x%08x\n", td->ep_no, temp);
350
351 if (temp & AVR32_EPTSTA_RX_SETUP) {
352 if (td->remainder == 0) {
353 /*
354 * We are actually complete and have
355 * received the next SETUP
356 */
357 DPRINTFN(5, "faking complete\n");
358 return (0); /* complete */
359 }
360 /*
361 * USB Host Aborted the transfer.
362 */
363 td->error = 1;
364 return (0); /* complete */
365 }
366 /* check status */
367 if (!(temp & AVR32_EPTSTA_RX_BK_RDY)) {
368 /* no data */
369 goto not_complete;
370 }
371 /* get the packet byte count */
372 count = AVR32_EPTSTA_BYTE_COUNT(temp);
373
374 /* verify the packet byte count */
375 if (count != td->max_packet_size) {
376 if (count < td->max_packet_size) {
377 /* we have a short packet */
378 td->short_pkt = 1;
379 got_short = 1;
380 } else {
381 /* invalid USB packet */
382 td->error = 1;
383 return (0); /* we are complete */
384 }
385 }
386 /* verify the packet byte count */
387 if (count > td->remainder) {
388 /* invalid USB packet */
389 td->error = 1;
390 return (0); /* we are complete */
391 }
392 while (count > 0) {
|
393 usb2_get_page(td->pc, td->offset, &buf_res);
| 393 usbd_get_page(td->pc, td->offset, &buf_res);
|
394
395 /* get correct length */
396 if (buf_res.length > count) {
397 buf_res.length = count;
398 }
399 /* receive data */
400 bcopy(sc->physdata +
401 (AVR32_EPTSTA_CURRENT_BANK(temp) << td->bank_shift) +
402 (td->ep_no << 16) + (td->offset % td->max_packet_size),
403 buf_res.buffer, buf_res.length)
404 /* update counters */
405 count -= buf_res.length;
406 td->offset += buf_res.length;
407 td->remainder -= buf_res.length;
408 }
409
410 /* clear OUT packet interrupt */
411 AVR32_WRITE_4(sc, AVR32_EPTCLRSTA(td->ep_no), AVR32_EPTSTA_RX_BK_RDY);
412
413 /* check if we are complete */
414 if ((td->remainder == 0) || got_short) {
415 if (td->short_pkt) {
416 /* we are complete */
417 return (0);
418 }
419 /* else need to receive a zero length packet */
420 }
421 if (--to) {
422 goto repeat;
423 }
424not_complete:
425 return (1); /* not complete */
426}
427
428static uint8_t
429avr32dci_data_tx(struct avr32dci_td *td)
430{
431 struct avr32dci_softc *sc;
432 struct usb_page_search buf_res;
433 uint16_t count;
434 uint8_t to;
435 uint32_t temp;
436
437 to = 4; /* don't loop forever! */
438
439 /* get pointer to softc */
440 sc = AVR32_PC2SC(td->pc);
441
442repeat:
443
444 /* check endpoint status */
445 temp = AVR32_READ_4(sc, AVR32_EPTSTA(td->ep_no));
446
447 DPRINTFN(5, "EPTSTA(%u)=0x%08x\n", td->ep_no, temp);
448
449 if (temp & AVR32_EPTSTA_RX_SETUP) {
450 /*
451 * The current transfer was aborted
452 * by the USB Host
453 */
454 td->error = 1;
455 return (0); /* complete */
456 }
457 if (temp & AVR32_EPTSTA_TX_PK_RDY) {
458 /* cannot write any data - all banks are busy */
459 goto not_complete;
460 }
461 count = td->max_packet_size;
462 if (td->remainder < count) {
463 /* we have a short packet */
464 td->short_pkt = 1;
465 count = td->remainder;
466 }
467 while (count > 0) {
468
| 394
395 /* get correct length */
396 if (buf_res.length > count) {
397 buf_res.length = count;
398 }
399 /* receive data */
400 bcopy(sc->physdata +
401 (AVR32_EPTSTA_CURRENT_BANK(temp) << td->bank_shift) +
402 (td->ep_no << 16) + (td->offset % td->max_packet_size),
403 buf_res.buffer, buf_res.length)
404 /* update counters */
405 count -= buf_res.length;
406 td->offset += buf_res.length;
407 td->remainder -= buf_res.length;
408 }
409
410 /* clear OUT packet interrupt */
411 AVR32_WRITE_4(sc, AVR32_EPTCLRSTA(td->ep_no), AVR32_EPTSTA_RX_BK_RDY);
412
413 /* check if we are complete */
414 if ((td->remainder == 0) || got_short) {
415 if (td->short_pkt) {
416 /* we are complete */
417 return (0);
418 }
419 /* else need to receive a zero length packet */
420 }
421 if (--to) {
422 goto repeat;
423 }
424not_complete:
425 return (1); /* not complete */
426}
427
428static uint8_t
429avr32dci_data_tx(struct avr32dci_td *td)
430{
431 struct avr32dci_softc *sc;
432 struct usb_page_search buf_res;
433 uint16_t count;
434 uint8_t to;
435 uint32_t temp;
436
437 to = 4; /* don't loop forever! */
438
439 /* get pointer to softc */
440 sc = AVR32_PC2SC(td->pc);
441
442repeat:
443
444 /* check endpoint status */
445 temp = AVR32_READ_4(sc, AVR32_EPTSTA(td->ep_no));
446
447 DPRINTFN(5, "EPTSTA(%u)=0x%08x\n", td->ep_no, temp);
448
449 if (temp & AVR32_EPTSTA_RX_SETUP) {
450 /*
451 * The current transfer was aborted
452 * by the USB Host
453 */
454 td->error = 1;
455 return (0); /* complete */
456 }
457 if (temp & AVR32_EPTSTA_TX_PK_RDY) {
458 /* cannot write any data - all banks are busy */
459 goto not_complete;
460 }
461 count = td->max_packet_size;
462 if (td->remainder < count) {
463 /* we have a short packet */
464 td->short_pkt = 1;
465 count = td->remainder;
466 }
467 while (count > 0) {
468
|
469 usb2_get_page(td->pc, td->offset, &buf_res);
| 469 usbd_get_page(td->pc, td->offset, &buf_res);
|
470
471 /* get correct length */
472 if (buf_res.length > count) {
473 buf_res.length = count;
474 }
475 /* transmit data */
476 bcopy(buf_res.buffer, sc->physdata +
477 (AVR32_EPTSTA_CURRENT_BANK(temp) << td->bank_shift) +
478 (td->ep_no << 16) + (td->offset % td->max_packet_size),
479 buf_res.length)
480 /* update counters */
481 count -= buf_res.length;
482 td->offset += buf_res.length;
483 td->remainder -= buf_res.length;
484 }
485
486 /* allocate FIFO bank */
487 AVR32_WRITE_4(sc, AVR32_EPTCLRSTA(td->ep_no), AVR32_EPTSTA_TX_BK_RDY);
488
489 /* check remainder */
490 if (td->remainder == 0) {
491 if (td->short_pkt) {
492 return (0); /* complete */
493 }
494 /* else we need to transmit a short packet */
495 }
496 if (--to) {
497 goto repeat;
498 }
499not_complete:
500 return (1); /* not complete */
501}
502
503static uint8_t
504avr32dci_data_tx_sync(struct avr32dci_td *td)
505{
506 struct avr32dci_softc *sc;
507 uint32_t temp;
508
509 /* get pointer to softc */
510 sc = AVR32_PC2SC(td->pc);
511
512 /* check endpoint status */
513 temp = AVR32_READ_4(sc, AVR32_EPTSTA(td->ep_no));
514
515 DPRINTFN(5, "EPTSTA(%u)=0x%08x\n", td->ep_no, temp);
516
517 if (temp & AVR32_EPTSTA_RX_SETUP) {
518 DPRINTFN(5, "faking complete\n");
519 /* Race condition */
520 return (0); /* complete */
521 }
522 /*
523 * The control endpoint has only got one bank, so if that bank
524 * is free the packet has been transferred!
525 */
526 if (AVR32_EPTSTA_BUSY_BANK_STA(temp) != 0) {
527 /* cannot write any data - a bank is busy */
528 goto not_complete;
529 }
530 if (sc->sc_dv_addr != 0xFF) {
531 /* set new address */
532 avr32dci_set_address(sc, sc->sc_dv_addr);
533 }
534 return (0); /* complete */
535
536not_complete:
537 return (1); /* not complete */
538}
539
540static uint8_t
541avr32dci_xfer_do_fifo(struct usb_xfer *xfer)
542{
543 struct avr32dci_td *td;
544
545 DPRINTFN(9, "\n");
546
547 td = xfer->td_transfer_cache;
548 while (1) {
549 if ((td->func) (td)) {
550 /* operation in progress */
551 break;
552 }
553 if (((void *)td) == xfer->td_transfer_last) {
554 goto done;
555 }
556 if (td->error) {
557 goto done;
558 } else if (td->remainder > 0) {
559 /*
560 * We had a short transfer. If there is no alternate
561 * next, stop processing !
562 */
563 if (!td->alt_next) {
564 goto done;
565 }
566 }
567 /*
568 * Fetch the next transfer descriptor and transfer
569 * some flags to the next transfer descriptor
570 */
571 td = td->obj_next;
572 xfer->td_transfer_cache = td;
573 }
574 return (1); /* not complete */
575
576done:
577 /* compute all actual lengths */
578
579 avr32dci_standard_done(xfer);
580 return (0); /* complete */
581}
582
583static void
584avr32dci_interrupt_poll(struct avr32dci_softc *sc)
585{
586 struct usb_xfer *xfer;
587
588repeat:
589 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
590 if (!avr32dci_xfer_do_fifo(xfer)) {
591 /* queue has been modified */
592 goto repeat;
593 }
594 }
595}
596
597void
598avr32dci_vbus_interrupt(struct avr32dci_softc *sc, uint8_t is_on)
599{
600 DPRINTFN(5, "vbus = %u\n", is_on);
601
602 if (is_on) {
603 if (!sc->sc_flags.status_vbus) {
604 sc->sc_flags.status_vbus = 1;
605
606 /* complete root HUB interrupt endpoint */
607
608 avr32dci_root_intr(sc);
609 }
610 } else {
611 if (sc->sc_flags.status_vbus) {
612 sc->sc_flags.status_vbus = 0;
613 sc->sc_flags.status_bus_reset = 0;
614 sc->sc_flags.status_suspend = 0;
615 sc->sc_flags.change_suspend = 0;
616 sc->sc_flags.change_connect = 1;
617
618 /* complete root HUB interrupt endpoint */
619
620 avr32dci_root_intr(sc);
621 }
622 }
623}
624
625void
626avr32dci_interrupt(struct avr32dci_softc *sc)
627{
628 uint32_t status;
629
630 USB_BUS_LOCK(&sc->sc_bus);
631
632 /* read interrupt status */
633 status = AVR32_READ_4(sc, AVR32_INTSTA);
634
635 /* clear all set interrupts */
636 AVR32_WRITE_4(sc, AVR32_CLRINT, status);
637
638 DPRINTFN(14, "INTSTA=0x%08x\n", status);
639
640 /* check for any bus state change interrupts */
641 if (status & AVR32_INT_ENDRESET) {
642
643 DPRINTFN(5, "end of reset\n");
644
645 /* set correct state */
646 sc->sc_flags.status_bus_reset = 1;
647 sc->sc_flags.status_suspend = 0;
648 sc->sc_flags.change_suspend = 0;
649 sc->sc_flags.change_connect = 1;
650
651 /* disable resume interrupt */
652 avr32dci_mod_ien(sc, AVR32_INT_DET_SUSPD |
653 AVR32_INT_ENDRESET, AVR32_INT_WAKE_UP);
654
655 /* complete root HUB interrupt endpoint */
656 avr32dci_root_intr(sc);
657 }
658 /*
659 * If resume and suspend is set at the same time we interpret
660 * that like RESUME. Resume is set when there is at least 3
661 * milliseconds of inactivity on the USB BUS.
662 */
663 if (status & AVR32_INT_WAKE_UP) {
664
665 DPRINTFN(5, "resume interrupt\n");
666
667 if (sc->sc_flags.status_suspend) {
668 /* update status bits */
669 sc->sc_flags.status_suspend = 0;
670 sc->sc_flags.change_suspend = 1;
671
672 /* disable resume interrupt */
673 avr32dci_mod_ien(sc, AVR32_INT_DET_SUSPD |
674 AVR32_INT_ENDRESET, AVR32_INT_WAKE_UP);
675
676 /* complete root HUB interrupt endpoint */
677 avr32dci_root_intr(sc);
678 }
679 } else if (status & AVR32_INT_DET_SUSPD) {
680
681 DPRINTFN(5, "suspend interrupt\n");
682
683 if (!sc->sc_flags.status_suspend) {
684 /* update status bits */
685 sc->sc_flags.status_suspend = 1;
686 sc->sc_flags.change_suspend = 1;
687
688 /* disable suspend interrupt */
689 avr32dci_mod_ien(sc, AVR32_INT_WAKE_UP |
690 AVR32_INT_ENDRESET, AVR32_INT_DET_SUSPD);
691
692 /* complete root HUB interrupt endpoint */
693 avr32dci_root_intr(sc);
694 }
695 }
696 /* check for any endpoint interrupts */
697 if (status & -AVR32_INT_EPT_INT(0)) {
698
699 DPRINTFN(5, "real endpoint interrupt\n");
700
701 avr32dci_interrupt_poll(sc);
702 }
703 USB_BUS_UNLOCK(&sc->sc_bus);
704}
705
706static void
707avr32dci_setup_standard_chain_sub(struct avr32dci_std_temp *temp)
708{
709 struct avr32dci_td *td;
710
711 /* get current Transfer Descriptor */
712 td = temp->td_next;
713 temp->td = td;
714
715 /* prepare for next TD */
716 temp->td_next = td->obj_next;
717
718 /* fill out the Transfer Descriptor */
719 td->func = temp->func;
720 td->pc = temp->pc;
721 td->offset = temp->offset;
722 td->remainder = temp->len;
723 td->error = 0;
724 td->did_stall = temp->did_stall;
725 td->short_pkt = temp->short_pkt;
726 td->alt_next = temp->setup_alt_next;
727}
728
729static void
730avr32dci_setup_standard_chain(struct usb_xfer *xfer)
731{
732 struct avr32dci_std_temp temp;
733 struct avr32dci_softc *sc;
734 struct avr32dci_td *td;
735 uint32_t x;
736 uint8_t ep_no;
737 uint8_t need_sync;
738
739 DPRINTFN(9, "addr=%d endpt=%d sumlen=%d speed=%d\n",
740 xfer->address, UE_GET_ADDR(xfer->endpoint),
| 470
471 /* get correct length */
472 if (buf_res.length > count) {
473 buf_res.length = count;
474 }
475 /* transmit data */
476 bcopy(buf_res.buffer, sc->physdata +
477 (AVR32_EPTSTA_CURRENT_BANK(temp) << td->bank_shift) +
478 (td->ep_no << 16) + (td->offset % td->max_packet_size),
479 buf_res.length)
480 /* update counters */
481 count -= buf_res.length;
482 td->offset += buf_res.length;
483 td->remainder -= buf_res.length;
484 }
485
486 /* allocate FIFO bank */
487 AVR32_WRITE_4(sc, AVR32_EPTCLRSTA(td->ep_no), AVR32_EPTSTA_TX_BK_RDY);
488
489 /* check remainder */
490 if (td->remainder == 0) {
491 if (td->short_pkt) {
492 return (0); /* complete */
493 }
494 /* else we need to transmit a short packet */
495 }
496 if (--to) {
497 goto repeat;
498 }
499not_complete:
500 return (1); /* not complete */
501}
502
503static uint8_t
504avr32dci_data_tx_sync(struct avr32dci_td *td)
505{
506 struct avr32dci_softc *sc;
507 uint32_t temp;
508
509 /* get pointer to softc */
510 sc = AVR32_PC2SC(td->pc);
511
512 /* check endpoint status */
513 temp = AVR32_READ_4(sc, AVR32_EPTSTA(td->ep_no));
514
515 DPRINTFN(5, "EPTSTA(%u)=0x%08x\n", td->ep_no, temp);
516
517 if (temp & AVR32_EPTSTA_RX_SETUP) {
518 DPRINTFN(5, "faking complete\n");
519 /* Race condition */
520 return (0); /* complete */
521 }
522 /*
523 * The control endpoint has only got one bank, so if that bank
524 * is free the packet has been transferred!
525 */
526 if (AVR32_EPTSTA_BUSY_BANK_STA(temp) != 0) {
527 /* cannot write any data - a bank is busy */
528 goto not_complete;
529 }
530 if (sc->sc_dv_addr != 0xFF) {
531 /* set new address */
532 avr32dci_set_address(sc, sc->sc_dv_addr);
533 }
534 return (0); /* complete */
535
536not_complete:
537 return (1); /* not complete */
538}
539
540static uint8_t
541avr32dci_xfer_do_fifo(struct usb_xfer *xfer)
542{
543 struct avr32dci_td *td;
544
545 DPRINTFN(9, "\n");
546
547 td = xfer->td_transfer_cache;
548 while (1) {
549 if ((td->func) (td)) {
550 /* operation in progress */
551 break;
552 }
553 if (((void *)td) == xfer->td_transfer_last) {
554 goto done;
555 }
556 if (td->error) {
557 goto done;
558 } else if (td->remainder > 0) {
559 /*
560 * We had a short transfer. If there is no alternate
561 * next, stop processing !
562 */
563 if (!td->alt_next) {
564 goto done;
565 }
566 }
567 /*
568 * Fetch the next transfer descriptor and transfer
569 * some flags to the next transfer descriptor
570 */
571 td = td->obj_next;
572 xfer->td_transfer_cache = td;
573 }
574 return (1); /* not complete */
575
576done:
577 /* compute all actual lengths */
578
579 avr32dci_standard_done(xfer);
580 return (0); /* complete */
581}
582
583static void
584avr32dci_interrupt_poll(struct avr32dci_softc *sc)
585{
586 struct usb_xfer *xfer;
587
588repeat:
589 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
590 if (!avr32dci_xfer_do_fifo(xfer)) {
591 /* queue has been modified */
592 goto repeat;
593 }
594 }
595}
596
597void
598avr32dci_vbus_interrupt(struct avr32dci_softc *sc, uint8_t is_on)
599{
600 DPRINTFN(5, "vbus = %u\n", is_on);
601
602 if (is_on) {
603 if (!sc->sc_flags.status_vbus) {
604 sc->sc_flags.status_vbus = 1;
605
606 /* complete root HUB interrupt endpoint */
607
608 avr32dci_root_intr(sc);
609 }
610 } else {
611 if (sc->sc_flags.status_vbus) {
612 sc->sc_flags.status_vbus = 0;
613 sc->sc_flags.status_bus_reset = 0;
614 sc->sc_flags.status_suspend = 0;
615 sc->sc_flags.change_suspend = 0;
616 sc->sc_flags.change_connect = 1;
617
618 /* complete root HUB interrupt endpoint */
619
620 avr32dci_root_intr(sc);
621 }
622 }
623}
624
625void
626avr32dci_interrupt(struct avr32dci_softc *sc)
627{
628 uint32_t status;
629
630 USB_BUS_LOCK(&sc->sc_bus);
631
632 /* read interrupt status */
633 status = AVR32_READ_4(sc, AVR32_INTSTA);
634
635 /* clear all set interrupts */
636 AVR32_WRITE_4(sc, AVR32_CLRINT, status);
637
638 DPRINTFN(14, "INTSTA=0x%08x\n", status);
639
640 /* check for any bus state change interrupts */
641 if (status & AVR32_INT_ENDRESET) {
642
643 DPRINTFN(5, "end of reset\n");
644
645 /* set correct state */
646 sc->sc_flags.status_bus_reset = 1;
647 sc->sc_flags.status_suspend = 0;
648 sc->sc_flags.change_suspend = 0;
649 sc->sc_flags.change_connect = 1;
650
651 /* disable resume interrupt */
652 avr32dci_mod_ien(sc, AVR32_INT_DET_SUSPD |
653 AVR32_INT_ENDRESET, AVR32_INT_WAKE_UP);
654
655 /* complete root HUB interrupt endpoint */
656 avr32dci_root_intr(sc);
657 }
658 /*
659 * If resume and suspend is set at the same time we interpret
660 * that like RESUME. Resume is set when there is at least 3
661 * milliseconds of inactivity on the USB BUS.
662 */
663 if (status & AVR32_INT_WAKE_UP) {
664
665 DPRINTFN(5, "resume interrupt\n");
666
667 if (sc->sc_flags.status_suspend) {
668 /* update status bits */
669 sc->sc_flags.status_suspend = 0;
670 sc->sc_flags.change_suspend = 1;
671
672 /* disable resume interrupt */
673 avr32dci_mod_ien(sc, AVR32_INT_DET_SUSPD |
674 AVR32_INT_ENDRESET, AVR32_INT_WAKE_UP);
675
676 /* complete root HUB interrupt endpoint */
677 avr32dci_root_intr(sc);
678 }
679 } else if (status & AVR32_INT_DET_SUSPD) {
680
681 DPRINTFN(5, "suspend interrupt\n");
682
683 if (!sc->sc_flags.status_suspend) {
684 /* update status bits */
685 sc->sc_flags.status_suspend = 1;
686 sc->sc_flags.change_suspend = 1;
687
688 /* disable suspend interrupt */
689 avr32dci_mod_ien(sc, AVR32_INT_WAKE_UP |
690 AVR32_INT_ENDRESET, AVR32_INT_DET_SUSPD);
691
692 /* complete root HUB interrupt endpoint */
693 avr32dci_root_intr(sc);
694 }
695 }
696 /* check for any endpoint interrupts */
697 if (status & -AVR32_INT_EPT_INT(0)) {
698
699 DPRINTFN(5, "real endpoint interrupt\n");
700
701 avr32dci_interrupt_poll(sc);
702 }
703 USB_BUS_UNLOCK(&sc->sc_bus);
704}
705
706static void
707avr32dci_setup_standard_chain_sub(struct avr32dci_std_temp *temp)
708{
709 struct avr32dci_td *td;
710
711 /* get current Transfer Descriptor */
712 td = temp->td_next;
713 temp->td = td;
714
715 /* prepare for next TD */
716 temp->td_next = td->obj_next;
717
718 /* fill out the Transfer Descriptor */
719 td->func = temp->func;
720 td->pc = temp->pc;
721 td->offset = temp->offset;
722 td->remainder = temp->len;
723 td->error = 0;
724 td->did_stall = temp->did_stall;
725 td->short_pkt = temp->short_pkt;
726 td->alt_next = temp->setup_alt_next;
727}
728
729static void
730avr32dci_setup_standard_chain(struct usb_xfer *xfer)
731{
732 struct avr32dci_std_temp temp;
733 struct avr32dci_softc *sc;
734 struct avr32dci_td *td;
735 uint32_t x;
736 uint8_t ep_no;
737 uint8_t need_sync;
738
739 DPRINTFN(9, "addr=%d endpt=%d sumlen=%d speed=%d\n",
740 xfer->address, UE_GET_ADDR(xfer->endpoint),
|
741 xfer->sumlen, usb2_get_speed(xfer->xroot->udev));
| 741 xfer->sumlen, usbd_get_speed(xfer->xroot->udev));
|
742
743 temp.max_frame_size = xfer->max_frame_size;
744
745 td = xfer->td_start[0];
746 xfer->td_transfer_first = td;
747 xfer->td_transfer_cache = td;
748
749 /* setup temp */
750
751 temp.td = NULL;
752 temp.td_next = xfer->td_start[0];
753 temp.offset = 0;
754 temp.setup_alt_next = xfer->flags_int.short_frames_ok;
755 temp.did_stall = !xfer->flags_int.control_stall;
756
757 sc = AVR32_BUS2SC(xfer->xroot->bus);
758 ep_no = (xfer->endpoint & UE_ADDR);
759
760 /* check if we should prepend a setup message */
761
762 if (xfer->flags_int.control_xfr) {
763 if (xfer->flags_int.control_hdr) {
764
765 temp.func = &avr32dci_setup_rx;
766 temp.len = xfer->frlengths[0];
767 temp.pc = xfer->frbuffers + 0;
768 temp.short_pkt = temp.len ? 1 : 0;
769 /* check for last frame */
770 if (xfer->nframes == 1) {
771 /* no STATUS stage yet, SETUP is last */
772 if (xfer->flags_int.control_act)
773 temp.setup_alt_next = 0;
774 }
775 avr32dci_setup_standard_chain_sub(&temp);
776 }
777 x = 1;
778 } else {
779 x = 0;
780 }
781
782 if (x != xfer->nframes) {
783 if (xfer->endpoint & UE_DIR_IN) {
784 temp.func = &avr32dci_data_tx;
785 need_sync = 1;
786 } else {
787 temp.func = &avr32dci_data_rx;
788 need_sync = 0;
789 }
790
791 /* setup "pc" pointer */
792 temp.pc = xfer->frbuffers + x;
793 } else {
794 need_sync = 0;
795 }
796 while (x != xfer->nframes) {
797
798 /* DATA0 / DATA1 message */
799
800 temp.len = xfer->frlengths[x];
801
802 x++;
803
804 if (x == xfer->nframes) {
805 if (xfer->flags_int.control_xfr) {
806 if (xfer->flags_int.control_act) {
807 temp.setup_alt_next = 0;
808 }
809 } else {
810 temp.setup_alt_next = 0;
811 }
812 }
813 if (temp.len == 0) {
814
815 /* make sure that we send an USB packet */
816
817 temp.short_pkt = 0;
818
819 } else {
820
821 /* regular data transfer */
822
823 temp.short_pkt = (xfer->flags.force_short_xfer) ? 0 : 1;
824 }
825
826 avr32dci_setup_standard_chain_sub(&temp);
827
828 if (xfer->flags_int.isochronous_xfr) {
829 temp.offset += temp.len;
830 } else {
831 /* get next Page Cache pointer */
832 temp.pc = xfer->frbuffers + x;
833 }
834 }
835
836 if (xfer->flags_int.control_xfr) {
837
838 /* always setup a valid "pc" pointer for status and sync */
839 temp.pc = xfer->frbuffers + 0;
840 temp.len = 0;
841 temp.short_pkt = 0;
842 temp.setup_alt_next = 0;
843
844 /* check if we need to sync */
845 if (need_sync) {
846 /* we need a SYNC point after TX */
847 temp.func = &avr32dci_data_tx_sync;
848 avr32dci_setup_standard_chain_sub(&temp);
849 }
850 /* check if we should append a status stage */
851 if (!xfer->flags_int.control_act) {
852
853 /*
854 * Send a DATA1 message and invert the current
855 * endpoint direction.
856 */
857 if (xfer->endpoint & UE_DIR_IN) {
858 temp.func = &avr32dci_data_rx;
859 need_sync = 0;
860 } else {
861 temp.func = &avr32dci_data_tx;
862 need_sync = 1;
863 }
864
865 avr32dci_setup_standard_chain_sub(&temp);
866 if (need_sync) {
867 /* we need a SYNC point after TX */
868 temp.func = &avr32dci_data_tx_sync;
869 avr32dci_setup_standard_chain_sub(&temp);
870 }
871 }
872 }
873 /* must have at least one frame! */
874 td = temp.td;
875 xfer->td_transfer_last = td;
876}
877
878static void
879avr32dci_timeout(void *arg)
880{
881 struct usb_xfer *xfer = arg;
882
883 DPRINTF("xfer=%p\n", xfer);
884
885 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED);
886
887 /* transfer is transferred */
888 avr32dci_device_done(xfer, USB_ERR_TIMEOUT);
889}
890
891static void
892avr32dci_start_standard_chain(struct usb_xfer *xfer)
893{
894 DPRINTFN(9, "\n");
895
896 /* poll one time - will turn on interrupts */
897 if (avr32dci_xfer_do_fifo(xfer)) {
898 uint8_t ep_no = xfer->endpoint & UE_ADDR_MASK;
899
900 avr32dci_mod_ien(sc, AVR32_INT_EPT_INT(ep_no), 0);
901
902 /* put transfer on interrupt queue */
| 742
743 temp.max_frame_size = xfer->max_frame_size;
744
745 td = xfer->td_start[0];
746 xfer->td_transfer_first = td;
747 xfer->td_transfer_cache = td;
748
749 /* setup temp */
750
751 temp.td = NULL;
752 temp.td_next = xfer->td_start[0];
753 temp.offset = 0;
754 temp.setup_alt_next = xfer->flags_int.short_frames_ok;
755 temp.did_stall = !xfer->flags_int.control_stall;
756
757 sc = AVR32_BUS2SC(xfer->xroot->bus);
758 ep_no = (xfer->endpoint & UE_ADDR);
759
760 /* check if we should prepend a setup message */
761
762 if (xfer->flags_int.control_xfr) {
763 if (xfer->flags_int.control_hdr) {
764
765 temp.func = &avr32dci_setup_rx;
766 temp.len = xfer->frlengths[0];
767 temp.pc = xfer->frbuffers + 0;
768 temp.short_pkt = temp.len ? 1 : 0;
769 /* check for last frame */
770 if (xfer->nframes == 1) {
771 /* no STATUS stage yet, SETUP is last */
772 if (xfer->flags_int.control_act)
773 temp.setup_alt_next = 0;
774 }
775 avr32dci_setup_standard_chain_sub(&temp);
776 }
777 x = 1;
778 } else {
779 x = 0;
780 }
781
782 if (x != xfer->nframes) {
783 if (xfer->endpoint & UE_DIR_IN) {
784 temp.func = &avr32dci_data_tx;
785 need_sync = 1;
786 } else {
787 temp.func = &avr32dci_data_rx;
788 need_sync = 0;
789 }
790
791 /* setup "pc" pointer */
792 temp.pc = xfer->frbuffers + x;
793 } else {
794 need_sync = 0;
795 }
796 while (x != xfer->nframes) {
797
798 /* DATA0 / DATA1 message */
799
800 temp.len = xfer->frlengths[x];
801
802 x++;
803
804 if (x == xfer->nframes) {
805 if (xfer->flags_int.control_xfr) {
806 if (xfer->flags_int.control_act) {
807 temp.setup_alt_next = 0;
808 }
809 } else {
810 temp.setup_alt_next = 0;
811 }
812 }
813 if (temp.len == 0) {
814
815 /* make sure that we send an USB packet */
816
817 temp.short_pkt = 0;
818
819 } else {
820
821 /* regular data transfer */
822
823 temp.short_pkt = (xfer->flags.force_short_xfer) ? 0 : 1;
824 }
825
826 avr32dci_setup_standard_chain_sub(&temp);
827
828 if (xfer->flags_int.isochronous_xfr) {
829 temp.offset += temp.len;
830 } else {
831 /* get next Page Cache pointer */
832 temp.pc = xfer->frbuffers + x;
833 }
834 }
835
836 if (xfer->flags_int.control_xfr) {
837
838 /* always setup a valid "pc" pointer for status and sync */
839 temp.pc = xfer->frbuffers + 0;
840 temp.len = 0;
841 temp.short_pkt = 0;
842 temp.setup_alt_next = 0;
843
844 /* check if we need to sync */
845 if (need_sync) {
846 /* we need a SYNC point after TX */
847 temp.func = &avr32dci_data_tx_sync;
848 avr32dci_setup_standard_chain_sub(&temp);
849 }
850 /* check if we should append a status stage */
851 if (!xfer->flags_int.control_act) {
852
853 /*
854 * Send a DATA1 message and invert the current
855 * endpoint direction.
856 */
857 if (xfer->endpoint & UE_DIR_IN) {
858 temp.func = &avr32dci_data_rx;
859 need_sync = 0;
860 } else {
861 temp.func = &avr32dci_data_tx;
862 need_sync = 1;
863 }
864
865 avr32dci_setup_standard_chain_sub(&temp);
866 if (need_sync) {
867 /* we need a SYNC point after TX */
868 temp.func = &avr32dci_data_tx_sync;
869 avr32dci_setup_standard_chain_sub(&temp);
870 }
871 }
872 }
873 /* must have at least one frame! */
874 td = temp.td;
875 xfer->td_transfer_last = td;
876}
877
878static void
879avr32dci_timeout(void *arg)
880{
881 struct usb_xfer *xfer = arg;
882
883 DPRINTF("xfer=%p\n", xfer);
884
885 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED);
886
887 /* transfer is transferred */
888 avr32dci_device_done(xfer, USB_ERR_TIMEOUT);
889}
890
891static void
892avr32dci_start_standard_chain(struct usb_xfer *xfer)
893{
894 DPRINTFN(9, "\n");
895
896 /* poll one time - will turn on interrupts */
897 if (avr32dci_xfer_do_fifo(xfer)) {
898 uint8_t ep_no = xfer->endpoint & UE_ADDR_MASK;
899
900 avr32dci_mod_ien(sc, AVR32_INT_EPT_INT(ep_no), 0);
901
902 /* put transfer on interrupt queue */
|
903 usb2_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer);
| 903 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer);
|
904
905 /* start timeout, if any */
906 if (xfer->timeout != 0) {
| 904
905 /* start timeout, if any */
906 if (xfer->timeout != 0) {
|
907 usb2_transfer_timeout_ms(xfer,
| 907 usbd_transfer_timeout_ms(xfer,
|
908 &avr32dci_timeout, xfer->timeout);
909 }
910 }
911}
912
913static void
914avr32dci_root_intr(struct avr32dci_softc *sc)
915{
916 DPRINTFN(9, "\n");
917
918 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
919
920 /* set port bit */
921 sc->sc_hub_idata[0] = 0x02; /* we only have one port */
922
923 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata,
924 sizeof(sc->sc_hub_idata));
925}
926
927static usb_error_t
928avr32dci_standard_done_sub(struct usb_xfer *xfer)
929{
930 struct avr32dci_td *td;
931 uint32_t len;
932 uint8_t error;
933
934 DPRINTFN(9, "\n");
935
936 td = xfer->td_transfer_cache;
937
938 do {
939 len = td->remainder;
940
941 if (xfer->aframes != xfer->nframes) {
942 /*
943 * Verify the length and subtract
944 * the remainder from "frlengths[]":
945 */
946 if (len > xfer->frlengths[xfer->aframes]) {
947 td->error = 1;
948 } else {
949 xfer->frlengths[xfer->aframes] -= len;
950 }
951 }
952 /* Check for transfer error */
953 if (td->error) {
954 /* the transfer is finished */
955 error = 1;
956 td = NULL;
957 break;
958 }
959 /* Check for short transfer */
960 if (len > 0) {
961 if (xfer->flags_int.short_frames_ok) {
962 /* follow alt next */
963 if (td->alt_next) {
964 td = td->obj_next;
965 } else {
966 td = NULL;
967 }
968 } else {
969 /* the transfer is finished */
970 td = NULL;
971 }
972 error = 0;
973 break;
974 }
975 td = td->obj_next;
976
977 /* this USB frame is complete */
978 error = 0;
979 break;
980
981 } while (0);
982
983 /* update transfer cache */
984
985 xfer->td_transfer_cache = td;
986
987 return (error ?
988 USB_ERR_STALLED : USB_ERR_NORMAL_COMPLETION);
989}
990
991static void
992avr32dci_standard_done(struct usb_xfer *xfer)
993{
994 usb_error_t err = 0;
995
996 DPRINTFN(13, "xfer=%p pipe=%p transfer done\n",
997 xfer, xfer->pipe);
998
999 /* reset scanner */
1000
1001 xfer->td_transfer_cache = xfer->td_transfer_first;
1002
1003 if (xfer->flags_int.control_xfr) {
1004
1005 if (xfer->flags_int.control_hdr) {
1006
1007 err = avr32dci_standard_done_sub(xfer);
1008 }
1009 xfer->aframes = 1;
1010
1011 if (xfer->td_transfer_cache == NULL) {
1012 goto done;
1013 }
1014 }
1015 while (xfer->aframes != xfer->nframes) {
1016
1017 err = avr32dci_standard_done_sub(xfer);
1018 xfer->aframes++;
1019
1020 if (xfer->td_transfer_cache == NULL) {
1021 goto done;
1022 }
1023 }
1024
1025 if (xfer->flags_int.control_xfr &&
1026 !xfer->flags_int.control_act) {
1027
1028 err = avr32dci_standard_done_sub(xfer);
1029 }
1030done:
1031 avr32dci_device_done(xfer, err);
1032}
1033
1034/*------------------------------------------------------------------------*
1035 * avr32dci_device_done
1036 *
1037 * NOTE: this function can be called more than one time on the
1038 * same USB transfer!
1039 *------------------------------------------------------------------------*/
1040static void
1041avr32dci_device_done(struct usb_xfer *xfer, usb_error_t error)
1042{
1043 struct avr32dci_softc *sc = AVR32_BUS2SC(xfer->xroot->bus);
1044 uint8_t ep_no;
1045
1046 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
1047
1048 DPRINTFN(9, "xfer=%p, pipe=%p, error=%d\n",
1049 xfer, xfer->pipe, error);
1050
1051 if (xfer->flags_int.usb_mode == USB_MODE_DEVICE) {
1052 ep_no = (xfer->endpoint & UE_ADDR);
1053
1054 /* disable endpoint interrupt */
1055 avr32dci_mod_ien(sc, 0, AVR32_INT_EPT_INT(ep_no));
1056
1057 DPRINTFN(15, "disabled interrupts!\n");
1058 }
1059 /* dequeue transfer and start next transfer */
| 908 &avr32dci_timeout, xfer->timeout);
909 }
910 }
911}
912
913static void
914avr32dci_root_intr(struct avr32dci_softc *sc)
915{
916 DPRINTFN(9, "\n");
917
918 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
919
920 /* set port bit */
921 sc->sc_hub_idata[0] = 0x02; /* we only have one port */
922
923 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata,
924 sizeof(sc->sc_hub_idata));
925}
926
927static usb_error_t
928avr32dci_standard_done_sub(struct usb_xfer *xfer)
929{
930 struct avr32dci_td *td;
931 uint32_t len;
932 uint8_t error;
933
934 DPRINTFN(9, "\n");
935
936 td = xfer->td_transfer_cache;
937
938 do {
939 len = td->remainder;
940
941 if (xfer->aframes != xfer->nframes) {
942 /*
943 * Verify the length and subtract
944 * the remainder from "frlengths[]":
945 */
946 if (len > xfer->frlengths[xfer->aframes]) {
947 td->error = 1;
948 } else {
949 xfer->frlengths[xfer->aframes] -= len;
950 }
951 }
952 /* Check for transfer error */
953 if (td->error) {
954 /* the transfer is finished */
955 error = 1;
956 td = NULL;
957 break;
958 }
959 /* Check for short transfer */
960 if (len > 0) {
961 if (xfer->flags_int.short_frames_ok) {
962 /* follow alt next */
963 if (td->alt_next) {
964 td = td->obj_next;
965 } else {
966 td = NULL;
967 }
968 } else {
969 /* the transfer is finished */
970 td = NULL;
971 }
972 error = 0;
973 break;
974 }
975 td = td->obj_next;
976
977 /* this USB frame is complete */
978 error = 0;
979 break;
980
981 } while (0);
982
983 /* update transfer cache */
984
985 xfer->td_transfer_cache = td;
986
987 return (error ?
988 USB_ERR_STALLED : USB_ERR_NORMAL_COMPLETION);
989}
990
991static void
992avr32dci_standard_done(struct usb_xfer *xfer)
993{
994 usb_error_t err = 0;
995
996 DPRINTFN(13, "xfer=%p pipe=%p transfer done\n",
997 xfer, xfer->pipe);
998
999 /* reset scanner */
1000
1001 xfer->td_transfer_cache = xfer->td_transfer_first;
1002
1003 if (xfer->flags_int.control_xfr) {
1004
1005 if (xfer->flags_int.control_hdr) {
1006
1007 err = avr32dci_standard_done_sub(xfer);
1008 }
1009 xfer->aframes = 1;
1010
1011 if (xfer->td_transfer_cache == NULL) {
1012 goto done;
1013 }
1014 }
1015 while (xfer->aframes != xfer->nframes) {
1016
1017 err = avr32dci_standard_done_sub(xfer);
1018 xfer->aframes++;
1019
1020 if (xfer->td_transfer_cache == NULL) {
1021 goto done;
1022 }
1023 }
1024
1025 if (xfer->flags_int.control_xfr &&
1026 !xfer->flags_int.control_act) {
1027
1028 err = avr32dci_standard_done_sub(xfer);
1029 }
1030done:
1031 avr32dci_device_done(xfer, err);
1032}
1033
1034/*------------------------------------------------------------------------*
1035 * avr32dci_device_done
1036 *
1037 * NOTE: this function can be called more than one time on the
1038 * same USB transfer!
1039 *------------------------------------------------------------------------*/
1040static void
1041avr32dci_device_done(struct usb_xfer *xfer, usb_error_t error)
1042{
1043 struct avr32dci_softc *sc = AVR32_BUS2SC(xfer->xroot->bus);
1044 uint8_t ep_no;
1045
1046 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
1047
1048 DPRINTFN(9, "xfer=%p, pipe=%p, error=%d\n",
1049 xfer, xfer->pipe, error);
1050
1051 if (xfer->flags_int.usb_mode == USB_MODE_DEVICE) {
1052 ep_no = (xfer->endpoint & UE_ADDR);
1053
1054 /* disable endpoint interrupt */
1055 avr32dci_mod_ien(sc, 0, AVR32_INT_EPT_INT(ep_no));
1056
1057 DPRINTFN(15, "disabled interrupts!\n");
1058 }
1059 /* dequeue transfer and start next transfer */
|
1060 usb2_transfer_done(xfer, error);
| 1060 usbd_transfer_done(xfer, error);
|
1061}
1062
1063static void
1064avr32dci_set_stall(struct usb_device *udev, struct usb_xfer *xfer,
1065 struct usb_endpoint *ep)
1066{
1067 struct avr32dci_softc *sc;
1068 uint8_t ep_no;
1069
1070 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED);
1071
1072 DPRINTFN(5, "pipe=%p\n", pipe);
1073
1074 if (xfer) {
1075 /* cancel any ongoing transfers */
1076 avr32dci_device_done(xfer, USB_ERR_STALLED);
1077 }
1078 sc = AVR32_BUS2SC(udev->bus);
1079 /* get endpoint number */
1080 ep_no = (pipe->edesc->bEndpointAddress & UE_ADDR);
1081 /* set stall */
1082 AVR32_WRITE_4(sc, AVR32_EPTSETSTA(ep_no), AVR32_EPTSTA_FRCESTALL);
1083}
1084
1085static void
1086avr32dci_clear_stall_sub(struct avr32dci_softc *sc, uint8_t ep_no,
1087 uint8_t ep_type, uint8_t ep_dir)
1088{
1089 const struct usb_hw_ep_profile *pf;
1090 uint32_t temp;
1091 uint32_t epsize;
1092 uint8_t n;
1093
1094 if (ep_type == UE_CONTROL) {
1095 /* clearing stall is not needed */
1096 return;
1097 }
1098 /* set endpoint reset */
1099 AVR32_WRITE_4(sc, AVR32_EPTRST, AVR32_EPTRST_MASK(ep_no));
1100
1101 /* set stall */
1102 AVR32_WRITE_4(sc, AVR32_EPTSETSTA(ep_no), AVR32_EPTSTA_FRCESTALL);
1103
1104 /* reset data toggle */
1105 AVR32_WRITE_4(sc, AVR32_EPTCLRSTA(ep_no), AVR32_EPTSTA_TOGGLESQ);
1106
1107 /* clear stall */
1108 AVR32_WRITE_4(sc, AVR32_EPTCLRSTA(ep_no), AVR32_EPTSTA_FRCESTALL);
1109
1110 if (ep_type == UE_BULK) {
1111 temp = AVR32_EPTCFG_TYPE_BULK;
1112 } else if (ep_type == UE_INTERRUPT) {
1113 temp = AVR32_EPTCFG_TYPE_INTR;
1114 } else {
1115 temp = AVR32_EPTCFG_TYPE_ISOC |
1116 AVR32_EPTCFG_NB_TRANS(1);
1117 }
1118 if (ep_dir & UE_DIR_IN) {
1119 temp |= AVR32_EPTCFG_EPDIR_IN;
1120 }
1121 avr32dci_get_hw_ep_profile(NULL, &pf, ep_no);
1122
1123 /* compute endpoint size (use maximum) */
1124 epsize = pf->max_in_frame_size | pf->max_out_frame_size;
1125 n = 0;
1126 while ((epsize /= 2))
1127 n++;
1128 temp |= AVR32_EPTCFG_EPSIZE(n);
1129
1130 /* use the maximum number of banks supported */
1131 if (ep_no < 1)
1132 temp |= AVR32_EPTCFG_NBANK(1);
1133 else if (ep_no < 3)
1134 temp |= AVR32_EPTCFG_NBANK(2);
1135 else
1136 temp |= AVR32_EPTCFG_NBANK(3);
1137
1138 AVR32_WRITE_4(sc, AVR32_EPTCFG(ep_no), temp);
1139
1140 temp = AVR32_READ_4(sc, AVR32_EPTCFG(ep_no));
1141
1142 if (!(temp & AVR32_EPTCFG_EPT_MAPD)) {
1143 DPRINTFN(0, "Chip rejected configuration\n");
1144 } else {
1145 AVR32_WRITE_4(sc, AVR32_EPTCTLENB(ep_no),
1146 AVR32_EPTCTL_EPT_ENABL);
1147 }
1148}
1149
1150static void
1151avr32dci_clear_stall(struct usb_device *udev, struct usb_endpoint *ep)
1152{
1153 struct avr32dci_softc *sc;
1154 struct usb_endpoint_descriptor *ed;
1155
1156 DPRINTFN(5, "pipe=%p\n", pipe);
1157
1158 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED);
1159
1160 /* check mode */
1161 if (udev->flags.usb_mode != USB_MODE_DEVICE) {
1162 /* not supported */
1163 return;
1164 }
1165 /* get softc */
1166 sc = AVR32_BUS2SC(udev->bus);
1167
1168 /* get endpoint descriptor */
1169 ed = pipe->edesc;
1170
1171 /* reset endpoint */
1172 avr32dci_clear_stall_sub(sc,
1173 (ed->bEndpointAddress & UE_ADDR),
1174 (ed->bmAttributes & UE_XFERTYPE),
1175 (ed->bEndpointAddress & (UE_DIR_IN | UE_DIR_OUT)));
1176}
1177
1178usb_error_t
1179avr32dci_init(struct avr32dci_softc *sc)
1180{
1181 uint8_t n;
1182
1183 DPRINTF("start\n");
1184
1185 /* set up the bus structure */
1186 sc->sc_bus.usbrev = USB_REV_1_1;
1187 sc->sc_bus.methods = &avr32dci_bus_methods;
1188
1189 USB_BUS_LOCK(&sc->sc_bus);
1190
1191 /* make sure USB is enabled */
1192 avr32dci_mod_ctrl(sc, AVR32_CTRL_DEV_EN_USBA, 0);
1193
1194 /* turn on clocks */
1195 (sc->sc_clocks_on) (&sc->sc_bus);
1196
1197 /* make sure device is re-enumerated */
1198 avr32dci_mod_ctrl(sc, AVR32_CTRL_DEV_DETACH, 0);
1199
1200 /* wait a little for things to stabilise */
| 1061}
1062
1063static void
1064avr32dci_set_stall(struct usb_device *udev, struct usb_xfer *xfer,
1065 struct usb_endpoint *ep)
1066{
1067 struct avr32dci_softc *sc;
1068 uint8_t ep_no;
1069
1070 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED);
1071
1072 DPRINTFN(5, "pipe=%p\n", pipe);
1073
1074 if (xfer) {
1075 /* cancel any ongoing transfers */
1076 avr32dci_device_done(xfer, USB_ERR_STALLED);
1077 }
1078 sc = AVR32_BUS2SC(udev->bus);
1079 /* get endpoint number */
1080 ep_no = (pipe->edesc->bEndpointAddress & UE_ADDR);
1081 /* set stall */
1082 AVR32_WRITE_4(sc, AVR32_EPTSETSTA(ep_no), AVR32_EPTSTA_FRCESTALL);
1083}
1084
1085static void
1086avr32dci_clear_stall_sub(struct avr32dci_softc *sc, uint8_t ep_no,
1087 uint8_t ep_type, uint8_t ep_dir)
1088{
1089 const struct usb_hw_ep_profile *pf;
1090 uint32_t temp;
1091 uint32_t epsize;
1092 uint8_t n;
1093
1094 if (ep_type == UE_CONTROL) {
1095 /* clearing stall is not needed */
1096 return;
1097 }
1098 /* set endpoint reset */
1099 AVR32_WRITE_4(sc, AVR32_EPTRST, AVR32_EPTRST_MASK(ep_no));
1100
1101 /* set stall */
1102 AVR32_WRITE_4(sc, AVR32_EPTSETSTA(ep_no), AVR32_EPTSTA_FRCESTALL);
1103
1104 /* reset data toggle */
1105 AVR32_WRITE_4(sc, AVR32_EPTCLRSTA(ep_no), AVR32_EPTSTA_TOGGLESQ);
1106
1107 /* clear stall */
1108 AVR32_WRITE_4(sc, AVR32_EPTCLRSTA(ep_no), AVR32_EPTSTA_FRCESTALL);
1109
1110 if (ep_type == UE_BULK) {
1111 temp = AVR32_EPTCFG_TYPE_BULK;
1112 } else if (ep_type == UE_INTERRUPT) {
1113 temp = AVR32_EPTCFG_TYPE_INTR;
1114 } else {
1115 temp = AVR32_EPTCFG_TYPE_ISOC |
1116 AVR32_EPTCFG_NB_TRANS(1);
1117 }
1118 if (ep_dir & UE_DIR_IN) {
1119 temp |= AVR32_EPTCFG_EPDIR_IN;
1120 }
1121 avr32dci_get_hw_ep_profile(NULL, &pf, ep_no);
1122
1123 /* compute endpoint size (use maximum) */
1124 epsize = pf->max_in_frame_size | pf->max_out_frame_size;
1125 n = 0;
1126 while ((epsize /= 2))
1127 n++;
1128 temp |= AVR32_EPTCFG_EPSIZE(n);
1129
1130 /* use the maximum number of banks supported */
1131 if (ep_no < 1)
1132 temp |= AVR32_EPTCFG_NBANK(1);
1133 else if (ep_no < 3)
1134 temp |= AVR32_EPTCFG_NBANK(2);
1135 else
1136 temp |= AVR32_EPTCFG_NBANK(3);
1137
1138 AVR32_WRITE_4(sc, AVR32_EPTCFG(ep_no), temp);
1139
1140 temp = AVR32_READ_4(sc, AVR32_EPTCFG(ep_no));
1141
1142 if (!(temp & AVR32_EPTCFG_EPT_MAPD)) {
1143 DPRINTFN(0, "Chip rejected configuration\n");
1144 } else {
1145 AVR32_WRITE_4(sc, AVR32_EPTCTLENB(ep_no),
1146 AVR32_EPTCTL_EPT_ENABL);
1147 }
1148}
1149
1150static void
1151avr32dci_clear_stall(struct usb_device *udev, struct usb_endpoint *ep)
1152{
1153 struct avr32dci_softc *sc;
1154 struct usb_endpoint_descriptor *ed;
1155
1156 DPRINTFN(5, "pipe=%p\n", pipe);
1157
1158 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED);
1159
1160 /* check mode */
1161 if (udev->flags.usb_mode != USB_MODE_DEVICE) {
1162 /* not supported */
1163 return;
1164 }
1165 /* get softc */
1166 sc = AVR32_BUS2SC(udev->bus);
1167
1168 /* get endpoint descriptor */
1169 ed = pipe->edesc;
1170
1171 /* reset endpoint */
1172 avr32dci_clear_stall_sub(sc,
1173 (ed->bEndpointAddress & UE_ADDR),
1174 (ed->bmAttributes & UE_XFERTYPE),
1175 (ed->bEndpointAddress & (UE_DIR_IN | UE_DIR_OUT)));
1176}
1177
1178usb_error_t
1179avr32dci_init(struct avr32dci_softc *sc)
1180{
1181 uint8_t n;
1182
1183 DPRINTF("start\n");
1184
1185 /* set up the bus structure */
1186 sc->sc_bus.usbrev = USB_REV_1_1;
1187 sc->sc_bus.methods = &avr32dci_bus_methods;
1188
1189 USB_BUS_LOCK(&sc->sc_bus);
1190
1191 /* make sure USB is enabled */
1192 avr32dci_mod_ctrl(sc, AVR32_CTRL_DEV_EN_USBA, 0);
1193
1194 /* turn on clocks */
1195 (sc->sc_clocks_on) (&sc->sc_bus);
1196
1197 /* make sure device is re-enumerated */
1198 avr32dci_mod_ctrl(sc, AVR32_CTRL_DEV_DETACH, 0);
1199
1200 /* wait a little for things to stabilise */
|
1201 usb2_pause_mtx(&sc->sc_bus.bus_mtx, hz / 20);
| 1201 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 20);
|
1202
1203 /* disable interrupts */
1204 avr32dci_mod_ien(sc, 0, 0xFFFFFFFF);
1205
1206 /* enable interrupts */
1207 avr32dci_mod_ien(sc, AVR32_INT_DET_SUSPD |
1208 AVR32_INT_ENDRESET, 0);
1209
1210 /* reset all endpoints */
1211/**INDENT** Warning@1207: Extra ) */
1212 AVR32_WRITE_4(sc, AVR32_EPTRST, (1 << AVR32_EP_MAX) - 1));
1213
1214 /* disable all endpoints */
1215 for (n = 0; n != AVR32_EP_MAX; n++) {
1216 /* disable endpoint */
1217 AVR32_WRITE_4(sc, AVR32_EPTCTLDIS(n), AVR32_EPTCTL_EPT_ENABL);
1218 }
1219
1220 /* turn off clocks */
1221
1222 avr32dci_clocks_off(sc);
1223
1224 USB_BUS_UNLOCK(&sc->sc_bus);
1225
1226 /* catch any lost interrupts */
1227
1228 avr32dci_do_poll(&sc->sc_bus);
1229
1230 return (0); /* success */
1231}
1232
1233void
1234avr32dci_uninit(struct avr32dci_softc *sc)
1235{
1236 uint8_t n;
1237
1238 USB_BUS_LOCK(&sc->sc_bus);
1239
1240 /* turn on clocks */
1241 (sc->sc_clocks_on) (&sc->sc_bus);
1242
1243 /* disable interrupts */
1244 avr32dci_mod_ien(sc, 0, 0xFFFFFFFF);
1245
1246 /* reset all endpoints */
1247/**INDENT** Warning@1242: Extra ) */
1248 AVR32_WRITE_4(sc, AVR32_EPTRST, (1 << AVR32_EP_MAX) - 1));
1249
1250 /* disable all endpoints */
1251 for (n = 0; n != AVR32_EP_MAX; n++) {
1252 /* disable endpoint */
1253 AVR32_WRITE_4(sc, AVR32_EPTCTLDIS(n), AVR32_EPTCTL_EPT_ENABL);
1254 }
1255
1256 sc->sc_flags.port_powered = 0;
1257 sc->sc_flags.status_vbus = 0;
1258 sc->sc_flags.status_bus_reset = 0;
1259 sc->sc_flags.status_suspend = 0;
1260 sc->sc_flags.change_suspend = 0;
1261 sc->sc_flags.change_connect = 1;
1262
1263 avr32dci_pull_down(sc);
1264 avr32dci_clocks_off(sc);
1265
1266 USB_BUS_UNLOCK(&sc->sc_bus);
1267}
1268
1269void
1270avr32dci_suspend(struct avr32dci_softc *sc)
1271{
1272 return;
1273}
1274
1275void
1276avr32dci_resume(struct avr32dci_softc *sc)
1277{
1278 return;
1279}
1280
1281static void
1282avr32dci_do_poll(struct usb_bus *bus)
1283{
1284 struct avr32dci_softc *sc = AVR32_BUS2SC(bus);
1285
1286 USB_BUS_LOCK(&sc->sc_bus);
1287 avr32dci_interrupt_poll(sc);
1288 USB_BUS_UNLOCK(&sc->sc_bus);
1289}
1290
1291/*------------------------------------------------------------------------*
1292 * at91dci bulk support
1293 * at91dci control support
1294 * at91dci interrupt support
1295 *------------------------------------------------------------------------*/
1296static void
1297avr32dci_device_non_isoc_open(struct usb_xfer *xfer)
1298{
1299 return;
1300}
1301
1302static void
1303avr32dci_device_non_isoc_close(struct usb_xfer *xfer)
1304{
1305 avr32dci_device_done(xfer, USB_ERR_CANCELLED);
1306}
1307
1308static void
1309avr32dci_device_non_isoc_enter(struct usb_xfer *xfer)
1310{
1311 return;
1312}
1313
1314static void
1315avr32dci_device_non_isoc_start(struct usb_xfer *xfer)
1316{
1317 /* setup TDs */
1318 avr32dci_setup_standard_chain(xfer);
1319 avr32dci_start_standard_chain(xfer);
1320}
1321
1322struct usb_pipe_methods avr32dci_device_non_isoc_methods =
1323{
1324 .open = avr32dci_device_non_isoc_open,
1325 .close = avr32dci_device_non_isoc_close,
1326 .enter = avr32dci_device_non_isoc_enter,
1327 .start = avr32dci_device_non_isoc_start,
1328};
1329
1330/*------------------------------------------------------------------------*
1331 * at91dci full speed isochronous support
1332 *------------------------------------------------------------------------*/
1333static void
1334avr32dci_device_isoc_fs_open(struct usb_xfer *xfer)
1335{
1336 return;
1337}
1338
1339static void
1340avr32dci_device_isoc_fs_close(struct usb_xfer *xfer)
1341{
1342 avr32dci_device_done(xfer, USB_ERR_CANCELLED);
1343}
1344
1345static void
1346avr32dci_device_isoc_fs_enter(struct usb_xfer *xfer)
1347{
1348 struct avr32dci_softc *sc = AVR32_BUS2SC(xfer->xroot->bus);
1349 uint32_t temp;
1350 uint32_t nframes;
1351 uint8_t ep_no;
1352
1353 DPRINTFN(6, "xfer=%p next=%d nframes=%d\n",
1354 xfer, xfer->pipe->isoc_next, xfer->nframes);
1355
1356 /* get the current frame index */
1357 ep_no = xfer->endpoint & UE_ADDR_MASK;
1358 nframes = (AVR32_READ_4(sc, AVR32_FNUM) / 8);
1359
1360 nframes &= AVR32_FRAME_MASK;
1361
1362 /*
1363 * check if the frame index is within the window where the frames
1364 * will be inserted
1365 */
1366 temp = (nframes - xfer->pipe->isoc_next) & AVR32_FRAME_MASK;
1367
1368 if ((xfer->pipe->is_synced == 0) ||
1369 (temp < xfer->nframes)) {
1370 /*
1371 * If there is data underflow or the pipe queue is
1372 * empty we schedule the transfer a few frames ahead
1373 * of the current frame position. Else two isochronous
1374 * transfers might overlap.
1375 */
1376 xfer->pipe->isoc_next = (nframes + 3) & AVR32_FRAME_MASK;
1377 xfer->pipe->is_synced = 1;
1378 DPRINTFN(3, "start next=%d\n", xfer->pipe->isoc_next);
1379 }
1380 /*
1381 * compute how many milliseconds the insertion is ahead of the
1382 * current frame position:
1383 */
1384 temp = (xfer->pipe->isoc_next - nframes) & AVR32_FRAME_MASK;
1385
1386 /*
1387 * pre-compute when the isochronous transfer will be finished:
1388 */
1389 xfer->isoc_time_complete =
| 1202
1203 /* disable interrupts */
1204 avr32dci_mod_ien(sc, 0, 0xFFFFFFFF);
1205
1206 /* enable interrupts */
1207 avr32dci_mod_ien(sc, AVR32_INT_DET_SUSPD |
1208 AVR32_INT_ENDRESET, 0);
1209
1210 /* reset all endpoints */
1211/**INDENT** Warning@1207: Extra ) */
1212 AVR32_WRITE_4(sc, AVR32_EPTRST, (1 << AVR32_EP_MAX) - 1));
1213
1214 /* disable all endpoints */
1215 for (n = 0; n != AVR32_EP_MAX; n++) {
1216 /* disable endpoint */
1217 AVR32_WRITE_4(sc, AVR32_EPTCTLDIS(n), AVR32_EPTCTL_EPT_ENABL);
1218 }
1219
1220 /* turn off clocks */
1221
1222 avr32dci_clocks_off(sc);
1223
1224 USB_BUS_UNLOCK(&sc->sc_bus);
1225
1226 /* catch any lost interrupts */
1227
1228 avr32dci_do_poll(&sc->sc_bus);
1229
1230 return (0); /* success */
1231}
1232
1233void
1234avr32dci_uninit(struct avr32dci_softc *sc)
1235{
1236 uint8_t n;
1237
1238 USB_BUS_LOCK(&sc->sc_bus);
1239
1240 /* turn on clocks */
1241 (sc->sc_clocks_on) (&sc->sc_bus);
1242
1243 /* disable interrupts */
1244 avr32dci_mod_ien(sc, 0, 0xFFFFFFFF);
1245
1246 /* reset all endpoints */
1247/**INDENT** Warning@1242: Extra ) */
1248 AVR32_WRITE_4(sc, AVR32_EPTRST, (1 << AVR32_EP_MAX) - 1));
1249
1250 /* disable all endpoints */
1251 for (n = 0; n != AVR32_EP_MAX; n++) {
1252 /* disable endpoint */
1253 AVR32_WRITE_4(sc, AVR32_EPTCTLDIS(n), AVR32_EPTCTL_EPT_ENABL);
1254 }
1255
1256 sc->sc_flags.port_powered = 0;
1257 sc->sc_flags.status_vbus = 0;
1258 sc->sc_flags.status_bus_reset = 0;
1259 sc->sc_flags.status_suspend = 0;
1260 sc->sc_flags.change_suspend = 0;
1261 sc->sc_flags.change_connect = 1;
1262
1263 avr32dci_pull_down(sc);
1264 avr32dci_clocks_off(sc);
1265
1266 USB_BUS_UNLOCK(&sc->sc_bus);
1267}
1268
1269void
1270avr32dci_suspend(struct avr32dci_softc *sc)
1271{
1272 return;
1273}
1274
1275void
1276avr32dci_resume(struct avr32dci_softc *sc)
1277{
1278 return;
1279}
1280
1281static void
1282avr32dci_do_poll(struct usb_bus *bus)
1283{
1284 struct avr32dci_softc *sc = AVR32_BUS2SC(bus);
1285
1286 USB_BUS_LOCK(&sc->sc_bus);
1287 avr32dci_interrupt_poll(sc);
1288 USB_BUS_UNLOCK(&sc->sc_bus);
1289}
1290
1291/*------------------------------------------------------------------------*
1292 * at91dci bulk support
1293 * at91dci control support
1294 * at91dci interrupt support
1295 *------------------------------------------------------------------------*/
1296static void
1297avr32dci_device_non_isoc_open(struct usb_xfer *xfer)
1298{
1299 return;
1300}
1301
1302static void
1303avr32dci_device_non_isoc_close(struct usb_xfer *xfer)
1304{
1305 avr32dci_device_done(xfer, USB_ERR_CANCELLED);
1306}
1307
1308static void
1309avr32dci_device_non_isoc_enter(struct usb_xfer *xfer)
1310{
1311 return;
1312}
1313
1314static void
1315avr32dci_device_non_isoc_start(struct usb_xfer *xfer)
1316{
1317 /* setup TDs */
1318 avr32dci_setup_standard_chain(xfer);
1319 avr32dci_start_standard_chain(xfer);
1320}
1321
1322struct usb_pipe_methods avr32dci_device_non_isoc_methods =
1323{
1324 .open = avr32dci_device_non_isoc_open,
1325 .close = avr32dci_device_non_isoc_close,
1326 .enter = avr32dci_device_non_isoc_enter,
1327 .start = avr32dci_device_non_isoc_start,
1328};
1329
1330/*------------------------------------------------------------------------*
1331 * at91dci full speed isochronous support
1332 *------------------------------------------------------------------------*/
1333static void
1334avr32dci_device_isoc_fs_open(struct usb_xfer *xfer)
1335{
1336 return;
1337}
1338
1339static void
1340avr32dci_device_isoc_fs_close(struct usb_xfer *xfer)
1341{
1342 avr32dci_device_done(xfer, USB_ERR_CANCELLED);
1343}
1344
1345static void
1346avr32dci_device_isoc_fs_enter(struct usb_xfer *xfer)
1347{
1348 struct avr32dci_softc *sc = AVR32_BUS2SC(xfer->xroot->bus);
1349 uint32_t temp;
1350 uint32_t nframes;
1351 uint8_t ep_no;
1352
1353 DPRINTFN(6, "xfer=%p next=%d nframes=%d\n",
1354 xfer, xfer->pipe->isoc_next, xfer->nframes);
1355
1356 /* get the current frame index */
1357 ep_no = xfer->endpoint & UE_ADDR_MASK;
1358 nframes = (AVR32_READ_4(sc, AVR32_FNUM) / 8);
1359
1360 nframes &= AVR32_FRAME_MASK;
1361
1362 /*
1363 * check if the frame index is within the window where the frames
1364 * will be inserted
1365 */
1366 temp = (nframes - xfer->pipe->isoc_next) & AVR32_FRAME_MASK;
1367
1368 if ((xfer->pipe->is_synced == 0) ||
1369 (temp < xfer->nframes)) {
1370 /*
1371 * If there is data underflow or the pipe queue is
1372 * empty we schedule the transfer a few frames ahead
1373 * of the current frame position. Else two isochronous
1374 * transfers might overlap.
1375 */
1376 xfer->pipe->isoc_next = (nframes + 3) & AVR32_FRAME_MASK;
1377 xfer->pipe->is_synced = 1;
1378 DPRINTFN(3, "start next=%d\n", xfer->pipe->isoc_next);
1379 }
1380 /*
1381 * compute how many milliseconds the insertion is ahead of the
1382 * current frame position:
1383 */
1384 temp = (xfer->pipe->isoc_next - nframes) & AVR32_FRAME_MASK;
1385
1386 /*
1387 * pre-compute when the isochronous transfer will be finished:
1388 */
1389 xfer->isoc_time_complete =
|
1390 usb2_isoc_time_expand(&sc->sc_bus, nframes) + temp +
| 1390 usb_isoc_time_expand(&sc->sc_bus, nframes) + temp +
|
1391 xfer->nframes;
1392
1393 /* compute frame number for next insertion */
1394 xfer->pipe->isoc_next += xfer->nframes;
1395
1396 /* setup TDs */
1397 avr32dci_setup_standard_chain(xfer);
1398}
1399
1400static void
1401avr32dci_device_isoc_fs_start(struct usb_xfer *xfer)
1402{
1403 /* start TD chain */
1404 avr32dci_start_standard_chain(xfer);
1405}
1406
1407struct usb_pipe_methods avr32dci_device_isoc_fs_methods =
1408{
1409 .open = avr32dci_device_isoc_fs_open,
1410 .close = avr32dci_device_isoc_fs_close,
1411 .enter = avr32dci_device_isoc_fs_enter,
1412 .start = avr32dci_device_isoc_fs_start,
1413};
1414
1415/*------------------------------------------------------------------------*
1416 * at91dci root control support
1417 *------------------------------------------------------------------------*
1418 * Simulate a hardware HUB by handling all the necessary requests.
1419 *------------------------------------------------------------------------*/
1420
1421static const struct usb_device_descriptor avr32dci_devd = {
1422 .bLength = sizeof(struct usb_device_descriptor),
1423 .bDescriptorType = UDESC_DEVICE,
1424 .bcdUSB = {0x00, 0x02},
1425 .bDeviceClass = UDCLASS_HUB,
1426 .bDeviceSubClass = UDSUBCLASS_HUB,
1427 .bDeviceProtocol = UDPROTO_HSHUBSTT,
1428 .bMaxPacketSize = 64,
1429 .bcdDevice = {0x00, 0x01},
1430 .iManufacturer = 1,
1431 .iProduct = 2,
1432 .bNumConfigurations = 1,
1433};
1434
1435static const struct usb_device_qualifier avr32dci_odevd = {
1436 .bLength = sizeof(struct usb_device_qualifier),
1437 .bDescriptorType = UDESC_DEVICE_QUALIFIER,
1438 .bcdUSB = {0x00, 0x02},
1439 .bDeviceClass = UDCLASS_HUB,
1440 .bDeviceSubClass = UDSUBCLASS_HUB,
1441 .bDeviceProtocol = UDPROTO_FSHUB,
1442 .bMaxPacketSize0 = 0,
1443 .bNumConfigurations = 0,
1444};
1445
1446static const struct avr32dci_config_desc avr32dci_confd = {
1447 .confd = {
1448 .bLength = sizeof(struct usb_config_descriptor),
1449 .bDescriptorType = UDESC_CONFIG,
1450 .wTotalLength[0] = sizeof(avr32dci_confd),
1451 .bNumInterface = 1,
1452 .bConfigurationValue = 1,
1453 .iConfiguration = 0,
1454 .bmAttributes = UC_SELF_POWERED,
1455 .bMaxPower = 0,
1456 },
1457 .ifcd = {
1458 .bLength = sizeof(struct usb_interface_descriptor),
1459 .bDescriptorType = UDESC_INTERFACE,
1460 .bNumEndpoints = 1,
1461 .bInterfaceClass = UICLASS_HUB,
1462 .bInterfaceSubClass = UISUBCLASS_HUB,
1463 .bInterfaceProtocol = UIPROTO_HSHUBSTT,
1464 },
1465 .endpd = {
1466 .bLength = sizeof(struct usb_endpoint_descriptor),
1467 .bDescriptorType = UDESC_ENDPOINT,
1468 .bEndpointAddress = (UE_DIR_IN | AVR32_INTR_ENDPT),
1469 .bmAttributes = UE_INTERRUPT,
1470 .wMaxPacketSize[0] = 8,
1471 .bInterval = 255,
1472 },
1473};
1474
1475static const struct usb_hub_descriptor_min avr32dci_hubd = {
1476 .bDescLength = sizeof(avr32dci_hubd),
1477 .bDescriptorType = UDESC_HUB,
1478 .bNbrPorts = 1,
1479 .wHubCharacteristics[0] =
1480 (UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL) & 0xFF,
1481 .wHubCharacteristics[1] =
1482 (UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL) >> 8,
1483 .bPwrOn2PwrGood = 50,
1484 .bHubContrCurrent = 0,
1485 .DeviceRemovable = {0}, /* port is removable */
1486};
1487
1488#define STRING_LANG \
1489 0x09, 0x04, /* American English */
1490
1491#define STRING_VENDOR \
1492 'A', 0, 'V', 0, 'R', 0, '3', 0, '2', 0
1493
1494#define STRING_PRODUCT \
1495 'D', 0, 'C', 0, 'I', 0, ' ', 0, 'R', 0, \
1496 'o', 0, 'o', 0, 't', 0, ' ', 0, 'H', 0, \
1497 'U', 0, 'B', 0,
1498
1499USB_MAKE_STRING_DESC(STRING_LANG, avr32dci_langtab);
1500USB_MAKE_STRING_DESC(STRING_VENDOR, avr32dci_vendor);
1501USB_MAKE_STRING_DESC(STRING_PRODUCT, avr32dci_product);
1502
1503static usb_error_t
1504avr32dci_roothub_exec(struct usb_device *udev,
1505 struct usb_device_request *req, const void **pptr, uint16_t *plength)
1506{
1507 struct avr32dci_softc *sc = AVR32_BUS2SC(udev->bus);
1508 const void *ptr;
1509 uint16_t len;
1510 uint16_t value;
1511 uint16_t index;
1512 uint32_t temp;
1513 usb_error_t err;
1514
1515 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
1516
1517 /* buffer reset */
1518 ptr = (const void *)&sc->sc_hub_temp;
1519 len = 0;
1520 err = 0;
1521
1522 value = UGETW(req->wValue);
1523 index = UGETW(req->wIndex);
1524
1525 /* demultiplex the control request */
1526
1527 switch (req->bmRequestType) {
1528 case UT_READ_DEVICE:
1529 switch (req->bRequest) {
1530 case UR_GET_DESCRIPTOR:
1531 goto tr_handle_get_descriptor;
1532 case UR_GET_CONFIG:
1533 goto tr_handle_get_config;
1534 case UR_GET_STATUS:
1535 goto tr_handle_get_status;
1536 default:
1537 goto tr_stalled;
1538 }
1539 break;
1540
1541 case UT_WRITE_DEVICE:
1542 switch (req->bRequest) {
1543 case UR_SET_ADDRESS:
1544 goto tr_handle_set_address;
1545 case UR_SET_CONFIG:
1546 goto tr_handle_set_config;
1547 case UR_CLEAR_FEATURE:
1548 goto tr_valid; /* nop */
1549 case UR_SET_DESCRIPTOR:
1550 goto tr_valid; /* nop */
1551 case UR_SET_FEATURE:
1552 default:
1553 goto tr_stalled;
1554 }
1555 break;
1556
1557 case UT_WRITE_ENDPOINT:
1558 switch (req->bRequest) {
1559 case UR_CLEAR_FEATURE:
1560 switch (UGETW(req->wValue)) {
1561 case UF_ENDPOINT_HALT:
1562 goto tr_handle_clear_halt;
1563 case UF_DEVICE_REMOTE_WAKEUP:
1564 goto tr_handle_clear_wakeup;
1565 default:
1566 goto tr_stalled;
1567 }
1568 break;
1569 case UR_SET_FEATURE:
1570 switch (UGETW(req->wValue)) {
1571 case UF_ENDPOINT_HALT:
1572 goto tr_handle_set_halt;
1573 case UF_DEVICE_REMOTE_WAKEUP:
1574 goto tr_handle_set_wakeup;
1575 default:
1576 goto tr_stalled;
1577 }
1578 break;
1579 case UR_SYNCH_FRAME:
1580 goto tr_valid; /* nop */
1581 default:
1582 goto tr_stalled;
1583 }
1584 break;
1585
1586 case UT_READ_ENDPOINT:
1587 switch (req->bRequest) {
1588 case UR_GET_STATUS:
1589 goto tr_handle_get_ep_status;
1590 default:
1591 goto tr_stalled;
1592 }
1593 break;
1594
1595 case UT_WRITE_INTERFACE:
1596 switch (req->bRequest) {
1597 case UR_SET_INTERFACE:
1598 goto tr_handle_set_interface;
1599 case UR_CLEAR_FEATURE:
1600 goto tr_valid; /* nop */
1601 case UR_SET_FEATURE:
1602 default:
1603 goto tr_stalled;
1604 }
1605 break;
1606
1607 case UT_READ_INTERFACE:
1608 switch (req->bRequest) {
1609 case UR_GET_INTERFACE:
1610 goto tr_handle_get_interface;
1611 case UR_GET_STATUS:
1612 goto tr_handle_get_iface_status;
1613 default:
1614 goto tr_stalled;
1615 }
1616 break;
1617
1618 case UT_WRITE_CLASS_INTERFACE:
1619 case UT_WRITE_VENDOR_INTERFACE:
1620 /* XXX forward */
1621 break;
1622
1623 case UT_READ_CLASS_INTERFACE:
1624 case UT_READ_VENDOR_INTERFACE:
1625 /* XXX forward */
1626 break;
1627
1628 case UT_WRITE_CLASS_DEVICE:
1629 switch (req->bRequest) {
1630 case UR_CLEAR_FEATURE:
1631 goto tr_valid;
1632 case UR_SET_DESCRIPTOR:
1633 case UR_SET_FEATURE:
1634 break;
1635 default:
1636 goto tr_stalled;
1637 }
1638 break;
1639
1640 case UT_WRITE_CLASS_OTHER:
1641 switch (req->bRequest) {
1642 case UR_CLEAR_FEATURE:
1643 goto tr_handle_clear_port_feature;
1644 case UR_SET_FEATURE:
1645 goto tr_handle_set_port_feature;
1646 case UR_CLEAR_TT_BUFFER:
1647 case UR_RESET_TT:
1648 case UR_STOP_TT:
1649 goto tr_valid;
1650
1651 default:
1652 goto tr_stalled;
1653 }
1654 break;
1655
1656 case UT_READ_CLASS_OTHER:
1657 switch (req->bRequest) {
1658 case UR_GET_TT_STATE:
1659 goto tr_handle_get_tt_state;
1660 case UR_GET_STATUS:
1661 goto tr_handle_get_port_status;
1662 default:
1663 goto tr_stalled;
1664 }
1665 break;
1666
1667 case UT_READ_CLASS_DEVICE:
1668 switch (req->bRequest) {
1669 case UR_GET_DESCRIPTOR:
1670 goto tr_handle_get_class_descriptor;
1671 case UR_GET_STATUS:
1672 goto tr_handle_get_class_status;
1673
1674 default:
1675 goto tr_stalled;
1676 }
1677 break;
1678 default:
1679 goto tr_stalled;
1680 }
1681 goto tr_valid;
1682
1683tr_handle_get_descriptor:
1684 switch (value >> 8) {
1685 case UDESC_DEVICE:
1686 if (value & 0xff) {
1687 goto tr_stalled;
1688 }
1689 len = sizeof(avr32dci_devd);
1690 ptr = (const void *)&avr32dci_devd;
1691 goto tr_valid;
1692 case UDESC_CONFIG:
1693 if (value & 0xff) {
1694 goto tr_stalled;
1695 }
1696 len = sizeof(avr32dci_confd);
1697 ptr = (const void *)&avr32dci_confd;
1698 goto tr_valid;
1699 case UDESC_STRING:
1700 switch (value & 0xff) {
1701 case 0: /* Language table */
1702 len = sizeof(avr32dci_langtab);
1703 ptr = (const void *)&avr32dci_langtab;
1704 goto tr_valid;
1705
1706 case 1: /* Vendor */
1707 len = sizeof(avr32dci_vendor);
1708 ptr = (const void *)&avr32dci_vendor;
1709 goto tr_valid;
1710
1711 case 2: /* Product */
1712 len = sizeof(avr32dci_product);
1713 ptr = (const void *)&avr32dci_product;
1714 goto tr_valid;
1715 default:
1716 break;
1717 }
1718 break;
1719 default:
1720 goto tr_stalled;
1721 }
1722 goto tr_stalled;
1723
1724tr_handle_get_config:
1725 len = 1;
1726 sc->sc_hub_temp.wValue[0] = sc->sc_conf;
1727 goto tr_valid;
1728
1729tr_handle_get_status:
1730 len = 2;
1731 USETW(sc->sc_hub_temp.wValue, UDS_SELF_POWERED);
1732 goto tr_valid;
1733
1734tr_handle_set_address:
1735 if (value & 0xFF00) {
1736 goto tr_stalled;
1737 }
1738 sc->sc_rt_addr = value;
1739 goto tr_valid;
1740
1741tr_handle_set_config:
1742 if (value >= 2) {
1743 goto tr_stalled;
1744 }
1745 sc->sc_conf = value;
1746 goto tr_valid;
1747
1748tr_handle_get_interface:
1749 len = 1;
1750 sc->sc_hub_temp.wValue[0] = 0;
1751 goto tr_valid;
1752
1753tr_handle_get_tt_state:
1754tr_handle_get_class_status:
1755tr_handle_get_iface_status:
1756tr_handle_get_ep_status:
1757 len = 2;
1758 USETW(sc->sc_hub_temp.wValue, 0);
1759 goto tr_valid;
1760
1761tr_handle_set_halt:
1762tr_handle_set_interface:
1763tr_handle_set_wakeup:
1764tr_handle_clear_wakeup:
1765tr_handle_clear_halt:
1766 goto tr_valid;
1767
1768tr_handle_clear_port_feature:
1769 if (index != 1) {
1770 goto tr_stalled;
1771 }
1772 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE on port %d\n", index);
1773
1774 switch (value) {
1775 case UHF_PORT_SUSPEND:
1776 avr32dci_wakeup_peer(sc);
1777 break;
1778
1779 case UHF_PORT_ENABLE:
1780 sc->sc_flags.port_enabled = 0;
1781 break;
1782
1783 case UHF_PORT_TEST:
1784 case UHF_PORT_INDICATOR:
1785 case UHF_C_PORT_ENABLE:
1786 case UHF_C_PORT_OVER_CURRENT:
1787 case UHF_C_PORT_RESET:
1788 /* nops */
1789 break;
1790 case UHF_PORT_POWER:
1791 sc->sc_flags.port_powered = 0;
1792 avr32dci_pull_down(sc);
1793 avr32dci_clocks_off(sc);
1794 break;
1795 case UHF_C_PORT_CONNECTION:
1796 /* clear connect change flag */
1797 sc->sc_flags.change_connect = 0;
1798
1799 if (!sc->sc_flags.status_bus_reset) {
1800 /* we are not connected */
1801 break;
1802 }
1803 /* configure the control endpoint */
1804 /* set endpoint reset */
1805 AVR32_WRITE_4(sc, AVR32_EPTRST, AVR32_EPTRST_MASK(0));
1806
1807 /* set stall */
1808 AVR32_WRITE_4(sc, AVR32_EPTSETSTA(0), AVR32_EPTSTA_FRCESTALL);
1809
1810 /* reset data toggle */
1811 AVR32_WRITE_4(sc, AVR32_EPTCLRSTA(0), AVR32_EPTSTA_TOGGLESQ);
1812
1813 /* clear stall */
1814 AVR32_WRITE_4(sc, AVR32_EPTCLRSTA(0), AVR32_EPTSTA_FRCESTALL);
1815
1816 /* configure */
1817 AVR32_WRITE_4(sc, AVR32_EPTCFG(0), AVR32_EPTCFG_TYPE_CONTROL |
1818 AVR32_EPTCFG_NBANK(1) | AVR32_EPTCFG_EPSIZE(6));
1819
1820 temp = AVR32_READ_4(sc, AVR32_EPTCFG(0));
1821
1822 if (!(temp & AVR32_EPTCFG_EPT_MAPD)) {
1823 DPRINTFN(0, "Chip rejected configuration\n");
1824 } else {
1825 AVR32_WRITE_4(sc, AVR32_EPTCTLENB(0),
1826 AVR32_EPTCTL_EPT_ENABL);
1827 }
1828 break;
1829 case UHF_C_PORT_SUSPEND:
1830 sc->sc_flags.change_suspend = 0;
1831 break;
1832 default:
1833 err = USB_ERR_IOERROR;
1834 goto done;
1835 }
1836 goto tr_valid;
1837
1838tr_handle_set_port_feature:
1839 if (index != 1) {
1840 goto tr_stalled;
1841 }
1842 DPRINTFN(9, "UR_SET_PORT_FEATURE\n");
1843
1844 switch (value) {
1845 case UHF_PORT_ENABLE:
1846 sc->sc_flags.port_enabled = 1;
1847 break;
1848 case UHF_PORT_SUSPEND:
1849 case UHF_PORT_RESET:
1850 case UHF_PORT_TEST:
1851 case UHF_PORT_INDICATOR:
1852 /* nops */
1853 break;
1854 case UHF_PORT_POWER:
1855 sc->sc_flags.port_powered = 1;
1856 break;
1857 default:
1858 err = USB_ERR_IOERROR;
1859 goto done;
1860 }
1861 goto tr_valid;
1862
1863tr_handle_get_port_status:
1864
1865 DPRINTFN(9, "UR_GET_PORT_STATUS\n");
1866
1867 if (index != 1) {
1868 goto tr_stalled;
1869 }
1870 if (sc->sc_flags.status_vbus) {
1871 avr32dci_clocks_on(sc);
1872 avr32dci_pull_up(sc);
1873 } else {
1874 avr32dci_pull_down(sc);
1875 avr32dci_clocks_off(sc);
1876 }
1877
1878 /* Select Device Side Mode */
1879
1880 value = UPS_PORT_MODE_DEVICE;
1881
1882 /* Check for High Speed */
1883 if (AVR32_READ_4(sc, AVR32_INTSTA) & AVR32_INT_SPEED)
1884 value |= UPS_HIGH_SPEED;
1885
1886 if (sc->sc_flags.port_powered) {
1887 value |= UPS_PORT_POWER;
1888 }
1889 if (sc->sc_flags.port_enabled) {
1890 value |= UPS_PORT_ENABLED;
1891 }
1892 if (sc->sc_flags.status_vbus &&
1893 sc->sc_flags.status_bus_reset) {
1894 value |= UPS_CURRENT_CONNECT_STATUS;
1895 }
1896 if (sc->sc_flags.status_suspend) {
1897 value |= UPS_SUSPEND;
1898 }
1899 USETW(sc->sc_hub_temp.ps.wPortStatus, value);
1900
1901 value = 0;
1902
1903 if (sc->sc_flags.change_connect) {
1904 value |= UPS_C_CONNECT_STATUS;
1905 }
1906 if (sc->sc_flags.change_suspend) {
1907 value |= UPS_C_SUSPEND;
1908 }
1909 USETW(sc->sc_hub_temp.ps.wPortChange, value);
1910 len = sizeof(sc->sc_hub_temp.ps);
1911 goto tr_valid;
1912
1913tr_handle_get_class_descriptor:
1914 if (value & 0xFF) {
1915 goto tr_stalled;
1916 }
1917 ptr = (const void *)&avr32dci_hubd;
1918 len = sizeof(avr32dci_hubd);
1919 goto tr_valid;
1920
1921tr_stalled:
1922 err = USB_ERR_STALLED;
1923tr_valid:
1924done:
1925 *plength = len;
1926 *pptr = ptr;
1927 return (err);
1928}
1929
1930static void
1931avr32dci_xfer_setup(struct usb_setup_params *parm)
1932{
1933 const struct usb_hw_ep_profile *pf;
1934 struct avr32dci_softc *sc;
1935 struct usb_xfer *xfer;
1936 void *last_obj;
1937 uint32_t ntd;
1938 uint32_t n;
1939 uint8_t ep_no;
1940
1941 sc = AVR32_BUS2SC(parm->udev->bus);
1942 xfer = parm->curr_xfer;
1943
1944 /*
1945 * NOTE: This driver does not use any of the parameters that
1946 * are computed from the following values. Just set some
1947 * reasonable dummies:
1948 */
1949 parm->hc_max_packet_size = 0x400;
1950 parm->hc_max_packet_count = 1;
1951 parm->hc_max_frame_size = 0x400;
1952
| 1391 xfer->nframes;
1392
1393 /* compute frame number for next insertion */
1394 xfer->pipe->isoc_next += xfer->nframes;
1395
1396 /* setup TDs */
1397 avr32dci_setup_standard_chain(xfer);
1398}
1399
1400static void
1401avr32dci_device_isoc_fs_start(struct usb_xfer *xfer)
1402{
1403 /* start TD chain */
1404 avr32dci_start_standard_chain(xfer);
1405}
1406
1407struct usb_pipe_methods avr32dci_device_isoc_fs_methods =
1408{
1409 .open = avr32dci_device_isoc_fs_open,
1410 .close = avr32dci_device_isoc_fs_close,
1411 .enter = avr32dci_device_isoc_fs_enter,
1412 .start = avr32dci_device_isoc_fs_start,
1413};
1414
1415/*------------------------------------------------------------------------*
1416 * at91dci root control support
1417 *------------------------------------------------------------------------*
1418 * Simulate a hardware HUB by handling all the necessary requests.
1419 *------------------------------------------------------------------------*/
1420
1421static const struct usb_device_descriptor avr32dci_devd = {
1422 .bLength = sizeof(struct usb_device_descriptor),
1423 .bDescriptorType = UDESC_DEVICE,
1424 .bcdUSB = {0x00, 0x02},
1425 .bDeviceClass = UDCLASS_HUB,
1426 .bDeviceSubClass = UDSUBCLASS_HUB,
1427 .bDeviceProtocol = UDPROTO_HSHUBSTT,
1428 .bMaxPacketSize = 64,
1429 .bcdDevice = {0x00, 0x01},
1430 .iManufacturer = 1,
1431 .iProduct = 2,
1432 .bNumConfigurations = 1,
1433};
1434
1435static const struct usb_device_qualifier avr32dci_odevd = {
1436 .bLength = sizeof(struct usb_device_qualifier),
1437 .bDescriptorType = UDESC_DEVICE_QUALIFIER,
1438 .bcdUSB = {0x00, 0x02},
1439 .bDeviceClass = UDCLASS_HUB,
1440 .bDeviceSubClass = UDSUBCLASS_HUB,
1441 .bDeviceProtocol = UDPROTO_FSHUB,
1442 .bMaxPacketSize0 = 0,
1443 .bNumConfigurations = 0,
1444};
1445
1446static const struct avr32dci_config_desc avr32dci_confd = {
1447 .confd = {
1448 .bLength = sizeof(struct usb_config_descriptor),
1449 .bDescriptorType = UDESC_CONFIG,
1450 .wTotalLength[0] = sizeof(avr32dci_confd),
1451 .bNumInterface = 1,
1452 .bConfigurationValue = 1,
1453 .iConfiguration = 0,
1454 .bmAttributes = UC_SELF_POWERED,
1455 .bMaxPower = 0,
1456 },
1457 .ifcd = {
1458 .bLength = sizeof(struct usb_interface_descriptor),
1459 .bDescriptorType = UDESC_INTERFACE,
1460 .bNumEndpoints = 1,
1461 .bInterfaceClass = UICLASS_HUB,
1462 .bInterfaceSubClass = UISUBCLASS_HUB,
1463 .bInterfaceProtocol = UIPROTO_HSHUBSTT,
1464 },
1465 .endpd = {
1466 .bLength = sizeof(struct usb_endpoint_descriptor),
1467 .bDescriptorType = UDESC_ENDPOINT,
1468 .bEndpointAddress = (UE_DIR_IN | AVR32_INTR_ENDPT),
1469 .bmAttributes = UE_INTERRUPT,
1470 .wMaxPacketSize[0] = 8,
1471 .bInterval = 255,
1472 },
1473};
1474
1475static const struct usb_hub_descriptor_min avr32dci_hubd = {
1476 .bDescLength = sizeof(avr32dci_hubd),
1477 .bDescriptorType = UDESC_HUB,
1478 .bNbrPorts = 1,
1479 .wHubCharacteristics[0] =
1480 (UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL) & 0xFF,
1481 .wHubCharacteristics[1] =
1482 (UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL) >> 8,
1483 .bPwrOn2PwrGood = 50,
1484 .bHubContrCurrent = 0,
1485 .DeviceRemovable = {0}, /* port is removable */
1486};
1487
1488#define STRING_LANG \
1489 0x09, 0x04, /* American English */
1490
1491#define STRING_VENDOR \
1492 'A', 0, 'V', 0, 'R', 0, '3', 0, '2', 0
1493
1494#define STRING_PRODUCT \
1495 'D', 0, 'C', 0, 'I', 0, ' ', 0, 'R', 0, \
1496 'o', 0, 'o', 0, 't', 0, ' ', 0, 'H', 0, \
1497 'U', 0, 'B', 0,
1498
1499USB_MAKE_STRING_DESC(STRING_LANG, avr32dci_langtab);
1500USB_MAKE_STRING_DESC(STRING_VENDOR, avr32dci_vendor);
1501USB_MAKE_STRING_DESC(STRING_PRODUCT, avr32dci_product);
1502
1503static usb_error_t
1504avr32dci_roothub_exec(struct usb_device *udev,
1505 struct usb_device_request *req, const void **pptr, uint16_t *plength)
1506{
1507 struct avr32dci_softc *sc = AVR32_BUS2SC(udev->bus);
1508 const void *ptr;
1509 uint16_t len;
1510 uint16_t value;
1511 uint16_t index;
1512 uint32_t temp;
1513 usb_error_t err;
1514
1515 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
1516
1517 /* buffer reset */
1518 ptr = (const void *)&sc->sc_hub_temp;
1519 len = 0;
1520 err = 0;
1521
1522 value = UGETW(req->wValue);
1523 index = UGETW(req->wIndex);
1524
1525 /* demultiplex the control request */
1526
1527 switch (req->bmRequestType) {
1528 case UT_READ_DEVICE:
1529 switch (req->bRequest) {
1530 case UR_GET_DESCRIPTOR:
1531 goto tr_handle_get_descriptor;
1532 case UR_GET_CONFIG:
1533 goto tr_handle_get_config;
1534 case UR_GET_STATUS:
1535 goto tr_handle_get_status;
1536 default:
1537 goto tr_stalled;
1538 }
1539 break;
1540
1541 case UT_WRITE_DEVICE:
1542 switch (req->bRequest) {
1543 case UR_SET_ADDRESS:
1544 goto tr_handle_set_address;
1545 case UR_SET_CONFIG:
1546 goto tr_handle_set_config;
1547 case UR_CLEAR_FEATURE:
1548 goto tr_valid; /* nop */
1549 case UR_SET_DESCRIPTOR:
1550 goto tr_valid; /* nop */
1551 case UR_SET_FEATURE:
1552 default:
1553 goto tr_stalled;
1554 }
1555 break;
1556
1557 case UT_WRITE_ENDPOINT:
1558 switch (req->bRequest) {
1559 case UR_CLEAR_FEATURE:
1560 switch (UGETW(req->wValue)) {
1561 case UF_ENDPOINT_HALT:
1562 goto tr_handle_clear_halt;
1563 case UF_DEVICE_REMOTE_WAKEUP:
1564 goto tr_handle_clear_wakeup;
1565 default:
1566 goto tr_stalled;
1567 }
1568 break;
1569 case UR_SET_FEATURE:
1570 switch (UGETW(req->wValue)) {
1571 case UF_ENDPOINT_HALT:
1572 goto tr_handle_set_halt;
1573 case UF_DEVICE_REMOTE_WAKEUP:
1574 goto tr_handle_set_wakeup;
1575 default:
1576 goto tr_stalled;
1577 }
1578 break;
1579 case UR_SYNCH_FRAME:
1580 goto tr_valid; /* nop */
1581 default:
1582 goto tr_stalled;
1583 }
1584 break;
1585
1586 case UT_READ_ENDPOINT:
1587 switch (req->bRequest) {
1588 case UR_GET_STATUS:
1589 goto tr_handle_get_ep_status;
1590 default:
1591 goto tr_stalled;
1592 }
1593 break;
1594
1595 case UT_WRITE_INTERFACE:
1596 switch (req->bRequest) {
1597 case UR_SET_INTERFACE:
1598 goto tr_handle_set_interface;
1599 case UR_CLEAR_FEATURE:
1600 goto tr_valid; /* nop */
1601 case UR_SET_FEATURE:
1602 default:
1603 goto tr_stalled;
1604 }
1605 break;
1606
1607 case UT_READ_INTERFACE:
1608 switch (req->bRequest) {
1609 case UR_GET_INTERFACE:
1610 goto tr_handle_get_interface;
1611 case UR_GET_STATUS:
1612 goto tr_handle_get_iface_status;
1613 default:
1614 goto tr_stalled;
1615 }
1616 break;
1617
1618 case UT_WRITE_CLASS_INTERFACE:
1619 case UT_WRITE_VENDOR_INTERFACE:
1620 /* XXX forward */
1621 break;
1622
1623 case UT_READ_CLASS_INTERFACE:
1624 case UT_READ_VENDOR_INTERFACE:
1625 /* XXX forward */
1626 break;
1627
1628 case UT_WRITE_CLASS_DEVICE:
1629 switch (req->bRequest) {
1630 case UR_CLEAR_FEATURE:
1631 goto tr_valid;
1632 case UR_SET_DESCRIPTOR:
1633 case UR_SET_FEATURE:
1634 break;
1635 default:
1636 goto tr_stalled;
1637 }
1638 break;
1639
1640 case UT_WRITE_CLASS_OTHER:
1641 switch (req->bRequest) {
1642 case UR_CLEAR_FEATURE:
1643 goto tr_handle_clear_port_feature;
1644 case UR_SET_FEATURE:
1645 goto tr_handle_set_port_feature;
1646 case UR_CLEAR_TT_BUFFER:
1647 case UR_RESET_TT:
1648 case UR_STOP_TT:
1649 goto tr_valid;
1650
1651 default:
1652 goto tr_stalled;
1653 }
1654 break;
1655
1656 case UT_READ_CLASS_OTHER:
1657 switch (req->bRequest) {
1658 case UR_GET_TT_STATE:
1659 goto tr_handle_get_tt_state;
1660 case UR_GET_STATUS:
1661 goto tr_handle_get_port_status;
1662 default:
1663 goto tr_stalled;
1664 }
1665 break;
1666
1667 case UT_READ_CLASS_DEVICE:
1668 switch (req->bRequest) {
1669 case UR_GET_DESCRIPTOR:
1670 goto tr_handle_get_class_descriptor;
1671 case UR_GET_STATUS:
1672 goto tr_handle_get_class_status;
1673
1674 default:
1675 goto tr_stalled;
1676 }
1677 break;
1678 default:
1679 goto tr_stalled;
1680 }
1681 goto tr_valid;
1682
1683tr_handle_get_descriptor:
1684 switch (value >> 8) {
1685 case UDESC_DEVICE:
1686 if (value & 0xff) {
1687 goto tr_stalled;
1688 }
1689 len = sizeof(avr32dci_devd);
1690 ptr = (const void *)&avr32dci_devd;
1691 goto tr_valid;
1692 case UDESC_CONFIG:
1693 if (value & 0xff) {
1694 goto tr_stalled;
1695 }
1696 len = sizeof(avr32dci_confd);
1697 ptr = (const void *)&avr32dci_confd;
1698 goto tr_valid;
1699 case UDESC_STRING:
1700 switch (value & 0xff) {
1701 case 0: /* Language table */
1702 len = sizeof(avr32dci_langtab);
1703 ptr = (const void *)&avr32dci_langtab;
1704 goto tr_valid;
1705
1706 case 1: /* Vendor */
1707 len = sizeof(avr32dci_vendor);
1708 ptr = (const void *)&avr32dci_vendor;
1709 goto tr_valid;
1710
1711 case 2: /* Product */
1712 len = sizeof(avr32dci_product);
1713 ptr = (const void *)&avr32dci_product;
1714 goto tr_valid;
1715 default:
1716 break;
1717 }
1718 break;
1719 default:
1720 goto tr_stalled;
1721 }
1722 goto tr_stalled;
1723
1724tr_handle_get_config:
1725 len = 1;
1726 sc->sc_hub_temp.wValue[0] = sc->sc_conf;
1727 goto tr_valid;
1728
1729tr_handle_get_status:
1730 len = 2;
1731 USETW(sc->sc_hub_temp.wValue, UDS_SELF_POWERED);
1732 goto tr_valid;
1733
1734tr_handle_set_address:
1735 if (value & 0xFF00) {
1736 goto tr_stalled;
1737 }
1738 sc->sc_rt_addr = value;
1739 goto tr_valid;
1740
1741tr_handle_set_config:
1742 if (value >= 2) {
1743 goto tr_stalled;
1744 }
1745 sc->sc_conf = value;
1746 goto tr_valid;
1747
1748tr_handle_get_interface:
1749 len = 1;
1750 sc->sc_hub_temp.wValue[0] = 0;
1751 goto tr_valid;
1752
1753tr_handle_get_tt_state:
1754tr_handle_get_class_status:
1755tr_handle_get_iface_status:
1756tr_handle_get_ep_status:
1757 len = 2;
1758 USETW(sc->sc_hub_temp.wValue, 0);
1759 goto tr_valid;
1760
1761tr_handle_set_halt:
1762tr_handle_set_interface:
1763tr_handle_set_wakeup:
1764tr_handle_clear_wakeup:
1765tr_handle_clear_halt:
1766 goto tr_valid;
1767
1768tr_handle_clear_port_feature:
1769 if (index != 1) {
1770 goto tr_stalled;
1771 }
1772 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE on port %d\n", index);
1773
1774 switch (value) {
1775 case UHF_PORT_SUSPEND:
1776 avr32dci_wakeup_peer(sc);
1777 break;
1778
1779 case UHF_PORT_ENABLE:
1780 sc->sc_flags.port_enabled = 0;
1781 break;
1782
1783 case UHF_PORT_TEST:
1784 case UHF_PORT_INDICATOR:
1785 case UHF_C_PORT_ENABLE:
1786 case UHF_C_PORT_OVER_CURRENT:
1787 case UHF_C_PORT_RESET:
1788 /* nops */
1789 break;
1790 case UHF_PORT_POWER:
1791 sc->sc_flags.port_powered = 0;
1792 avr32dci_pull_down(sc);
1793 avr32dci_clocks_off(sc);
1794 break;
1795 case UHF_C_PORT_CONNECTION:
1796 /* clear connect change flag */
1797 sc->sc_flags.change_connect = 0;
1798
1799 if (!sc->sc_flags.status_bus_reset) {
1800 /* we are not connected */
1801 break;
1802 }
1803 /* configure the control endpoint */
1804 /* set endpoint reset */
1805 AVR32_WRITE_4(sc, AVR32_EPTRST, AVR32_EPTRST_MASK(0));
1806
1807 /* set stall */
1808 AVR32_WRITE_4(sc, AVR32_EPTSETSTA(0), AVR32_EPTSTA_FRCESTALL);
1809
1810 /* reset data toggle */
1811 AVR32_WRITE_4(sc, AVR32_EPTCLRSTA(0), AVR32_EPTSTA_TOGGLESQ);
1812
1813 /* clear stall */
1814 AVR32_WRITE_4(sc, AVR32_EPTCLRSTA(0), AVR32_EPTSTA_FRCESTALL);
1815
1816 /* configure */
1817 AVR32_WRITE_4(sc, AVR32_EPTCFG(0), AVR32_EPTCFG_TYPE_CONTROL |
1818 AVR32_EPTCFG_NBANK(1) | AVR32_EPTCFG_EPSIZE(6));
1819
1820 temp = AVR32_READ_4(sc, AVR32_EPTCFG(0));
1821
1822 if (!(temp & AVR32_EPTCFG_EPT_MAPD)) {
1823 DPRINTFN(0, "Chip rejected configuration\n");
1824 } else {
1825 AVR32_WRITE_4(sc, AVR32_EPTCTLENB(0),
1826 AVR32_EPTCTL_EPT_ENABL);
1827 }
1828 break;
1829 case UHF_C_PORT_SUSPEND:
1830 sc->sc_flags.change_suspend = 0;
1831 break;
1832 default:
1833 err = USB_ERR_IOERROR;
1834 goto done;
1835 }
1836 goto tr_valid;
1837
1838tr_handle_set_port_feature:
1839 if (index != 1) {
1840 goto tr_stalled;
1841 }
1842 DPRINTFN(9, "UR_SET_PORT_FEATURE\n");
1843
1844 switch (value) {
1845 case UHF_PORT_ENABLE:
1846 sc->sc_flags.port_enabled = 1;
1847 break;
1848 case UHF_PORT_SUSPEND:
1849 case UHF_PORT_RESET:
1850 case UHF_PORT_TEST:
1851 case UHF_PORT_INDICATOR:
1852 /* nops */
1853 break;
1854 case UHF_PORT_POWER:
1855 sc->sc_flags.port_powered = 1;
1856 break;
1857 default:
1858 err = USB_ERR_IOERROR;
1859 goto done;
1860 }
1861 goto tr_valid;
1862
1863tr_handle_get_port_status:
1864
1865 DPRINTFN(9, "UR_GET_PORT_STATUS\n");
1866
1867 if (index != 1) {
1868 goto tr_stalled;
1869 }
1870 if (sc->sc_flags.status_vbus) {
1871 avr32dci_clocks_on(sc);
1872 avr32dci_pull_up(sc);
1873 } else {
1874 avr32dci_pull_down(sc);
1875 avr32dci_clocks_off(sc);
1876 }
1877
1878 /* Select Device Side Mode */
1879
1880 value = UPS_PORT_MODE_DEVICE;
1881
1882 /* Check for High Speed */
1883 if (AVR32_READ_4(sc, AVR32_INTSTA) & AVR32_INT_SPEED)
1884 value |= UPS_HIGH_SPEED;
1885
1886 if (sc->sc_flags.port_powered) {
1887 value |= UPS_PORT_POWER;
1888 }
1889 if (sc->sc_flags.port_enabled) {
1890 value |= UPS_PORT_ENABLED;
1891 }
1892 if (sc->sc_flags.status_vbus &&
1893 sc->sc_flags.status_bus_reset) {
1894 value |= UPS_CURRENT_CONNECT_STATUS;
1895 }
1896 if (sc->sc_flags.status_suspend) {
1897 value |= UPS_SUSPEND;
1898 }
1899 USETW(sc->sc_hub_temp.ps.wPortStatus, value);
1900
1901 value = 0;
1902
1903 if (sc->sc_flags.change_connect) {
1904 value |= UPS_C_CONNECT_STATUS;
1905 }
1906 if (sc->sc_flags.change_suspend) {
1907 value |= UPS_C_SUSPEND;
1908 }
1909 USETW(sc->sc_hub_temp.ps.wPortChange, value);
1910 len = sizeof(sc->sc_hub_temp.ps);
1911 goto tr_valid;
1912
1913tr_handle_get_class_descriptor:
1914 if (value & 0xFF) {
1915 goto tr_stalled;
1916 }
1917 ptr = (const void *)&avr32dci_hubd;
1918 len = sizeof(avr32dci_hubd);
1919 goto tr_valid;
1920
1921tr_stalled:
1922 err = USB_ERR_STALLED;
1923tr_valid:
1924done:
1925 *plength = len;
1926 *pptr = ptr;
1927 return (err);
1928}
1929
1930static void
1931avr32dci_xfer_setup(struct usb_setup_params *parm)
1932{
1933 const struct usb_hw_ep_profile *pf;
1934 struct avr32dci_softc *sc;
1935 struct usb_xfer *xfer;
1936 void *last_obj;
1937 uint32_t ntd;
1938 uint32_t n;
1939 uint8_t ep_no;
1940
1941 sc = AVR32_BUS2SC(parm->udev->bus);
1942 xfer = parm->curr_xfer;
1943
1944 /*
1945 * NOTE: This driver does not use any of the parameters that
1946 * are computed from the following values. Just set some
1947 * reasonable dummies:
1948 */
1949 parm->hc_max_packet_size = 0x400;
1950 parm->hc_max_packet_count = 1;
1951 parm->hc_max_frame_size = 0x400;
1952
|
1953 usb2_transfer_setup_sub(parm);
| 1953 usbd_transfer_setup_sub(parm);
|
1954
1955 /*
1956 * compute maximum number of TDs
1957 */
1958 if ((xfer->pipe->edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL) {
1959
1960 ntd = xfer->nframes + 1 /* STATUS */ + 1 /* SYNC 1 */
1961 + 1 /* SYNC 2 */ ;
1962 } else {
1963
1964 ntd = xfer->nframes + 1 /* SYNC */ ;
1965 }
1966
1967 /*
| 1954
1955 /*
1956 * compute maximum number of TDs
1957 */
1958 if ((xfer->pipe->edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL) {
1959
1960 ntd = xfer->nframes + 1 /* STATUS */ + 1 /* SYNC 1 */
1961 + 1 /* SYNC 2 */ ;
1962 } else {
1963
1964 ntd = xfer->nframes + 1 /* SYNC */ ;
1965 }
1966
1967 /*
|
1968 * check if "usb2_transfer_setup_sub" set an error
| 1968 * check if "usbd_transfer_setup_sub" set an error
|
1969 */
1970 if (parm->err)
1971 return;
1972
1973 /*
1974 * allocate transfer descriptors
1975 */
1976 last_obj = NULL;
1977
1978 /*
1979 * get profile stuff
1980 */
1981 ep_no = xfer->endpoint & UE_ADDR;
1982 avr32dci_get_hw_ep_profile(parm->udev, &pf, ep_no);
1983
1984 if (pf == NULL) {
1985 /* should not happen */
1986 parm->err = USB_ERR_INVAL;
1987 return;
1988 }
1989 /* align data */
1990 parm->size[0] += ((-parm->size[0]) & (USB_HOST_ALIGN - 1));
1991
1992 for (n = 0; n != ntd; n++) {
1993
1994 struct avr32dci_td *td;
1995
1996 if (parm->buf) {
1997 uint32_t temp;
1998
1999 td = USB_ADD_BYTES(parm->buf, parm->size[0]);
2000
2001 /* init TD */
2002 td->max_packet_size = xfer->max_packet_size;
2003 td->ep_no = ep_no;
2004 temp = pf->max_in_frame_size | pf->max_out_frame_size;
2005 td->bank_shift = 0;
2006 while ((temp /= 2))
2007 td->bank_shift++;
2008 if (pf->support_multi_buffer) {
2009 td->support_multi_buffer = 1;
2010 }
2011 td->obj_next = last_obj;
2012
2013 last_obj = td;
2014 }
2015 parm->size[0] += sizeof(*td);
2016 }
2017
2018 xfer->td_start[0] = last_obj;
2019}
2020
2021static void
2022avr32dci_xfer_unsetup(struct usb_xfer *xfer)
2023{
2024 return;
2025}
2026
2027static void
2028avr32dci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc,
2029 struct usb_endpoint *ep)
2030{
2031 struct avr32dci_softc *sc = AVR32_BUS2SC(udev->bus);
2032
2033 DPRINTFN(2, "pipe=%p, addr=%d, endpt=%d, mode=%d (%d,%d)\n",
2034 pipe, udev->address,
2035 edesc->bEndpointAddress, udev->flags.usb_mode,
2036 sc->sc_rt_addr, udev->device_index);
2037
2038 if (udev->device_index != sc->sc_rt_addr) {
2039
2040 if (udev->flags.usb_mode != USB_MODE_DEVICE) {
2041 /* not supported */
2042 return;
2043 }
2044 if ((udev->speed != USB_SPEED_FULL) &&
2045 (udev->speed != USB_SPEED_HIGH)) {
2046 /* not supported */
2047 return;
2048 }
2049 if ((edesc->bmAttributes & UE_XFERTYPE) == UE_ISOCHRONOUS)
2050 pipe->methods = &avr32dci_device_isoc_fs_methods;
2051 else
2052 pipe->methods = &avr32dci_device_non_isoc_methods;
2053 }
2054}
2055
2056struct usb_bus_methods avr32dci_bus_methods =
2057{
2058 .endpoint_init = &avr32dci_ep_init,
2059 .xfer_setup = &avr32dci_xfer_setup,
2060 .xfer_unsetup = &avr32dci_xfer_unsetup,
2061 .get_hw_ep_profile = &avr32dci_get_hw_ep_profile,
2062 .set_stall = &avr32dci_set_stall,
2063 .clear_stall = &avr32dci_clear_stall,
2064 .roothub_exec = &avr32dci_roothub_exec,
2065};
| 1969 */
1970 if (parm->err)
1971 return;
1972
1973 /*
1974 * allocate transfer descriptors
1975 */
1976 last_obj = NULL;
1977
1978 /*
1979 * get profile stuff
1980 */
1981 ep_no = xfer->endpoint & UE_ADDR;
1982 avr32dci_get_hw_ep_profile(parm->udev, &pf, ep_no);
1983
1984 if (pf == NULL) {
1985 /* should not happen */
1986 parm->err = USB_ERR_INVAL;
1987 return;
1988 }
1989 /* align data */
1990 parm->size[0] += ((-parm->size[0]) & (USB_HOST_ALIGN - 1));
1991
1992 for (n = 0; n != ntd; n++) {
1993
1994 struct avr32dci_td *td;
1995
1996 if (parm->buf) {
1997 uint32_t temp;
1998
1999 td = USB_ADD_BYTES(parm->buf, parm->size[0]);
2000
2001 /* init TD */
2002 td->max_packet_size = xfer->max_packet_size;
2003 td->ep_no = ep_no;
2004 temp = pf->max_in_frame_size | pf->max_out_frame_size;
2005 td->bank_shift = 0;
2006 while ((temp /= 2))
2007 td->bank_shift++;
2008 if (pf->support_multi_buffer) {
2009 td->support_multi_buffer = 1;
2010 }
2011 td->obj_next = last_obj;
2012
2013 last_obj = td;
2014 }
2015 parm->size[0] += sizeof(*td);
2016 }
2017
2018 xfer->td_start[0] = last_obj;
2019}
2020
2021static void
2022avr32dci_xfer_unsetup(struct usb_xfer *xfer)
2023{
2024 return;
2025}
2026
2027static void
2028avr32dci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc,
2029 struct usb_endpoint *ep)
2030{
2031 struct avr32dci_softc *sc = AVR32_BUS2SC(udev->bus);
2032
2033 DPRINTFN(2, "pipe=%p, addr=%d, endpt=%d, mode=%d (%d,%d)\n",
2034 pipe, udev->address,
2035 edesc->bEndpointAddress, udev->flags.usb_mode,
2036 sc->sc_rt_addr, udev->device_index);
2037
2038 if (udev->device_index != sc->sc_rt_addr) {
2039
2040 if (udev->flags.usb_mode != USB_MODE_DEVICE) {
2041 /* not supported */
2042 return;
2043 }
2044 if ((udev->speed != USB_SPEED_FULL) &&
2045 (udev->speed != USB_SPEED_HIGH)) {
2046 /* not supported */
2047 return;
2048 }
2049 if ((edesc->bmAttributes & UE_XFERTYPE) == UE_ISOCHRONOUS)
2050 pipe->methods = &avr32dci_device_isoc_fs_methods;
2051 else
2052 pipe->methods = &avr32dci_device_non_isoc_methods;
2053 }
2054}
2055
2056struct usb_bus_methods avr32dci_bus_methods =
2057{
2058 .endpoint_init = &avr32dci_ep_init,
2059 .xfer_setup = &avr32dci_xfer_setup,
2060 .xfer_unsetup = &avr32dci_xfer_unsetup,
2061 .get_hw_ep_profile = &avr32dci_get_hw_ep_profile,
2062 .set_stall = &avr32dci_set_stall,
2063 .clear_stall = &avr32dci_clear_stall,
2064 .roothub_exec = &avr32dci_roothub_exec,
2065};
|