2/*-
3 * Copyright (c) 2009 Hans Petter Selasky. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27/*
28 * USB Device Port register definitions, copied from ATMEGA documentation
29 * provided by ATMEL.
30 */
31
32#ifndef _ATMEGADCI_H_
33#define _ATMEGADCI_H_
34
35#define ATMEGA_MAX_DEVICES (USB_MIN_DEVICES + 1)
36
37#define ATMEGA_OTGTCON 0xF9
38#define ATMEGA_OTGTCON_VALUE(x) ((x) << 0)
39#define ATMEGA_OTGTCON_PAGE(x) ((x) << 5)
40
41#define ATMEGA_UEINT 0xF4
42#define ATMEGA_UEINT_MASK(n) (1 << (n)) /* endpoint interrupt mask */
43
44#define ATMEGA_UEBCHX 0xF3 /* FIFO byte count high */
45#define ATMEGA_UEBCLX 0xF2 /* FIFO byte count low */
46#define ATMEGA_UEDATX 0xF1 /* FIFO data */
47
48#define ATMEGA_UEIENX 0xF0 /* interrupt enable register */
49#define ATMEGA_UEIENX_TXINE (1 << 0)
50#define ATMEGA_UEIENX_STALLEDE (1 << 1)
51#define ATMEGA_UEIENX_RXOUTE (1 << 2)
52#define ATMEGA_UEIENX_RXSTPE (1 << 3) /* received SETUP packet */
53#define ATMEGA_UEIENX_NAKOUTE (1 << 4)
54#define ATMEGA_UEIENX_NAKINE (1 << 6)
55#define ATMEGA_UEIENX_FLERRE (1 << 7)
56
57#define ATMEGA_UESTA1X 0xEF
58#define ATMEGA_UESTA1X_CURRBK (3 << 0) /* current bank */
59#define ATMEGA_UESTA1X_CTRLDIR (1 << 2) /* control endpoint direction */
60
61#define ATMEGA_UESTA0X 0xEE
62#define ATMEGA_UESTA0X_NBUSYBK (3 << 0)
63#define ATMEGA_UESTA0X_DTSEQ (3 << 2)
64#define ATMEGA_UESTA0X_UNDERFI (1 << 5) /* underflow */
65#define ATMEGA_UESTA0X_OVERFI (1 << 6) /* overflow */
66#define ATMEGA_UESTA0X_CFGOK (1 << 7)
67
68#define ATMEGA_UECFG1X 0xED /* endpoint config register */
69#define ATMEGA_UECFG1X_ALLOC (1 << 1)
70#define ATMEGA_UECFG1X_EPBK0 (0 << 2)
71#define ATMEGA_UECFG1X_EPBK1 (1 << 2)
72#define ATMEGA_UECFG1X_EPBK2 (2 << 2)
73#define ATMEGA_UECFG1X_EPBK3 (3 << 2)
74#define ATMEGA_UECFG1X_EPSIZE(n) ((n) << 4)
75
76#define ATMEGA_UECFG0X 0xEC
77#define ATMEGA_UECFG0X_EPDIR (1 << 0) /* endpoint direction */
78#define ATMEGA_UECFG0X_EPTYPE0 (0 << 6)
79#define ATMEGA_UECFG0X_EPTYPE1 (1 << 6)
80#define ATMEGA_UECFG0X_EPTYPE2 (2 << 6)
81#define ATMEGA_UECFG0X_EPTYPE3 (3 << 6)
82
83#define ATMEGA_UECONX 0xEB
84#define ATMEGA_UECONX_EPEN (1 << 0)
85#define ATMEGA_UECONX_RSTDT (1 << 3)
86#define ATMEGA_UECONX_STALLRQC (1 << 4) /* stall request clear */
87#define ATMEGA_UECONX_STALLRQ (1 << 5) /* stall request set */
88
89#define ATMEGA_UERST 0xEA /* endpoint reset register */
90#define ATMEGA_UERST_MASK(n) (1 << (n))
91
92#define ATMEGA_UENUM 0xE9 /* endpoint number */
93
94#define ATMEGA_UEINTX 0xE8 /* interrupt register */
95#define ATMEGA_UEINTX_TXINI (1 << 0)
96#define ATMEGA_UEINTX_STALLEDI (1 << 1)
97#define ATMEGA_UEINTX_RXOUTI (1 << 2)
98#define ATMEGA_UEINTX_RXSTPI (1 << 3) /* received setup packet */
99#define ATMEGA_UEINTX_NAKOUTI (1 << 4)
100#define ATMEGA_UEINTX_RWAL (1 << 5)
101#define ATMEGA_UEINTX_NAKINI (1 << 6)
102#define ATMEGA_UEINTX_FIFOCON (1 << 7)
103
104#define ATMEGA_UDMFN 0xE6
105#define ATMEGA_UDMFN_FNCERR (1 << 4)
106
107#define ATMEGA_UDFNUMH 0xE5 /* frame number high */
108#define ATMEGA_UDFNUMH_MASK 7
109
110#define ATMEGA_UDFNUML 0xE4 /* frame number low */
111#define ATMEGA_UDFNUML_MASK 0xFF
112
113#define ATMEGA_FRAME_MASK 0x7FF
114
115#define ATMEGA_UDADDR 0xE3 /* USB address */
116#define ATMEGA_UDADDR_MASK 0x7F
117#define ATMEGA_UDADDR_ADDEN (1 << 7)
118
119#define ATMEGA_UDIEN 0xE2 /* USB device interrupt enable */
120#define ATMEGA_UDINT_SUSPE (1 << 0)
121#define ATMEGA_UDINT_MSOFE (1 << 1)
122#define ATMEGA_UDINT_SOFE (1 << 2)
123#define ATMEGA_UDINT_EORSTE (1 << 3)
124#define ATMEGA_UDINT_WAKEUPE (1 << 4)
125#define ATMEGA_UDINT_EORSME (1 << 5)
126#define ATMEGA_UDINT_UPRSME (1 << 6)
127
128#define ATMEGA_UDINT 0xE1 /* USB device interrupt status */
129#define ATMEGA_UDINT_SUSPI (1 << 0)
130#define ATMEGA_UDINT_MSOFI (1 << 1)
131#define ATMEGA_UDINT_SOFI (1 << 2)
132#define ATMEGA_UDINT_EORSTI (1 << 3)
133#define ATMEGA_UDINT_WAKEUPI (1 << 4)
134#define ATMEGA_UDINT_EORSMI (1 << 5)
135#define ATMEGA_UDINT_UPRSMI (1 << 6)
136
137#define ATMEGA_UDCON 0xE0 /* USB device connection register */
138#define ATMEGA_UDCON_DETACH (1 << 0)
139#define ATMEGA_UDCON_RMWKUP (1 << 1)
140#define ATMEGA_UDCON_LSM (1 << 2)
141#define ATMEGA_UDCON_RSTCPU (1 << 3)
142
143#define ATMEGA_OTGINT 0xDF
144
145#define ATMEGA_OTGCON 0xDD
146#define ATMEGA_OTGCON_VBUSRQC (1 << 0)
147#define ATMEGA_OTGCON_VBUSREQ (1 << 1)
148#define ATMEGA_OTGCON_VBUSHWC (1 << 2)
149#define ATMEGA_OTGCON_SRPSEL (1 << 3)
150#define ATMEGA_OTGCON_SRPREQ (1 << 4)
151#define ATMEGA_OTGCON_HNPREQ (1 << 5)
152
153#define ATMEGA_USBINT 0xDA
154#define ATMEGA_USBINT_VBUSTI (1 << 0) /* USB VBUS interrupt */
155#define ATMEGA_USBINT_IDI (1 << 1) /* USB ID interrupt */
156
157#define ATMEGA_USBSTA 0xD9
158#define ATMEGA_USBSTA_VBUS (1 << 0)
159#define ATMEGA_USBSTA_ID (1 << 1)
160
161#define ATMEGA_USBCON 0xD8
162#define ATMEGA_USBCON_VBUSTE (1 << 0)
163#define ATMEGA_USBCON_IDE (1 << 1)
164#define ATMEGA_USBCON_OTGPADE (1 << 4)
165#define ATMEGA_USBCON_FRZCLK (1 << 5)
166#define ATMEGA_USBCON_USBE (1 << 7)
167
168#define ATMEGA_UHWCON 0xD7
169#define ATMEGA_UHWCON_UVREGE (1 << 0)
170#define ATMEGA_UHWCON_UVCONE (1 << 4)
171#define ATMEGA_UHWCON_UIDE (1 << 6)
172#define ATMEGA_UHWCON_UIMOD (1 << 7)
173
174#define ATMEGA_READ_1(sc, reg) \
175 bus_space_read_1((sc)->sc_io_tag, (sc)->sc_io_hdl, reg)
176
177#define ATMEGA_WRITE_1(sc, reg, data) \
178 bus_space_write_1((sc)->sc_io_tag, (sc)->sc_io_hdl, reg, data)
179
180#define ATMEGA_WRITE_MULTI_1(sc, reg, ptr, len) \
181 bus_space_write_multi_1((sc)->sc_io_tag, (sc)->sc_io_hdl, reg, ptr, len)
182
183#define ATMEGA_READ_MULTI_1(sc, reg, ptr, len) \
184 bus_space_read_multi_1((sc)->sc_io_tag, (sc)->sc_io_hdl, reg, ptr, len)
185
186/*
187 * Maximum number of endpoints supported:
188 */
189#define ATMEGA_EP_MAX 7
190
191struct atmegadci_td;
192
193typedef uint8_t (atmegadci_cmd_t)(struct atmegadci_td *td);
194typedef void (atmegadci_clocks_t)(struct usb_bus *);
195
196struct atmegadci_td {
197 struct atmegadci_td *obj_next;
198 atmegadci_cmd_t *func;
199 struct usb_page_cache *pc;
200 uint32_t offset;
201 uint32_t remainder;
202 uint16_t max_packet_size;
203 uint8_t error:1;
204 uint8_t alt_next:1;
205 uint8_t short_pkt:1;
206 uint8_t support_multi_buffer:1;
207 uint8_t did_stall:1;
208 uint8_t ep_no:3;
209};
210
211struct atmegadci_std_temp {
212 atmegadci_cmd_t *func;
213 struct usb_page_cache *pc;
214 struct atmegadci_td *td;
215 struct atmegadci_td *td_next;
216 uint32_t len;
217 uint32_t offset;
218 uint16_t max_frame_size;
219 uint8_t short_pkt;
220 /*
221 * short_pkt = 0: transfer should be short terminated
222 * short_pkt = 1: transfer should not be short terminated
223 */
224 uint8_t setup_alt_next;
225 uint8_t did_stall;
226};
227
228struct atmegadci_config_desc {
229 struct usb_config_descriptor confd;
230 struct usb_interface_descriptor ifcd;
231 struct usb_endpoint_descriptor endpd;
232} __packed;
233
234union atmegadci_hub_temp {
235 uWord wValue;
236 struct usb_port_status ps;
237};
238
239struct atmegadci_flags {
240 uint8_t change_connect:1;
241 uint8_t change_suspend:1;
242 uint8_t status_suspend:1; /* set if suspended */
243 uint8_t status_vbus:1; /* set if present */
244 uint8_t status_bus_reset:1; /* set if reset complete */
245 uint8_t remote_wakeup:1;
246 uint8_t self_powered:1;
247 uint8_t clocks_off:1;
248 uint8_t port_powered:1;
249 uint8_t port_enabled:1;
250 uint8_t d_pulled_up:1;
251};
252
253struct atmegadci_softc {
254 struct usb_bus sc_bus;
255 union atmegadci_hub_temp sc_hub_temp;
256
257 /* must be set by by the bus interface layer */
258 atmegadci_clocks_t *sc_clocks_on;
259 atmegadci_clocks_t *sc_clocks_off;
260
261 struct usb_device *sc_devices[ATMEGA_MAX_DEVICES];
262 struct resource *sc_irq_res;
263 void *sc_intr_hdl;
264 struct resource *sc_io_res;
265 bus_space_tag_t sc_io_tag;
266 bus_space_handle_t sc_io_hdl;
267
268 uint8_t sc_rt_addr; /* root hub address */
269 uint8_t sc_dv_addr; /* device address */
270 uint8_t sc_conf; /* root hub config */
271
272 uint8_t sc_hub_idata[1];
273
274 struct atmegadci_flags sc_flags;
275};
276
277/* prototypes */
278
279usb_error_t atmegadci_init(struct atmegadci_softc *sc);
280void atmegadci_uninit(struct atmegadci_softc *sc);
| 2/*-
3 * Copyright (c) 2009 Hans Petter Selasky. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27/*
28 * USB Device Port register definitions, copied from ATMEGA documentation
29 * provided by ATMEL.
30 */
31
32#ifndef _ATMEGADCI_H_
33#define _ATMEGADCI_H_
34
35#define ATMEGA_MAX_DEVICES (USB_MIN_DEVICES + 1)
36
37#define ATMEGA_OTGTCON 0xF9
38#define ATMEGA_OTGTCON_VALUE(x) ((x) << 0)
39#define ATMEGA_OTGTCON_PAGE(x) ((x) << 5)
40
41#define ATMEGA_UEINT 0xF4
42#define ATMEGA_UEINT_MASK(n) (1 << (n)) /* endpoint interrupt mask */
43
44#define ATMEGA_UEBCHX 0xF3 /* FIFO byte count high */
45#define ATMEGA_UEBCLX 0xF2 /* FIFO byte count low */
46#define ATMEGA_UEDATX 0xF1 /* FIFO data */
47
48#define ATMEGA_UEIENX 0xF0 /* interrupt enable register */
49#define ATMEGA_UEIENX_TXINE (1 << 0)
50#define ATMEGA_UEIENX_STALLEDE (1 << 1)
51#define ATMEGA_UEIENX_RXOUTE (1 << 2)
52#define ATMEGA_UEIENX_RXSTPE (1 << 3) /* received SETUP packet */
53#define ATMEGA_UEIENX_NAKOUTE (1 << 4)
54#define ATMEGA_UEIENX_NAKINE (1 << 6)
55#define ATMEGA_UEIENX_FLERRE (1 << 7)
56
57#define ATMEGA_UESTA1X 0xEF
58#define ATMEGA_UESTA1X_CURRBK (3 << 0) /* current bank */
59#define ATMEGA_UESTA1X_CTRLDIR (1 << 2) /* control endpoint direction */
60
61#define ATMEGA_UESTA0X 0xEE
62#define ATMEGA_UESTA0X_NBUSYBK (3 << 0)
63#define ATMEGA_UESTA0X_DTSEQ (3 << 2)
64#define ATMEGA_UESTA0X_UNDERFI (1 << 5) /* underflow */
65#define ATMEGA_UESTA0X_OVERFI (1 << 6) /* overflow */
66#define ATMEGA_UESTA0X_CFGOK (1 << 7)
67
68#define ATMEGA_UECFG1X 0xED /* endpoint config register */
69#define ATMEGA_UECFG1X_ALLOC (1 << 1)
70#define ATMEGA_UECFG1X_EPBK0 (0 << 2)
71#define ATMEGA_UECFG1X_EPBK1 (1 << 2)
72#define ATMEGA_UECFG1X_EPBK2 (2 << 2)
73#define ATMEGA_UECFG1X_EPBK3 (3 << 2)
74#define ATMEGA_UECFG1X_EPSIZE(n) ((n) << 4)
75
76#define ATMEGA_UECFG0X 0xEC
77#define ATMEGA_UECFG0X_EPDIR (1 << 0) /* endpoint direction */
78#define ATMEGA_UECFG0X_EPTYPE0 (0 << 6)
79#define ATMEGA_UECFG0X_EPTYPE1 (1 << 6)
80#define ATMEGA_UECFG0X_EPTYPE2 (2 << 6)
81#define ATMEGA_UECFG0X_EPTYPE3 (3 << 6)
82
83#define ATMEGA_UECONX 0xEB
84#define ATMEGA_UECONX_EPEN (1 << 0)
85#define ATMEGA_UECONX_RSTDT (1 << 3)
86#define ATMEGA_UECONX_STALLRQC (1 << 4) /* stall request clear */
87#define ATMEGA_UECONX_STALLRQ (1 << 5) /* stall request set */
88
89#define ATMEGA_UERST 0xEA /* endpoint reset register */
90#define ATMEGA_UERST_MASK(n) (1 << (n))
91
92#define ATMEGA_UENUM 0xE9 /* endpoint number */
93
94#define ATMEGA_UEINTX 0xE8 /* interrupt register */
95#define ATMEGA_UEINTX_TXINI (1 << 0)
96#define ATMEGA_UEINTX_STALLEDI (1 << 1)
97#define ATMEGA_UEINTX_RXOUTI (1 << 2)
98#define ATMEGA_UEINTX_RXSTPI (1 << 3) /* received setup packet */
99#define ATMEGA_UEINTX_NAKOUTI (1 << 4)
100#define ATMEGA_UEINTX_RWAL (1 << 5)
101#define ATMEGA_UEINTX_NAKINI (1 << 6)
102#define ATMEGA_UEINTX_FIFOCON (1 << 7)
103
104#define ATMEGA_UDMFN 0xE6
105#define ATMEGA_UDMFN_FNCERR (1 << 4)
106
107#define ATMEGA_UDFNUMH 0xE5 /* frame number high */
108#define ATMEGA_UDFNUMH_MASK 7
109
110#define ATMEGA_UDFNUML 0xE4 /* frame number low */
111#define ATMEGA_UDFNUML_MASK 0xFF
112
113#define ATMEGA_FRAME_MASK 0x7FF
114
115#define ATMEGA_UDADDR 0xE3 /* USB address */
116#define ATMEGA_UDADDR_MASK 0x7F
117#define ATMEGA_UDADDR_ADDEN (1 << 7)
118
119#define ATMEGA_UDIEN 0xE2 /* USB device interrupt enable */
120#define ATMEGA_UDINT_SUSPE (1 << 0)
121#define ATMEGA_UDINT_MSOFE (1 << 1)
122#define ATMEGA_UDINT_SOFE (1 << 2)
123#define ATMEGA_UDINT_EORSTE (1 << 3)
124#define ATMEGA_UDINT_WAKEUPE (1 << 4)
125#define ATMEGA_UDINT_EORSME (1 << 5)
126#define ATMEGA_UDINT_UPRSME (1 << 6)
127
128#define ATMEGA_UDINT 0xE1 /* USB device interrupt status */
129#define ATMEGA_UDINT_SUSPI (1 << 0)
130#define ATMEGA_UDINT_MSOFI (1 << 1)
131#define ATMEGA_UDINT_SOFI (1 << 2)
132#define ATMEGA_UDINT_EORSTI (1 << 3)
133#define ATMEGA_UDINT_WAKEUPI (1 << 4)
134#define ATMEGA_UDINT_EORSMI (1 << 5)
135#define ATMEGA_UDINT_UPRSMI (1 << 6)
136
137#define ATMEGA_UDCON 0xE0 /* USB device connection register */
138#define ATMEGA_UDCON_DETACH (1 << 0)
139#define ATMEGA_UDCON_RMWKUP (1 << 1)
140#define ATMEGA_UDCON_LSM (1 << 2)
141#define ATMEGA_UDCON_RSTCPU (1 << 3)
142
143#define ATMEGA_OTGINT 0xDF
144
145#define ATMEGA_OTGCON 0xDD
146#define ATMEGA_OTGCON_VBUSRQC (1 << 0)
147#define ATMEGA_OTGCON_VBUSREQ (1 << 1)
148#define ATMEGA_OTGCON_VBUSHWC (1 << 2)
149#define ATMEGA_OTGCON_SRPSEL (1 << 3)
150#define ATMEGA_OTGCON_SRPREQ (1 << 4)
151#define ATMEGA_OTGCON_HNPREQ (1 << 5)
152
153#define ATMEGA_USBINT 0xDA
154#define ATMEGA_USBINT_VBUSTI (1 << 0) /* USB VBUS interrupt */
155#define ATMEGA_USBINT_IDI (1 << 1) /* USB ID interrupt */
156
157#define ATMEGA_USBSTA 0xD9
158#define ATMEGA_USBSTA_VBUS (1 << 0)
159#define ATMEGA_USBSTA_ID (1 << 1)
160
161#define ATMEGA_USBCON 0xD8
162#define ATMEGA_USBCON_VBUSTE (1 << 0)
163#define ATMEGA_USBCON_IDE (1 << 1)
164#define ATMEGA_USBCON_OTGPADE (1 << 4)
165#define ATMEGA_USBCON_FRZCLK (1 << 5)
166#define ATMEGA_USBCON_USBE (1 << 7)
167
168#define ATMEGA_UHWCON 0xD7
169#define ATMEGA_UHWCON_UVREGE (1 << 0)
170#define ATMEGA_UHWCON_UVCONE (1 << 4)
171#define ATMEGA_UHWCON_UIDE (1 << 6)
172#define ATMEGA_UHWCON_UIMOD (1 << 7)
173
174#define ATMEGA_READ_1(sc, reg) \
175 bus_space_read_1((sc)->sc_io_tag, (sc)->sc_io_hdl, reg)
176
177#define ATMEGA_WRITE_1(sc, reg, data) \
178 bus_space_write_1((sc)->sc_io_tag, (sc)->sc_io_hdl, reg, data)
179
180#define ATMEGA_WRITE_MULTI_1(sc, reg, ptr, len) \
181 bus_space_write_multi_1((sc)->sc_io_tag, (sc)->sc_io_hdl, reg, ptr, len)
182
183#define ATMEGA_READ_MULTI_1(sc, reg, ptr, len) \
184 bus_space_read_multi_1((sc)->sc_io_tag, (sc)->sc_io_hdl, reg, ptr, len)
185
186/*
187 * Maximum number of endpoints supported:
188 */
189#define ATMEGA_EP_MAX 7
190
191struct atmegadci_td;
192
193typedef uint8_t (atmegadci_cmd_t)(struct atmegadci_td *td);
194typedef void (atmegadci_clocks_t)(struct usb_bus *);
195
196struct atmegadci_td {
197 struct atmegadci_td *obj_next;
198 atmegadci_cmd_t *func;
199 struct usb_page_cache *pc;
200 uint32_t offset;
201 uint32_t remainder;
202 uint16_t max_packet_size;
203 uint8_t error:1;
204 uint8_t alt_next:1;
205 uint8_t short_pkt:1;
206 uint8_t support_multi_buffer:1;
207 uint8_t did_stall:1;
208 uint8_t ep_no:3;
209};
210
211struct atmegadci_std_temp {
212 atmegadci_cmd_t *func;
213 struct usb_page_cache *pc;
214 struct atmegadci_td *td;
215 struct atmegadci_td *td_next;
216 uint32_t len;
217 uint32_t offset;
218 uint16_t max_frame_size;
219 uint8_t short_pkt;
220 /*
221 * short_pkt = 0: transfer should be short terminated
222 * short_pkt = 1: transfer should not be short terminated
223 */
224 uint8_t setup_alt_next;
225 uint8_t did_stall;
226};
227
228struct atmegadci_config_desc {
229 struct usb_config_descriptor confd;
230 struct usb_interface_descriptor ifcd;
231 struct usb_endpoint_descriptor endpd;
232} __packed;
233
234union atmegadci_hub_temp {
235 uWord wValue;
236 struct usb_port_status ps;
237};
238
239struct atmegadci_flags {
240 uint8_t change_connect:1;
241 uint8_t change_suspend:1;
242 uint8_t status_suspend:1; /* set if suspended */
243 uint8_t status_vbus:1; /* set if present */
244 uint8_t status_bus_reset:1; /* set if reset complete */
245 uint8_t remote_wakeup:1;
246 uint8_t self_powered:1;
247 uint8_t clocks_off:1;
248 uint8_t port_powered:1;
249 uint8_t port_enabled:1;
250 uint8_t d_pulled_up:1;
251};
252
253struct atmegadci_softc {
254 struct usb_bus sc_bus;
255 union atmegadci_hub_temp sc_hub_temp;
256
257 /* must be set by by the bus interface layer */
258 atmegadci_clocks_t *sc_clocks_on;
259 atmegadci_clocks_t *sc_clocks_off;
260
261 struct usb_device *sc_devices[ATMEGA_MAX_DEVICES];
262 struct resource *sc_irq_res;
263 void *sc_intr_hdl;
264 struct resource *sc_io_res;
265 bus_space_tag_t sc_io_tag;
266 bus_space_handle_t sc_io_hdl;
267
268 uint8_t sc_rt_addr; /* root hub address */
269 uint8_t sc_dv_addr; /* device address */
270 uint8_t sc_conf; /* root hub config */
271
272 uint8_t sc_hub_idata[1];
273
274 struct atmegadci_flags sc_flags;
275};
276
277/* prototypes */
278
279usb_error_t atmegadci_init(struct atmegadci_softc *sc);
280void atmegadci_uninit(struct atmegadci_softc *sc);
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