Cross Reference: /freebsd-11.0-release/sys/dev/urtwn/if_urtwnreg.h

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if_urtwnreg.h (300433)	if_urtwnreg.h (300754)
1/- 2 Copyright (c) 2010 Damien Bergamini <damien.bergamini@free.fr> 3 * 4 * Permission to use, copy, modify, and distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 * 16 * $OpenBSD: if_urtwnreg.h,v 1.3 2010/11/16 18:02:59 damien Exp $	1/- 2 Copyright (c) 2010 Damien Bergamini <damien.bergamini@free.fr> 3 * 4 * Permission to use, copy, modify, and distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 * 16 * $OpenBSD: if_urtwnreg.h,v 1.3 2010/11/16 18:02:59 damien Exp $
17 * $FreeBSD: head/sys/dev/urtwn/if_urtwnreg.h 300433 2016-05-22 19:43:40Z avos $	17 * $FreeBSD: head/sys/dev/urtwn/if_urtwnreg.h 300754 2016-05-26 16:39:11Z avos $
18 / 19 20#define URTWN_CONFIG_INDEX 0 21#define URTWN_IFACE_INDEX 0 22 23#define URTWN_NOISE_FLOOR -95 24 25#define R92C_MAX_CHAINS 2 26 27/ Maximum number of output pipes is 3. / 28#define R92C_MAX_EPOUT 3 29 30#define R92C_MAX_TX_PWR 0x3f 31 32#define R92C_PUBQ_NPAGES 231 33#define R92C_TXPKTBUF_COUNT 256 34#define R92C_TX_PAGE_COUNT 248 35#define R92C_TX_PAGE_BOUNDARY (R92C_TX_PAGE_COUNT + 1) 36#define R88E_TXPKTBUF_COUNT 177 37#define R88E_TX_PAGE_COUNT 169 38#define R88E_TX_PAGE_BOUNDARY (R88E_TX_PAGE_COUNT + 1) 39 40#define R92C_H2C_NBOX 4 41 42/ USB Requests. / 43#define R92C_REQ_REGS 0x05 44 45/ 46 * MAC registers. 47 / 48/ System Configuration. / 49#define R92C_SYS_ISO_CTRL 0x000 50#define R92C_SYS_FUNC_EN 0x002 51#define R92C_APS_FSMCO 0x004 52#define R92C_SYS_CLKR 0x008 53#define R92C_AFE_MISC 0x010 54#define R92C_SPS0_CTRL 0x011 55#define R92C_SPS_OCP_CFG 0x018 56#define R92C_RSV_CTRL 0x01c 57#define R92C_RF_CTRL 0x01f 58#define R92C_LDOA15_CTRL 0x020 59#define R92C_LDOV12D_CTRL 0x021 60#define R92C_LDOHCI12_CTRL 0x022 61#define R92C_LPLDO_CTRL 0x023 62#define R92C_AFE_XTAL_CTRL 0x024 63#define R92C_AFE_PLL_CTRL 0x028 64#define R92C_EFUSE_CTRL 0x030 65#define R92C_EFUSE_TEST 0x034 66#define R92C_PWR_DATA 0x038 67#define R92C_CAL_TIMER 0x03c 68#define R92C_ACLK_MON 0x03e 69#define R92C_GPIO_MUXCFG 0x040 70#define R92C_GPIO_IO_SEL 0x042 71#define R92C_MAC_PINMUX_CFG 0x043 72#define R92C_GPIO_PIN_CTRL 0x044 73#define R92C_GPIO_IN 0x044 74#define R92C_GPIO_OUT 0x045 75#define R92C_GPIO_IOSEL 0x046 76#define R92C_GPIO_MOD 0x047 77#define R92C_GPIO_INTM 0x048 78#define R92C_LEDCFG0 0x04c 79#define R92C_LEDCFG1 0x04d 80#define R92C_LEDCFG2 0x04e 81#define R92C_LEDCFG3 0x04f 82#define R92C_FSIMR 0x050 83#define R92C_FSISR 0x054 84#define R92C_HSIMR 0x058 85#define R92C_HSISR 0x05c 86#define R88E_BB_PAD_CTRL 0x064 87#define R92C_MCUFWDL 0x080 88#define R92C_HMEBOX_EXT(idx) (0x088 + (idx) 2) 89#define R88E_HIMR 0x0b0 90#define R88E_HISR 0x0b4 91#define R88E_HIMRE 0x0b8 92#define R88E_HISRE 0x0bc 93#define R92C_EFUSE_ACCESS 0x0cf 94#define R92C_BIST_SCAN 0x0d0 95#define R92C_BIST_RPT 0x0d4 96#define R92C_BIST_ROM_RPT 0x0d8 97#define R92C_USB_SIE_INTF 0x0e0 98#define R92C_PCIE_MIO_INTF 0x0e4 99#define R92C_PCIE_MIO_INTD 0x0e8 100#define R92C_HPON_FSM 0x0ec 101#define R92C_SYS_CFG 0x0f0 102/* MAC General Configuration. / 103#define R92C_CR 0x100 104#define R92C_MSR 0x102 105#define R92C_PBP 0x104 106#define R92C_TRXDMA_CTRL 0x10c 107#define R92C_TRXFF_BNDY 0x114 108#define R92C_TRXFF_STATUS 0x118 109#define R92C_RXFF_PTR 0x11c 110#define R92C_HIMR 0x120 111#define R92C_HISR 0x124 112#define R92C_HIMRE 0x128 113#define R92C_HISRE 0x12c 114#define R92C_CPWM 0x12f 115#define R92C_FWIMR 0x130 116#define R92C_FWISR 0x134 117#define R92C_PKTBUF_DBG_CTRL 0x140 118#define R92C_PKTBUF_DBG_DATA_L 0x144 119#define R92C_PKTBUF_DBG_DATA_H 0x148 120#define R92C_TC0_CTRL(i) (0x150 + (i) 4) 121#define R92C_TCUNIT_BASE 0x164 122#define R92C_MBIST_START 0x174 123#define R92C_MBIST_DONE 0x178 124#define R92C_MBIST_FAIL 0x17c 125#define R88E_32K_CTRL 0x194 126#define R92C_C2HEVT_MSG_NORMAL 0x1a0 127#define R92C_C2HEVT_MSG_TEST 0x1b8 128#define R92C_C2HEVT_CLEAR 0x1bf 129#define R92C_MCUTST_1 0x1c0 130#define R92C_FMETHR 0x1c8 131#define R92C_HMETFR 0x1cc 132#define R92C_HMEBOX(idx) (0x1d0 + (idx) * 4) 133#define R92C_LLT_INIT 0x1e0 134#define R92C_BB_ACCESS_CTRL 0x1e8 135#define R92C_BB_ACCESS_DATA 0x1ec 136#define R88E_HMEBOX_EXT(idx) (0x1f0 + (idx) * 4) 137/* Tx DMA Configuration. / 138#define R92C_RQPN 0x200 139#define R92C_FIFOPAGE 0x204 140#define R92C_TDECTRL 0x208 141#define R92C_TXDMA_OFFSET_CHK 0x20c 142#define R92C_TXDMA_STATUS 0x210 143#define R92C_RQPN_NPQ 0x214 144/ Rx DMA Configuration. / 145#define R92C_RXDMA_AGG_PG_TH 0x280 146#define R92C_RXPKT_NUM 0x284 147#define R92C_RXDMA_STATUS 0x288 148/ Protocol Configuration. / 149#define R92C_FWHW_TXQ_CTRL 0x420 150#define R92C_HWSEQ_CTRL 0x423 151#define R92C_TXPKTBUF_BCNQ_BDNY 0x424 152#define R92C_TXPKTBUF_MGQ_BDNY 0x425 153#define R92C_SPEC_SIFS 0x428 154#define R92C_RL 0x42a 155#define R92C_DARFRC 0x430 156#define R92C_RARFRC 0x438 157#define R92C_RRSR 0x440 158#define R92C_ARFR(i) (0x444 + (i) 4) 159#define R92C_AGGLEN_LMT 0x458 160#define R92C_AMPDU_MIN_SPACE 0x45c 161#define R92C_TXPKTBUF_WMAC_LBK_BF_HD 0x45d 162#define R92C_FAST_EDCA_CTRL 0x460 163#define R92C_RD_RESP_PKT_TH 0x463 164#define R92C_INIRTS_RATE_SEL 0x480 165#define R92C_INIDATA_RATE_SEL(macid) (0x484 + (macid)) 166#define R92C_MAX_AGGR_NUM 0x4ca 167#define R88E_TX_RPT_CTRL 0x4ec 168#define R88E_TX_RPT_MACID_MAX 0x4ed 169#define R88E_TX_RPT_TIME 0x4f0 170/* EDCA Configuration. / 171#define R92C_EDCA_VO_PARAM 0x500 172#define R92C_EDCA_VI_PARAM 0x504 173#define R92C_EDCA_BE_PARAM 0x508 174#define R92C_EDCA_BK_PARAM 0x50c 175#define R92C_BCNTCFG 0x510 176#define R92C_PIFS 0x512 177#define R92C_RDG_PIFS 0x513 178#define R92C_SIFS_CCK 0x514 179#define R92C_SIFS_OFDM 0x516 180#define R92C_AGGR_BREAK_TIME 0x51a 181#define R92C_SLOT 0x51b 182#define R92C_TX_PTCL_CTRL 0x520 183#define R92C_TXPAUSE 0x522 184#define R92C_DIS_TXREQ_CLR 0x523 185#define R92C_RD_CTRL 0x524 186#define R92C_TBTT_PROHIBIT 0x540 187#define R92C_RD_NAV_NXT 0x544 188#define R92C_NAV_PROT_LEN 0x546 189#define R92C_BCN_CTRL 0x550 190#define R92C_MBID_NUM 0x552 191#define R92C_DUAL_TSF_RST 0x553 192#define R92C_BCN_INTERVAL 0x554 193#define R92C_DRVERLYINT 0x558 194#define R92C_BCNDMATIM 0x559 195#define R92C_ATIMWND 0x55a 196#define R92C_USTIME_TSF 0x55c 197#define R92C_BCN_MAX_ERR 0x55d 198#define R92C_RXTSF_OFFSET_CCK 0x55e 199#define R92C_RXTSF_OFFSET_OFDM 0x55f 200#define R92C_TSFTR 0x560 201#define R92C_INIT_TSFTR 0x564 202#define R92C_PSTIMER 0x580 203#define R92C_TIMER0 0x584 204#define R92C_TIMER1 0x588 205#define R92C_ACMHWCTRL 0x5c0 206#define R92C_ACMRSTCTRL 0x5c1 207#define R92C_ACMAVG 0x5c2 208#define R92C_VO_ADMTIME 0x5c4 209#define R92C_VI_ADMTIME 0x5c6 210#define R92C_BE_ADMTIME 0x5c8 211#define R92C_EDCA_RANDOM_GEN 0x5cc 212#define R92C_SCH_TXCMD 0x5d0 213#define R88E_SCH_TXCMD 0x5f8 214/ WMAC Configuration. / 215#define R92C_APSD_CTRL 0x600 216#define R92C_BWOPMODE 0x603 217#define R92C_RCR 0x608 218#define R92C_RX_DRVINFO_SZ 0x60f 219#define R92C_MACID 0x610 220#define R92C_BSSID 0x618 221#define R92C_MAR 0x620 222#define R92C_MAC_SPEC_SIFS 0x63a 223#define R92C_R2T_SIFS 0x63c 224#define R92C_T2T_SIFS 0x63e 225#define R92C_ACKTO 0x640 226#define R92C_CAMCMD 0x670 227#define R92C_CAMWRITE 0x674 228#define R92C_CAMREAD 0x678 229#define R92C_CAMDBG 0x67c 230#define R92C_SECCFG 0x680 231#define R92C_RXFLTMAP0 0x6a0 232#define R92C_RXFLTMAP1 0x6a2 233#define R92C_RXFLTMAP2 0x6a4 234* 235/* Bits for R92C_SYS_ISO_CTRL. / 236#define R92C_SYS_ISO_CTRL_MD2PP 0x0001 237#define R92C_SYS_ISO_CTRL_UA2USB 0x0002 238#define R92C_SYS_ISO_CTRL_UD2CORE 0x0004 239#define R92C_SYS_ISO_CTRL_PA2PCIE 0x0008 240#define R92C_SYS_ISO_CTRL_PD2CORE 0x0010 241#define R92C_SYS_ISO_CTRL_IP2MAC 0x0020 242#define R92C_SYS_ISO_CTRL_DIOP 0x0040 243#define R92C_SYS_ISO_CTRL_DIOE 0x0080 244#define R92C_SYS_ISO_CTRL_EB2CORE 0x0100 245#define R92C_SYS_ISO_CTRL_DIOR 0x0200 246#define R92C_SYS_ISO_CTRL_PWC_EV25V 0x4000 247#define R92C_SYS_ISO_CTRL_PWC_EV12V 0x8000 248* 249/* Bits for R92C_SYS_FUNC_EN. / 250#define R92C_SYS_FUNC_EN_BBRSTB 0x0001 251#define R92C_SYS_FUNC_EN_BB_GLB_RST 0x0002 252#define R92C_SYS_FUNC_EN_USBA 0x0004 253#define R92C_SYS_FUNC_EN_UPLL 0x0008 254#define R92C_SYS_FUNC_EN_USBD 0x0010 255#define R92C_SYS_FUNC_EN_DIO_PCIE 0x0020 256#define R92C_SYS_FUNC_EN_PCIEA 0x0040 257#define R92C_SYS_FUNC_EN_PPLL 0x0080 258#define R92C_SYS_FUNC_EN_PCIED 0x0100 259#define R92C_SYS_FUNC_EN_DIOE 0x0200 260#define R92C_SYS_FUNC_EN_CPUEN 0x0400 261#define R92C_SYS_FUNC_EN_DCORE 0x0800 262#define R92C_SYS_FUNC_EN_ELDR 0x1000 263#define R92C_SYS_FUNC_EN_DIO_RF 0x2000 264#define R92C_SYS_FUNC_EN_HWPDN 0x4000 265#define R92C_SYS_FUNC_EN_MREGEN 0x8000 266* 267/* Bits for R92C_APS_FSMCO. / 268#define R92C_APS_FSMCO_PFM_LDALL 0x00000001 269#define R92C_APS_FSMCO_PFM_ALDN 0x00000002 270#define R92C_APS_FSMCO_PFM_LDKP 0x00000004 271#define R92C_APS_FSMCO_PFM_WOWL 0x00000008 272#define R92C_APS_FSMCO_PDN_EN 0x00000010 273#define R92C_APS_FSMCO_PDN_PL 0x00000020 274#define R92C_APS_FSMCO_APFM_ONMAC 0x00000100 275#define R92C_APS_FSMCO_APFM_OFF 0x00000200 276#define R92C_APS_FSMCO_APFM_RSM 0x00000400 277#define R92C_APS_FSMCO_AFSM_HSUS 0x00000800 278#define R92C_APS_FSMCO_AFSM_PCIE 0x00001000 279#define R92C_APS_FSMCO_APDM_MAC 0x00002000 280#define R92C_APS_FSMCO_APDM_HOST 0x00004000 281#define R92C_APS_FSMCO_APDM_HPDN 0x00008000 282#define R92C_APS_FSMCO_RDY_MACON 0x00010000 283#define R92C_APS_FSMCO_SUS_HOST 0x00020000 284#define R92C_APS_FSMCO_ROP_ALD 0x00100000 285#define R92C_APS_FSMCO_ROP_PWR 0x00200000 286#define R92C_APS_FSMCO_ROP_SPS 0x00400000 287#define R92C_APS_FSMCO_SOP_MRST 0x02000000 288#define R92C_APS_FSMCO_SOP_FUSE 0x04000000 289#define R92C_APS_FSMCO_SOP_ABG 0x08000000 290#define R92C_APS_FSMCO_SOP_AMB 0x10000000 291#define R92C_APS_FSMCO_SOP_RCK 0x20000000 292#define R92C_APS_FSMCO_SOP_A8M 0x40000000 293#define R92C_APS_FSMCO_XOP_BTCK 0x80000000 294* 295/* Bits for R92C_SYS_CLKR. / 296#define R92C_SYS_CLKR_ANAD16V_EN 0x00000001 297#define R92C_SYS_CLKR_ANA8M 0x00000002 298#define R92C_SYS_CLKR_MACSLP 0x00000010 299#define R92C_SYS_CLKR_LOADER_EN 0x00000020 300#define R92C_SYS_CLKR_80M_SSC_DIS 0x00000080 301#define R92C_SYS_CLKR_80M_SSC_EN_HO 0x00000100 302#define R92C_SYS_CLKR_PHY_SSC_RSTB 0x00000200 303#define R92C_SYS_CLKR_SEC_EN 0x00000400 304#define R92C_SYS_CLKR_MAC_EN 0x00000800 305#define R92C_SYS_CLKR_SYS_EN 0x00001000 306#define R92C_SYS_CLKR_RING_EN 0x00002000 307* 308/* Bits for R92C_RF_CTRL. / 309#define R92C_RF_CTRL_EN 0x01 310#define R92C_RF_CTRL_RSTB 0x02 311#define R92C_RF_CTRL_SDMRSTB 0x04 312* 313/* Bits for R92C_LDOA15_CTRL. / 314#define R92C_LDOA15_CTRL_EN 0x01 315#define R92C_LDOA15_CTRL_STBY 0x02 316#define R92C_LDOA15_CTRL_OBUF 0x04 317#define R92C_LDOA15_CTRL_REG_VOS 0x08 318* 319/* Bits for R92C_LDOV12D_CTRL. / 320#define R92C_LDOV12D_CTRL_LDV12_EN 0x01 321* 322/* Bits for R92C_LPLDO_CTRL. / 323#define R92C_LPLDO_CTRL_SLEEP 0x10 324* 325/* Bits for R92C_AFE_XTAL_CTRL. / 326#define R92C_AFE_XTAL_CTRL_ADDR_M 0x007ff800 327#define R92C_AFE_XTAL_CTRL_ADDR_S 11 328* 329/* Bits for R92C_AFE_PLL_CTRL. / 330#define R92C_AFE_PLL_CTRL_EN 0x0001 331#define R92C_AFE_PLL_CTRL_320_EN 0x0002 332#define R92C_AFE_PLL_CTRL_FREF_SEL 0x0004 333#define R92C_AFE_PLL_CTRL_EDGE_SEL 0x0008 334#define R92C_AFE_PLL_CTRL_WDOGB 0x0010 335#define R92C_AFE_PLL_CTRL_LPFEN 0x0020 336* 337/* Bits for R92C_EFUSE_CTRL. / 338#define R92C_EFUSE_CTRL_DATA_M 0x000000ff 339#define R92C_EFUSE_CTRL_DATA_S 0 340#define R92C_EFUSE_CTRL_ADDR_M 0x0003ff00 341#define R92C_EFUSE_CTRL_ADDR_S 8 342#define R92C_EFUSE_CTRL_VALID 0x80000000 343* 344/* Bits for R92C_GPIO_MUXCFG. / 345#define R92C_GPIO_MUXCFG_ENBT 0x0020 346* 347/* Bits for R92C_LEDCFG0. / 348#define R92C_LEDCFG0_DIS 0x08 349* 350/* Bits for R92C_MCUFWDL. / 351#define R92C_MCUFWDL_EN 0x00000001 352#define R92C_MCUFWDL_RDY 0x00000002 353#define R92C_MCUFWDL_CHKSUM_RPT 0x00000004 354#define R92C_MCUFWDL_MACINI_RDY 0x00000008 355#define R92C_MCUFWDL_BBINI_RDY 0x00000010 356#define R92C_MCUFWDL_RFINI_RDY 0x00000020 357#define R92C_MCUFWDL_WINTINI_RDY 0x00000040 358#define R92C_MCUFWDL_RAM_DL_SEL 0x00000080 359#define R92C_MCUFWDL_PAGE_M 0x00070000 360#define R92C_MCUFWDL_PAGE_S 16 361#define R92C_MCUFWDL_CPRST 0x00800000 362* 363/* Bits for R88E_HIMR. / 364#define R88E_HIMR_CPWM 0x00000100 365#define R88E_HIMR_CPWM2 0x00000200 366#define R88E_HIMR_TBDER 0x04000000 367#define R88E_HIMR_PSTIMEOUT 0x20000000 368* 369/* Bits for R88E_HIMRE./ 370#define R88E_HIMRE_RXFOVW 0x00000100 371#define R88E_HIMRE_TXFOVW 0x00000200 372#define R88E_HIMRE_RXERR 0x00000400 373#define R88E_HIMRE_TXERR 0x00000800 374* 375/* Bits for R92C_EFUSE_ACCESS. / 376#define R92C_EFUSE_ACCESS_OFF 0x00 377#define R92C_EFUSE_ACCESS_ON 0x69 378* 379/* Bits for R92C_HPON_FSM. / 380#define R92C_HPON_FSM_CHIP_BONDING_ID_S 22 381#define R92C_HPON_FSM_CHIP_BONDING_ID_M 0x00c00000 382#define R92C_HPON_FSM_CHIP_BONDING_ID_92C_1T2R 1 383* 384/* Bits for R92C_SYS_CFG. / 385#define R92C_SYS_CFG_XCLK_VLD 0x00000001 386#define R92C_SYS_CFG_ACLK_VLD 0x00000002 387#define R92C_SYS_CFG_UCLK_VLD 0x00000004 388#define R92C_SYS_CFG_PCLK_VLD 0x00000008 389#define R92C_SYS_CFG_PCIRSTB 0x00000010 390#define R92C_SYS_CFG_V15_VLD 0x00000020 391#define R92C_SYS_CFG_TRP_B15V_EN 0x00000080 392#define R92C_SYS_CFG_SIC_IDLE 0x00000100 393#define R92C_SYS_CFG_BD_MAC2 0x00000200 394#define R92C_SYS_CFG_BD_MAC1 0x00000400 395#define R92C_SYS_CFG_IC_MACPHY_MODE 0x00000800 396#define R92C_SYS_CFG_CHIP_VER_RTL_M 0x0000f000 397#define R92C_SYS_CFG_CHIP_VER_RTL_S 12 398#define R92C_SYS_CFG_BT_FUNC 0x00010000 399#define R92C_SYS_CFG_VENDOR_UMC 0x00080000 400#define R92C_SYS_CFG_PAD_HWPD_IDN 0x00400000 401#define R92C_SYS_CFG_TRP_VAUX_EN 0x00800000 402#define R92C_SYS_CFG_TRP_BT_EN 0x01000000 403#define R92C_SYS_CFG_BD_PKG_SEL 0x02000000 404#define R92C_SYS_CFG_BD_HCI_SEL 0x04000000 405#define R92C_SYS_CFG_TYPE_92C 0x08000000 406* 407/* Bits for R92C_CR. / 408#define R92C_CR_HCI_TXDMA_EN 0x0001 409#define R92C_CR_HCI_RXDMA_EN 0x0002 410#define R92C_CR_TXDMA_EN 0x0004 411#define R92C_CR_RXDMA_EN 0x0008 412#define R92C_CR_PROTOCOL_EN 0x0010 413#define R92C_CR_SCHEDULE_EN 0x0020 414#define R92C_CR_MACTXEN 0x0040 415#define R92C_CR_MACRXEN 0x0080 416#define R92C_CR_ENSEC 0x0200 417#define R92C_CR_CALTMR_EN 0x0400 418* 419/* Bits for R92C_MSR. / 420#define R92C_MSR_NOLINK 0x00 421#define R92C_MSR_ADHOC 0x01 422#define R92C_MSR_INFRA 0x02 423#define R92C_MSR_AP 0x03 424#define R92C_MSR_MASK (R92C_MSR_AP) 425* 426/* Bits for R92C_PBP. / 427#define R92C_PBP_PSRX_M 0x0f 428#define R92C_PBP_PSRX_S 0 429#define R92C_PBP_PSTX_M 0xf0 430#define R92C_PBP_PSTX_S 4 431#define R92C_PBP_64 0 432#define R92C_PBP_128 1 433#define R92C_PBP_256 2 434#define R92C_PBP_512 3 435#define R92C_PBP_1024 4 436* 437/* Bits for R92C_TRXDMA_CTRL. / 438#define R92C_TRXDMA_CTRL_RXDMA_AGG_EN 0x0004 439#define R92C_TRXDMA_CTRL_TXDMA_VOQ_MAP_M 0x0030 440#define R92C_TRXDMA_CTRL_TXDMA_VOQ_MAP_S 4 441#define R92C_TRXDMA_CTRL_TXDMA_VIQ_MAP_M 0x00c0 442#define R92C_TRXDMA_CTRL_TXDMA_VIQ_MAP_S 6 443#define R92C_TRXDMA_CTRL_TXDMA_BEQ_MAP_M 0x0300 444#define R92C_TRXDMA_CTRL_TXDMA_BEQ_MAP_S 8 445#define R92C_TRXDMA_CTRL_TXDMA_BKQ_MAP_M 0x0c00 446#define R92C_TRXDMA_CTRL_TXDMA_BKQ_MAP_S 10 447#define R92C_TRXDMA_CTRL_TXDMA_MGQ_MAP_M 0x3000 448#define R92C_TRXDMA_CTRL_TXDMA_MGQ_MAP_S 12 449#define R92C_TRXDMA_CTRL_TXDMA_HIQ_MAP_M 0xc000 450#define R92C_TRXDMA_CTRL_TXDMA_HIQ_MAP_S 14 451#define R92C_TRXDMA_CTRL_QUEUE_LOW 1 452#define R92C_TRXDMA_CTRL_QUEUE_NORMAL 2 453#define R92C_TRXDMA_CTRL_QUEUE_HIGH 3 454#define R92C_TRXDMA_CTRL_QMAP_M 0xfff0 455/ Shortcuts. / 456#define R92C_TRXDMA_CTRL_QMAP_3EP 0xf5b0 457#define R92C_TRXDMA_CTRL_QMAP_HQ_LQ 0xf5f0 458#define R92C_TRXDMA_CTRL_QMAP_HQ_NQ 0xfaf0 459#define R92C_TRXDMA_CTRL_QMAP_LQ 0x5550 460#define R92C_TRXDMA_CTRL_QMAP_NQ 0xaaa0 461#define R92C_TRXDMA_CTRL_QMAP_HQ 0xfff0 462* 463/* Bits for R92C_LLT_INIT. / 464#define R92C_LLT_INIT_DATA_M 0x000000ff 465#define R92C_LLT_INIT_DATA_S 0 466#define R92C_LLT_INIT_ADDR_M 0x0000ff00 467#define R92C_LLT_INIT_ADDR_S 8 468#define R92C_LLT_INIT_OP_M 0xc0000000 469#define R92C_LLT_INIT_OP_S 30 470#define R92C_LLT_INIT_OP_NO_ACTIVE 0 471#define R92C_LLT_INIT_OP_WRITE 1 472* 473/* Bits for R92C_RQPN. / 474#define R92C_RQPN_HPQ_M 0x000000ff 475#define R92C_RQPN_HPQ_S 0 476#define R92C_RQPN_LPQ_M 0x0000ff00 477#define R92C_RQPN_LPQ_S 8 478#define R92C_RQPN_PUBQ_M 0x00ff0000 479#define R92C_RQPN_PUBQ_S 16 480#define R92C_RQPN_LD 0x80000000 481* 482/* Bits for R92C_TDECTRL. / 483#define R92C_TDECTRL_BLK_DESC_NUM_M 0x000000f0 484#define R92C_TDECTRL_BLK_DESC_NUM_S 4 485#define R92C_TDECTRL_BCN_VALID 0x00010000 486* 487/* Bits for R92C_FWHW_TXQ_CTRL. / 488#define R92C_FWHW_TXQ_CTRL_AMPDU_RTY_NEW 0x80 489* 490/* Bits for R92C_SPEC_SIFS. / 491#define R92C_SPEC_SIFS_CCK_M 0x00ff 492#define R92C_SPEC_SIFS_CCK_S 0 493#define R92C_SPEC_SIFS_OFDM_M 0xff00 494#define R92C_SPEC_SIFS_OFDM_S 8 495* 496/* Bits for R92C_RL. / 497#define R92C_RL_LRL_M 0x003f 498#define R92C_RL_LRL_S 0 499#define R92C_RL_SRL_M 0x3f00 500#define R92C_RL_SRL_S 8 501* 502/* Bits for R92C_RRSR. / 503#define R92C_RRSR_RATE_BITMAP_M 0x000fffff 504#define R92C_RRSR_RATE_BITMAP_S 0 505#define R92C_RRSR_RATE_CCK_ONLY_1M 0xffff1 506#define R92C_RRSR_RSC_LOWSUBCHNL 0x00200000 507#define R92C_RRSR_RSC_UPSUBCHNL 0x00400000 508#define R92C_RRSR_SHORT 0x00800000 509* 510/* Bits for R88E_TX_RPT_CTRL. / 511#define R88E_TX_RPT1_ENA 0x01 512#define R88E_TX_RPT2_ENA 0x02 513* 514/* Bits for R92C_EDCA_XX_PARAM. / 515#define R92C_EDCA_PARAM_AIFS_M 0x000000ff 516#define R92C_EDCA_PARAM_AIFS_S 0 517#define R92C_EDCA_PARAM_ECWMIN_M 0x00000f00 518#define R92C_EDCA_PARAM_ECWMIN_S 8 519#define R92C_EDCA_PARAM_ECWMAX_M 0x0000f000 520#define R92C_EDCA_PARAM_ECWMAX_S 12 521#define R92C_EDCA_PARAM_TXOP_M 0xffff0000 522#define R92C_EDCA_PARAM_TXOP_S 16 523* 524/* Bits for R92C_HWSEQ_CTRL / R92C_TXPAUSE. / 525#define R92C_TX_QUEUE_VO 0x01 526#define R92C_TX_QUEUE_VI 0x02 527#define R92C_TX_QUEUE_BE 0x04 528#define R92C_TX_QUEUE_BK 0x08 529#define R92C_TX_QUEUE_MGT 0x10 530#define R92C_TX_QUEUE_HIGH 0x20 531#define R92C_TX_QUEUE_BCN 0x40 532* 533/* Shortcuts. / 534#define R92C_TX_QUEUE_AC \ 535* (R92C_TX_QUEUE_VO \| R92C_TX_QUEUE_VI \| \ 536 R92C_TX_QUEUE_BE \| R92C_TX_QUEUE_BK) 537 538#define R92C_TX_QUEUE_ALL \ 539 (R92C_TX_QUEUE_AC \| R92C_TX_QUEUE_MGT \| \ 540 R92C_TX_QUEUE_HIGH \| R92C_TX_QUEUE_BCN \| 0x80) /* XXX / 541* 542/* Bits for R92C_BCN_CTRL. / 543#define R92C_BCN_CTRL_EN_MBSSID 0x02 544#define R92C_BCN_CTRL_TXBCN_RPT 0x04 545#define R92C_BCN_CTRL_EN_BCN 0x08 546#define R92C_BCN_CTRL_DIS_TSF_UDT0 0x10 547* 548/* Bits for R92C_MBID_NUM. / 549#define R92C_MBID_TXBCN_RPT0 0x08 550#define R92C_MBID_TXBCN_RPT1 0x10 551* 552/* Bits for R92C_DUAL_TSF_RST. / 553#define R92C_DUAL_TSF_RST0 0x01 554#define R92C_DUAL_TSF_RST1 0x02 555* 556/* Bits for R92C_ACMHWCTRL. / 557#define R92C_ACMHWCTRL_EN 0x01 558#define R92C_ACMHWCTRL_BE 0x02 559#define R92C_ACMHWCTRL_VI 0x04 560#define R92C_ACMHWCTRL_VO 0x08 561#define R92C_ACMHWCTRL_ACM_MASK 0x0f 562* 563/* Bits for R92C_APSD_CTRL. / 564#define R92C_APSD_CTRL_OFF 0x40 565#define R92C_APSD_CTRL_OFF_STATUS 0x80 566* 567/* Bits for R92C_BWOPMODE. / 568#define R92C_BWOPMODE_11J 0x01 569#define R92C_BWOPMODE_5G 0x02 570#define R92C_BWOPMODE_20MHZ 0x04 571* 572/* Bits for R92C_RCR. / 573#define R92C_RCR_AAP 0x00000001 574#define R92C_RCR_APM 0x00000002 575#define R92C_RCR_AM 0x00000004 576#define R92C_RCR_AB 0x00000008 577#define R92C_RCR_ADD3 0x00000010 578#define R92C_RCR_APWRMGT 0x00000020 579#define R92C_RCR_CBSSID_DATA 0x00000040 580#define R92C_RCR_CBSSID_BCN 0x00000080 581#define R92C_RCR_ACRC32 0x00000100 582#define R92C_RCR_AICV 0x00000200 583#define R92C_RCR_ADF 0x00000800 584#define R92C_RCR_ACF 0x00001000 585#define R92C_RCR_AMF 0x00002000 586#define R92C_RCR_HTC_LOC_CTRL 0x00004000 587#define R92C_RCR_MFBEN 0x00400000 588#define R92C_RCR_LSIGEN 0x00800000 589#define R92C_RCR_ENMBID 0x01000000 590#define R92C_RCR_APP_BA_SSN 0x08000000 591#define R92C_RCR_APP_PHYSTS 0x10000000 592#define R92C_RCR_APP_ICV 0x20000000 593#define R92C_RCR_APP_MIC 0x40000000 594#define R92C_RCR_APPFCS 0x80000000 595* 596/* Bits for R92C_CAMCMD. / 597#define R92C_CAMCMD_ADDR_M 0x0000ffff 598#define R92C_CAMCMD_ADDR_S 0 599#define R92C_CAMCMD_WRITE 0x00010000 600#define R92C_CAMCMD_CLR 0x40000000 601#define R92C_CAMCMD_POLLING 0x80000000 602* 603/* Bits for R92C_SECCFG. / 604#define R92C_SECCFG_TXUCKEY_DEF 0x0001 605#define R92C_SECCFG_RXUCKEY_DEF 0x0002 606#define R92C_SECCFG_TXENC_ENA 0x0004 607#define R92C_SECCFG_RXDEC_ENA 0x0008 608#define R92C_SECCFG_CMP_A2 0x0010 609#define R92C_SECCFG_TXBCKEY_DEF 0x0040 610#define R92C_SECCFG_RXBCKEY_DEF 0x0080 611#define R88E_SECCFG_CHK_KEYID 0x0100 612* 613/* Bits for R92C_RXFLTMAP. / 614#define R92C_RXFLTMAP_SUBTYPE(subtype) \ 615 (1 << ((subtype) >> IEEE80211_FC0_SUBTYPE_SHIFT)) 616 617 618/* 619 * Baseband registers. 620 / 621#define R92C_FPGA0_RFMOD 0x800 622#define R92C_FPGA0_TXINFO 0x804 623#define R92C_HSSI_PARAM1(chain) (0x820 + (chain) 8) 624#define R92C_HSSI_PARAM2(chain) (0x824 + (chain) * 8) 625#define R92C_TXAGC_RATE18_06(i) (((i) == 0) ? 0xe00 : 0x830) 626#define R92C_TXAGC_RATE54_24(i) (((i) == 0) ? 0xe04 : 0x834) 627#define R92C_TXAGC_A_CCK1_MCS32 0xe08 628#define R92C_TXAGC_B_CCK1_55_MCS32 0x838 629#define R92C_TXAGC_B_CCK11_A_CCK2_11 0x86c 630#define R92C_TXAGC_MCS03_MCS00(i) (((i) == 0) ? 0xe10 : 0x83c) 631#define R92C_TXAGC_MCS07_MCS04(i) (((i) == 0) ? 0xe14 : 0x848) 632#define R92C_TXAGC_MCS11_MCS08(i) (((i) == 0) ? 0xe18 : 0x84c) 633#define R92C_TXAGC_MCS15_MCS12(i) (((i) == 0) ? 0xe1c : 0x868) 634#define R92C_LSSI_PARAM(chain) (0x840 + (chain) * 4) 635#define R92C_FPGA0_RFIFACEOE(chain) (0x860 + (chain) * 4) 636#define R92C_FPGA0_RFIFACESW(idx) (0x870 + (idx) * 4) 637#define R92C_FPGA0_RFPARAM(idx) (0x878 + (idx) * 4) 638#define R92C_FPGA0_ANAPARAM2 0x884 639#define R92C_LSSI_READBACK(chain) (0x8a0 + (chain) * 4) 640#define R92C_HSPI_READBACK(chain) (0x8b8 + (chain) * 4) 641#define R92C_FPGA1_RFMOD 0x900 642#define R92C_FPGA1_TXINFO 0x90c 643#define R92C_CCK0_SYSTEM 0xa00 644#define R92C_CCK0_AFESETTING 0xa04 645#define R92C_OFDM0_TRXPATHENA 0xc04 646#define R92C_OFDM0_TRMUXPAR 0xc08 647#define R92C_OFDM0_AGCCORE1(chain) (0xc50 + (chain) * 8) 648#define R92C_OFDM0_AGCPARAM1 0xc70 649#define R92C_OFDM0_AGCRSSITABLE 0xc78 650#define R92C_OFDM1_LSTF 0xd00 651 652/* Bits for R92C_FPGA[01]_RFMOD. / 653#define R92C_RFMOD_40MHZ 0x00000001 654#define R92C_RFMOD_JAPAN 0x00000002 655#define R92C_RFMOD_CCK_TXSC 0x00000030 656#define R92C_RFMOD_CCK_EN 0x01000000 657#define R92C_RFMOD_OFDM_EN 0x02000000 658* 659/* Bits for R92C_HSSI_PARAM1(i). / 660#define R92C_HSSI_PARAM1_PI 0x00000100 661* 662/* Bits for R92C_HSSI_PARAM2(i). / 663#define R92C_HSSI_PARAM2_CCK_HIPWR 0x00000200 664#define R92C_HSSI_PARAM2_ADDR_LENGTH 0x00000400 665#define R92C_HSSI_PARAM2_DATA_LENGTH 0x00000800 666#define R92C_HSSI_PARAM2_READ_ADDR_M 0x7f800000 667#define R92C_HSSI_PARAM2_READ_ADDR_S 23 668#define R92C_HSSI_PARAM2_READ_EDGE 0x80000000 669* 670/* Bits for R92C_TXAGC_A_CCK1_MCS32. / 671#define R92C_TXAGC_A_CCK1_M 0x0000ff00 672#define R92C_TXAGC_A_CCK1_S 8 673* 674/* Bits for R92C_TXAGC_B_CCK11_A_CCK2_11. / 675#define R92C_TXAGC_B_CCK11_M 0x000000ff 676#define R92C_TXAGC_B_CCK11_S 0 677#define R92C_TXAGC_A_CCK2_M 0x0000ff00 678#define R92C_TXAGC_A_CCK2_S 8 679#define R92C_TXAGC_A_CCK55_M 0x00ff0000 680#define R92C_TXAGC_A_CCK55_S 16 681#define R92C_TXAGC_A_CCK11_M 0xff000000 682#define R92C_TXAGC_A_CCK11_S 24 683* 684/* Bits for R92C_TXAGC_B_CCK1_55_MCS32. / 685#define R92C_TXAGC_B_CCK1_M 0x0000ff00 686#define R92C_TXAGC_B_CCK1_S 8 687#define R92C_TXAGC_B_CCK2_M 0x00ff0000 688#define R92C_TXAGC_B_CCK2_S 16 689#define R92C_TXAGC_B_CCK55_M 0xff000000 690#define R92C_TXAGC_B_CCK55_S 24 691* 692/* Bits for R92C_TXAGC_RATE18_06(x). / 693#define R92C_TXAGC_RATE06_M 0x000000ff 694#define R92C_TXAGC_RATE06_S 0 695#define R92C_TXAGC_RATE09_M 0x0000ff00 696#define R92C_TXAGC_RATE09_S 8 697#define R92C_TXAGC_RATE12_M 0x00ff0000 698#define R92C_TXAGC_RATE12_S 16 699#define R92C_TXAGC_RATE18_M 0xff000000 700#define R92C_TXAGC_RATE18_S 24 701* 702/* Bits for R92C_TXAGC_RATE54_24(x). / 703#define R92C_TXAGC_RATE24_M 0x000000ff 704#define R92C_TXAGC_RATE24_S 0 705#define R92C_TXAGC_RATE36_M 0x0000ff00 706#define R92C_TXAGC_RATE36_S 8 707#define R92C_TXAGC_RATE48_M 0x00ff0000 708#define R92C_TXAGC_RATE48_S 16 709#define R92C_TXAGC_RATE54_M 0xff000000 710#define R92C_TXAGC_RATE54_S 24 711* 712/* Bits for R92C_TXAGC_MCS03_MCS00(x). / 713#define R92C_TXAGC_MCS00_M 0x000000ff 714#define R92C_TXAGC_MCS00_S 0 715#define R92C_TXAGC_MCS01_M 0x0000ff00 716#define R92C_TXAGC_MCS01_S 8 717#define R92C_TXAGC_MCS02_M 0x00ff0000 718#define R92C_TXAGC_MCS02_S 16 719#define R92C_TXAGC_MCS03_M 0xff000000 720#define R92C_TXAGC_MCS03_S 24 721* 722/* Bits for R92C_TXAGC_MCS07_MCS04(x). / 723#define R92C_TXAGC_MCS04_M 0x000000ff 724#define R92C_TXAGC_MCS04_S 0 725#define R92C_TXAGC_MCS05_M 0x0000ff00 726#define R92C_TXAGC_MCS05_S 8 727#define R92C_TXAGC_MCS06_M 0x00ff0000 728#define R92C_TXAGC_MCS06_S 16 729#define R92C_TXAGC_MCS07_M 0xff000000 730#define R92C_TXAGC_MCS07_S 24 731* 732/* Bits for R92C_TXAGC_MCS11_MCS08(x). / 733#define R92C_TXAGC_MCS08_M 0x000000ff 734#define R92C_TXAGC_MCS08_S 0 735#define R92C_TXAGC_MCS09_M 0x0000ff00 736#define R92C_TXAGC_MCS09_S 8 737#define R92C_TXAGC_MCS10_M 0x00ff0000 738#define R92C_TXAGC_MCS10_S 16 739#define R92C_TXAGC_MCS11_M 0xff000000 740#define R92C_TXAGC_MCS11_S 24 741* 742/* Bits for R92C_TXAGC_MCS15_MCS12(x). / 743#define R92C_TXAGC_MCS12_M 0x000000ff 744#define R92C_TXAGC_MCS12_S 0 745#define R92C_TXAGC_MCS13_M 0x0000ff00 746#define R92C_TXAGC_MCS13_S 8 747#define R92C_TXAGC_MCS14_M 0x00ff0000 748#define R92C_TXAGC_MCS14_S 16 749#define R92C_TXAGC_MCS15_M 0xff000000 750#define R92C_TXAGC_MCS15_S 24 751* 752/* Bits for R92C_LSSI_PARAM(i). / 753#define R92C_LSSI_PARAM_DATA_M 0x000fffff 754#define R92C_LSSI_PARAM_DATA_S 0 755#define R92C_LSSI_PARAM_ADDR_M 0x03f00000 756#define R92C_LSSI_PARAM_ADDR_S 20 757#define R88E_LSSI_PARAM_ADDR_M 0x0ff00000 758#define R88E_LSSI_PARAM_ADDR_S 20 759* 760/* Bits for R92C_FPGA0_ANAPARAM2. / 761#define R92C_FPGA0_ANAPARAM2_CBW20 0x00000400 762* 763/* Bits for R92C_LSSI_READBACK(i). / 764#define R92C_LSSI_READBACK_DATA_M 0x000fffff 765#define R92C_LSSI_READBACK_DATA_S 0 766* 767/* Bits for R92C_OFDM0_AGCCORE1(i). / 768#define R92C_OFDM0_AGCCORE1_GAIN_M 0x0000007f 769#define R92C_OFDM0_AGCCORE1_GAIN_S 0 770* 771 772/* 773 * USB registers. 774 / 775#define R92C_USB_SUSPEND 0xfe10 776#define R92C_USB_INFO 0xfe17 777#define R92C_USB_SPECIAL_OPTION 0xfe55 778#define R92C_USB_HCPWM 0xfe57 779#define R92C_USB_HRPWM 0xfe58 780#define R92C_USB_DMA_AGG_TO 0xfe5b 781#define R92C_USB_AGG_TO 0xfe5c 782#define R92C_USB_AGG_TH 0xfe5d 783#define R92C_USB_VID 0xfe60 784#define R92C_USB_PID 0xfe62 785#define R92C_USB_OPTIONAL 0xfe64 786#define R92C_USB_EP 0xfe65 787#define R92C_USB_PHY 0xfe68 788#define R92C_USB_MAC_ADDR 0xfe70 789#define R92C_USB_STRING 0xfe80 790* 791/* Bits for R92C_USB_SPECIAL_OPTION. / 792#define R92C_USB_SPECIAL_OPTION_AGG_EN 0x08 793#define R92C_USB_SPECIAL_OPTION_INT_BULK_SEL 0x10 794* 795/* Bits for R92C_USB_EP. / 796#define R92C_USB_EP_HQ_M 0x000f 797#define R92C_USB_EP_HQ_S 0 798#define R92C_USB_EP_NQ_M 0x00f0 799#define R92C_USB_EP_NQ_S 4 800#define R92C_USB_EP_LQ_M 0x0f00 801#define R92C_USB_EP_LQ_S 8 802* 803 804/* 805 * Firmware base address. 806 / 807#define R92C_FW_START_ADDR 0x1000 808#define R92C_FW_PAGE_SIZE 4096 809* 810 811/* 812 * RF (6052) registers. 813 / 814#define R92C_RF_AC 0x00 815#define R92C_RF_IQADJ_G(i) (0x01 + (i)) 816#define R92C_RF_POW_TRSW 0x05 817#define R92C_RF_GAIN_RX 0x06 818#define R92C_RF_GAIN_TX 0x07 819#define R92C_RF_TXM_IDAC 0x08 820#define R92C_RF_BS_IQGEN 0x0f 821#define R92C_RF_MODE1 0x10 822#define R92C_RF_MODE2 0x11 823#define R92C_RF_RX_AGC_HP 0x12 824#define R92C_RF_TX_AGC 0x13 825#define R92C_RF_BIAS 0x14 826#define R92C_RF_IPA 0x15 827#define R92C_RF_POW_ABILITY 0x17 828#define R92C_RF_CHNLBW 0x18 829#define R92C_RF_RX_G1 0x1a 830#define R92C_RF_RX_G2 0x1b 831#define R92C_RF_RX_BB2 0x1c 832#define R92C_RF_RX_BB1 0x1d 833#define R92C_RF_RCK1 0x1e 834#define R92C_RF_RCK2 0x1f 835#define R92C_RF_TX_G(i) (0x20 + (i)) 836#define R92C_RF_TX_BB1 0x23 837#define R92C_RF_T_METER 0x24 838#define R92C_RF_SYN_G(i) (0x25 + (i)) 839#define R92C_RF_RCK_OS 0x30 840#define R92C_RF_TXPA_G(i) (0x31 + (i)) 841#define R88E_RF_T_METER 0x42 842* 843/* Bits for R92C_RF_AC. / 844#define R92C_RF_AC_MODE_M 0x70000 845#define R92C_RF_AC_MODE_S 16 846#define R92C_RF_AC_MODE_STANDBY 1 847* 848/* Bits for R92C_RF_CHNLBW. / 849#define R92C_RF_CHNLBW_CHNL_M 0x003ff 850#define R92C_RF_CHNLBW_CHNL_S 0 851#define R92C_RF_CHNLBW_BW20 0x00400 852#define R88E_RF_CHNLBW_BW20 0x00c00 853#define R92C_RF_CHNLBW_LCSTART 0x08000 854* 855/* Bits for R92C_RF_T_METER. / 856#define R92C_RF_T_METER_START 0x60 857#define R92C_RF_T_METER_VAL_M 0x1f 858#define R92C_RF_T_METER_VAL_S 0 859* 860/* Bits for R88E_RF_T_METER. / 861#define R88E_RF_T_METER_VAL_M 0x0fc00 862#define R88E_RF_T_METER_VAL_S 10 863#define R88E_RF_T_METER_START 0x30000 864* 865 866/* 867 * CAM entries. 868 / 869#define R92C_CAM_ENTRY_COUNT 32 870* 871#define R92C_CAM_CTL0(entry) ((entry) * 8 + 0) 872#define R92C_CAM_CTL1(entry) ((entry) * 8 + 1) 873#define R92C_CAM_KEY(entry, i) ((entry) * 8 + 2 + (i)) 874 875/* Bits for R92C_CAM_CTL0(i). / 876#define R92C_CAM_KEYID_M 0x00000003 877#define R92C_CAM_KEYID_S 0 878#define R92C_CAM_ALGO_M 0x0000001c 879#define R92C_CAM_ALGO_S 2 880#define R92C_CAM_ALGO_NONE 0 881#define R92C_CAM_ALGO_WEP40 1 882#define R92C_CAM_ALGO_TKIP 2 883#define R92C_CAM_ALGO_AES 4 884#define R92C_CAM_ALGO_WEP104 5 885#define R92C_CAM_VALID 0x00008000 886#define R92C_CAM_MACLO_M 0xffff0000 887#define R92C_CAM_MACLO_S 16 888* 889/* Rate adaptation modes. / 890#define R92C_RAID_11GN 1 891#define R92C_RAID_11N 3 892#define R92C_RAID_11BG 4 893#define R92C_RAID_11G 5 / "pure" 11g / 894#define R92C_RAID_11B 6 895* 896 897/* 898 * Macros to access subfields in registers. 899 / 900/ Mask and Shift (getter). / 901#define MS(val, field) \ 902* (((val) & field##_M) >> field##_S) 903 904/* Shift and Mask (setter). / 905#define SM(field, val) \ 906* (((val) << field##_S) & field##_M) 907 908/* Rewrite. / 909#define RW(var, field, val) \ 910* (((var) & ~field##_M) \| SM(field, val)) 911 912/* 913 * Firmware image header. 914 / 915struct r92c_fw_hdr { 916* /* QWORD0 / 917* uint16_t signature; 918 uint8_t category; 919 uint8_t function; 920 uint16_t version; 921 uint16_t subversion; 922 /* QWORD1 / 923* uint8_t month; 924 uint8_t date; 925 uint8_t hour; 926 uint8_t minute; 927 uint16_t ramcodesize; 928 uint16_t reserved2; 929 /* QWORD2 / 930* uint32_t svnidx; 931 uint32_t reserved3; 932 /* QWORD3 / 933* uint32_t reserved4; 934 uint32_t reserved5; 935} __packed; 936 937/* 938 * Host to firmware commands. 939 / 940struct r92c_fw_cmd { 941* uint8_t id; 942#define R92C_CMD_AP_OFFLOAD 0 943#define R92C_CMD_SET_PWRMODE 1 944#define R92C_CMD_JOINBSS_RPT 2 945#define R92C_CMD_RSVD_PAGE 3 946#define R92C_CMD_RSSI 4 947#define R92C_CMD_RSSI_SETTING 5 948#define R92C_CMD_MACID_CONFIG 6 949#define R92C_CMD_MACID_PS_MODE 7 950#define R92C_CMD_P2P_PS_OFFLOAD 8 951#define R92C_CMD_SELECTIVE_SUSPEND 9 952#define R92C_CMD_FLAG_EXT 0x80 953 954 uint8_t msg[5]; 955} __packed; 956 957/* Structure for R92C_CMD_RSSI_SETTING. / 958struct r92c_fw_cmd_rssi { 959* uint8_t macid; 960 uint8_t reserved; 961 uint8_t pwdb; 962} __packed; 963 964/* Structure for R92C_CMD_MACID_CONFIG. / 965struct r92c_fw_cmd_macid_cfg { 966* uint32_t mask; 967 uint8_t macid; 968#define URTWN_MACID_BSS 0 969#define URTWN_MACID_BC 4 /* Broadcast. / 970#define R92C_MACID_MAX 31 971#define R88E_MACID_MAX 63 972#define URTWN_MACID_MAX(sc) (((sc)->chip & URTWN_CHIP_88E) ? \ 973* R88E_MACID_MAX : R92C_MACID_MAX) 974#define URTWN_MACID_UNDEFINED (uint8_t)-1 975#define URTWN_MACID_VALID 0x80 976} __packed; 977 978/* 979 * RTL8192CU ROM image. 980 / 981struct r92c_rom { 982* uint16_t id; /* 0x8192 / 983* uint8_t reserved1[5]; 984 uint8_t dbg_sel; 985 uint16_t reserved2; 986 uint16_t vid; 987 uint16_t pid; 988 uint8_t usb_opt; 989 uint8_t ep_setting; 990 uint16_t reserved3; 991 uint8_t usb_phy; 992 uint8_t reserved4[3]; 993 uint8_t macaddr[IEEE80211_ADDR_LEN]; 994 uint8_t string[61]; /* "Realtek" / 995* uint8_t subcustomer_id; 996 uint8_t cck_tx_pwr[R92C_MAX_CHAINS][3]; 997 uint8_t ht40_1s_tx_pwr[R92C_MAX_CHAINS][3]; 998 uint8_t ht40_2s_tx_pwr_diff[3]; 999 uint8_t ht20_tx_pwr_diff[3]; 1000 uint8_t ofdm_tx_pwr_diff[3]; 1001 uint8_t ht40_max_pwr[3]; 1002 uint8_t ht20_max_pwr[3]; 1003 uint8_t xtal_calib; 1004 uint8_t tssi[R92C_MAX_CHAINS]; 1005 uint8_t thermal_meter; 1006 uint8_t rf_opt1; 1007#define R92C_ROM_RF1_REGULATORY_M 0x07 1008#define R92C_ROM_RF1_REGULATORY_S 0 1009#define R92C_ROM_RF1_BOARD_TYPE_M 0xe0 1010#define R92C_ROM_RF1_BOARD_TYPE_S 5 1011#define R92C_BOARD_TYPE_DONGLE 0 1012#define R92C_BOARD_TYPE_HIGHPA 1 1013#define R92C_BOARD_TYPE_MINICARD 2 1014#define R92C_BOARD_TYPE_SOLO 3 1015#define R92C_BOARD_TYPE_COMBO 4 1016 1017 uint8_t rf_opt2; 1018 uint8_t rf_opt3; 1019 uint8_t rf_opt4; 1020 uint8_t channel_plan;	18 / 19 20#define URTWN_CONFIG_INDEX 0 21#define URTWN_IFACE_INDEX 0 22 23#define URTWN_NOISE_FLOOR -95 24 25#define R92C_MAX_CHAINS 2 26 27/ Maximum number of output pipes is 3. / 28#define R92C_MAX_EPOUT 3 29 30#define R92C_MAX_TX_PWR 0x3f 31 32#define R92C_PUBQ_NPAGES 231 33#define R92C_TXPKTBUF_COUNT 256 34#define R92C_TX_PAGE_COUNT 248 35#define R92C_TX_PAGE_BOUNDARY (R92C_TX_PAGE_COUNT + 1) 36#define R88E_TXPKTBUF_COUNT 177 37#define R88E_TX_PAGE_COUNT 169 38#define R88E_TX_PAGE_BOUNDARY (R88E_TX_PAGE_COUNT + 1) 39 40#define R92C_H2C_NBOX 4 41 42/ USB Requests. / 43#define R92C_REQ_REGS 0x05 44 45/ 46 * MAC registers. 47 / 48/ System Configuration. / 49#define R92C_SYS_ISO_CTRL 0x000 50#define R92C_SYS_FUNC_EN 0x002 51#define R92C_APS_FSMCO 0x004 52#define R92C_SYS_CLKR 0x008 53#define R92C_AFE_MISC 0x010 54#define R92C_SPS0_CTRL 0x011 55#define R92C_SPS_OCP_CFG 0x018 56#define R92C_RSV_CTRL 0x01c 57#define R92C_RF_CTRL 0x01f 58#define R92C_LDOA15_CTRL 0x020 59#define R92C_LDOV12D_CTRL 0x021 60#define R92C_LDOHCI12_CTRL 0x022 61#define R92C_LPLDO_CTRL 0x023 62#define R92C_AFE_XTAL_CTRL 0x024 63#define R92C_AFE_PLL_CTRL 0x028 64#define R92C_EFUSE_CTRL 0x030 65#define R92C_EFUSE_TEST 0x034 66#define R92C_PWR_DATA 0x038 67#define R92C_CAL_TIMER 0x03c 68#define R92C_ACLK_MON 0x03e 69#define R92C_GPIO_MUXCFG 0x040 70#define R92C_GPIO_IO_SEL 0x042 71#define R92C_MAC_PINMUX_CFG 0x043 72#define R92C_GPIO_PIN_CTRL 0x044 73#define R92C_GPIO_IN 0x044 74#define R92C_GPIO_OUT 0x045 75#define R92C_GPIO_IOSEL 0x046 76#define R92C_GPIO_MOD 0x047 77#define R92C_GPIO_INTM 0x048 78#define R92C_LEDCFG0 0x04c 79#define R92C_LEDCFG1 0x04d 80#define R92C_LEDCFG2 0x04e 81#define R92C_LEDCFG3 0x04f 82#define R92C_FSIMR 0x050 83#define R92C_FSISR 0x054 84#define R92C_HSIMR 0x058 85#define R92C_HSISR 0x05c 86#define R88E_BB_PAD_CTRL 0x064 87#define R92C_MCUFWDL 0x080 88#define R92C_HMEBOX_EXT(idx) (0x088 + (idx) 2) 89#define R88E_HIMR 0x0b0 90#define R88E_HISR 0x0b4 91#define R88E_HIMRE 0x0b8 92#define R88E_HISRE 0x0bc 93#define R92C_EFUSE_ACCESS 0x0cf 94#define R92C_BIST_SCAN 0x0d0 95#define R92C_BIST_RPT 0x0d4 96#define R92C_BIST_ROM_RPT 0x0d8 97#define R92C_USB_SIE_INTF 0x0e0 98#define R92C_PCIE_MIO_INTF 0x0e4 99#define R92C_PCIE_MIO_INTD 0x0e8 100#define R92C_HPON_FSM 0x0ec 101#define R92C_SYS_CFG 0x0f0 102/* MAC General Configuration. / 103#define R92C_CR 0x100 104#define R92C_MSR 0x102 105#define R92C_PBP 0x104 106#define R92C_TRXDMA_CTRL 0x10c 107#define R92C_TRXFF_BNDY 0x114 108#define R92C_TRXFF_STATUS 0x118 109#define R92C_RXFF_PTR 0x11c 110#define R92C_HIMR 0x120 111#define R92C_HISR 0x124 112#define R92C_HIMRE 0x128 113#define R92C_HISRE 0x12c 114#define R92C_CPWM 0x12f 115#define R92C_FWIMR 0x130 116#define R92C_FWISR 0x134 117#define R92C_PKTBUF_DBG_CTRL 0x140 118#define R92C_PKTBUF_DBG_DATA_L 0x144 119#define R92C_PKTBUF_DBG_DATA_H 0x148 120#define R92C_TC0_CTRL(i) (0x150 + (i) 4) 121#define R92C_TCUNIT_BASE 0x164 122#define R92C_MBIST_START 0x174 123#define R92C_MBIST_DONE 0x178 124#define R92C_MBIST_FAIL 0x17c 125#define R88E_32K_CTRL 0x194 126#define R92C_C2HEVT_MSG_NORMAL 0x1a0 127#define R92C_C2HEVT_MSG_TEST 0x1b8 128#define R92C_C2HEVT_CLEAR 0x1bf 129#define R92C_MCUTST_1 0x1c0 130#define R92C_FMETHR 0x1c8 131#define R92C_HMETFR 0x1cc 132#define R92C_HMEBOX(idx) (0x1d0 + (idx) * 4) 133#define R92C_LLT_INIT 0x1e0 134#define R92C_BB_ACCESS_CTRL 0x1e8 135#define R92C_BB_ACCESS_DATA 0x1ec 136#define R88E_HMEBOX_EXT(idx) (0x1f0 + (idx) * 4) 137/* Tx DMA Configuration. / 138#define R92C_RQPN 0x200 139#define R92C_FIFOPAGE 0x204 140#define R92C_TDECTRL 0x208 141#define R92C_TXDMA_OFFSET_CHK 0x20c 142#define R92C_TXDMA_STATUS 0x210 143#define R92C_RQPN_NPQ 0x214 144/ Rx DMA Configuration. / 145#define R92C_RXDMA_AGG_PG_TH 0x280 146#define R92C_RXPKT_NUM 0x284 147#define R92C_RXDMA_STATUS 0x288 148/ Protocol Configuration. / 149#define R92C_FWHW_TXQ_CTRL 0x420 150#define R92C_HWSEQ_CTRL 0x423 151#define R92C_TXPKTBUF_BCNQ_BDNY 0x424 152#define R92C_TXPKTBUF_MGQ_BDNY 0x425 153#define R92C_SPEC_SIFS 0x428 154#define R92C_RL 0x42a 155#define R92C_DARFRC 0x430 156#define R92C_RARFRC 0x438 157#define R92C_RRSR 0x440 158#define R92C_ARFR(i) (0x444 + (i) 4) 159#define R92C_AGGLEN_LMT 0x458 160#define R92C_AMPDU_MIN_SPACE 0x45c 161#define R92C_TXPKTBUF_WMAC_LBK_BF_HD 0x45d 162#define R92C_FAST_EDCA_CTRL 0x460 163#define R92C_RD_RESP_PKT_TH 0x463 164#define R92C_INIRTS_RATE_SEL 0x480 165#define R92C_INIDATA_RATE_SEL(macid) (0x484 + (macid)) 166#define R92C_MAX_AGGR_NUM 0x4ca 167#define R88E_TX_RPT_CTRL 0x4ec 168#define R88E_TX_RPT_MACID_MAX 0x4ed 169#define R88E_TX_RPT_TIME 0x4f0 170/* EDCA Configuration. / 171#define R92C_EDCA_VO_PARAM 0x500 172#define R92C_EDCA_VI_PARAM 0x504 173#define R92C_EDCA_BE_PARAM 0x508 174#define R92C_EDCA_BK_PARAM 0x50c 175#define R92C_BCNTCFG 0x510 176#define R92C_PIFS 0x512 177#define R92C_RDG_PIFS 0x513 178#define R92C_SIFS_CCK 0x514 179#define R92C_SIFS_OFDM 0x516 180#define R92C_AGGR_BREAK_TIME 0x51a 181#define R92C_SLOT 0x51b 182#define R92C_TX_PTCL_CTRL 0x520 183#define R92C_TXPAUSE 0x522 184#define R92C_DIS_TXREQ_CLR 0x523 185#define R92C_RD_CTRL 0x524 186#define R92C_TBTT_PROHIBIT 0x540 187#define R92C_RD_NAV_NXT 0x544 188#define R92C_NAV_PROT_LEN 0x546 189#define R92C_BCN_CTRL 0x550 190#define R92C_MBID_NUM 0x552 191#define R92C_DUAL_TSF_RST 0x553 192#define R92C_BCN_INTERVAL 0x554 193#define R92C_DRVERLYINT 0x558 194#define R92C_BCNDMATIM 0x559 195#define R92C_ATIMWND 0x55a 196#define R92C_USTIME_TSF 0x55c 197#define R92C_BCN_MAX_ERR 0x55d 198#define R92C_RXTSF_OFFSET_CCK 0x55e 199#define R92C_RXTSF_OFFSET_OFDM 0x55f 200#define R92C_TSFTR 0x560 201#define R92C_INIT_TSFTR 0x564 202#define R92C_PSTIMER 0x580 203#define R92C_TIMER0 0x584 204#define R92C_TIMER1 0x588 205#define R92C_ACMHWCTRL 0x5c0 206#define R92C_ACMRSTCTRL 0x5c1 207#define R92C_ACMAVG 0x5c2 208#define R92C_VO_ADMTIME 0x5c4 209#define R92C_VI_ADMTIME 0x5c6 210#define R92C_BE_ADMTIME 0x5c8 211#define R92C_EDCA_RANDOM_GEN 0x5cc 212#define R92C_SCH_TXCMD 0x5d0 213#define R88E_SCH_TXCMD 0x5f8 214/ WMAC Configuration. / 215#define R92C_APSD_CTRL 0x600 216#define R92C_BWOPMODE 0x603 217#define R92C_RCR 0x608 218#define R92C_RX_DRVINFO_SZ 0x60f 219#define R92C_MACID 0x610 220#define R92C_BSSID 0x618 221#define R92C_MAR 0x620 222#define R92C_MAC_SPEC_SIFS 0x63a 223#define R92C_R2T_SIFS 0x63c 224#define R92C_T2T_SIFS 0x63e 225#define R92C_ACKTO 0x640 226#define R92C_CAMCMD 0x670 227#define R92C_CAMWRITE 0x674 228#define R92C_CAMREAD 0x678 229#define R92C_CAMDBG 0x67c 230#define R92C_SECCFG 0x680 231#define R92C_RXFLTMAP0 0x6a0 232#define R92C_RXFLTMAP1 0x6a2 233#define R92C_RXFLTMAP2 0x6a4 234* 235/* Bits for R92C_SYS_ISO_CTRL. / 236#define R92C_SYS_ISO_CTRL_MD2PP 0x0001 237#define R92C_SYS_ISO_CTRL_UA2USB 0x0002 238#define R92C_SYS_ISO_CTRL_UD2CORE 0x0004 239#define R92C_SYS_ISO_CTRL_PA2PCIE 0x0008 240#define R92C_SYS_ISO_CTRL_PD2CORE 0x0010 241#define R92C_SYS_ISO_CTRL_IP2MAC 0x0020 242#define R92C_SYS_ISO_CTRL_DIOP 0x0040 243#define R92C_SYS_ISO_CTRL_DIOE 0x0080 244#define R92C_SYS_ISO_CTRL_EB2CORE 0x0100 245#define R92C_SYS_ISO_CTRL_DIOR 0x0200 246#define R92C_SYS_ISO_CTRL_PWC_EV25V 0x4000 247#define R92C_SYS_ISO_CTRL_PWC_EV12V 0x8000 248* 249/* Bits for R92C_SYS_FUNC_EN. / 250#define R92C_SYS_FUNC_EN_BBRSTB 0x0001 251#define R92C_SYS_FUNC_EN_BB_GLB_RST 0x0002 252#define R92C_SYS_FUNC_EN_USBA 0x0004 253#define R92C_SYS_FUNC_EN_UPLL 0x0008 254#define R92C_SYS_FUNC_EN_USBD 0x0010 255#define R92C_SYS_FUNC_EN_DIO_PCIE 0x0020 256#define R92C_SYS_FUNC_EN_PCIEA 0x0040 257#define R92C_SYS_FUNC_EN_PPLL 0x0080 258#define R92C_SYS_FUNC_EN_PCIED 0x0100 259#define R92C_SYS_FUNC_EN_DIOE 0x0200 260#define R92C_SYS_FUNC_EN_CPUEN 0x0400 261#define R92C_SYS_FUNC_EN_DCORE 0x0800 262#define R92C_SYS_FUNC_EN_ELDR 0x1000 263#define R92C_SYS_FUNC_EN_DIO_RF 0x2000 264#define R92C_SYS_FUNC_EN_HWPDN 0x4000 265#define R92C_SYS_FUNC_EN_MREGEN 0x8000 266* 267/* Bits for R92C_APS_FSMCO. / 268#define R92C_APS_FSMCO_PFM_LDALL 0x00000001 269#define R92C_APS_FSMCO_PFM_ALDN 0x00000002 270#define R92C_APS_FSMCO_PFM_LDKP 0x00000004 271#define R92C_APS_FSMCO_PFM_WOWL 0x00000008 272#define R92C_APS_FSMCO_PDN_EN 0x00000010 273#define R92C_APS_FSMCO_PDN_PL 0x00000020 274#define R92C_APS_FSMCO_APFM_ONMAC 0x00000100 275#define R92C_APS_FSMCO_APFM_OFF 0x00000200 276#define R92C_APS_FSMCO_APFM_RSM 0x00000400 277#define R92C_APS_FSMCO_AFSM_HSUS 0x00000800 278#define R92C_APS_FSMCO_AFSM_PCIE 0x00001000 279#define R92C_APS_FSMCO_APDM_MAC 0x00002000 280#define R92C_APS_FSMCO_APDM_HOST 0x00004000 281#define R92C_APS_FSMCO_APDM_HPDN 0x00008000 282#define R92C_APS_FSMCO_RDY_MACON 0x00010000 283#define R92C_APS_FSMCO_SUS_HOST 0x00020000 284#define R92C_APS_FSMCO_ROP_ALD 0x00100000 285#define R92C_APS_FSMCO_ROP_PWR 0x00200000 286#define R92C_APS_FSMCO_ROP_SPS 0x00400000 287#define R92C_APS_FSMCO_SOP_MRST 0x02000000 288#define R92C_APS_FSMCO_SOP_FUSE 0x04000000 289#define R92C_APS_FSMCO_SOP_ABG 0x08000000 290#define R92C_APS_FSMCO_SOP_AMB 0x10000000 291#define R92C_APS_FSMCO_SOP_RCK 0x20000000 292#define R92C_APS_FSMCO_SOP_A8M 0x40000000 293#define R92C_APS_FSMCO_XOP_BTCK 0x80000000 294* 295/* Bits for R92C_SYS_CLKR. / 296#define R92C_SYS_CLKR_ANAD16V_EN 0x00000001 297#define R92C_SYS_CLKR_ANA8M 0x00000002 298#define R92C_SYS_CLKR_MACSLP 0x00000010 299#define R92C_SYS_CLKR_LOADER_EN 0x00000020 300#define R92C_SYS_CLKR_80M_SSC_DIS 0x00000080 301#define R92C_SYS_CLKR_80M_SSC_EN_HO 0x00000100 302#define R92C_SYS_CLKR_PHY_SSC_RSTB 0x00000200 303#define R92C_SYS_CLKR_SEC_EN 0x00000400 304#define R92C_SYS_CLKR_MAC_EN 0x00000800 305#define R92C_SYS_CLKR_SYS_EN 0x00001000 306#define R92C_SYS_CLKR_RING_EN 0x00002000 307* 308/* Bits for R92C_RF_CTRL. / 309#define R92C_RF_CTRL_EN 0x01 310#define R92C_RF_CTRL_RSTB 0x02 311#define R92C_RF_CTRL_SDMRSTB 0x04 312* 313/* Bits for R92C_LDOA15_CTRL. / 314#define R92C_LDOA15_CTRL_EN 0x01 315#define R92C_LDOA15_CTRL_STBY 0x02 316#define R92C_LDOA15_CTRL_OBUF 0x04 317#define R92C_LDOA15_CTRL_REG_VOS 0x08 318* 319/* Bits for R92C_LDOV12D_CTRL. / 320#define R92C_LDOV12D_CTRL_LDV12_EN 0x01 321* 322/* Bits for R92C_LPLDO_CTRL. / 323#define R92C_LPLDO_CTRL_SLEEP 0x10 324* 325/* Bits for R92C_AFE_XTAL_CTRL. / 326#define R92C_AFE_XTAL_CTRL_ADDR_M 0x007ff800 327#define R92C_AFE_XTAL_CTRL_ADDR_S 11 328* 329/* Bits for R92C_AFE_PLL_CTRL. / 330#define R92C_AFE_PLL_CTRL_EN 0x0001 331#define R92C_AFE_PLL_CTRL_320_EN 0x0002 332#define R92C_AFE_PLL_CTRL_FREF_SEL 0x0004 333#define R92C_AFE_PLL_CTRL_EDGE_SEL 0x0008 334#define R92C_AFE_PLL_CTRL_WDOGB 0x0010 335#define R92C_AFE_PLL_CTRL_LPFEN 0x0020 336* 337/* Bits for R92C_EFUSE_CTRL. / 338#define R92C_EFUSE_CTRL_DATA_M 0x000000ff 339#define R92C_EFUSE_CTRL_DATA_S 0 340#define R92C_EFUSE_CTRL_ADDR_M 0x0003ff00 341#define R92C_EFUSE_CTRL_ADDR_S 8 342#define R92C_EFUSE_CTRL_VALID 0x80000000 343* 344/* Bits for R92C_GPIO_MUXCFG. / 345#define R92C_GPIO_MUXCFG_ENBT 0x0020 346* 347/* Bits for R92C_LEDCFG0. / 348#define R92C_LEDCFG0_DIS 0x08 349* 350/* Bits for R92C_MCUFWDL. / 351#define R92C_MCUFWDL_EN 0x00000001 352#define R92C_MCUFWDL_RDY 0x00000002 353#define R92C_MCUFWDL_CHKSUM_RPT 0x00000004 354#define R92C_MCUFWDL_MACINI_RDY 0x00000008 355#define R92C_MCUFWDL_BBINI_RDY 0x00000010 356#define R92C_MCUFWDL_RFINI_RDY 0x00000020 357#define R92C_MCUFWDL_WINTINI_RDY 0x00000040 358#define R92C_MCUFWDL_RAM_DL_SEL 0x00000080 359#define R92C_MCUFWDL_PAGE_M 0x00070000 360#define R92C_MCUFWDL_PAGE_S 16 361#define R92C_MCUFWDL_CPRST 0x00800000 362* 363/* Bits for R88E_HIMR. / 364#define R88E_HIMR_CPWM 0x00000100 365#define R88E_HIMR_CPWM2 0x00000200 366#define R88E_HIMR_TBDER 0x04000000 367#define R88E_HIMR_PSTIMEOUT 0x20000000 368* 369/* Bits for R88E_HIMRE./ 370#define R88E_HIMRE_RXFOVW 0x00000100 371#define R88E_HIMRE_TXFOVW 0x00000200 372#define R88E_HIMRE_RXERR 0x00000400 373#define R88E_HIMRE_TXERR 0x00000800 374* 375/* Bits for R92C_EFUSE_ACCESS. / 376#define R92C_EFUSE_ACCESS_OFF 0x00 377#define R92C_EFUSE_ACCESS_ON 0x69 378* 379/* Bits for R92C_HPON_FSM. / 380#define R92C_HPON_FSM_CHIP_BONDING_ID_S 22 381#define R92C_HPON_FSM_CHIP_BONDING_ID_M 0x00c00000 382#define R92C_HPON_FSM_CHIP_BONDING_ID_92C_1T2R 1 383* 384/* Bits for R92C_SYS_CFG. / 385#define R92C_SYS_CFG_XCLK_VLD 0x00000001 386#define R92C_SYS_CFG_ACLK_VLD 0x00000002 387#define R92C_SYS_CFG_UCLK_VLD 0x00000004 388#define R92C_SYS_CFG_PCLK_VLD 0x00000008 389#define R92C_SYS_CFG_PCIRSTB 0x00000010 390#define R92C_SYS_CFG_V15_VLD 0x00000020 391#define R92C_SYS_CFG_TRP_B15V_EN 0x00000080 392#define R92C_SYS_CFG_SIC_IDLE 0x00000100 393#define R92C_SYS_CFG_BD_MAC2 0x00000200 394#define R92C_SYS_CFG_BD_MAC1 0x00000400 395#define R92C_SYS_CFG_IC_MACPHY_MODE 0x00000800 396#define R92C_SYS_CFG_CHIP_VER_RTL_M 0x0000f000 397#define R92C_SYS_CFG_CHIP_VER_RTL_S 12 398#define R92C_SYS_CFG_BT_FUNC 0x00010000 399#define R92C_SYS_CFG_VENDOR_UMC 0x00080000 400#define R92C_SYS_CFG_PAD_HWPD_IDN 0x00400000 401#define R92C_SYS_CFG_TRP_VAUX_EN 0x00800000 402#define R92C_SYS_CFG_TRP_BT_EN 0x01000000 403#define R92C_SYS_CFG_BD_PKG_SEL 0x02000000 404#define R92C_SYS_CFG_BD_HCI_SEL 0x04000000 405#define R92C_SYS_CFG_TYPE_92C 0x08000000 406* 407/* Bits for R92C_CR. / 408#define R92C_CR_HCI_TXDMA_EN 0x0001 409#define R92C_CR_HCI_RXDMA_EN 0x0002 410#define R92C_CR_TXDMA_EN 0x0004 411#define R92C_CR_RXDMA_EN 0x0008 412#define R92C_CR_PROTOCOL_EN 0x0010 413#define R92C_CR_SCHEDULE_EN 0x0020 414#define R92C_CR_MACTXEN 0x0040 415#define R92C_CR_MACRXEN 0x0080 416#define R92C_CR_ENSEC 0x0200 417#define R92C_CR_CALTMR_EN 0x0400 418* 419/* Bits for R92C_MSR. / 420#define R92C_MSR_NOLINK 0x00 421#define R92C_MSR_ADHOC 0x01 422#define R92C_MSR_INFRA 0x02 423#define R92C_MSR_AP 0x03 424#define R92C_MSR_MASK (R92C_MSR_AP) 425* 426/* Bits for R92C_PBP. / 427#define R92C_PBP_PSRX_M 0x0f 428#define R92C_PBP_PSRX_S 0 429#define R92C_PBP_PSTX_M 0xf0 430#define R92C_PBP_PSTX_S 4 431#define R92C_PBP_64 0 432#define R92C_PBP_128 1 433#define R92C_PBP_256 2 434#define R92C_PBP_512 3 435#define R92C_PBP_1024 4 436* 437/* Bits for R92C_TRXDMA_CTRL. / 438#define R92C_TRXDMA_CTRL_RXDMA_AGG_EN 0x0004 439#define R92C_TRXDMA_CTRL_TXDMA_VOQ_MAP_M 0x0030 440#define R92C_TRXDMA_CTRL_TXDMA_VOQ_MAP_S 4 441#define R92C_TRXDMA_CTRL_TXDMA_VIQ_MAP_M 0x00c0 442#define R92C_TRXDMA_CTRL_TXDMA_VIQ_MAP_S 6 443#define R92C_TRXDMA_CTRL_TXDMA_BEQ_MAP_M 0x0300 444#define R92C_TRXDMA_CTRL_TXDMA_BEQ_MAP_S 8 445#define R92C_TRXDMA_CTRL_TXDMA_BKQ_MAP_M 0x0c00 446#define R92C_TRXDMA_CTRL_TXDMA_BKQ_MAP_S 10 447#define R92C_TRXDMA_CTRL_TXDMA_MGQ_MAP_M 0x3000 448#define R92C_TRXDMA_CTRL_TXDMA_MGQ_MAP_S 12 449#define R92C_TRXDMA_CTRL_TXDMA_HIQ_MAP_M 0xc000 450#define R92C_TRXDMA_CTRL_TXDMA_HIQ_MAP_S 14 451#define R92C_TRXDMA_CTRL_QUEUE_LOW 1 452#define R92C_TRXDMA_CTRL_QUEUE_NORMAL 2 453#define R92C_TRXDMA_CTRL_QUEUE_HIGH 3 454#define R92C_TRXDMA_CTRL_QMAP_M 0xfff0 455/ Shortcuts. / 456#define R92C_TRXDMA_CTRL_QMAP_3EP 0xf5b0 457#define R92C_TRXDMA_CTRL_QMAP_HQ_LQ 0xf5f0 458#define R92C_TRXDMA_CTRL_QMAP_HQ_NQ 0xfaf0 459#define R92C_TRXDMA_CTRL_QMAP_LQ 0x5550 460#define R92C_TRXDMA_CTRL_QMAP_NQ 0xaaa0 461#define R92C_TRXDMA_CTRL_QMAP_HQ 0xfff0 462* 463/* Bits for R92C_LLT_INIT. / 464#define R92C_LLT_INIT_DATA_M 0x000000ff 465#define R92C_LLT_INIT_DATA_S 0 466#define R92C_LLT_INIT_ADDR_M 0x0000ff00 467#define R92C_LLT_INIT_ADDR_S 8 468#define R92C_LLT_INIT_OP_M 0xc0000000 469#define R92C_LLT_INIT_OP_S 30 470#define R92C_LLT_INIT_OP_NO_ACTIVE 0 471#define R92C_LLT_INIT_OP_WRITE 1 472* 473/* Bits for R92C_RQPN. / 474#define R92C_RQPN_HPQ_M 0x000000ff 475#define R92C_RQPN_HPQ_S 0 476#define R92C_RQPN_LPQ_M 0x0000ff00 477#define R92C_RQPN_LPQ_S 8 478#define R92C_RQPN_PUBQ_M 0x00ff0000 479#define R92C_RQPN_PUBQ_S 16 480#define R92C_RQPN_LD 0x80000000 481* 482/* Bits for R92C_TDECTRL. / 483#define R92C_TDECTRL_BLK_DESC_NUM_M 0x000000f0 484#define R92C_TDECTRL_BLK_DESC_NUM_S 4 485#define R92C_TDECTRL_BCN_VALID 0x00010000 486* 487/* Bits for R92C_FWHW_TXQ_CTRL. / 488#define R92C_FWHW_TXQ_CTRL_AMPDU_RTY_NEW 0x80 489* 490/* Bits for R92C_SPEC_SIFS. / 491#define R92C_SPEC_SIFS_CCK_M 0x00ff 492#define R92C_SPEC_SIFS_CCK_S 0 493#define R92C_SPEC_SIFS_OFDM_M 0xff00 494#define R92C_SPEC_SIFS_OFDM_S 8 495* 496/* Bits for R92C_RL. / 497#define R92C_RL_LRL_M 0x003f 498#define R92C_RL_LRL_S 0 499#define R92C_RL_SRL_M 0x3f00 500#define R92C_RL_SRL_S 8 501* 502/* Bits for R92C_RRSR. / 503#define R92C_RRSR_RATE_BITMAP_M 0x000fffff 504#define R92C_RRSR_RATE_BITMAP_S 0 505#define R92C_RRSR_RATE_CCK_ONLY_1M 0xffff1 506#define R92C_RRSR_RSC_LOWSUBCHNL 0x00200000 507#define R92C_RRSR_RSC_UPSUBCHNL 0x00400000 508#define R92C_RRSR_SHORT 0x00800000 509* 510/* Bits for R88E_TX_RPT_CTRL. / 511#define R88E_TX_RPT1_ENA 0x01 512#define R88E_TX_RPT2_ENA 0x02 513* 514/* Bits for R92C_EDCA_XX_PARAM. / 515#define R92C_EDCA_PARAM_AIFS_M 0x000000ff 516#define R92C_EDCA_PARAM_AIFS_S 0 517#define R92C_EDCA_PARAM_ECWMIN_M 0x00000f00 518#define R92C_EDCA_PARAM_ECWMIN_S 8 519#define R92C_EDCA_PARAM_ECWMAX_M 0x0000f000 520#define R92C_EDCA_PARAM_ECWMAX_S 12 521#define R92C_EDCA_PARAM_TXOP_M 0xffff0000 522#define R92C_EDCA_PARAM_TXOP_S 16 523* 524/* Bits for R92C_HWSEQ_CTRL / R92C_TXPAUSE. / 525#define R92C_TX_QUEUE_VO 0x01 526#define R92C_TX_QUEUE_VI 0x02 527#define R92C_TX_QUEUE_BE 0x04 528#define R92C_TX_QUEUE_BK 0x08 529#define R92C_TX_QUEUE_MGT 0x10 530#define R92C_TX_QUEUE_HIGH 0x20 531#define R92C_TX_QUEUE_BCN 0x40 532* 533/* Shortcuts. / 534#define R92C_TX_QUEUE_AC \ 535* (R92C_TX_QUEUE_VO \| R92C_TX_QUEUE_VI \| \ 536 R92C_TX_QUEUE_BE \| R92C_TX_QUEUE_BK) 537 538#define R92C_TX_QUEUE_ALL \ 539 (R92C_TX_QUEUE_AC \| R92C_TX_QUEUE_MGT \| \ 540 R92C_TX_QUEUE_HIGH \| R92C_TX_QUEUE_BCN \| 0x80) /* XXX / 541* 542/* Bits for R92C_BCN_CTRL. / 543#define R92C_BCN_CTRL_EN_MBSSID 0x02 544#define R92C_BCN_CTRL_TXBCN_RPT 0x04 545#define R92C_BCN_CTRL_EN_BCN 0x08 546#define R92C_BCN_CTRL_DIS_TSF_UDT0 0x10 547* 548/* Bits for R92C_MBID_NUM. / 549#define R92C_MBID_TXBCN_RPT0 0x08 550#define R92C_MBID_TXBCN_RPT1 0x10 551* 552/* Bits for R92C_DUAL_TSF_RST. / 553#define R92C_DUAL_TSF_RST0 0x01 554#define R92C_DUAL_TSF_RST1 0x02 555* 556/* Bits for R92C_ACMHWCTRL. / 557#define R92C_ACMHWCTRL_EN 0x01 558#define R92C_ACMHWCTRL_BE 0x02 559#define R92C_ACMHWCTRL_VI 0x04 560#define R92C_ACMHWCTRL_VO 0x08 561#define R92C_ACMHWCTRL_ACM_MASK 0x0f 562* 563/* Bits for R92C_APSD_CTRL. / 564#define R92C_APSD_CTRL_OFF 0x40 565#define R92C_APSD_CTRL_OFF_STATUS 0x80 566* 567/* Bits for R92C_BWOPMODE. / 568#define R92C_BWOPMODE_11J 0x01 569#define R92C_BWOPMODE_5G 0x02 570#define R92C_BWOPMODE_20MHZ 0x04 571* 572/* Bits for R92C_RCR. / 573#define R92C_RCR_AAP 0x00000001 574#define R92C_RCR_APM 0x00000002 575#define R92C_RCR_AM 0x00000004 576#define R92C_RCR_AB 0x00000008 577#define R92C_RCR_ADD3 0x00000010 578#define R92C_RCR_APWRMGT 0x00000020 579#define R92C_RCR_CBSSID_DATA 0x00000040 580#define R92C_RCR_CBSSID_BCN 0x00000080 581#define R92C_RCR_ACRC32 0x00000100 582#define R92C_RCR_AICV 0x00000200 583#define R92C_RCR_ADF 0x00000800 584#define R92C_RCR_ACF 0x00001000 585#define R92C_RCR_AMF 0x00002000 586#define R92C_RCR_HTC_LOC_CTRL 0x00004000 587#define R92C_RCR_MFBEN 0x00400000 588#define R92C_RCR_LSIGEN 0x00800000 589#define R92C_RCR_ENMBID 0x01000000 590#define R92C_RCR_APP_BA_SSN 0x08000000 591#define R92C_RCR_APP_PHYSTS 0x10000000 592#define R92C_RCR_APP_ICV 0x20000000 593#define R92C_RCR_APP_MIC 0x40000000 594#define R92C_RCR_APPFCS 0x80000000 595* 596/* Bits for R92C_CAMCMD. / 597#define R92C_CAMCMD_ADDR_M 0x0000ffff 598#define R92C_CAMCMD_ADDR_S 0 599#define R92C_CAMCMD_WRITE 0x00010000 600#define R92C_CAMCMD_CLR 0x40000000 601#define R92C_CAMCMD_POLLING 0x80000000 602* 603/* Bits for R92C_SECCFG. / 604#define R92C_SECCFG_TXUCKEY_DEF 0x0001 605#define R92C_SECCFG_RXUCKEY_DEF 0x0002 606#define R92C_SECCFG_TXENC_ENA 0x0004 607#define R92C_SECCFG_RXDEC_ENA 0x0008 608#define R92C_SECCFG_CMP_A2 0x0010 609#define R92C_SECCFG_TXBCKEY_DEF 0x0040 610#define R92C_SECCFG_RXBCKEY_DEF 0x0080 611#define R88E_SECCFG_CHK_KEYID 0x0100 612* 613/* Bits for R92C_RXFLTMAP. / 614#define R92C_RXFLTMAP_SUBTYPE(subtype) \ 615 (1 << ((subtype) >> IEEE80211_FC0_SUBTYPE_SHIFT)) 616 617 618/* 619 * Baseband registers. 620 / 621#define R92C_FPGA0_RFMOD 0x800 622#define R92C_FPGA0_TXINFO 0x804 623#define R92C_HSSI_PARAM1(chain) (0x820 + (chain) 8) 624#define R92C_HSSI_PARAM2(chain) (0x824 + (chain) * 8) 625#define R92C_TXAGC_RATE18_06(i) (((i) == 0) ? 0xe00 : 0x830) 626#define R92C_TXAGC_RATE54_24(i) (((i) == 0) ? 0xe04 : 0x834) 627#define R92C_TXAGC_A_CCK1_MCS32 0xe08 628#define R92C_TXAGC_B_CCK1_55_MCS32 0x838 629#define R92C_TXAGC_B_CCK11_A_CCK2_11 0x86c 630#define R92C_TXAGC_MCS03_MCS00(i) (((i) == 0) ? 0xe10 : 0x83c) 631#define R92C_TXAGC_MCS07_MCS04(i) (((i) == 0) ? 0xe14 : 0x848) 632#define R92C_TXAGC_MCS11_MCS08(i) (((i) == 0) ? 0xe18 : 0x84c) 633#define R92C_TXAGC_MCS15_MCS12(i) (((i) == 0) ? 0xe1c : 0x868) 634#define R92C_LSSI_PARAM(chain) (0x840 + (chain) * 4) 635#define R92C_FPGA0_RFIFACEOE(chain) (0x860 + (chain) * 4) 636#define R92C_FPGA0_RFIFACESW(idx) (0x870 + (idx) * 4) 637#define R92C_FPGA0_RFPARAM(idx) (0x878 + (idx) * 4) 638#define R92C_FPGA0_ANAPARAM2 0x884 639#define R92C_LSSI_READBACK(chain) (0x8a0 + (chain) * 4) 640#define R92C_HSPI_READBACK(chain) (0x8b8 + (chain) * 4) 641#define R92C_FPGA1_RFMOD 0x900 642#define R92C_FPGA1_TXINFO 0x90c 643#define R92C_CCK0_SYSTEM 0xa00 644#define R92C_CCK0_AFESETTING 0xa04 645#define R92C_OFDM0_TRXPATHENA 0xc04 646#define R92C_OFDM0_TRMUXPAR 0xc08 647#define R92C_OFDM0_AGCCORE1(chain) (0xc50 + (chain) * 8) 648#define R92C_OFDM0_AGCPARAM1 0xc70 649#define R92C_OFDM0_AGCRSSITABLE 0xc78 650#define R92C_OFDM1_LSTF 0xd00 651 652/* Bits for R92C_FPGA[01]_RFMOD. / 653#define R92C_RFMOD_40MHZ 0x00000001 654#define R92C_RFMOD_JAPAN 0x00000002 655#define R92C_RFMOD_CCK_TXSC 0x00000030 656#define R92C_RFMOD_CCK_EN 0x01000000 657#define R92C_RFMOD_OFDM_EN 0x02000000 658* 659/* Bits for R92C_HSSI_PARAM1(i). / 660#define R92C_HSSI_PARAM1_PI 0x00000100 661* 662/* Bits for R92C_HSSI_PARAM2(i). / 663#define R92C_HSSI_PARAM2_CCK_HIPWR 0x00000200 664#define R92C_HSSI_PARAM2_ADDR_LENGTH 0x00000400 665#define R92C_HSSI_PARAM2_DATA_LENGTH 0x00000800 666#define R92C_HSSI_PARAM2_READ_ADDR_M 0x7f800000 667#define R92C_HSSI_PARAM2_READ_ADDR_S 23 668#define R92C_HSSI_PARAM2_READ_EDGE 0x80000000 669* 670/* Bits for R92C_TXAGC_A_CCK1_MCS32. / 671#define R92C_TXAGC_A_CCK1_M 0x0000ff00 672#define R92C_TXAGC_A_CCK1_S 8 673* 674/* Bits for R92C_TXAGC_B_CCK11_A_CCK2_11. / 675#define R92C_TXAGC_B_CCK11_M 0x000000ff 676#define R92C_TXAGC_B_CCK11_S 0 677#define R92C_TXAGC_A_CCK2_M 0x0000ff00 678#define R92C_TXAGC_A_CCK2_S 8 679#define R92C_TXAGC_A_CCK55_M 0x00ff0000 680#define R92C_TXAGC_A_CCK55_S 16 681#define R92C_TXAGC_A_CCK11_M 0xff000000 682#define R92C_TXAGC_A_CCK11_S 24 683* 684/* Bits for R92C_TXAGC_B_CCK1_55_MCS32. / 685#define R92C_TXAGC_B_CCK1_M 0x0000ff00 686#define R92C_TXAGC_B_CCK1_S 8 687#define R92C_TXAGC_B_CCK2_M 0x00ff0000 688#define R92C_TXAGC_B_CCK2_S 16 689#define R92C_TXAGC_B_CCK55_M 0xff000000 690#define R92C_TXAGC_B_CCK55_S 24 691* 692/* Bits for R92C_TXAGC_RATE18_06(x). / 693#define R92C_TXAGC_RATE06_M 0x000000ff 694#define R92C_TXAGC_RATE06_S 0 695#define R92C_TXAGC_RATE09_M 0x0000ff00 696#define R92C_TXAGC_RATE09_S 8 697#define R92C_TXAGC_RATE12_M 0x00ff0000 698#define R92C_TXAGC_RATE12_S 16 699#define R92C_TXAGC_RATE18_M 0xff000000 700#define R92C_TXAGC_RATE18_S 24 701* 702/* Bits for R92C_TXAGC_RATE54_24(x). / 703#define R92C_TXAGC_RATE24_M 0x000000ff 704#define R92C_TXAGC_RATE24_S 0 705#define R92C_TXAGC_RATE36_M 0x0000ff00 706#define R92C_TXAGC_RATE36_S 8 707#define R92C_TXAGC_RATE48_M 0x00ff0000 708#define R92C_TXAGC_RATE48_S 16 709#define R92C_TXAGC_RATE54_M 0xff000000 710#define R92C_TXAGC_RATE54_S 24 711* 712/* Bits for R92C_TXAGC_MCS03_MCS00(x). / 713#define R92C_TXAGC_MCS00_M 0x000000ff 714#define R92C_TXAGC_MCS00_S 0 715#define R92C_TXAGC_MCS01_M 0x0000ff00 716#define R92C_TXAGC_MCS01_S 8 717#define R92C_TXAGC_MCS02_M 0x00ff0000 718#define R92C_TXAGC_MCS02_S 16 719#define R92C_TXAGC_MCS03_M 0xff000000 720#define R92C_TXAGC_MCS03_S 24 721* 722/* Bits for R92C_TXAGC_MCS07_MCS04(x). / 723#define R92C_TXAGC_MCS04_M 0x000000ff 724#define R92C_TXAGC_MCS04_S 0 725#define R92C_TXAGC_MCS05_M 0x0000ff00 726#define R92C_TXAGC_MCS05_S 8 727#define R92C_TXAGC_MCS06_M 0x00ff0000 728#define R92C_TXAGC_MCS06_S 16 729#define R92C_TXAGC_MCS07_M 0xff000000 730#define R92C_TXAGC_MCS07_S 24 731* 732/* Bits for R92C_TXAGC_MCS11_MCS08(x). / 733#define R92C_TXAGC_MCS08_M 0x000000ff 734#define R92C_TXAGC_MCS08_S 0 735#define R92C_TXAGC_MCS09_M 0x0000ff00 736#define R92C_TXAGC_MCS09_S 8 737#define R92C_TXAGC_MCS10_M 0x00ff0000 738#define R92C_TXAGC_MCS10_S 16 739#define R92C_TXAGC_MCS11_M 0xff000000 740#define R92C_TXAGC_MCS11_S 24 741* 742/* Bits for R92C_TXAGC_MCS15_MCS12(x). / 743#define R92C_TXAGC_MCS12_M 0x000000ff 744#define R92C_TXAGC_MCS12_S 0 745#define R92C_TXAGC_MCS13_M 0x0000ff00 746#define R92C_TXAGC_MCS13_S 8 747#define R92C_TXAGC_MCS14_M 0x00ff0000 748#define R92C_TXAGC_MCS14_S 16 749#define R92C_TXAGC_MCS15_M 0xff000000 750#define R92C_TXAGC_MCS15_S 24 751* 752/* Bits for R92C_LSSI_PARAM(i). / 753#define R92C_LSSI_PARAM_DATA_M 0x000fffff 754#define R92C_LSSI_PARAM_DATA_S 0 755#define R92C_LSSI_PARAM_ADDR_M 0x03f00000 756#define R92C_LSSI_PARAM_ADDR_S 20 757#define R88E_LSSI_PARAM_ADDR_M 0x0ff00000 758#define R88E_LSSI_PARAM_ADDR_S 20 759* 760/* Bits for R92C_FPGA0_ANAPARAM2. / 761#define R92C_FPGA0_ANAPARAM2_CBW20 0x00000400 762* 763/* Bits for R92C_LSSI_READBACK(i). / 764#define R92C_LSSI_READBACK_DATA_M 0x000fffff 765#define R92C_LSSI_READBACK_DATA_S 0 766* 767/* Bits for R92C_OFDM0_AGCCORE1(i). / 768#define R92C_OFDM0_AGCCORE1_GAIN_M 0x0000007f 769#define R92C_OFDM0_AGCCORE1_GAIN_S 0 770* 771 772/* 773 * USB registers. 774 / 775#define R92C_USB_SUSPEND 0xfe10 776#define R92C_USB_INFO 0xfe17 777#define R92C_USB_SPECIAL_OPTION 0xfe55 778#define R92C_USB_HCPWM 0xfe57 779#define R92C_USB_HRPWM 0xfe58 780#define R92C_USB_DMA_AGG_TO 0xfe5b 781#define R92C_USB_AGG_TO 0xfe5c 782#define R92C_USB_AGG_TH 0xfe5d 783#define R92C_USB_VID 0xfe60 784#define R92C_USB_PID 0xfe62 785#define R92C_USB_OPTIONAL 0xfe64 786#define R92C_USB_EP 0xfe65 787#define R92C_USB_PHY 0xfe68 788#define R92C_USB_MAC_ADDR 0xfe70 789#define R92C_USB_STRING 0xfe80 790* 791/* Bits for R92C_USB_SPECIAL_OPTION. / 792#define R92C_USB_SPECIAL_OPTION_AGG_EN 0x08 793#define R92C_USB_SPECIAL_OPTION_INT_BULK_SEL 0x10 794* 795/* Bits for R92C_USB_EP. / 796#define R92C_USB_EP_HQ_M 0x000f 797#define R92C_USB_EP_HQ_S 0 798#define R92C_USB_EP_NQ_M 0x00f0 799#define R92C_USB_EP_NQ_S 4 800#define R92C_USB_EP_LQ_M 0x0f00 801#define R92C_USB_EP_LQ_S 8 802* 803 804/* 805 * Firmware base address. 806 / 807#define R92C_FW_START_ADDR 0x1000 808#define R92C_FW_PAGE_SIZE 4096 809* 810 811/* 812 * RF (6052) registers. 813 / 814#define R92C_RF_AC 0x00 815#define R92C_RF_IQADJ_G(i) (0x01 + (i)) 816#define R92C_RF_POW_TRSW 0x05 817#define R92C_RF_GAIN_RX 0x06 818#define R92C_RF_GAIN_TX 0x07 819#define R92C_RF_TXM_IDAC 0x08 820#define R92C_RF_BS_IQGEN 0x0f 821#define R92C_RF_MODE1 0x10 822#define R92C_RF_MODE2 0x11 823#define R92C_RF_RX_AGC_HP 0x12 824#define R92C_RF_TX_AGC 0x13 825#define R92C_RF_BIAS 0x14 826#define R92C_RF_IPA 0x15 827#define R92C_RF_POW_ABILITY 0x17 828#define R92C_RF_CHNLBW 0x18 829#define R92C_RF_RX_G1 0x1a 830#define R92C_RF_RX_G2 0x1b 831#define R92C_RF_RX_BB2 0x1c 832#define R92C_RF_RX_BB1 0x1d 833#define R92C_RF_RCK1 0x1e 834#define R92C_RF_RCK2 0x1f 835#define R92C_RF_TX_G(i) (0x20 + (i)) 836#define R92C_RF_TX_BB1 0x23 837#define R92C_RF_T_METER 0x24 838#define R92C_RF_SYN_G(i) (0x25 + (i)) 839#define R92C_RF_RCK_OS 0x30 840#define R92C_RF_TXPA_G(i) (0x31 + (i)) 841#define R88E_RF_T_METER 0x42 842* 843/* Bits for R92C_RF_AC. / 844#define R92C_RF_AC_MODE_M 0x70000 845#define R92C_RF_AC_MODE_S 16 846#define R92C_RF_AC_MODE_STANDBY 1 847* 848/* Bits for R92C_RF_CHNLBW. / 849#define R92C_RF_CHNLBW_CHNL_M 0x003ff 850#define R92C_RF_CHNLBW_CHNL_S 0 851#define R92C_RF_CHNLBW_BW20 0x00400 852#define R88E_RF_CHNLBW_BW20 0x00c00 853#define R92C_RF_CHNLBW_LCSTART 0x08000 854* 855/* Bits for R92C_RF_T_METER. / 856#define R92C_RF_T_METER_START 0x60 857#define R92C_RF_T_METER_VAL_M 0x1f 858#define R92C_RF_T_METER_VAL_S 0 859* 860/* Bits for R88E_RF_T_METER. / 861#define R88E_RF_T_METER_VAL_M 0x0fc00 862#define R88E_RF_T_METER_VAL_S 10 863#define R88E_RF_T_METER_START 0x30000 864* 865 866/* 867 * CAM entries. 868 / 869#define R92C_CAM_ENTRY_COUNT 32 870* 871#define R92C_CAM_CTL0(entry) ((entry) * 8 + 0) 872#define R92C_CAM_CTL1(entry) ((entry) * 8 + 1) 873#define R92C_CAM_KEY(entry, i) ((entry) * 8 + 2 + (i)) 874 875/* Bits for R92C_CAM_CTL0(i). / 876#define R92C_CAM_KEYID_M 0x00000003 877#define R92C_CAM_KEYID_S 0 878#define R92C_CAM_ALGO_M 0x0000001c 879#define R92C_CAM_ALGO_S 2 880#define R92C_CAM_ALGO_NONE 0 881#define R92C_CAM_ALGO_WEP40 1 882#define R92C_CAM_ALGO_TKIP 2 883#define R92C_CAM_ALGO_AES 4 884#define R92C_CAM_ALGO_WEP104 5 885#define R92C_CAM_VALID 0x00008000 886#define R92C_CAM_MACLO_M 0xffff0000 887#define R92C_CAM_MACLO_S 16 888* 889/* Rate adaptation modes. / 890#define R92C_RAID_11GN 1 891#define R92C_RAID_11N 3 892#define R92C_RAID_11BG 4 893#define R92C_RAID_11G 5 / "pure" 11g / 894#define R92C_RAID_11B 6 895* 896 897/* 898 * Macros to access subfields in registers. 899 / 900/ Mask and Shift (getter). / 901#define MS(val, field) \ 902* (((val) & field##_M) >> field##_S) 903 904/* Shift and Mask (setter). / 905#define SM(field, val) \ 906* (((val) << field##_S) & field##_M) 907 908/* Rewrite. / 909#define RW(var, field, val) \ 910* (((var) & ~field##_M) \| SM(field, val)) 911 912/* 913 * Firmware image header. 914 / 915struct r92c_fw_hdr { 916* /* QWORD0 / 917* uint16_t signature; 918 uint8_t category; 919 uint8_t function; 920 uint16_t version; 921 uint16_t subversion; 922 /* QWORD1 / 923* uint8_t month; 924 uint8_t date; 925 uint8_t hour; 926 uint8_t minute; 927 uint16_t ramcodesize; 928 uint16_t reserved2; 929 /* QWORD2 / 930* uint32_t svnidx; 931 uint32_t reserved3; 932 /* QWORD3 / 933* uint32_t reserved4; 934 uint32_t reserved5; 935} __packed; 936 937/* 938 * Host to firmware commands. 939 / 940struct r92c_fw_cmd { 941* uint8_t id; 942#define R92C_CMD_AP_OFFLOAD 0 943#define R92C_CMD_SET_PWRMODE 1 944#define R92C_CMD_JOINBSS_RPT 2 945#define R92C_CMD_RSVD_PAGE 3 946#define R92C_CMD_RSSI 4 947#define R92C_CMD_RSSI_SETTING 5 948#define R92C_CMD_MACID_CONFIG 6 949#define R92C_CMD_MACID_PS_MODE 7 950#define R92C_CMD_P2P_PS_OFFLOAD 8 951#define R92C_CMD_SELECTIVE_SUSPEND 9 952#define R92C_CMD_FLAG_EXT 0x80 953 954 uint8_t msg[5]; 955} __packed; 956 957/* Structure for R92C_CMD_RSSI_SETTING. / 958struct r92c_fw_cmd_rssi { 959* uint8_t macid; 960 uint8_t reserved; 961 uint8_t pwdb; 962} __packed; 963 964/* Structure for R92C_CMD_MACID_CONFIG. / 965struct r92c_fw_cmd_macid_cfg { 966* uint32_t mask; 967 uint8_t macid; 968#define URTWN_MACID_BSS 0 969#define URTWN_MACID_BC 4 /* Broadcast. / 970#define R92C_MACID_MAX 31 971#define R88E_MACID_MAX 63 972#define URTWN_MACID_MAX(sc) (((sc)->chip & URTWN_CHIP_88E) ? \ 973* R88E_MACID_MAX : R92C_MACID_MAX) 974#define URTWN_MACID_UNDEFINED (uint8_t)-1 975#define URTWN_MACID_VALID 0x80 976} __packed; 977 978/* 979 * RTL8192CU ROM image. 980 / 981struct r92c_rom { 982* uint16_t id; /* 0x8192 / 983* uint8_t reserved1[5]; 984 uint8_t dbg_sel; 985 uint16_t reserved2; 986 uint16_t vid; 987 uint16_t pid; 988 uint8_t usb_opt; 989 uint8_t ep_setting; 990 uint16_t reserved3; 991 uint8_t usb_phy; 992 uint8_t reserved4[3]; 993 uint8_t macaddr[IEEE80211_ADDR_LEN]; 994 uint8_t string[61]; /* "Realtek" / 995* uint8_t subcustomer_id; 996 uint8_t cck_tx_pwr[R92C_MAX_CHAINS][3]; 997 uint8_t ht40_1s_tx_pwr[R92C_MAX_CHAINS][3]; 998 uint8_t ht40_2s_tx_pwr_diff[3]; 999 uint8_t ht20_tx_pwr_diff[3]; 1000 uint8_t ofdm_tx_pwr_diff[3]; 1001 uint8_t ht40_max_pwr[3]; 1002 uint8_t ht20_max_pwr[3]; 1003 uint8_t xtal_calib; 1004 uint8_t tssi[R92C_MAX_CHAINS]; 1005 uint8_t thermal_meter; 1006 uint8_t rf_opt1; 1007#define R92C_ROM_RF1_REGULATORY_M 0x07 1008#define R92C_ROM_RF1_REGULATORY_S 0 1009#define R92C_ROM_RF1_BOARD_TYPE_M 0xe0 1010#define R92C_ROM_RF1_BOARD_TYPE_S 5 1011#define R92C_BOARD_TYPE_DONGLE 0 1012#define R92C_BOARD_TYPE_HIGHPA 1 1013#define R92C_BOARD_TYPE_MINICARD 2 1014#define R92C_BOARD_TYPE_SOLO 3 1015#define R92C_BOARD_TYPE_COMBO 4 1016 1017 uint8_t rf_opt2; 1018 uint8_t rf_opt3; 1019 uint8_t rf_opt4; 1020 uint8_t channel_plan;
	1021#define R92C_CHANNEL_PLAN_BY_HW 0x80 1022
1021 uint8_t version; 1022 uint8_t customer_id; 1023} __packed; 1024 1025/* 1026 * RTL8188EU ROM image. 1027 / 1028struct r88e_rom { 1029* uint8_t reserved1[16]; 1030 uint8_t cck_tx_pwr[6]; 1031 uint8_t ht40_tx_pwr[5]; 1032 uint8_t tx_pwr_diff; 1033 uint8_t reserved2[156]; 1034 uint8_t channel_plan; 1035 uint8_t crystalcap; 1036 uint8_t reserved3[7]; 1037 uint8_t rf_board_opt; 1038 uint8_t rf_feature_opt; 1039 uint8_t rf_bt_opt; 1040 uint8_t version; 1041 uint8_t customer_id; 1042 uint8_t reserved4[3]; 1043 uint8_t rf_ant_opt; 1044 uint8_t reserved5[6]; 1045 uint16_t vid; 1046 uint16_t pid; 1047 uint8_t usb_opt; 1048 uint8_t reserved6[2]; 1049 uint8_t macaddr[IEEE80211_ADDR_LEN]; 1050 uint8_t reserved7[2]; 1051 uint8_t string[33]; /* "realtek 802.11n NIC" / 1052* uint8_t reserved8[256]; 1053} __packed; 1054 1055#define URTWN_EFUSE_MAX_LEN 512 1056 1057/* Rx MAC descriptor. / 1058struct r92c_rx_stat { 1059* uint32_t rxdw0; 1060#define R92C_RXDW0_PKTLEN_M 0x00003fff 1061#define R92C_RXDW0_PKTLEN_S 0 1062#define R92C_RXDW0_CRCERR 0x00004000 1063#define R92C_RXDW0_ICVERR 0x00008000 1064#define R92C_RXDW0_INFOSZ_M 0x000f0000 1065#define R92C_RXDW0_INFOSZ_S 16 1066#define R92C_RXDW0_CIPHER_M 0x00700000 1067#define R92C_RXDW0_CIPHER_S 20 1068#define R92C_RXDW0_QOS 0x00800000 1069#define R92C_RXDW0_SHIFT_M 0x03000000 1070#define R92C_RXDW0_SHIFT_S 24 1071#define R92C_RXDW0_PHYST 0x04000000 1072#define R92C_RXDW0_DECRYPTED 0x08000000 1073 1074 uint32_t rxdw1; 1075 uint32_t rxdw2; 1076#define R92C_RXDW2_PKTCNT_M 0x00ff0000 1077#define R92C_RXDW2_PKTCNT_S 16 1078 1079 uint32_t rxdw3; 1080#define R92C_RXDW3_RATE_M 0x0000003f 1081#define R92C_RXDW3_RATE_S 0 1082#define R92C_RXDW3_HT 0x00000040 1083#define R92C_RXDW3_HTC 0x00000400 1084#define R88E_RXDW3_RPT_M 0x0000c000 1085#define R88E_RXDW3_RPT_S 14 1086#define R88E_RXDW3_RPT_RX 0 1087#define R88E_RXDW3_RPT_TX1 1 1088#define R88E_RXDW3_RPT_TX2 2 1089 1090 uint32_t rxdw4; 1091 uint32_t rxdw5; 1092} __packed __attribute__((aligned(4))); 1093 1094/* Rx PHY descriptor. / 1095struct r92c_rx_phystat { 1096* uint32_t phydw0; 1097 uint32_t phydw1; 1098 uint32_t phydw2; 1099 uint32_t phydw3; 1100 uint32_t phydw4; 1101 uint32_t phydw5; 1102 uint32_t phydw6; 1103 uint32_t phydw7; 1104} __packed __attribute__((aligned(4))); 1105 1106/* Rx PHY CCK descriptor. / 1107struct r92c_rx_cck { 1108* uint8_t adc_pwdb[4]; 1109 uint8_t sq_rpt; 1110 uint8_t agc_rpt; 1111} __packed; 1112 1113struct r88e_rx_cck { 1114 uint8_t path_agc[2]; 1115 uint8_t chan; 1116 uint8_t reserved1; 1117 uint8_t sig_qual; 1118 uint8_t agc_rpt; 1119 uint8_t rpt_b; 1120 uint8_t reserved2; 1121 uint8_t noise_power; 1122 uint8_t path_cfotail[2]; 1123 uint8_t pcts_mask[2]; 1124 uint8_t stream_rxevm[2]; 1125 uint8_t path_rxsnr[2]; 1126 uint8_t noise_power_db_lsb; 1127 uint8_t reserved3[3]; 1128 uint8_t stream_csi[2]; 1129 uint8_t stream_target_csi[2]; 1130 uint8_t sig_evm; 1131} __packed; 1132 1133/* Tx MAC descriptor. / 1134struct r92c_tx_desc { 1135* uint32_t txdw0; 1136#define R92C_TXDW0_PKTLEN_M 0x0000ffff 1137#define R92C_TXDW0_PKTLEN_S 0 1138#define R92C_TXDW0_OFFSET_M 0x00ff0000 1139#define R92C_TXDW0_OFFSET_S 16 1140#define R92C_TXDW0_BMCAST 0x01000000 1141#define R92C_TXDW0_LSG 0x04000000 1142#define R92C_TXDW0_FSG 0x08000000 1143#define R92C_TXDW0_OWN 0x80000000 1144 1145 uint32_t txdw1; 1146#define R92C_TXDW1_MACID_M 0x0000001f 1147#define R92C_TXDW1_MACID_S 0 1148#define R88E_TXDW1_MACID_M 0x0000003f 1149#define R88E_TXDW1_MACID_S 0 1150#define R92C_TXDW1_AGGEN 0x00000020 1151#define R92C_TXDW1_AGGBK 0x00000040 1152#define R92C_TXDW1_QSEL_M 0x00001f00 1153#define R92C_TXDW1_QSEL_S 8 1154 1155#define R92C_TXDW1_QSEL_BE 0x00 /* or 0x03 / 1156#define R92C_TXDW1_QSEL_BK 0x01 / or 0x02 / 1157#define R92C_TXDW1_QSEL_VI 0x04 / or 0x05 / 1158#define R92C_TXDW1_QSEL_VO 0x06 / or 0x07 / 1159#define URTWN_MAX_TID 8 1160* 1161#define R92C_TXDW1_QSEL_BEACON 0x10 1162#define R92C_TXDW1_QSEL_MGNT 0x12 1163 1164#define R92C_TXDW1_RAID_M 0x000f0000 1165#define R92C_TXDW1_RAID_S 16 1166#define R92C_TXDW1_CIPHER_M 0x00c00000 1167#define R92C_TXDW1_CIPHER_S 22 1168#define R92C_TXDW1_CIPHER_NONE 0 1169#define R92C_TXDW1_CIPHER_RC4 1 1170#define R92C_TXDW1_CIPHER_AES 3 1171#define R92C_TXDW1_PKTOFF_M 0x7c000000 1172#define R92C_TXDW1_PKTOFF_S 26 1173 1174 uint32_t txdw2; 1175#define R88E_TXDW2_AGGBK 0x00010000 1176#define R88E_TXDW2_CCX_RPT 0x00080000 1177 1178 uint16_t txdw3; 1179 uint16_t txdseq; 1180#define R88E_TXDSEQ_HWSEQ_EN 0x8000 1181 1182 uint32_t txdw4; 1183#define R92C_TXDW4_RTSRATE_M 0x0000003f 1184#define R92C_TXDW4_RTSRATE_S 0 1185#define R92C_TXDW4_HWSEQ_QOS 0x00000040 1186#define R92C_TXDW4_HWSEQ_EN 0x00000080 1187#define R92C_TXDW4_DRVRATE 0x00000100 1188#define R92C_TXDW4_CTS2SELF 0x00000800 1189#define R92C_TXDW4_RTSEN 0x00001000 1190#define R92C_TXDW4_HWRTSEN 0x00002000 1191#define R92C_TXDW4_SCO_M 0x003f0000 1192#define R92C_TXDW4_SCO_S 20 1193#define R92C_TXDW4_SCO_SCA 1 1194#define R92C_TXDW4_SCO_SCB 2 1195#define R92C_TXDW4_40MHZ 0x02000000 1196 1197 uint32_t txdw5; 1198#define R92C_TXDW5_DATARATE_M 0x0000003f 1199#define R92C_TXDW5_DATARATE_S 0 1200#define R92C_TXDW5_SGI 0x00000040 1201#define R92C_TXDW5_RTY_LMT_ENA 0x00020000 1202#define R92C_TXDW5_RTY_LMT_M 0x00fc0000 1203#define R92C_TXDW5_RTY_LMT_S 18 1204#define R92C_TXDW5_AGGNUM_M 0xff000000 1205#define R92C_TXDW5_AGGNUM_S 24 1206 1207 uint32_t txdw6; 1208 uint16_t txdsum; 1209 uint16_t pad; 1210} __packed __attribute__((aligned(4))); 1211 1212struct r88e_tx_rpt_ccx { 1213 uint8_t rptb0; 1214 uint8_t rptb1; 1215#define R88E_RPTB1_MACID_M 0x3f 1216#define R88E_RPTB1_MACID_S 0 1217#define R88E_RPTB1_PKT_OK 0x40 1218#define R88E_RPTB1_BMC 0x80 1219 1220 uint8_t rptb2; 1221#define R88E_RPTB2_RETRY_CNT_M 0x3f 1222#define R88E_RPTB2_RETRY_CNT_S 0 1223#define R88E_RPTB2_LIFE_EXPIRE 0x40 1224#define R88E_RPTB2_RETRY_OVER 0x80 1225 1226 uint8_t rptb3; 1227 uint8_t rptb4; 1228 uint8_t rptb5; 1229 uint8_t rptb6; 1230#define R88E_RPTB6_QSEL_M 0xf0 1231#define R88E_RPTB6_QSEL_S 4 1232 1233 uint8_t rptb7; 1234} __packed; 1235 1236 1237static const uint8_t ridx2rate[] = 1238 { 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108 }; 1239 1240/* HW rate indices. / 1241#define URTWN_RIDX_CCK1 0 1242#define URTWN_RIDX_CCK11 3 1243#define URTWN_RIDX_OFDM6 4 1244#define URTWN_RIDX_OFDM24 8 1245#define URTWN_RIDX_OFDM54 11 1246* 1247#define URTWN_RIDX_COUNT 28 1248#define URTWN_RIDX_UNKNOWN (uint8_t)-1 1249 1250 1251/* 1252 * MAC initialization values. 1253 / 1254static const struct { 1255* uint16_t reg; 1256 uint8_t val; 1257} rtl8188eu_mac[] = { 1258 { 0x026, 0x41 }, { 0x027, 0x35 }, { 0x040, 0x00 }, { 0x428, 0x0a }, 1259 { 0x429, 0x10 }, { 0x430, 0x00 }, { 0x431, 0x01 }, { 0x432, 0x02 }, 1260 { 0x433, 0x04 }, { 0x434, 0x05 }, { 0x435, 0x06 }, { 0x436, 0x07 }, 1261 { 0x437, 0x08 }, { 0x438, 0x00 }, { 0x439, 0x00 }, { 0x43a, 0x01 }, 1262 { 0x43b, 0x02 }, { 0x43c, 0x04 }, { 0x43d, 0x05 }, { 0x43e, 0x06 }, 1263 { 0x43f, 0x07 }, { 0x440, 0x5d }, { 0x441, 0x01 }, { 0x442, 0x00 }, 1264 { 0x444, 0x15 }, { 0x445, 0xf0 }, { 0x446, 0x0f }, { 0x447, 0x00 }, 1265 { 0x458, 0x41 }, { 0x459, 0xa8 }, { 0x45a, 0x72 }, { 0x45b, 0xb9 }, 1266 { 0x460, 0x66 }, { 0x461, 0x66 }, { 0x480, 0x08 }, { 0x4c8, 0xff }, 1267 { 0x4c9, 0x08 }, { 0x4cc, 0xff }, { 0x4cd, 0xff }, { 0x4ce, 0x01 }, 1268 { 0x4d3, 0x01 }, { 0x500, 0x26 }, { 0x501, 0xa2 }, { 0x502, 0x2f }, 1269 { 0x503, 0x00 }, { 0x504, 0x28 }, { 0x505, 0xa3 }, { 0x506, 0x5e }, 1270 { 0x507, 0x00 }, { 0x508, 0x2b }, { 0x509, 0xa4 }, { 0x50a, 0x5e }, 1271 { 0x50b, 0x00 }, { 0x50c, 0x4f }, { 0x50d, 0xa4 }, { 0x50e, 0x00 }, 1272 { 0x50f, 0x00 }, { 0x512, 0x1c }, { 0x514, 0x0a }, { 0x516, 0x0a }, 1273 { 0x525, 0x4f }, { 0x550, 0x10 }, { 0x551, 0x10 }, { 0x559, 0x02 }, 1274 { 0x55d, 0xff }, { 0x605, 0x30 }, { 0x608, 0x0e }, { 0x609, 0x2a }, 1275 { 0x620, 0xff }, { 0x621, 0xff }, { 0x622, 0xff }, { 0x623, 0xff }, 1276 { 0x624, 0xff }, { 0x625, 0xff }, { 0x626, 0xff }, { 0x627, 0xff }, 1277 { 0x652, 0x20 }, { 0x63c, 0x0a }, { 0x63d, 0x0a }, { 0x63e, 0x0e }, 1278 { 0x63f, 0x0e }, { 0x640, 0x40 }, { 0x66e, 0x05 }, { 0x700, 0x21 }, 1279 { 0x701, 0x43 }, { 0x702, 0x65 }, { 0x703, 0x87 }, { 0x708, 0x21 }, 1280 { 0x709, 0x43 }, { 0x70a, 0x65 }, { 0x70b, 0x87 } 1281}, rtl8192cu_mac[] = { 1282 { 0x420, 0x80 }, { 0x423, 0x00 }, { 0x430, 0x00 }, { 0x431, 0x00 }, 1283 { 0x432, 0x00 }, { 0x433, 0x01 }, { 0x434, 0x04 }, { 0x435, 0x05 }, 1284 { 0x436, 0x06 }, { 0x437, 0x07 }, { 0x438, 0x00 }, { 0x439, 0x00 }, 1285 { 0x43a, 0x00 }, { 0x43b, 0x01 }, { 0x43c, 0x04 }, { 0x43d, 0x05 }, 1286 { 0x43e, 0x06 }, { 0x43f, 0x07 }, { 0x440, 0x5d }, { 0x441, 0x01 }, 1287 { 0x442, 0x00 }, { 0x444, 0x15 }, { 0x445, 0xf0 }, { 0x446, 0x0f }, 1288 { 0x447, 0x00 }, { 0x458, 0x41 }, { 0x459, 0xa8 }, { 0x45a, 0x72 }, 1289 { 0x45b, 0xb9 }, { 0x460, 0x66 }, { 0x461, 0x66 }, { 0x462, 0x08 }, 1290 { 0x463, 0x03 }, { 0x4c8, 0xff }, { 0x4c9, 0x08 }, { 0x4cc, 0xff }, 1291 { 0x4cd, 0xff }, { 0x4ce, 0x01 }, { 0x500, 0x26 }, { 0x501, 0xa2 }, 1292 { 0x502, 0x2f }, { 0x503, 0x00 }, { 0x504, 0x28 }, { 0x505, 0xa3 }, 1293 { 0x506, 0x5e }, { 0x507, 0x00 }, { 0x508, 0x2b }, { 0x509, 0xa4 }, 1294 { 0x50a, 0x5e }, { 0x50b, 0x00 }, { 0x50c, 0x4f }, { 0x50d, 0xa4 }, 1295 { 0x50e, 0x00 }, { 0x50f, 0x00 }, { 0x512, 0x1c }, { 0x514, 0x0a }, 1296 { 0x515, 0x10 }, { 0x516, 0x0a }, { 0x517, 0x10 }, { 0x51a, 0x16 }, 1297 { 0x524, 0x0f }, { 0x525, 0x4f }, { 0x546, 0x40 }, { 0x547, 0x00 }, 1298 { 0x550, 0x10 }, { 0x551, 0x10 }, { 0x559, 0x02 }, { 0x55a, 0x02 }, 1299 { 0x55d, 0xff }, { 0x605, 0x30 }, { 0x608, 0x0e }, { 0x609, 0x2a }, 1300 { 0x652, 0x20 }, { 0x63c, 0x0a }, { 0x63d, 0x0e }, { 0x63e, 0x0a }, 1301 { 0x63f, 0x0e }, { 0x66e, 0x05 }, { 0x700, 0x21 }, { 0x701, 0x43 }, 1302 { 0x702, 0x65 }, { 0x703, 0x87 }, { 0x708, 0x21 }, { 0x709, 0x43 }, 1303 { 0x70a, 0x65 }, { 0x70b, 0x87 } 1304}; 1305 1306/* 1307 * Baseband initialization values. 1308 / 1309struct urtwn_bb_prog { 1310* int count; 1311 const uint16_t regs; 1312* const uint32_t vals; 1313* int agccount; 1314 const uint32_t agcvals; 1315}; 1316* 1317/* 1318 * RTL8192CU and RTL8192CE-VAU. 1319 / 1320static const uint16_t rtl8192ce_bb_regs[] = { 1321* 0x024, 0x028, 0x800, 0x804, 0x808, 0x80c, 0x810, 0x814, 0x818, 1322 0x81c, 0x820, 0x824, 0x828, 0x82c, 0x830, 0x834, 0x838, 0x83c, 1323 0x840, 0x844, 0x848, 0x84c, 0x850, 0x854, 0x858, 0x85c, 0x860, 1324 0x864, 0x868, 0x86c, 0x870, 0x874, 0x878, 0x87c, 0x880, 0x884, 1325 0x888, 0x88c, 0x890, 0x894, 0x898, 0x89c, 0x900, 0x904, 0x908, 1326 0x90c, 0xa00, 0xa04, 0xa08, 0xa0c, 0xa10, 0xa14, 0xa18, 0xa1c, 1327 0xa20, 0xa24, 0xa28, 0xa2c, 0xa70, 0xa74, 0xc00, 0xc04, 0xc08, 1328 0xc0c, 0xc10, 0xc14, 0xc18, 0xc1c, 0xc20, 0xc24, 0xc28, 0xc2c, 1329 0xc30, 0xc34, 0xc38, 0xc3c, 0xc40, 0xc44, 0xc48, 0xc4c, 0xc50, 1330 0xc54, 0xc58, 0xc5c, 0xc60, 0xc64, 0xc68, 0xc6c, 0xc70, 0xc74, 1331 0xc78, 0xc7c, 0xc80, 0xc84, 0xc88, 0xc8c, 0xc90, 0xc94, 0xc98, 1332 0xc9c, 0xca0, 0xca4, 0xca8, 0xcac, 0xcb0, 0xcb4, 0xcb8, 0xcbc, 1333 0xcc0, 0xcc4, 0xcc8, 0xccc, 0xcd0, 0xcd4, 0xcd8, 0xcdc, 0xce0, 1334 0xce4, 0xce8, 0xcec, 0xd00, 0xd04, 0xd08, 0xd0c, 0xd10, 0xd14, 1335 0xd18, 0xd2c, 0xd30, 0xd34, 0xd38, 0xd3c, 0xd40, 0xd44, 0xd48, 1336 0xd4c, 0xd50, 0xd54, 0xd58, 0xd5c, 0xd60, 0xd64, 0xd68, 0xd6c, 1337 0xd70, 0xd74, 0xd78, 0xe00, 0xe04, 0xe08, 0xe10, 0xe14, 0xe18, 1338 0xe1c, 0xe28, 0xe30, 0xe34, 0xe38, 0xe3c, 0xe40, 0xe44, 0xe48, 1339 0xe4c, 0xe50, 0xe54, 0xe58, 0xe5c, 0xe60, 0xe68, 0xe6c, 0xe70, 1340 0xe74, 0xe78, 0xe7c, 0xe80, 0xe84, 0xe88, 0xe8c, 0xed0, 0xed4, 1341 0xed8, 0xedc, 0xee0, 0xeec, 0xf14, 0xf4c, 0xf00 1342}; 1343 1344static const uint32_t rtl8192ce_bb_vals[] = { 1345 0x0011800d, 0x00ffdb83, 0x80040002, 0x00000003, 0x0000fc00, 1346 0x0000000a, 0x10005388, 0x020c3d10, 0x02200385, 0x00000000, 1347 0x01000100, 0x00390004, 0x01000100, 0x00390004, 0x27272727, 1348 0x27272727, 0x27272727, 0x27272727, 0x00010000, 0x00010000, 1349 0x27272727, 0x27272727, 0x00000000, 0x00000000, 0x569a569a, 1350 0x0c1b25a4, 0x66e60230, 0x061f0130, 0x27272727, 0x2b2b2b27, 1351 0x07000700, 0x22184000, 0x08080808, 0x00000000, 0xc0083070, 1352 0x000004d5, 0x00000000, 0xcc0000c0, 0x00000800, 0xfffffffe, 1353 0x40302010, 0x00706050, 0x00000000, 0x00000023, 0x00000000, 1354 0x81121313, 0x00d047c8, 0x80ff000c, 0x8c838300, 0x2e68120f, 1355 0x9500bb78, 0x11144028, 0x00881117, 0x89140f00, 0x1a1b0000, 1356 0x090e1317, 0x00000204, 0x00d30000, 0x101fbf00, 0x00000007, 1357 0x48071d40, 0x03a05633, 0x000000e4, 0x6c6c6c6c, 0x08800000, 1358 0x40000100, 0x08800000, 0x40000100, 0x00000000, 0x00000000, 1359 0x00000000, 0x00000000, 0x69e9ac44, 0x469652cf, 0x49795994, 1360 0x0a97971c, 0x1f7c403f, 0x000100b7, 0xec020107, 0x007f037f, 1361 0x6954341e, 0x43bc0094, 0x6954341e, 0x433c0094, 0x00000000, 1362 0x5116848b, 0x47c00bff, 0x00000036, 0x2c7f000d, 0x018610db, 1363 0x0000001f, 0x00b91612, 0x40000100, 0x20f60000, 0x40000100, 1364 0x20200000, 0x00121820, 0x00000000, 0x00121820, 0x00007f7f, 1365 0x00000000, 0x00000080, 0x00000000, 0x00000000, 0x00000000, 1366 0x00000000, 0x00000000, 0x28000000, 0x00000000, 0x00000000, 1367 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x64b22427, 1368 0x00766932, 0x00222222, 0x00000000, 0x37644302, 0x2f97d40c, 1369 0x00080740, 0x00020403, 0x0000907f, 0x20010201, 0xa0633333, 1370 0x3333bc43, 0x7a8f5b6b, 0xcc979975, 0x00000000, 0x80608000, 1371 0x00000000, 0x00027293, 0x00000000, 0x00000000, 0x00000000, 1372 0x00000000, 0x6437140a, 0x00000000, 0x00000000, 0x30032064, 1373 0x4653de68, 0x04518a3c, 0x00002101, 0x2a201c16, 0x1812362e, 1374 0x322c2220, 0x000e3c24, 0x2a2a2a2a, 0x2a2a2a2a, 0x03902a2a, 1375 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x00000000, 1376 0x1000dc1f, 0x10008c1f, 0x02140102, 0x681604c2, 0x01007c00, 1377 0x01004800, 0xfb000000, 0x000028d1, 0x1000dc1f, 0x10008c1f, 1378 0x02140102, 0x28160d05, 0x00000010, 0x001b25a4, 0x63db25a4, 1379 0x63db25a4, 0x0c1b25a4, 0x0c1b25a4, 0x0c1b25a4, 0x0c1b25a4, 1380 0x63db25a4, 0x0c1b25a4, 0x63db25a4, 0x63db25a4, 0x63db25a4, 1381 0x63db25a4, 0x001b25a4, 0x001b25a4, 0x6fdb25a4, 0x00000003, 1382 0x00000000, 0x00000300 1383}; 1384 1385static const uint32_t rtl8192ce_agc_vals[] = { 1386 0x7b000001, 0x7b010001, 0x7b020001, 0x7b030001, 0x7b040001, 1387 0x7b050001, 0x7a060001, 0x79070001, 0x78080001, 0x77090001, 1388 0x760a0001, 0x750b0001, 0x740c0001, 0x730d0001, 0x720e0001, 1389 0x710f0001, 0x70100001, 0x6f110001, 0x6e120001, 0x6d130001, 1390 0x6c140001, 0x6b150001, 0x6a160001, 0x69170001, 0x68180001, 1391 0x67190001, 0x661a0001, 0x651b0001, 0x641c0001, 0x631d0001, 1392 0x621e0001, 0x611f0001, 0x60200001, 0x49210001, 0x48220001, 1393 0x47230001, 0x46240001, 0x45250001, 0x44260001, 0x43270001, 1394 0x42280001, 0x41290001, 0x402a0001, 0x262b0001, 0x252c0001, 1395 0x242d0001, 0x232e0001, 0x222f0001, 0x21300001, 0x20310001, 1396 0x06320001, 0x05330001, 0x04340001, 0x03350001, 0x02360001, 1397 0x01370001, 0x00380001, 0x00390001, 0x003a0001, 0x003b0001, 1398 0x003c0001, 0x003d0001, 0x003e0001, 0x003f0001, 0x7b400001, 1399 0x7b410001, 0x7b420001, 0x7b430001, 0x7b440001, 0x7b450001, 1400 0x7a460001, 0x79470001, 0x78480001, 0x77490001, 0x764a0001, 1401 0x754b0001, 0x744c0001, 0x734d0001, 0x724e0001, 0x714f0001, 1402 0x70500001, 0x6f510001, 0x6e520001, 0x6d530001, 0x6c540001, 1403 0x6b550001, 0x6a560001, 0x69570001, 0x68580001, 0x67590001, 1404 0x665a0001, 0x655b0001, 0x645c0001, 0x635d0001, 0x625e0001, 1405 0x615f0001, 0x60600001, 0x49610001, 0x48620001, 0x47630001, 1406 0x46640001, 0x45650001, 0x44660001, 0x43670001, 0x42680001, 1407 0x41690001, 0x406a0001, 0x266b0001, 0x256c0001, 0x246d0001, 1408 0x236e0001, 0x226f0001, 0x21700001, 0x20710001, 0x06720001, 1409 0x05730001, 0x04740001, 0x03750001, 0x02760001, 0x01770001, 1410 0x00780001, 0x00790001, 0x007a0001, 0x007b0001, 0x007c0001, 1411 0x007d0001, 0x007e0001, 0x007f0001, 0x3800001e, 0x3801001e, 1412 0x3802001e, 0x3803001e, 0x3804001e, 0x3805001e, 0x3806001e, 1413 0x3807001e, 0x3808001e, 0x3c09001e, 0x3e0a001e, 0x400b001e, 1414 0x440c001e, 0x480d001e, 0x4c0e001e, 0x500f001e, 0x5210001e, 1415 0x5611001e, 0x5a12001e, 0x5e13001e, 0x6014001e, 0x6015001e, 1416 0x6016001e, 0x6217001e, 0x6218001e, 0x6219001e, 0x621a001e, 1417 0x621b001e, 0x621c001e, 0x621d001e, 0x621e001e, 0x621f001e 1418}; 1419 1420static const struct urtwn_bb_prog rtl8192ce_bb_prog = { 1421 nitems(rtl8192ce_bb_regs), 1422 rtl8192ce_bb_regs, 1423 rtl8192ce_bb_vals, 1424 nitems(rtl8192ce_agc_vals), 1425 rtl8192ce_agc_vals 1426}; 1427 1428/* 1429 * RTL8188CU. 1430 / 1431static const uint32_t rtl8192cu_bb_vals[] = { 1432* 0x0011800d, 0x00ffdb83, 0x80040002, 0x00000003, 0x0000fc00, 1433 0x0000000a, 0x10005388, 0x020c3d10, 0x02200385, 0x00000000, 1434 0x01000100, 0x00390004, 0x01000100, 0x00390004, 0x27272727, 1435 0x27272727, 0x27272727, 0x27272727, 0x00010000, 0x00010000, 1436 0x27272727, 0x27272727, 0x00000000, 0x00000000, 0x569a569a, 1437 0x0c1b25a4, 0x66e60230, 0x061f0130, 0x27272727, 0x2b2b2b27, 1438 0x07000700, 0x22184000, 0x08080808, 0x00000000, 0xc0083070, 1439 0x000004d5, 0x00000000, 0xcc0000c0, 0x00000800, 0xfffffffe, 1440 0x40302010, 0x00706050, 0x00000000, 0x00000023, 0x00000000, 1441 0x81121313, 0x00d047c8, 0x80ff000c, 0x8c838300, 0x2e68120f, 1442 0x9500bb78, 0x11144028, 0x00881117, 0x89140f00, 0x1a1b0000, 1443 0x090e1317, 0x00000204, 0x00d30000, 0x101fbf00, 0x00000007, 1444 0x48071d40, 0x03a05633, 0x000000e4, 0x6c6c6c6c, 0x08800000, 1445 0x40000100, 0x08800000, 0x40000100, 0x00000000, 0x00000000, 1446 0x00000000, 0x00000000, 0x69e9ac44, 0x469652cf, 0x49795994, 1447 0x0a97971c, 0x1f7c403f, 0x000100b7, 0xec020107, 0x007f037f, 1448 0x6954341e, 0x43bc0094, 0x6954341e, 0x433c0094, 0x00000000, 1449 0x5116848b, 0x47c00bff, 0x00000036, 0x2c7f000d, 0x0186115b, 1450 0x0000001f, 0x00b99612, 0x40000100, 0x20f60000, 0x40000100, 1451 0x20200000, 0x00121820, 0x00000000, 0x00121820, 0x00007f7f, 1452 0x00000000, 0x00000080, 0x00000000, 0x00000000, 0x00000000, 1453 0x00000000, 0x00000000, 0x28000000, 0x00000000, 0x00000000, 1454 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x64b22427, 1455 0x00766932, 0x00222222, 0x00000000, 0x37644302, 0x2f97d40c, 1456 0x00080740, 0x00020403, 0x0000907f, 0x20010201, 0xa0633333, 1457 0x3333bc43, 0x7a8f5b6b, 0xcc979975, 0x00000000, 0x80608000, 1458 0x00000000, 0x00027293, 0x00000000, 0x00000000, 0x00000000, 1459 0x00000000, 0x6437140a, 0x00000000, 0x00000000, 0x30032064, 1460 0x4653de68, 0x04518a3c, 0x00002101, 0x2a201c16, 0x1812362e, 1461 0x322c2220, 0x000e3c24, 0x2a2a2a2a, 0x2a2a2a2a, 0x03902a2a, 1462 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x00000000, 1463 0x1000dc1f, 0x10008c1f, 0x02140102, 0x681604c2, 0x01007c00, 1464 0x01004800, 0xfb000000, 0x000028d1, 0x1000dc1f, 0x10008c1f, 1465 0x02140102, 0x28160d05, 0x00000010, 0x001b25a4, 0x63db25a4, 1466 0x63db25a4, 0x0c1b25a4, 0x0c1b25a4, 0x0c1b25a4, 0x0c1b25a4, 1467 0x63db25a4, 0x0c1b25a4, 0x63db25a4, 0x63db25a4, 0x63db25a4, 1468 0x63db25a4, 0x001b25a4, 0x001b25a4, 0x6fdb25a4, 0x00000003, 1469 0x00000000, 0x00000300 1470}; 1471 1472static const struct urtwn_bb_prog rtl8192cu_bb_prog = { 1473 nitems(rtl8192ce_bb_regs), 1474 rtl8192ce_bb_regs, 1475 rtl8192cu_bb_vals, 1476 nitems(rtl8192ce_agc_vals), 1477 rtl8192ce_agc_vals 1478}; 1479 1480/* 1481 * RTL8188CE-VAU. 1482 / 1483static const uint32_t rtl8188ce_bb_vals[] = { 1484* 0x0011800d, 0x00ffdb83, 0x80040000, 0x00000001, 0x0000fc00, 1485 0x0000000a, 0x10005388, 0x020c3d10, 0x02200385, 0x00000000, 1486 0x01000100, 0x00390004, 0x00000000, 0x00000000, 0x00000000, 1487 0x00000000, 0x00000000, 0x00000000, 0x00010000, 0x00000000, 1488 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x569a569a, 1489 0x001b25a4, 0x66e60230, 0x061f0130, 0x00000000, 0x32323200, 1490 0x07000700, 0x22004000, 0x00000808, 0x00000000, 0xc0083070, 1491 0x000004d5, 0x00000000, 0xccc000c0, 0x00000800, 0xfffffffe, 1492 0x40302010, 0x00706050, 0x00000000, 0x00000023, 0x00000000, 1493 0x81121111, 0x00d047c8, 0x80ff000c, 0x8c838300, 0x2e68120f, 1494 0x9500bb78, 0x11144028, 0x00881117, 0x89140f00, 0x1a1b0000, 1495 0x090e1317, 0x00000204, 0x00d30000, 0x101fbf00, 0x00000007, 1496 0x48071d40, 0x03a05611, 0x000000e4, 0x6c6c6c6c, 0x08800000, 1497 0x40000100, 0x08800000, 0x40000100, 0x00000000, 0x00000000, 1498 0x00000000, 0x00000000, 0x69e9ac44, 0x469652cf, 0x49795994, 1499 0x0a97971c, 0x1f7c403f, 0x000100b7, 0xec020107, 0x007f037f, 1500 0x6954341e, 0x43bc0094, 0x6954341e, 0x433c0094, 0x00000000, 1501 0x5116848b, 0x47c00bff, 0x00000036, 0x2c7f000d, 0x018610db, 1502 0x0000001f, 0x00b91612, 0x40000100, 0x20f60000, 0x40000100, 1503 0x20200000, 0x00121820, 0x00000000, 0x00121820, 0x00007f7f, 1504 0x00000000, 0x00000080, 0x00000000, 0x00000000, 0x00000000, 1505 0x00000000, 0x00000000, 0x28000000, 0x00000000, 0x00000000, 1506 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x64b22427, 1507 0x00766932, 0x00222222, 0x00000000, 0x37644302, 0x2f97d40c, 1508 0x00080740, 0x00020401, 0x0000907f, 0x20010201, 0xa0633333, 1509 0x3333bc43, 0x7a8f5b6b, 0xcc979975, 0x00000000, 0x80608000, 1510 0x00000000, 0x00027293, 0x00000000, 0x00000000, 0x00000000, 1511 0x00000000, 0x6437140a, 0x00000000, 0x00000000, 0x30032064, 1512 0x4653de68, 0x04518a3c, 0x00002101, 0x2a201c16, 0x1812362e, 1513 0x322c2220, 0x000e3c24, 0x2a2a2a2a, 0x2a2a2a2a, 0x03902a2a, 1514 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x00000000, 1515 0x1000dc1f, 0x10008c1f, 0x02140102, 0x681604c2, 0x01007c00, 1516 0x01004800, 0xfb000000, 0x000028d1, 0x1000dc1f, 0x10008c1f, 1517 0x02140102, 0x28160d05, 0x00000008, 0x001b25a4, 0x631b25a0, 1518 0x631b25a0, 0x081b25a0, 0x081b25a0, 0x081b25a0, 0x081b25a0, 1519 0x631b25a0, 0x081b25a0, 0x631b25a0, 0x631b25a0, 0x631b25a0, 1520 0x631b25a0, 0x001b25a0, 0x001b25a0, 0x6b1b25a0, 0x00000003, 1521 0x00000000, 0x00000300 1522}; 1523 1524static const uint32_t rtl8188ce_agc_vals[] = { 1525 0x7b000001, 0x7b010001, 0x7b020001, 0x7b030001, 0x7b040001, 1526 0x7b050001, 0x7a060001, 0x79070001, 0x78080001, 0x77090001, 1527 0x760a0001, 0x750b0001, 0x740c0001, 0x730d0001, 0x720e0001, 1528 0x710f0001, 0x70100001, 0x6f110001, 0x6e120001, 0x6d130001, 1529 0x6c140001, 0x6b150001, 0x6a160001, 0x69170001, 0x68180001, 1530 0x67190001, 0x661a0001, 0x651b0001, 0x641c0001, 0x631d0001, 1531 0x621e0001, 0x611f0001, 0x60200001, 0x49210001, 0x48220001, 1532 0x47230001, 0x46240001, 0x45250001, 0x44260001, 0x43270001, 1533 0x42280001, 0x41290001, 0x402a0001, 0x262b0001, 0x252c0001, 1534 0x242d0001, 0x232e0001, 0x222f0001, 0x21300001, 0x20310001, 1535 0x06320001, 0x05330001, 0x04340001, 0x03350001, 0x02360001, 1536 0x01370001, 0x00380001, 0x00390001, 0x003a0001, 0x003b0001, 1537 0x003c0001, 0x003d0001, 0x003e0001, 0x003f0001, 0x7b400001, 1538 0x7b410001, 0x7b420001, 0x7b430001, 0x7b440001, 0x7b450001, 1539 0x7a460001, 0x79470001, 0x78480001, 0x77490001, 0x764a0001, 1540 0x754b0001, 0x744c0001, 0x734d0001, 0x724e0001, 0x714f0001, 1541 0x70500001, 0x6f510001, 0x6e520001, 0x6d530001, 0x6c540001, 1542 0x6b550001, 0x6a560001, 0x69570001, 0x68580001, 0x67590001, 1543 0x665a0001, 0x655b0001, 0x645c0001, 0x635d0001, 0x625e0001, 1544 0x615f0001, 0x60600001, 0x49610001, 0x48620001, 0x47630001, 1545 0x46640001, 0x45650001, 0x44660001, 0x43670001, 0x42680001, 1546 0x41690001, 0x406a0001, 0x266b0001, 0x256c0001, 0x246d0001, 1547 0x236e0001, 0x226f0001, 0x21700001, 0x20710001, 0x06720001, 1548 0x05730001, 0x04740001, 0x03750001, 0x02760001, 0x01770001, 1549 0x00780001, 0x00790001, 0x007a0001, 0x007b0001, 0x007c0001, 1550 0x007d0001, 0x007e0001, 0x007f0001, 0x3800001e, 0x3801001e, 1551 0x3802001e, 0x3803001e, 0x3804001e, 0x3805001e, 0x3806001e, 1552 0x3807001e, 0x3808001e, 0x3c09001e, 0x3e0a001e, 0x400b001e, 1553 0x440c001e, 0x480d001e, 0x4c0e001e, 0x500f001e, 0x5210001e, 1554 0x5611001e, 0x5a12001e, 0x5e13001e, 0x6014001e, 0x6015001e, 1555 0x6016001e, 0x6217001e, 0x6218001e, 0x6219001e, 0x621a001e, 1556 0x621b001e, 0x621c001e, 0x621d001e, 0x621e001e, 0x621f001e 1557}; 1558 1559static const struct urtwn_bb_prog rtl8188ce_bb_prog = { 1560 nitems(rtl8192ce_bb_regs), 1561 rtl8192ce_bb_regs, 1562 rtl8188ce_bb_vals, 1563 nitems(rtl8188ce_agc_vals), 1564 rtl8188ce_agc_vals 1565}; 1566 1567static const uint32_t rtl8188cu_bb_vals[] = { 1568 0x0011800d, 0x00ffdb83, 0x80040000, 0x00000001, 0x0000fc00, 1569 0x0000000a, 0x10005388, 0x020c3d10, 0x02200385, 0x00000000, 1570 0x01000100, 0x00390004, 0x00000000, 0x00000000, 0x00000000, 1571 0x00000000, 0x00000000, 0x00000000, 0x00010000, 0x00000000, 1572 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x569a569a, 1573 0x001b25a4, 0x66e60230, 0x061f0130, 0x00000000, 0x32323200, 1574 0x07000700, 0x22004000, 0x00000808, 0x00000000, 0xc0083070, 1575 0x000004d5, 0x00000000, 0xccc000c0, 0x00000800, 0xfffffffe, 1576 0x40302010, 0x00706050, 0x00000000, 0x00000023, 0x00000000, 1577 0x81121111, 0x00d047c8, 0x80ff000c, 0x8c838300, 0x2e68120f, 1578 0x9500bb78, 0x11144028, 0x00881117, 0x89140f00, 0x1a1b0000, 1579 0x090e1317, 0x00000204, 0x00d30000, 0x101fbf00, 0x00000007, 1580 0x48071d40, 0x03a05611, 0x000000e4, 0x6c6c6c6c, 0x08800000, 1581 0x40000100, 0x08800000, 0x40000100, 0x00000000, 0x00000000, 1582 0x00000000, 0x00000000, 0x69e9ac44, 0x469652cf, 0x49795994, 1583 0x0a97971c, 0x1f7c403f, 0x000100b7, 0xec020107, 0x007f037f, 1584 0x6954341e, 0x43bc0094, 0x6954341e, 0x433c0094, 0x00000000, 1585 0x5116848b, 0x47c00bff, 0x00000036, 0x2c7f000d, 0x018610db, 1586 0x0000001f, 0x00b91612, 0x40000100, 0x20f60000, 0x40000100, 1587 0x20200000, 0x00121820, 0x00000000, 0x00121820, 0x00007f7f, 1588 0x00000000, 0x00000080, 0x00000000, 0x00000000, 0x00000000, 1589 0x00000000, 0x00000000, 0x28000000, 0x00000000, 0x00000000, 1590 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x64b22427, 1591 0x00766932, 0x00222222, 0x00000000, 0x37644302, 0x2f97d40c, 1592 0x00080740, 0x00020401, 0x0000907f, 0x20010201, 0xa0633333, 1593 0x3333bc43, 0x7a8f5b6b, 0xcc979975, 0x00000000, 0x80608000, 1594 0x00000000, 0x00027293, 0x00000000, 0x00000000, 0x00000000, 1595 0x00000000, 0x6437140a, 0x00000000, 0x00000000, 0x30032064, 1596 0x4653de68, 0x04518a3c, 0x00002101, 0x2a201c16, 0x1812362e, 1597 0x322c2220, 0x000e3c24, 0x2a2a2a2a, 0x2a2a2a2a, 0x03902a2a, 1598 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x00000000, 1599 0x1000dc1f, 0x10008c1f, 0x02140102, 0x681604c2, 0x01007c00, 1600 0x01004800, 0xfb000000, 0x000028d1, 0x1000dc1f, 0x10008c1f, 1601 0x02140102, 0x28160d05, 0x00000008, 0x001b25a4, 0x631b25a0, 1602 0x631b25a0, 0x081b25a0, 0x081b25a0, 0x081b25a0, 0x081b25a0, 1603 0x631b25a0, 0x081b25a0, 0x631b25a0, 0x631b25a0, 0x631b25a0, 1604 0x631b25a0, 0x001b25a0, 0x001b25a0, 0x6b1b25a0, 0x00000003, 1605 0x00000000, 0x00000300 1606}; 1607 1608static const struct urtwn_bb_prog rtl8188cu_bb_prog = { 1609 nitems(rtl8192ce_bb_regs), 1610 rtl8192ce_bb_regs, 1611 rtl8188cu_bb_vals, 1612 nitems(rtl8188ce_agc_vals), 1613 rtl8188ce_agc_vals 1614}; 1615 1616/* 1617 * RTL8188EU. 1618 / 1619static const uint16_t rtl8188eu_bb_regs[] = { 1620* 0x800, 0x804, 0x808, 0x80c, 0x810, 0x814, 0x818, 0x81c, 1621 0x820, 0x824, 0x828, 0x82c, 0x830, 0x834, 0x838, 0x83c, 1622 0x840, 0x844, 0x848, 0x84c, 0x850, 0x854, 0x858, 0x85c, 1623 0x860, 0x864, 0x868, 0x86c, 0x870, 0x874, 0x878, 0x87c, 1624 0x880, 0x884, 0x888, 0x88c, 0x890, 0x894, 0x898, 0x89c, 1625 0x900, 0x904, 0x908, 0x90c, 0x910, 0x914, 0xa00, 0xa04, 1626 0xa08, 0xa0c, 0xa10, 0xa14, 0xa18, 0xa1c, 0xa20, 0xa24, 1627 0xa28, 0xa2c, 0xa70, 0xa74, 0xa78, 0xa7c, 0xa80, 0xb2c, 1628 0xc00, 0xc04, 0xc08, 0xc0c, 0xc10, 0xc14, 0xc18, 0xc1c, 1629 0xc20, 0xc24, 0xc28, 0xc2c, 0xc30, 0xc34, 0xc38, 0xc3c, 1630 0xc40, 0xc44, 0xc48, 0xc4c, 0xc50, 0xc54, 0xc58, 0xc5c, 1631 0xc60, 0xc64, 0xc68, 0xc6c, 0xc70, 0xc74, 0xc78, 0xc7c, 1632 0xc80, 0xc84, 0xc88, 0xc8c, 0xc90, 0xc94, 0xc98, 0xc9c, 1633 0xca0, 0xca4, 0xca8, 0xcac, 0xcb0, 0xcb4, 0xcb8, 0xcbc, 1634 0xcc0, 0xcc4, 0xcc8, 0xccc, 0xcd0, 0xcd4, 0xcd8, 0xcdc, 1635 0xce0, 0xce4, 0xce8, 0xcec, 0xd00, 0xd04, 0xd08, 0xd0c, 1636 0xd10, 0xd14, 0xd18, 0xd2c, 0xd30, 0xd34, 0xd38, 0xd3c, 1637 0xd40, 0xd44, 0xd48, 0xd4c, 0xd50, 0xd54, 0xd58, 0xd5c, 1638 0xd60, 0xd64, 0xd68, 0xd6c, 0xd70, 0xd74, 0xd78, 0xe00, 1639 0xe04, 0xe08, 0xe10, 0xe14, 0xe18, 0xe1c, 0xe28, 0xe30, 1640 0xe34, 0xe38, 0xe3c, 0xe40, 0xe44, 0xe48, 0xe4c, 0xe50, 1641 0xe54, 0xe58, 0xe5c, 0xe60, 0xe68, 0xe6c, 0xe70, 0xe74, 1642 0xe78, 0xe7c, 0xe80, 0xe84, 0xe88, 0xe8c, 0xed0, 0xed4, 1643 0xed8, 0xedc, 0xee0, 0xee8, 0xeec, 0xf14, 0xf4c, 0xf00 1644}; 1645 1646static const uint32_t rtl8188eu_bb_vals[] = { 1647 0x80040000, 0x00000003, 0x0000fc00, 0x0000000a, 0x10001331, 1648 0x020c3d10, 0x02200385, 0x00000000, 0x01000100, 0x00390204, 1649 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 1650 0x00000000, 0x00010000, 0x00000000, 0x00000000, 0x00000000, 1651 0x00000000, 0x00000000, 0x569a11a9, 0x01000014, 0x66f60110, 1652 0x061f0649, 0x00000000, 0x27272700, 0x07000760, 0x25004000, 1653 0x00000808, 0x00000000, 0xb0000c1c, 0x00000001, 0x00000000, 1654 0xccc000c0, 0x00000800, 0xfffffffe, 0x40302010, 0x00706050, 1655 0x00000000, 0x00000023, 0x00000000, 0x81121111, 0x00000002, 1656 0x00000201, 0x00d047c8, 0x80ff000c, 0x8c838300, 0x2e7f120f, 1657 0x9500bb78, 0x1114d028, 0x00881117, 0x89140f00, 0x1a1b0000, 1658 0x090e1317, 0x00000204, 0x00d30000, 0x101fbf00, 0x00000007, 1659 0x00000900, 0x225b0606, 0x218075b1, 0x80000000, 0x48071d40, 1660 0x03a05611, 0x000000e4, 0x6c6c6c6c, 0x08800000, 0x40000100, 1661 0x08800000, 0x40000100, 0x00000000, 0x00000000, 0x00000000, 1662 0x00000000, 0x69e9ac47, 0x469652af, 0x49795994, 0x0a97971c, 1663 0x1f7c403f, 0x000100b7, 0xec020107, 0x007f037f, 0x69553420, 1664 0x43bc0094, 0x00013169, 0x00250492, 0x00000000, 0x7112848b, 1665 0x47c00bff, 0x00000036, 0x2c7f000d, 0x020610db, 0x0000001f, 1666 0x00b91612, 0x390000e4, 0x20f60000, 0x40000100, 0x20200000, 1667 0x00091521, 0x00000000, 0x00121820, 0x00007f7f, 0x00000000, 1668 0x000300a0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 1669 0x00000000, 0x28000000, 0x00000000, 0x00000000, 0x00000000, 1670 0x00000000, 0x00000000, 0x00000000, 0x64b22427, 0x00766932, 1671 0x00222222, 0x00000000, 0x37644302, 0x2f97d40c, 0x00000740, 1672 0x00020401, 0x0000907f, 0x20010201, 0xa0633333, 0x3333bc43, 1673 0x7a8f5b6f, 0xcc979975, 0x00000000, 0x80608000, 0x00000000, 1674 0x00127353, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 1675 0x6437140a, 0x00000000, 0x00000282, 0x30032064, 0x4653de68, 1676 0x04518a3c, 0x00002101, 0x2a201c16, 0x1812362e, 0x322c2220, 1677 0x000e3c24, 0x2d2d2d2d, 0x2d2d2d2d, 0x0390272d, 0x2d2d2d2d, 1678 0x2d2d2d2d, 0x2d2d2d2d, 0x2d2d2d2d, 0x00000000, 0x1000dc1f, 1679 0x10008c1f, 0x02140102, 0x681604c2, 0x01007c00, 0x01004800, 1680 0xfb000000, 0x000028d1, 0x1000dc1f, 0x10008c1f, 0x02140102, 1681 0x28160d05, 0x00000008, 0x001b25a4, 0x00c00014, 0x00c00014, 1682 0x01000014, 0x01000014, 0x01000014, 0x01000014, 0x00c00014, 1683 0x01000014, 0x00c00014, 0x00c00014, 0x00c00014, 0x00c00014, 1684 0x00000014, 0x00000014, 0x21555448, 0x01c00014, 0x00000003, 1685 0x00000000, 0x00000300 1686}; 1687 1688static const uint32_t rtl8188eu_agc_vals[] = { 1689 0xfb000001, 0xfb010001, 0xfb020001, 0xfb030001, 0xfb040001, 1690 0xfb050001, 0xfa060001, 0xf9070001, 0xf8080001, 0xf7090001, 1691 0xf60a0001, 0xf50b0001, 0xf40c0001, 0xf30d0001, 0xf20e0001, 1692 0xf10f0001, 0xf0100001, 0xef110001, 0xee120001, 0xed130001, 1693 0xec140001, 0xeb150001, 0xea160001, 0xe9170001, 0xe8180001, 1694 0xe7190001, 0xe61a0001, 0xe51b0001, 0xe41c0001, 0xe31d0001, 1695 0xe21e0001, 0xe11f0001, 0x8a200001, 0x89210001, 0x88220001, 1696 0x87230001, 0x86240001, 0x85250001, 0x84260001, 0x83270001, 1697 0x82280001, 0x6b290001, 0x6a2a0001, 0x692b0001, 0x682c0001, 1698 0x672d0001, 0x662e0001, 0x652f0001, 0x64300001, 0x63310001, 1699 0x62320001, 0x61330001, 0x46340001, 0x45350001, 0x44360001, 1700 0x43370001, 0x42380001, 0x41390001, 0x403a0001, 0x403b0001, 1701 0x403c0001, 0x403d0001, 0x403e0001, 0x403f0001, 0xfb400001, 1702 0xfb410001, 0xfb420001, 0xfb430001, 0xfb440001, 0xfb450001, 1703 0xfb460001, 0xfb470001, 0xfb480001, 0xfa490001, 0xf94a0001, 1704 0xf84B0001, 0xf74c0001, 0xf64d0001, 0xf54e0001, 0xf44f0001, 1705 0xf3500001, 0xf2510001, 0xf1520001, 0xf0530001, 0xef540001, 1706 0xee550001, 0xed560001, 0xec570001, 0xeb580001, 0xea590001, 1707 0xe95a0001, 0xe85b0001, 0xe75c0001, 0xe65d0001, 0xe55e0001, 1708 0xe45f0001, 0xe3600001, 0xe2610001, 0xc3620001, 0xc2630001, 1709 0xc1640001, 0x8b650001, 0x8a660001, 0x89670001, 0x88680001, 1710 0x87690001, 0x866a0001, 0x856b0001, 0x846c0001, 0x676d0001, 1711 0x666e0001, 0x656f0001, 0x64700001, 0x63710001, 0x62720001, 1712 0x61730001, 0x60740001, 0x46750001, 0x45760001, 0x44770001, 1713 0x43780001, 0x42790001, 0x417a0001, 0x407b0001, 0x407c0001, 1714 0x407d0001, 0x407e0001, 0x407f0001 1715}; 1716 1717static const struct urtwn_bb_prog rtl8188eu_bb_prog = { 1718 nitems(rtl8188eu_bb_regs), 1719 rtl8188eu_bb_regs, 1720 rtl8188eu_bb_vals, 1721 nitems(rtl8188eu_agc_vals), 1722 rtl8188eu_agc_vals 1723}; 1724 1725/* 1726 * RTL8188RU. 1727 / 1728static const uint16_t rtl8188ru_bb_regs[] = { 1729* 0x024, 0x028, 0x040, 0x800, 0x804, 0x808, 0x80c, 0x810, 0x814, 1730 0x818, 0x81c, 0x820, 0x824, 0x828, 0x82c, 0x830, 0x834, 0x838, 1731 0x83c, 0x840, 0x844, 0x848, 0x84c, 0x850, 0x854, 0x858, 0x85c, 1732 0x860, 0x864, 0x868, 0x86c, 0x870, 0x874, 0x878, 0x87c, 0x880, 1733 0x884, 0x888, 0x88c, 0x890, 0x894, 0x898, 0x89c, 0x900, 0x904, 1734 0x908, 0x90c, 0xa00, 0xa04, 0xa08, 0xa0c, 0xa10, 0xa14, 0xa18, 1735 0xa1c, 0xa20, 0xa24, 0xa28, 0xa2c, 0xa70, 0xa74, 0xc00, 0xc04, 1736 0xc08, 0xc0c, 0xc10, 0xc14, 0xc18, 0xc1c, 0xc20, 0xc24, 0xc28, 1737 0xc2c, 0xc30, 0xc34, 0xc38, 0xc3c, 0xc40, 0xc44, 0xc48, 0xc4c, 1738 0xc50, 0xc54, 0xc58, 0xc5c, 0xc60, 0xc64, 0xc68, 0xc6c, 0xc70, 1739 0xc74, 0xc78, 0xc7c, 0xc80, 0xc84, 0xc88, 0xc8c, 0xc90, 0xc94, 1740 0xc98, 0xc9c, 0xca0, 0xca4, 0xca8, 0xcac, 0xcb0, 0xcb4, 0xcb8, 1741 0xcbc, 0xcc0, 0xcc4, 0xcc8, 0xccc, 0xcd0, 0xcd4, 0xcd8, 0xcdc, 1742 0xce0, 0xce4, 0xce8, 0xcec, 0xd00, 0xd04, 0xd08, 0xd0c, 0xd10, 1743 0xd14, 0xd18, 0xd2c, 0xd30, 0xd34, 0xd38, 0xd3c, 0xd40, 0xd44, 1744 0xd48, 0xd4c, 0xd50, 0xd54, 0xd58, 0xd5c, 0xd60, 0xd64, 0xd68, 1745 0xd6c, 0xd70, 0xd74, 0xd78, 0xe00, 0xe04, 0xe08, 0xe10, 0xe14, 1746 0xe18, 0xe1c, 0xe28, 0xe30, 0xe34, 0xe38, 0xe3c, 0xe40, 0xe44, 1747 0xe48, 0xe4c, 0xe50, 0xe54, 0xe58, 0xe5c, 0xe60, 0xe68, 0xe6c, 1748 0xe70, 0xe74, 0xe78, 0xe7c, 0xe80, 0xe84, 0xe88, 0xe8c, 0xed0, 1749 0xed4, 0xed8, 0xedc, 0xee0, 0xeec, 0xee8, 0xf14, 0xf4c, 0xf00 1750}; 1751 1752static const uint32_t rtl8188ru_bb_vals[] = { 1753 0x0011800d, 0x00ffdb83, 0x000c0004, 0x80040000, 0x00000001, 1754 0x0000fc00, 0x0000000a, 0x10005388, 0x020c3d10, 0x02200385, 1755 0x00000000, 0x01000100, 0x00390204, 0x00000000, 0x00000000, 1756 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00010000, 1757 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 1758 0x569a569a, 0x001b25a4, 0x66e60230, 0x061f0130, 0x00000000, 1759 0x32323200, 0x03000300, 0x22004000, 0x00000808, 0x00ffc3f1, 1760 0xc0083070, 0x000004d5, 0x00000000, 0xccc000c0, 0x00000800, 1761 0xfffffffe, 0x40302010, 0x00706050, 0x00000000, 0x00000023, 1762 0x00000000, 0x81121111, 0x00d047c8, 0x80ff000c, 0x8c838300, 1763 0x2e68120f, 0x9500bb78, 0x11144028, 0x00881117, 0x89140f00, 1764 0x15160000, 0x070b0f12, 0x00000104, 0x00d30000, 0x101fbf00, 1765 0x00000007, 0x48071d40, 0x03a05611, 0x000000e4, 0x6c6c6c6c, 1766 0x08800000, 0x40000100, 0x08800000, 0x40000100, 0x00000000, 1767 0x00000000, 0x00000000, 0x00000000, 0x69e9ac44, 0x469652cf, 1768 0x49795994, 0x0a97971c, 0x1f7c403f, 0x000100b7, 0xec020107, 1769 0x007f037f, 0x6954342e, 0x43bc0094, 0x6954342f, 0x433c0094, 1770 0x00000000, 0x5116848b, 0x47c00bff, 0x00000036, 0x2c56000d, 1771 0x018610db, 0x0000001f, 0x00b91612, 0x24000090, 0x20f60000, 1772 0x24000090, 0x20200000, 0x00121820, 0x00000000, 0x00121820, 1773 0x00007f7f, 0x00000000, 0x00000080, 0x00000000, 0x00000000, 1774 0x00000000, 0x00000000, 0x00000000, 0x28000000, 0x00000000, 1775 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 1776 0x64b22427, 0x00766932, 0x00222222, 0x00000000, 0x37644302, 1777 0x2f97d40c, 0x00080740, 0x00020401, 0x0000907f, 0x20010201, 1778 0xa0633333, 0x3333bc43, 0x7a8f5b6b, 0xcc979975, 0x00000000, 1779 0x80608000, 0x00000000, 0x00027293, 0x00000000, 0x00000000, 1780 0x00000000, 0x00000000, 0x6437140a, 0x00000000, 0x00000000, 1781 0x30032064, 0x4653de68, 0x04518a3c, 0x00002101, 0x2a201c16, 1782 0x1812362e, 0x322c2220, 0x000e3c24, 0x2a2a2a2a, 0x2a2a2a2a, 1783 0x03902a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 1784 0x00000000, 0x1000dc1f, 0x10008c1f, 0x02140102, 0x681604c2, 1785 0x01007c00, 0x01004800, 0xfb000000, 0x000028d1, 0x1000dc1f, 1786 0x10008c1f, 0x02140102, 0x28160d05, 0x00000010, 0x001b25a4, 1787 0x631b25a0, 0x631b25a0, 0x081b25a0, 0x081b25a0, 0x081b25a0, 1788 0x081b25a0, 0x631b25a0, 0x081b25a0, 0x631b25a0, 0x631b25a0, 1789 0x631b25a0, 0x631b25a0, 0x001b25a0, 0x001b25a0, 0x6b1b25a0, 1790 0x31555448, 0x00000003, 0x00000000, 0x00000300 1791}; 1792 1793static const uint32_t rtl8188ru_agc_vals[] = { 1794 0x7b000001, 0x7b010001, 0x7b020001, 0x7b030001, 0x7b040001, 1795 0x7b050001, 0x7b060001, 0x7b070001, 0x7b080001, 0x7a090001, 1796 0x790a0001, 0x780b0001, 0x770c0001, 0x760d0001, 0x750e0001, 1797 0x740f0001, 0x73100001, 0x72110001, 0x71120001, 0x70130001, 1798 0x6f140001, 0x6e150001, 0x6d160001, 0x6c170001, 0x6b180001, 1799 0x6a190001, 0x691a0001, 0x681b0001, 0x671c0001, 0x661d0001, 1800 0x651e0001, 0x641f0001, 0x63200001, 0x62210001, 0x61220001, 1801 0x60230001, 0x46240001, 0x45250001, 0x44260001, 0x43270001, 1802 0x42280001, 0x41290001, 0x402a0001, 0x262b0001, 0x252c0001, 1803 0x242d0001, 0x232e0001, 0x222f0001, 0x21300001, 0x20310001, 1804 0x06320001, 0x05330001, 0x04340001, 0x03350001, 0x02360001, 1805 0x01370001, 0x00380001, 0x00390001, 0x003a0001, 0x003b0001, 1806 0x003c0001, 0x003d0001, 0x003e0001, 0x003f0001, 0x7b400001, 1807 0x7b410001, 0x7b420001, 0x7b430001, 0x7b440001, 0x7b450001, 1808 0x7b460001, 0x7b470001, 0x7b480001, 0x7a490001, 0x794a0001, 1809 0x784b0001, 0x774c0001, 0x764d0001, 0x754e0001, 0x744f0001, 1810 0x73500001, 0x72510001, 0x71520001, 0x70530001, 0x6f540001, 1811 0x6e550001, 0x6d560001, 0x6c570001, 0x6b580001, 0x6a590001, 1812 0x695a0001, 0x685b0001, 0x675c0001, 0x665d0001, 0x655e0001, 1813 0x645f0001, 0x63600001, 0x62610001, 0x61620001, 0x60630001, 1814 0x46640001, 0x45650001, 0x44660001, 0x43670001, 0x42680001, 1815 0x41690001, 0x406a0001, 0x266b0001, 0x256c0001, 0x246d0001, 1816 0x236e0001, 0x226f0001, 0x21700001, 0x20710001, 0x06720001, 1817 0x05730001, 0x04740001, 0x03750001, 0x02760001, 0x01770001, 1818 0x00780001, 0x00790001, 0x007a0001, 0x007b0001, 0x007c0001, 1819 0x007d0001, 0x007e0001, 0x007f0001, 0x3800001e, 0x3801001e, 1820 0x3802001e, 0x3803001e, 0x3804001e, 0x3805001e, 0x3806001e, 1821 0x3807001e, 0x3808001e, 0x3c09001e, 0x3e0a001e, 0x400b001e, 1822 0x440c001e, 0x480d001e, 0x4c0e001e, 0x500f001e, 0x5210001e, 1823 0x5611001e, 0x5a12001e, 0x5e13001e, 0x6014001e, 0x6015001e, 1824 0x6016001e, 0x6217001e, 0x6218001e, 0x6219001e, 0x621a001e, 1825 0x621b001e, 0x621c001e, 0x621d001e, 0x621e001e, 0x621f001e 1826}; 1827 1828static const struct urtwn_bb_prog rtl8188ru_bb_prog = { 1829 nitems(rtl8188ru_bb_regs), 1830 rtl8188ru_bb_regs, 1831 rtl8188ru_bb_vals, 1832 nitems(rtl8188ru_agc_vals), 1833 rtl8188ru_agc_vals 1834}; 1835 1836/* 1837 * RF initialization values. 1838 / 1839struct urtwn_rf_prog { 1840* int count; 1841 const uint8_t regs; 1842* const uint32_t vals; 1843}; 1844* 1845/* 1846 * RTL8192CU and RTL8192CE-VAU. 1847 / 1848static const uint8_t rtl8192ce_rf1_regs[] = { 1849* 0x00, 0x01, 0x02, 0x03, 0x04, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 1850 0x0f, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f, 0x20, 0x21, 0x22, 1851 0x23, 0x24, 0x25, 0x26, 0x27, 0x28, 0x29, 0x2a, 0x2b, 0x2a, 0x2b, 1852 0x2a, 0x2b, 0x2b, 0x2c, 0x2a, 0x2b, 0x2b, 0x2c, 0x2a, 0x2b, 0x2b, 1853 0x2c, 0x2a, 0x2b, 0x2b, 0x2c, 0x2a, 0x2b, 0x2b, 0x2c, 0x2a, 0x2b, 1854 0x2b, 0x2c, 0x2a, 0x2b, 0x2b, 0x2c, 0x2a, 0x2b, 0x2b, 0x2c, 0x2a, 1855 0x2b, 0x2b, 0x2c, 0x2a, 0x2b, 0x2b, 0x2c, 0x2a, 0x2b, 0x2b, 0x2c, 1856 0x2a, 0x2b, 0x2b, 0x2c, 0x2a, 0x2b, 0x2b, 0x2c, 0x2a, 0x2b, 0x2b, 1857 0x2c, 0x2a, 0x10, 0x11, 0x10, 0x11, 0x10, 0x11, 0x10, 0x11, 0x10, 1858 0x11, 0x10, 0x11, 0x10, 0x11, 0x12, 0x12, 0x12, 0x12, 0x13, 0x13, 1859 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x14, 0x14, 1860 0x14, 0x14, 0x15, 0x15, 0x15, 0x15, 0x16, 0x16, 0x16, 0x16, 0x00, 1861 0x18, 0xfe, 0xfe, 0x1f, 0xfe, 0xfe, 0x1e, 0x1f, 0x00 1862}; 1863 1864static const uint32_t rtl8192ce_rf1_vals[] = { 1865 0x30159, 0x31284, 0x98000, 0x18c63, 0x210e7, 0x2044f, 0x1adb1, 1866 0x54867, 0x8992e, 0x0e52c, 0x39ce7, 0x00451, 0x00000, 0x10255, 1867 0x60a00, 0xfc378, 0xa1250, 0x4445f, 0x80001, 0x0b614, 0x6c000, 1868 0x00000, 0x01558, 0x00060, 0x00483, 0x4f000, 0xec7d9, 0x577c0, 1869 0x04783, 0x00001, 0x21334, 0x00000, 0x00054, 0x00001, 0x00808, 1870 0x53333, 0x0000c, 0x00002, 0x00808, 0x5b333, 0x0000d, 0x00003, 1871 0x00808, 0x63333, 0x0000d, 0x00004, 0x00808, 0x6b333, 0x0000d, 1872 0x00005, 0x00808, 0x73333, 0x0000d, 0x00006, 0x00709, 0x5b333, 1873 0x0000d, 0x00007, 0x00709, 0x63333, 0x0000d, 0x00008, 0x0060a, 1874 0x4b333, 0x0000d, 0x00009, 0x0060a, 0x53333, 0x0000d, 0x0000a, 1875 0x0060a, 0x5b333, 0x0000d, 0x0000b, 0x0060a, 0x63333, 0x0000d, 1876 0x0000c, 0x0060a, 0x6b333, 0x0000d, 0x0000d, 0x0060a, 0x73333, 1877 0x0000d, 0x0000e, 0x0050b, 0x66666, 0x0001a, 0xe0000, 0x4000f, 1878 0xe31fc, 0x6000f, 0xff9f8, 0x2000f, 0x203f9, 0x3000f, 0xff500, 1879 0x00000, 0x00000, 0x8000f, 0x3f100, 0x9000f, 0x23100, 0x32000, 1880 0x71000, 0xb0000, 0xfc000, 0x287af, 0x244b7, 0x204ab, 0x1c49f, 1881 0x18493, 0x14297, 0x10295, 0x0c298, 0x0819c, 0x040a8, 0x0001c, 1882 0x1944c, 0x59444, 0x9944c, 0xd9444, 0x0f424, 0x4f424, 0x8f424, 1883 0xcf424, 0xe0330, 0xa0330, 0x60330, 0x20330, 0x10159, 0x0f401, 1884 0x00000, 0x00000, 0x80003, 0x00000, 0x00000, 0x44457, 0x80000, 1885 0x30159 1886}; 1887 1888static const uint8_t rtl8192ce_rf2_regs[] = { 1889 0x00, 0x01, 0x02, 0x03, 0x04, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 1890 0x0f, 0x12, 0x12, 0x12, 0x12, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 1891 0x13, 0x13, 0x13, 0x13, 0x13, 0x14, 0x14, 0x14, 0x14, 0x15, 0x15, 1892 0x15, 0x15, 0x16, 0x16, 0x16, 0x16 1893}; 1894 1895static const uint32_t rtl8192ce_rf2_vals[] = { 1896 0x30159, 0x31284, 0x98000, 0x18c63, 0x210e7, 0x2044f, 0x1adb1, 1897 0x54867, 0x8992e, 0x0e52c, 0x39ce7, 0x00451, 0x32000, 0x71000, 1898 0xb0000, 0xfc000, 0x287af, 0x244b7, 0x204ab, 0x1c49f, 0x18493, 1899 0x14297, 0x10295, 0x0c298, 0x0819c, 0x040a8, 0x0001c, 0x1944c, 1900 0x59444, 0x9944c, 0xd9444, 0x0f424, 0x4f424, 0x8f424, 0xcf424, 1901 0xe0330, 0xa0330, 0x60330, 0x20330 1902}; 1903 1904static const struct urtwn_rf_prog rtl8192ce_rf_prog[] = { 1905 { 1906 nitems(rtl8192ce_rf1_regs), 1907 rtl8192ce_rf1_regs, 1908 rtl8192ce_rf1_vals 1909 }, 1910 { 1911 nitems(rtl8192ce_rf2_regs), 1912 rtl8192ce_rf2_regs, 1913 rtl8192ce_rf2_vals 1914 } 1915}; 1916 1917/* 1918 * RTL8188CE-VAU. 1919 / 1920static const uint32_t rtl8188ce_rf_vals[] = { 1921* 0x30159, 0x31284, 0x98000, 0x18c63, 0x210e7, 0x2044f, 0x1adb1, 1922 0x54867, 0x8992e, 0x0e52c, 0x39ce7, 0x00451, 0x00000, 0x10255, 1923 0x60a00, 0xfc378, 0xa1250, 0x4445f, 0x80001, 0x0b614, 0x6c000, 1924 0x00000, 0x01558, 0x00060, 0x00483, 0x4f200, 0xec7d9, 0x577c0, 1925 0x04783, 0x00001, 0x21334, 0x00000, 0x00054, 0x00001, 0x00808, 1926 0x53333, 0x0000c, 0x00002, 0x00808, 0x5b333, 0x0000d, 0x00003, 1927 0x00808, 0x63333, 0x0000d, 0x00004, 0x00808, 0x6b333, 0x0000d, 1928 0x00005, 0x00808, 0x73333, 0x0000d, 0x00006, 0x00709, 0x5b333, 1929 0x0000d, 0x00007, 0x00709, 0x63333, 0x0000d, 0x00008, 0x0060a, 1930 0x4b333, 0x0000d, 0x00009, 0x0060a, 0x53333, 0x0000d, 0x0000a, 1931 0x0060a, 0x5b333, 0x0000d, 0x0000b, 0x0060a, 0x63333, 0x0000d, 1932 0x0000c, 0x0060a, 0x6b333, 0x0000d, 0x0000d, 0x0060a, 0x73333, 1933 0x0000d, 0x0000e, 0x0050b, 0x66666, 0x0001a, 0xe0000, 0x4000f, 1934 0xe31fc, 0x6000f, 0xff9f8, 0x2000f, 0x203f9, 0x3000f, 0xff500, 1935 0x00000, 0x00000, 0x8000f, 0x3f100, 0x9000f, 0x23100, 0x32000, 1936 0x71000, 0xb0000, 0xfc000, 0x287b3, 0x244b7, 0x204ab, 0x1c49f, 1937 0x18493, 0x1429b, 0x10299, 0x0c29c, 0x081a0, 0x040ac, 0x00020, 1938 0x1944c, 0x59444, 0x9944c, 0xd9444, 0x0f424, 0x4f424, 0x8f424, 1939 0xcf424, 0xe0330, 0xa0330, 0x60330, 0x20330, 0x10159, 0x0f401, 1940 0x00000, 0x00000, 0x80003, 0x00000, 0x00000, 0x44457, 0x80000, 1941 0x30159 1942}; 1943 1944static const struct urtwn_rf_prog rtl8188ce_rf_prog[] = { 1945 { 1946 nitems(rtl8192ce_rf1_regs), 1947 rtl8192ce_rf1_regs, 1948 rtl8188ce_rf_vals 1949 } 1950}; 1951 1952 1953/* 1954 * RTL8188CU. 1955 / 1956static const uint32_t rtl8188cu_rf_vals[] = { 1957* 0x30159, 0x31284, 0x98000, 0x18c63, 0x210e7, 0x2044f, 0x1adb1, 1958 0x54867, 0x8992e, 0x0e52c, 0x39ce7, 0x00451, 0x00000, 0x10255, 1959 0x60a00, 0xfc378, 0xa1250, 0x4445f, 0x80001, 0x0b614, 0x6c000, 1960 0x00000, 0x01558, 0x00060, 0x00483, 0x4f000, 0xec7d9, 0x577c0, 1961 0x04783, 0x00001, 0x21334, 0x00000, 0x00054, 0x00001, 0x00808, 1962 0x53333, 0x0000c, 0x00002, 0x00808, 0x5b333, 0x0000d, 0x00003, 1963 0x00808, 0x63333, 0x0000d, 0x00004, 0x00808, 0x6b333, 0x0000d, 1964 0x00005, 0x00808, 0x73333, 0x0000d, 0x00006, 0x00709, 0x5b333, 1965 0x0000d, 0x00007, 0x00709, 0x63333, 0x0000d, 0x00008, 0x0060a, 1966 0x4b333, 0x0000d, 0x00009, 0x0060a, 0x53333, 0x0000d, 0x0000a, 1967 0x0060a, 0x5b333, 0x0000d, 0x0000b, 0x0060a, 0x63333, 0x0000d, 1968 0x0000c, 0x0060a, 0x6b333, 0x0000d, 0x0000d, 0x0060a, 0x73333, 1969 0x0000d, 0x0000e, 0x0050b, 0x66666, 0x0001a, 0xe0000, 0x4000f, 1970 0xe31fc, 0x6000f, 0xff9f8, 0x2000f, 0x203f9, 0x3000f, 0xff500, 1971 0x00000, 0x00000, 0x8000f, 0x3f100, 0x9000f, 0x23100, 0x32000, 1972 0x71000, 0xb0000, 0xfc000, 0x287b3, 0x244b7, 0x204ab, 0x1c49f, 1973 0x18493, 0x1429b, 0x10299, 0x0c29c, 0x081a0, 0x040ac, 0x00020, 1974 0x1944c, 0x59444, 0x9944c, 0xd9444, 0x0f405, 0x4f405, 0x8f405, 1975 0xcf405, 0xe0330, 0xa0330, 0x60330, 0x20330, 0x10159, 0x0f401, 1976 0x00000, 0x00000, 0x80003, 0x00000, 0x00000, 0x44457, 0x80000, 1977 0x30159 1978}; 1979 1980static const struct urtwn_rf_prog rtl8188cu_rf_prog[] = { 1981 { 1982 nitems(rtl8192ce_rf1_regs), 1983 rtl8192ce_rf1_regs, 1984 rtl8188cu_rf_vals 1985 } 1986}; 1987 1988/* 1989 * RTL8188EU. 1990 / 1991static const uint8_t rtl8188eu_rf_regs[] = { 1992* 0x00, 0x08, 0x18, 0x19, 0x1e, 0x1f, 0x2f, 0x3f, 0x42, 0x57, 1993 0x58, 0x67, 0x83, 0xb0, 0xb1, 0xb2, 0xb4, 0xb6, 0xb7, 0xb8, 1994 0xb9, 0xba, 0xbb, 0xbf, 0xc2, 0xc3, 0xc4, 0xc5, 0xc6, 0xc7, 1995 0xc8, 0xc9, 0xca, 0xdf, 0xef, 0x51, 0x52, 0x53, 0x56, 1996 0x35, 0x35, 0x35, 0x36, 0x36, 0x36, 0x36, 0xb6, 0x18, 0x5a, 1997 0x19, 0x34, 0x34, 0x34, 0x34, 0x34, 0x34, 0x34, 0x34, 0x34, 1998 0x34, 0x34, 0x00, 0x84, 0x86, 0x87, 0x8e, 0x8f, 0xef, 0x3b, 1999 0x3b, 0x3b, 0x3b, 0x3b, 0x3b, 0x3b, 0x3b, 0x3b, 0x3b, 0x3b, 2000 0x3b, 0x3b, 0x3b, 0x3b, 0x3b, 0xef, 0x00, 0x18, 0xfe, 0xfe, 2001 0x1f, 0xfe, 0xfe, 0x1e, 0x1f, 0x00 2002}; 2003 2004static const uint32_t rtl8188eu_rf_vals[] = { 2005 0x30000, 0x84000, 0x00407, 0x00012, 0x80009, 0x00880, 0x1a060, 2006 0x00000, 0x060c0, 0xd0000, 0xbe180, 0x01552, 0x00000, 0xff8fc, 2007 0x54400, 0xccc19, 0x43003, 0x4953e, 0x1c718, 0x060ff, 0x80001, 2008 0x40000, 0x00400, 0xc0000, 0x02400, 0x00009, 0x40c91, 0x99999, 2009 0x000a3, 0x88820, 0x76c06, 0x00000, 0x80000, 0x00180, 0x001a0, 2010 0x6b27d, 0x7e49d, 0x00073, 0x51ff3, 0x00086, 0x00186, 2011 0x00286, 0x01c25, 0x09c25, 0x11c25, 0x19c25, 0x48538, 0x00c07, 2012 0x4bd00, 0x739d0, 0x0adf3, 0x09df0, 0x08ded, 0x07dea, 0x06de7, 2013 0x054ee, 0x044eb, 0x034e8, 0x0246b, 0x01468, 0x0006d, 0x30159, 2014 0x68200, 0x000ce, 0x48a00, 0x65540, 0x88000, 0x020a0, 0xf02b0, 2015 0xef7b0, 0xd4fb0, 0xcf060, 0xb0090, 0xa0080, 0x90080, 0x8f780, 2016 0x722b0, 0x6f7b0, 0x54fb0, 0x4f060, 0x30090, 0x20080, 0x10080, 2017 0x0f780, 0x000a0, 0x10159, 0x0f407, 0x00000, 0x00000, 0x80003, 2018 0x00000, 0x00000, 0x00001, 0x80000, 0x33e60 2019}; 2020 2021static const struct urtwn_rf_prog rtl8188eu_rf_prog[] = { 2022 { 2023 nitems(rtl8188eu_rf_regs), 2024 rtl8188eu_rf_regs, 2025 rtl8188eu_rf_vals 2026 } 2027}; 2028 2029/* 2030 * RTL8188RU. 2031 / 2032static const uint32_t rtl8188ru_rf_vals[] = { 2033* 0x30159, 0x31284, 0x98000, 0x18c63, 0x210e7, 0x2044f, 0x1adb0, 2034 0x54867, 0x8992e, 0x0e529, 0x39ce7, 0x00451, 0x00000, 0x00255, 2035 0x60a00, 0xfc378, 0xa1250, 0x4445f, 0x80001, 0x0b614, 0x6c000, 2036 0x0083c, 0x01558, 0x00060, 0x00483, 0x4f000, 0xec7d9, 0x977c0, 2037 0x04783, 0x00001, 0x21334, 0x00000, 0x00054, 0x00001, 0x00808, 2038 0x53333, 0x0000c, 0x00002, 0x00808, 0x5b333, 0x0000d, 0x00003, 2039 0x00808, 0x63333, 0x0000d, 0x00004, 0x00808, 0x6b333, 0x0000d, 2040 0x00005, 0x00808, 0x73333, 0x0000d, 0x00006, 0x00709, 0x5b333, 2041 0x0000d, 0x00007, 0x00709, 0x63333, 0x0000d, 0x00008, 0x0060a, 2042 0x4b333, 0x0000d, 0x00009, 0x0060a, 0x53333, 0x0000d, 0x0000a, 2043 0x0060a, 0x5b333, 0x0000d, 0x0000b, 0x0060a, 0x63333, 0x0000d, 2044 0x0000c, 0x0060a, 0x6b333, 0x0000d, 0x0000d, 0x0060a, 0x73333, 2045 0x0000d, 0x0000e, 0x0050b, 0x66666, 0x0001a, 0xe0000, 0x4000f, 2046 0xe31fc, 0x6000f, 0xff9f8, 0x2000f, 0x203f9, 0x3000f, 0xff500, 2047 0x00000, 0x00000, 0x8000f, 0x3f100, 0x9000f, 0x23100, 0xd8000, 2048 0x90000, 0x51000, 0x12000, 0x28fb4, 0x24fa8, 0x207a4, 0x1c798, 2049 0x183a4, 0x14398, 0x101a4, 0x0c198, 0x080a4, 0x04098, 0x00014, 2050 0x1944c, 0x59444, 0x9944c, 0xd9444, 0x0f405, 0x4f405, 0x8f405, 2051 0xcf405, 0xe0330, 0xa0330, 0x60330, 0x20330, 0x10159, 0x0f401, 2052 0x00000, 0x00000, 0x80003, 0x00000, 0x00000, 0x44457, 0x80000, 2053 0x30159 2054}; 2055 2056static const struct urtwn_rf_prog rtl8188ru_rf_prog[] = { 2057 { 2058 nitems(rtl8192ce_rf1_regs), 2059 rtl8192ce_rf1_regs, 2060 rtl8188ru_rf_vals 2061 } 2062}; 2063 2064struct urtwn_txpwr { 2065 uint8_t pwr[3][28]; 2066}; 2067 2068struct urtwn_r88e_txpwr { 2069 uint8_t pwr[6][28]; 2070}; 2071 2072/* 2073 * Per RF chain/group/rate Tx gain values. 2074 / 2075static const struct urtwn_txpwr rtl8192cu_txagc[] = { 2076* { { /* Chain 0. / 2077* { /* Group 0. / 2078* 0x00, 0x00, 0x00, 0x00, /* CCK1~11. / 2079* 0x0c, 0x0c, 0x0c, 0x0a, 0x08, 0x06, 0x04, 0x02, /* OFDM6~54. / 2080* 0x0e, 0x0d, 0x0c, 0x0a, 0x08, 0x06, 0x04, 0x02, /* MCS0~7. / 2081* 0x0e, 0x0d, 0x0c, 0x0a, 0x08, 0x06, 0x04, 0x02 /* MCS8~15. / 2082* }, 2083 { /* Group 1. / 2084* 0x00, 0x00, 0x00, 0x00, /* CCK1~11. / 2085* 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* OFDM6~54. / 2086* 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* MCS0~7. / 2087* 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* MCS8~15. / 2088* }, 2089 { /* Group 2. / 2090* 0x00, 0x00, 0x00, 0x00, /* CCK1~11. / 2091* 0x04, 0x04, 0x04, 0x04, 0x04, 0x02, 0x02, 0x00, /* OFDM6~54. / 2092* 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* MCS0~7. / 2093* 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* MCS8~15. / 2094* } 2095 } }, 2096 { { /* Chain 1. / 2097* { /* Group 0. / 2098* 0x00, 0x00, 0x00, 0x00, /* CCK1~11. / 2099* 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* OFDM6~54. / 2100* 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* MCS0~7. / 2101* 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* MCS8~15. / 2102* }, 2103 { /* Group 1. / 2104* 0x00, 0x00, 0x00, 0x00, /* CCK1~11. / 2105* 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* OFDM6~54. / 2106* 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* MCS0~7. / 2107* 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* MCS8~15. / 2108* }, 2109 { /* Group 2. / 2110* 0x00, 0x00, 0x00, 0x00, /* CCK1~11. / 2111* 0x04, 0x04, 0x04, 0x04, 0x04, 0x02, 0x02, 0x00, /* OFDM6~54. / 2112* 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* MCS0~7. / 2113* 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* MCS8~15. / 2114* } 2115 } } 2116}; 2117 2118static const struct urtwn_txpwr rtl8188ru_txagc[] = { 2119 { { /* Chain 0. / 2120* { /* Group 0. / 2121* 0x00, 0x00, 0x00, 0x00, /* CCK1~11. / 2122* 0x08, 0x08, 0x08, 0x06, 0x06, 0x04, 0x04, 0x00, /* OFDM6~54. / 2123* 0x08, 0x06, 0x06, 0x04, 0x04, 0x02, 0x02, 0x00, /* MCS0~7. / 2124* 0x08, 0x06, 0x06, 0x04, 0x04, 0x02, 0x02, 0x00 /* MCS8~15. / 2125* }, 2126 { /* Group 1. / 2127* 0x00, 0x00, 0x00, 0x00, /* CCK1~11. / 2128* 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* OFDM6~54. / 2129* 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* MCS0~7. / 2130* 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* MCS8~15. / 2131* }, 2132 { /* Group 2. / 2133* 0x00, 0x00, 0x00, 0x00, /* CCK1~11. / 2134* 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* OFDM6~54. / 2135* 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* MCS0~7. / 2136* 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* MCS8~15. / 2137* } 2138 } } 2139}; 2140 2141static const struct urtwn_r88e_txpwr rtl8188eu_txagc[] = { 2142 { { /* Chain 0. / 2143* { /* Group 0. / 2144* 0x00, 0x00, 0x00, 0x00, /* CCK1~11. / 2145* 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* OFDM6~54. / 2146* 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* MCS0~7. / 2147* 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* MCS8~15. / 2148* }, 2149 { /* Group 1. / 2150* 0x00, 0x00, 0x00, 0x00, /* CCK1~11. / 2151* 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* OFDM6~54. / 2152* 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* MCS0~7. / 2153* 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* MCS8~15. / 2154* }, 2155 { /* Group 2. / 2156* 0x00, 0x00, 0x00, 0x00, /* CCK1~11. / 2157* 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* OFDM6~54. / 2158* 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* MCS0~7. / 2159* 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* MCS8~15. / 2160* }, 2161 { /* Group 3. / 2162* 0x00, 0x00, 0x00, 0x00, /* CCK1~11. / 2163* 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* OFDM6~54. / 2164* 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* MCS0~7. / 2165* 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* MCS8~15. / 2166* }, 2167 { /* Group 4. / 2168* 0x00, 0x00, 0x00, 0x00, /* CCK1~11. / 2169* 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* OFDM6~54. / 2170* 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* MCS0~7. / 2171* 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* MCS8~15. / 2172* }, 2173 { /* Group 5. / 2174* 0x00, 0x00, 0x00, 0x00, /* CCK1~11. / 2175* 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* OFDM6~54. / 2176* 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* MCS0~7. / 2177* 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* MCS8~15. / 2178* } 2179 } } 2180};	1023 uint8_t version; 1024 uint8_t customer_id; 1025} __packed; 1026 1027/* 1028 * RTL8188EU ROM image. 1029 / 1030struct r88e_rom { 1031* uint8_t reserved1[16]; 1032 uint8_t cck_tx_pwr[6]; 1033 uint8_t ht40_tx_pwr[5]; 1034 uint8_t tx_pwr_diff; 1035 uint8_t reserved2[156]; 1036 uint8_t channel_plan; 1037 uint8_t crystalcap; 1038 uint8_t reserved3[7]; 1039 uint8_t rf_board_opt; 1040 uint8_t rf_feature_opt; 1041 uint8_t rf_bt_opt; 1042 uint8_t version; 1043 uint8_t customer_id; 1044 uint8_t reserved4[3]; 1045 uint8_t rf_ant_opt; 1046 uint8_t reserved5[6]; 1047 uint16_t vid; 1048 uint16_t pid; 1049 uint8_t usb_opt; 1050 uint8_t reserved6[2]; 1051 uint8_t macaddr[IEEE80211_ADDR_LEN]; 1052 uint8_t reserved7[2]; 1053 uint8_t string[33]; /* "realtek 802.11n NIC" / 1054* uint8_t reserved8[256]; 1055} __packed; 1056 1057#define URTWN_EFUSE_MAX_LEN 512 1058 1059/* Rx MAC descriptor. / 1060struct r92c_rx_stat { 1061* uint32_t rxdw0; 1062#define R92C_RXDW0_PKTLEN_M 0x00003fff 1063#define R92C_RXDW0_PKTLEN_S 0 1064#define R92C_RXDW0_CRCERR 0x00004000 1065#define R92C_RXDW0_ICVERR 0x00008000 1066#define R92C_RXDW0_INFOSZ_M 0x000f0000 1067#define R92C_RXDW0_INFOSZ_S 16 1068#define R92C_RXDW0_CIPHER_M 0x00700000 1069#define R92C_RXDW0_CIPHER_S 20 1070#define R92C_RXDW0_QOS 0x00800000 1071#define R92C_RXDW0_SHIFT_M 0x03000000 1072#define R92C_RXDW0_SHIFT_S 24 1073#define R92C_RXDW0_PHYST 0x04000000 1074#define R92C_RXDW0_DECRYPTED 0x08000000 1075 1076 uint32_t rxdw1; 1077 uint32_t rxdw2; 1078#define R92C_RXDW2_PKTCNT_M 0x00ff0000 1079#define R92C_RXDW2_PKTCNT_S 16 1080 1081 uint32_t rxdw3; 1082#define R92C_RXDW3_RATE_M 0x0000003f 1083#define R92C_RXDW3_RATE_S 0 1084#define R92C_RXDW3_HT 0x00000040 1085#define R92C_RXDW3_HTC 0x00000400 1086#define R88E_RXDW3_RPT_M 0x0000c000 1087#define R88E_RXDW3_RPT_S 14 1088#define R88E_RXDW3_RPT_RX 0 1089#define R88E_RXDW3_RPT_TX1 1 1090#define R88E_RXDW3_RPT_TX2 2 1091 1092 uint32_t rxdw4; 1093 uint32_t rxdw5; 1094} __packed __attribute__((aligned(4))); 1095 1096/* Rx PHY descriptor. / 1097struct r92c_rx_phystat { 1098* uint32_t phydw0; 1099 uint32_t phydw1; 1100 uint32_t phydw2; 1101 uint32_t phydw3; 1102 uint32_t phydw4; 1103 uint32_t phydw5; 1104 uint32_t phydw6; 1105 uint32_t phydw7; 1106} __packed __attribute__((aligned(4))); 1107 1108/* Rx PHY CCK descriptor. / 1109struct r92c_rx_cck { 1110* uint8_t adc_pwdb[4]; 1111 uint8_t sq_rpt; 1112 uint8_t agc_rpt; 1113} __packed; 1114 1115struct r88e_rx_cck { 1116 uint8_t path_agc[2]; 1117 uint8_t chan; 1118 uint8_t reserved1; 1119 uint8_t sig_qual; 1120 uint8_t agc_rpt; 1121 uint8_t rpt_b; 1122 uint8_t reserved2; 1123 uint8_t noise_power; 1124 uint8_t path_cfotail[2]; 1125 uint8_t pcts_mask[2]; 1126 uint8_t stream_rxevm[2]; 1127 uint8_t path_rxsnr[2]; 1128 uint8_t noise_power_db_lsb; 1129 uint8_t reserved3[3]; 1130 uint8_t stream_csi[2]; 1131 uint8_t stream_target_csi[2]; 1132 uint8_t sig_evm; 1133} __packed; 1134 1135/* Tx MAC descriptor. / 1136struct r92c_tx_desc { 1137* uint32_t txdw0; 1138#define R92C_TXDW0_PKTLEN_M 0x0000ffff 1139#define R92C_TXDW0_PKTLEN_S 0 1140#define R92C_TXDW0_OFFSET_M 0x00ff0000 1141#define R92C_TXDW0_OFFSET_S 16 1142#define R92C_TXDW0_BMCAST 0x01000000 1143#define R92C_TXDW0_LSG 0x04000000 1144#define R92C_TXDW0_FSG 0x08000000 1145#define R92C_TXDW0_OWN 0x80000000 1146 1147 uint32_t txdw1; 1148#define R92C_TXDW1_MACID_M 0x0000001f 1149#define R92C_TXDW1_MACID_S 0 1150#define R88E_TXDW1_MACID_M 0x0000003f 1151#define R88E_TXDW1_MACID_S 0 1152#define R92C_TXDW1_AGGEN 0x00000020 1153#define R92C_TXDW1_AGGBK 0x00000040 1154#define R92C_TXDW1_QSEL_M 0x00001f00 1155#define R92C_TXDW1_QSEL_S 8 1156 1157#define R92C_TXDW1_QSEL_BE 0x00 /* or 0x03 / 1158#define R92C_TXDW1_QSEL_BK 0x01 / or 0x02 / 1159#define R92C_TXDW1_QSEL_VI 0x04 / or 0x05 / 1160#define R92C_TXDW1_QSEL_VO 0x06 / or 0x07 / 1161#define URTWN_MAX_TID 8 1162* 1163#define R92C_TXDW1_QSEL_BEACON 0x10 1164#define R92C_TXDW1_QSEL_MGNT 0x12 1165 1166#define R92C_TXDW1_RAID_M 0x000f0000 1167#define R92C_TXDW1_RAID_S 16 1168#define R92C_TXDW1_CIPHER_M 0x00c00000 1169#define R92C_TXDW1_CIPHER_S 22 1170#define R92C_TXDW1_CIPHER_NONE 0 1171#define R92C_TXDW1_CIPHER_RC4 1 1172#define R92C_TXDW1_CIPHER_AES 3 1173#define R92C_TXDW1_PKTOFF_M 0x7c000000 1174#define R92C_TXDW1_PKTOFF_S 26 1175 1176 uint32_t txdw2; 1177#define R88E_TXDW2_AGGBK 0x00010000 1178#define R88E_TXDW2_CCX_RPT 0x00080000 1179 1180 uint16_t txdw3; 1181 uint16_t txdseq; 1182#define R88E_TXDSEQ_HWSEQ_EN 0x8000 1183 1184 uint32_t txdw4; 1185#define R92C_TXDW4_RTSRATE_M 0x0000003f 1186#define R92C_TXDW4_RTSRATE_S 0 1187#define R92C_TXDW4_HWSEQ_QOS 0x00000040 1188#define R92C_TXDW4_HWSEQ_EN 0x00000080 1189#define R92C_TXDW4_DRVRATE 0x00000100 1190#define R92C_TXDW4_CTS2SELF 0x00000800 1191#define R92C_TXDW4_RTSEN 0x00001000 1192#define R92C_TXDW4_HWRTSEN 0x00002000 1193#define R92C_TXDW4_SCO_M 0x003f0000 1194#define R92C_TXDW4_SCO_S 20 1195#define R92C_TXDW4_SCO_SCA 1 1196#define R92C_TXDW4_SCO_SCB 2 1197#define R92C_TXDW4_40MHZ 0x02000000 1198 1199 uint32_t txdw5; 1200#define R92C_TXDW5_DATARATE_M 0x0000003f 1201#define R92C_TXDW5_DATARATE_S 0 1202#define R92C_TXDW5_SGI 0x00000040 1203#define R92C_TXDW5_RTY_LMT_ENA 0x00020000 1204#define R92C_TXDW5_RTY_LMT_M 0x00fc0000 1205#define R92C_TXDW5_RTY_LMT_S 18 1206#define R92C_TXDW5_AGGNUM_M 0xff000000 1207#define R92C_TXDW5_AGGNUM_S 24 1208 1209 uint32_t txdw6; 1210 uint16_t txdsum; 1211 uint16_t pad; 1212} __packed __attribute__((aligned(4))); 1213 1214struct r88e_tx_rpt_ccx { 1215 uint8_t rptb0; 1216 uint8_t rptb1; 1217#define R88E_RPTB1_MACID_M 0x3f 1218#define R88E_RPTB1_MACID_S 0 1219#define R88E_RPTB1_PKT_OK 0x40 1220#define R88E_RPTB1_BMC 0x80 1221 1222 uint8_t rptb2; 1223#define R88E_RPTB2_RETRY_CNT_M 0x3f 1224#define R88E_RPTB2_RETRY_CNT_S 0 1225#define R88E_RPTB2_LIFE_EXPIRE 0x40 1226#define R88E_RPTB2_RETRY_OVER 0x80 1227 1228 uint8_t rptb3; 1229 uint8_t rptb4; 1230 uint8_t rptb5; 1231 uint8_t rptb6; 1232#define R88E_RPTB6_QSEL_M 0xf0 1233#define R88E_RPTB6_QSEL_S 4 1234 1235 uint8_t rptb7; 1236} __packed; 1237 1238 1239static const uint8_t ridx2rate[] = 1240 { 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108 }; 1241 1242/* HW rate indices. / 1243#define URTWN_RIDX_CCK1 0 1244#define URTWN_RIDX_CCK11 3 1245#define URTWN_RIDX_OFDM6 4 1246#define URTWN_RIDX_OFDM24 8 1247#define URTWN_RIDX_OFDM54 11 1248* 1249#define URTWN_RIDX_COUNT 28 1250#define URTWN_RIDX_UNKNOWN (uint8_t)-1 1251 1252 1253/* 1254 * MAC initialization values. 1255 / 1256static const struct { 1257* uint16_t reg; 1258 uint8_t val; 1259} rtl8188eu_mac[] = { 1260 { 0x026, 0x41 }, { 0x027, 0x35 }, { 0x040, 0x00 }, { 0x428, 0x0a }, 1261 { 0x429, 0x10 }, { 0x430, 0x00 }, { 0x431, 0x01 }, { 0x432, 0x02 }, 1262 { 0x433, 0x04 }, { 0x434, 0x05 }, { 0x435, 0x06 }, { 0x436, 0x07 }, 1263 { 0x437, 0x08 }, { 0x438, 0x00 }, { 0x439, 0x00 }, { 0x43a, 0x01 }, 1264 { 0x43b, 0x02 }, { 0x43c, 0x04 }, { 0x43d, 0x05 }, { 0x43e, 0x06 }, 1265 { 0x43f, 0x07 }, { 0x440, 0x5d }, { 0x441, 0x01 }, { 0x442, 0x00 }, 1266 { 0x444, 0x15 }, { 0x445, 0xf0 }, { 0x446, 0x0f }, { 0x447, 0x00 }, 1267 { 0x458, 0x41 }, { 0x459, 0xa8 }, { 0x45a, 0x72 }, { 0x45b, 0xb9 }, 1268 { 0x460, 0x66 }, { 0x461, 0x66 }, { 0x480, 0x08 }, { 0x4c8, 0xff }, 1269 { 0x4c9, 0x08 }, { 0x4cc, 0xff }, { 0x4cd, 0xff }, { 0x4ce, 0x01 }, 1270 { 0x4d3, 0x01 }, { 0x500, 0x26 }, { 0x501, 0xa2 }, { 0x502, 0x2f }, 1271 { 0x503, 0x00 }, { 0x504, 0x28 }, { 0x505, 0xa3 }, { 0x506, 0x5e }, 1272 { 0x507, 0x00 }, { 0x508, 0x2b }, { 0x509, 0xa4 }, { 0x50a, 0x5e }, 1273 { 0x50b, 0x00 }, { 0x50c, 0x4f }, { 0x50d, 0xa4 }, { 0x50e, 0x00 }, 1274 { 0x50f, 0x00 }, { 0x512, 0x1c }, { 0x514, 0x0a }, { 0x516, 0x0a }, 1275 { 0x525, 0x4f }, { 0x550, 0x10 }, { 0x551, 0x10 }, { 0x559, 0x02 }, 1276 { 0x55d, 0xff }, { 0x605, 0x30 }, { 0x608, 0x0e }, { 0x609, 0x2a }, 1277 { 0x620, 0xff }, { 0x621, 0xff }, { 0x622, 0xff }, { 0x623, 0xff }, 1278 { 0x624, 0xff }, { 0x625, 0xff }, { 0x626, 0xff }, { 0x627, 0xff }, 1279 { 0x652, 0x20 }, { 0x63c, 0x0a }, { 0x63d, 0x0a }, { 0x63e, 0x0e }, 1280 { 0x63f, 0x0e }, { 0x640, 0x40 }, { 0x66e, 0x05 }, { 0x700, 0x21 }, 1281 { 0x701, 0x43 }, { 0x702, 0x65 }, { 0x703, 0x87 }, { 0x708, 0x21 }, 1282 { 0x709, 0x43 }, { 0x70a, 0x65 }, { 0x70b, 0x87 } 1283}, rtl8192cu_mac[] = { 1284 { 0x420, 0x80 }, { 0x423, 0x00 }, { 0x430, 0x00 }, { 0x431, 0x00 }, 1285 { 0x432, 0x00 }, { 0x433, 0x01 }, { 0x434, 0x04 }, { 0x435, 0x05 }, 1286 { 0x436, 0x06 }, { 0x437, 0x07 }, { 0x438, 0x00 }, { 0x439, 0x00 }, 1287 { 0x43a, 0x00 }, { 0x43b, 0x01 }, { 0x43c, 0x04 }, { 0x43d, 0x05 }, 1288 { 0x43e, 0x06 }, { 0x43f, 0x07 }, { 0x440, 0x5d }, { 0x441, 0x01 }, 1289 { 0x442, 0x00 }, { 0x444, 0x15 }, { 0x445, 0xf0 }, { 0x446, 0x0f }, 1290 { 0x447, 0x00 }, { 0x458, 0x41 }, { 0x459, 0xa8 }, { 0x45a, 0x72 }, 1291 { 0x45b, 0xb9 }, { 0x460, 0x66 }, { 0x461, 0x66 }, { 0x462, 0x08 }, 1292 { 0x463, 0x03 }, { 0x4c8, 0xff }, { 0x4c9, 0x08 }, { 0x4cc, 0xff }, 1293 { 0x4cd, 0xff }, { 0x4ce, 0x01 }, { 0x500, 0x26 }, { 0x501, 0xa2 }, 1294 { 0x502, 0x2f }, { 0x503, 0x00 }, { 0x504, 0x28 }, { 0x505, 0xa3 }, 1295 { 0x506, 0x5e }, { 0x507, 0x00 }, { 0x508, 0x2b }, { 0x509, 0xa4 }, 1296 { 0x50a, 0x5e }, { 0x50b, 0x00 }, { 0x50c, 0x4f }, { 0x50d, 0xa4 }, 1297 { 0x50e, 0x00 }, { 0x50f, 0x00 }, { 0x512, 0x1c }, { 0x514, 0x0a }, 1298 { 0x515, 0x10 }, { 0x516, 0x0a }, { 0x517, 0x10 }, { 0x51a, 0x16 }, 1299 { 0x524, 0x0f }, { 0x525, 0x4f }, { 0x546, 0x40 }, { 0x547, 0x00 }, 1300 { 0x550, 0x10 }, { 0x551, 0x10 }, { 0x559, 0x02 }, { 0x55a, 0x02 }, 1301 { 0x55d, 0xff }, { 0x605, 0x30 }, { 0x608, 0x0e }, { 0x609, 0x2a }, 1302 { 0x652, 0x20 }, { 0x63c, 0x0a }, { 0x63d, 0x0e }, { 0x63e, 0x0a }, 1303 { 0x63f, 0x0e }, { 0x66e, 0x05 }, { 0x700, 0x21 }, { 0x701, 0x43 }, 1304 { 0x702, 0x65 }, { 0x703, 0x87 }, { 0x708, 0x21 }, { 0x709, 0x43 }, 1305 { 0x70a, 0x65 }, { 0x70b, 0x87 } 1306}; 1307 1308/* 1309 * Baseband initialization values. 1310 / 1311struct urtwn_bb_prog { 1312* int count; 1313 const uint16_t regs; 1314* const uint32_t vals; 1315* int agccount; 1316 const uint32_t agcvals; 1317}; 1318* 1319/* 1320 * RTL8192CU and RTL8192CE-VAU. 1321 / 1322static const uint16_t rtl8192ce_bb_regs[] = { 1323* 0x024, 0x028, 0x800, 0x804, 0x808, 0x80c, 0x810, 0x814, 0x818, 1324 0x81c, 0x820, 0x824, 0x828, 0x82c, 0x830, 0x834, 0x838, 0x83c, 1325 0x840, 0x844, 0x848, 0x84c, 0x850, 0x854, 0x858, 0x85c, 0x860, 1326 0x864, 0x868, 0x86c, 0x870, 0x874, 0x878, 0x87c, 0x880, 0x884, 1327 0x888, 0x88c, 0x890, 0x894, 0x898, 0x89c, 0x900, 0x904, 0x908, 1328 0x90c, 0xa00, 0xa04, 0xa08, 0xa0c, 0xa10, 0xa14, 0xa18, 0xa1c, 1329 0xa20, 0xa24, 0xa28, 0xa2c, 0xa70, 0xa74, 0xc00, 0xc04, 0xc08, 1330 0xc0c, 0xc10, 0xc14, 0xc18, 0xc1c, 0xc20, 0xc24, 0xc28, 0xc2c, 1331 0xc30, 0xc34, 0xc38, 0xc3c, 0xc40, 0xc44, 0xc48, 0xc4c, 0xc50, 1332 0xc54, 0xc58, 0xc5c, 0xc60, 0xc64, 0xc68, 0xc6c, 0xc70, 0xc74, 1333 0xc78, 0xc7c, 0xc80, 0xc84, 0xc88, 0xc8c, 0xc90, 0xc94, 0xc98, 1334 0xc9c, 0xca0, 0xca4, 0xca8, 0xcac, 0xcb0, 0xcb4, 0xcb8, 0xcbc, 1335 0xcc0, 0xcc4, 0xcc8, 0xccc, 0xcd0, 0xcd4, 0xcd8, 0xcdc, 0xce0, 1336 0xce4, 0xce8, 0xcec, 0xd00, 0xd04, 0xd08, 0xd0c, 0xd10, 0xd14, 1337 0xd18, 0xd2c, 0xd30, 0xd34, 0xd38, 0xd3c, 0xd40, 0xd44, 0xd48, 1338 0xd4c, 0xd50, 0xd54, 0xd58, 0xd5c, 0xd60, 0xd64, 0xd68, 0xd6c, 1339 0xd70, 0xd74, 0xd78, 0xe00, 0xe04, 0xe08, 0xe10, 0xe14, 0xe18, 1340 0xe1c, 0xe28, 0xe30, 0xe34, 0xe38, 0xe3c, 0xe40, 0xe44, 0xe48, 1341 0xe4c, 0xe50, 0xe54, 0xe58, 0xe5c, 0xe60, 0xe68, 0xe6c, 0xe70, 1342 0xe74, 0xe78, 0xe7c, 0xe80, 0xe84, 0xe88, 0xe8c, 0xed0, 0xed4, 1343 0xed8, 0xedc, 0xee0, 0xeec, 0xf14, 0xf4c, 0xf00 1344}; 1345 1346static const uint32_t rtl8192ce_bb_vals[] = { 1347 0x0011800d, 0x00ffdb83, 0x80040002, 0x00000003, 0x0000fc00, 1348 0x0000000a, 0x10005388, 0x020c3d10, 0x02200385, 0x00000000, 1349 0x01000100, 0x00390004, 0x01000100, 0x00390004, 0x27272727, 1350 0x27272727, 0x27272727, 0x27272727, 0x00010000, 0x00010000, 1351 0x27272727, 0x27272727, 0x00000000, 0x00000000, 0x569a569a, 1352 0x0c1b25a4, 0x66e60230, 0x061f0130, 0x27272727, 0x2b2b2b27, 1353 0x07000700, 0x22184000, 0x08080808, 0x00000000, 0xc0083070, 1354 0x000004d5, 0x00000000, 0xcc0000c0, 0x00000800, 0xfffffffe, 1355 0x40302010, 0x00706050, 0x00000000, 0x00000023, 0x00000000, 1356 0x81121313, 0x00d047c8, 0x80ff000c, 0x8c838300, 0x2e68120f, 1357 0x9500bb78, 0x11144028, 0x00881117, 0x89140f00, 0x1a1b0000, 1358 0x090e1317, 0x00000204, 0x00d30000, 0x101fbf00, 0x00000007, 1359 0x48071d40, 0x03a05633, 0x000000e4, 0x6c6c6c6c, 0x08800000, 1360 0x40000100, 0x08800000, 0x40000100, 0x00000000, 0x00000000, 1361 0x00000000, 0x00000000, 0x69e9ac44, 0x469652cf, 0x49795994, 1362 0x0a97971c, 0x1f7c403f, 0x000100b7, 0xec020107, 0x007f037f, 1363 0x6954341e, 0x43bc0094, 0x6954341e, 0x433c0094, 0x00000000, 1364 0x5116848b, 0x47c00bff, 0x00000036, 0x2c7f000d, 0x018610db, 1365 0x0000001f, 0x00b91612, 0x40000100, 0x20f60000, 0x40000100, 1366 0x20200000, 0x00121820, 0x00000000, 0x00121820, 0x00007f7f, 1367 0x00000000, 0x00000080, 0x00000000, 0x00000000, 0x00000000, 1368 0x00000000, 0x00000000, 0x28000000, 0x00000000, 0x00000000, 1369 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x64b22427, 1370 0x00766932, 0x00222222, 0x00000000, 0x37644302, 0x2f97d40c, 1371 0x00080740, 0x00020403, 0x0000907f, 0x20010201, 0xa0633333, 1372 0x3333bc43, 0x7a8f5b6b, 0xcc979975, 0x00000000, 0x80608000, 1373 0x00000000, 0x00027293, 0x00000000, 0x00000000, 0x00000000, 1374 0x00000000, 0x6437140a, 0x00000000, 0x00000000, 0x30032064, 1375 0x4653de68, 0x04518a3c, 0x00002101, 0x2a201c16, 0x1812362e, 1376 0x322c2220, 0x000e3c24, 0x2a2a2a2a, 0x2a2a2a2a, 0x03902a2a, 1377 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x00000000, 1378 0x1000dc1f, 0x10008c1f, 0x02140102, 0x681604c2, 0x01007c00, 1379 0x01004800, 0xfb000000, 0x000028d1, 0x1000dc1f, 0x10008c1f, 1380 0x02140102, 0x28160d05, 0x00000010, 0x001b25a4, 0x63db25a4, 1381 0x63db25a4, 0x0c1b25a4, 0x0c1b25a4, 0x0c1b25a4, 0x0c1b25a4, 1382 0x63db25a4, 0x0c1b25a4, 0x63db25a4, 0x63db25a4, 0x63db25a4, 1383 0x63db25a4, 0x001b25a4, 0x001b25a4, 0x6fdb25a4, 0x00000003, 1384 0x00000000, 0x00000300 1385}; 1386 1387static const uint32_t rtl8192ce_agc_vals[] = { 1388 0x7b000001, 0x7b010001, 0x7b020001, 0x7b030001, 0x7b040001, 1389 0x7b050001, 0x7a060001, 0x79070001, 0x78080001, 0x77090001, 1390 0x760a0001, 0x750b0001, 0x740c0001, 0x730d0001, 0x720e0001, 1391 0x710f0001, 0x70100001, 0x6f110001, 0x6e120001, 0x6d130001, 1392 0x6c140001, 0x6b150001, 0x6a160001, 0x69170001, 0x68180001, 1393 0x67190001, 0x661a0001, 0x651b0001, 0x641c0001, 0x631d0001, 1394 0x621e0001, 0x611f0001, 0x60200001, 0x49210001, 0x48220001, 1395 0x47230001, 0x46240001, 0x45250001, 0x44260001, 0x43270001, 1396 0x42280001, 0x41290001, 0x402a0001, 0x262b0001, 0x252c0001, 1397 0x242d0001, 0x232e0001, 0x222f0001, 0x21300001, 0x20310001, 1398 0x06320001, 0x05330001, 0x04340001, 0x03350001, 0x02360001, 1399 0x01370001, 0x00380001, 0x00390001, 0x003a0001, 0x003b0001, 1400 0x003c0001, 0x003d0001, 0x003e0001, 0x003f0001, 0x7b400001, 1401 0x7b410001, 0x7b420001, 0x7b430001, 0x7b440001, 0x7b450001, 1402 0x7a460001, 0x79470001, 0x78480001, 0x77490001, 0x764a0001, 1403 0x754b0001, 0x744c0001, 0x734d0001, 0x724e0001, 0x714f0001, 1404 0x70500001, 0x6f510001, 0x6e520001, 0x6d530001, 0x6c540001, 1405 0x6b550001, 0x6a560001, 0x69570001, 0x68580001, 0x67590001, 1406 0x665a0001, 0x655b0001, 0x645c0001, 0x635d0001, 0x625e0001, 1407 0x615f0001, 0x60600001, 0x49610001, 0x48620001, 0x47630001, 1408 0x46640001, 0x45650001, 0x44660001, 0x43670001, 0x42680001, 1409 0x41690001, 0x406a0001, 0x266b0001, 0x256c0001, 0x246d0001, 1410 0x236e0001, 0x226f0001, 0x21700001, 0x20710001, 0x06720001, 1411 0x05730001, 0x04740001, 0x03750001, 0x02760001, 0x01770001, 1412 0x00780001, 0x00790001, 0x007a0001, 0x007b0001, 0x007c0001, 1413 0x007d0001, 0x007e0001, 0x007f0001, 0x3800001e, 0x3801001e, 1414 0x3802001e, 0x3803001e, 0x3804001e, 0x3805001e, 0x3806001e, 1415 0x3807001e, 0x3808001e, 0x3c09001e, 0x3e0a001e, 0x400b001e, 1416 0x440c001e, 0x480d001e, 0x4c0e001e, 0x500f001e, 0x5210001e, 1417 0x5611001e, 0x5a12001e, 0x5e13001e, 0x6014001e, 0x6015001e, 1418 0x6016001e, 0x6217001e, 0x6218001e, 0x6219001e, 0x621a001e, 1419 0x621b001e, 0x621c001e, 0x621d001e, 0x621e001e, 0x621f001e 1420}; 1421 1422static const struct urtwn_bb_prog rtl8192ce_bb_prog = { 1423 nitems(rtl8192ce_bb_regs), 1424 rtl8192ce_bb_regs, 1425 rtl8192ce_bb_vals, 1426 nitems(rtl8192ce_agc_vals), 1427 rtl8192ce_agc_vals 1428}; 1429 1430/* 1431 * RTL8188CU. 1432 / 1433static const uint32_t rtl8192cu_bb_vals[] = { 1434* 0x0011800d, 0x00ffdb83, 0x80040002, 0x00000003, 0x0000fc00, 1435 0x0000000a, 0x10005388, 0x020c3d10, 0x02200385, 0x00000000, 1436 0x01000100, 0x00390004, 0x01000100, 0x00390004, 0x27272727, 1437 0x27272727, 0x27272727, 0x27272727, 0x00010000, 0x00010000, 1438 0x27272727, 0x27272727, 0x00000000, 0x00000000, 0x569a569a, 1439 0x0c1b25a4, 0x66e60230, 0x061f0130, 0x27272727, 0x2b2b2b27, 1440 0x07000700, 0x22184000, 0x08080808, 0x00000000, 0xc0083070, 1441 0x000004d5, 0x00000000, 0xcc0000c0, 0x00000800, 0xfffffffe, 1442 0x40302010, 0x00706050, 0x00000000, 0x00000023, 0x00000000, 1443 0x81121313, 0x00d047c8, 0x80ff000c, 0x8c838300, 0x2e68120f, 1444 0x9500bb78, 0x11144028, 0x00881117, 0x89140f00, 0x1a1b0000, 1445 0x090e1317, 0x00000204, 0x00d30000, 0x101fbf00, 0x00000007, 1446 0x48071d40, 0x03a05633, 0x000000e4, 0x6c6c6c6c, 0x08800000, 1447 0x40000100, 0x08800000, 0x40000100, 0x00000000, 0x00000000, 1448 0x00000000, 0x00000000, 0x69e9ac44, 0x469652cf, 0x49795994, 1449 0x0a97971c, 0x1f7c403f, 0x000100b7, 0xec020107, 0x007f037f, 1450 0x6954341e, 0x43bc0094, 0x6954341e, 0x433c0094, 0x00000000, 1451 0x5116848b, 0x47c00bff, 0x00000036, 0x2c7f000d, 0x0186115b, 1452 0x0000001f, 0x00b99612, 0x40000100, 0x20f60000, 0x40000100, 1453 0x20200000, 0x00121820, 0x00000000, 0x00121820, 0x00007f7f, 1454 0x00000000, 0x00000080, 0x00000000, 0x00000000, 0x00000000, 1455 0x00000000, 0x00000000, 0x28000000, 0x00000000, 0x00000000, 1456 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x64b22427, 1457 0x00766932, 0x00222222, 0x00000000, 0x37644302, 0x2f97d40c, 1458 0x00080740, 0x00020403, 0x0000907f, 0x20010201, 0xa0633333, 1459 0x3333bc43, 0x7a8f5b6b, 0xcc979975, 0x00000000, 0x80608000, 1460 0x00000000, 0x00027293, 0x00000000, 0x00000000, 0x00000000, 1461 0x00000000, 0x6437140a, 0x00000000, 0x00000000, 0x30032064, 1462 0x4653de68, 0x04518a3c, 0x00002101, 0x2a201c16, 0x1812362e, 1463 0x322c2220, 0x000e3c24, 0x2a2a2a2a, 0x2a2a2a2a, 0x03902a2a, 1464 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x00000000, 1465 0x1000dc1f, 0x10008c1f, 0x02140102, 0x681604c2, 0x01007c00, 1466 0x01004800, 0xfb000000, 0x000028d1, 0x1000dc1f, 0x10008c1f, 1467 0x02140102, 0x28160d05, 0x00000010, 0x001b25a4, 0x63db25a4, 1468 0x63db25a4, 0x0c1b25a4, 0x0c1b25a4, 0x0c1b25a4, 0x0c1b25a4, 1469 0x63db25a4, 0x0c1b25a4, 0x63db25a4, 0x63db25a4, 0x63db25a4, 1470 0x63db25a4, 0x001b25a4, 0x001b25a4, 0x6fdb25a4, 0x00000003, 1471 0x00000000, 0x00000300 1472}; 1473 1474static const struct urtwn_bb_prog rtl8192cu_bb_prog = { 1475 nitems(rtl8192ce_bb_regs), 1476 rtl8192ce_bb_regs, 1477 rtl8192cu_bb_vals, 1478 nitems(rtl8192ce_agc_vals), 1479 rtl8192ce_agc_vals 1480}; 1481 1482/* 1483 * RTL8188CE-VAU. 1484 / 1485static const uint32_t rtl8188ce_bb_vals[] = { 1486* 0x0011800d, 0x00ffdb83, 0x80040000, 0x00000001, 0x0000fc00, 1487 0x0000000a, 0x10005388, 0x020c3d10, 0x02200385, 0x00000000, 1488 0x01000100, 0x00390004, 0x00000000, 0x00000000, 0x00000000, 1489 0x00000000, 0x00000000, 0x00000000, 0x00010000, 0x00000000, 1490 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x569a569a, 1491 0x001b25a4, 0x66e60230, 0x061f0130, 0x00000000, 0x32323200, 1492 0x07000700, 0x22004000, 0x00000808, 0x00000000, 0xc0083070, 1493 0x000004d5, 0x00000000, 0xccc000c0, 0x00000800, 0xfffffffe, 1494 0x40302010, 0x00706050, 0x00000000, 0x00000023, 0x00000000, 1495 0x81121111, 0x00d047c8, 0x80ff000c, 0x8c838300, 0x2e68120f, 1496 0x9500bb78, 0x11144028, 0x00881117, 0x89140f00, 0x1a1b0000, 1497 0x090e1317, 0x00000204, 0x00d30000, 0x101fbf00, 0x00000007, 1498 0x48071d40, 0x03a05611, 0x000000e4, 0x6c6c6c6c, 0x08800000, 1499 0x40000100, 0x08800000, 0x40000100, 0x00000000, 0x00000000, 1500 0x00000000, 0x00000000, 0x69e9ac44, 0x469652cf, 0x49795994, 1501 0x0a97971c, 0x1f7c403f, 0x000100b7, 0xec020107, 0x007f037f, 1502 0x6954341e, 0x43bc0094, 0x6954341e, 0x433c0094, 0x00000000, 1503 0x5116848b, 0x47c00bff, 0x00000036, 0x2c7f000d, 0x018610db, 1504 0x0000001f, 0x00b91612, 0x40000100, 0x20f60000, 0x40000100, 1505 0x20200000, 0x00121820, 0x00000000, 0x00121820, 0x00007f7f, 1506 0x00000000, 0x00000080, 0x00000000, 0x00000000, 0x00000000, 1507 0x00000000, 0x00000000, 0x28000000, 0x00000000, 0x00000000, 1508 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x64b22427, 1509 0x00766932, 0x00222222, 0x00000000, 0x37644302, 0x2f97d40c, 1510 0x00080740, 0x00020401, 0x0000907f, 0x20010201, 0xa0633333, 1511 0x3333bc43, 0x7a8f5b6b, 0xcc979975, 0x00000000, 0x80608000, 1512 0x00000000, 0x00027293, 0x00000000, 0x00000000, 0x00000000, 1513 0x00000000, 0x6437140a, 0x00000000, 0x00000000, 0x30032064, 1514 0x4653de68, 0x04518a3c, 0x00002101, 0x2a201c16, 0x1812362e, 1515 0x322c2220, 0x000e3c24, 0x2a2a2a2a, 0x2a2a2a2a, 0x03902a2a, 1516 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x00000000, 1517 0x1000dc1f, 0x10008c1f, 0x02140102, 0x681604c2, 0x01007c00, 1518 0x01004800, 0xfb000000, 0x000028d1, 0x1000dc1f, 0x10008c1f, 1519 0x02140102, 0x28160d05, 0x00000008, 0x001b25a4, 0x631b25a0, 1520 0x631b25a0, 0x081b25a0, 0x081b25a0, 0x081b25a0, 0x081b25a0, 1521 0x631b25a0, 0x081b25a0, 0x631b25a0, 0x631b25a0, 0x631b25a0, 1522 0x631b25a0, 0x001b25a0, 0x001b25a0, 0x6b1b25a0, 0x00000003, 1523 0x00000000, 0x00000300 1524}; 1525 1526static const uint32_t rtl8188ce_agc_vals[] = { 1527 0x7b000001, 0x7b010001, 0x7b020001, 0x7b030001, 0x7b040001, 1528 0x7b050001, 0x7a060001, 0x79070001, 0x78080001, 0x77090001, 1529 0x760a0001, 0x750b0001, 0x740c0001, 0x730d0001, 0x720e0001, 1530 0x710f0001, 0x70100001, 0x6f110001, 0x6e120001, 0x6d130001, 1531 0x6c140001, 0x6b150001, 0x6a160001, 0x69170001, 0x68180001, 1532 0x67190001, 0x661a0001, 0x651b0001, 0x641c0001, 0x631d0001, 1533 0x621e0001, 0x611f0001, 0x60200001, 0x49210001, 0x48220001, 1534 0x47230001, 0x46240001, 0x45250001, 0x44260001, 0x43270001, 1535 0x42280001, 0x41290001, 0x402a0001, 0x262b0001, 0x252c0001, 1536 0x242d0001, 0x232e0001, 0x222f0001, 0x21300001, 0x20310001, 1537 0x06320001, 0x05330001, 0x04340001, 0x03350001, 0x02360001, 1538 0x01370001, 0x00380001, 0x00390001, 0x003a0001, 0x003b0001, 1539 0x003c0001, 0x003d0001, 0x003e0001, 0x003f0001, 0x7b400001, 1540 0x7b410001, 0x7b420001, 0x7b430001, 0x7b440001, 0x7b450001, 1541 0x7a460001, 0x79470001, 0x78480001, 0x77490001, 0x764a0001, 1542 0x754b0001, 0x744c0001, 0x734d0001, 0x724e0001, 0x714f0001, 1543 0x70500001, 0x6f510001, 0x6e520001, 0x6d530001, 0x6c540001, 1544 0x6b550001, 0x6a560001, 0x69570001, 0x68580001, 0x67590001, 1545 0x665a0001, 0x655b0001, 0x645c0001, 0x635d0001, 0x625e0001, 1546 0x615f0001, 0x60600001, 0x49610001, 0x48620001, 0x47630001, 1547 0x46640001, 0x45650001, 0x44660001, 0x43670001, 0x42680001, 1548 0x41690001, 0x406a0001, 0x266b0001, 0x256c0001, 0x246d0001, 1549 0x236e0001, 0x226f0001, 0x21700001, 0x20710001, 0x06720001, 1550 0x05730001, 0x04740001, 0x03750001, 0x02760001, 0x01770001, 1551 0x00780001, 0x00790001, 0x007a0001, 0x007b0001, 0x007c0001, 1552 0x007d0001, 0x007e0001, 0x007f0001, 0x3800001e, 0x3801001e, 1553 0x3802001e, 0x3803001e, 0x3804001e, 0x3805001e, 0x3806001e, 1554 0x3807001e, 0x3808001e, 0x3c09001e, 0x3e0a001e, 0x400b001e, 1555 0x440c001e, 0x480d001e, 0x4c0e001e, 0x500f001e, 0x5210001e, 1556 0x5611001e, 0x5a12001e, 0x5e13001e, 0x6014001e, 0x6015001e, 1557 0x6016001e, 0x6217001e, 0x6218001e, 0x6219001e, 0x621a001e, 1558 0x621b001e, 0x621c001e, 0x621d001e, 0x621e001e, 0x621f001e 1559}; 1560 1561static const struct urtwn_bb_prog rtl8188ce_bb_prog = { 1562 nitems(rtl8192ce_bb_regs), 1563 rtl8192ce_bb_regs, 1564 rtl8188ce_bb_vals, 1565 nitems(rtl8188ce_agc_vals), 1566 rtl8188ce_agc_vals 1567}; 1568 1569static const uint32_t rtl8188cu_bb_vals[] = { 1570 0x0011800d, 0x00ffdb83, 0x80040000, 0x00000001, 0x0000fc00, 1571 0x0000000a, 0x10005388, 0x020c3d10, 0x02200385, 0x00000000, 1572 0x01000100, 0x00390004, 0x00000000, 0x00000000, 0x00000000, 1573 0x00000000, 0x00000000, 0x00000000, 0x00010000, 0x00000000, 1574 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x569a569a, 1575 0x001b25a4, 0x66e60230, 0x061f0130, 0x00000000, 0x32323200, 1576 0x07000700, 0x22004000, 0x00000808, 0x00000000, 0xc0083070, 1577 0x000004d5, 0x00000000, 0xccc000c0, 0x00000800, 0xfffffffe, 1578 0x40302010, 0x00706050, 0x00000000, 0x00000023, 0x00000000, 1579 0x81121111, 0x00d047c8, 0x80ff000c, 0x8c838300, 0x2e68120f, 1580 0x9500bb78, 0x11144028, 0x00881117, 0x89140f00, 0x1a1b0000, 1581 0x090e1317, 0x00000204, 0x00d30000, 0x101fbf00, 0x00000007, 1582 0x48071d40, 0x03a05611, 0x000000e4, 0x6c6c6c6c, 0x08800000, 1583 0x40000100, 0x08800000, 0x40000100, 0x00000000, 0x00000000, 1584 0x00000000, 0x00000000, 0x69e9ac44, 0x469652cf, 0x49795994, 1585 0x0a97971c, 0x1f7c403f, 0x000100b7, 0xec020107, 0x007f037f, 1586 0x6954341e, 0x43bc0094, 0x6954341e, 0x433c0094, 0x00000000, 1587 0x5116848b, 0x47c00bff, 0x00000036, 0x2c7f000d, 0x018610db, 1588 0x0000001f, 0x00b91612, 0x40000100, 0x20f60000, 0x40000100, 1589 0x20200000, 0x00121820, 0x00000000, 0x00121820, 0x00007f7f, 1590 0x00000000, 0x00000080, 0x00000000, 0x00000000, 0x00000000, 1591 0x00000000, 0x00000000, 0x28000000, 0x00000000, 0x00000000, 1592 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x64b22427, 1593 0x00766932, 0x00222222, 0x00000000, 0x37644302, 0x2f97d40c, 1594 0x00080740, 0x00020401, 0x0000907f, 0x20010201, 0xa0633333, 1595 0x3333bc43, 0x7a8f5b6b, 0xcc979975, 0x00000000, 0x80608000, 1596 0x00000000, 0x00027293, 0x00000000, 0x00000000, 0x00000000, 1597 0x00000000, 0x6437140a, 0x00000000, 0x00000000, 0x30032064, 1598 0x4653de68, 0x04518a3c, 0x00002101, 0x2a201c16, 0x1812362e, 1599 0x322c2220, 0x000e3c24, 0x2a2a2a2a, 0x2a2a2a2a, 0x03902a2a, 1600 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x00000000, 1601 0x1000dc1f, 0x10008c1f, 0x02140102, 0x681604c2, 0x01007c00, 1602 0x01004800, 0xfb000000, 0x000028d1, 0x1000dc1f, 0x10008c1f, 1603 0x02140102, 0x28160d05, 0x00000008, 0x001b25a4, 0x631b25a0, 1604 0x631b25a0, 0x081b25a0, 0x081b25a0, 0x081b25a0, 0x081b25a0, 1605 0x631b25a0, 0x081b25a0, 0x631b25a0, 0x631b25a0, 0x631b25a0, 1606 0x631b25a0, 0x001b25a0, 0x001b25a0, 0x6b1b25a0, 0x00000003, 1607 0x00000000, 0x00000300 1608}; 1609 1610static const struct urtwn_bb_prog rtl8188cu_bb_prog = { 1611 nitems(rtl8192ce_bb_regs), 1612 rtl8192ce_bb_regs, 1613 rtl8188cu_bb_vals, 1614 nitems(rtl8188ce_agc_vals), 1615 rtl8188ce_agc_vals 1616}; 1617 1618/* 1619 * RTL8188EU. 1620 / 1621static const uint16_t rtl8188eu_bb_regs[] = { 1622* 0x800, 0x804, 0x808, 0x80c, 0x810, 0x814, 0x818, 0x81c, 1623 0x820, 0x824, 0x828, 0x82c, 0x830, 0x834, 0x838, 0x83c, 1624 0x840, 0x844, 0x848, 0x84c, 0x850, 0x854, 0x858, 0x85c, 1625 0x860, 0x864, 0x868, 0x86c, 0x870, 0x874, 0x878, 0x87c, 1626 0x880, 0x884, 0x888, 0x88c, 0x890, 0x894, 0x898, 0x89c, 1627 0x900, 0x904, 0x908, 0x90c, 0x910, 0x914, 0xa00, 0xa04, 1628 0xa08, 0xa0c, 0xa10, 0xa14, 0xa18, 0xa1c, 0xa20, 0xa24, 1629 0xa28, 0xa2c, 0xa70, 0xa74, 0xa78, 0xa7c, 0xa80, 0xb2c, 1630 0xc00, 0xc04, 0xc08, 0xc0c, 0xc10, 0xc14, 0xc18, 0xc1c, 1631 0xc20, 0xc24, 0xc28, 0xc2c, 0xc30, 0xc34, 0xc38, 0xc3c, 1632 0xc40, 0xc44, 0xc48, 0xc4c, 0xc50, 0xc54, 0xc58, 0xc5c, 1633 0xc60, 0xc64, 0xc68, 0xc6c, 0xc70, 0xc74, 0xc78, 0xc7c, 1634 0xc80, 0xc84, 0xc88, 0xc8c, 0xc90, 0xc94, 0xc98, 0xc9c, 1635 0xca0, 0xca4, 0xca8, 0xcac, 0xcb0, 0xcb4, 0xcb8, 0xcbc, 1636 0xcc0, 0xcc4, 0xcc8, 0xccc, 0xcd0, 0xcd4, 0xcd8, 0xcdc, 1637 0xce0, 0xce4, 0xce8, 0xcec, 0xd00, 0xd04, 0xd08, 0xd0c, 1638 0xd10, 0xd14, 0xd18, 0xd2c, 0xd30, 0xd34, 0xd38, 0xd3c, 1639 0xd40, 0xd44, 0xd48, 0xd4c, 0xd50, 0xd54, 0xd58, 0xd5c, 1640 0xd60, 0xd64, 0xd68, 0xd6c, 0xd70, 0xd74, 0xd78, 0xe00, 1641 0xe04, 0xe08, 0xe10, 0xe14, 0xe18, 0xe1c, 0xe28, 0xe30, 1642 0xe34, 0xe38, 0xe3c, 0xe40, 0xe44, 0xe48, 0xe4c, 0xe50, 1643 0xe54, 0xe58, 0xe5c, 0xe60, 0xe68, 0xe6c, 0xe70, 0xe74, 1644 0xe78, 0xe7c, 0xe80, 0xe84, 0xe88, 0xe8c, 0xed0, 0xed4, 1645 0xed8, 0xedc, 0xee0, 0xee8, 0xeec, 0xf14, 0xf4c, 0xf00 1646}; 1647 1648static const uint32_t rtl8188eu_bb_vals[] = { 1649 0x80040000, 0x00000003, 0x0000fc00, 0x0000000a, 0x10001331, 1650 0x020c3d10, 0x02200385, 0x00000000, 0x01000100, 0x00390204, 1651 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 1652 0x00000000, 0x00010000, 0x00000000, 0x00000000, 0x00000000, 1653 0x00000000, 0x00000000, 0x569a11a9, 0x01000014, 0x66f60110, 1654 0x061f0649, 0x00000000, 0x27272700, 0x07000760, 0x25004000, 1655 0x00000808, 0x00000000, 0xb0000c1c, 0x00000001, 0x00000000, 1656 0xccc000c0, 0x00000800, 0xfffffffe, 0x40302010, 0x00706050, 1657 0x00000000, 0x00000023, 0x00000000, 0x81121111, 0x00000002, 1658 0x00000201, 0x00d047c8, 0x80ff000c, 0x8c838300, 0x2e7f120f, 1659 0x9500bb78, 0x1114d028, 0x00881117, 0x89140f00, 0x1a1b0000, 1660 0x090e1317, 0x00000204, 0x00d30000, 0x101fbf00, 0x00000007, 1661 0x00000900, 0x225b0606, 0x218075b1, 0x80000000, 0x48071d40, 1662 0x03a05611, 0x000000e4, 0x6c6c6c6c, 0x08800000, 0x40000100, 1663 0x08800000, 0x40000100, 0x00000000, 0x00000000, 0x00000000, 1664 0x00000000, 0x69e9ac47, 0x469652af, 0x49795994, 0x0a97971c, 1665 0x1f7c403f, 0x000100b7, 0xec020107, 0x007f037f, 0x69553420, 1666 0x43bc0094, 0x00013169, 0x00250492, 0x00000000, 0x7112848b, 1667 0x47c00bff, 0x00000036, 0x2c7f000d, 0x020610db, 0x0000001f, 1668 0x00b91612, 0x390000e4, 0x20f60000, 0x40000100, 0x20200000, 1669 0x00091521, 0x00000000, 0x00121820, 0x00007f7f, 0x00000000, 1670 0x000300a0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 1671 0x00000000, 0x28000000, 0x00000000, 0x00000000, 0x00000000, 1672 0x00000000, 0x00000000, 0x00000000, 0x64b22427, 0x00766932, 1673 0x00222222, 0x00000000, 0x37644302, 0x2f97d40c, 0x00000740, 1674 0x00020401, 0x0000907f, 0x20010201, 0xa0633333, 0x3333bc43, 1675 0x7a8f5b6f, 0xcc979975, 0x00000000, 0x80608000, 0x00000000, 1676 0x00127353, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 1677 0x6437140a, 0x00000000, 0x00000282, 0x30032064, 0x4653de68, 1678 0x04518a3c, 0x00002101, 0x2a201c16, 0x1812362e, 0x322c2220, 1679 0x000e3c24, 0x2d2d2d2d, 0x2d2d2d2d, 0x0390272d, 0x2d2d2d2d, 1680 0x2d2d2d2d, 0x2d2d2d2d, 0x2d2d2d2d, 0x00000000, 0x1000dc1f, 1681 0x10008c1f, 0x02140102, 0x681604c2, 0x01007c00, 0x01004800, 1682 0xfb000000, 0x000028d1, 0x1000dc1f, 0x10008c1f, 0x02140102, 1683 0x28160d05, 0x00000008, 0x001b25a4, 0x00c00014, 0x00c00014, 1684 0x01000014, 0x01000014, 0x01000014, 0x01000014, 0x00c00014, 1685 0x01000014, 0x00c00014, 0x00c00014, 0x00c00014, 0x00c00014, 1686 0x00000014, 0x00000014, 0x21555448, 0x01c00014, 0x00000003, 1687 0x00000000, 0x00000300 1688}; 1689 1690static const uint32_t rtl8188eu_agc_vals[] = { 1691 0xfb000001, 0xfb010001, 0xfb020001, 0xfb030001, 0xfb040001, 1692 0xfb050001, 0xfa060001, 0xf9070001, 0xf8080001, 0xf7090001, 1693 0xf60a0001, 0xf50b0001, 0xf40c0001, 0xf30d0001, 0xf20e0001, 1694 0xf10f0001, 0xf0100001, 0xef110001, 0xee120001, 0xed130001, 1695 0xec140001, 0xeb150001, 0xea160001, 0xe9170001, 0xe8180001, 1696 0xe7190001, 0xe61a0001, 0xe51b0001, 0xe41c0001, 0xe31d0001, 1697 0xe21e0001, 0xe11f0001, 0x8a200001, 0x89210001, 0x88220001, 1698 0x87230001, 0x86240001, 0x85250001, 0x84260001, 0x83270001, 1699 0x82280001, 0x6b290001, 0x6a2a0001, 0x692b0001, 0x682c0001, 1700 0x672d0001, 0x662e0001, 0x652f0001, 0x64300001, 0x63310001, 1701 0x62320001, 0x61330001, 0x46340001, 0x45350001, 0x44360001, 1702 0x43370001, 0x42380001, 0x41390001, 0x403a0001, 0x403b0001, 1703 0x403c0001, 0x403d0001, 0x403e0001, 0x403f0001, 0xfb400001, 1704 0xfb410001, 0xfb420001, 0xfb430001, 0xfb440001, 0xfb450001, 1705 0xfb460001, 0xfb470001, 0xfb480001, 0xfa490001, 0xf94a0001, 1706 0xf84B0001, 0xf74c0001, 0xf64d0001, 0xf54e0001, 0xf44f0001, 1707 0xf3500001, 0xf2510001, 0xf1520001, 0xf0530001, 0xef540001, 1708 0xee550001, 0xed560001, 0xec570001, 0xeb580001, 0xea590001, 1709 0xe95a0001, 0xe85b0001, 0xe75c0001, 0xe65d0001, 0xe55e0001, 1710 0xe45f0001, 0xe3600001, 0xe2610001, 0xc3620001, 0xc2630001, 1711 0xc1640001, 0x8b650001, 0x8a660001, 0x89670001, 0x88680001, 1712 0x87690001, 0x866a0001, 0x856b0001, 0x846c0001, 0x676d0001, 1713 0x666e0001, 0x656f0001, 0x64700001, 0x63710001, 0x62720001, 1714 0x61730001, 0x60740001, 0x46750001, 0x45760001, 0x44770001, 1715 0x43780001, 0x42790001, 0x417a0001, 0x407b0001, 0x407c0001, 1716 0x407d0001, 0x407e0001, 0x407f0001 1717}; 1718 1719static const struct urtwn_bb_prog rtl8188eu_bb_prog = { 1720 nitems(rtl8188eu_bb_regs), 1721 rtl8188eu_bb_regs, 1722 rtl8188eu_bb_vals, 1723 nitems(rtl8188eu_agc_vals), 1724 rtl8188eu_agc_vals 1725}; 1726 1727/* 1728 * RTL8188RU. 1729 / 1730static const uint16_t rtl8188ru_bb_regs[] = { 1731* 0x024, 0x028, 0x040, 0x800, 0x804, 0x808, 0x80c, 0x810, 0x814, 1732 0x818, 0x81c, 0x820, 0x824, 0x828, 0x82c, 0x830, 0x834, 0x838, 1733 0x83c, 0x840, 0x844, 0x848, 0x84c, 0x850, 0x854, 0x858, 0x85c, 1734 0x860, 0x864, 0x868, 0x86c, 0x870, 0x874, 0x878, 0x87c, 0x880, 1735 0x884, 0x888, 0x88c, 0x890, 0x894, 0x898, 0x89c, 0x900, 0x904, 1736 0x908, 0x90c, 0xa00, 0xa04, 0xa08, 0xa0c, 0xa10, 0xa14, 0xa18, 1737 0xa1c, 0xa20, 0xa24, 0xa28, 0xa2c, 0xa70, 0xa74, 0xc00, 0xc04, 1738 0xc08, 0xc0c, 0xc10, 0xc14, 0xc18, 0xc1c, 0xc20, 0xc24, 0xc28, 1739 0xc2c, 0xc30, 0xc34, 0xc38, 0xc3c, 0xc40, 0xc44, 0xc48, 0xc4c, 1740 0xc50, 0xc54, 0xc58, 0xc5c, 0xc60, 0xc64, 0xc68, 0xc6c, 0xc70, 1741 0xc74, 0xc78, 0xc7c, 0xc80, 0xc84, 0xc88, 0xc8c, 0xc90, 0xc94, 1742 0xc98, 0xc9c, 0xca0, 0xca4, 0xca8, 0xcac, 0xcb0, 0xcb4, 0xcb8, 1743 0xcbc, 0xcc0, 0xcc4, 0xcc8, 0xccc, 0xcd0, 0xcd4, 0xcd8, 0xcdc, 1744 0xce0, 0xce4, 0xce8, 0xcec, 0xd00, 0xd04, 0xd08, 0xd0c, 0xd10, 1745 0xd14, 0xd18, 0xd2c, 0xd30, 0xd34, 0xd38, 0xd3c, 0xd40, 0xd44, 1746 0xd48, 0xd4c, 0xd50, 0xd54, 0xd58, 0xd5c, 0xd60, 0xd64, 0xd68, 1747 0xd6c, 0xd70, 0xd74, 0xd78, 0xe00, 0xe04, 0xe08, 0xe10, 0xe14, 1748 0xe18, 0xe1c, 0xe28, 0xe30, 0xe34, 0xe38, 0xe3c, 0xe40, 0xe44, 1749 0xe48, 0xe4c, 0xe50, 0xe54, 0xe58, 0xe5c, 0xe60, 0xe68, 0xe6c, 1750 0xe70, 0xe74, 0xe78, 0xe7c, 0xe80, 0xe84, 0xe88, 0xe8c, 0xed0, 1751 0xed4, 0xed8, 0xedc, 0xee0, 0xeec, 0xee8, 0xf14, 0xf4c, 0xf00 1752}; 1753 1754static const uint32_t rtl8188ru_bb_vals[] = { 1755 0x0011800d, 0x00ffdb83, 0x000c0004, 0x80040000, 0x00000001, 1756 0x0000fc00, 0x0000000a, 0x10005388, 0x020c3d10, 0x02200385, 1757 0x00000000, 0x01000100, 0x00390204, 0x00000000, 0x00000000, 1758 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00010000, 1759 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 1760 0x569a569a, 0x001b25a4, 0x66e60230, 0x061f0130, 0x00000000, 1761 0x32323200, 0x03000300, 0x22004000, 0x00000808, 0x00ffc3f1, 1762 0xc0083070, 0x000004d5, 0x00000000, 0xccc000c0, 0x00000800, 1763 0xfffffffe, 0x40302010, 0x00706050, 0x00000000, 0x00000023, 1764 0x00000000, 0x81121111, 0x00d047c8, 0x80ff000c, 0x8c838300, 1765 0x2e68120f, 0x9500bb78, 0x11144028, 0x00881117, 0x89140f00, 1766 0x15160000, 0x070b0f12, 0x00000104, 0x00d30000, 0x101fbf00, 1767 0x00000007, 0x48071d40, 0x03a05611, 0x000000e4, 0x6c6c6c6c, 1768 0x08800000, 0x40000100, 0x08800000, 0x40000100, 0x00000000, 1769 0x00000000, 0x00000000, 0x00000000, 0x69e9ac44, 0x469652cf, 1770 0x49795994, 0x0a97971c, 0x1f7c403f, 0x000100b7, 0xec020107, 1771 0x007f037f, 0x6954342e, 0x43bc0094, 0x6954342f, 0x433c0094, 1772 0x00000000, 0x5116848b, 0x47c00bff, 0x00000036, 0x2c56000d, 1773 0x018610db, 0x0000001f, 0x00b91612, 0x24000090, 0x20f60000, 1774 0x24000090, 0x20200000, 0x00121820, 0x00000000, 0x00121820, 1775 0x00007f7f, 0x00000000, 0x00000080, 0x00000000, 0x00000000, 1776 0x00000000, 0x00000000, 0x00000000, 0x28000000, 0x00000000, 1777 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 1778 0x64b22427, 0x00766932, 0x00222222, 0x00000000, 0x37644302, 1779 0x2f97d40c, 0x00080740, 0x00020401, 0x0000907f, 0x20010201, 1780 0xa0633333, 0x3333bc43, 0x7a8f5b6b, 0xcc979975, 0x00000000, 1781 0x80608000, 0x00000000, 0x00027293, 0x00000000, 0x00000000, 1782 0x00000000, 0x00000000, 0x6437140a, 0x00000000, 0x00000000, 1783 0x30032064, 0x4653de68, 0x04518a3c, 0x00002101, 0x2a201c16, 1784 0x1812362e, 0x322c2220, 0x000e3c24, 0x2a2a2a2a, 0x2a2a2a2a, 1785 0x03902a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 1786 0x00000000, 0x1000dc1f, 0x10008c1f, 0x02140102, 0x681604c2, 1787 0x01007c00, 0x01004800, 0xfb000000, 0x000028d1, 0x1000dc1f, 1788 0x10008c1f, 0x02140102, 0x28160d05, 0x00000010, 0x001b25a4, 1789 0x631b25a0, 0x631b25a0, 0x081b25a0, 0x081b25a0, 0x081b25a0, 1790 0x081b25a0, 0x631b25a0, 0x081b25a0, 0x631b25a0, 0x631b25a0, 1791 0x631b25a0, 0x631b25a0, 0x001b25a0, 0x001b25a0, 0x6b1b25a0, 1792 0x31555448, 0x00000003, 0x00000000, 0x00000300 1793}; 1794 1795static const uint32_t rtl8188ru_agc_vals[] = { 1796 0x7b000001, 0x7b010001, 0x7b020001, 0x7b030001, 0x7b040001, 1797 0x7b050001, 0x7b060001, 0x7b070001, 0x7b080001, 0x7a090001, 1798 0x790a0001, 0x780b0001, 0x770c0001, 0x760d0001, 0x750e0001, 1799 0x740f0001, 0x73100001, 0x72110001, 0x71120001, 0x70130001, 1800 0x6f140001, 0x6e150001, 0x6d160001, 0x6c170001, 0x6b180001, 1801 0x6a190001, 0x691a0001, 0x681b0001, 0x671c0001, 0x661d0001, 1802 0x651e0001, 0x641f0001, 0x63200001, 0x62210001, 0x61220001, 1803 0x60230001, 0x46240001, 0x45250001, 0x44260001, 0x43270001, 1804 0x42280001, 0x41290001, 0x402a0001, 0x262b0001, 0x252c0001, 1805 0x242d0001, 0x232e0001, 0x222f0001, 0x21300001, 0x20310001, 1806 0x06320001, 0x05330001, 0x04340001, 0x03350001, 0x02360001, 1807 0x01370001, 0x00380001, 0x00390001, 0x003a0001, 0x003b0001, 1808 0x003c0001, 0x003d0001, 0x003e0001, 0x003f0001, 0x7b400001, 1809 0x7b410001, 0x7b420001, 0x7b430001, 0x7b440001, 0x7b450001, 1810 0x7b460001, 0x7b470001, 0x7b480001, 0x7a490001, 0x794a0001, 1811 0x784b0001, 0x774c0001, 0x764d0001, 0x754e0001, 0x744f0001, 1812 0x73500001, 0x72510001, 0x71520001, 0x70530001, 0x6f540001, 1813 0x6e550001, 0x6d560001, 0x6c570001, 0x6b580001, 0x6a590001, 1814 0x695a0001, 0x685b0001, 0x675c0001, 0x665d0001, 0x655e0001, 1815 0x645f0001, 0x63600001, 0x62610001, 0x61620001, 0x60630001, 1816 0x46640001, 0x45650001, 0x44660001, 0x43670001, 0x42680001, 1817 0x41690001, 0x406a0001, 0x266b0001, 0x256c0001, 0x246d0001, 1818 0x236e0001, 0x226f0001, 0x21700001, 0x20710001, 0x06720001, 1819 0x05730001, 0x04740001, 0x03750001, 0x02760001, 0x01770001, 1820 0x00780001, 0x00790001, 0x007a0001, 0x007b0001, 0x007c0001, 1821 0x007d0001, 0x007e0001, 0x007f0001, 0x3800001e, 0x3801001e, 1822 0x3802001e, 0x3803001e, 0x3804001e, 0x3805001e, 0x3806001e, 1823 0x3807001e, 0x3808001e, 0x3c09001e, 0x3e0a001e, 0x400b001e, 1824 0x440c001e, 0x480d001e, 0x4c0e001e, 0x500f001e, 0x5210001e, 1825 0x5611001e, 0x5a12001e, 0x5e13001e, 0x6014001e, 0x6015001e, 1826 0x6016001e, 0x6217001e, 0x6218001e, 0x6219001e, 0x621a001e, 1827 0x621b001e, 0x621c001e, 0x621d001e, 0x621e001e, 0x621f001e 1828}; 1829 1830static const struct urtwn_bb_prog rtl8188ru_bb_prog = { 1831 nitems(rtl8188ru_bb_regs), 1832 rtl8188ru_bb_regs, 1833 rtl8188ru_bb_vals, 1834 nitems(rtl8188ru_agc_vals), 1835 rtl8188ru_agc_vals 1836}; 1837 1838/* 1839 * RF initialization values. 1840 / 1841struct urtwn_rf_prog { 1842* int count; 1843 const uint8_t regs; 1844* const uint32_t vals; 1845}; 1846* 1847/* 1848 * RTL8192CU and RTL8192CE-VAU. 1849 / 1850static const uint8_t rtl8192ce_rf1_regs[] = { 1851* 0x00, 0x01, 0x02, 0x03, 0x04, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 1852 0x0f, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f, 0x20, 0x21, 0x22, 1853 0x23, 0x24, 0x25, 0x26, 0x27, 0x28, 0x29, 0x2a, 0x2b, 0x2a, 0x2b, 1854 0x2a, 0x2b, 0x2b, 0x2c, 0x2a, 0x2b, 0x2b, 0x2c, 0x2a, 0x2b, 0x2b, 1855 0x2c, 0x2a, 0x2b, 0x2b, 0x2c, 0x2a, 0x2b, 0x2b, 0x2c, 0x2a, 0x2b, 1856 0x2b, 0x2c, 0x2a, 0x2b, 0x2b, 0x2c, 0x2a, 0x2b, 0x2b, 0x2c, 0x2a, 1857 0x2b, 0x2b, 0x2c, 0x2a, 0x2b, 0x2b, 0x2c, 0x2a, 0x2b, 0x2b, 0x2c, 1858 0x2a, 0x2b, 0x2b, 0x2c, 0x2a, 0x2b, 0x2b, 0x2c, 0x2a, 0x2b, 0x2b, 1859 0x2c, 0x2a, 0x10, 0x11, 0x10, 0x11, 0x10, 0x11, 0x10, 0x11, 0x10, 1860 0x11, 0x10, 0x11, 0x10, 0x11, 0x12, 0x12, 0x12, 0x12, 0x13, 0x13, 1861 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x14, 0x14, 1862 0x14, 0x14, 0x15, 0x15, 0x15, 0x15, 0x16, 0x16, 0x16, 0x16, 0x00, 1863 0x18, 0xfe, 0xfe, 0x1f, 0xfe, 0xfe, 0x1e, 0x1f, 0x00 1864}; 1865 1866static const uint32_t rtl8192ce_rf1_vals[] = { 1867 0x30159, 0x31284, 0x98000, 0x18c63, 0x210e7, 0x2044f, 0x1adb1, 1868 0x54867, 0x8992e, 0x0e52c, 0x39ce7, 0x00451, 0x00000, 0x10255, 1869 0x60a00, 0xfc378, 0xa1250, 0x4445f, 0x80001, 0x0b614, 0x6c000, 1870 0x00000, 0x01558, 0x00060, 0x00483, 0x4f000, 0xec7d9, 0x577c0, 1871 0x04783, 0x00001, 0x21334, 0x00000, 0x00054, 0x00001, 0x00808, 1872 0x53333, 0x0000c, 0x00002, 0x00808, 0x5b333, 0x0000d, 0x00003, 1873 0x00808, 0x63333, 0x0000d, 0x00004, 0x00808, 0x6b333, 0x0000d, 1874 0x00005, 0x00808, 0x73333, 0x0000d, 0x00006, 0x00709, 0x5b333, 1875 0x0000d, 0x00007, 0x00709, 0x63333, 0x0000d, 0x00008, 0x0060a, 1876 0x4b333, 0x0000d, 0x00009, 0x0060a, 0x53333, 0x0000d, 0x0000a, 1877 0x0060a, 0x5b333, 0x0000d, 0x0000b, 0x0060a, 0x63333, 0x0000d, 1878 0x0000c, 0x0060a, 0x6b333, 0x0000d, 0x0000d, 0x0060a, 0x73333, 1879 0x0000d, 0x0000e, 0x0050b, 0x66666, 0x0001a, 0xe0000, 0x4000f, 1880 0xe31fc, 0x6000f, 0xff9f8, 0x2000f, 0x203f9, 0x3000f, 0xff500, 1881 0x00000, 0x00000, 0x8000f, 0x3f100, 0x9000f, 0x23100, 0x32000, 1882 0x71000, 0xb0000, 0xfc000, 0x287af, 0x244b7, 0x204ab, 0x1c49f, 1883 0x18493, 0x14297, 0x10295, 0x0c298, 0x0819c, 0x040a8, 0x0001c, 1884 0x1944c, 0x59444, 0x9944c, 0xd9444, 0x0f424, 0x4f424, 0x8f424, 1885 0xcf424, 0xe0330, 0xa0330, 0x60330, 0x20330, 0x10159, 0x0f401, 1886 0x00000, 0x00000, 0x80003, 0x00000, 0x00000, 0x44457, 0x80000, 1887 0x30159 1888}; 1889 1890static const uint8_t rtl8192ce_rf2_regs[] = { 1891 0x00, 0x01, 0x02, 0x03, 0x04, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 1892 0x0f, 0x12, 0x12, 0x12, 0x12, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 1893 0x13, 0x13, 0x13, 0x13, 0x13, 0x14, 0x14, 0x14, 0x14, 0x15, 0x15, 1894 0x15, 0x15, 0x16, 0x16, 0x16, 0x16 1895}; 1896 1897static const uint32_t rtl8192ce_rf2_vals[] = { 1898 0x30159, 0x31284, 0x98000, 0x18c63, 0x210e7, 0x2044f, 0x1adb1, 1899 0x54867, 0x8992e, 0x0e52c, 0x39ce7, 0x00451, 0x32000, 0x71000, 1900 0xb0000, 0xfc000, 0x287af, 0x244b7, 0x204ab, 0x1c49f, 0x18493, 1901 0x14297, 0x10295, 0x0c298, 0x0819c, 0x040a8, 0x0001c, 0x1944c, 1902 0x59444, 0x9944c, 0xd9444, 0x0f424, 0x4f424, 0x8f424, 0xcf424, 1903 0xe0330, 0xa0330, 0x60330, 0x20330 1904}; 1905 1906static const struct urtwn_rf_prog rtl8192ce_rf_prog[] = { 1907 { 1908 nitems(rtl8192ce_rf1_regs), 1909 rtl8192ce_rf1_regs, 1910 rtl8192ce_rf1_vals 1911 }, 1912 { 1913 nitems(rtl8192ce_rf2_regs), 1914 rtl8192ce_rf2_regs, 1915 rtl8192ce_rf2_vals 1916 } 1917}; 1918 1919/* 1920 * RTL8188CE-VAU. 1921 / 1922static const uint32_t rtl8188ce_rf_vals[] = { 1923* 0x30159, 0x31284, 0x98000, 0x18c63, 0x210e7, 0x2044f, 0x1adb1, 1924 0x54867, 0x8992e, 0x0e52c, 0x39ce7, 0x00451, 0x00000, 0x10255, 1925 0x60a00, 0xfc378, 0xa1250, 0x4445f, 0x80001, 0x0b614, 0x6c000, 1926 0x00000, 0x01558, 0x00060, 0x00483, 0x4f200, 0xec7d9, 0x577c0, 1927 0x04783, 0x00001, 0x21334, 0x00000, 0x00054, 0x00001, 0x00808, 1928 0x53333, 0x0000c, 0x00002, 0x00808, 0x5b333, 0x0000d, 0x00003, 1929 0x00808, 0x63333, 0x0000d, 0x00004, 0x00808, 0x6b333, 0x0000d, 1930 0x00005, 0x00808, 0x73333, 0x0000d, 0x00006, 0x00709, 0x5b333, 1931 0x0000d, 0x00007, 0x00709, 0x63333, 0x0000d, 0x00008, 0x0060a, 1932 0x4b333, 0x0000d, 0x00009, 0x0060a, 0x53333, 0x0000d, 0x0000a, 1933 0x0060a, 0x5b333, 0x0000d, 0x0000b, 0x0060a, 0x63333, 0x0000d, 1934 0x0000c, 0x0060a, 0x6b333, 0x0000d, 0x0000d, 0x0060a, 0x73333, 1935 0x0000d, 0x0000e, 0x0050b, 0x66666, 0x0001a, 0xe0000, 0x4000f, 1936 0xe31fc, 0x6000f, 0xff9f8, 0x2000f, 0x203f9, 0x3000f, 0xff500, 1937 0x00000, 0x00000, 0x8000f, 0x3f100, 0x9000f, 0x23100, 0x32000, 1938 0x71000, 0xb0000, 0xfc000, 0x287b3, 0x244b7, 0x204ab, 0x1c49f, 1939 0x18493, 0x1429b, 0x10299, 0x0c29c, 0x081a0, 0x040ac, 0x00020, 1940 0x1944c, 0x59444, 0x9944c, 0xd9444, 0x0f424, 0x4f424, 0x8f424, 1941 0xcf424, 0xe0330, 0xa0330, 0x60330, 0x20330, 0x10159, 0x0f401, 1942 0x00000, 0x00000, 0x80003, 0x00000, 0x00000, 0x44457, 0x80000, 1943 0x30159 1944}; 1945 1946static const struct urtwn_rf_prog rtl8188ce_rf_prog[] = { 1947 { 1948 nitems(rtl8192ce_rf1_regs), 1949 rtl8192ce_rf1_regs, 1950 rtl8188ce_rf_vals 1951 } 1952}; 1953 1954 1955/* 1956 * RTL8188CU. 1957 / 1958static const uint32_t rtl8188cu_rf_vals[] = { 1959* 0x30159, 0x31284, 0x98000, 0x18c63, 0x210e7, 0x2044f, 0x1adb1, 1960 0x54867, 0x8992e, 0x0e52c, 0x39ce7, 0x00451, 0x00000, 0x10255, 1961 0x60a00, 0xfc378, 0xa1250, 0x4445f, 0x80001, 0x0b614, 0x6c000, 1962 0x00000, 0x01558, 0x00060, 0x00483, 0x4f000, 0xec7d9, 0x577c0, 1963 0x04783, 0x00001, 0x21334, 0x00000, 0x00054, 0x00001, 0x00808, 1964 0x53333, 0x0000c, 0x00002, 0x00808, 0x5b333, 0x0000d, 0x00003, 1965 0x00808, 0x63333, 0x0000d, 0x00004, 0x00808, 0x6b333, 0x0000d, 1966 0x00005, 0x00808, 0x73333, 0x0000d, 0x00006, 0x00709, 0x5b333, 1967 0x0000d, 0x00007, 0x00709, 0x63333, 0x0000d, 0x00008, 0x0060a, 1968 0x4b333, 0x0000d, 0x00009, 0x0060a, 0x53333, 0x0000d, 0x0000a, 1969 0x0060a, 0x5b333, 0x0000d, 0x0000b, 0x0060a, 0x63333, 0x0000d, 1970 0x0000c, 0x0060a, 0x6b333, 0x0000d, 0x0000d, 0x0060a, 0x73333, 1971 0x0000d, 0x0000e, 0x0050b, 0x66666, 0x0001a, 0xe0000, 0x4000f, 1972 0xe31fc, 0x6000f, 0xff9f8, 0x2000f, 0x203f9, 0x3000f, 0xff500, 1973 0x00000, 0x00000, 0x8000f, 0x3f100, 0x9000f, 0x23100, 0x32000, 1974 0x71000, 0xb0000, 0xfc000, 0x287b3, 0x244b7, 0x204ab, 0x1c49f, 1975 0x18493, 0x1429b, 0x10299, 0x0c29c, 0x081a0, 0x040ac, 0x00020, 1976 0x1944c, 0x59444, 0x9944c, 0xd9444, 0x0f405, 0x4f405, 0x8f405, 1977 0xcf405, 0xe0330, 0xa0330, 0x60330, 0x20330, 0x10159, 0x0f401, 1978 0x00000, 0x00000, 0x80003, 0x00000, 0x00000, 0x44457, 0x80000, 1979 0x30159 1980}; 1981 1982static const struct urtwn_rf_prog rtl8188cu_rf_prog[] = { 1983 { 1984 nitems(rtl8192ce_rf1_regs), 1985 rtl8192ce_rf1_regs, 1986 rtl8188cu_rf_vals 1987 } 1988}; 1989 1990/* 1991 * RTL8188EU. 1992 / 1993static const uint8_t rtl8188eu_rf_regs[] = { 1994* 0x00, 0x08, 0x18, 0x19, 0x1e, 0x1f, 0x2f, 0x3f, 0x42, 0x57, 1995 0x58, 0x67, 0x83, 0xb0, 0xb1, 0xb2, 0xb4, 0xb6, 0xb7, 0xb8, 1996 0xb9, 0xba, 0xbb, 0xbf, 0xc2, 0xc3, 0xc4, 0xc5, 0xc6, 0xc7, 1997 0xc8, 0xc9, 0xca, 0xdf, 0xef, 0x51, 0x52, 0x53, 0x56, 1998 0x35, 0x35, 0x35, 0x36, 0x36, 0x36, 0x36, 0xb6, 0x18, 0x5a, 1999 0x19, 0x34, 0x34, 0x34, 0x34, 0x34, 0x34, 0x34, 0x34, 0x34, 2000 0x34, 0x34, 0x00, 0x84, 0x86, 0x87, 0x8e, 0x8f, 0xef, 0x3b, 2001 0x3b, 0x3b, 0x3b, 0x3b, 0x3b, 0x3b, 0x3b, 0x3b, 0x3b, 0x3b, 2002 0x3b, 0x3b, 0x3b, 0x3b, 0x3b, 0xef, 0x00, 0x18, 0xfe, 0xfe, 2003 0x1f, 0xfe, 0xfe, 0x1e, 0x1f, 0x00 2004}; 2005 2006static const uint32_t rtl8188eu_rf_vals[] = { 2007 0x30000, 0x84000, 0x00407, 0x00012, 0x80009, 0x00880, 0x1a060, 2008 0x00000, 0x060c0, 0xd0000, 0xbe180, 0x01552, 0x00000, 0xff8fc, 2009 0x54400, 0xccc19, 0x43003, 0x4953e, 0x1c718, 0x060ff, 0x80001, 2010 0x40000, 0x00400, 0xc0000, 0x02400, 0x00009, 0x40c91, 0x99999, 2011 0x000a3, 0x88820, 0x76c06, 0x00000, 0x80000, 0x00180, 0x001a0, 2012 0x6b27d, 0x7e49d, 0x00073, 0x51ff3, 0x00086, 0x00186, 2013 0x00286, 0x01c25, 0x09c25, 0x11c25, 0x19c25, 0x48538, 0x00c07, 2014 0x4bd00, 0x739d0, 0x0adf3, 0x09df0, 0x08ded, 0x07dea, 0x06de7, 2015 0x054ee, 0x044eb, 0x034e8, 0x0246b, 0x01468, 0x0006d, 0x30159, 2016 0x68200, 0x000ce, 0x48a00, 0x65540, 0x88000, 0x020a0, 0xf02b0, 2017 0xef7b0, 0xd4fb0, 0xcf060, 0xb0090, 0xa0080, 0x90080, 0x8f780, 2018 0x722b0, 0x6f7b0, 0x54fb0, 0x4f060, 0x30090, 0x20080, 0x10080, 2019 0x0f780, 0x000a0, 0x10159, 0x0f407, 0x00000, 0x00000, 0x80003, 2020 0x00000, 0x00000, 0x00001, 0x80000, 0x33e60 2021}; 2022 2023static const struct urtwn_rf_prog rtl8188eu_rf_prog[] = { 2024 { 2025 nitems(rtl8188eu_rf_regs), 2026 rtl8188eu_rf_regs, 2027 rtl8188eu_rf_vals 2028 } 2029}; 2030 2031/* 2032 * RTL8188RU. 2033 / 2034static const uint32_t rtl8188ru_rf_vals[] = { 2035* 0x30159, 0x31284, 0x98000, 0x18c63, 0x210e7, 0x2044f, 0x1adb0, 2036 0x54867, 0x8992e, 0x0e529, 0x39ce7, 0x00451, 0x00000, 0x00255, 2037 0x60a00, 0xfc378, 0xa1250, 0x4445f, 0x80001, 0x0b614, 0x6c000, 2038 0x0083c, 0x01558, 0x00060, 0x00483, 0x4f000, 0xec7d9, 0x977c0, 2039 0x04783, 0x00001, 0x21334, 0x00000, 0x00054, 0x00001, 0x00808, 2040 0x53333, 0x0000c, 0x00002, 0x00808, 0x5b333, 0x0000d, 0x00003, 2041 0x00808, 0x63333, 0x0000d, 0x00004, 0x00808, 0x6b333, 0x0000d, 2042 0x00005, 0x00808, 0x73333, 0x0000d, 0x00006, 0x00709, 0x5b333, 2043 0x0000d, 0x00007, 0x00709, 0x63333, 0x0000d, 0x00008, 0x0060a, 2044 0x4b333, 0x0000d, 0x00009, 0x0060a, 0x53333, 0x0000d, 0x0000a, 2045 0x0060a, 0x5b333, 0x0000d, 0x0000b, 0x0060a, 0x63333, 0x0000d, 2046 0x0000c, 0x0060a, 0x6b333, 0x0000d, 0x0000d, 0x0060a, 0x73333, 2047 0x0000d, 0x0000e, 0x0050b, 0x66666, 0x0001a, 0xe0000, 0x4000f, 2048 0xe31fc, 0x6000f, 0xff9f8, 0x2000f, 0x203f9, 0x3000f, 0xff500, 2049 0x00000, 0x00000, 0x8000f, 0x3f100, 0x9000f, 0x23100, 0xd8000, 2050 0x90000, 0x51000, 0x12000, 0x28fb4, 0x24fa8, 0x207a4, 0x1c798, 2051 0x183a4, 0x14398, 0x101a4, 0x0c198, 0x080a4, 0x04098, 0x00014, 2052 0x1944c, 0x59444, 0x9944c, 0xd9444, 0x0f405, 0x4f405, 0x8f405, 2053 0xcf405, 0xe0330, 0xa0330, 0x60330, 0x20330, 0x10159, 0x0f401, 2054 0x00000, 0x00000, 0x80003, 0x00000, 0x00000, 0x44457, 0x80000, 2055 0x30159 2056}; 2057 2058static const struct urtwn_rf_prog rtl8188ru_rf_prog[] = { 2059 { 2060 nitems(rtl8192ce_rf1_regs), 2061 rtl8192ce_rf1_regs, 2062 rtl8188ru_rf_vals 2063 } 2064}; 2065 2066struct urtwn_txpwr { 2067 uint8_t pwr[3][28]; 2068}; 2069 2070struct urtwn_r88e_txpwr { 2071 uint8_t pwr[6][28]; 2072}; 2073 2074/* 2075 * Per RF chain/group/rate Tx gain values. 2076 / 2077static const struct urtwn_txpwr rtl8192cu_txagc[] = { 2078* { { /* Chain 0. / 2079* { /* Group 0. / 2080* 0x00, 0x00, 0x00, 0x00, /* CCK1~11. / 2081* 0x0c, 0x0c, 0x0c, 0x0a, 0x08, 0x06, 0x04, 0x02, /* OFDM6~54. / 2082* 0x0e, 0x0d, 0x0c, 0x0a, 0x08, 0x06, 0x04, 0x02, /* MCS0~7. / 2083* 0x0e, 0x0d, 0x0c, 0x0a, 0x08, 0x06, 0x04, 0x02 /* MCS8~15. / 2084* }, 2085 { /* Group 1. / 2086* 0x00, 0x00, 0x00, 0x00, /* CCK1~11. / 2087* 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* OFDM6~54. / 2088* 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* MCS0~7. / 2089* 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* MCS8~15. / 2090* }, 2091 { /* Group 2. / 2092* 0x00, 0x00, 0x00, 0x00, /* CCK1~11. / 2093* 0x04, 0x04, 0x04, 0x04, 0x04, 0x02, 0x02, 0x00, /* OFDM6~54. / 2094* 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* MCS0~7. / 2095* 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* MCS8~15. / 2096* } 2097 } }, 2098 { { /* Chain 1. / 2099* { /* Group 0. / 2100* 0x00, 0x00, 0x00, 0x00, /* CCK1~11. / 2101* 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* OFDM6~54. / 2102* 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* MCS0~7. / 2103* 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* MCS8~15. / 2104* }, 2105 { /* Group 1. / 2106* 0x00, 0x00, 0x00, 0x00, /* CCK1~11. / 2107* 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* OFDM6~54. / 2108* 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* MCS0~7. / 2109* 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* MCS8~15. / 2110* }, 2111 { /* Group 2. / 2112* 0x00, 0x00, 0x00, 0x00, /* CCK1~11. / 2113* 0x04, 0x04, 0x04, 0x04, 0x04, 0x02, 0x02, 0x00, /* OFDM6~54. / 2114* 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* MCS0~7. / 2115* 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* MCS8~15. / 2116* } 2117 } } 2118}; 2119 2120static const struct urtwn_txpwr rtl8188ru_txagc[] = { 2121 { { /* Chain 0. / 2122* { /* Group 0. / 2123* 0x00, 0x00, 0x00, 0x00, /* CCK1~11. / 2124* 0x08, 0x08, 0x08, 0x06, 0x06, 0x04, 0x04, 0x00, /* OFDM6~54. / 2125* 0x08, 0x06, 0x06, 0x04, 0x04, 0x02, 0x02, 0x00, /* MCS0~7. / 2126* 0x08, 0x06, 0x06, 0x04, 0x04, 0x02, 0x02, 0x00 /* MCS8~15. / 2127* }, 2128 { /* Group 1. / 2129* 0x00, 0x00, 0x00, 0x00, /* CCK1~11. / 2130* 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* OFDM6~54. / 2131* 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* MCS0~7. / 2132* 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* MCS8~15. / 2133* }, 2134 { /* Group 2. / 2135* 0x00, 0x00, 0x00, 0x00, /* CCK1~11. / 2136* 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* OFDM6~54. / 2137* 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* MCS0~7. / 2138* 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* MCS8~15. / 2139* } 2140 } } 2141}; 2142 2143static const struct urtwn_r88e_txpwr rtl8188eu_txagc[] = { 2144 { { /* Chain 0. / 2145* { /* Group 0. / 2146* 0x00, 0x00, 0x00, 0x00, /* CCK1~11. / 2147* 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* OFDM6~54. / 2148* 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* MCS0~7. / 2149* 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* MCS8~15. / 2150* }, 2151 { /* Group 1. / 2152* 0x00, 0x00, 0x00, 0x00, /* CCK1~11. / 2153* 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* OFDM6~54. / 2154* 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* MCS0~7. / 2155* 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* MCS8~15. / 2156* }, 2157 { /* Group 2. / 2158* 0x00, 0x00, 0x00, 0x00, /* CCK1~11. / 2159* 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* OFDM6~54. / 2160* 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* MCS0~7. / 2161* 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* MCS8~15. / 2162* }, 2163 { /* Group 3. / 2164* 0x00, 0x00, 0x00, 0x00, /* CCK1~11. / 2165* 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* OFDM6~54. / 2166* 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* MCS0~7. / 2167* 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* MCS8~15. / 2168* }, 2169 { /* Group 4. / 2170* 0x00, 0x00, 0x00, 0x00, /* CCK1~11. / 2171* 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* OFDM6~54. / 2172* 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* MCS0~7. / 2173* 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* MCS8~15. / 2174* }, 2175 { /* Group 5. / 2176* 0x00, 0x00, 0x00, 0x00, /* CCK1~11. / 2177* 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* OFDM6~54. / 2178* 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* MCS0~7. / 2179* 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* MCS8~15. / 2180* } 2181 } } 2182};