622 ic->ic_set_channel = urtwn_set_channel;
623 ic->ic_transmit = urtwn_transmit;
624 ic->ic_parent = urtwn_parent;
625 ic->ic_vap_create = urtwn_vap_create;
626 ic->ic_vap_delete = urtwn_vap_delete;
627 ic->ic_wme.wme_update = urtwn_wme_update;
628 ic->ic_updateslot = urtwn_update_slot;
629 ic->ic_update_promisc = urtwn_update_promisc;
630 ic->ic_update_mcast = urtwn_update_mcast;
631 if (sc->chip & URTWN_CHIP_88E) {
632 ic->ic_node_alloc = urtwn_node_alloc;
633 ic->ic_newassoc = urtwn_newassoc;
634 sc->sc_node_free = ic->ic_node_free;
635 ic->ic_node_free = urtwn_node_free;
636 }
637 ic->ic_update_chw = urtwn_update_chw;
638 ic->ic_ampdu_enable = urtwn_ampdu_enable;
639
640 ieee80211_radiotap_attach(ic, &sc->sc_txtap.wt_ihdr,
641 sizeof(sc->sc_txtap), URTWN_TX_RADIOTAP_PRESENT,
642 &sc->sc_rxtap.wr_ihdr, sizeof(sc->sc_rxtap),
643 URTWN_RX_RADIOTAP_PRESENT);
644
645 TASK_INIT(&sc->cmdq_task, 0, urtwn_cmdq_cb, sc);
646
647 urtwn_sysctlattach(sc);
648
649 if (bootverbose)
650 ieee80211_announce(ic);
651
652 return (0);
653
654detach:
655 urtwn_detach(self);
656 return (ENXIO); /* failure */
657}
658
659static void
660urtwn_sysctlattach(struct urtwn_softc *sc)
661{
662#ifdef USB_DEBUG
663 struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(sc->sc_dev);
664 struct sysctl_oid *tree = device_get_sysctl_tree(sc->sc_dev);
665
666 SYSCTL_ADD_U32(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
667 "debug", CTLFLAG_RW, &sc->sc_debug, sc->sc_debug,
668 "control debugging printfs");
669#endif
670}
671
672static int
673urtwn_detach(device_t self)
674{
675 struct urtwn_softc *sc = device_get_softc(self);
676 struct ieee80211com *ic = &sc->sc_ic;
677 unsigned int x;
678
679 /* Prevent further ioctls. */
680 URTWN_LOCK(sc);
681 sc->sc_flags |= URTWN_DETACHED;
682 URTWN_UNLOCK(sc);
683
684 urtwn_stop(sc);
685
686 callout_drain(&sc->sc_watchdog_ch);
687 callout_drain(&sc->sc_calib_to);
688
689 /* stop all USB transfers */
690 usbd_transfer_unsetup(sc->sc_xfer, URTWN_N_TRANSFER);
691
692 /* Prevent further allocations from RX/TX data lists. */
693 URTWN_LOCK(sc);
694 STAILQ_INIT(&sc->sc_tx_active);
695 STAILQ_INIT(&sc->sc_tx_inactive);
696 STAILQ_INIT(&sc->sc_tx_pending);
697
698 STAILQ_INIT(&sc->sc_rx_active);
699 STAILQ_INIT(&sc->sc_rx_inactive);
700 URTWN_UNLOCK(sc);
701
702 /* drain USB transfers */
703 for (x = 0; x != URTWN_N_TRANSFER; x++)
704 usbd_transfer_drain(sc->sc_xfer[x]);
705
706 /* Free data buffers. */
707 URTWN_LOCK(sc);
708 urtwn_free_tx_list(sc);
709 urtwn_free_rx_list(sc);
710 URTWN_UNLOCK(sc);
711
712 if (ic->ic_softc == sc) {
713 ieee80211_draintask(ic, &sc->cmdq_task);
714 ieee80211_ifdetach(ic);
715 }
716
717 URTWN_NT_LOCK_DESTROY(sc);
718 URTWN_CMDQ_LOCK_DESTROY(sc);
719 mtx_destroy(&sc->sc_mtx);
720
721 return (0);
722}
723
724static void
725urtwn_drain_mbufq(struct urtwn_softc *sc)
726{
727 struct mbuf *m;
728 struct ieee80211_node *ni;
729 URTWN_ASSERT_LOCKED(sc);
730 while ((m = mbufq_dequeue(&sc->sc_snd)) != NULL) {
731 ni = (struct ieee80211_node *)m->m_pkthdr.rcvif;
732 m->m_pkthdr.rcvif = NULL;
733 ieee80211_free_node(ni);
734 m_freem(m);
735 }
736}
737
738static usb_error_t
739urtwn_do_request(struct urtwn_softc *sc, struct usb_device_request *req,
740 void *data)
741{
742 usb_error_t err;
743 int ntries = 10;
744
745 URTWN_ASSERT_LOCKED(sc);
746
747 while (ntries--) {
748 err = usbd_do_request_flags(sc->sc_udev, &sc->sc_mtx,
749 req, data, 0, NULL, 250 /* ms */);
750 if (err == 0)
751 break;
752
753 URTWN_DPRINTF(sc, URTWN_DEBUG_USB,
754 "%s: control request failed, %s (retries left: %d)\n",
755 __func__, usbd_errstr(err), ntries);
756 usb_pause_mtx(&sc->sc_mtx, hz / 100);
757 }
758 return (err);
759}
760
761static struct ieee80211vap *
762urtwn_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit,
763 enum ieee80211_opmode opmode, int flags,
764 const uint8_t bssid[IEEE80211_ADDR_LEN],
765 const uint8_t mac[IEEE80211_ADDR_LEN])
766{
767 struct urtwn_softc *sc = ic->ic_softc;
768 struct urtwn_vap *uvp;
769 struct ieee80211vap *vap;
770
771 if (!TAILQ_EMPTY(&ic->ic_vaps)) /* only one at a time */
772 return (NULL);
773
774 uvp = malloc(sizeof(struct urtwn_vap), M_80211_VAP, M_WAITOK | M_ZERO);
775 vap = &uvp->vap;
776 /* enable s/w bmiss handling for sta mode */
777
778 if (ieee80211_vap_setup(ic, vap, name, unit, opmode,
779 flags | IEEE80211_CLONE_NOBEACONS, bssid) != 0) {
780 /* out of memory */
781 free(uvp, M_80211_VAP);
782 return (NULL);
783 }
784
785 if (opmode == IEEE80211_M_HOSTAP || opmode == IEEE80211_M_IBSS)
786 urtwn_init_beacon(sc, uvp);
787
788 /* override state transition machine */
789 uvp->newstate = vap->iv_newstate;
790 vap->iv_newstate = urtwn_newstate;
791 vap->iv_update_beacon = urtwn_update_beacon;
792 vap->iv_key_alloc = urtwn_key_alloc;
793 vap->iv_key_set = urtwn_key_set;
794 vap->iv_key_delete = urtwn_key_delete;
795
796 /* 802.11n parameters */
797 vap->iv_ampdu_density = IEEE80211_HTCAP_MPDUDENSITY_16;
798 vap->iv_ampdu_rxmax = IEEE80211_HTCAP_MAXRXAMPDU_64K;
799
800 if (opmode == IEEE80211_M_IBSS) {
801 uvp->recv_mgmt = vap->iv_recv_mgmt;
802 vap->iv_recv_mgmt = urtwn_ibss_recv_mgmt;
803 TASK_INIT(&uvp->tsf_task_adhoc, 0, urtwn_tsf_task_adhoc, vap);
804 }
805
806 if (URTWN_CHIP_HAS_RATECTL(sc))
807 ieee80211_ratectl_init(vap);
808 /* complete setup */
809 ieee80211_vap_attach(vap, ieee80211_media_change,
810 ieee80211_media_status, mac);
811 ic->ic_opmode = opmode;
812 return (vap);
813}
814
815static void
816urtwn_vap_delete(struct ieee80211vap *vap)
817{
818 struct ieee80211com *ic = vap->iv_ic;
819 struct urtwn_softc *sc = ic->ic_softc;
820 struct urtwn_vap *uvp = URTWN_VAP(vap);
821
822 if (uvp->bcn_mbuf != NULL)
823 m_freem(uvp->bcn_mbuf);
824 if (vap->iv_opmode == IEEE80211_M_IBSS)
825 ieee80211_draintask(ic, &uvp->tsf_task_adhoc);
826 if (URTWN_CHIP_HAS_RATECTL(sc))
827 ieee80211_ratectl_deinit(vap);
828 ieee80211_vap_detach(vap);
829 free(uvp, M_80211_VAP);
830}
831
832static struct mbuf *
833urtwn_rx_copy_to_mbuf(struct urtwn_softc *sc, struct r92c_rx_stat *stat,
834 int totlen)
835{
836 struct ieee80211com *ic = &sc->sc_ic;
837 struct mbuf *m;
838 uint32_t rxdw0;
839 int pktlen;
840
841 /*
842 * don't pass packets to the ieee80211 framework if the driver isn't
843 * RUNNING.
844 */
845 if (!(sc->sc_flags & URTWN_RUNNING))
846 return (NULL);
847
848 rxdw0 = le32toh(stat->rxdw0);
849 if (rxdw0 & (R92C_RXDW0_CRCERR | R92C_RXDW0_ICVERR)) {
850 /*
851 * This should not happen since we setup our Rx filter
852 * to not receive these frames.
853 */
854 URTWN_DPRINTF(sc, URTWN_DEBUG_RECV,
855 "%s: RX flags error (%s)\n", __func__,
856 rxdw0 & R92C_RXDW0_CRCERR ? "CRC" : "ICV");
857 goto fail;
858 }
859
860 pktlen = MS(rxdw0, R92C_RXDW0_PKTLEN);
861 if (pktlen < sizeof(struct ieee80211_frame_ack)) {
862 URTWN_DPRINTF(sc, URTWN_DEBUG_RECV,
863 "%s: frame is too short: %d\n", __func__, pktlen);
864 goto fail;
865 }
866
867 if (__predict_false(totlen > MCLBYTES)) {
868 /* convert to m_getjcl if this happens */
869 device_printf(sc->sc_dev, "%s: frame too long: %d (%d)\n",
870 __func__, pktlen, totlen);
871 goto fail;
872 }
873
874 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
875 if (__predict_false(m == NULL)) {
876 device_printf(sc->sc_dev, "%s: could not allocate RX mbuf\n",
877 __func__);
878 goto fail;
879 }
880
881 /* Finalize mbuf. */
882 memcpy(mtod(m, uint8_t *), (uint8_t *)stat, totlen);
883 m->m_pkthdr.len = m->m_len = totlen;
884
885 return (m);
886fail:
887 counter_u64_add(ic->ic_ierrors, 1);
888 return (NULL);
889}
890
891static struct mbuf *
892urtwn_report_intr(struct usb_xfer *xfer, struct urtwn_data *data)
893{
894 struct urtwn_softc *sc = data->sc;
895 struct ieee80211com *ic = &sc->sc_ic;
896 struct r92c_rx_stat *stat;
897 uint8_t *buf;
898 int len;
899
900 usbd_xfer_status(xfer, &len, NULL, NULL, NULL);
901
902 if (len < sizeof(*stat)) {
903 counter_u64_add(ic->ic_ierrors, 1);
904 return (NULL);
905 }
906
907 buf = data->buf;
908 stat = (struct r92c_rx_stat *)buf;
909
910 /*
911 * For 88E chips we can tie the FF flushing here;
912 * this is where we do know exactly how deep the
913 * transmit queue is.
914 *
915 * But it won't work for R92 chips, so we can't
916 * take the easy way out.
917 */
918
919 if (sc->chip & URTWN_CHIP_88E) {
920 int report_sel = MS(le32toh(stat->rxdw3), R88E_RXDW3_RPT);
921
922 switch (report_sel) {
923 case R88E_RXDW3_RPT_RX:
924 return (urtwn_rxeof(sc, buf, len));
925 case R88E_RXDW3_RPT_TX1:
926 urtwn_r88e_ratectl_tx_complete(sc, &stat[1]);
927 break;
928 default:
929 URTWN_DPRINTF(sc, URTWN_DEBUG_INTR,
930 "%s: case %d was not handled\n", __func__,
931 report_sel);
932 break;
933 }
934 } else
935 return (urtwn_rxeof(sc, buf, len));
936
937 return (NULL);
938}
939
940static struct mbuf *
941urtwn_rxeof(struct urtwn_softc *sc, uint8_t *buf, int len)
942{
943 struct r92c_rx_stat *stat;
944 struct mbuf *m, *m0 = NULL, *prevm = NULL;
945 uint32_t rxdw0;
946 int totlen, pktlen, infosz, npkts;
947
948 /* Get the number of encapsulated frames. */
949 stat = (struct r92c_rx_stat *)buf;
950 npkts = MS(le32toh(stat->rxdw2), R92C_RXDW2_PKTCNT);
951 URTWN_DPRINTF(sc, URTWN_DEBUG_RECV,
952 "%s: Rx %d frames in one chunk\n", __func__, npkts);
953
954 /* Process all of them. */
955 while (npkts-- > 0) {
956 if (len < sizeof(*stat))
957 break;
958 stat = (struct r92c_rx_stat *)buf;
959 rxdw0 = le32toh(stat->rxdw0);
960
961 pktlen = MS(rxdw0, R92C_RXDW0_PKTLEN);
962 if (pktlen == 0)
963 break;
964
965 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8;
966
967 /* Make sure everything fits in xfer. */
968 totlen = sizeof(*stat) + infosz + pktlen;
969 if (totlen > len)
970 break;
971
972 m = urtwn_rx_copy_to_mbuf(sc, stat, totlen);
973 if (m0 == NULL)
974 m0 = m;
975 if (prevm == NULL)
976 prevm = m;
977 else {
978 prevm->m_next = m;
979 prevm = m;
980 }
981
982 /* Next chunk is 128-byte aligned. */
983 totlen = (totlen + 127) & ~127;
984 buf += totlen;
985 len -= totlen;
986 }
987
988 return (m0);
989}
990
991static void
992urtwn_r88e_ratectl_tx_complete(struct urtwn_softc *sc, void *arg)
993{
994 struct r88e_tx_rpt_ccx *rpt = arg;
995 struct ieee80211vap *vap;
996 struct ieee80211_node *ni;
997 uint8_t macid;
998 int ntries;
999
1000 macid = MS(rpt->rptb1, R88E_RPTB1_MACID);
1001 ntries = MS(rpt->rptb2, R88E_RPTB2_RETRY_CNT);
1002
1003 URTWN_NT_LOCK(sc);
1004 ni = sc->node_list[macid];
1005 if (ni != NULL) {
1006 vap = ni->ni_vap;
1007 URTWN_DPRINTF(sc, URTWN_DEBUG_INTR, "%s: frame for macid %d was"
1008 "%s sent (%d retries)\n", __func__, macid,
1009 (rpt->rptb1 & R88E_RPTB1_PKT_OK) ? "" : " not",
1010 ntries);
1011
1012 if (rpt->rptb1 & R88E_RPTB1_PKT_OK) {
1013 ieee80211_ratectl_tx_complete(vap, ni,
1014 IEEE80211_RATECTL_TX_SUCCESS, &ntries, NULL);
1015 } else {
1016 ieee80211_ratectl_tx_complete(vap, ni,
1017 IEEE80211_RATECTL_TX_FAILURE, &ntries, NULL);
1018 }
1019 } else {
1020 URTWN_DPRINTF(sc, URTWN_DEBUG_INTR, "%s: macid %d, ni is NULL\n",
1021 __func__, macid);
1022 }
1023 URTWN_NT_UNLOCK(sc);
1024}
1025
1026static struct ieee80211_node *
1027urtwn_rx_frame(struct urtwn_softc *sc, struct mbuf *m, int8_t *rssi_p)
1028{
1029 struct ieee80211com *ic = &sc->sc_ic;
1030 struct ieee80211_frame_min *wh;
1031 struct r92c_rx_stat *stat;
1032 uint32_t rxdw0, rxdw3;
1033 uint8_t rate, cipher;
1034 int8_t rssi = -127;
1035 int infosz;
1036
1037 stat = mtod(m, struct r92c_rx_stat *);
1038 rxdw0 = le32toh(stat->rxdw0);
1039 rxdw3 = le32toh(stat->rxdw3);
1040
1041 rate = MS(rxdw3, R92C_RXDW3_RATE);
1042 cipher = MS(rxdw0, R92C_RXDW0_CIPHER);
1043 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8;
1044
1045 /* Get RSSI from PHY status descriptor if present. */
1046 if (infosz != 0 && (rxdw0 & R92C_RXDW0_PHYST)) {
1047 if (sc->chip & URTWN_CHIP_88E)
1048 rssi = urtwn_r88e_get_rssi(sc, rate, &stat[1]);
1049 else
1050 rssi = urtwn_get_rssi(sc, rate, &stat[1]);
1051 URTWN_DPRINTF(sc, URTWN_DEBUG_RSSI, "%s: rssi=%d\n", __func__, rssi);
1052 /* Update our average RSSI. */
1053 urtwn_update_avgrssi(sc, rate, rssi);
1054 }
1055
1056 if (ieee80211_radiotap_active(ic)) {
1057 struct urtwn_rx_radiotap_header *tap = &sc->sc_rxtap;
1058
1059 tap->wr_flags = 0;
1060
1061 urtwn_get_tsf(sc, &tap->wr_tsft);
1062 if (__predict_false(le32toh((uint32_t)tap->wr_tsft) <
1063 le32toh(stat->rxdw5))) {
1064 tap->wr_tsft = le32toh(tap->wr_tsft >> 32) - 1;
1065 tap->wr_tsft = (uint64_t)htole32(tap->wr_tsft) << 32;
1066 } else
1067 tap->wr_tsft &= 0xffffffff00000000;
1068 tap->wr_tsft += stat->rxdw5;
1069
1070 /* XXX 20/40? */
1071 /* XXX shortgi? */
1072
1073 /* Map HW rate index to 802.11 rate. */
1074 if (!(rxdw3 & R92C_RXDW3_HT)) {
1075 tap->wr_rate = ridx2rate[rate];
1076 } else if (rate >= 12) { /* MCS0~15. */
1077 /* Bit 7 set means HT MCS instead of rate. */
1078 tap->wr_rate = 0x80 | (rate - 12);
1079 }
1080
1081 /* XXX TODO: this isn't right; should use the last good RSSI */
1082 tap->wr_dbm_antsignal = rssi;
1083 tap->wr_dbm_antnoise = URTWN_NOISE_FLOOR;
1084 }
1085
1086 *rssi_p = rssi;
1087
1088 /* Drop descriptor. */
1089 m_adj(m, sizeof(*stat) + infosz);
1090 wh = mtod(m, struct ieee80211_frame_min *);
1091
1092 if ((wh->i_fc[1] & IEEE80211_FC1_PROTECTED) &&
1093 cipher != R92C_CAM_ALGO_NONE) {
1094 m->m_flags |= M_WEP;
1095 }
1096
1097 if (m->m_len >= sizeof(*wh))
1098 return (ieee80211_find_rxnode(ic, wh));
1099
1100 return (NULL);
1101}
1102
1103static void
1104urtwn_bulk_rx_callback(struct usb_xfer *xfer, usb_error_t error)
1105{
1106 struct urtwn_softc *sc = usbd_xfer_softc(xfer);
1107 struct ieee80211com *ic = &sc->sc_ic;
1108 struct ieee80211_node *ni;
1109 struct mbuf *m = NULL, *next;
1110 struct urtwn_data *data;
1111 int8_t nf, rssi;
1112
1113 URTWN_ASSERT_LOCKED(sc);
1114
1115 switch (USB_GET_STATE(xfer)) {
1116 case USB_ST_TRANSFERRED:
1117 data = STAILQ_FIRST(&sc->sc_rx_active);
1118 if (data == NULL)
1119 goto tr_setup;
1120 STAILQ_REMOVE_HEAD(&sc->sc_rx_active, next);
1121 m = urtwn_report_intr(xfer, data);
1122 STAILQ_INSERT_TAIL(&sc->sc_rx_inactive, data, next);
1123 /* FALLTHROUGH */
1124 case USB_ST_SETUP:
1125tr_setup:
1126 data = STAILQ_FIRST(&sc->sc_rx_inactive);
1127 if (data == NULL) {
1128 KASSERT(m == NULL, ("mbuf isn't NULL"));
1129 goto finish;
1130 }
1131 STAILQ_REMOVE_HEAD(&sc->sc_rx_inactive, next);
1132 STAILQ_INSERT_TAIL(&sc->sc_rx_active, data, next);
1133 usbd_xfer_set_frame_data(xfer, 0, data->buf,
1134 usbd_xfer_max_len(xfer));
1135 usbd_transfer_submit(xfer);
1136
1137 /*
1138 * To avoid LOR we should unlock our private mutex here to call
1139 * ieee80211_input() because here is at the end of a USB
1140 * callback and safe to unlock.
1141 */
1142 while (m != NULL) {
1143 next = m->m_next;
1144 m->m_next = NULL;
1145
1146 ni = urtwn_rx_frame(sc, m, &rssi);
1147
1148 /* Store a global last-good RSSI */
1149 if (rssi != -127)
1150 sc->last_rssi = rssi;
1151
1152 URTWN_UNLOCK(sc);
1153
1154 nf = URTWN_NOISE_FLOOR;
1155 if (ni != NULL) {
1156 if (rssi != -127)
1157 URTWN_NODE(ni)->last_rssi = rssi;
1158 if (ni->ni_flags & IEEE80211_NODE_HT)
1159 m->m_flags |= M_AMPDU;
1160 (void)ieee80211_input(ni, m,
1161 URTWN_NODE(ni)->last_rssi - nf, nf);
1162 ieee80211_free_node(ni);
1163 } else {
1164 /* Use last good global RSSI */
1165 (void)ieee80211_input_all(ic, m,
1166 sc->last_rssi - nf, nf);
1167 }
1168 URTWN_LOCK(sc);
1169 m = next;
1170 }
1171 break;
1172 default:
1173 /* needs it to the inactive queue due to a error. */
1174 data = STAILQ_FIRST(&sc->sc_rx_active);
1175 if (data != NULL) {
1176 STAILQ_REMOVE_HEAD(&sc->sc_rx_active, next);
1177 STAILQ_INSERT_TAIL(&sc->sc_rx_inactive, data, next);
1178 }
1179 if (error != USB_ERR_CANCELLED) {
1180 usbd_xfer_set_stall(xfer);
1181 counter_u64_add(ic->ic_ierrors, 1);
1182 goto tr_setup;
1183 }
1184 break;
1185 }
1186finish:
1187 /* Finished receive; age anything left on the FF queue by a little bump */
1188 /*
1189 * XXX TODO: just make this a callout timer schedule so we can
1190 * flush the FF staging queue if we're approaching idle.
1191 */
1192#ifdef IEEE80211_SUPPORT_SUPERG
1193 URTWN_UNLOCK(sc);
1194 ieee80211_ff_age_all(ic, 1);
1195 URTWN_LOCK(sc);
1196#endif
1197
1198 /* Kick-start more transmit in case we stalled */
1199 urtwn_start(sc);
1200}
1201
1202static void
1203urtwn_txeof(struct urtwn_softc *sc, struct urtwn_data *data, int status)
1204{
1205
1206 URTWN_ASSERT_LOCKED(sc);
1207
1208 if (data->ni != NULL) /* not a beacon frame */
1209 ieee80211_tx_complete(data->ni, data->m, status);
1210
1211 if (sc->sc_tx_n_active > 0)
1212 sc->sc_tx_n_active--;
1213
1214 data->ni = NULL;
1215 data->m = NULL;
1216
1217 sc->sc_txtimer = 0;
1218
1219 STAILQ_INSERT_TAIL(&sc->sc_tx_inactive, data, next);
1220}
1221
1222static int
1223urtwn_alloc_list(struct urtwn_softc *sc, struct urtwn_data data[],
1224 int ndata, int maxsz)
1225{
1226 int i, error;
1227
1228 for (i = 0; i < ndata; i++) {
1229 struct urtwn_data *dp = &data[i];
1230 dp->sc = sc;
1231 dp->m = NULL;
1232 dp->buf = malloc(maxsz, M_USBDEV, M_NOWAIT);
1233 if (dp->buf == NULL) {
1234 device_printf(sc->sc_dev,
1235 "could not allocate buffer\n");
1236 error = ENOMEM;
1237 goto fail;
1238 }
1239 dp->ni = NULL;
1240 }
1241
1242 return (0);
1243fail:
1244 urtwn_free_list(sc, data, ndata);
1245 return (error);
1246}
1247
1248static int
1249urtwn_alloc_rx_list(struct urtwn_softc *sc)
1250{
1251 int error, i;
1252
1253 error = urtwn_alloc_list(sc, sc->sc_rx, URTWN_RX_LIST_COUNT,
1254 URTWN_RXBUFSZ);
1255 if (error != 0)
1256 return (error);
1257
1258 STAILQ_INIT(&sc->sc_rx_active);
1259 STAILQ_INIT(&sc->sc_rx_inactive);
1260
1261 for (i = 0; i < URTWN_RX_LIST_COUNT; i++)
1262 STAILQ_INSERT_HEAD(&sc->sc_rx_inactive, &sc->sc_rx[i], next);
1263
1264 return (0);
1265}
1266
1267static int
1268urtwn_alloc_tx_list(struct urtwn_softc *sc)
1269{
1270 int error, i;
1271
1272 error = urtwn_alloc_list(sc, sc->sc_tx, URTWN_TX_LIST_COUNT,
1273 URTWN_TXBUFSZ);
1274 if (error != 0)
1275 return (error);
1276
1277 STAILQ_INIT(&sc->sc_tx_active);
1278 STAILQ_INIT(&sc->sc_tx_inactive);
1279 STAILQ_INIT(&sc->sc_tx_pending);
1280
1281 for (i = 0; i < URTWN_TX_LIST_COUNT; i++)
1282 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, &sc->sc_tx[i], next);
1283
1284 return (0);
1285}
1286
1287static void
1288urtwn_free_list(struct urtwn_softc *sc, struct urtwn_data data[], int ndata)
1289{
1290 int i;
1291
1292 for (i = 0; i < ndata; i++) {
1293 struct urtwn_data *dp = &data[i];
1294
1295 if (dp->buf != NULL) {
1296 free(dp->buf, M_USBDEV);
1297 dp->buf = NULL;
1298 }
1299 if (dp->ni != NULL) {
1300 ieee80211_free_node(dp->ni);
1301 dp->ni = NULL;
1302 }
1303 }
1304}
1305
1306static void
1307urtwn_free_rx_list(struct urtwn_softc *sc)
1308{
1309 urtwn_free_list(sc, sc->sc_rx, URTWN_RX_LIST_COUNT);
1310}
1311
1312static void
1313urtwn_free_tx_list(struct urtwn_softc *sc)
1314{
1315 urtwn_free_list(sc, sc->sc_tx, URTWN_TX_LIST_COUNT);
1316}
1317
1318static void
1319urtwn_bulk_tx_callback(struct usb_xfer *xfer, usb_error_t error)
1320{
1321 struct urtwn_softc *sc = usbd_xfer_softc(xfer);
1322#ifdef IEEE80211_SUPPORT_SUPERG
1323 struct ieee80211com *ic = &sc->sc_ic;
1324#endif
1325 struct urtwn_data *data;
1326
1327 URTWN_ASSERT_LOCKED(sc);
1328
1329 switch (USB_GET_STATE(xfer)){
1330 case USB_ST_TRANSFERRED:
1331 data = STAILQ_FIRST(&sc->sc_tx_active);
1332 if (data == NULL)
1333 goto tr_setup;
1334 STAILQ_REMOVE_HEAD(&sc->sc_tx_active, next);
1335 urtwn_txeof(sc, data, 0);
1336 /* FALLTHROUGH */
1337 case USB_ST_SETUP:
1338tr_setup:
1339 data = STAILQ_FIRST(&sc->sc_tx_pending);
1340 if (data == NULL) {
1341 URTWN_DPRINTF(sc, URTWN_DEBUG_XMIT,
1342 "%s: empty pending queue\n", __func__);
1343 sc->sc_tx_n_active = 0;
1344 goto finish;
1345 }
1346 STAILQ_REMOVE_HEAD(&sc->sc_tx_pending, next);
1347 STAILQ_INSERT_TAIL(&sc->sc_tx_active, data, next);
1348 usbd_xfer_set_frame_data(xfer, 0, data->buf, data->buflen);
1349 usbd_transfer_submit(xfer);
1350 sc->sc_tx_n_active++;
1351 break;
1352 default:
1353 data = STAILQ_FIRST(&sc->sc_tx_active);
1354 if (data == NULL)
1355 goto tr_setup;
1356 STAILQ_REMOVE_HEAD(&sc->sc_tx_active, next);
1357 urtwn_txeof(sc, data, 1);
1358 if (error != USB_ERR_CANCELLED) {
1359 usbd_xfer_set_stall(xfer);
1360 goto tr_setup;
1361 }
1362 break;
1363 }
1364finish:
1365#ifdef IEEE80211_SUPPORT_SUPERG
1366 /*
1367 * If the TX active queue drops below a certain
1368 * threshold, ensure we age fast-frames out so they're
1369 * transmitted.
1370 */
1371 if (sc->sc_tx_n_active <= 1) {
1372 /* XXX ew - net80211 should defer this for us! */
1373
1374 /*
1375 * Note: this sc_tx_n_active currently tracks
1376 * the number of pending transmit submissions
1377 * and not the actual depth of the TX frames
1378 * pending to the hardware. That means that
1379 * we're going to end up with some sub-optimal
1380 * aggregation behaviour.
1381 */
1382 /*
1383 * XXX TODO: just make this a callout timer schedule so we can
1384 * flush the FF staging queue if we're approaching idle.
1385 */
1386 URTWN_UNLOCK(sc);
1387 ieee80211_ff_flush(ic, WME_AC_VO);
1388 ieee80211_ff_flush(ic, WME_AC_VI);
1389 ieee80211_ff_flush(ic, WME_AC_BE);
1390 ieee80211_ff_flush(ic, WME_AC_BK);
1391 URTWN_LOCK(sc);
1392 }
1393#endif
1394 /* Kick-start more transmit */
1395 urtwn_start(sc);
1396}
1397
1398static struct urtwn_data *
1399_urtwn_getbuf(struct urtwn_softc *sc)
1400{
1401 struct urtwn_data *bf;
1402
1403 bf = STAILQ_FIRST(&sc->sc_tx_inactive);
1404 if (bf != NULL)
1405 STAILQ_REMOVE_HEAD(&sc->sc_tx_inactive, next);
1406 else {
1407 URTWN_DPRINTF(sc, URTWN_DEBUG_XMIT,
1408 "%s: out of xmit buffers\n", __func__);
1409 }
1410 return (bf);
1411}
1412
1413static struct urtwn_data *
1414urtwn_getbuf(struct urtwn_softc *sc)
1415{
1416 struct urtwn_data *bf;
1417
1418 URTWN_ASSERT_LOCKED(sc);
1419
1420 bf = _urtwn_getbuf(sc);
1421 if (bf == NULL) {
1422 URTWN_DPRINTF(sc, URTWN_DEBUG_XMIT, "%s: stop queue\n",
1423 __func__);
1424 }
1425 return (bf);
1426}
1427
1428static usb_error_t
1429urtwn_write_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf,
1430 int len)
1431{
1432 usb_device_request_t req;
1433
1434 req.bmRequestType = UT_WRITE_VENDOR_DEVICE;
1435 req.bRequest = R92C_REQ_REGS;
1436 USETW(req.wValue, addr);
1437 USETW(req.wIndex, 0);
1438 USETW(req.wLength, len);
1439 return (urtwn_do_request(sc, &req, buf));
1440}
1441
1442static usb_error_t
1443urtwn_write_1(struct urtwn_softc *sc, uint16_t addr, uint8_t val)
1444{
1445 return (urtwn_write_region_1(sc, addr, &val, sizeof(val)));
1446}
1447
1448static usb_error_t
1449urtwn_write_2(struct urtwn_softc *sc, uint16_t addr, uint16_t val)
1450{
1451 val = htole16(val);
1452 return (urtwn_write_region_1(sc, addr, (uint8_t *)&val, sizeof(val)));
1453}
1454
1455static usb_error_t
1456urtwn_write_4(struct urtwn_softc *sc, uint16_t addr, uint32_t val)
1457{
1458 val = htole32(val);
1459 return (urtwn_write_region_1(sc, addr, (uint8_t *)&val, sizeof(val)));
1460}
1461
1462static usb_error_t
1463urtwn_read_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf,
1464 int len)
1465{
1466 usb_device_request_t req;
1467
1468 req.bmRequestType = UT_READ_VENDOR_DEVICE;
1469 req.bRequest = R92C_REQ_REGS;
1470 USETW(req.wValue, addr);
1471 USETW(req.wIndex, 0);
1472 USETW(req.wLength, len);
1473 return (urtwn_do_request(sc, &req, buf));
1474}
1475
1476static uint8_t
1477urtwn_read_1(struct urtwn_softc *sc, uint16_t addr)
1478{
1479 uint8_t val;
1480
1481 if (urtwn_read_region_1(sc, addr, &val, 1) != 0)
1482 return (0xff);
1483 return (val);
1484}
1485
1486static uint16_t
1487urtwn_read_2(struct urtwn_softc *sc, uint16_t addr)
1488{
1489 uint16_t val;
1490
1491 if (urtwn_read_region_1(sc, addr, (uint8_t *)&val, 2) != 0)
1492 return (0xffff);
1493 return (le16toh(val));
1494}
1495
1496static uint32_t
1497urtwn_read_4(struct urtwn_softc *sc, uint16_t addr)
1498{
1499 uint32_t val;
1500
1501 if (urtwn_read_region_1(sc, addr, (uint8_t *)&val, 4) != 0)
1502 return (0xffffffff);
1503 return (le32toh(val));
1504}
1505
1506static int
1507urtwn_fw_cmd(struct urtwn_softc *sc, uint8_t id, const void *buf, int len)
1508{
1509 struct r92c_fw_cmd cmd;
1510 usb_error_t error;
1511 int ntries;
1512
1513 if (!(sc->sc_flags & URTWN_FW_LOADED)) {
1514 URTWN_DPRINTF(sc, URTWN_DEBUG_FIRMWARE, "%s: firmware "
1515 "was not loaded; command (id %d) will be discarded\n",
1516 __func__, id);
1517 return (0);
1518 }
1519
1520 /* Wait for current FW box to be empty. */
1521 for (ntries = 0; ntries < 100; ntries++) {
1522 if (!(urtwn_read_1(sc, R92C_HMETFR) & (1 << sc->fwcur)))
1523 break;
1524 urtwn_ms_delay(sc);
1525 }
1526 if (ntries == 100) {
1527 device_printf(sc->sc_dev,
1528 "could not send firmware command\n");
1529 return (ETIMEDOUT);
1530 }
1531 memset(&cmd, 0, sizeof(cmd));
1532 cmd.id = id;
1533 if (len > 3)
1534 cmd.id |= R92C_CMD_FLAG_EXT;
1535 KASSERT(len <= sizeof(cmd.msg), ("urtwn_fw_cmd\n"));
1536 memcpy(cmd.msg, buf, len);
1537
1538 /* Write the first word last since that will trigger the FW. */
1539 error = urtwn_write_region_1(sc, R92C_HMEBOX_EXT(sc->fwcur),
1540 (uint8_t *)&cmd + 4, 2);
1541 if (error != USB_ERR_NORMAL_COMPLETION)
1542 return (EIO);
1543 error = urtwn_write_region_1(sc, R92C_HMEBOX(sc->fwcur),
1544 (uint8_t *)&cmd + 0, 4);
1545 if (error != USB_ERR_NORMAL_COMPLETION)
1546 return (EIO);
1547
1548 sc->fwcur = (sc->fwcur + 1) % R92C_H2C_NBOX;
1549 return (0);
1550}
1551
1552static void
1553urtwn_cmdq_cb(void *arg, int pending)
1554{
1555 struct urtwn_softc *sc = arg;
1556 struct urtwn_cmdq *item;
1557
1558 /*
1559 * Device must be powered on (via urtwn_power_on())
1560 * before any command may be sent.
1561 */
1562 URTWN_LOCK(sc);
1563 if (!(sc->sc_flags & URTWN_RUNNING)) {
1564 URTWN_UNLOCK(sc);
1565 return;
1566 }
1567
1568 URTWN_CMDQ_LOCK(sc);
1569 while (sc->cmdq[sc->cmdq_first].func != NULL) {
1570 item = &sc->cmdq[sc->cmdq_first];
1571 sc->cmdq_first = (sc->cmdq_first + 1) % URTWN_CMDQ_SIZE;
1572 URTWN_CMDQ_UNLOCK(sc);
1573
1574 item->func(sc, &item->data);
1575
1576 URTWN_CMDQ_LOCK(sc);
1577 memset(item, 0, sizeof (*item));
1578 }
1579 URTWN_CMDQ_UNLOCK(sc);
1580 URTWN_UNLOCK(sc);
1581}
1582
1583static int
1584urtwn_cmd_sleepable(struct urtwn_softc *sc, const void *ptr, size_t len,
1585 CMD_FUNC_PROTO)
1586{
1587 struct ieee80211com *ic = &sc->sc_ic;
1588
1589 KASSERT(len <= sizeof(union sec_param), ("buffer overflow"));
1590
1591 URTWN_CMDQ_LOCK(sc);
1592 if (sc->cmdq[sc->cmdq_last].func != NULL) {
1593 device_printf(sc->sc_dev, "%s: cmdq overflow\n", __func__);
1594 URTWN_CMDQ_UNLOCK(sc);
1595
1596 return (EAGAIN);
1597 }
1598
1599 if (ptr != NULL)
1600 memcpy(&sc->cmdq[sc->cmdq_last].data, ptr, len);
1601 sc->cmdq[sc->cmdq_last].func = func;
1602 sc->cmdq_last = (sc->cmdq_last + 1) % URTWN_CMDQ_SIZE;
1603 URTWN_CMDQ_UNLOCK(sc);
1604
1605 ieee80211_runtask(ic, &sc->cmdq_task);
1606
1607 return (0);
1608}
1609
1610static __inline void
1611urtwn_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, uint32_t val)
1612{
1613
1614 sc->sc_rf_write(sc, chain, addr, val);
1615}
1616
1617static void
1618urtwn_r92c_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr,
1619 uint32_t val)
1620{
1621 urtwn_bb_write(sc, R92C_LSSI_PARAM(chain),
1622 SM(R92C_LSSI_PARAM_ADDR, addr) |
1623 SM(R92C_LSSI_PARAM_DATA, val));
1624}
1625
1626static void
1627urtwn_r88e_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr,
1628uint32_t val)
1629{
1630 urtwn_bb_write(sc, R92C_LSSI_PARAM(chain),
1631 SM(R88E_LSSI_PARAM_ADDR, addr) |
1632 SM(R92C_LSSI_PARAM_DATA, val));
1633}
1634
1635static uint32_t
1636urtwn_rf_read(struct urtwn_softc *sc, int chain, uint8_t addr)
1637{
1638 uint32_t reg[R92C_MAX_CHAINS], val;
1639
1640 reg[0] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(0));
1641 if (chain != 0)
1642 reg[chain] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(chain));
1643
1644 urtwn_bb_write(sc, R92C_HSSI_PARAM2(0),
1645 reg[0] & ~R92C_HSSI_PARAM2_READ_EDGE);
1646 urtwn_ms_delay(sc);
1647
1648 urtwn_bb_write(sc, R92C_HSSI_PARAM2(chain),
1649 RW(reg[chain], R92C_HSSI_PARAM2_READ_ADDR, addr) |
1650 R92C_HSSI_PARAM2_READ_EDGE);
1651 urtwn_ms_delay(sc);
1652
1653 urtwn_bb_write(sc, R92C_HSSI_PARAM2(0),
1654 reg[0] | R92C_HSSI_PARAM2_READ_EDGE);
1655 urtwn_ms_delay(sc);
1656
1657 if (urtwn_bb_read(sc, R92C_HSSI_PARAM1(chain)) & R92C_HSSI_PARAM1_PI)
1658 val = urtwn_bb_read(sc, R92C_HSPI_READBACK(chain));
1659 else
1660 val = urtwn_bb_read(sc, R92C_LSSI_READBACK(chain));
1661 return (MS(val, R92C_LSSI_READBACK_DATA));
1662}
1663
1664static int
1665urtwn_llt_write(struct urtwn_softc *sc, uint32_t addr, uint32_t data)
1666{
1667 usb_error_t error;
1668 int ntries;
1669
1670 error = urtwn_write_4(sc, R92C_LLT_INIT,
1671 SM(R92C_LLT_INIT_OP, R92C_LLT_INIT_OP_WRITE) |
1672 SM(R92C_LLT_INIT_ADDR, addr) |
1673 SM(R92C_LLT_INIT_DATA, data));
1674 if (error != USB_ERR_NORMAL_COMPLETION)
1675 return (EIO);
1676 /* Wait for write operation to complete. */
1677 for (ntries = 0; ntries < 20; ntries++) {
1678 if (MS(urtwn_read_4(sc, R92C_LLT_INIT), R92C_LLT_INIT_OP) ==
1679 R92C_LLT_INIT_OP_NO_ACTIVE)
1680 return (0);
1681 urtwn_ms_delay(sc);
1682 }
1683 return (ETIMEDOUT);
1684}
1685
1686static int
1687urtwn_efuse_read_next(struct urtwn_softc *sc, uint8_t *val)
1688{
1689 uint32_t reg;
1690 usb_error_t error;
1691 int ntries;
1692
1693 if (sc->last_rom_addr >= URTWN_EFUSE_MAX_LEN)
1694 return (EFAULT);
1695
1696 reg = urtwn_read_4(sc, R92C_EFUSE_CTRL);
1697 reg = RW(reg, R92C_EFUSE_CTRL_ADDR, sc->last_rom_addr);
1698 reg &= ~R92C_EFUSE_CTRL_VALID;
1699
1700 error = urtwn_write_4(sc, R92C_EFUSE_CTRL, reg);
1701 if (error != USB_ERR_NORMAL_COMPLETION)
1702 return (EIO);
1703 /* Wait for read operation to complete. */
1704 for (ntries = 0; ntries < 100; ntries++) {
1705 reg = urtwn_read_4(sc, R92C_EFUSE_CTRL);
1706 if (reg & R92C_EFUSE_CTRL_VALID)
1707 break;
1708 urtwn_ms_delay(sc);
1709 }
1710 if (ntries == 100) {
1711 device_printf(sc->sc_dev,
1712 "could not read efuse byte at address 0x%x\n",
1713 sc->last_rom_addr);
1714 return (ETIMEDOUT);
1715 }
1716
1717 *val = MS(reg, R92C_EFUSE_CTRL_DATA);
1718 sc->last_rom_addr++;
1719
1720 return (0);
1721}
1722
1723static int
1724urtwn_efuse_read_data(struct urtwn_softc *sc, uint8_t *rom, uint8_t off,
1725 uint8_t msk)
1726{
1727 uint8_t reg;
1728 int i, error;
1729
1730 for (i = 0; i < 4; i++) {
1731 if (msk & (1 << i))
1732 continue;
1733 error = urtwn_efuse_read_next(sc, ®);
1734 if (error != 0)
1735 return (error);
1736 URTWN_DPRINTF(sc, URTWN_DEBUG_ROM, "rom[0x%03X] == 0x%02X\n",
1737 off * 8 + i * 2, reg);
1738 rom[off * 8 + i * 2 + 0] = reg;
1739
1740 error = urtwn_efuse_read_next(sc, ®);
1741 if (error != 0)
1742 return (error);
1743 URTWN_DPRINTF(sc, URTWN_DEBUG_ROM, "rom[0x%03X] == 0x%02X\n",
1744 off * 8 + i * 2 + 1, reg);
1745 rom[off * 8 + i * 2 + 1] = reg;
1746 }
1747
1748 return (0);
1749}
1750
1751#ifdef USB_DEBUG
1752static void
1753urtwn_dump_rom_contents(struct urtwn_softc *sc, uint8_t *rom, uint16_t size)
1754{
1755 int i;
1756
1757 /* Dump ROM contents. */
1758 device_printf(sc->sc_dev, "%s:", __func__);
1759 for (i = 0; i < size; i++) {
1760 if (i % 32 == 0)
1761 printf("\n%03X: ", i);
1762 else if (i % 4 == 0)
1763 printf(" ");
1764
1765 printf("%02X", rom[i]);
1766 }
1767 printf("\n");
1768}
1769#endif
1770
1771static int
1772urtwn_efuse_read(struct urtwn_softc *sc, uint8_t *rom, uint16_t size)
1773{
1774#define URTWN_CHK(res) do { \
1775 if ((error = res) != 0) \
1776 goto end; \
1777} while(0)
1778 uint8_t msk, off, reg;
1779 int error;
1780
1781 URTWN_CHK(urtwn_efuse_switch_power(sc));
1782
1783 /* Read full ROM image. */
1784 sc->last_rom_addr = 0;
1785 memset(rom, 0xff, size);
1786
1787 URTWN_CHK(urtwn_efuse_read_next(sc, ®));
1788 while (reg != 0xff) {
1789 /* check for extended header */
1790 if ((sc->chip & URTWN_CHIP_88E) && (reg & 0x1f) == 0x0f) {
1791 off = reg >> 5;
1792 URTWN_CHK(urtwn_efuse_read_next(sc, ®));
1793
1794 if ((reg & 0x0f) != 0x0f)
1795 off = ((reg & 0xf0) >> 1) | off;
1796 else
1797 continue;
1798 } else
1799 off = reg >> 4;
1800 msk = reg & 0xf;
1801
1802 URTWN_CHK(urtwn_efuse_read_data(sc, rom, off, msk));
1803 URTWN_CHK(urtwn_efuse_read_next(sc, ®));
1804 }
1805
1806end:
1807
1808#ifdef USB_DEBUG
1809 if (sc->sc_debug & URTWN_DEBUG_ROM)
1810 urtwn_dump_rom_contents(sc, rom, size);
1811#endif
1812
1813 urtwn_write_1(sc, R92C_EFUSE_ACCESS, R92C_EFUSE_ACCESS_OFF);
1814
1815 if (error != 0) {
1816 device_printf(sc->sc_dev, "%s: error while reading ROM\n",
1817 __func__);
1818 }
1819
1820 return (error);
1821#undef URTWN_CHK
1822}
1823
1824static int
1825urtwn_efuse_switch_power(struct urtwn_softc *sc)
1826{
1827 usb_error_t error;
1828 uint32_t reg;
1829
1830 error = urtwn_write_1(sc, R92C_EFUSE_ACCESS, R92C_EFUSE_ACCESS_ON);
1831 if (error != USB_ERR_NORMAL_COMPLETION)
1832 return (EIO);
1833
1834 reg = urtwn_read_2(sc, R92C_SYS_ISO_CTRL);
1835 if (!(reg & R92C_SYS_ISO_CTRL_PWC_EV12V)) {
1836 error = urtwn_write_2(sc, R92C_SYS_ISO_CTRL,
1837 reg | R92C_SYS_ISO_CTRL_PWC_EV12V);
1838 if (error != USB_ERR_NORMAL_COMPLETION)
1839 return (EIO);
1840 }
1841 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN);
1842 if (!(reg & R92C_SYS_FUNC_EN_ELDR)) {
1843 error = urtwn_write_2(sc, R92C_SYS_FUNC_EN,
1844 reg | R92C_SYS_FUNC_EN_ELDR);
1845 if (error != USB_ERR_NORMAL_COMPLETION)
1846 return (EIO);
1847 }
1848 reg = urtwn_read_2(sc, R92C_SYS_CLKR);
1849 if ((reg & (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) !=
1850 (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) {
1851 error = urtwn_write_2(sc, R92C_SYS_CLKR,
1852 reg | R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M);
1853 if (error != USB_ERR_NORMAL_COMPLETION)
1854 return (EIO);
1855 }
1856
1857 return (0);
1858}
1859
1860static int
1861urtwn_read_chipid(struct urtwn_softc *sc)
1862{
1863 uint32_t reg;
1864
1865 if (sc->chip & URTWN_CHIP_88E)
1866 return (0);
1867
1868 reg = urtwn_read_4(sc, R92C_SYS_CFG);
1869 if (reg & R92C_SYS_CFG_TRP_VAUX_EN)
1870 return (EIO);
1871
1872 if (reg & R92C_SYS_CFG_TYPE_92C) {
1873 sc->chip |= URTWN_CHIP_92C;
1874 /* Check if it is a castrated 8192C. */
1875 if (MS(urtwn_read_4(sc, R92C_HPON_FSM),
1876 R92C_HPON_FSM_CHIP_BONDING_ID) ==
1877 R92C_HPON_FSM_CHIP_BONDING_ID_92C_1T2R)
1878 sc->chip |= URTWN_CHIP_92C_1T2R;
1879 }
1880 if (reg & R92C_SYS_CFG_VENDOR_UMC) {
1881 sc->chip |= URTWN_CHIP_UMC;
1882 if (MS(reg, R92C_SYS_CFG_CHIP_VER_RTL) == 0)
1883 sc->chip |= URTWN_CHIP_UMC_A_CUT;
1884 }
1885 return (0);
1886}
1887
1888static int
1889urtwn_read_rom(struct urtwn_softc *sc)
1890{
1891 struct r92c_rom *rom = &sc->rom.r92c_rom;
1892 int error;
1893
1894 /* Read full ROM image. */
1895 error = urtwn_efuse_read(sc, (uint8_t *)rom, sizeof(*rom));
1896 if (error != 0)
1897 return (error);
1898
1899 /* XXX Weird but this is what the vendor driver does. */
1900 sc->last_rom_addr = 0x1fa;
1901 error = urtwn_efuse_read_next(sc, &sc->pa_setting);
1902 if (error != 0)
1903 return (error);
1904 URTWN_DPRINTF(sc, URTWN_DEBUG_ROM, "%s: PA setting=0x%x\n", __func__,
1905 sc->pa_setting);
1906
1907 sc->board_type = MS(rom->rf_opt1, R92C_ROM_RF1_BOARD_TYPE);
1908
1909 sc->regulatory = MS(rom->rf_opt1, R92C_ROM_RF1_REGULATORY);
1910 URTWN_DPRINTF(sc, URTWN_DEBUG_ROM, "%s: regulatory type=%d\n",
1911 __func__, sc->regulatory);
1912 IEEE80211_ADDR_COPY(sc->sc_ic.ic_macaddr, rom->macaddr);
1913
1914 sc->sc_rf_write = urtwn_r92c_rf_write;
1915 sc->sc_power_on = urtwn_r92c_power_on;
1916 sc->sc_power_off = urtwn_r92c_power_off;
1917
1918 return (0);
1919}
1920
1921static int
1922urtwn_r88e_read_rom(struct urtwn_softc *sc)
1923{
1924 struct r88e_rom *rom = &sc->rom.r88e_rom;
1925 int error;
1926
1927 error = urtwn_efuse_read(sc, (uint8_t *)rom, sizeof(sc->rom.r88e_rom));
1928 if (error != 0)
1929 return (error);
1930
1931 sc->bw20_tx_pwr_diff = (rom->tx_pwr_diff >> 4);
1932 if (sc->bw20_tx_pwr_diff & 0x08)
1933 sc->bw20_tx_pwr_diff |= 0xf0;
1934 sc->ofdm_tx_pwr_diff = (rom->tx_pwr_diff & 0xf);
1935 if (sc->ofdm_tx_pwr_diff & 0x08)
1936 sc->ofdm_tx_pwr_diff |= 0xf0;
1937 sc->regulatory = MS(rom->rf_board_opt, R92C_ROM_RF1_REGULATORY);
1938 URTWN_DPRINTF(sc, URTWN_DEBUG_ROM, "%s: regulatory type %d\n",
1939 __func__,sc->regulatory);
1940 IEEE80211_ADDR_COPY(sc->sc_ic.ic_macaddr, rom->macaddr);
1941
1942 sc->sc_rf_write = urtwn_r88e_rf_write;
1943 sc->sc_power_on = urtwn_r88e_power_on;
1944 sc->sc_power_off = urtwn_r88e_power_off;
1945
1946 return (0);
1947}
1948
1949static __inline uint8_t
1950rate2ridx(uint8_t rate)
1951{
1952 if (rate & IEEE80211_RATE_MCS) {
1953 /* 11n rates start at idx 12 */
1954 return ((rate & 0xf) + 12);
1955 }
1956 switch (rate) {
1957 /* 11g */
1958 case 12: return 4;
1959 case 18: return 5;
1960 case 24: return 6;
1961 case 36: return 7;
1962 case 48: return 8;
1963 case 72: return 9;
1964 case 96: return 10;
1965 case 108: return 11;
1966 /* 11b */
1967 case 2: return 0;
1968 case 4: return 1;
1969 case 11: return 2;
1970 case 22: return 3;
1971 default: return URTWN_RIDX_UNKNOWN;
1972 }
1973}
1974
1975/*
1976 * Initialize rate adaptation in firmware.
1977 */
1978static int
1979urtwn_ra_init(struct urtwn_softc *sc)
1980{
1981 struct ieee80211com *ic = &sc->sc_ic;
1982 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps);
1983 struct ieee80211_node *ni;
1984 struct ieee80211_rateset *rs, *rs_ht;
1985 struct r92c_fw_cmd_macid_cfg cmd;
1986 uint32_t rates, basicrates;
1987 uint8_t mode, ridx;
1988 int maxrate, maxbasicrate, error, i;
1989
1990 ni = ieee80211_ref_node(vap->iv_bss);
1991 rs = &ni->ni_rates;
1992 rs_ht = (struct ieee80211_rateset *) &ni->ni_htrates;
1993
1994 /* Get normal and basic rates mask. */
1995 rates = basicrates = 0;
1996 maxrate = maxbasicrate = 0;
1997
1998 /* This is for 11bg */
1999 for (i = 0; i < rs->rs_nrates; i++) {
2000 /* Convert 802.11 rate to HW rate index. */
2001 ridx = rate2ridx(IEEE80211_RV(rs->rs_rates[i]));
2002 if (ridx == URTWN_RIDX_UNKNOWN) /* Unknown rate, skip. */
2003 continue;
2004 rates |= 1 << ridx;
2005 if (ridx > maxrate)
2006 maxrate = ridx;
2007 if (rs->rs_rates[i] & IEEE80211_RATE_BASIC) {
2008 basicrates |= 1 << ridx;
2009 if (ridx > maxbasicrate)
2010 maxbasicrate = ridx;
2011 }
2012 }
2013
2014 /* If we're doing 11n, enable 11n rates */
2015 if (ni->ni_flags & IEEE80211_NODE_HT) {
2016 for (i = 0; i < rs_ht->rs_nrates; i++) {
2017 if ((rs_ht->rs_rates[i] & 0x7f) > 0xf)
2018 continue;
2019 /* 11n rates start at index 12 */
2020 ridx = ((rs_ht->rs_rates[i]) & 0xf) + 12;
2021 rates |= (1 << ridx);
2022
2023 /* Guard against the rate table being oddly ordered */
2024 if (ridx > maxrate)
2025 maxrate = ridx;
2026 }
2027 }
2028
2029#if 0
2030 if (ic->ic_curmode == IEEE80211_MODE_11NG)
2031 raid = R92C_RAID_11GN;
2032#endif
2033 /* NB: group addressed frames are done at 11bg rates for now */
2034 if (ic->ic_curmode == IEEE80211_MODE_11B)
2035 mode = R92C_RAID_11B;
2036 else
2037 mode = R92C_RAID_11BG;
2038 /* XXX misleading 'mode' value here for unicast frames */
2039 URTWN_DPRINTF(sc, URTWN_DEBUG_RA,
2040 "%s: mode 0x%x, rates 0x%08x, basicrates 0x%08x\n", __func__,
2041 mode, rates, basicrates);
2042
2043 /* Set rates mask for group addressed frames. */
2044 cmd.macid = URTWN_MACID_BC | URTWN_MACID_VALID;
2045 cmd.mask = htole32(mode << 28 | basicrates);
2046 error = urtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd));
2047 if (error != 0) {
2048 ieee80211_free_node(ni);
2049 device_printf(sc->sc_dev,
2050 "could not add broadcast station\n");
2051 return (error);
2052 }
2053
2054 /* Set initial MRR rate. */
2055 URTWN_DPRINTF(sc, URTWN_DEBUG_RA, "%s: maxbasicrate %d\n", __func__,
2056 maxbasicrate);
2057 urtwn_write_1(sc, R92C_INIDATA_RATE_SEL(URTWN_MACID_BC),
2058 maxbasicrate);
2059
2060 /* Set rates mask for unicast frames. */
2061 if (ni->ni_flags & IEEE80211_NODE_HT)
2062 mode = R92C_RAID_11GN;
2063 else if (ic->ic_curmode == IEEE80211_MODE_11B)
2064 mode = R92C_RAID_11B;
2065 else
2066 mode = R92C_RAID_11BG;
2067 cmd.macid = URTWN_MACID_BSS | URTWN_MACID_VALID;
2068 cmd.mask = htole32(mode << 28 | rates);
2069 error = urtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd));
2070 if (error != 0) {
2071 ieee80211_free_node(ni);
2072 device_printf(sc->sc_dev, "could not add BSS station\n");
2073 return (error);
2074 }
2075 /* Set initial MRR rate. */
2076 URTWN_DPRINTF(sc, URTWN_DEBUG_RA, "%s: maxrate %d\n", __func__,
2077 maxrate);
2078 urtwn_write_1(sc, R92C_INIDATA_RATE_SEL(URTWN_MACID_BSS),
2079 maxrate);
2080
2081 /* Indicate highest supported rate. */
2082 if (ni->ni_flags & IEEE80211_NODE_HT)
2083 ni->ni_txrate = rs_ht->rs_rates[rs_ht->rs_nrates - 1]
2084 | IEEE80211_RATE_MCS;
2085 else
2086 ni->ni_txrate = rs->rs_rates[rs->rs_nrates - 1];
2087 ieee80211_free_node(ni);
2088
2089 return (0);
2090}
2091
2092static void
2093urtwn_init_beacon(struct urtwn_softc *sc, struct urtwn_vap *uvp)
2094{
2095 struct r92c_tx_desc *txd = &uvp->bcn_desc;
2096
2097 txd->txdw0 = htole32(
2098 SM(R92C_TXDW0_OFFSET, sizeof(*txd)) | R92C_TXDW0_BMCAST |
2099 R92C_TXDW0_OWN | R92C_TXDW0_FSG | R92C_TXDW0_LSG);
2100 txd->txdw1 = htole32(
2101 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_BEACON) |
2102 SM(R92C_TXDW1_RAID, R92C_RAID_11B));
2103
2104 if (sc->chip & URTWN_CHIP_88E) {
2105 txd->txdw1 |= htole32(SM(R88E_TXDW1_MACID, URTWN_MACID_BC));
2106 txd->txdseq |= htole16(R88E_TXDSEQ_HWSEQ_EN);
2107 } else {
2108 txd->txdw1 |= htole32(SM(R92C_TXDW1_MACID, URTWN_MACID_BC));
2109 txd->txdw4 |= htole32(R92C_TXDW4_HWSEQ_EN);
2110 }
2111
2112 txd->txdw4 = htole32(R92C_TXDW4_DRVRATE);
2113 txd->txdw5 = htole32(SM(R92C_TXDW5_DATARATE, URTWN_RIDX_CCK1));
2114}
2115
2116static int
2117urtwn_setup_beacon(struct urtwn_softc *sc, struct ieee80211_node *ni)
2118{
2119 struct ieee80211vap *vap = ni->ni_vap;
2120 struct urtwn_vap *uvp = URTWN_VAP(vap);
2121 struct mbuf *m;
2122 int error;
2123
2124 URTWN_ASSERT_LOCKED(sc);
2125
2126 if (ni->ni_chan == IEEE80211_CHAN_ANYC)
2127 return (EINVAL);
2128
2129 m = ieee80211_beacon_alloc(ni);
2130 if (m == NULL) {
2131 device_printf(sc->sc_dev,
2132 "%s: could not allocate beacon frame\n", __func__);
2133 return (ENOMEM);
2134 }
2135
2136 if (uvp->bcn_mbuf != NULL)
2137 m_freem(uvp->bcn_mbuf);
2138
2139 uvp->bcn_mbuf = m;
2140
2141 if ((error = urtwn_tx_beacon(sc, uvp)) != 0)
2142 return (error);
2143
2144 /* XXX bcnq stuck workaround */
2145 if ((error = urtwn_tx_beacon(sc, uvp)) != 0)
2146 return (error);
2147
2148 URTWN_DPRINTF(sc, URTWN_DEBUG_BEACON, "%s: beacon was %srecognized\n",
2149 __func__, urtwn_read_1(sc, R92C_TDECTRL + 2) &
2150 (R92C_TDECTRL_BCN_VALID >> 16) ? "" : "not ");
2151
2152 return (0);
2153}
2154
2155static void
2156urtwn_update_beacon(struct ieee80211vap *vap, int item)
2157{
2158 struct urtwn_softc *sc = vap->iv_ic->ic_softc;
2159 struct urtwn_vap *uvp = URTWN_VAP(vap);
2160 struct ieee80211_beacon_offsets *bo = &vap->iv_bcn_off;
2161 struct ieee80211_node *ni = vap->iv_bss;
2162 int mcast = 0;
2163
2164 URTWN_LOCK(sc);
2165 if (uvp->bcn_mbuf == NULL) {
2166 uvp->bcn_mbuf = ieee80211_beacon_alloc(ni);
2167 if (uvp->bcn_mbuf == NULL) {
2168 device_printf(sc->sc_dev,
2169 "%s: could not allocate beacon frame\n", __func__);
2170 URTWN_UNLOCK(sc);
2171 return;
2172 }
2173 }
2174 URTWN_UNLOCK(sc);
2175
2176 if (item == IEEE80211_BEACON_TIM)
2177 mcast = 1; /* XXX */
2178
2179 setbit(bo->bo_flags, item);
2180 ieee80211_beacon_update(ni, uvp->bcn_mbuf, mcast);
2181
2182 URTWN_LOCK(sc);
2183 urtwn_tx_beacon(sc, uvp);
2184 URTWN_UNLOCK(sc);
2185}
2186
2187/*
2188 * Push a beacon frame into the chip. Beacon will
2189 * be repeated by the chip every R92C_BCN_INTERVAL.
2190 */
2191static int
2192urtwn_tx_beacon(struct urtwn_softc *sc, struct urtwn_vap *uvp)
2193{
2194 struct r92c_tx_desc *desc = &uvp->bcn_desc;
2195 struct urtwn_data *bf;
2196
2197 URTWN_ASSERT_LOCKED(sc);
2198
2199 bf = urtwn_getbuf(sc);
2200 if (bf == NULL)
2201 return (ENOMEM);
2202
2203 memcpy(bf->buf, desc, sizeof(*desc));
2204 urtwn_tx_start(sc, uvp->bcn_mbuf, IEEE80211_FC0_TYPE_MGT, bf);
2205
2206 sc->sc_txtimer = 5;
2207 callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc);
2208
2209 return (0);
2210}
2211
2212static int
2213urtwn_key_alloc(struct ieee80211vap *vap, struct ieee80211_key *k,
2214 ieee80211_keyix *keyix, ieee80211_keyix *rxkeyix)
2215{
2216 struct urtwn_softc *sc = vap->iv_ic->ic_softc;
2217 uint8_t i;
2218
2219 if (!(&vap->iv_nw_keys[0] <= k &&
2220 k < &vap->iv_nw_keys[IEEE80211_WEP_NKID])) {
2221 if (!(k->wk_flags & IEEE80211_KEY_SWCRYPT)) {
2222 URTWN_LOCK(sc);
2223 /*
2224 * First 4 slots for group keys,
2225 * what is left - for pairwise.
2226 * XXX incompatible with IBSS RSN.
2227 */
2228 for (i = IEEE80211_WEP_NKID;
2229 i < R92C_CAM_ENTRY_COUNT; i++) {
2230 if ((sc->keys_bmap & (1 << i)) == 0) {
2231 sc->keys_bmap |= 1 << i;
2232 *keyix = i;
2233 break;
2234 }
2235 }
2236 URTWN_UNLOCK(sc);
2237 if (i == R92C_CAM_ENTRY_COUNT) {
2238 device_printf(sc->sc_dev,
2239 "%s: no free space in the key table\n",
2240 __func__);
2241 return 0;
2242 }
2243 } else
2244 *keyix = 0;
2245 } else {
2246 *keyix = k - vap->iv_nw_keys;
2247 }
2248 *rxkeyix = *keyix;
2249 return 1;
2250}
2251
2252static void
2253urtwn_key_set_cb(struct urtwn_softc *sc, union sec_param *data)
2254{
2255 struct ieee80211_key *k = &data->key;
2256 uint8_t algo, keyid;
2257 int i, error;
2258
2259 if (k->wk_keyix < IEEE80211_WEP_NKID)
2260 keyid = k->wk_keyix;
2261 else
2262 keyid = 0;
2263
2264 /* Map net80211 cipher to HW crypto algorithm. */
2265 switch (k->wk_cipher->ic_cipher) {
2266 case IEEE80211_CIPHER_WEP:
2267 if (k->wk_keylen < 8)
2268 algo = R92C_CAM_ALGO_WEP40;
2269 else
2270 algo = R92C_CAM_ALGO_WEP104;
2271 break;
2272 case IEEE80211_CIPHER_TKIP:
2273 algo = R92C_CAM_ALGO_TKIP;
2274 break;
2275 case IEEE80211_CIPHER_AES_CCM:
2276 algo = R92C_CAM_ALGO_AES;
2277 break;
2278 default:
2279 device_printf(sc->sc_dev, "%s: undefined cipher %d\n",
2280 __func__, k->wk_cipher->ic_cipher);
2281 return;
2282 }
2283
2284 URTWN_DPRINTF(sc, URTWN_DEBUG_KEY,
2285 "%s: keyix %d, keyid %d, algo %d/%d, flags %04X, len %d, "
2286 "macaddr %s\n", __func__, k->wk_keyix, keyid,
2287 k->wk_cipher->ic_cipher, algo, k->wk_flags, k->wk_keylen,
2288 ether_sprintf(k->wk_macaddr));
2289
2290 /* Write key. */
2291 for (i = 0; i < 4; i++) {
2292 error = urtwn_cam_write(sc, R92C_CAM_KEY(k->wk_keyix, i),
2293 le32dec(&k->wk_key[i * 4]));
2294 if (error != 0)
2295 goto fail;
2296 }
2297
2298 /* Write CTL0 last since that will validate the CAM entry. */
2299 error = urtwn_cam_write(sc, R92C_CAM_CTL1(k->wk_keyix),
2300 le32dec(&k->wk_macaddr[2]));
2301 if (error != 0)
2302 goto fail;
2303 error = urtwn_cam_write(sc, R92C_CAM_CTL0(k->wk_keyix),
2304 SM(R92C_CAM_ALGO, algo) |
2305 SM(R92C_CAM_KEYID, keyid) |
2306 SM(R92C_CAM_MACLO, le16dec(&k->wk_macaddr[0])) |
2307 R92C_CAM_VALID);
2308 if (error != 0)
2309 goto fail;
2310
2311 return;
2312
2313fail:
2314 device_printf(sc->sc_dev, "%s fails, error %d\n", __func__, error);
2315}
2316
2317static void
2318urtwn_key_del_cb(struct urtwn_softc *sc, union sec_param *data)
2319{
2320 struct ieee80211_key *k = &data->key;
2321 int i;
2322
2323 URTWN_DPRINTF(sc, URTWN_DEBUG_KEY,
2324 "%s: keyix %d, flags %04X, macaddr %s\n", __func__,
2325 k->wk_keyix, k->wk_flags, ether_sprintf(k->wk_macaddr));
2326
2327 urtwn_cam_write(sc, R92C_CAM_CTL0(k->wk_keyix), 0);
2328 urtwn_cam_write(sc, R92C_CAM_CTL1(k->wk_keyix), 0);
2329
2330 /* Clear key. */
2331 for (i = 0; i < 4; i++)
2332 urtwn_cam_write(sc, R92C_CAM_KEY(k->wk_keyix, i), 0);
2333 sc->keys_bmap &= ~(1 << k->wk_keyix);
2334}
2335
2336static int
2337urtwn_key_set(struct ieee80211vap *vap, const struct ieee80211_key *k)
2338{
2339 struct urtwn_softc *sc = vap->iv_ic->ic_softc;
2340
2341 if (k->wk_flags & IEEE80211_KEY_SWCRYPT) {
2342 /* Not for us. */
2343 return (1);
2344 }
2345
2346 return (!urtwn_cmd_sleepable(sc, k, sizeof(*k), urtwn_key_set_cb));
2347}
2348
2349static int
2350urtwn_key_delete(struct ieee80211vap *vap, const struct ieee80211_key *k)
2351{
2352 struct urtwn_softc *sc = vap->iv_ic->ic_softc;
2353
2354 if (k->wk_flags & IEEE80211_KEY_SWCRYPT) {
2355 /* Not for us. */
2356 return (1);
2357 }
2358
2359 return (!urtwn_cmd_sleepable(sc, k, sizeof(*k), urtwn_key_del_cb));
2360}
2361
2362static void
2363urtwn_tsf_task_adhoc(void *arg, int pending)
2364{
2365 struct ieee80211vap *vap = arg;
2366 struct urtwn_softc *sc = vap->iv_ic->ic_softc;
2367 struct ieee80211_node *ni;
2368 uint32_t reg;
2369
2370 URTWN_LOCK(sc);
2371 ni = ieee80211_ref_node(vap->iv_bss);
2372 reg = urtwn_read_1(sc, R92C_BCN_CTRL);
2373
2374 /* Accept beacons with the same BSSID. */
2375 urtwn_set_rx_bssid_all(sc, 0);
2376
2377 /* Enable synchronization. */
2378 reg &= ~R92C_BCN_CTRL_DIS_TSF_UDT0;
2379 urtwn_write_1(sc, R92C_BCN_CTRL, reg);
2380
2381 /* Synchronize. */
2382 usb_pause_mtx(&sc->sc_mtx, hz * ni->ni_intval * 5 / 1000);
2383
2384 /* Disable synchronization. */
2385 reg |= R92C_BCN_CTRL_DIS_TSF_UDT0;
2386 urtwn_write_1(sc, R92C_BCN_CTRL, reg);
2387
2388 /* Remove beacon filter. */
2389 urtwn_set_rx_bssid_all(sc, 1);
2390
2391 /* Enable beaconing. */
2392 urtwn_write_1(sc, R92C_MBID_NUM,
2393 urtwn_read_1(sc, R92C_MBID_NUM) | R92C_MBID_TXBCN_RPT0);
2394 reg |= R92C_BCN_CTRL_EN_BCN;
2395
2396 urtwn_write_1(sc, R92C_BCN_CTRL, reg);
2397 ieee80211_free_node(ni);
2398 URTWN_UNLOCK(sc);
2399}
2400
2401static void
2402urtwn_tsf_sync_enable(struct urtwn_softc *sc, struct ieee80211vap *vap)
2403{
2404 struct ieee80211com *ic = &sc->sc_ic;
2405 struct urtwn_vap *uvp = URTWN_VAP(vap);
2406
2407 /* Reset TSF. */
2408 urtwn_write_1(sc, R92C_DUAL_TSF_RST, R92C_DUAL_TSF_RST0);
2409
2410 switch (vap->iv_opmode) {
2411 case IEEE80211_M_STA:
2412 /* Enable TSF synchronization. */
2413 urtwn_write_1(sc, R92C_BCN_CTRL,
2414 urtwn_read_1(sc, R92C_BCN_CTRL) &
2415 ~R92C_BCN_CTRL_DIS_TSF_UDT0);
2416 break;
2417 case IEEE80211_M_IBSS:
2418 ieee80211_runtask(ic, &uvp->tsf_task_adhoc);
2419 break;
2420 case IEEE80211_M_HOSTAP:
2421 /* Enable beaconing. */
2422 urtwn_write_1(sc, R92C_MBID_NUM,
2423 urtwn_read_1(sc, R92C_MBID_NUM) | R92C_MBID_TXBCN_RPT0);
2424 urtwn_write_1(sc, R92C_BCN_CTRL,
2425 urtwn_read_1(sc, R92C_BCN_CTRL) | R92C_BCN_CTRL_EN_BCN);
2426 break;
2427 default:
2428 device_printf(sc->sc_dev, "undefined opmode %d\n",
2429 vap->iv_opmode);
2430 return;
2431 }
2432}
2433
2434static void
2435urtwn_get_tsf(struct urtwn_softc *sc, uint64_t *buf)
2436{
2437 urtwn_read_region_1(sc, R92C_TSFTR, (uint8_t *)buf, sizeof(*buf));
2438}
2439
2440static void
2441urtwn_set_led(struct urtwn_softc *sc, int led, int on)
2442{
2443 uint8_t reg;
2444
2445 if (led == URTWN_LED_LINK) {
2446 if (sc->chip & URTWN_CHIP_88E) {
2447 reg = urtwn_read_1(sc, R92C_LEDCFG2) & 0xf0;
2448 urtwn_write_1(sc, R92C_LEDCFG2, reg | 0x60);
2449 if (!on) {
2450 reg = urtwn_read_1(sc, R92C_LEDCFG2) & 0x90;
2451 urtwn_write_1(sc, R92C_LEDCFG2,
2452 reg | R92C_LEDCFG0_DIS);
2453 urtwn_write_1(sc, R92C_MAC_PINMUX_CFG,
2454 urtwn_read_1(sc, R92C_MAC_PINMUX_CFG) &
2455 0xfe);
2456 }
2457 } else {
2458 reg = urtwn_read_1(sc, R92C_LEDCFG0) & 0x70;
2459 if (!on)
2460 reg |= R92C_LEDCFG0_DIS;
2461 urtwn_write_1(sc, R92C_LEDCFG0, reg);
2462 }
2463 sc->ledlink = on; /* Save LED state. */
2464 }
2465}
2466
2467static void
2468urtwn_set_mode(struct urtwn_softc *sc, uint8_t mode)
2469{
2470 uint8_t reg;
2471
2472 reg = urtwn_read_1(sc, R92C_MSR);
2473 reg = (reg & ~R92C_MSR_MASK) | mode;
2474 urtwn_write_1(sc, R92C_MSR, reg);
2475}
2476
2477static void
2478urtwn_ibss_recv_mgmt(struct ieee80211_node *ni, struct mbuf *m, int subtype,
2479 const struct ieee80211_rx_stats *rxs,
2480 int rssi, int nf)
2481{
2482 struct ieee80211vap *vap = ni->ni_vap;
2483 struct urtwn_softc *sc = vap->iv_ic->ic_softc;
2484 struct urtwn_vap *uvp = URTWN_VAP(vap);
2485 uint64_t ni_tstamp, curr_tstamp;
2486
2487 uvp->recv_mgmt(ni, m, subtype, rxs, rssi, nf);
2488
2489 if (vap->iv_state == IEEE80211_S_RUN &&
2490 (subtype == IEEE80211_FC0_SUBTYPE_BEACON ||
2491 subtype == IEEE80211_FC0_SUBTYPE_PROBE_RESP)) {
2492 ni_tstamp = le64toh(ni->ni_tstamp.tsf);
2493 URTWN_LOCK(sc);
2494 urtwn_get_tsf(sc, &curr_tstamp);
2495 URTWN_UNLOCK(sc);
2496 curr_tstamp = le64toh(curr_tstamp);
2497
2498 if (ni_tstamp >= curr_tstamp)
2499 (void) ieee80211_ibss_merge(ni);
2500 }
2501}
2502
2503static int
2504urtwn_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg)
2505{
2506 struct urtwn_vap *uvp = URTWN_VAP(vap);
2507 struct ieee80211com *ic = vap->iv_ic;
2508 struct urtwn_softc *sc = ic->ic_softc;
2509 struct ieee80211_node *ni;
2510 enum ieee80211_state ostate;
2511 uint32_t reg;
2512 uint8_t mode;
2513 int error = 0;
2514
2515 ostate = vap->iv_state;
2516 URTWN_DPRINTF(sc, URTWN_DEBUG_STATE, "%s -> %s\n",
2517 ieee80211_state_name[ostate], ieee80211_state_name[nstate]);
2518
2519 IEEE80211_UNLOCK(ic);
2520 URTWN_LOCK(sc);
2521 callout_stop(&sc->sc_watchdog_ch);
2522
2523 if (ostate == IEEE80211_S_RUN) {
2524 /* Stop calibration. */
2525 callout_stop(&sc->sc_calib_to);
2526
2527 /* Turn link LED off. */
2528 urtwn_set_led(sc, URTWN_LED_LINK, 0);
2529
2530 /* Set media status to 'No Link'. */
2531 urtwn_set_mode(sc, R92C_MSR_NOLINK);
2532
2533 /* Stop Rx of data frames. */
2534 urtwn_write_2(sc, R92C_RXFLTMAP2, 0);
2535
2536 /* Disable TSF synchronization. */
2537 urtwn_write_1(sc, R92C_BCN_CTRL,
2538 (urtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_EN_BCN) |
2539 R92C_BCN_CTRL_DIS_TSF_UDT0);
2540
2541 /* Disable beaconing. */
2542 urtwn_write_1(sc, R92C_MBID_NUM,
2543 urtwn_read_1(sc, R92C_MBID_NUM) & ~R92C_MBID_TXBCN_RPT0);
2544
2545 /* Reset TSF. */
2546 urtwn_write_1(sc, R92C_DUAL_TSF_RST, R92C_DUAL_TSF_RST0);
2547
2548 /* Reset EDCA parameters. */
2549 urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002f3217);
2550 urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005e4317);
2551 urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x00105320);
2552 urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a444);
2553 }
2554
2555 switch (nstate) {
2556 case IEEE80211_S_INIT:
2557 /* Turn link LED off. */
2558 urtwn_set_led(sc, URTWN_LED_LINK, 0);
2559 break;
2560 case IEEE80211_S_SCAN:
2561 /* Pause AC Tx queues. */
2562 urtwn_write_1(sc, R92C_TXPAUSE,
2563 urtwn_read_1(sc, R92C_TXPAUSE) | R92C_TX_QUEUE_AC);
2564 break;
2565 case IEEE80211_S_AUTH:
2566 urtwn_set_chan(sc, ic->ic_curchan, NULL);
2567 break;
2568 case IEEE80211_S_RUN:
2569 if (vap->iv_opmode == IEEE80211_M_MONITOR) {
2570 /* Turn link LED on. */
2571 urtwn_set_led(sc, URTWN_LED_LINK, 1);
2572 break;
2573 }
2574
2575 ni = ieee80211_ref_node(vap->iv_bss);
2576
2577 if (ic->ic_bsschan == IEEE80211_CHAN_ANYC ||
2578 ni->ni_chan == IEEE80211_CHAN_ANYC) {
2579 device_printf(sc->sc_dev,
2580 "%s: could not move to RUN state\n", __func__);
2581 error = EINVAL;
2582 goto end_run;
2583 }
2584
2585 switch (vap->iv_opmode) {
2586 case IEEE80211_M_STA:
2587 mode = R92C_MSR_INFRA;
2588 break;
2589 case IEEE80211_M_IBSS:
2590 mode = R92C_MSR_ADHOC;
2591 break;
2592 case IEEE80211_M_HOSTAP:
2593 mode = R92C_MSR_AP;
2594 break;
2595 default:
2596 device_printf(sc->sc_dev, "undefined opmode %d\n",
2597 vap->iv_opmode);
2598 error = EINVAL;
2599 goto end_run;
2600 }
2601
2602 /* Set media status to 'Associated'. */
2603 urtwn_set_mode(sc, mode);
2604
2605 /* Set BSSID. */
2606 urtwn_write_4(sc, R92C_BSSID + 0, le32dec(&ni->ni_bssid[0]));
2607 urtwn_write_4(sc, R92C_BSSID + 4, le16dec(&ni->ni_bssid[4]));
2608
2609 if (ic->ic_curmode == IEEE80211_MODE_11B)
2610 urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 0);
2611 else /* 802.11b/g */
2612 urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 3);
2613
2614 /* Enable Rx of data frames. */
2615 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff);
2616
2617 /* Flush all AC queues. */
2618 urtwn_write_1(sc, R92C_TXPAUSE, 0);
2619
2620 /* Set beacon interval. */
2621 urtwn_write_2(sc, R92C_BCN_INTERVAL, ni->ni_intval);
2622
2623 /* Allow Rx from our BSSID only. */
2624 if (ic->ic_promisc == 0) {
2625 reg = urtwn_read_4(sc, R92C_RCR);
2626
2627 if (vap->iv_opmode != IEEE80211_M_HOSTAP)
2628 reg |= R92C_RCR_CBSSID_DATA;
2629 if (vap->iv_opmode != IEEE80211_M_IBSS)
2630 reg |= R92C_RCR_CBSSID_BCN;
2631
2632 urtwn_write_4(sc, R92C_RCR, reg);
2633 }
2634
2635 if (vap->iv_opmode == IEEE80211_M_HOSTAP ||
2636 vap->iv_opmode == IEEE80211_M_IBSS) {
2637 error = urtwn_setup_beacon(sc, ni);
2638 if (error != 0) {
2639 device_printf(sc->sc_dev,
2640 "unable to push beacon into the chip, "
2641 "error %d\n", error);
2642 goto end_run;
2643 }
2644 }
2645
2646 /* Enable TSF synchronization. */
2647 urtwn_tsf_sync_enable(sc, vap);
2648
2649 urtwn_write_1(sc, R92C_SIFS_CCK + 1, 10);
2650 urtwn_write_1(sc, R92C_SIFS_OFDM + 1, 10);
2651 urtwn_write_1(sc, R92C_SPEC_SIFS + 1, 10);
2652 urtwn_write_1(sc, R92C_MAC_SPEC_SIFS + 1, 10);
2653 urtwn_write_1(sc, R92C_R2T_SIFS + 1, 10);
2654 urtwn_write_1(sc, R92C_T2T_SIFS + 1, 10);
2655
2656 /* Intialize rate adaptation. */
2657 if (!(sc->chip & URTWN_CHIP_88E))
2658 urtwn_ra_init(sc);
2659 /* Turn link LED on. */
2660 urtwn_set_led(sc, URTWN_LED_LINK, 1);
2661
2662 sc->avg_pwdb = -1; /* Reset average RSSI. */
2663 /* Reset temperature calibration state machine. */
2664 sc->sc_flags &= ~URTWN_TEMP_MEASURED;
2665 sc->thcal_lctemp = 0;
2666 /* Start periodic calibration. */
2667 callout_reset(&sc->sc_calib_to, 2*hz, urtwn_calib_to, sc);
2668
2669end_run:
2670 ieee80211_free_node(ni);
2671 break;
2672 default:
2673 break;
2674 }
2675
2676 URTWN_UNLOCK(sc);
2677 IEEE80211_LOCK(ic);
2678 return (error != 0 ? error : uvp->newstate(vap, nstate, arg));
2679}
2680
2681static void
2682urtwn_calib_to(void *arg)
2683{
2684 struct urtwn_softc *sc = arg;
2685
2686 /* Do it in a process context. */
2687 urtwn_cmd_sleepable(sc, NULL, 0, urtwn_calib_cb);
2688}
2689
2690static void
2691urtwn_calib_cb(struct urtwn_softc *sc, union sec_param *data)
2692{
2693 /* Do temperature compensation. */
2694 urtwn_temp_calib(sc);
2695
2696 if ((urtwn_read_1(sc, R92C_MSR) & R92C_MSR_MASK) != R92C_MSR_NOLINK)
2697 callout_reset(&sc->sc_calib_to, 2*hz, urtwn_calib_to, sc);
2698}
2699
2700static void
2701urtwn_watchdog(void *arg)
2702{
2703 struct urtwn_softc *sc = arg;
2704
2705 if (sc->sc_txtimer > 0) {
2706 if (--sc->sc_txtimer == 0) {
2707 device_printf(sc->sc_dev, "device timeout\n");
2708 counter_u64_add(sc->sc_ic.ic_oerrors, 1);
2709 return;
2710 }
2711 callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc);
2712 }
2713}
2714
2715static void
2716urtwn_update_avgrssi(struct urtwn_softc *sc, int rate, int8_t rssi)
2717{
2718 int pwdb;
2719
2720 /* Convert antenna signal to percentage. */
2721 if (rssi <= -100 || rssi >= 20)
2722 pwdb = 0;
2723 else if (rssi >= 0)
2724 pwdb = 100;
2725 else
2726 pwdb = 100 + rssi;
2727 if (!(sc->chip & URTWN_CHIP_88E)) {
2728 if (rate <= URTWN_RIDX_CCK11) {
2729 /* CCK gain is smaller than OFDM/MCS gain. */
2730 pwdb += 6;
2731 if (pwdb > 100)
2732 pwdb = 100;
2733 if (pwdb <= 14)
2734 pwdb -= 4;
2735 else if (pwdb <= 26)
2736 pwdb -= 8;
2737 else if (pwdb <= 34)
2738 pwdb -= 6;
2739 else if (pwdb <= 42)
2740 pwdb -= 2;
2741 }
2742 }
2743 if (sc->avg_pwdb == -1) /* Init. */
2744 sc->avg_pwdb = pwdb;
2745 else if (sc->avg_pwdb < pwdb)
2746 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20) + 1;
2747 else
2748 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20);
2749 URTWN_DPRINTF(sc, URTWN_DEBUG_RSSI, "%s: PWDB %d, EMA %d\n", __func__,
2750 pwdb, sc->avg_pwdb);
2751}
2752
2753static int8_t
2754urtwn_get_rssi(struct urtwn_softc *sc, int rate, void *physt)
2755{
2756 static const int8_t cckoff[] = { 16, -12, -26, -46 };
2757 struct r92c_rx_phystat *phy;
2758 struct r92c_rx_cck *cck;
2759 uint8_t rpt;
2760 int8_t rssi;
2761
2762 if (rate <= URTWN_RIDX_CCK11) {
2763 cck = (struct r92c_rx_cck *)physt;
2764 if (sc->sc_flags & URTWN_FLAG_CCK_HIPWR) {
2765 rpt = (cck->agc_rpt >> 5) & 0x3;
2766 rssi = (cck->agc_rpt & 0x1f) << 1;
2767 } else {
2768 rpt = (cck->agc_rpt >> 6) & 0x3;
2769 rssi = cck->agc_rpt & 0x3e;
2770 }
2771 rssi = cckoff[rpt] - rssi;
2772 } else { /* OFDM/HT. */
2773 phy = (struct r92c_rx_phystat *)physt;
2774 rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110;
2775 }
2776 return (rssi);
2777}
2778
2779static int8_t
2780urtwn_r88e_get_rssi(struct urtwn_softc *sc, int rate, void *physt)
2781{
2782 struct r92c_rx_phystat *phy;
2783 struct r88e_rx_cck *cck;
2784 uint8_t cck_agc_rpt, lna_idx, vga_idx;
2785 int8_t rssi;
2786
2787 rssi = 0;
2788 if (rate <= URTWN_RIDX_CCK11) {
2789 cck = (struct r88e_rx_cck *)physt;
2790 cck_agc_rpt = cck->agc_rpt;
2791 lna_idx = (cck_agc_rpt & 0xe0) >> 5;
2792 vga_idx = cck_agc_rpt & 0x1f;
2793 switch (lna_idx) {
2794 case 7:
2795 if (vga_idx <= 27)
2796 rssi = -100 + 2* (27 - vga_idx);
2797 else
2798 rssi = -100;
2799 break;
2800 case 6:
2801 rssi = -48 + 2 * (2 - vga_idx);
2802 break;
2803 case 5:
2804 rssi = -42 + 2 * (7 - vga_idx);
2805 break;
2806 case 4:
2807 rssi = -36 + 2 * (7 - vga_idx);
2808 break;
2809 case 3:
2810 rssi = -24 + 2 * (7 - vga_idx);
2811 break;
2812 case 2:
2813 rssi = -12 + 2 * (5 - vga_idx);
2814 break;
2815 case 1:
2816 rssi = 8 - (2 * vga_idx);
2817 break;
2818 case 0:
2819 rssi = 14 - (2 * vga_idx);
2820 break;
2821 }
2822 rssi += 6;
2823 } else { /* OFDM/HT. */
2824 phy = (struct r92c_rx_phystat *)physt;
2825 rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110;
2826 }
2827 return (rssi);
2828}
2829
2830static int
2831urtwn_tx_data(struct urtwn_softc *sc, struct ieee80211_node *ni,
2832 struct mbuf *m, struct urtwn_data *data)
2833{
2834 const struct ieee80211_txparam *tp;
2835 struct ieee80211com *ic = &sc->sc_ic;
2836 struct ieee80211vap *vap = ni->ni_vap;
2837 struct ieee80211_key *k = NULL;
2838 struct ieee80211_channel *chan;
2839 struct ieee80211_frame *wh;
2840 struct r92c_tx_desc *txd;
2841 uint8_t macid, raid, rate, ridx, type, tid, qos, qsel;
2842 int hasqos, ismcast;
2843
2844 URTWN_ASSERT_LOCKED(sc);
2845
2846 wh = mtod(m, struct ieee80211_frame *);
2847 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK;
2848 hasqos = IEEE80211_QOS_HAS_SEQ(wh);
2849 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1);
2850
2851 /* Select TX ring for this frame. */
2852 if (hasqos) {
2853 qos = ((const struct ieee80211_qosframe *)wh)->i_qos[0];
2854 tid = qos & IEEE80211_QOS_TID;
2855 } else {
2856 qos = 0;
2857 tid = 0;
2858 }
2859
2860 chan = (ni->ni_chan != IEEE80211_CHAN_ANYC) ?
2861 ni->ni_chan : ic->ic_curchan;
2862 tp = &vap->iv_txparms[ieee80211_chan2mode(chan)];
2863
2864 /* Choose a TX rate index. */
2865 if (type == IEEE80211_FC0_TYPE_MGT)
2866 rate = tp->mgmtrate;
2867 else if (ismcast)
2868 rate = tp->mcastrate;
2869 else if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE)
2870 rate = tp->ucastrate;
2871 else if (m->m_flags & M_EAPOL)
2872 rate = tp->mgmtrate;
2873 else {
2874 if (URTWN_CHIP_HAS_RATECTL(sc)) {
2875 /* XXX pass pktlen */
2876 (void) ieee80211_ratectl_rate(ni, NULL, 0);
2877 rate = ni->ni_txrate;
2878 } else {
2879 /* XXX TODO: drop the default rate for 11b/11g? */
2880 if (ni->ni_flags & IEEE80211_NODE_HT)
2881 rate = IEEE80211_RATE_MCS | 0x4; /* MCS4 */
2882 else if (ic->ic_curmode != IEEE80211_MODE_11B)
2883 rate = 108;
2884 else
2885 rate = 22;
2886 }
2887 }
2888
2889 /*
2890 * XXX TODO: this should be per-node, for 11b versus 11bg
2891 * nodes in hostap mode
2892 */
2893 ridx = rate2ridx(rate);
2894 if (ni->ni_flags & IEEE80211_NODE_HT)
2895 raid = R92C_RAID_11GN;
2896 else if (ic->ic_curmode != IEEE80211_MODE_11B)
2897 raid = R92C_RAID_11BG;
2898 else
2899 raid = R92C_RAID_11B;
2900
2901 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) {
2902 k = ieee80211_crypto_encap(ni, m);
2903 if (k == NULL) {
2904 device_printf(sc->sc_dev,
2905 "ieee80211_crypto_encap returns NULL.\n");
2906 return (ENOBUFS);
2907 }
2908
2909 /* in case packet header moved, reset pointer */
2910 wh = mtod(m, struct ieee80211_frame *);
2911 }
2912
2913 /* Fill Tx descriptor. */
2914 txd = (struct r92c_tx_desc *)data->buf;
2915 memset(txd, 0, sizeof(*txd));
2916
2917 txd->txdw0 |= htole32(
2918 SM(R92C_TXDW0_OFFSET, sizeof(*txd)) |
2919 R92C_TXDW0_OWN | R92C_TXDW0_FSG | R92C_TXDW0_LSG);
2920 if (ismcast)
2921 txd->txdw0 |= htole32(R92C_TXDW0_BMCAST);
2922
2923 if (!ismcast) {
2924 /* Unicast frame, check if an ACK is expected. */
2925 if (!qos || (qos & IEEE80211_QOS_ACKPOLICY) !=
2926 IEEE80211_QOS_ACKPOLICY_NOACK) {
2927 txd->txdw5 |= htole32(R92C_TXDW5_RTY_LMT_ENA);
2928 txd->txdw5 |= htole32(SM(R92C_TXDW5_RTY_LMT,
2929 tp->maxretry));
2930 }
2931
2932 if (sc->chip & URTWN_CHIP_88E) {
2933 struct urtwn_node *un = URTWN_NODE(ni);
2934 macid = un->id;
2935 } else
2936 macid = URTWN_MACID_BSS;
2937
2938 if (type == IEEE80211_FC0_TYPE_DATA) {
2939 qsel = tid % URTWN_MAX_TID;
2940
2941 if (sc->chip & URTWN_CHIP_88E) {
2942 txd->txdw2 |= htole32(
2943 R88E_TXDW2_AGGBK |
2944 R88E_TXDW2_CCX_RPT);
2945 } else
2946 txd->txdw1 |= htole32(R92C_TXDW1_AGGBK);
2947
2948 /* protmode, non-HT */
2949 /* XXX TODO: noack frames? */
2950 if ((rate & 0x80) == 0 &&
2951 (ic->ic_flags & IEEE80211_F_USEPROT)) {
2952 switch (ic->ic_protmode) {
2953 case IEEE80211_PROT_CTSONLY:
2954 txd->txdw4 |= htole32(
2955 R92C_TXDW4_CTS2SELF |
2956 R92C_TXDW4_HWRTSEN);
2957 break;
2958 case IEEE80211_PROT_RTSCTS:
2959 txd->txdw4 |= htole32(
2960 R92C_TXDW4_RTSEN |
2961 R92C_TXDW4_HWRTSEN);
2962 break;
2963 default:
2964 break;
2965 }
2966 }
2967
2968 /* protmode, HT */
2969 /* XXX TODO: noack frames? */
2970 if ((rate & 0x80) &&
2971 (ic->ic_htprotmode == IEEE80211_PROT_RTSCTS)) {
2972 txd->txdw4 |= htole32(
2973 R92C_TXDW4_RTSEN |
2974 R92C_TXDW4_HWRTSEN);
2975 }
2976
2977 /* XXX TODO: rtsrate is configurable? 24mbit may
2978 * be a bit high for RTS rate? */
2979 txd->txdw4 |= htole32(SM(R92C_TXDW4_RTSRATE,
2980 URTWN_RIDX_OFDM24));
2981
2982 txd->txdw5 |= htole32(0x0001ff00);
2983 } else /* IEEE80211_FC0_TYPE_MGT */
2984 qsel = R92C_TXDW1_QSEL_MGNT;
2985 } else {
2986 macid = URTWN_MACID_BC;
2987 qsel = R92C_TXDW1_QSEL_MGNT;
2988 }
2989
2990 txd->txdw1 |= htole32(
2991 SM(R92C_TXDW1_QSEL, qsel) |
2992 SM(R92C_TXDW1_RAID, raid));
2993
2994 /* XXX TODO: 40MHZ flag? */
2995 /* XXX TODO: AMPDU flag? (AGG_ENABLE or AGG_BREAK?) Density shift? */
2996 /* XXX Short preamble? */
2997 /* XXX Short-GI? */
2998
2999 if (sc->chip & URTWN_CHIP_88E)
3000 txd->txdw1 |= htole32(SM(R88E_TXDW1_MACID, macid));
3001 else
3002 txd->txdw1 |= htole32(SM(R92C_TXDW1_MACID, macid));
3003
3004 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, ridx));
3005
3006 /* Force this rate if needed. */
3007 if (URTWN_CHIP_HAS_RATECTL(sc) || ismcast ||
3008 (tp->ucastrate != IEEE80211_FIXED_RATE_NONE) ||
3009 (m->m_flags & M_EAPOL) || type != IEEE80211_FC0_TYPE_DATA)
3010 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE);
3011
3012 if (!hasqos) {
3013 /* Use HW sequence numbering for non-QoS frames. */
3014 if (sc->chip & URTWN_CHIP_88E)
3015 txd->txdseq = htole16(R88E_TXDSEQ_HWSEQ_EN);
3016 else
3017 txd->txdw4 |= htole32(R92C_TXDW4_HWSEQ_EN);
3018 } else {
3019 /* Set sequence number. */
3020 txd->txdseq = htole16(M_SEQNO_GET(m) % IEEE80211_SEQ_RANGE);
3021 }
3022
3023 if (k != NULL && !(k->wk_flags & IEEE80211_KEY_SWCRYPT)) {
3024 uint8_t cipher;
3025
3026 switch (k->wk_cipher->ic_cipher) {
3027 case IEEE80211_CIPHER_WEP:
3028 case IEEE80211_CIPHER_TKIP:
3029 cipher = R92C_TXDW1_CIPHER_RC4;
3030 break;
3031 case IEEE80211_CIPHER_AES_CCM:
3032 cipher = R92C_TXDW1_CIPHER_AES;
3033 break;
3034 default:
3035 device_printf(sc->sc_dev, "%s: unknown cipher %d\n",
3036 __func__, k->wk_cipher->ic_cipher);
3037 return (EINVAL);
3038 }
3039
3040 txd->txdw1 |= htole32(SM(R92C_TXDW1_CIPHER, cipher));
3041 }
3042
3043 if (ieee80211_radiotap_active_vap(vap)) {
3044 struct urtwn_tx_radiotap_header *tap = &sc->sc_txtap;
3045
3046 tap->wt_flags = 0;
3047 if (k != NULL)
3048 tap->wt_flags |= IEEE80211_RADIOTAP_F_WEP;
3049 ieee80211_radiotap_tx(vap, m);
3050 }
3051
3052 data->ni = ni;
3053
3054 urtwn_tx_start(sc, m, type, data);
3055
3056 return (0);
3057}
3058
3059static int
3060urtwn_tx_raw(struct urtwn_softc *sc, struct ieee80211_node *ni,
3061 struct mbuf *m, struct urtwn_data *data,
3062 const struct ieee80211_bpf_params *params)
3063{
3064 struct ieee80211vap *vap = ni->ni_vap;
3065 struct ieee80211_key *k = NULL;
3066 struct ieee80211_frame *wh;
3067 struct r92c_tx_desc *txd;
3068 uint8_t cipher, ridx, type;
3069
3070 /* Encrypt the frame if need be. */
3071 cipher = R92C_TXDW1_CIPHER_NONE;
3072 if (params->ibp_flags & IEEE80211_BPF_CRYPTO) {
3073 /* Retrieve key for TX. */
3074 k = ieee80211_crypto_encap(ni, m);
3075 if (k == NULL)
3076 return (ENOBUFS);
3077
3078 if (!(k->wk_flags & IEEE80211_KEY_SWCRYPT)) {
3079 switch (k->wk_cipher->ic_cipher) {
3080 case IEEE80211_CIPHER_WEP:
3081 case IEEE80211_CIPHER_TKIP:
3082 cipher = R92C_TXDW1_CIPHER_RC4;
3083 break;
3084 case IEEE80211_CIPHER_AES_CCM:
3085 cipher = R92C_TXDW1_CIPHER_AES;
3086 break;
3087 default:
3088 device_printf(sc->sc_dev,
3089 "%s: unknown cipher %d\n",
3090 __func__, k->wk_cipher->ic_cipher);
3091 return (EINVAL);
3092 }
3093 }
3094 }
3095
3096 /* XXX TODO: 11n checks, matching urtwn_tx_data() */
3097
3098 wh = mtod(m, struct ieee80211_frame *);
3099 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK;
3100
3101 /* Fill Tx descriptor. */
3102 txd = (struct r92c_tx_desc *)data->buf;
3103 memset(txd, 0, sizeof(*txd));
3104
3105 txd->txdw0 |= htole32(
3106 SM(R92C_TXDW0_OFFSET, sizeof(*txd)) |
3107 R92C_TXDW0_OWN | R92C_TXDW0_FSG | R92C_TXDW0_LSG);
3108 if (IEEE80211_IS_MULTICAST(wh->i_addr1))
3109 txd->txdw0 |= htole32(R92C_TXDW0_BMCAST);
3110
3111 if ((params->ibp_flags & IEEE80211_BPF_NOACK) == 0) {
3112 txd->txdw5 |= htole32(R92C_TXDW5_RTY_LMT_ENA);
3113 txd->txdw5 |= htole32(SM(R92C_TXDW5_RTY_LMT,
3114 params->ibp_try0));
3115 }
3116 if (params->ibp_flags & IEEE80211_BPF_RTS)
3117 txd->txdw4 |= htole32(R92C_TXDW4_RTSEN);
3118 if (params->ibp_flags & IEEE80211_BPF_CTS)
3119 txd->txdw4 |= htole32(R92C_TXDW4_CTS2SELF);
3120 if (txd->txdw4 & htole32(R92C_TXDW4_RTSEN | R92C_TXDW4_CTS2SELF)) {
3121 txd->txdw4 |= htole32(R92C_TXDW4_HWRTSEN);
3122 txd->txdw4 |= htole32(SM(R92C_TXDW4_RTSRATE,
3123 URTWN_RIDX_OFDM24));
3124 }
3125
3126 if (sc->chip & URTWN_CHIP_88E)
3127 txd->txdw1 |= htole32(SM(R88E_TXDW1_MACID, URTWN_MACID_BC));
3128 else
3129 txd->txdw1 |= htole32(SM(R92C_TXDW1_MACID, URTWN_MACID_BC));
3130
3131 /* XXX TODO: rate index/config (RAID) for 11n? */
3132 txd->txdw1 |= htole32(SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_MGNT));
3133 txd->txdw1 |= htole32(SM(R92C_TXDW1_CIPHER, cipher));
3134
3135 /* Choose a TX rate index. */
3136 ridx = rate2ridx(params->ibp_rate0);
3137 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, ridx));
3138 txd->txdw5 |= htole32(0x0001ff00);
3139 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE);
3140
3141 if (!IEEE80211_QOS_HAS_SEQ(wh)) {
3142 /* Use HW sequence numbering for non-QoS frames. */
3143 if (sc->chip & URTWN_CHIP_88E)
3144 txd->txdseq = htole16(R88E_TXDSEQ_HWSEQ_EN);
3145 else
3146 txd->txdw4 |= htole32(R92C_TXDW4_HWSEQ_EN);
3147 } else {
3148 /* Set sequence number. */
3149 txd->txdseq = htole16(M_SEQNO_GET(m) % IEEE80211_SEQ_RANGE);
3150 }
3151
3152 if (ieee80211_radiotap_active_vap(vap)) {
3153 struct urtwn_tx_radiotap_header *tap = &sc->sc_txtap;
3154
3155 tap->wt_flags = 0;
3156 if (k != NULL)
3157 tap->wt_flags |= IEEE80211_RADIOTAP_F_WEP;
3158 ieee80211_radiotap_tx(vap, m);
3159 }
3160
3161 data->ni = ni;
3162
3163 urtwn_tx_start(sc, m, type, data);
3164
3165 return (0);
3166}
3167
3168static void
3169urtwn_tx_start(struct urtwn_softc *sc, struct mbuf *m, uint8_t type,
3170 struct urtwn_data *data)
3171{
3172 struct usb_xfer *xfer;
3173 struct r92c_tx_desc *txd;
3174 uint16_t ac, sum;
3175 int i, xferlen;
3176
3177 URTWN_ASSERT_LOCKED(sc);
3178
3179 ac = M_WME_GETAC(m);
3180
3181 switch (type) {
3182 case IEEE80211_FC0_TYPE_CTL:
3183 case IEEE80211_FC0_TYPE_MGT:
3184 xfer = sc->sc_xfer[URTWN_BULK_TX_VO];
3185 break;
3186 default:
3187 xfer = sc->sc_xfer[wme2queue[ac].qid];
3188 break;
3189 }
3190
3191 txd = (struct r92c_tx_desc *)data->buf;
3192 txd->txdw0 |= htole32(SM(R92C_TXDW0_PKTLEN, m->m_pkthdr.len));
3193
3194 /* Compute Tx descriptor checksum. */
3195 sum = 0;
3196 for (i = 0; i < sizeof(*txd) / 2; i++)
3197 sum ^= ((uint16_t *)txd)[i];
3198 txd->txdsum = sum; /* NB: already little endian. */
3199
3200 xferlen = sizeof(*txd) + m->m_pkthdr.len;
3201 m_copydata(m, 0, m->m_pkthdr.len, (caddr_t)&txd[1]);
3202
3203 data->buflen = xferlen;
3204 data->m = m;
3205
3206 STAILQ_INSERT_TAIL(&sc->sc_tx_pending, data, next);
3207 usbd_transfer_start(xfer);
3208}
3209
3210static int
3211urtwn_transmit(struct ieee80211com *ic, struct mbuf *m)
3212{
3213 struct urtwn_softc *sc = ic->ic_softc;
3214 int error;
3215
3216 URTWN_LOCK(sc);
3217 if ((sc->sc_flags & URTWN_RUNNING) == 0) {
3218 URTWN_UNLOCK(sc);
3219 return (ENXIO);
3220 }
3221 error = mbufq_enqueue(&sc->sc_snd, m);
3222 if (error) {
3223 URTWN_UNLOCK(sc);
3224 return (error);
3225 }
3226 urtwn_start(sc);
3227 URTWN_UNLOCK(sc);
3228
3229 return (0);
3230}
3231
3232static void
3233urtwn_start(struct urtwn_softc *sc)
3234{
3235 struct ieee80211_node *ni;
3236 struct mbuf *m;
3237 struct urtwn_data *bf;
3238
3239 URTWN_ASSERT_LOCKED(sc);
3240 while ((m = mbufq_dequeue(&sc->sc_snd)) != NULL) {
3241 bf = urtwn_getbuf(sc);
3242 if (bf == NULL) {
3243 mbufq_prepend(&sc->sc_snd, m);
3244 break;
3245 }
3246 ni = (struct ieee80211_node *)m->m_pkthdr.rcvif;
3247 m->m_pkthdr.rcvif = NULL;
3248
3249 URTWN_DPRINTF(sc, URTWN_DEBUG_XMIT, "%s: called; m=%p\n",
3250 __func__,
3251 m);
3252
3253 if (urtwn_tx_data(sc, ni, m, bf) != 0) {
3254 if_inc_counter(ni->ni_vap->iv_ifp,
3255 IFCOUNTER_OERRORS, 1);
3256 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, bf, next);
3257 m_freem(m);
3258 ieee80211_free_node(ni);
3259 break;
3260 }
3261 sc->sc_txtimer = 5;
3262 callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc);
3263 }
3264}
3265
3266static void
3267urtwn_parent(struct ieee80211com *ic)
3268{
3269 struct urtwn_softc *sc = ic->ic_softc;
3270
3271 URTWN_LOCK(sc);
3272 if (sc->sc_flags & URTWN_DETACHED) {
3273 URTWN_UNLOCK(sc);
3274 return;
3275 }
3276 URTWN_UNLOCK(sc);
3277
3278 if (ic->ic_nrunning > 0) {
3279 if (urtwn_init(sc) != 0) {
3280 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps);
3281 if (vap != NULL)
3282 ieee80211_stop(vap);
3283 } else
3284 ieee80211_start_all(ic);
3285 } else
3286 urtwn_stop(sc);
3287}
3288
3289static __inline int
3290urtwn_power_on(struct urtwn_softc *sc)
3291{
3292
3293 return sc->sc_power_on(sc);
3294}
3295
3296static int
3297urtwn_r92c_power_on(struct urtwn_softc *sc)
3298{
3299 uint32_t reg;
3300 usb_error_t error;
3301 int ntries;
3302
3303 /* Wait for autoload done bit. */
3304 for (ntries = 0; ntries < 1000; ntries++) {
3305 if (urtwn_read_1(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_PFM_ALDN)
3306 break;
3307 urtwn_ms_delay(sc);
3308 }
3309 if (ntries == 1000) {
3310 device_printf(sc->sc_dev,
3311 "timeout waiting for chip autoload\n");
3312 return (ETIMEDOUT);
3313 }
3314
3315 /* Unlock ISO/CLK/Power control register. */
3316 error = urtwn_write_1(sc, R92C_RSV_CTRL, 0);
3317 if (error != USB_ERR_NORMAL_COMPLETION)
3318 return (EIO);
3319 /* Move SPS into PWM mode. */
3320 error = urtwn_write_1(sc, R92C_SPS0_CTRL, 0x2b);
3321 if (error != USB_ERR_NORMAL_COMPLETION)
3322 return (EIO);
3323 urtwn_ms_delay(sc);
3324
3325 reg = urtwn_read_1(sc, R92C_LDOV12D_CTRL);
3326 if (!(reg & R92C_LDOV12D_CTRL_LDV12_EN)) {
3327 error = urtwn_write_1(sc, R92C_LDOV12D_CTRL,
3328 reg | R92C_LDOV12D_CTRL_LDV12_EN);
3329 if (error != USB_ERR_NORMAL_COMPLETION)
3330 return (EIO);
3331 urtwn_ms_delay(sc);
3332 error = urtwn_write_1(sc, R92C_SYS_ISO_CTRL,
3333 urtwn_read_1(sc, R92C_SYS_ISO_CTRL) &
3334 ~R92C_SYS_ISO_CTRL_MD2PP);
3335 if (error != USB_ERR_NORMAL_COMPLETION)
3336 return (EIO);
3337 }
3338
3339 /* Auto enable WLAN. */
3340 error = urtwn_write_2(sc, R92C_APS_FSMCO,
3341 urtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC);
3342 if (error != USB_ERR_NORMAL_COMPLETION)
3343 return (EIO);
3344 for (ntries = 0; ntries < 1000; ntries++) {
3345 if (!(urtwn_read_2(sc, R92C_APS_FSMCO) &
3346 R92C_APS_FSMCO_APFM_ONMAC))
3347 break;
3348 urtwn_ms_delay(sc);
3349 }
3350 if (ntries == 1000) {
3351 device_printf(sc->sc_dev,
3352 "timeout waiting for MAC auto ON\n");
3353 return (ETIMEDOUT);
3354 }
3355
3356 /* Enable radio, GPIO and LED functions. */
3357 error = urtwn_write_2(sc, R92C_APS_FSMCO,
3358 R92C_APS_FSMCO_AFSM_HSUS |
3359 R92C_APS_FSMCO_PDN_EN |
3360 R92C_APS_FSMCO_PFM_ALDN);
3361 if (error != USB_ERR_NORMAL_COMPLETION)
3362 return (EIO);
3363 /* Release RF digital isolation. */
3364 error = urtwn_write_2(sc, R92C_SYS_ISO_CTRL,
3365 urtwn_read_2(sc, R92C_SYS_ISO_CTRL) & ~R92C_SYS_ISO_CTRL_DIOR);
3366 if (error != USB_ERR_NORMAL_COMPLETION)
3367 return (EIO);
3368
3369 /* Initialize MAC. */
3370 error = urtwn_write_1(sc, R92C_APSD_CTRL,
3371 urtwn_read_1(sc, R92C_APSD_CTRL) & ~R92C_APSD_CTRL_OFF);
3372 if (error != USB_ERR_NORMAL_COMPLETION)
3373 return (EIO);
3374 for (ntries = 0; ntries < 200; ntries++) {
3375 if (!(urtwn_read_1(sc, R92C_APSD_CTRL) &
3376 R92C_APSD_CTRL_OFF_STATUS))
3377 break;
3378 urtwn_ms_delay(sc);
3379 }
3380 if (ntries == 200) {
3381 device_printf(sc->sc_dev,
3382 "timeout waiting for MAC initialization\n");
3383 return (ETIMEDOUT);
3384 }
3385
3386 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */
3387 reg = urtwn_read_2(sc, R92C_CR);
3388 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN |
3389 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN |
3390 R92C_CR_SCHEDULE_EN | R92C_CR_MACTXEN | R92C_CR_MACRXEN |
3391 R92C_CR_ENSEC;
3392 error = urtwn_write_2(sc, R92C_CR, reg);
3393 if (error != USB_ERR_NORMAL_COMPLETION)
3394 return (EIO);
3395
3396 error = urtwn_write_1(sc, 0xfe10, 0x19);
3397 if (error != USB_ERR_NORMAL_COMPLETION)
3398 return (EIO);
3399 return (0);
3400}
3401
3402static int
3403urtwn_r88e_power_on(struct urtwn_softc *sc)
3404{
3405 uint32_t reg;
3406 usb_error_t error;
3407 int ntries;
3408
3409 /* Wait for power ready bit. */
3410 for (ntries = 0; ntries < 5000; ntries++) {
3411 if (urtwn_read_4(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_SUS_HOST)
3412 break;
3413 urtwn_ms_delay(sc);
3414 }
3415 if (ntries == 5000) {
3416 device_printf(sc->sc_dev,
3417 "timeout waiting for chip power up\n");
3418 return (ETIMEDOUT);
3419 }
3420
3421 /* Reset BB. */
3422 error = urtwn_write_1(sc, R92C_SYS_FUNC_EN,
3423 urtwn_read_1(sc, R92C_SYS_FUNC_EN) & ~(R92C_SYS_FUNC_EN_BBRSTB |
3424 R92C_SYS_FUNC_EN_BB_GLB_RST));
3425 if (error != USB_ERR_NORMAL_COMPLETION)
3426 return (EIO);
3427
3428 error = urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 2,
3429 urtwn_read_1(sc, R92C_AFE_XTAL_CTRL + 2) | 0x80);
3430 if (error != USB_ERR_NORMAL_COMPLETION)
3431 return (EIO);
3432
3433 /* Disable HWPDN. */
3434 error = urtwn_write_2(sc, R92C_APS_FSMCO,
3435 urtwn_read_2(sc, R92C_APS_FSMCO) & ~R92C_APS_FSMCO_APDM_HPDN);
3436 if (error != USB_ERR_NORMAL_COMPLETION)
3437 return (EIO);
3438
3439 /* Disable WL suspend. */
3440 error = urtwn_write_2(sc, R92C_APS_FSMCO,
3441 urtwn_read_2(sc, R92C_APS_FSMCO) &
3442 ~(R92C_APS_FSMCO_AFSM_HSUS | R92C_APS_FSMCO_AFSM_PCIE));
3443 if (error != USB_ERR_NORMAL_COMPLETION)
3444 return (EIO);
3445
3446 error = urtwn_write_2(sc, R92C_APS_FSMCO,
3447 urtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC);
3448 if (error != USB_ERR_NORMAL_COMPLETION)
3449 return (EIO);
3450 for (ntries = 0; ntries < 5000; ntries++) {
3451 if (!(urtwn_read_2(sc, R92C_APS_FSMCO) &
3452 R92C_APS_FSMCO_APFM_ONMAC))
3453 break;
3454 urtwn_ms_delay(sc);
3455 }
3456 if (ntries == 5000)
3457 return (ETIMEDOUT);
3458
3459 /* Enable LDO normal mode. */
3460 error = urtwn_write_1(sc, R92C_LPLDO_CTRL,
3461 urtwn_read_1(sc, R92C_LPLDO_CTRL) & ~R92C_LPLDO_CTRL_SLEEP);
3462 if (error != USB_ERR_NORMAL_COMPLETION)
3463 return (EIO);
3464
3465 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */
3466 error = urtwn_write_2(sc, R92C_CR, 0);
3467 if (error != USB_ERR_NORMAL_COMPLETION)
3468 return (EIO);
3469 reg = urtwn_read_2(sc, R92C_CR);
3470 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN |
3471 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN |
3472 R92C_CR_SCHEDULE_EN | R92C_CR_ENSEC | R92C_CR_CALTMR_EN;
3473 error = urtwn_write_2(sc, R92C_CR, reg);
3474 if (error != USB_ERR_NORMAL_COMPLETION)
3475 return (EIO);
3476
3477 return (0);
3478}
3479
3480static __inline void
3481urtwn_power_off(struct urtwn_softc *sc)
3482{
3483
3484 return sc->sc_power_off(sc);
3485}
3486
3487static void
3488urtwn_r92c_power_off(struct urtwn_softc *sc)
3489{
3490 uint32_t reg;
3491
3492 /* Block all Tx queues. */
3493 urtwn_write_1(sc, R92C_TXPAUSE, R92C_TX_QUEUE_ALL);
3494
3495 /* Disable RF */
3496 urtwn_rf_write(sc, 0, 0, 0);
3497
3498 urtwn_write_1(sc, R92C_APSD_CTRL, R92C_APSD_CTRL_OFF);
3499
3500 /* Reset BB state machine */
3501 urtwn_write_1(sc, R92C_SYS_FUNC_EN,
3502 R92C_SYS_FUNC_EN_USBD | R92C_SYS_FUNC_EN_USBA |
3503 R92C_SYS_FUNC_EN_BB_GLB_RST);
3504 urtwn_write_1(sc, R92C_SYS_FUNC_EN,
3505 R92C_SYS_FUNC_EN_USBD | R92C_SYS_FUNC_EN_USBA);
3506
3507 /*
3508 * Reset digital sequence
3509 */
3510#ifndef URTWN_WITHOUT_UCODE
3511 if (urtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RDY) {
3512 /* Reset MCU ready status */
3513 urtwn_write_1(sc, R92C_MCUFWDL, 0);
3514
3515 /* If firmware in ram code, do reset */
3516 urtwn_fw_reset(sc);
3517 }
3518#endif
3519
3520 /* Reset MAC and Enable 8051 */
3521 urtwn_write_1(sc, R92C_SYS_FUNC_EN + 1,
3522 (R92C_SYS_FUNC_EN_CPUEN |
3523 R92C_SYS_FUNC_EN_ELDR |
3524 R92C_SYS_FUNC_EN_HWPDN) >> 8);
3525
3526 /* Reset MCU ready status */
3527 urtwn_write_1(sc, R92C_MCUFWDL, 0);
3528
3529 /* Disable MAC clock */
3530 urtwn_write_2(sc, R92C_SYS_CLKR,
3531 R92C_SYS_CLKR_ANAD16V_EN |
3532 R92C_SYS_CLKR_ANA8M |
3533 R92C_SYS_CLKR_LOADER_EN |
3534 R92C_SYS_CLKR_80M_SSC_DIS |
3535 R92C_SYS_CLKR_SYS_EN |
3536 R92C_SYS_CLKR_RING_EN |
3537 0x4000);
3538
3539 /* Disable AFE PLL */
3540 urtwn_write_1(sc, R92C_AFE_PLL_CTRL, 0x80);
3541
3542 /* Gated AFE DIG_CLOCK */
3543 urtwn_write_2(sc, R92C_AFE_XTAL_CTRL, 0x880F);
3544
3545 /* Isolated digital to PON */
3546 urtwn_write_1(sc, R92C_SYS_ISO_CTRL,
3547 R92C_SYS_ISO_CTRL_MD2PP |
3548 R92C_SYS_ISO_CTRL_PA2PCIE |
3549 R92C_SYS_ISO_CTRL_PD2CORE |
3550 R92C_SYS_ISO_CTRL_IP2MAC |
3551 R92C_SYS_ISO_CTRL_DIOP |
3552 R92C_SYS_ISO_CTRL_DIOE);
3553
3554 /*
3555 * Pull GPIO PIN to balance level and LED control
3556 */
3557 /* 1. Disable GPIO[7:0] */
3558 urtwn_write_2(sc, R92C_GPIO_IOSEL, 0x0000);
3559
3560 reg = urtwn_read_4(sc, R92C_GPIO_PIN_CTRL) & ~0x0000ff00;
3561 reg |= ((reg << 8) & 0x0000ff00) | 0x00ff0000;
3562 urtwn_write_4(sc, R92C_GPIO_PIN_CTRL, reg);
3563
3564 /* Disable GPIO[10:8] */
3565 urtwn_write_1(sc, R92C_MAC_PINMUX_CFG, 0x00);
3566
3567 reg = urtwn_read_2(sc, R92C_GPIO_IO_SEL) & ~0x00f0;
3568 reg |= (((reg & 0x000f) << 4) | 0x0780);
3569 urtwn_write_2(sc, R92C_GPIO_IO_SEL, reg);
3570
3571 /* Disable LED0 & 1 */
3572 urtwn_write_2(sc, R92C_LEDCFG0, 0x8080);
3573
3574 /*
3575 * Reset digital sequence
3576 */
3577 /* Disable ELDR clock */
3578 urtwn_write_2(sc, R92C_SYS_CLKR,
3579 R92C_SYS_CLKR_ANAD16V_EN |
3580 R92C_SYS_CLKR_ANA8M |
3581 R92C_SYS_CLKR_LOADER_EN |
3582 R92C_SYS_CLKR_80M_SSC_DIS |
3583 R92C_SYS_CLKR_SYS_EN |
3584 R92C_SYS_CLKR_RING_EN |
3585 0x4000);
3586
3587 /* Isolated ELDR to PON */
3588 urtwn_write_1(sc, R92C_SYS_ISO_CTRL + 1,
3589 (R92C_SYS_ISO_CTRL_DIOR |
3590 R92C_SYS_ISO_CTRL_PWC_EV12V) >> 8);
3591
3592 /*
3593 * Disable analog sequence
3594 */
3595 /* Disable A15 power */
3596 urtwn_write_1(sc, R92C_LDOA15_CTRL, R92C_LDOA15_CTRL_OBUF);
3597 /* Disable digital core power */
3598 urtwn_write_1(sc, R92C_LDOV12D_CTRL,
3599 urtwn_read_1(sc, R92C_LDOV12D_CTRL) &
3600 ~R92C_LDOV12D_CTRL_LDV12_EN);
3601
3602 /* Enter PFM mode */
3603 urtwn_write_1(sc, R92C_SPS0_CTRL, 0x23);
3604
3605 /* Set USB suspend */
3606 urtwn_write_2(sc, R92C_APS_FSMCO,
3607 R92C_APS_FSMCO_APDM_HOST |
3608 R92C_APS_FSMCO_AFSM_HSUS |
3609 R92C_APS_FSMCO_PFM_ALDN);
3610
3611 /* Lock ISO/CLK/Power control register. */
3612 urtwn_write_1(sc, R92C_RSV_CTRL, 0x0E);
3613}
3614
3615static void
3616urtwn_r88e_power_off(struct urtwn_softc *sc)
3617{
3618 uint8_t reg;
3619 int ntries;
3620
3621 /* Disable any kind of TX reports. */
3622 urtwn_write_1(sc, R88E_TX_RPT_CTRL,
3623 urtwn_read_1(sc, R88E_TX_RPT_CTRL) &
3624 ~(R88E_TX_RPT1_ENA | R88E_TX_RPT2_ENA));
3625
3626 /* Stop Rx. */
3627 urtwn_write_1(sc, R92C_CR, 0);
3628
3629 /* Move card to Low Power State. */
3630 /* Block all Tx queues. */
3631 urtwn_write_1(sc, R92C_TXPAUSE, R92C_TX_QUEUE_ALL);
3632
3633 for (ntries = 0; ntries < 20; ntries++) {
3634 /* Should be zero if no packet is transmitting. */
3635 if (urtwn_read_4(sc, R88E_SCH_TXCMD) == 0)
3636 break;
3637
3638 urtwn_ms_delay(sc);
3639 }
3640 if (ntries == 20) {
3641 device_printf(sc->sc_dev, "%s: failed to block Tx queues\n",
3642 __func__);
3643 return;
3644 }
3645
3646 /* CCK and OFDM are disabled, and clock are gated. */
3647 urtwn_write_1(sc, R92C_SYS_FUNC_EN,
3648 urtwn_read_1(sc, R92C_SYS_FUNC_EN) & ~R92C_SYS_FUNC_EN_BBRSTB);
3649
3650 urtwn_ms_delay(sc);
3651
3652 /* Reset MAC TRX */
3653 urtwn_write_1(sc, R92C_CR,
3654 R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN |
3655 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN |
3656 R92C_CR_PROTOCOL_EN | R92C_CR_SCHEDULE_EN);
3657
3658 /* check if removed later */
3659 urtwn_write_1(sc, R92C_CR + 1,
3660 urtwn_read_1(sc, R92C_CR + 1) & ~(R92C_CR_ENSEC >> 8));
3661
3662 /* Respond TxOK to scheduler */
3663 urtwn_write_1(sc, R92C_DUAL_TSF_RST,
3664 urtwn_read_1(sc, R92C_DUAL_TSF_RST) | 0x20);
3665
3666 /* If firmware in ram code, do reset. */
3667#ifndef URTWN_WITHOUT_UCODE
3668 if (urtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RDY)
3669 urtwn_r88e_fw_reset(sc);
3670#endif
3671
3672 /* Reset MCU ready status. */
3673 urtwn_write_1(sc, R92C_MCUFWDL, 0x00);
3674
3675 /* Disable 32k. */
3676 urtwn_write_1(sc, R88E_32K_CTRL,
3677 urtwn_read_1(sc, R88E_32K_CTRL) & ~0x01);
3678
3679 /* Move card to Disabled state. */
3680 /* Turn off RF. */
3681 urtwn_write_1(sc, R92C_RF_CTRL, 0);
3682
3683 /* LDO Sleep mode. */
3684 urtwn_write_1(sc, R92C_LPLDO_CTRL,
3685 urtwn_read_1(sc, R92C_LPLDO_CTRL) | R92C_LPLDO_CTRL_SLEEP);
3686
3687 /* Turn off MAC by HW state machine */
3688 urtwn_write_1(sc, R92C_APS_FSMCO + 1,
3689 urtwn_read_1(sc, R92C_APS_FSMCO + 1) |
3690 (R92C_APS_FSMCO_APFM_OFF >> 8));
3691
3692 for (ntries = 0; ntries < 20; ntries++) {
3693 /* Wait until it will be disabled. */
3694 if ((urtwn_read_1(sc, R92C_APS_FSMCO + 1) &
3695 (R92C_APS_FSMCO_APFM_OFF >> 8)) == 0)
3696 break;
3697
3698 urtwn_ms_delay(sc);
3699 }
3700 if (ntries == 20) {
3701 device_printf(sc->sc_dev, "%s: could not turn off MAC\n",
3702 __func__);
3703 return;
3704 }
3705
3706 /* schmit trigger */
3707 urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 2,
3708 urtwn_read_1(sc, R92C_AFE_XTAL_CTRL + 2) | 0x80);
3709
3710 /* Enable WL suspend. */
3711 urtwn_write_1(sc, R92C_APS_FSMCO + 1,
3712 (urtwn_read_1(sc, R92C_APS_FSMCO + 1) & ~0x10) | 0x08);
3713
3714 /* Enable bandgap mbias in suspend. */
3715 urtwn_write_1(sc, R92C_APS_FSMCO + 3, 0);
3716
3717 /* Clear SIC_EN register. */
3718 urtwn_write_1(sc, R92C_GPIO_MUXCFG + 1,
3719 urtwn_read_1(sc, R92C_GPIO_MUXCFG + 1) & ~0x10);
3720
3721 /* Set USB suspend enable local register */
3722 urtwn_write_1(sc, R92C_USB_SUSPEND,
3723 urtwn_read_1(sc, R92C_USB_SUSPEND) | 0x10);
3724
3725 /* Reset MCU IO Wrapper. */
3726 reg = urtwn_read_1(sc, R92C_RSV_CTRL + 1);
3727 urtwn_write_1(sc, R92C_RSV_CTRL + 1, reg & ~0x08);
3728 urtwn_write_1(sc, R92C_RSV_CTRL + 1, reg | 0x08);
3729
3730 /* marked as 'For Power Consumption' code. */
3731 urtwn_write_1(sc, R92C_GPIO_OUT, urtwn_read_1(sc, R92C_GPIO_IN));
3732 urtwn_write_1(sc, R92C_GPIO_IOSEL, 0xff);
3733
3734 urtwn_write_1(sc, R92C_GPIO_IO_SEL,
3735 urtwn_read_1(sc, R92C_GPIO_IO_SEL) << 4);
3736 urtwn_write_1(sc, R92C_GPIO_MOD,
3737 urtwn_read_1(sc, R92C_GPIO_MOD) | 0x0f);
3738
3739 /* Set LNA, TRSW, EX_PA Pin to output mode. */
3740 urtwn_write_4(sc, R88E_BB_PAD_CTRL, 0x00080808);
3741}
3742
3743static int
3744urtwn_llt_init(struct urtwn_softc *sc)
3745{
3746 int i, error, page_count, pktbuf_count;
3747
3748 page_count = (sc->chip & URTWN_CHIP_88E) ?
3749 R88E_TX_PAGE_COUNT : R92C_TX_PAGE_COUNT;
3750 pktbuf_count = (sc->chip & URTWN_CHIP_88E) ?
3751 R88E_TXPKTBUF_COUNT : R92C_TXPKTBUF_COUNT;
3752
3753 /* Reserve pages [0; page_count]. */
3754 for (i = 0; i < page_count; i++) {
3755 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0)
3756 return (error);
3757 }
3758 /* NB: 0xff indicates end-of-list. */
3759 if ((error = urtwn_llt_write(sc, i, 0xff)) != 0)
3760 return (error);
3761 /*
3762 * Use pages [page_count + 1; pktbuf_count - 1]
3763 * as ring buffer.
3764 */
3765 for (++i; i < pktbuf_count - 1; i++) {
3766 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0)
3767 return (error);
3768 }
3769 /* Make the last page point to the beginning of the ring buffer. */
3770 error = urtwn_llt_write(sc, i, page_count + 1);
3771 return (error);
3772}
3773
3774#ifndef URTWN_WITHOUT_UCODE
3775static void
3776urtwn_fw_reset(struct urtwn_softc *sc)
3777{
3778 uint16_t reg;
3779 int ntries;
3780
3781 /* Tell 8051 to reset itself. */
3782 urtwn_write_1(sc, R92C_HMETFR + 3, 0x20);
3783
3784 /* Wait until 8051 resets by itself. */
3785 for (ntries = 0; ntries < 100; ntries++) {
3786 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN);
3787 if (!(reg & R92C_SYS_FUNC_EN_CPUEN))
3788 return;
3789 urtwn_ms_delay(sc);
3790 }
3791 /* Force 8051 reset. */
3792 urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg & ~R92C_SYS_FUNC_EN_CPUEN);
3793}
3794
3795static void
3796urtwn_r88e_fw_reset(struct urtwn_softc *sc)
3797{
3798 uint16_t reg;
3799
3800 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN);
3801 urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg & ~R92C_SYS_FUNC_EN_CPUEN);
3802 urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg | R92C_SYS_FUNC_EN_CPUEN);
3803}
3804
3805static int
3806urtwn_fw_loadpage(struct urtwn_softc *sc, int page, const uint8_t *buf, int len)
3807{
3808 uint32_t reg;
3809 usb_error_t error = USB_ERR_NORMAL_COMPLETION;
3810 int off, mlen;
3811
3812 reg = urtwn_read_4(sc, R92C_MCUFWDL);
3813 reg = RW(reg, R92C_MCUFWDL_PAGE, page);
3814 urtwn_write_4(sc, R92C_MCUFWDL, reg);
3815
3816 off = R92C_FW_START_ADDR;
3817 while (len > 0) {
3818 if (len > 196)
3819 mlen = 196;
3820 else if (len > 4)
3821 mlen = 4;
3822 else
3823 mlen = 1;
3824 /* XXX fix this deconst */
3825 error = urtwn_write_region_1(sc, off,
3826 __DECONST(uint8_t *, buf), mlen);
3827 if (error != USB_ERR_NORMAL_COMPLETION)
3828 break;
3829 off += mlen;
3830 buf += mlen;
3831 len -= mlen;
3832 }
3833 return (error);
3834}
3835
3836static int
3837urtwn_load_firmware(struct urtwn_softc *sc)
3838{
3839 const struct firmware *fw;
3840 const struct r92c_fw_hdr *hdr;
3841 const char *imagename;
3842 const u_char *ptr;
3843 size_t len;
3844 uint32_t reg;
3845 int mlen, ntries, page, error;
3846
3847 URTWN_UNLOCK(sc);
3848 /* Read firmware image from the filesystem. */
3849 if (sc->chip & URTWN_CHIP_88E)
3850 imagename = "urtwn-rtl8188eufw";
3851 else if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) ==
3852 URTWN_CHIP_UMC_A_CUT)
3853 imagename = "urtwn-rtl8192cfwU";
3854 else
3855 imagename = "urtwn-rtl8192cfwT";
3856
3857 fw = firmware_get(imagename);
3858 URTWN_LOCK(sc);
3859 if (fw == NULL) {
3860 device_printf(sc->sc_dev,
3861 "failed loadfirmware of file %s\n", imagename);
3862 return (ENOENT);
3863 }
3864
3865 len = fw->datasize;
3866
3867 if (len < sizeof(*hdr)) {
3868 device_printf(sc->sc_dev, "firmware too short\n");
3869 error = EINVAL;
3870 goto fail;
3871 }
3872 ptr = fw->data;
3873 hdr = (const struct r92c_fw_hdr *)ptr;
3874 /* Check if there is a valid FW header and skip it. */
3875 if ((le16toh(hdr->signature) >> 4) == 0x88c ||
3876 (le16toh(hdr->signature) >> 4) == 0x88e ||
3877 (le16toh(hdr->signature) >> 4) == 0x92c) {
3878 URTWN_DPRINTF(sc, URTWN_DEBUG_FIRMWARE,
3879 "FW V%d.%d %02d-%02d %02d:%02d\n",
3880 le16toh(hdr->version), le16toh(hdr->subversion),
3881 hdr->month, hdr->date, hdr->hour, hdr->minute);
3882 ptr += sizeof(*hdr);
3883 len -= sizeof(*hdr);
3884 }
3885
3886 if (urtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RAM_DL_SEL) {
3887 if (sc->chip & URTWN_CHIP_88E)
3888 urtwn_r88e_fw_reset(sc);
3889 else
3890 urtwn_fw_reset(sc);
3891 urtwn_write_1(sc, R92C_MCUFWDL, 0);
3892 }
3893
3894 if (!(sc->chip & URTWN_CHIP_88E)) {
3895 urtwn_write_2(sc, R92C_SYS_FUNC_EN,
3896 urtwn_read_2(sc, R92C_SYS_FUNC_EN) |
3897 R92C_SYS_FUNC_EN_CPUEN);
3898 }
3899 urtwn_write_1(sc, R92C_MCUFWDL,
3900 urtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_EN);
3901 urtwn_write_1(sc, R92C_MCUFWDL + 2,
3902 urtwn_read_1(sc, R92C_MCUFWDL + 2) & ~0x08);
3903
3904 /* Reset the FWDL checksum. */
3905 urtwn_write_1(sc, R92C_MCUFWDL,
3906 urtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_CHKSUM_RPT);
3907
3908 for (page = 0; len > 0; page++) {
3909 mlen = min(len, R92C_FW_PAGE_SIZE);
3910 error = urtwn_fw_loadpage(sc, page, ptr, mlen);
3911 if (error != 0) {
3912 device_printf(sc->sc_dev,
3913 "could not load firmware page\n");
3914 goto fail;
3915 }
3916 ptr += mlen;
3917 len -= mlen;
3918 }
3919 urtwn_write_1(sc, R92C_MCUFWDL,
3920 urtwn_read_1(sc, R92C_MCUFWDL) & ~R92C_MCUFWDL_EN);
3921 urtwn_write_1(sc, R92C_MCUFWDL + 1, 0);
3922
3923 /* Wait for checksum report. */
3924 for (ntries = 0; ntries < 1000; ntries++) {
3925 if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_CHKSUM_RPT)
3926 break;
3927 urtwn_ms_delay(sc);
3928 }
3929 if (ntries == 1000) {
3930 device_printf(sc->sc_dev,
3931 "timeout waiting for checksum report\n");
3932 error = ETIMEDOUT;
3933 goto fail;
3934 }
3935
3936 reg = urtwn_read_4(sc, R92C_MCUFWDL);
3937 reg = (reg & ~R92C_MCUFWDL_WINTINI_RDY) | R92C_MCUFWDL_RDY;
3938 urtwn_write_4(sc, R92C_MCUFWDL, reg);
3939 if (sc->chip & URTWN_CHIP_88E)
3940 urtwn_r88e_fw_reset(sc);
3941 /* Wait for firmware readiness. */
3942 for (ntries = 0; ntries < 1000; ntries++) {
3943 if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_WINTINI_RDY)
3944 break;
3945 urtwn_ms_delay(sc);
3946 }
3947 if (ntries == 1000) {
3948 device_printf(sc->sc_dev,
3949 "timeout waiting for firmware readiness\n");
3950 error = ETIMEDOUT;
3951 goto fail;
3952 }
3953fail:
3954 firmware_put(fw, FIRMWARE_UNLOAD);
3955 return (error);
3956}
3957#endif
3958
3959static int
3960urtwn_dma_init(struct urtwn_softc *sc)
3961{
3962 struct usb_endpoint *ep, *ep_end;
3963 usb_error_t usb_err;
3964 uint32_t reg;
3965 int hashq, hasnq, haslq, nqueues, ntx;
3966 int error, pagecount, npubqpages, nqpages, nrempages, tx_boundary;
3967
3968 /* Initialize LLT table. */
3969 error = urtwn_llt_init(sc);
3970 if (error != 0)
3971 return (error);
3972
3973 /* Determine the number of bulk-out pipes. */
3974 ntx = 0;
3975 ep = sc->sc_udev->endpoints;
3976 ep_end = sc->sc_udev->endpoints + sc->sc_udev->endpoints_max;
3977 for (; ep != ep_end; ep++) {
3978 if ((ep->edesc == NULL) ||
3979 (ep->iface_index != sc->sc_iface_index))
3980 continue;
3981 if (UE_GET_DIR(ep->edesc->bEndpointAddress) == UE_DIR_OUT)
3982 ntx++;
3983 }
3984 if (ntx == 0) {
3985 device_printf(sc->sc_dev,
3986 "%d: invalid number of Tx bulk pipes\n", ntx);
3987 return (EIO);
3988 }
3989
3990 /* Get Tx queues to USB endpoints mapping. */
3991 hashq = hasnq = haslq = nqueues = 0;
3992 switch (ntx) {
3993 case 1: hashq = 1; break;
3994 case 2: hashq = hasnq = 1; break;
3995 case 3: case 4: hashq = hasnq = haslq = 1; break;
3996 }
3997 nqueues = hashq + hasnq + haslq;
3998 if (nqueues == 0)
3999 return (EIO);
4000
4001 npubqpages = nqpages = nrempages = pagecount = 0;
4002 if (sc->chip & URTWN_CHIP_88E)
4003 tx_boundary = R88E_TX_PAGE_BOUNDARY;
4004 else {
4005 pagecount = R92C_TX_PAGE_COUNT;
4006 npubqpages = R92C_PUBQ_NPAGES;
4007 tx_boundary = R92C_TX_PAGE_BOUNDARY;
4008 }
4009
4010 /* Set number of pages for normal priority queue. */
4011 if (sc->chip & URTWN_CHIP_88E) {
4012 usb_err = urtwn_write_2(sc, R92C_RQPN_NPQ, 0xd);
4013 if (usb_err != USB_ERR_NORMAL_COMPLETION)
4014 return (EIO);
4015 usb_err = urtwn_write_4(sc, R92C_RQPN, 0x808e000d);
4016 if (usb_err != USB_ERR_NORMAL_COMPLETION)
4017 return (EIO);
4018 } else {
4019 /* Get the number of pages for each queue. */
4020 nqpages = (pagecount - npubqpages) / nqueues;
4021 /*
4022 * The remaining pages are assigned to the high priority
4023 * queue.
4024 */
4025 nrempages = (pagecount - npubqpages) % nqueues;
4026 usb_err = urtwn_write_1(sc, R92C_RQPN_NPQ, hasnq ? nqpages : 0);
4027 if (usb_err != USB_ERR_NORMAL_COMPLETION)
4028 return (EIO);
4029 usb_err = urtwn_write_4(sc, R92C_RQPN,
4030 /* Set number of pages for public queue. */
4031 SM(R92C_RQPN_PUBQ, npubqpages) |
4032 /* Set number of pages for high priority queue. */
4033 SM(R92C_RQPN_HPQ, hashq ? nqpages + nrempages : 0) |
4034 /* Set number of pages for low priority queue. */
4035 SM(R92C_RQPN_LPQ, haslq ? nqpages : 0) |
4036 /* Load values. */
4037 R92C_RQPN_LD);
4038 if (usb_err != USB_ERR_NORMAL_COMPLETION)
4039 return (EIO);
4040 }
4041
4042 usb_err = urtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, tx_boundary);
4043 if (usb_err != USB_ERR_NORMAL_COMPLETION)
4044 return (EIO);
4045 usb_err = urtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, tx_boundary);
4046 if (usb_err != USB_ERR_NORMAL_COMPLETION)
4047 return (EIO);
4048 usb_err = urtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, tx_boundary);
4049 if (usb_err != USB_ERR_NORMAL_COMPLETION)
4050 return (EIO);
4051 usb_err = urtwn_write_1(sc, R92C_TRXFF_BNDY, tx_boundary);
4052 if (usb_err != USB_ERR_NORMAL_COMPLETION)
4053 return (EIO);
4054 usb_err = urtwn_write_1(sc, R92C_TDECTRL + 1, tx_boundary);
4055 if (usb_err != USB_ERR_NORMAL_COMPLETION)
4056 return (EIO);
4057
4058 /* Set queue to USB pipe mapping. */
4059 reg = urtwn_read_2(sc, R92C_TRXDMA_CTRL);
4060 reg &= ~R92C_TRXDMA_CTRL_QMAP_M;
4061 if (nqueues == 1) {
4062 if (hashq)
4063 reg |= R92C_TRXDMA_CTRL_QMAP_HQ;
4064 else if (hasnq)
4065 reg |= R92C_TRXDMA_CTRL_QMAP_NQ;
4066 else
4067 reg |= R92C_TRXDMA_CTRL_QMAP_LQ;
4068 } else if (nqueues == 2) {
4069 /*
4070 * All 2-endpoints configs have high and normal
4071 * priority queues.
4072 */
4073 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_NQ;
4074 } else
4075 reg |= R92C_TRXDMA_CTRL_QMAP_3EP;
4076 usb_err = urtwn_write_2(sc, R92C_TRXDMA_CTRL, reg);
4077 if (usb_err != USB_ERR_NORMAL_COMPLETION)
4078 return (EIO);
4079
4080 /* Set Tx/Rx transfer page boundary. */
4081 usb_err = urtwn_write_2(sc, R92C_TRXFF_BNDY + 2,
4082 (sc->chip & URTWN_CHIP_88E) ? 0x23ff : 0x27ff);
4083 if (usb_err != USB_ERR_NORMAL_COMPLETION)
4084 return (EIO);
4085
4086 /* Set Tx/Rx transfer page size. */
4087 usb_err = urtwn_write_1(sc, R92C_PBP,
4088 SM(R92C_PBP_PSRX, R92C_PBP_128) |
4089 SM(R92C_PBP_PSTX, R92C_PBP_128));
4090 if (usb_err != USB_ERR_NORMAL_COMPLETION)
4091 return (EIO);
4092
4093 return (0);
4094}
4095
4096static int
4097urtwn_mac_init(struct urtwn_softc *sc)
4098{
4099 usb_error_t error;
4100 int i;
4101
4102 /* Write MAC initialization values. */
4103 if (sc->chip & URTWN_CHIP_88E) {
4104 for (i = 0; i < nitems(rtl8188eu_mac); i++) {
4105 error = urtwn_write_1(sc, rtl8188eu_mac[i].reg,
4106 rtl8188eu_mac[i].val);
4107 if (error != USB_ERR_NORMAL_COMPLETION)
4108 return (EIO);
4109 }
4110 urtwn_write_1(sc, R92C_MAX_AGGR_NUM, 0x07);
4111 } else {
4112 for (i = 0; i < nitems(rtl8192cu_mac); i++)
4113 error = urtwn_write_1(sc, rtl8192cu_mac[i].reg,
4114 rtl8192cu_mac[i].val);
4115 if (error != USB_ERR_NORMAL_COMPLETION)
4116 return (EIO);
4117 }
4118
4119 return (0);
4120}
4121
4122static void
4123urtwn_bb_init(struct urtwn_softc *sc)
4124{
4125 const struct urtwn_bb_prog *prog;
4126 uint32_t reg;
4127 uint8_t crystalcap;
4128 int i;
4129
4130 /* Enable BB and RF. */
4131 urtwn_write_2(sc, R92C_SYS_FUNC_EN,
4132 urtwn_read_2(sc, R92C_SYS_FUNC_EN) |
4133 R92C_SYS_FUNC_EN_BBRSTB | R92C_SYS_FUNC_EN_BB_GLB_RST |
4134 R92C_SYS_FUNC_EN_DIO_RF);
4135
4136 if (!(sc->chip & URTWN_CHIP_88E))
4137 urtwn_write_2(sc, R92C_AFE_PLL_CTRL, 0xdb83);
4138
4139 urtwn_write_1(sc, R92C_RF_CTRL,
4140 R92C_RF_CTRL_EN | R92C_RF_CTRL_RSTB | R92C_RF_CTRL_SDMRSTB);
4141 urtwn_write_1(sc, R92C_SYS_FUNC_EN,
4142 R92C_SYS_FUNC_EN_USBA | R92C_SYS_FUNC_EN_USBD |
4143 R92C_SYS_FUNC_EN_BB_GLB_RST | R92C_SYS_FUNC_EN_BBRSTB);
4144
4145 if (!(sc->chip & URTWN_CHIP_88E)) {
4146 urtwn_write_1(sc, R92C_LDOHCI12_CTRL, 0x0f);
4147 urtwn_write_1(sc, 0x15, 0xe9);
4148 urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 1, 0x80);
4149 }
4150
4151 /* Select BB programming based on board type. */
4152 if (sc->chip & URTWN_CHIP_88E)
4153 prog = &rtl8188eu_bb_prog;
4154 else if (!(sc->chip & URTWN_CHIP_92C)) {
4155 if (sc->board_type == R92C_BOARD_TYPE_MINICARD)
4156 prog = &rtl8188ce_bb_prog;
4157 else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA)
4158 prog = &rtl8188ru_bb_prog;
4159 else
4160 prog = &rtl8188cu_bb_prog;
4161 } else {
4162 if (sc->board_type == R92C_BOARD_TYPE_MINICARD)
4163 prog = &rtl8192ce_bb_prog;
4164 else
4165 prog = &rtl8192cu_bb_prog;
4166 }
4167 /* Write BB initialization values. */
4168 for (i = 0; i < prog->count; i++) {
4169 urtwn_bb_write(sc, prog->regs[i], prog->vals[i]);
4170 urtwn_ms_delay(sc);
4171 }
4172
4173 if (sc->chip & URTWN_CHIP_92C_1T2R) {
4174 /* 8192C 1T only configuration. */
4175 reg = urtwn_bb_read(sc, R92C_FPGA0_TXINFO);
4176 reg = (reg & ~0x00000003) | 0x2;
4177 urtwn_bb_write(sc, R92C_FPGA0_TXINFO, reg);
4178
4179 reg = urtwn_bb_read(sc, R92C_FPGA1_TXINFO);
4180 reg = (reg & ~0x00300033) | 0x00200022;
4181 urtwn_bb_write(sc, R92C_FPGA1_TXINFO, reg);
4182
4183 reg = urtwn_bb_read(sc, R92C_CCK0_AFESETTING);
4184 reg = (reg & ~0xff000000) | 0x45 << 24;
4185 urtwn_bb_write(sc, R92C_CCK0_AFESETTING, reg);
4186
4187 reg = urtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA);
4188 reg = (reg & ~0x000000ff) | 0x23;
4189 urtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, reg);
4190
4191 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCPARAM1);
4192 reg = (reg & ~0x00000030) | 1 << 4;
4193 urtwn_bb_write(sc, R92C_OFDM0_AGCPARAM1, reg);
4194
4195 reg = urtwn_bb_read(sc, 0xe74);
4196 reg = (reg & ~0x0c000000) | 2 << 26;
4197 urtwn_bb_write(sc, 0xe74, reg);
4198 reg = urtwn_bb_read(sc, 0xe78);
4199 reg = (reg & ~0x0c000000) | 2 << 26;
4200 urtwn_bb_write(sc, 0xe78, reg);
4201 reg = urtwn_bb_read(sc, 0xe7c);
4202 reg = (reg & ~0x0c000000) | 2 << 26;
4203 urtwn_bb_write(sc, 0xe7c, reg);
4204 reg = urtwn_bb_read(sc, 0xe80);
4205 reg = (reg & ~0x0c000000) | 2 << 26;
4206 urtwn_bb_write(sc, 0xe80, reg);
4207 reg = urtwn_bb_read(sc, 0xe88);
4208 reg = (reg & ~0x0c000000) | 2 << 26;
4209 urtwn_bb_write(sc, 0xe88, reg);
4210 }
4211
4212 /* Write AGC values. */
4213 for (i = 0; i < prog->agccount; i++) {
4214 urtwn_bb_write(sc, R92C_OFDM0_AGCRSSITABLE,
4215 prog->agcvals[i]);
4216 urtwn_ms_delay(sc);
4217 }
4218
4219 if (sc->chip & URTWN_CHIP_88E) {
4220 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553422);
4221 urtwn_ms_delay(sc);
4222 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553420);
4223 urtwn_ms_delay(sc);
4224
4225 crystalcap = sc->rom.r88e_rom.crystalcap;
4226 if (crystalcap == 0xff)
4227 crystalcap = 0x20;
4228 crystalcap &= 0x3f;
4229 reg = urtwn_bb_read(sc, R92C_AFE_XTAL_CTRL);
4230 urtwn_bb_write(sc, R92C_AFE_XTAL_CTRL,
4231 RW(reg, R92C_AFE_XTAL_CTRL_ADDR,
4232 crystalcap | crystalcap << 6));
4233 } else {
4234 if (urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)) &
4235 R92C_HSSI_PARAM2_CCK_HIPWR)
4236 sc->sc_flags |= URTWN_FLAG_CCK_HIPWR;
4237 }
4238}
4239
4240static void
4241urtwn_rf_init(struct urtwn_softc *sc)
4242{
4243 const struct urtwn_rf_prog *prog;
4244 uint32_t reg, type;
4245 int i, j, idx, off;
4246
4247 /* Select RF programming based on board type. */
4248 if (sc->chip & URTWN_CHIP_88E)
4249 prog = rtl8188eu_rf_prog;
4250 else if (!(sc->chip & URTWN_CHIP_92C)) {
4251 if (sc->board_type == R92C_BOARD_TYPE_MINICARD)
4252 prog = rtl8188ce_rf_prog;
4253 else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA)
4254 prog = rtl8188ru_rf_prog;
4255 else
4256 prog = rtl8188cu_rf_prog;
4257 } else
4258 prog = rtl8192ce_rf_prog;
4259
4260 for (i = 0; i < sc->nrxchains; i++) {
4261 /* Save RF_ENV control type. */
4262 idx = i / 2;
4263 off = (i % 2) * 16;
4264 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx));
4265 type = (reg >> off) & 0x10;
4266
4267 /* Set RF_ENV enable. */
4268 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i));
4269 reg |= 0x100000;
4270 urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg);
4271 urtwn_ms_delay(sc);
4272 /* Set RF_ENV output high. */
4273 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i));
4274 reg |= 0x10;
4275 urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg);
4276 urtwn_ms_delay(sc);
4277 /* Set address and data lengths of RF registers. */
4278 reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i));
4279 reg &= ~R92C_HSSI_PARAM2_ADDR_LENGTH;
4280 urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg);
4281 urtwn_ms_delay(sc);
4282 reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i));
4283 reg &= ~R92C_HSSI_PARAM2_DATA_LENGTH;
4284 urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg);
4285 urtwn_ms_delay(sc);
4286
4287 /* Write RF initialization values for this chain. */
4288 for (j = 0; j < prog[i].count; j++) {
4289 if (prog[i].regs[j] >= 0xf9 &&
4290 prog[i].regs[j] <= 0xfe) {
4291 /*
4292 * These are fake RF registers offsets that
4293 * indicate a delay is required.
4294 */
4295 usb_pause_mtx(&sc->sc_mtx, hz / 20); /* 50ms */
4296 continue;
4297 }
4298 urtwn_rf_write(sc, i, prog[i].regs[j],
4299 prog[i].vals[j]);
4300 urtwn_ms_delay(sc);
4301 }
4302
4303 /* Restore RF_ENV control type. */
4304 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx));
4305 reg &= ~(0x10 << off) | (type << off);
4306 urtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(idx), reg);
4307
4308 /* Cache RF register CHNLBW. */
4309 sc->rf_chnlbw[i] = urtwn_rf_read(sc, i, R92C_RF_CHNLBW);
4310 }
4311
4312 if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) ==
4313 URTWN_CHIP_UMC_A_CUT) {
4314 urtwn_rf_write(sc, 0, R92C_RF_RX_G1, 0x30255);
4315 urtwn_rf_write(sc, 0, R92C_RF_RX_G2, 0x50a00);
4316 }
4317}
4318
4319static void
4320urtwn_cam_init(struct urtwn_softc *sc)
4321{
4322 /* Invalidate all CAM entries. */
4323 urtwn_write_4(sc, R92C_CAMCMD,
4324 R92C_CAMCMD_POLLING | R92C_CAMCMD_CLR);
4325}
4326
4327static int
4328urtwn_cam_write(struct urtwn_softc *sc, uint32_t addr, uint32_t data)
4329{
4330 usb_error_t error;
4331
4332 error = urtwn_write_4(sc, R92C_CAMWRITE, data);
4333 if (error != USB_ERR_NORMAL_COMPLETION)
4334 return (EIO);
4335 error = urtwn_write_4(sc, R92C_CAMCMD,
4336 R92C_CAMCMD_POLLING | R92C_CAMCMD_WRITE |
4337 SM(R92C_CAMCMD_ADDR, addr));
4338 if (error != USB_ERR_NORMAL_COMPLETION)
4339 return (EIO);
4340
4341 return (0);
4342}
4343
4344static void
4345urtwn_pa_bias_init(struct urtwn_softc *sc)
4346{
4347 uint8_t reg;
4348 int i;
4349
4350 for (i = 0; i < sc->nrxchains; i++) {
4351 if (sc->pa_setting & (1 << i))
4352 continue;
4353 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x0f406);
4354 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x4f406);
4355 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x8f406);
4356 urtwn_rf_write(sc, i, R92C_RF_IPA, 0xcf406);
4357 }
4358 if (!(sc->pa_setting & 0x10)) {
4359 reg = urtwn_read_1(sc, 0x16);
4360 reg = (reg & ~0xf0) | 0x90;
4361 urtwn_write_1(sc, 0x16, reg);
4362 }
4363}
4364
4365static void
4366urtwn_rxfilter_init(struct urtwn_softc *sc)
4367{
4368 struct ieee80211com *ic = &sc->sc_ic;
4369 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps);
4370 uint32_t rcr;
4371 uint16_t filter;
4372
4373 URTWN_ASSERT_LOCKED(sc);
4374
4375 /* Setup multicast filter. */
4376 urtwn_set_multi(sc);
4377
4378 /* Filter for management frames. */
4379 filter = 0x7f3f;
4380 switch (vap->iv_opmode) {
4381 case IEEE80211_M_STA:
4382 filter &= ~(
4383 R92C_RXFLTMAP_SUBTYPE(IEEE80211_FC0_SUBTYPE_ASSOC_REQ) |
4384 R92C_RXFLTMAP_SUBTYPE(IEEE80211_FC0_SUBTYPE_REASSOC_REQ) |
4385 R92C_RXFLTMAP_SUBTYPE(IEEE80211_FC0_SUBTYPE_PROBE_REQ));
4386 break;
4387 case IEEE80211_M_HOSTAP:
4388 filter &= ~(
4389 R92C_RXFLTMAP_SUBTYPE(IEEE80211_FC0_SUBTYPE_ASSOC_RESP) |
4390 R92C_RXFLTMAP_SUBTYPE(IEEE80211_FC0_SUBTYPE_REASSOC_RESP));
4391 break;
4392 case IEEE80211_M_MONITOR:
4393 case IEEE80211_M_IBSS:
4394 break;
4395 default:
4396 device_printf(sc->sc_dev, "%s: undefined opmode %d\n",
4397 __func__, vap->iv_opmode);
4398 break;
4399 }
4400 urtwn_write_2(sc, R92C_RXFLTMAP0, filter);
4401
4402 /* Reject all control frames. */
4403 urtwn_write_2(sc, R92C_RXFLTMAP1, 0x0000);
4404
4405 /* Reject all data frames. */
4406 urtwn_write_2(sc, R92C_RXFLTMAP2, 0x0000);
4407
4408 rcr = R92C_RCR_AM | R92C_RCR_AB | R92C_RCR_APM |
4409 R92C_RCR_HTC_LOC_CTRL | R92C_RCR_APP_PHYSTS |
4410 R92C_RCR_APP_ICV | R92C_RCR_APP_MIC;
4411
4412 if (vap->iv_opmode == IEEE80211_M_MONITOR) {
4413 /* Accept all frames. */
4414 rcr |= R92C_RCR_ACF | R92C_RCR_ADF | R92C_RCR_AMF |
4415 R92C_RCR_AAP;
4416 }
4417
4418 /* Set Rx filter. */
4419 urtwn_write_4(sc, R92C_RCR, rcr);
4420
4421 if (ic->ic_promisc != 0) {
4422 /* Update Rx filter. */
4423 urtwn_set_promisc(sc);
4424 }
4425}
4426
4427static void
4428urtwn_edca_init(struct urtwn_softc *sc)
4429{
4430 urtwn_write_2(sc, R92C_SPEC_SIFS, 0x100a);
4431 urtwn_write_2(sc, R92C_MAC_SPEC_SIFS, 0x100a);
4432 urtwn_write_2(sc, R92C_SIFS_CCK, 0x100a);
4433 urtwn_write_2(sc, R92C_SIFS_OFDM, 0x100a);
4434 urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x005ea42b);
4435 urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a44f);
4436 urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005ea324);
4437 urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002fa226);
4438}
4439
4440static void
4441urtwn_write_txpower(struct urtwn_softc *sc, int chain,
4442 uint16_t power[URTWN_RIDX_COUNT])
4443{
4444 uint32_t reg;
4445
4446 /* Write per-CCK rate Tx power. */
4447 if (chain == 0) {
4448 reg = urtwn_bb_read(sc, R92C_TXAGC_A_CCK1_MCS32);
4449 reg = RW(reg, R92C_TXAGC_A_CCK1, power[0]);
4450 urtwn_bb_write(sc, R92C_TXAGC_A_CCK1_MCS32, reg);
4451 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11);
4452 reg = RW(reg, R92C_TXAGC_A_CCK2, power[1]);
4453 reg = RW(reg, R92C_TXAGC_A_CCK55, power[2]);
4454 reg = RW(reg, R92C_TXAGC_A_CCK11, power[3]);
4455 urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg);
4456 } else {
4457 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK1_55_MCS32);
4458 reg = RW(reg, R92C_TXAGC_B_CCK1, power[0]);
4459 reg = RW(reg, R92C_TXAGC_B_CCK2, power[1]);
4460 reg = RW(reg, R92C_TXAGC_B_CCK55, power[2]);
4461 urtwn_bb_write(sc, R92C_TXAGC_B_CCK1_55_MCS32, reg);
4462 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11);
4463 reg = RW(reg, R92C_TXAGC_B_CCK11, power[3]);
4464 urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg);
4465 }
4466 /* Write per-OFDM rate Tx power. */
4467 urtwn_bb_write(sc, R92C_TXAGC_RATE18_06(chain),
4468 SM(R92C_TXAGC_RATE06, power[ 4]) |
4469 SM(R92C_TXAGC_RATE09, power[ 5]) |
4470 SM(R92C_TXAGC_RATE12, power[ 6]) |
4471 SM(R92C_TXAGC_RATE18, power[ 7]));
4472 urtwn_bb_write(sc, R92C_TXAGC_RATE54_24(chain),
4473 SM(R92C_TXAGC_RATE24, power[ 8]) |
4474 SM(R92C_TXAGC_RATE36, power[ 9]) |
4475 SM(R92C_TXAGC_RATE48, power[10]) |
4476 SM(R92C_TXAGC_RATE54, power[11]));
4477 /* Write per-MCS Tx power. */
4478 urtwn_bb_write(sc, R92C_TXAGC_MCS03_MCS00(chain),
4479 SM(R92C_TXAGC_MCS00, power[12]) |
4480 SM(R92C_TXAGC_MCS01, power[13]) |
4481 SM(R92C_TXAGC_MCS02, power[14]) |
4482 SM(R92C_TXAGC_MCS03, power[15]));
4483 urtwn_bb_write(sc, R92C_TXAGC_MCS07_MCS04(chain),
4484 SM(R92C_TXAGC_MCS04, power[16]) |
4485 SM(R92C_TXAGC_MCS05, power[17]) |
4486 SM(R92C_TXAGC_MCS06, power[18]) |
4487 SM(R92C_TXAGC_MCS07, power[19]));
4488 urtwn_bb_write(sc, R92C_TXAGC_MCS11_MCS08(chain),
4489 SM(R92C_TXAGC_MCS08, power[20]) |
4490 SM(R92C_TXAGC_MCS09, power[21]) |
4491 SM(R92C_TXAGC_MCS10, power[22]) |
4492 SM(R92C_TXAGC_MCS11, power[23]));
4493 urtwn_bb_write(sc, R92C_TXAGC_MCS15_MCS12(chain),
4494 SM(R92C_TXAGC_MCS12, power[24]) |
4495 SM(R92C_TXAGC_MCS13, power[25]) |
4496 SM(R92C_TXAGC_MCS14, power[26]) |
4497 SM(R92C_TXAGC_MCS15, power[27]));
4498}
4499
4500static void
4501urtwn_get_txpower(struct urtwn_softc *sc, int chain,
4502 struct ieee80211_channel *c, struct ieee80211_channel *extc,
4503 uint16_t power[URTWN_RIDX_COUNT])
4504{
4505 struct ieee80211com *ic = &sc->sc_ic;
4506 struct r92c_rom *rom = &sc->rom.r92c_rom;
4507 uint16_t cckpow, ofdmpow, htpow, diff, max;
4508 const struct urtwn_txpwr *base;
4509 int ridx, chan, group;
4510
4511 /* Determine channel group. */
4512 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */
4513 if (chan <= 3)
4514 group = 0;
4515 else if (chan <= 9)
4516 group = 1;
4517 else
4518 group = 2;
4519
4520 /* Get original Tx power based on board type and RF chain. */
4521 if (!(sc->chip & URTWN_CHIP_92C)) {
4522 if (sc->board_type == R92C_BOARD_TYPE_HIGHPA)
4523 base = &rtl8188ru_txagc[chain];
4524 else
4525 base = &rtl8192cu_txagc[chain];
4526 } else
4527 base = &rtl8192cu_txagc[chain];
4528
4529 memset(power, 0, URTWN_RIDX_COUNT * sizeof(power[0]));
4530 if (sc->regulatory == 0) {
4531 for (ridx = URTWN_RIDX_CCK1; ridx <= URTWN_RIDX_CCK11; ridx++)
4532 power[ridx] = base->pwr[0][ridx];
4533 }
4534 for (ridx = URTWN_RIDX_OFDM6; ridx < URTWN_RIDX_COUNT; ridx++) {
4535 if (sc->regulatory == 3) {
4536 power[ridx] = base->pwr[0][ridx];
4537 /* Apply vendor limits. */
4538 if (extc != NULL)
4539 max = rom->ht40_max_pwr[group];
4540 else
4541 max = rom->ht20_max_pwr[group];
4542 max = (max >> (chain * 4)) & 0xf;
4543 if (power[ridx] > max)
4544 power[ridx] = max;
4545 } else if (sc->regulatory == 1) {
4546 if (extc == NULL)
4547 power[ridx] = base->pwr[group][ridx];
4548 } else if (sc->regulatory != 2)
4549 power[ridx] = base->pwr[0][ridx];
4550 }
4551
4552 /* Compute per-CCK rate Tx power. */
4553 cckpow = rom->cck_tx_pwr[chain][group];
4554 for (ridx = URTWN_RIDX_CCK1; ridx <= URTWN_RIDX_CCK11; ridx++) {
4555 power[ridx] += cckpow;
4556 if (power[ridx] > R92C_MAX_TX_PWR)
4557 power[ridx] = R92C_MAX_TX_PWR;
4558 }
4559
4560 htpow = rom->ht40_1s_tx_pwr[chain][group];
4561 if (sc->ntxchains > 1) {
4562 /* Apply reduction for 2 spatial streams. */
4563 diff = rom->ht40_2s_tx_pwr_diff[group];
4564 diff = (diff >> (chain * 4)) & 0xf;
4565 htpow = (htpow > diff) ? htpow - diff : 0;
4566 }
4567
4568 /* Compute per-OFDM rate Tx power. */
4569 diff = rom->ofdm_tx_pwr_diff[group];
4570 diff = (diff >> (chain * 4)) & 0xf;
4571 ofdmpow = htpow + diff; /* HT->OFDM correction. */
4572 for (ridx = URTWN_RIDX_OFDM6; ridx <= URTWN_RIDX_OFDM54; ridx++) {
4573 power[ridx] += ofdmpow;
4574 if (power[ridx] > R92C_MAX_TX_PWR)
4575 power[ridx] = R92C_MAX_TX_PWR;
4576 }
4577
4578 /* Compute per-MCS Tx power. */
4579 if (extc == NULL) {
4580 diff = rom->ht20_tx_pwr_diff[group];
4581 diff = (diff >> (chain * 4)) & 0xf;
4582 htpow += diff; /* HT40->HT20 correction. */
4583 }
4584 for (ridx = 12; ridx <= 27; ridx++) {
4585 power[ridx] += htpow;
4586 if (power[ridx] > R92C_MAX_TX_PWR)
4587 power[ridx] = R92C_MAX_TX_PWR;
4588 }
4589#ifdef USB_DEBUG
4590 if (sc->sc_debug & URTWN_DEBUG_TXPWR) {
4591 /* Dump per-rate Tx power values. */
4592 printf("Tx power for chain %d:\n", chain);
4593 for (ridx = URTWN_RIDX_CCK1; ridx < URTWN_RIDX_COUNT; ridx++)
4594 printf("Rate %d = %u\n", ridx, power[ridx]);
4595 }
4596#endif
4597}
4598
4599static void
4600urtwn_r88e_get_txpower(struct urtwn_softc *sc, int chain,
4601 struct ieee80211_channel *c, struct ieee80211_channel *extc,
4602 uint16_t power[URTWN_RIDX_COUNT])
4603{
4604 struct ieee80211com *ic = &sc->sc_ic;
4605 struct r88e_rom *rom = &sc->rom.r88e_rom;
4606 uint16_t cckpow, ofdmpow, bw20pow, htpow;
4607 const struct urtwn_r88e_txpwr *base;
4608 int ridx, chan, group;
4609
4610 /* Determine channel group. */
4611 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */
4612 if (chan <= 2)
4613 group = 0;
4614 else if (chan <= 5)
4615 group = 1;
4616 else if (chan <= 8)
4617 group = 2;
4618 else if (chan <= 11)
4619 group = 3;
4620 else if (chan <= 13)
4621 group = 4;
4622 else
4623 group = 5;
4624
4625 /* Get original Tx power based on board type and RF chain. */
4626 base = &rtl8188eu_txagc[chain];
4627
4628 memset(power, 0, URTWN_RIDX_COUNT * sizeof(power[0]));
4629 if (sc->regulatory == 0) {
4630 for (ridx = URTWN_RIDX_CCK1; ridx <= URTWN_RIDX_CCK11; ridx++)
4631 power[ridx] = base->pwr[0][ridx];
4632 }
4633 for (ridx = URTWN_RIDX_OFDM6; ridx < URTWN_RIDX_COUNT; ridx++) {
4634 if (sc->regulatory == 3)
4635 power[ridx] = base->pwr[0][ridx];
4636 else if (sc->regulatory == 1) {
4637 if (extc == NULL)
4638 power[ridx] = base->pwr[group][ridx];
4639 } else if (sc->regulatory != 2)
4640 power[ridx] = base->pwr[0][ridx];
4641 }
4642
4643 /* Compute per-CCK rate Tx power. */
4644 cckpow = rom->cck_tx_pwr[group];
4645 for (ridx = URTWN_RIDX_CCK1; ridx <= URTWN_RIDX_CCK11; ridx++) {
4646 power[ridx] += cckpow;
4647 if (power[ridx] > R92C_MAX_TX_PWR)
4648 power[ridx] = R92C_MAX_TX_PWR;
4649 }
4650
4651 htpow = rom->ht40_tx_pwr[group];
4652
4653 /* Compute per-OFDM rate Tx power. */
4654 ofdmpow = htpow + sc->ofdm_tx_pwr_diff;
4655 for (ridx = URTWN_RIDX_OFDM6; ridx <= URTWN_RIDX_OFDM54; ridx++) {
4656 power[ridx] += ofdmpow;
4657 if (power[ridx] > R92C_MAX_TX_PWR)
4658 power[ridx] = R92C_MAX_TX_PWR;
4659 }
4660
4661 bw20pow = htpow + sc->bw20_tx_pwr_diff;
4662 for (ridx = 12; ridx <= 27; ridx++) {
4663 power[ridx] += bw20pow;
4664 if (power[ridx] > R92C_MAX_TX_PWR)
4665 power[ridx] = R92C_MAX_TX_PWR;
4666 }
4667}
4668
4669static void
4670urtwn_set_txpower(struct urtwn_softc *sc, struct ieee80211_channel *c,
4671 struct ieee80211_channel *extc)
4672{
4673 uint16_t power[URTWN_RIDX_COUNT];
4674 int i;
4675
4676 for (i = 0; i < sc->ntxchains; i++) {
4677 /* Compute per-rate Tx power values. */
4678 if (sc->chip & URTWN_CHIP_88E)
4679 urtwn_r88e_get_txpower(sc, i, c, extc, power);
4680 else
4681 urtwn_get_txpower(sc, i, c, extc, power);
4682 /* Write per-rate Tx power values to hardware. */
4683 urtwn_write_txpower(sc, i, power);
4684 }
4685}
4686
4687static void
4688urtwn_set_rx_bssid_all(struct urtwn_softc *sc, int enable)
4689{
4690 uint32_t reg;
4691
4692 reg = urtwn_read_4(sc, R92C_RCR);
4693 if (enable)
4694 reg &= ~R92C_RCR_CBSSID_BCN;
4695 else
4696 reg |= R92C_RCR_CBSSID_BCN;
4697 urtwn_write_4(sc, R92C_RCR, reg);
4698}
4699
4700static void
4701urtwn_set_gain(struct urtwn_softc *sc, uint8_t gain)
4702{
4703 uint32_t reg;
4704
4705 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0));
4706 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, gain);
4707 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg);
4708
4709 if (!(sc->chip & URTWN_CHIP_88E)) {
4710 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1));
4711 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, gain);
4712 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg);
4713 }
4714}
4715
4716static void
4717urtwn_scan_start(struct ieee80211com *ic)
4718{
4719 struct urtwn_softc *sc = ic->ic_softc;
4720
4721 URTWN_LOCK(sc);
4722 /* Receive beacons / probe responses from any BSSID. */
4723 if (ic->ic_opmode != IEEE80211_M_IBSS)
4724 urtwn_set_rx_bssid_all(sc, 1);
4725
4726 /* Set gain for scanning. */
4727 urtwn_set_gain(sc, 0x20);
4728 URTWN_UNLOCK(sc);
4729}
4730
4731static void
4732urtwn_scan_end(struct ieee80211com *ic)
4733{
4734 struct urtwn_softc *sc = ic->ic_softc;
4735
4736 URTWN_LOCK(sc);
4737 /* Restore limitations. */
4738 if (ic->ic_promisc == 0 && ic->ic_opmode != IEEE80211_M_IBSS)
4739 urtwn_set_rx_bssid_all(sc, 0);
4740
4741 /* Set gain under link. */
4742 urtwn_set_gain(sc, 0x32);
4743 URTWN_UNLOCK(sc);
4744}
4745
4746static void
| 625 ic->ic_set_channel = urtwn_set_channel;
626 ic->ic_transmit = urtwn_transmit;
627 ic->ic_parent = urtwn_parent;
628 ic->ic_vap_create = urtwn_vap_create;
629 ic->ic_vap_delete = urtwn_vap_delete;
630 ic->ic_wme.wme_update = urtwn_wme_update;
631 ic->ic_updateslot = urtwn_update_slot;
632 ic->ic_update_promisc = urtwn_update_promisc;
633 ic->ic_update_mcast = urtwn_update_mcast;
634 if (sc->chip & URTWN_CHIP_88E) {
635 ic->ic_node_alloc = urtwn_node_alloc;
636 ic->ic_newassoc = urtwn_newassoc;
637 sc->sc_node_free = ic->ic_node_free;
638 ic->ic_node_free = urtwn_node_free;
639 }
640 ic->ic_update_chw = urtwn_update_chw;
641 ic->ic_ampdu_enable = urtwn_ampdu_enable;
642
643 ieee80211_radiotap_attach(ic, &sc->sc_txtap.wt_ihdr,
644 sizeof(sc->sc_txtap), URTWN_TX_RADIOTAP_PRESENT,
645 &sc->sc_rxtap.wr_ihdr, sizeof(sc->sc_rxtap),
646 URTWN_RX_RADIOTAP_PRESENT);
647
648 TASK_INIT(&sc->cmdq_task, 0, urtwn_cmdq_cb, sc);
649
650 urtwn_sysctlattach(sc);
651
652 if (bootverbose)
653 ieee80211_announce(ic);
654
655 return (0);
656
657detach:
658 urtwn_detach(self);
659 return (ENXIO); /* failure */
660}
661
662static void
663urtwn_sysctlattach(struct urtwn_softc *sc)
664{
665#ifdef USB_DEBUG
666 struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(sc->sc_dev);
667 struct sysctl_oid *tree = device_get_sysctl_tree(sc->sc_dev);
668
669 SYSCTL_ADD_U32(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
670 "debug", CTLFLAG_RW, &sc->sc_debug, sc->sc_debug,
671 "control debugging printfs");
672#endif
673}
674
675static int
676urtwn_detach(device_t self)
677{
678 struct urtwn_softc *sc = device_get_softc(self);
679 struct ieee80211com *ic = &sc->sc_ic;
680 unsigned int x;
681
682 /* Prevent further ioctls. */
683 URTWN_LOCK(sc);
684 sc->sc_flags |= URTWN_DETACHED;
685 URTWN_UNLOCK(sc);
686
687 urtwn_stop(sc);
688
689 callout_drain(&sc->sc_watchdog_ch);
690 callout_drain(&sc->sc_calib_to);
691
692 /* stop all USB transfers */
693 usbd_transfer_unsetup(sc->sc_xfer, URTWN_N_TRANSFER);
694
695 /* Prevent further allocations from RX/TX data lists. */
696 URTWN_LOCK(sc);
697 STAILQ_INIT(&sc->sc_tx_active);
698 STAILQ_INIT(&sc->sc_tx_inactive);
699 STAILQ_INIT(&sc->sc_tx_pending);
700
701 STAILQ_INIT(&sc->sc_rx_active);
702 STAILQ_INIT(&sc->sc_rx_inactive);
703 URTWN_UNLOCK(sc);
704
705 /* drain USB transfers */
706 for (x = 0; x != URTWN_N_TRANSFER; x++)
707 usbd_transfer_drain(sc->sc_xfer[x]);
708
709 /* Free data buffers. */
710 URTWN_LOCK(sc);
711 urtwn_free_tx_list(sc);
712 urtwn_free_rx_list(sc);
713 URTWN_UNLOCK(sc);
714
715 if (ic->ic_softc == sc) {
716 ieee80211_draintask(ic, &sc->cmdq_task);
717 ieee80211_ifdetach(ic);
718 }
719
720 URTWN_NT_LOCK_DESTROY(sc);
721 URTWN_CMDQ_LOCK_DESTROY(sc);
722 mtx_destroy(&sc->sc_mtx);
723
724 return (0);
725}
726
727static void
728urtwn_drain_mbufq(struct urtwn_softc *sc)
729{
730 struct mbuf *m;
731 struct ieee80211_node *ni;
732 URTWN_ASSERT_LOCKED(sc);
733 while ((m = mbufq_dequeue(&sc->sc_snd)) != NULL) {
734 ni = (struct ieee80211_node *)m->m_pkthdr.rcvif;
735 m->m_pkthdr.rcvif = NULL;
736 ieee80211_free_node(ni);
737 m_freem(m);
738 }
739}
740
741static usb_error_t
742urtwn_do_request(struct urtwn_softc *sc, struct usb_device_request *req,
743 void *data)
744{
745 usb_error_t err;
746 int ntries = 10;
747
748 URTWN_ASSERT_LOCKED(sc);
749
750 while (ntries--) {
751 err = usbd_do_request_flags(sc->sc_udev, &sc->sc_mtx,
752 req, data, 0, NULL, 250 /* ms */);
753 if (err == 0)
754 break;
755
756 URTWN_DPRINTF(sc, URTWN_DEBUG_USB,
757 "%s: control request failed, %s (retries left: %d)\n",
758 __func__, usbd_errstr(err), ntries);
759 usb_pause_mtx(&sc->sc_mtx, hz / 100);
760 }
761 return (err);
762}
763
764static struct ieee80211vap *
765urtwn_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit,
766 enum ieee80211_opmode opmode, int flags,
767 const uint8_t bssid[IEEE80211_ADDR_LEN],
768 const uint8_t mac[IEEE80211_ADDR_LEN])
769{
770 struct urtwn_softc *sc = ic->ic_softc;
771 struct urtwn_vap *uvp;
772 struct ieee80211vap *vap;
773
774 if (!TAILQ_EMPTY(&ic->ic_vaps)) /* only one at a time */
775 return (NULL);
776
777 uvp = malloc(sizeof(struct urtwn_vap), M_80211_VAP, M_WAITOK | M_ZERO);
778 vap = &uvp->vap;
779 /* enable s/w bmiss handling for sta mode */
780
781 if (ieee80211_vap_setup(ic, vap, name, unit, opmode,
782 flags | IEEE80211_CLONE_NOBEACONS, bssid) != 0) {
783 /* out of memory */
784 free(uvp, M_80211_VAP);
785 return (NULL);
786 }
787
788 if (opmode == IEEE80211_M_HOSTAP || opmode == IEEE80211_M_IBSS)
789 urtwn_init_beacon(sc, uvp);
790
791 /* override state transition machine */
792 uvp->newstate = vap->iv_newstate;
793 vap->iv_newstate = urtwn_newstate;
794 vap->iv_update_beacon = urtwn_update_beacon;
795 vap->iv_key_alloc = urtwn_key_alloc;
796 vap->iv_key_set = urtwn_key_set;
797 vap->iv_key_delete = urtwn_key_delete;
798
799 /* 802.11n parameters */
800 vap->iv_ampdu_density = IEEE80211_HTCAP_MPDUDENSITY_16;
801 vap->iv_ampdu_rxmax = IEEE80211_HTCAP_MAXRXAMPDU_64K;
802
803 if (opmode == IEEE80211_M_IBSS) {
804 uvp->recv_mgmt = vap->iv_recv_mgmt;
805 vap->iv_recv_mgmt = urtwn_ibss_recv_mgmt;
806 TASK_INIT(&uvp->tsf_task_adhoc, 0, urtwn_tsf_task_adhoc, vap);
807 }
808
809 if (URTWN_CHIP_HAS_RATECTL(sc))
810 ieee80211_ratectl_init(vap);
811 /* complete setup */
812 ieee80211_vap_attach(vap, ieee80211_media_change,
813 ieee80211_media_status, mac);
814 ic->ic_opmode = opmode;
815 return (vap);
816}
817
818static void
819urtwn_vap_delete(struct ieee80211vap *vap)
820{
821 struct ieee80211com *ic = vap->iv_ic;
822 struct urtwn_softc *sc = ic->ic_softc;
823 struct urtwn_vap *uvp = URTWN_VAP(vap);
824
825 if (uvp->bcn_mbuf != NULL)
826 m_freem(uvp->bcn_mbuf);
827 if (vap->iv_opmode == IEEE80211_M_IBSS)
828 ieee80211_draintask(ic, &uvp->tsf_task_adhoc);
829 if (URTWN_CHIP_HAS_RATECTL(sc))
830 ieee80211_ratectl_deinit(vap);
831 ieee80211_vap_detach(vap);
832 free(uvp, M_80211_VAP);
833}
834
835static struct mbuf *
836urtwn_rx_copy_to_mbuf(struct urtwn_softc *sc, struct r92c_rx_stat *stat,
837 int totlen)
838{
839 struct ieee80211com *ic = &sc->sc_ic;
840 struct mbuf *m;
841 uint32_t rxdw0;
842 int pktlen;
843
844 /*
845 * don't pass packets to the ieee80211 framework if the driver isn't
846 * RUNNING.
847 */
848 if (!(sc->sc_flags & URTWN_RUNNING))
849 return (NULL);
850
851 rxdw0 = le32toh(stat->rxdw0);
852 if (rxdw0 & (R92C_RXDW0_CRCERR | R92C_RXDW0_ICVERR)) {
853 /*
854 * This should not happen since we setup our Rx filter
855 * to not receive these frames.
856 */
857 URTWN_DPRINTF(sc, URTWN_DEBUG_RECV,
858 "%s: RX flags error (%s)\n", __func__,
859 rxdw0 & R92C_RXDW0_CRCERR ? "CRC" : "ICV");
860 goto fail;
861 }
862
863 pktlen = MS(rxdw0, R92C_RXDW0_PKTLEN);
864 if (pktlen < sizeof(struct ieee80211_frame_ack)) {
865 URTWN_DPRINTF(sc, URTWN_DEBUG_RECV,
866 "%s: frame is too short: %d\n", __func__, pktlen);
867 goto fail;
868 }
869
870 if (__predict_false(totlen > MCLBYTES)) {
871 /* convert to m_getjcl if this happens */
872 device_printf(sc->sc_dev, "%s: frame too long: %d (%d)\n",
873 __func__, pktlen, totlen);
874 goto fail;
875 }
876
877 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
878 if (__predict_false(m == NULL)) {
879 device_printf(sc->sc_dev, "%s: could not allocate RX mbuf\n",
880 __func__);
881 goto fail;
882 }
883
884 /* Finalize mbuf. */
885 memcpy(mtod(m, uint8_t *), (uint8_t *)stat, totlen);
886 m->m_pkthdr.len = m->m_len = totlen;
887
888 return (m);
889fail:
890 counter_u64_add(ic->ic_ierrors, 1);
891 return (NULL);
892}
893
894static struct mbuf *
895urtwn_report_intr(struct usb_xfer *xfer, struct urtwn_data *data)
896{
897 struct urtwn_softc *sc = data->sc;
898 struct ieee80211com *ic = &sc->sc_ic;
899 struct r92c_rx_stat *stat;
900 uint8_t *buf;
901 int len;
902
903 usbd_xfer_status(xfer, &len, NULL, NULL, NULL);
904
905 if (len < sizeof(*stat)) {
906 counter_u64_add(ic->ic_ierrors, 1);
907 return (NULL);
908 }
909
910 buf = data->buf;
911 stat = (struct r92c_rx_stat *)buf;
912
913 /*
914 * For 88E chips we can tie the FF flushing here;
915 * this is where we do know exactly how deep the
916 * transmit queue is.
917 *
918 * But it won't work for R92 chips, so we can't
919 * take the easy way out.
920 */
921
922 if (sc->chip & URTWN_CHIP_88E) {
923 int report_sel = MS(le32toh(stat->rxdw3), R88E_RXDW3_RPT);
924
925 switch (report_sel) {
926 case R88E_RXDW3_RPT_RX:
927 return (urtwn_rxeof(sc, buf, len));
928 case R88E_RXDW3_RPT_TX1:
929 urtwn_r88e_ratectl_tx_complete(sc, &stat[1]);
930 break;
931 default:
932 URTWN_DPRINTF(sc, URTWN_DEBUG_INTR,
933 "%s: case %d was not handled\n", __func__,
934 report_sel);
935 break;
936 }
937 } else
938 return (urtwn_rxeof(sc, buf, len));
939
940 return (NULL);
941}
942
943static struct mbuf *
944urtwn_rxeof(struct urtwn_softc *sc, uint8_t *buf, int len)
945{
946 struct r92c_rx_stat *stat;
947 struct mbuf *m, *m0 = NULL, *prevm = NULL;
948 uint32_t rxdw0;
949 int totlen, pktlen, infosz, npkts;
950
951 /* Get the number of encapsulated frames. */
952 stat = (struct r92c_rx_stat *)buf;
953 npkts = MS(le32toh(stat->rxdw2), R92C_RXDW2_PKTCNT);
954 URTWN_DPRINTF(sc, URTWN_DEBUG_RECV,
955 "%s: Rx %d frames in one chunk\n", __func__, npkts);
956
957 /* Process all of them. */
958 while (npkts-- > 0) {
959 if (len < sizeof(*stat))
960 break;
961 stat = (struct r92c_rx_stat *)buf;
962 rxdw0 = le32toh(stat->rxdw0);
963
964 pktlen = MS(rxdw0, R92C_RXDW0_PKTLEN);
965 if (pktlen == 0)
966 break;
967
968 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8;
969
970 /* Make sure everything fits in xfer. */
971 totlen = sizeof(*stat) + infosz + pktlen;
972 if (totlen > len)
973 break;
974
975 m = urtwn_rx_copy_to_mbuf(sc, stat, totlen);
976 if (m0 == NULL)
977 m0 = m;
978 if (prevm == NULL)
979 prevm = m;
980 else {
981 prevm->m_next = m;
982 prevm = m;
983 }
984
985 /* Next chunk is 128-byte aligned. */
986 totlen = (totlen + 127) & ~127;
987 buf += totlen;
988 len -= totlen;
989 }
990
991 return (m0);
992}
993
994static void
995urtwn_r88e_ratectl_tx_complete(struct urtwn_softc *sc, void *arg)
996{
997 struct r88e_tx_rpt_ccx *rpt = arg;
998 struct ieee80211vap *vap;
999 struct ieee80211_node *ni;
1000 uint8_t macid;
1001 int ntries;
1002
1003 macid = MS(rpt->rptb1, R88E_RPTB1_MACID);
1004 ntries = MS(rpt->rptb2, R88E_RPTB2_RETRY_CNT);
1005
1006 URTWN_NT_LOCK(sc);
1007 ni = sc->node_list[macid];
1008 if (ni != NULL) {
1009 vap = ni->ni_vap;
1010 URTWN_DPRINTF(sc, URTWN_DEBUG_INTR, "%s: frame for macid %d was"
1011 "%s sent (%d retries)\n", __func__, macid,
1012 (rpt->rptb1 & R88E_RPTB1_PKT_OK) ? "" : " not",
1013 ntries);
1014
1015 if (rpt->rptb1 & R88E_RPTB1_PKT_OK) {
1016 ieee80211_ratectl_tx_complete(vap, ni,
1017 IEEE80211_RATECTL_TX_SUCCESS, &ntries, NULL);
1018 } else {
1019 ieee80211_ratectl_tx_complete(vap, ni,
1020 IEEE80211_RATECTL_TX_FAILURE, &ntries, NULL);
1021 }
1022 } else {
1023 URTWN_DPRINTF(sc, URTWN_DEBUG_INTR, "%s: macid %d, ni is NULL\n",
1024 __func__, macid);
1025 }
1026 URTWN_NT_UNLOCK(sc);
1027}
1028
1029static struct ieee80211_node *
1030urtwn_rx_frame(struct urtwn_softc *sc, struct mbuf *m, int8_t *rssi_p)
1031{
1032 struct ieee80211com *ic = &sc->sc_ic;
1033 struct ieee80211_frame_min *wh;
1034 struct r92c_rx_stat *stat;
1035 uint32_t rxdw0, rxdw3;
1036 uint8_t rate, cipher;
1037 int8_t rssi = -127;
1038 int infosz;
1039
1040 stat = mtod(m, struct r92c_rx_stat *);
1041 rxdw0 = le32toh(stat->rxdw0);
1042 rxdw3 = le32toh(stat->rxdw3);
1043
1044 rate = MS(rxdw3, R92C_RXDW3_RATE);
1045 cipher = MS(rxdw0, R92C_RXDW0_CIPHER);
1046 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8;
1047
1048 /* Get RSSI from PHY status descriptor if present. */
1049 if (infosz != 0 && (rxdw0 & R92C_RXDW0_PHYST)) {
1050 if (sc->chip & URTWN_CHIP_88E)
1051 rssi = urtwn_r88e_get_rssi(sc, rate, &stat[1]);
1052 else
1053 rssi = urtwn_get_rssi(sc, rate, &stat[1]);
1054 URTWN_DPRINTF(sc, URTWN_DEBUG_RSSI, "%s: rssi=%d\n", __func__, rssi);
1055 /* Update our average RSSI. */
1056 urtwn_update_avgrssi(sc, rate, rssi);
1057 }
1058
1059 if (ieee80211_radiotap_active(ic)) {
1060 struct urtwn_rx_radiotap_header *tap = &sc->sc_rxtap;
1061
1062 tap->wr_flags = 0;
1063
1064 urtwn_get_tsf(sc, &tap->wr_tsft);
1065 if (__predict_false(le32toh((uint32_t)tap->wr_tsft) <
1066 le32toh(stat->rxdw5))) {
1067 tap->wr_tsft = le32toh(tap->wr_tsft >> 32) - 1;
1068 tap->wr_tsft = (uint64_t)htole32(tap->wr_tsft) << 32;
1069 } else
1070 tap->wr_tsft &= 0xffffffff00000000;
1071 tap->wr_tsft += stat->rxdw5;
1072
1073 /* XXX 20/40? */
1074 /* XXX shortgi? */
1075
1076 /* Map HW rate index to 802.11 rate. */
1077 if (!(rxdw3 & R92C_RXDW3_HT)) {
1078 tap->wr_rate = ridx2rate[rate];
1079 } else if (rate >= 12) { /* MCS0~15. */
1080 /* Bit 7 set means HT MCS instead of rate. */
1081 tap->wr_rate = 0x80 | (rate - 12);
1082 }
1083
1084 /* XXX TODO: this isn't right; should use the last good RSSI */
1085 tap->wr_dbm_antsignal = rssi;
1086 tap->wr_dbm_antnoise = URTWN_NOISE_FLOOR;
1087 }
1088
1089 *rssi_p = rssi;
1090
1091 /* Drop descriptor. */
1092 m_adj(m, sizeof(*stat) + infosz);
1093 wh = mtod(m, struct ieee80211_frame_min *);
1094
1095 if ((wh->i_fc[1] & IEEE80211_FC1_PROTECTED) &&
1096 cipher != R92C_CAM_ALGO_NONE) {
1097 m->m_flags |= M_WEP;
1098 }
1099
1100 if (m->m_len >= sizeof(*wh))
1101 return (ieee80211_find_rxnode(ic, wh));
1102
1103 return (NULL);
1104}
1105
1106static void
1107urtwn_bulk_rx_callback(struct usb_xfer *xfer, usb_error_t error)
1108{
1109 struct urtwn_softc *sc = usbd_xfer_softc(xfer);
1110 struct ieee80211com *ic = &sc->sc_ic;
1111 struct ieee80211_node *ni;
1112 struct mbuf *m = NULL, *next;
1113 struct urtwn_data *data;
1114 int8_t nf, rssi;
1115
1116 URTWN_ASSERT_LOCKED(sc);
1117
1118 switch (USB_GET_STATE(xfer)) {
1119 case USB_ST_TRANSFERRED:
1120 data = STAILQ_FIRST(&sc->sc_rx_active);
1121 if (data == NULL)
1122 goto tr_setup;
1123 STAILQ_REMOVE_HEAD(&sc->sc_rx_active, next);
1124 m = urtwn_report_intr(xfer, data);
1125 STAILQ_INSERT_TAIL(&sc->sc_rx_inactive, data, next);
1126 /* FALLTHROUGH */
1127 case USB_ST_SETUP:
1128tr_setup:
1129 data = STAILQ_FIRST(&sc->sc_rx_inactive);
1130 if (data == NULL) {
1131 KASSERT(m == NULL, ("mbuf isn't NULL"));
1132 goto finish;
1133 }
1134 STAILQ_REMOVE_HEAD(&sc->sc_rx_inactive, next);
1135 STAILQ_INSERT_TAIL(&sc->sc_rx_active, data, next);
1136 usbd_xfer_set_frame_data(xfer, 0, data->buf,
1137 usbd_xfer_max_len(xfer));
1138 usbd_transfer_submit(xfer);
1139
1140 /*
1141 * To avoid LOR we should unlock our private mutex here to call
1142 * ieee80211_input() because here is at the end of a USB
1143 * callback and safe to unlock.
1144 */
1145 while (m != NULL) {
1146 next = m->m_next;
1147 m->m_next = NULL;
1148
1149 ni = urtwn_rx_frame(sc, m, &rssi);
1150
1151 /* Store a global last-good RSSI */
1152 if (rssi != -127)
1153 sc->last_rssi = rssi;
1154
1155 URTWN_UNLOCK(sc);
1156
1157 nf = URTWN_NOISE_FLOOR;
1158 if (ni != NULL) {
1159 if (rssi != -127)
1160 URTWN_NODE(ni)->last_rssi = rssi;
1161 if (ni->ni_flags & IEEE80211_NODE_HT)
1162 m->m_flags |= M_AMPDU;
1163 (void)ieee80211_input(ni, m,
1164 URTWN_NODE(ni)->last_rssi - nf, nf);
1165 ieee80211_free_node(ni);
1166 } else {
1167 /* Use last good global RSSI */
1168 (void)ieee80211_input_all(ic, m,
1169 sc->last_rssi - nf, nf);
1170 }
1171 URTWN_LOCK(sc);
1172 m = next;
1173 }
1174 break;
1175 default:
1176 /* needs it to the inactive queue due to a error. */
1177 data = STAILQ_FIRST(&sc->sc_rx_active);
1178 if (data != NULL) {
1179 STAILQ_REMOVE_HEAD(&sc->sc_rx_active, next);
1180 STAILQ_INSERT_TAIL(&sc->sc_rx_inactive, data, next);
1181 }
1182 if (error != USB_ERR_CANCELLED) {
1183 usbd_xfer_set_stall(xfer);
1184 counter_u64_add(ic->ic_ierrors, 1);
1185 goto tr_setup;
1186 }
1187 break;
1188 }
1189finish:
1190 /* Finished receive; age anything left on the FF queue by a little bump */
1191 /*
1192 * XXX TODO: just make this a callout timer schedule so we can
1193 * flush the FF staging queue if we're approaching idle.
1194 */
1195#ifdef IEEE80211_SUPPORT_SUPERG
1196 URTWN_UNLOCK(sc);
1197 ieee80211_ff_age_all(ic, 1);
1198 URTWN_LOCK(sc);
1199#endif
1200
1201 /* Kick-start more transmit in case we stalled */
1202 urtwn_start(sc);
1203}
1204
1205static void
1206urtwn_txeof(struct urtwn_softc *sc, struct urtwn_data *data, int status)
1207{
1208
1209 URTWN_ASSERT_LOCKED(sc);
1210
1211 if (data->ni != NULL) /* not a beacon frame */
1212 ieee80211_tx_complete(data->ni, data->m, status);
1213
1214 if (sc->sc_tx_n_active > 0)
1215 sc->sc_tx_n_active--;
1216
1217 data->ni = NULL;
1218 data->m = NULL;
1219
1220 sc->sc_txtimer = 0;
1221
1222 STAILQ_INSERT_TAIL(&sc->sc_tx_inactive, data, next);
1223}
1224
1225static int
1226urtwn_alloc_list(struct urtwn_softc *sc, struct urtwn_data data[],
1227 int ndata, int maxsz)
1228{
1229 int i, error;
1230
1231 for (i = 0; i < ndata; i++) {
1232 struct urtwn_data *dp = &data[i];
1233 dp->sc = sc;
1234 dp->m = NULL;
1235 dp->buf = malloc(maxsz, M_USBDEV, M_NOWAIT);
1236 if (dp->buf == NULL) {
1237 device_printf(sc->sc_dev,
1238 "could not allocate buffer\n");
1239 error = ENOMEM;
1240 goto fail;
1241 }
1242 dp->ni = NULL;
1243 }
1244
1245 return (0);
1246fail:
1247 urtwn_free_list(sc, data, ndata);
1248 return (error);
1249}
1250
1251static int
1252urtwn_alloc_rx_list(struct urtwn_softc *sc)
1253{
1254 int error, i;
1255
1256 error = urtwn_alloc_list(sc, sc->sc_rx, URTWN_RX_LIST_COUNT,
1257 URTWN_RXBUFSZ);
1258 if (error != 0)
1259 return (error);
1260
1261 STAILQ_INIT(&sc->sc_rx_active);
1262 STAILQ_INIT(&sc->sc_rx_inactive);
1263
1264 for (i = 0; i < URTWN_RX_LIST_COUNT; i++)
1265 STAILQ_INSERT_HEAD(&sc->sc_rx_inactive, &sc->sc_rx[i], next);
1266
1267 return (0);
1268}
1269
1270static int
1271urtwn_alloc_tx_list(struct urtwn_softc *sc)
1272{
1273 int error, i;
1274
1275 error = urtwn_alloc_list(sc, sc->sc_tx, URTWN_TX_LIST_COUNT,
1276 URTWN_TXBUFSZ);
1277 if (error != 0)
1278 return (error);
1279
1280 STAILQ_INIT(&sc->sc_tx_active);
1281 STAILQ_INIT(&sc->sc_tx_inactive);
1282 STAILQ_INIT(&sc->sc_tx_pending);
1283
1284 for (i = 0; i < URTWN_TX_LIST_COUNT; i++)
1285 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, &sc->sc_tx[i], next);
1286
1287 return (0);
1288}
1289
1290static void
1291urtwn_free_list(struct urtwn_softc *sc, struct urtwn_data data[], int ndata)
1292{
1293 int i;
1294
1295 for (i = 0; i < ndata; i++) {
1296 struct urtwn_data *dp = &data[i];
1297
1298 if (dp->buf != NULL) {
1299 free(dp->buf, M_USBDEV);
1300 dp->buf = NULL;
1301 }
1302 if (dp->ni != NULL) {
1303 ieee80211_free_node(dp->ni);
1304 dp->ni = NULL;
1305 }
1306 }
1307}
1308
1309static void
1310urtwn_free_rx_list(struct urtwn_softc *sc)
1311{
1312 urtwn_free_list(sc, sc->sc_rx, URTWN_RX_LIST_COUNT);
1313}
1314
1315static void
1316urtwn_free_tx_list(struct urtwn_softc *sc)
1317{
1318 urtwn_free_list(sc, sc->sc_tx, URTWN_TX_LIST_COUNT);
1319}
1320
1321static void
1322urtwn_bulk_tx_callback(struct usb_xfer *xfer, usb_error_t error)
1323{
1324 struct urtwn_softc *sc = usbd_xfer_softc(xfer);
1325#ifdef IEEE80211_SUPPORT_SUPERG
1326 struct ieee80211com *ic = &sc->sc_ic;
1327#endif
1328 struct urtwn_data *data;
1329
1330 URTWN_ASSERT_LOCKED(sc);
1331
1332 switch (USB_GET_STATE(xfer)){
1333 case USB_ST_TRANSFERRED:
1334 data = STAILQ_FIRST(&sc->sc_tx_active);
1335 if (data == NULL)
1336 goto tr_setup;
1337 STAILQ_REMOVE_HEAD(&sc->sc_tx_active, next);
1338 urtwn_txeof(sc, data, 0);
1339 /* FALLTHROUGH */
1340 case USB_ST_SETUP:
1341tr_setup:
1342 data = STAILQ_FIRST(&sc->sc_tx_pending);
1343 if (data == NULL) {
1344 URTWN_DPRINTF(sc, URTWN_DEBUG_XMIT,
1345 "%s: empty pending queue\n", __func__);
1346 sc->sc_tx_n_active = 0;
1347 goto finish;
1348 }
1349 STAILQ_REMOVE_HEAD(&sc->sc_tx_pending, next);
1350 STAILQ_INSERT_TAIL(&sc->sc_tx_active, data, next);
1351 usbd_xfer_set_frame_data(xfer, 0, data->buf, data->buflen);
1352 usbd_transfer_submit(xfer);
1353 sc->sc_tx_n_active++;
1354 break;
1355 default:
1356 data = STAILQ_FIRST(&sc->sc_tx_active);
1357 if (data == NULL)
1358 goto tr_setup;
1359 STAILQ_REMOVE_HEAD(&sc->sc_tx_active, next);
1360 urtwn_txeof(sc, data, 1);
1361 if (error != USB_ERR_CANCELLED) {
1362 usbd_xfer_set_stall(xfer);
1363 goto tr_setup;
1364 }
1365 break;
1366 }
1367finish:
1368#ifdef IEEE80211_SUPPORT_SUPERG
1369 /*
1370 * If the TX active queue drops below a certain
1371 * threshold, ensure we age fast-frames out so they're
1372 * transmitted.
1373 */
1374 if (sc->sc_tx_n_active <= 1) {
1375 /* XXX ew - net80211 should defer this for us! */
1376
1377 /*
1378 * Note: this sc_tx_n_active currently tracks
1379 * the number of pending transmit submissions
1380 * and not the actual depth of the TX frames
1381 * pending to the hardware. That means that
1382 * we're going to end up with some sub-optimal
1383 * aggregation behaviour.
1384 */
1385 /*
1386 * XXX TODO: just make this a callout timer schedule so we can
1387 * flush the FF staging queue if we're approaching idle.
1388 */
1389 URTWN_UNLOCK(sc);
1390 ieee80211_ff_flush(ic, WME_AC_VO);
1391 ieee80211_ff_flush(ic, WME_AC_VI);
1392 ieee80211_ff_flush(ic, WME_AC_BE);
1393 ieee80211_ff_flush(ic, WME_AC_BK);
1394 URTWN_LOCK(sc);
1395 }
1396#endif
1397 /* Kick-start more transmit */
1398 urtwn_start(sc);
1399}
1400
1401static struct urtwn_data *
1402_urtwn_getbuf(struct urtwn_softc *sc)
1403{
1404 struct urtwn_data *bf;
1405
1406 bf = STAILQ_FIRST(&sc->sc_tx_inactive);
1407 if (bf != NULL)
1408 STAILQ_REMOVE_HEAD(&sc->sc_tx_inactive, next);
1409 else {
1410 URTWN_DPRINTF(sc, URTWN_DEBUG_XMIT,
1411 "%s: out of xmit buffers\n", __func__);
1412 }
1413 return (bf);
1414}
1415
1416static struct urtwn_data *
1417urtwn_getbuf(struct urtwn_softc *sc)
1418{
1419 struct urtwn_data *bf;
1420
1421 URTWN_ASSERT_LOCKED(sc);
1422
1423 bf = _urtwn_getbuf(sc);
1424 if (bf == NULL) {
1425 URTWN_DPRINTF(sc, URTWN_DEBUG_XMIT, "%s: stop queue\n",
1426 __func__);
1427 }
1428 return (bf);
1429}
1430
1431static usb_error_t
1432urtwn_write_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf,
1433 int len)
1434{
1435 usb_device_request_t req;
1436
1437 req.bmRequestType = UT_WRITE_VENDOR_DEVICE;
1438 req.bRequest = R92C_REQ_REGS;
1439 USETW(req.wValue, addr);
1440 USETW(req.wIndex, 0);
1441 USETW(req.wLength, len);
1442 return (urtwn_do_request(sc, &req, buf));
1443}
1444
1445static usb_error_t
1446urtwn_write_1(struct urtwn_softc *sc, uint16_t addr, uint8_t val)
1447{
1448 return (urtwn_write_region_1(sc, addr, &val, sizeof(val)));
1449}
1450
1451static usb_error_t
1452urtwn_write_2(struct urtwn_softc *sc, uint16_t addr, uint16_t val)
1453{
1454 val = htole16(val);
1455 return (urtwn_write_region_1(sc, addr, (uint8_t *)&val, sizeof(val)));
1456}
1457
1458static usb_error_t
1459urtwn_write_4(struct urtwn_softc *sc, uint16_t addr, uint32_t val)
1460{
1461 val = htole32(val);
1462 return (urtwn_write_region_1(sc, addr, (uint8_t *)&val, sizeof(val)));
1463}
1464
1465static usb_error_t
1466urtwn_read_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf,
1467 int len)
1468{
1469 usb_device_request_t req;
1470
1471 req.bmRequestType = UT_READ_VENDOR_DEVICE;
1472 req.bRequest = R92C_REQ_REGS;
1473 USETW(req.wValue, addr);
1474 USETW(req.wIndex, 0);
1475 USETW(req.wLength, len);
1476 return (urtwn_do_request(sc, &req, buf));
1477}
1478
1479static uint8_t
1480urtwn_read_1(struct urtwn_softc *sc, uint16_t addr)
1481{
1482 uint8_t val;
1483
1484 if (urtwn_read_region_1(sc, addr, &val, 1) != 0)
1485 return (0xff);
1486 return (val);
1487}
1488
1489static uint16_t
1490urtwn_read_2(struct urtwn_softc *sc, uint16_t addr)
1491{
1492 uint16_t val;
1493
1494 if (urtwn_read_region_1(sc, addr, (uint8_t *)&val, 2) != 0)
1495 return (0xffff);
1496 return (le16toh(val));
1497}
1498
1499static uint32_t
1500urtwn_read_4(struct urtwn_softc *sc, uint16_t addr)
1501{
1502 uint32_t val;
1503
1504 if (urtwn_read_region_1(sc, addr, (uint8_t *)&val, 4) != 0)
1505 return (0xffffffff);
1506 return (le32toh(val));
1507}
1508
1509static int
1510urtwn_fw_cmd(struct urtwn_softc *sc, uint8_t id, const void *buf, int len)
1511{
1512 struct r92c_fw_cmd cmd;
1513 usb_error_t error;
1514 int ntries;
1515
1516 if (!(sc->sc_flags & URTWN_FW_LOADED)) {
1517 URTWN_DPRINTF(sc, URTWN_DEBUG_FIRMWARE, "%s: firmware "
1518 "was not loaded; command (id %d) will be discarded\n",
1519 __func__, id);
1520 return (0);
1521 }
1522
1523 /* Wait for current FW box to be empty. */
1524 for (ntries = 0; ntries < 100; ntries++) {
1525 if (!(urtwn_read_1(sc, R92C_HMETFR) & (1 << sc->fwcur)))
1526 break;
1527 urtwn_ms_delay(sc);
1528 }
1529 if (ntries == 100) {
1530 device_printf(sc->sc_dev,
1531 "could not send firmware command\n");
1532 return (ETIMEDOUT);
1533 }
1534 memset(&cmd, 0, sizeof(cmd));
1535 cmd.id = id;
1536 if (len > 3)
1537 cmd.id |= R92C_CMD_FLAG_EXT;
1538 KASSERT(len <= sizeof(cmd.msg), ("urtwn_fw_cmd\n"));
1539 memcpy(cmd.msg, buf, len);
1540
1541 /* Write the first word last since that will trigger the FW. */
1542 error = urtwn_write_region_1(sc, R92C_HMEBOX_EXT(sc->fwcur),
1543 (uint8_t *)&cmd + 4, 2);
1544 if (error != USB_ERR_NORMAL_COMPLETION)
1545 return (EIO);
1546 error = urtwn_write_region_1(sc, R92C_HMEBOX(sc->fwcur),
1547 (uint8_t *)&cmd + 0, 4);
1548 if (error != USB_ERR_NORMAL_COMPLETION)
1549 return (EIO);
1550
1551 sc->fwcur = (sc->fwcur + 1) % R92C_H2C_NBOX;
1552 return (0);
1553}
1554
1555static void
1556urtwn_cmdq_cb(void *arg, int pending)
1557{
1558 struct urtwn_softc *sc = arg;
1559 struct urtwn_cmdq *item;
1560
1561 /*
1562 * Device must be powered on (via urtwn_power_on())
1563 * before any command may be sent.
1564 */
1565 URTWN_LOCK(sc);
1566 if (!(sc->sc_flags & URTWN_RUNNING)) {
1567 URTWN_UNLOCK(sc);
1568 return;
1569 }
1570
1571 URTWN_CMDQ_LOCK(sc);
1572 while (sc->cmdq[sc->cmdq_first].func != NULL) {
1573 item = &sc->cmdq[sc->cmdq_first];
1574 sc->cmdq_first = (sc->cmdq_first + 1) % URTWN_CMDQ_SIZE;
1575 URTWN_CMDQ_UNLOCK(sc);
1576
1577 item->func(sc, &item->data);
1578
1579 URTWN_CMDQ_LOCK(sc);
1580 memset(item, 0, sizeof (*item));
1581 }
1582 URTWN_CMDQ_UNLOCK(sc);
1583 URTWN_UNLOCK(sc);
1584}
1585
1586static int
1587urtwn_cmd_sleepable(struct urtwn_softc *sc, const void *ptr, size_t len,
1588 CMD_FUNC_PROTO)
1589{
1590 struct ieee80211com *ic = &sc->sc_ic;
1591
1592 KASSERT(len <= sizeof(union sec_param), ("buffer overflow"));
1593
1594 URTWN_CMDQ_LOCK(sc);
1595 if (sc->cmdq[sc->cmdq_last].func != NULL) {
1596 device_printf(sc->sc_dev, "%s: cmdq overflow\n", __func__);
1597 URTWN_CMDQ_UNLOCK(sc);
1598
1599 return (EAGAIN);
1600 }
1601
1602 if (ptr != NULL)
1603 memcpy(&sc->cmdq[sc->cmdq_last].data, ptr, len);
1604 sc->cmdq[sc->cmdq_last].func = func;
1605 sc->cmdq_last = (sc->cmdq_last + 1) % URTWN_CMDQ_SIZE;
1606 URTWN_CMDQ_UNLOCK(sc);
1607
1608 ieee80211_runtask(ic, &sc->cmdq_task);
1609
1610 return (0);
1611}
1612
1613static __inline void
1614urtwn_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, uint32_t val)
1615{
1616
1617 sc->sc_rf_write(sc, chain, addr, val);
1618}
1619
1620static void
1621urtwn_r92c_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr,
1622 uint32_t val)
1623{
1624 urtwn_bb_write(sc, R92C_LSSI_PARAM(chain),
1625 SM(R92C_LSSI_PARAM_ADDR, addr) |
1626 SM(R92C_LSSI_PARAM_DATA, val));
1627}
1628
1629static void
1630urtwn_r88e_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr,
1631uint32_t val)
1632{
1633 urtwn_bb_write(sc, R92C_LSSI_PARAM(chain),
1634 SM(R88E_LSSI_PARAM_ADDR, addr) |
1635 SM(R92C_LSSI_PARAM_DATA, val));
1636}
1637
1638static uint32_t
1639urtwn_rf_read(struct urtwn_softc *sc, int chain, uint8_t addr)
1640{
1641 uint32_t reg[R92C_MAX_CHAINS], val;
1642
1643 reg[0] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(0));
1644 if (chain != 0)
1645 reg[chain] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(chain));
1646
1647 urtwn_bb_write(sc, R92C_HSSI_PARAM2(0),
1648 reg[0] & ~R92C_HSSI_PARAM2_READ_EDGE);
1649 urtwn_ms_delay(sc);
1650
1651 urtwn_bb_write(sc, R92C_HSSI_PARAM2(chain),
1652 RW(reg[chain], R92C_HSSI_PARAM2_READ_ADDR, addr) |
1653 R92C_HSSI_PARAM2_READ_EDGE);
1654 urtwn_ms_delay(sc);
1655
1656 urtwn_bb_write(sc, R92C_HSSI_PARAM2(0),
1657 reg[0] | R92C_HSSI_PARAM2_READ_EDGE);
1658 urtwn_ms_delay(sc);
1659
1660 if (urtwn_bb_read(sc, R92C_HSSI_PARAM1(chain)) & R92C_HSSI_PARAM1_PI)
1661 val = urtwn_bb_read(sc, R92C_HSPI_READBACK(chain));
1662 else
1663 val = urtwn_bb_read(sc, R92C_LSSI_READBACK(chain));
1664 return (MS(val, R92C_LSSI_READBACK_DATA));
1665}
1666
1667static int
1668urtwn_llt_write(struct urtwn_softc *sc, uint32_t addr, uint32_t data)
1669{
1670 usb_error_t error;
1671 int ntries;
1672
1673 error = urtwn_write_4(sc, R92C_LLT_INIT,
1674 SM(R92C_LLT_INIT_OP, R92C_LLT_INIT_OP_WRITE) |
1675 SM(R92C_LLT_INIT_ADDR, addr) |
1676 SM(R92C_LLT_INIT_DATA, data));
1677 if (error != USB_ERR_NORMAL_COMPLETION)
1678 return (EIO);
1679 /* Wait for write operation to complete. */
1680 for (ntries = 0; ntries < 20; ntries++) {
1681 if (MS(urtwn_read_4(sc, R92C_LLT_INIT), R92C_LLT_INIT_OP) ==
1682 R92C_LLT_INIT_OP_NO_ACTIVE)
1683 return (0);
1684 urtwn_ms_delay(sc);
1685 }
1686 return (ETIMEDOUT);
1687}
1688
1689static int
1690urtwn_efuse_read_next(struct urtwn_softc *sc, uint8_t *val)
1691{
1692 uint32_t reg;
1693 usb_error_t error;
1694 int ntries;
1695
1696 if (sc->last_rom_addr >= URTWN_EFUSE_MAX_LEN)
1697 return (EFAULT);
1698
1699 reg = urtwn_read_4(sc, R92C_EFUSE_CTRL);
1700 reg = RW(reg, R92C_EFUSE_CTRL_ADDR, sc->last_rom_addr);
1701 reg &= ~R92C_EFUSE_CTRL_VALID;
1702
1703 error = urtwn_write_4(sc, R92C_EFUSE_CTRL, reg);
1704 if (error != USB_ERR_NORMAL_COMPLETION)
1705 return (EIO);
1706 /* Wait for read operation to complete. */
1707 for (ntries = 0; ntries < 100; ntries++) {
1708 reg = urtwn_read_4(sc, R92C_EFUSE_CTRL);
1709 if (reg & R92C_EFUSE_CTRL_VALID)
1710 break;
1711 urtwn_ms_delay(sc);
1712 }
1713 if (ntries == 100) {
1714 device_printf(sc->sc_dev,
1715 "could not read efuse byte at address 0x%x\n",
1716 sc->last_rom_addr);
1717 return (ETIMEDOUT);
1718 }
1719
1720 *val = MS(reg, R92C_EFUSE_CTRL_DATA);
1721 sc->last_rom_addr++;
1722
1723 return (0);
1724}
1725
1726static int
1727urtwn_efuse_read_data(struct urtwn_softc *sc, uint8_t *rom, uint8_t off,
1728 uint8_t msk)
1729{
1730 uint8_t reg;
1731 int i, error;
1732
1733 for (i = 0; i < 4; i++) {
1734 if (msk & (1 << i))
1735 continue;
1736 error = urtwn_efuse_read_next(sc, ®);
1737 if (error != 0)
1738 return (error);
1739 URTWN_DPRINTF(sc, URTWN_DEBUG_ROM, "rom[0x%03X] == 0x%02X\n",
1740 off * 8 + i * 2, reg);
1741 rom[off * 8 + i * 2 + 0] = reg;
1742
1743 error = urtwn_efuse_read_next(sc, ®);
1744 if (error != 0)
1745 return (error);
1746 URTWN_DPRINTF(sc, URTWN_DEBUG_ROM, "rom[0x%03X] == 0x%02X\n",
1747 off * 8 + i * 2 + 1, reg);
1748 rom[off * 8 + i * 2 + 1] = reg;
1749 }
1750
1751 return (0);
1752}
1753
1754#ifdef USB_DEBUG
1755static void
1756urtwn_dump_rom_contents(struct urtwn_softc *sc, uint8_t *rom, uint16_t size)
1757{
1758 int i;
1759
1760 /* Dump ROM contents. */
1761 device_printf(sc->sc_dev, "%s:", __func__);
1762 for (i = 0; i < size; i++) {
1763 if (i % 32 == 0)
1764 printf("\n%03X: ", i);
1765 else if (i % 4 == 0)
1766 printf(" ");
1767
1768 printf("%02X", rom[i]);
1769 }
1770 printf("\n");
1771}
1772#endif
1773
1774static int
1775urtwn_efuse_read(struct urtwn_softc *sc, uint8_t *rom, uint16_t size)
1776{
1777#define URTWN_CHK(res) do { \
1778 if ((error = res) != 0) \
1779 goto end; \
1780} while(0)
1781 uint8_t msk, off, reg;
1782 int error;
1783
1784 URTWN_CHK(urtwn_efuse_switch_power(sc));
1785
1786 /* Read full ROM image. */
1787 sc->last_rom_addr = 0;
1788 memset(rom, 0xff, size);
1789
1790 URTWN_CHK(urtwn_efuse_read_next(sc, ®));
1791 while (reg != 0xff) {
1792 /* check for extended header */
1793 if ((sc->chip & URTWN_CHIP_88E) && (reg & 0x1f) == 0x0f) {
1794 off = reg >> 5;
1795 URTWN_CHK(urtwn_efuse_read_next(sc, ®));
1796
1797 if ((reg & 0x0f) != 0x0f)
1798 off = ((reg & 0xf0) >> 1) | off;
1799 else
1800 continue;
1801 } else
1802 off = reg >> 4;
1803 msk = reg & 0xf;
1804
1805 URTWN_CHK(urtwn_efuse_read_data(sc, rom, off, msk));
1806 URTWN_CHK(urtwn_efuse_read_next(sc, ®));
1807 }
1808
1809end:
1810
1811#ifdef USB_DEBUG
1812 if (sc->sc_debug & URTWN_DEBUG_ROM)
1813 urtwn_dump_rom_contents(sc, rom, size);
1814#endif
1815
1816 urtwn_write_1(sc, R92C_EFUSE_ACCESS, R92C_EFUSE_ACCESS_OFF);
1817
1818 if (error != 0) {
1819 device_printf(sc->sc_dev, "%s: error while reading ROM\n",
1820 __func__);
1821 }
1822
1823 return (error);
1824#undef URTWN_CHK
1825}
1826
1827static int
1828urtwn_efuse_switch_power(struct urtwn_softc *sc)
1829{
1830 usb_error_t error;
1831 uint32_t reg;
1832
1833 error = urtwn_write_1(sc, R92C_EFUSE_ACCESS, R92C_EFUSE_ACCESS_ON);
1834 if (error != USB_ERR_NORMAL_COMPLETION)
1835 return (EIO);
1836
1837 reg = urtwn_read_2(sc, R92C_SYS_ISO_CTRL);
1838 if (!(reg & R92C_SYS_ISO_CTRL_PWC_EV12V)) {
1839 error = urtwn_write_2(sc, R92C_SYS_ISO_CTRL,
1840 reg | R92C_SYS_ISO_CTRL_PWC_EV12V);
1841 if (error != USB_ERR_NORMAL_COMPLETION)
1842 return (EIO);
1843 }
1844 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN);
1845 if (!(reg & R92C_SYS_FUNC_EN_ELDR)) {
1846 error = urtwn_write_2(sc, R92C_SYS_FUNC_EN,
1847 reg | R92C_SYS_FUNC_EN_ELDR);
1848 if (error != USB_ERR_NORMAL_COMPLETION)
1849 return (EIO);
1850 }
1851 reg = urtwn_read_2(sc, R92C_SYS_CLKR);
1852 if ((reg & (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) !=
1853 (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) {
1854 error = urtwn_write_2(sc, R92C_SYS_CLKR,
1855 reg | R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M);
1856 if (error != USB_ERR_NORMAL_COMPLETION)
1857 return (EIO);
1858 }
1859
1860 return (0);
1861}
1862
1863static int
1864urtwn_read_chipid(struct urtwn_softc *sc)
1865{
1866 uint32_t reg;
1867
1868 if (sc->chip & URTWN_CHIP_88E)
1869 return (0);
1870
1871 reg = urtwn_read_4(sc, R92C_SYS_CFG);
1872 if (reg & R92C_SYS_CFG_TRP_VAUX_EN)
1873 return (EIO);
1874
1875 if (reg & R92C_SYS_CFG_TYPE_92C) {
1876 sc->chip |= URTWN_CHIP_92C;
1877 /* Check if it is a castrated 8192C. */
1878 if (MS(urtwn_read_4(sc, R92C_HPON_FSM),
1879 R92C_HPON_FSM_CHIP_BONDING_ID) ==
1880 R92C_HPON_FSM_CHIP_BONDING_ID_92C_1T2R)
1881 sc->chip |= URTWN_CHIP_92C_1T2R;
1882 }
1883 if (reg & R92C_SYS_CFG_VENDOR_UMC) {
1884 sc->chip |= URTWN_CHIP_UMC;
1885 if (MS(reg, R92C_SYS_CFG_CHIP_VER_RTL) == 0)
1886 sc->chip |= URTWN_CHIP_UMC_A_CUT;
1887 }
1888 return (0);
1889}
1890
1891static int
1892urtwn_read_rom(struct urtwn_softc *sc)
1893{
1894 struct r92c_rom *rom = &sc->rom.r92c_rom;
1895 int error;
1896
1897 /* Read full ROM image. */
1898 error = urtwn_efuse_read(sc, (uint8_t *)rom, sizeof(*rom));
1899 if (error != 0)
1900 return (error);
1901
1902 /* XXX Weird but this is what the vendor driver does. */
1903 sc->last_rom_addr = 0x1fa;
1904 error = urtwn_efuse_read_next(sc, &sc->pa_setting);
1905 if (error != 0)
1906 return (error);
1907 URTWN_DPRINTF(sc, URTWN_DEBUG_ROM, "%s: PA setting=0x%x\n", __func__,
1908 sc->pa_setting);
1909
1910 sc->board_type = MS(rom->rf_opt1, R92C_ROM_RF1_BOARD_TYPE);
1911
1912 sc->regulatory = MS(rom->rf_opt1, R92C_ROM_RF1_REGULATORY);
1913 URTWN_DPRINTF(sc, URTWN_DEBUG_ROM, "%s: regulatory type=%d\n",
1914 __func__, sc->regulatory);
1915 IEEE80211_ADDR_COPY(sc->sc_ic.ic_macaddr, rom->macaddr);
1916
1917 sc->sc_rf_write = urtwn_r92c_rf_write;
1918 sc->sc_power_on = urtwn_r92c_power_on;
1919 sc->sc_power_off = urtwn_r92c_power_off;
1920
1921 return (0);
1922}
1923
1924static int
1925urtwn_r88e_read_rom(struct urtwn_softc *sc)
1926{
1927 struct r88e_rom *rom = &sc->rom.r88e_rom;
1928 int error;
1929
1930 error = urtwn_efuse_read(sc, (uint8_t *)rom, sizeof(sc->rom.r88e_rom));
1931 if (error != 0)
1932 return (error);
1933
1934 sc->bw20_tx_pwr_diff = (rom->tx_pwr_diff >> 4);
1935 if (sc->bw20_tx_pwr_diff & 0x08)
1936 sc->bw20_tx_pwr_diff |= 0xf0;
1937 sc->ofdm_tx_pwr_diff = (rom->tx_pwr_diff & 0xf);
1938 if (sc->ofdm_tx_pwr_diff & 0x08)
1939 sc->ofdm_tx_pwr_diff |= 0xf0;
1940 sc->regulatory = MS(rom->rf_board_opt, R92C_ROM_RF1_REGULATORY);
1941 URTWN_DPRINTF(sc, URTWN_DEBUG_ROM, "%s: regulatory type %d\n",
1942 __func__,sc->regulatory);
1943 IEEE80211_ADDR_COPY(sc->sc_ic.ic_macaddr, rom->macaddr);
1944
1945 sc->sc_rf_write = urtwn_r88e_rf_write;
1946 sc->sc_power_on = urtwn_r88e_power_on;
1947 sc->sc_power_off = urtwn_r88e_power_off;
1948
1949 return (0);
1950}
1951
1952static __inline uint8_t
1953rate2ridx(uint8_t rate)
1954{
1955 if (rate & IEEE80211_RATE_MCS) {
1956 /* 11n rates start at idx 12 */
1957 return ((rate & 0xf) + 12);
1958 }
1959 switch (rate) {
1960 /* 11g */
1961 case 12: return 4;
1962 case 18: return 5;
1963 case 24: return 6;
1964 case 36: return 7;
1965 case 48: return 8;
1966 case 72: return 9;
1967 case 96: return 10;
1968 case 108: return 11;
1969 /* 11b */
1970 case 2: return 0;
1971 case 4: return 1;
1972 case 11: return 2;
1973 case 22: return 3;
1974 default: return URTWN_RIDX_UNKNOWN;
1975 }
1976}
1977
1978/*
1979 * Initialize rate adaptation in firmware.
1980 */
1981static int
1982urtwn_ra_init(struct urtwn_softc *sc)
1983{
1984 struct ieee80211com *ic = &sc->sc_ic;
1985 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps);
1986 struct ieee80211_node *ni;
1987 struct ieee80211_rateset *rs, *rs_ht;
1988 struct r92c_fw_cmd_macid_cfg cmd;
1989 uint32_t rates, basicrates;
1990 uint8_t mode, ridx;
1991 int maxrate, maxbasicrate, error, i;
1992
1993 ni = ieee80211_ref_node(vap->iv_bss);
1994 rs = &ni->ni_rates;
1995 rs_ht = (struct ieee80211_rateset *) &ni->ni_htrates;
1996
1997 /* Get normal and basic rates mask. */
1998 rates = basicrates = 0;
1999 maxrate = maxbasicrate = 0;
2000
2001 /* This is for 11bg */
2002 for (i = 0; i < rs->rs_nrates; i++) {
2003 /* Convert 802.11 rate to HW rate index. */
2004 ridx = rate2ridx(IEEE80211_RV(rs->rs_rates[i]));
2005 if (ridx == URTWN_RIDX_UNKNOWN) /* Unknown rate, skip. */
2006 continue;
2007 rates |= 1 << ridx;
2008 if (ridx > maxrate)
2009 maxrate = ridx;
2010 if (rs->rs_rates[i] & IEEE80211_RATE_BASIC) {
2011 basicrates |= 1 << ridx;
2012 if (ridx > maxbasicrate)
2013 maxbasicrate = ridx;
2014 }
2015 }
2016
2017 /* If we're doing 11n, enable 11n rates */
2018 if (ni->ni_flags & IEEE80211_NODE_HT) {
2019 for (i = 0; i < rs_ht->rs_nrates; i++) {
2020 if ((rs_ht->rs_rates[i] & 0x7f) > 0xf)
2021 continue;
2022 /* 11n rates start at index 12 */
2023 ridx = ((rs_ht->rs_rates[i]) & 0xf) + 12;
2024 rates |= (1 << ridx);
2025
2026 /* Guard against the rate table being oddly ordered */
2027 if (ridx > maxrate)
2028 maxrate = ridx;
2029 }
2030 }
2031
2032#if 0
2033 if (ic->ic_curmode == IEEE80211_MODE_11NG)
2034 raid = R92C_RAID_11GN;
2035#endif
2036 /* NB: group addressed frames are done at 11bg rates for now */
2037 if (ic->ic_curmode == IEEE80211_MODE_11B)
2038 mode = R92C_RAID_11B;
2039 else
2040 mode = R92C_RAID_11BG;
2041 /* XXX misleading 'mode' value here for unicast frames */
2042 URTWN_DPRINTF(sc, URTWN_DEBUG_RA,
2043 "%s: mode 0x%x, rates 0x%08x, basicrates 0x%08x\n", __func__,
2044 mode, rates, basicrates);
2045
2046 /* Set rates mask for group addressed frames. */
2047 cmd.macid = URTWN_MACID_BC | URTWN_MACID_VALID;
2048 cmd.mask = htole32(mode << 28 | basicrates);
2049 error = urtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd));
2050 if (error != 0) {
2051 ieee80211_free_node(ni);
2052 device_printf(sc->sc_dev,
2053 "could not add broadcast station\n");
2054 return (error);
2055 }
2056
2057 /* Set initial MRR rate. */
2058 URTWN_DPRINTF(sc, URTWN_DEBUG_RA, "%s: maxbasicrate %d\n", __func__,
2059 maxbasicrate);
2060 urtwn_write_1(sc, R92C_INIDATA_RATE_SEL(URTWN_MACID_BC),
2061 maxbasicrate);
2062
2063 /* Set rates mask for unicast frames. */
2064 if (ni->ni_flags & IEEE80211_NODE_HT)
2065 mode = R92C_RAID_11GN;
2066 else if (ic->ic_curmode == IEEE80211_MODE_11B)
2067 mode = R92C_RAID_11B;
2068 else
2069 mode = R92C_RAID_11BG;
2070 cmd.macid = URTWN_MACID_BSS | URTWN_MACID_VALID;
2071 cmd.mask = htole32(mode << 28 | rates);
2072 error = urtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd));
2073 if (error != 0) {
2074 ieee80211_free_node(ni);
2075 device_printf(sc->sc_dev, "could not add BSS station\n");
2076 return (error);
2077 }
2078 /* Set initial MRR rate. */
2079 URTWN_DPRINTF(sc, URTWN_DEBUG_RA, "%s: maxrate %d\n", __func__,
2080 maxrate);
2081 urtwn_write_1(sc, R92C_INIDATA_RATE_SEL(URTWN_MACID_BSS),
2082 maxrate);
2083
2084 /* Indicate highest supported rate. */
2085 if (ni->ni_flags & IEEE80211_NODE_HT)
2086 ni->ni_txrate = rs_ht->rs_rates[rs_ht->rs_nrates - 1]
2087 | IEEE80211_RATE_MCS;
2088 else
2089 ni->ni_txrate = rs->rs_rates[rs->rs_nrates - 1];
2090 ieee80211_free_node(ni);
2091
2092 return (0);
2093}
2094
2095static void
2096urtwn_init_beacon(struct urtwn_softc *sc, struct urtwn_vap *uvp)
2097{
2098 struct r92c_tx_desc *txd = &uvp->bcn_desc;
2099
2100 txd->txdw0 = htole32(
2101 SM(R92C_TXDW0_OFFSET, sizeof(*txd)) | R92C_TXDW0_BMCAST |
2102 R92C_TXDW0_OWN | R92C_TXDW0_FSG | R92C_TXDW0_LSG);
2103 txd->txdw1 = htole32(
2104 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_BEACON) |
2105 SM(R92C_TXDW1_RAID, R92C_RAID_11B));
2106
2107 if (sc->chip & URTWN_CHIP_88E) {
2108 txd->txdw1 |= htole32(SM(R88E_TXDW1_MACID, URTWN_MACID_BC));
2109 txd->txdseq |= htole16(R88E_TXDSEQ_HWSEQ_EN);
2110 } else {
2111 txd->txdw1 |= htole32(SM(R92C_TXDW1_MACID, URTWN_MACID_BC));
2112 txd->txdw4 |= htole32(R92C_TXDW4_HWSEQ_EN);
2113 }
2114
2115 txd->txdw4 = htole32(R92C_TXDW4_DRVRATE);
2116 txd->txdw5 = htole32(SM(R92C_TXDW5_DATARATE, URTWN_RIDX_CCK1));
2117}
2118
2119static int
2120urtwn_setup_beacon(struct urtwn_softc *sc, struct ieee80211_node *ni)
2121{
2122 struct ieee80211vap *vap = ni->ni_vap;
2123 struct urtwn_vap *uvp = URTWN_VAP(vap);
2124 struct mbuf *m;
2125 int error;
2126
2127 URTWN_ASSERT_LOCKED(sc);
2128
2129 if (ni->ni_chan == IEEE80211_CHAN_ANYC)
2130 return (EINVAL);
2131
2132 m = ieee80211_beacon_alloc(ni);
2133 if (m == NULL) {
2134 device_printf(sc->sc_dev,
2135 "%s: could not allocate beacon frame\n", __func__);
2136 return (ENOMEM);
2137 }
2138
2139 if (uvp->bcn_mbuf != NULL)
2140 m_freem(uvp->bcn_mbuf);
2141
2142 uvp->bcn_mbuf = m;
2143
2144 if ((error = urtwn_tx_beacon(sc, uvp)) != 0)
2145 return (error);
2146
2147 /* XXX bcnq stuck workaround */
2148 if ((error = urtwn_tx_beacon(sc, uvp)) != 0)
2149 return (error);
2150
2151 URTWN_DPRINTF(sc, URTWN_DEBUG_BEACON, "%s: beacon was %srecognized\n",
2152 __func__, urtwn_read_1(sc, R92C_TDECTRL + 2) &
2153 (R92C_TDECTRL_BCN_VALID >> 16) ? "" : "not ");
2154
2155 return (0);
2156}
2157
2158static void
2159urtwn_update_beacon(struct ieee80211vap *vap, int item)
2160{
2161 struct urtwn_softc *sc = vap->iv_ic->ic_softc;
2162 struct urtwn_vap *uvp = URTWN_VAP(vap);
2163 struct ieee80211_beacon_offsets *bo = &vap->iv_bcn_off;
2164 struct ieee80211_node *ni = vap->iv_bss;
2165 int mcast = 0;
2166
2167 URTWN_LOCK(sc);
2168 if (uvp->bcn_mbuf == NULL) {
2169 uvp->bcn_mbuf = ieee80211_beacon_alloc(ni);
2170 if (uvp->bcn_mbuf == NULL) {
2171 device_printf(sc->sc_dev,
2172 "%s: could not allocate beacon frame\n", __func__);
2173 URTWN_UNLOCK(sc);
2174 return;
2175 }
2176 }
2177 URTWN_UNLOCK(sc);
2178
2179 if (item == IEEE80211_BEACON_TIM)
2180 mcast = 1; /* XXX */
2181
2182 setbit(bo->bo_flags, item);
2183 ieee80211_beacon_update(ni, uvp->bcn_mbuf, mcast);
2184
2185 URTWN_LOCK(sc);
2186 urtwn_tx_beacon(sc, uvp);
2187 URTWN_UNLOCK(sc);
2188}
2189
2190/*
2191 * Push a beacon frame into the chip. Beacon will
2192 * be repeated by the chip every R92C_BCN_INTERVAL.
2193 */
2194static int
2195urtwn_tx_beacon(struct urtwn_softc *sc, struct urtwn_vap *uvp)
2196{
2197 struct r92c_tx_desc *desc = &uvp->bcn_desc;
2198 struct urtwn_data *bf;
2199
2200 URTWN_ASSERT_LOCKED(sc);
2201
2202 bf = urtwn_getbuf(sc);
2203 if (bf == NULL)
2204 return (ENOMEM);
2205
2206 memcpy(bf->buf, desc, sizeof(*desc));
2207 urtwn_tx_start(sc, uvp->bcn_mbuf, IEEE80211_FC0_TYPE_MGT, bf);
2208
2209 sc->sc_txtimer = 5;
2210 callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc);
2211
2212 return (0);
2213}
2214
2215static int
2216urtwn_key_alloc(struct ieee80211vap *vap, struct ieee80211_key *k,
2217 ieee80211_keyix *keyix, ieee80211_keyix *rxkeyix)
2218{
2219 struct urtwn_softc *sc = vap->iv_ic->ic_softc;
2220 uint8_t i;
2221
2222 if (!(&vap->iv_nw_keys[0] <= k &&
2223 k < &vap->iv_nw_keys[IEEE80211_WEP_NKID])) {
2224 if (!(k->wk_flags & IEEE80211_KEY_SWCRYPT)) {
2225 URTWN_LOCK(sc);
2226 /*
2227 * First 4 slots for group keys,
2228 * what is left - for pairwise.
2229 * XXX incompatible with IBSS RSN.
2230 */
2231 for (i = IEEE80211_WEP_NKID;
2232 i < R92C_CAM_ENTRY_COUNT; i++) {
2233 if ((sc->keys_bmap & (1 << i)) == 0) {
2234 sc->keys_bmap |= 1 << i;
2235 *keyix = i;
2236 break;
2237 }
2238 }
2239 URTWN_UNLOCK(sc);
2240 if (i == R92C_CAM_ENTRY_COUNT) {
2241 device_printf(sc->sc_dev,
2242 "%s: no free space in the key table\n",
2243 __func__);
2244 return 0;
2245 }
2246 } else
2247 *keyix = 0;
2248 } else {
2249 *keyix = k - vap->iv_nw_keys;
2250 }
2251 *rxkeyix = *keyix;
2252 return 1;
2253}
2254
2255static void
2256urtwn_key_set_cb(struct urtwn_softc *sc, union sec_param *data)
2257{
2258 struct ieee80211_key *k = &data->key;
2259 uint8_t algo, keyid;
2260 int i, error;
2261
2262 if (k->wk_keyix < IEEE80211_WEP_NKID)
2263 keyid = k->wk_keyix;
2264 else
2265 keyid = 0;
2266
2267 /* Map net80211 cipher to HW crypto algorithm. */
2268 switch (k->wk_cipher->ic_cipher) {
2269 case IEEE80211_CIPHER_WEP:
2270 if (k->wk_keylen < 8)
2271 algo = R92C_CAM_ALGO_WEP40;
2272 else
2273 algo = R92C_CAM_ALGO_WEP104;
2274 break;
2275 case IEEE80211_CIPHER_TKIP:
2276 algo = R92C_CAM_ALGO_TKIP;
2277 break;
2278 case IEEE80211_CIPHER_AES_CCM:
2279 algo = R92C_CAM_ALGO_AES;
2280 break;
2281 default:
2282 device_printf(sc->sc_dev, "%s: undefined cipher %d\n",
2283 __func__, k->wk_cipher->ic_cipher);
2284 return;
2285 }
2286
2287 URTWN_DPRINTF(sc, URTWN_DEBUG_KEY,
2288 "%s: keyix %d, keyid %d, algo %d/%d, flags %04X, len %d, "
2289 "macaddr %s\n", __func__, k->wk_keyix, keyid,
2290 k->wk_cipher->ic_cipher, algo, k->wk_flags, k->wk_keylen,
2291 ether_sprintf(k->wk_macaddr));
2292
2293 /* Write key. */
2294 for (i = 0; i < 4; i++) {
2295 error = urtwn_cam_write(sc, R92C_CAM_KEY(k->wk_keyix, i),
2296 le32dec(&k->wk_key[i * 4]));
2297 if (error != 0)
2298 goto fail;
2299 }
2300
2301 /* Write CTL0 last since that will validate the CAM entry. */
2302 error = urtwn_cam_write(sc, R92C_CAM_CTL1(k->wk_keyix),
2303 le32dec(&k->wk_macaddr[2]));
2304 if (error != 0)
2305 goto fail;
2306 error = urtwn_cam_write(sc, R92C_CAM_CTL0(k->wk_keyix),
2307 SM(R92C_CAM_ALGO, algo) |
2308 SM(R92C_CAM_KEYID, keyid) |
2309 SM(R92C_CAM_MACLO, le16dec(&k->wk_macaddr[0])) |
2310 R92C_CAM_VALID);
2311 if (error != 0)
2312 goto fail;
2313
2314 return;
2315
2316fail:
2317 device_printf(sc->sc_dev, "%s fails, error %d\n", __func__, error);
2318}
2319
2320static void
2321urtwn_key_del_cb(struct urtwn_softc *sc, union sec_param *data)
2322{
2323 struct ieee80211_key *k = &data->key;
2324 int i;
2325
2326 URTWN_DPRINTF(sc, URTWN_DEBUG_KEY,
2327 "%s: keyix %d, flags %04X, macaddr %s\n", __func__,
2328 k->wk_keyix, k->wk_flags, ether_sprintf(k->wk_macaddr));
2329
2330 urtwn_cam_write(sc, R92C_CAM_CTL0(k->wk_keyix), 0);
2331 urtwn_cam_write(sc, R92C_CAM_CTL1(k->wk_keyix), 0);
2332
2333 /* Clear key. */
2334 for (i = 0; i < 4; i++)
2335 urtwn_cam_write(sc, R92C_CAM_KEY(k->wk_keyix, i), 0);
2336 sc->keys_bmap &= ~(1 << k->wk_keyix);
2337}
2338
2339static int
2340urtwn_key_set(struct ieee80211vap *vap, const struct ieee80211_key *k)
2341{
2342 struct urtwn_softc *sc = vap->iv_ic->ic_softc;
2343
2344 if (k->wk_flags & IEEE80211_KEY_SWCRYPT) {
2345 /* Not for us. */
2346 return (1);
2347 }
2348
2349 return (!urtwn_cmd_sleepable(sc, k, sizeof(*k), urtwn_key_set_cb));
2350}
2351
2352static int
2353urtwn_key_delete(struct ieee80211vap *vap, const struct ieee80211_key *k)
2354{
2355 struct urtwn_softc *sc = vap->iv_ic->ic_softc;
2356
2357 if (k->wk_flags & IEEE80211_KEY_SWCRYPT) {
2358 /* Not for us. */
2359 return (1);
2360 }
2361
2362 return (!urtwn_cmd_sleepable(sc, k, sizeof(*k), urtwn_key_del_cb));
2363}
2364
2365static void
2366urtwn_tsf_task_adhoc(void *arg, int pending)
2367{
2368 struct ieee80211vap *vap = arg;
2369 struct urtwn_softc *sc = vap->iv_ic->ic_softc;
2370 struct ieee80211_node *ni;
2371 uint32_t reg;
2372
2373 URTWN_LOCK(sc);
2374 ni = ieee80211_ref_node(vap->iv_bss);
2375 reg = urtwn_read_1(sc, R92C_BCN_CTRL);
2376
2377 /* Accept beacons with the same BSSID. */
2378 urtwn_set_rx_bssid_all(sc, 0);
2379
2380 /* Enable synchronization. */
2381 reg &= ~R92C_BCN_CTRL_DIS_TSF_UDT0;
2382 urtwn_write_1(sc, R92C_BCN_CTRL, reg);
2383
2384 /* Synchronize. */
2385 usb_pause_mtx(&sc->sc_mtx, hz * ni->ni_intval * 5 / 1000);
2386
2387 /* Disable synchronization. */
2388 reg |= R92C_BCN_CTRL_DIS_TSF_UDT0;
2389 urtwn_write_1(sc, R92C_BCN_CTRL, reg);
2390
2391 /* Remove beacon filter. */
2392 urtwn_set_rx_bssid_all(sc, 1);
2393
2394 /* Enable beaconing. */
2395 urtwn_write_1(sc, R92C_MBID_NUM,
2396 urtwn_read_1(sc, R92C_MBID_NUM) | R92C_MBID_TXBCN_RPT0);
2397 reg |= R92C_BCN_CTRL_EN_BCN;
2398
2399 urtwn_write_1(sc, R92C_BCN_CTRL, reg);
2400 ieee80211_free_node(ni);
2401 URTWN_UNLOCK(sc);
2402}
2403
2404static void
2405urtwn_tsf_sync_enable(struct urtwn_softc *sc, struct ieee80211vap *vap)
2406{
2407 struct ieee80211com *ic = &sc->sc_ic;
2408 struct urtwn_vap *uvp = URTWN_VAP(vap);
2409
2410 /* Reset TSF. */
2411 urtwn_write_1(sc, R92C_DUAL_TSF_RST, R92C_DUAL_TSF_RST0);
2412
2413 switch (vap->iv_opmode) {
2414 case IEEE80211_M_STA:
2415 /* Enable TSF synchronization. */
2416 urtwn_write_1(sc, R92C_BCN_CTRL,
2417 urtwn_read_1(sc, R92C_BCN_CTRL) &
2418 ~R92C_BCN_CTRL_DIS_TSF_UDT0);
2419 break;
2420 case IEEE80211_M_IBSS:
2421 ieee80211_runtask(ic, &uvp->tsf_task_adhoc);
2422 break;
2423 case IEEE80211_M_HOSTAP:
2424 /* Enable beaconing. */
2425 urtwn_write_1(sc, R92C_MBID_NUM,
2426 urtwn_read_1(sc, R92C_MBID_NUM) | R92C_MBID_TXBCN_RPT0);
2427 urtwn_write_1(sc, R92C_BCN_CTRL,
2428 urtwn_read_1(sc, R92C_BCN_CTRL) | R92C_BCN_CTRL_EN_BCN);
2429 break;
2430 default:
2431 device_printf(sc->sc_dev, "undefined opmode %d\n",
2432 vap->iv_opmode);
2433 return;
2434 }
2435}
2436
2437static void
2438urtwn_get_tsf(struct urtwn_softc *sc, uint64_t *buf)
2439{
2440 urtwn_read_region_1(sc, R92C_TSFTR, (uint8_t *)buf, sizeof(*buf));
2441}
2442
2443static void
2444urtwn_set_led(struct urtwn_softc *sc, int led, int on)
2445{
2446 uint8_t reg;
2447
2448 if (led == URTWN_LED_LINK) {
2449 if (sc->chip & URTWN_CHIP_88E) {
2450 reg = urtwn_read_1(sc, R92C_LEDCFG2) & 0xf0;
2451 urtwn_write_1(sc, R92C_LEDCFG2, reg | 0x60);
2452 if (!on) {
2453 reg = urtwn_read_1(sc, R92C_LEDCFG2) & 0x90;
2454 urtwn_write_1(sc, R92C_LEDCFG2,
2455 reg | R92C_LEDCFG0_DIS);
2456 urtwn_write_1(sc, R92C_MAC_PINMUX_CFG,
2457 urtwn_read_1(sc, R92C_MAC_PINMUX_CFG) &
2458 0xfe);
2459 }
2460 } else {
2461 reg = urtwn_read_1(sc, R92C_LEDCFG0) & 0x70;
2462 if (!on)
2463 reg |= R92C_LEDCFG0_DIS;
2464 urtwn_write_1(sc, R92C_LEDCFG0, reg);
2465 }
2466 sc->ledlink = on; /* Save LED state. */
2467 }
2468}
2469
2470static void
2471urtwn_set_mode(struct urtwn_softc *sc, uint8_t mode)
2472{
2473 uint8_t reg;
2474
2475 reg = urtwn_read_1(sc, R92C_MSR);
2476 reg = (reg & ~R92C_MSR_MASK) | mode;
2477 urtwn_write_1(sc, R92C_MSR, reg);
2478}
2479
2480static void
2481urtwn_ibss_recv_mgmt(struct ieee80211_node *ni, struct mbuf *m, int subtype,
2482 const struct ieee80211_rx_stats *rxs,
2483 int rssi, int nf)
2484{
2485 struct ieee80211vap *vap = ni->ni_vap;
2486 struct urtwn_softc *sc = vap->iv_ic->ic_softc;
2487 struct urtwn_vap *uvp = URTWN_VAP(vap);
2488 uint64_t ni_tstamp, curr_tstamp;
2489
2490 uvp->recv_mgmt(ni, m, subtype, rxs, rssi, nf);
2491
2492 if (vap->iv_state == IEEE80211_S_RUN &&
2493 (subtype == IEEE80211_FC0_SUBTYPE_BEACON ||
2494 subtype == IEEE80211_FC0_SUBTYPE_PROBE_RESP)) {
2495 ni_tstamp = le64toh(ni->ni_tstamp.tsf);
2496 URTWN_LOCK(sc);
2497 urtwn_get_tsf(sc, &curr_tstamp);
2498 URTWN_UNLOCK(sc);
2499 curr_tstamp = le64toh(curr_tstamp);
2500
2501 if (ni_tstamp >= curr_tstamp)
2502 (void) ieee80211_ibss_merge(ni);
2503 }
2504}
2505
2506static int
2507urtwn_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg)
2508{
2509 struct urtwn_vap *uvp = URTWN_VAP(vap);
2510 struct ieee80211com *ic = vap->iv_ic;
2511 struct urtwn_softc *sc = ic->ic_softc;
2512 struct ieee80211_node *ni;
2513 enum ieee80211_state ostate;
2514 uint32_t reg;
2515 uint8_t mode;
2516 int error = 0;
2517
2518 ostate = vap->iv_state;
2519 URTWN_DPRINTF(sc, URTWN_DEBUG_STATE, "%s -> %s\n",
2520 ieee80211_state_name[ostate], ieee80211_state_name[nstate]);
2521
2522 IEEE80211_UNLOCK(ic);
2523 URTWN_LOCK(sc);
2524 callout_stop(&sc->sc_watchdog_ch);
2525
2526 if (ostate == IEEE80211_S_RUN) {
2527 /* Stop calibration. */
2528 callout_stop(&sc->sc_calib_to);
2529
2530 /* Turn link LED off. */
2531 urtwn_set_led(sc, URTWN_LED_LINK, 0);
2532
2533 /* Set media status to 'No Link'. */
2534 urtwn_set_mode(sc, R92C_MSR_NOLINK);
2535
2536 /* Stop Rx of data frames. */
2537 urtwn_write_2(sc, R92C_RXFLTMAP2, 0);
2538
2539 /* Disable TSF synchronization. */
2540 urtwn_write_1(sc, R92C_BCN_CTRL,
2541 (urtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_EN_BCN) |
2542 R92C_BCN_CTRL_DIS_TSF_UDT0);
2543
2544 /* Disable beaconing. */
2545 urtwn_write_1(sc, R92C_MBID_NUM,
2546 urtwn_read_1(sc, R92C_MBID_NUM) & ~R92C_MBID_TXBCN_RPT0);
2547
2548 /* Reset TSF. */
2549 urtwn_write_1(sc, R92C_DUAL_TSF_RST, R92C_DUAL_TSF_RST0);
2550
2551 /* Reset EDCA parameters. */
2552 urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002f3217);
2553 urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005e4317);
2554 urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x00105320);
2555 urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a444);
2556 }
2557
2558 switch (nstate) {
2559 case IEEE80211_S_INIT:
2560 /* Turn link LED off. */
2561 urtwn_set_led(sc, URTWN_LED_LINK, 0);
2562 break;
2563 case IEEE80211_S_SCAN:
2564 /* Pause AC Tx queues. */
2565 urtwn_write_1(sc, R92C_TXPAUSE,
2566 urtwn_read_1(sc, R92C_TXPAUSE) | R92C_TX_QUEUE_AC);
2567 break;
2568 case IEEE80211_S_AUTH:
2569 urtwn_set_chan(sc, ic->ic_curchan, NULL);
2570 break;
2571 case IEEE80211_S_RUN:
2572 if (vap->iv_opmode == IEEE80211_M_MONITOR) {
2573 /* Turn link LED on. */
2574 urtwn_set_led(sc, URTWN_LED_LINK, 1);
2575 break;
2576 }
2577
2578 ni = ieee80211_ref_node(vap->iv_bss);
2579
2580 if (ic->ic_bsschan == IEEE80211_CHAN_ANYC ||
2581 ni->ni_chan == IEEE80211_CHAN_ANYC) {
2582 device_printf(sc->sc_dev,
2583 "%s: could not move to RUN state\n", __func__);
2584 error = EINVAL;
2585 goto end_run;
2586 }
2587
2588 switch (vap->iv_opmode) {
2589 case IEEE80211_M_STA:
2590 mode = R92C_MSR_INFRA;
2591 break;
2592 case IEEE80211_M_IBSS:
2593 mode = R92C_MSR_ADHOC;
2594 break;
2595 case IEEE80211_M_HOSTAP:
2596 mode = R92C_MSR_AP;
2597 break;
2598 default:
2599 device_printf(sc->sc_dev, "undefined opmode %d\n",
2600 vap->iv_opmode);
2601 error = EINVAL;
2602 goto end_run;
2603 }
2604
2605 /* Set media status to 'Associated'. */
2606 urtwn_set_mode(sc, mode);
2607
2608 /* Set BSSID. */
2609 urtwn_write_4(sc, R92C_BSSID + 0, le32dec(&ni->ni_bssid[0]));
2610 urtwn_write_4(sc, R92C_BSSID + 4, le16dec(&ni->ni_bssid[4]));
2611
2612 if (ic->ic_curmode == IEEE80211_MODE_11B)
2613 urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 0);
2614 else /* 802.11b/g */
2615 urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 3);
2616
2617 /* Enable Rx of data frames. */
2618 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff);
2619
2620 /* Flush all AC queues. */
2621 urtwn_write_1(sc, R92C_TXPAUSE, 0);
2622
2623 /* Set beacon interval. */
2624 urtwn_write_2(sc, R92C_BCN_INTERVAL, ni->ni_intval);
2625
2626 /* Allow Rx from our BSSID only. */
2627 if (ic->ic_promisc == 0) {
2628 reg = urtwn_read_4(sc, R92C_RCR);
2629
2630 if (vap->iv_opmode != IEEE80211_M_HOSTAP)
2631 reg |= R92C_RCR_CBSSID_DATA;
2632 if (vap->iv_opmode != IEEE80211_M_IBSS)
2633 reg |= R92C_RCR_CBSSID_BCN;
2634
2635 urtwn_write_4(sc, R92C_RCR, reg);
2636 }
2637
2638 if (vap->iv_opmode == IEEE80211_M_HOSTAP ||
2639 vap->iv_opmode == IEEE80211_M_IBSS) {
2640 error = urtwn_setup_beacon(sc, ni);
2641 if (error != 0) {
2642 device_printf(sc->sc_dev,
2643 "unable to push beacon into the chip, "
2644 "error %d\n", error);
2645 goto end_run;
2646 }
2647 }
2648
2649 /* Enable TSF synchronization. */
2650 urtwn_tsf_sync_enable(sc, vap);
2651
2652 urtwn_write_1(sc, R92C_SIFS_CCK + 1, 10);
2653 urtwn_write_1(sc, R92C_SIFS_OFDM + 1, 10);
2654 urtwn_write_1(sc, R92C_SPEC_SIFS + 1, 10);
2655 urtwn_write_1(sc, R92C_MAC_SPEC_SIFS + 1, 10);
2656 urtwn_write_1(sc, R92C_R2T_SIFS + 1, 10);
2657 urtwn_write_1(sc, R92C_T2T_SIFS + 1, 10);
2658
2659 /* Intialize rate adaptation. */
2660 if (!(sc->chip & URTWN_CHIP_88E))
2661 urtwn_ra_init(sc);
2662 /* Turn link LED on. */
2663 urtwn_set_led(sc, URTWN_LED_LINK, 1);
2664
2665 sc->avg_pwdb = -1; /* Reset average RSSI. */
2666 /* Reset temperature calibration state machine. */
2667 sc->sc_flags &= ~URTWN_TEMP_MEASURED;
2668 sc->thcal_lctemp = 0;
2669 /* Start periodic calibration. */
2670 callout_reset(&sc->sc_calib_to, 2*hz, urtwn_calib_to, sc);
2671
2672end_run:
2673 ieee80211_free_node(ni);
2674 break;
2675 default:
2676 break;
2677 }
2678
2679 URTWN_UNLOCK(sc);
2680 IEEE80211_LOCK(ic);
2681 return (error != 0 ? error : uvp->newstate(vap, nstate, arg));
2682}
2683
2684static void
2685urtwn_calib_to(void *arg)
2686{
2687 struct urtwn_softc *sc = arg;
2688
2689 /* Do it in a process context. */
2690 urtwn_cmd_sleepable(sc, NULL, 0, urtwn_calib_cb);
2691}
2692
2693static void
2694urtwn_calib_cb(struct urtwn_softc *sc, union sec_param *data)
2695{
2696 /* Do temperature compensation. */
2697 urtwn_temp_calib(sc);
2698
2699 if ((urtwn_read_1(sc, R92C_MSR) & R92C_MSR_MASK) != R92C_MSR_NOLINK)
2700 callout_reset(&sc->sc_calib_to, 2*hz, urtwn_calib_to, sc);
2701}
2702
2703static void
2704urtwn_watchdog(void *arg)
2705{
2706 struct urtwn_softc *sc = arg;
2707
2708 if (sc->sc_txtimer > 0) {
2709 if (--sc->sc_txtimer == 0) {
2710 device_printf(sc->sc_dev, "device timeout\n");
2711 counter_u64_add(sc->sc_ic.ic_oerrors, 1);
2712 return;
2713 }
2714 callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc);
2715 }
2716}
2717
2718static void
2719urtwn_update_avgrssi(struct urtwn_softc *sc, int rate, int8_t rssi)
2720{
2721 int pwdb;
2722
2723 /* Convert antenna signal to percentage. */
2724 if (rssi <= -100 || rssi >= 20)
2725 pwdb = 0;
2726 else if (rssi >= 0)
2727 pwdb = 100;
2728 else
2729 pwdb = 100 + rssi;
2730 if (!(sc->chip & URTWN_CHIP_88E)) {
2731 if (rate <= URTWN_RIDX_CCK11) {
2732 /* CCK gain is smaller than OFDM/MCS gain. */
2733 pwdb += 6;
2734 if (pwdb > 100)
2735 pwdb = 100;
2736 if (pwdb <= 14)
2737 pwdb -= 4;
2738 else if (pwdb <= 26)
2739 pwdb -= 8;
2740 else if (pwdb <= 34)
2741 pwdb -= 6;
2742 else if (pwdb <= 42)
2743 pwdb -= 2;
2744 }
2745 }
2746 if (sc->avg_pwdb == -1) /* Init. */
2747 sc->avg_pwdb = pwdb;
2748 else if (sc->avg_pwdb < pwdb)
2749 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20) + 1;
2750 else
2751 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20);
2752 URTWN_DPRINTF(sc, URTWN_DEBUG_RSSI, "%s: PWDB %d, EMA %d\n", __func__,
2753 pwdb, sc->avg_pwdb);
2754}
2755
2756static int8_t
2757urtwn_get_rssi(struct urtwn_softc *sc, int rate, void *physt)
2758{
2759 static const int8_t cckoff[] = { 16, -12, -26, -46 };
2760 struct r92c_rx_phystat *phy;
2761 struct r92c_rx_cck *cck;
2762 uint8_t rpt;
2763 int8_t rssi;
2764
2765 if (rate <= URTWN_RIDX_CCK11) {
2766 cck = (struct r92c_rx_cck *)physt;
2767 if (sc->sc_flags & URTWN_FLAG_CCK_HIPWR) {
2768 rpt = (cck->agc_rpt >> 5) & 0x3;
2769 rssi = (cck->agc_rpt & 0x1f) << 1;
2770 } else {
2771 rpt = (cck->agc_rpt >> 6) & 0x3;
2772 rssi = cck->agc_rpt & 0x3e;
2773 }
2774 rssi = cckoff[rpt] - rssi;
2775 } else { /* OFDM/HT. */
2776 phy = (struct r92c_rx_phystat *)physt;
2777 rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110;
2778 }
2779 return (rssi);
2780}
2781
2782static int8_t
2783urtwn_r88e_get_rssi(struct urtwn_softc *sc, int rate, void *physt)
2784{
2785 struct r92c_rx_phystat *phy;
2786 struct r88e_rx_cck *cck;
2787 uint8_t cck_agc_rpt, lna_idx, vga_idx;
2788 int8_t rssi;
2789
2790 rssi = 0;
2791 if (rate <= URTWN_RIDX_CCK11) {
2792 cck = (struct r88e_rx_cck *)physt;
2793 cck_agc_rpt = cck->agc_rpt;
2794 lna_idx = (cck_agc_rpt & 0xe0) >> 5;
2795 vga_idx = cck_agc_rpt & 0x1f;
2796 switch (lna_idx) {
2797 case 7:
2798 if (vga_idx <= 27)
2799 rssi = -100 + 2* (27 - vga_idx);
2800 else
2801 rssi = -100;
2802 break;
2803 case 6:
2804 rssi = -48 + 2 * (2 - vga_idx);
2805 break;
2806 case 5:
2807 rssi = -42 + 2 * (7 - vga_idx);
2808 break;
2809 case 4:
2810 rssi = -36 + 2 * (7 - vga_idx);
2811 break;
2812 case 3:
2813 rssi = -24 + 2 * (7 - vga_idx);
2814 break;
2815 case 2:
2816 rssi = -12 + 2 * (5 - vga_idx);
2817 break;
2818 case 1:
2819 rssi = 8 - (2 * vga_idx);
2820 break;
2821 case 0:
2822 rssi = 14 - (2 * vga_idx);
2823 break;
2824 }
2825 rssi += 6;
2826 } else { /* OFDM/HT. */
2827 phy = (struct r92c_rx_phystat *)physt;
2828 rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110;
2829 }
2830 return (rssi);
2831}
2832
2833static int
2834urtwn_tx_data(struct urtwn_softc *sc, struct ieee80211_node *ni,
2835 struct mbuf *m, struct urtwn_data *data)
2836{
2837 const struct ieee80211_txparam *tp;
2838 struct ieee80211com *ic = &sc->sc_ic;
2839 struct ieee80211vap *vap = ni->ni_vap;
2840 struct ieee80211_key *k = NULL;
2841 struct ieee80211_channel *chan;
2842 struct ieee80211_frame *wh;
2843 struct r92c_tx_desc *txd;
2844 uint8_t macid, raid, rate, ridx, type, tid, qos, qsel;
2845 int hasqos, ismcast;
2846
2847 URTWN_ASSERT_LOCKED(sc);
2848
2849 wh = mtod(m, struct ieee80211_frame *);
2850 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK;
2851 hasqos = IEEE80211_QOS_HAS_SEQ(wh);
2852 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1);
2853
2854 /* Select TX ring for this frame. */
2855 if (hasqos) {
2856 qos = ((const struct ieee80211_qosframe *)wh)->i_qos[0];
2857 tid = qos & IEEE80211_QOS_TID;
2858 } else {
2859 qos = 0;
2860 tid = 0;
2861 }
2862
2863 chan = (ni->ni_chan != IEEE80211_CHAN_ANYC) ?
2864 ni->ni_chan : ic->ic_curchan;
2865 tp = &vap->iv_txparms[ieee80211_chan2mode(chan)];
2866
2867 /* Choose a TX rate index. */
2868 if (type == IEEE80211_FC0_TYPE_MGT)
2869 rate = tp->mgmtrate;
2870 else if (ismcast)
2871 rate = tp->mcastrate;
2872 else if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE)
2873 rate = tp->ucastrate;
2874 else if (m->m_flags & M_EAPOL)
2875 rate = tp->mgmtrate;
2876 else {
2877 if (URTWN_CHIP_HAS_RATECTL(sc)) {
2878 /* XXX pass pktlen */
2879 (void) ieee80211_ratectl_rate(ni, NULL, 0);
2880 rate = ni->ni_txrate;
2881 } else {
2882 /* XXX TODO: drop the default rate for 11b/11g? */
2883 if (ni->ni_flags & IEEE80211_NODE_HT)
2884 rate = IEEE80211_RATE_MCS | 0x4; /* MCS4 */
2885 else if (ic->ic_curmode != IEEE80211_MODE_11B)
2886 rate = 108;
2887 else
2888 rate = 22;
2889 }
2890 }
2891
2892 /*
2893 * XXX TODO: this should be per-node, for 11b versus 11bg
2894 * nodes in hostap mode
2895 */
2896 ridx = rate2ridx(rate);
2897 if (ni->ni_flags & IEEE80211_NODE_HT)
2898 raid = R92C_RAID_11GN;
2899 else if (ic->ic_curmode != IEEE80211_MODE_11B)
2900 raid = R92C_RAID_11BG;
2901 else
2902 raid = R92C_RAID_11B;
2903
2904 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) {
2905 k = ieee80211_crypto_encap(ni, m);
2906 if (k == NULL) {
2907 device_printf(sc->sc_dev,
2908 "ieee80211_crypto_encap returns NULL.\n");
2909 return (ENOBUFS);
2910 }
2911
2912 /* in case packet header moved, reset pointer */
2913 wh = mtod(m, struct ieee80211_frame *);
2914 }
2915
2916 /* Fill Tx descriptor. */
2917 txd = (struct r92c_tx_desc *)data->buf;
2918 memset(txd, 0, sizeof(*txd));
2919
2920 txd->txdw0 |= htole32(
2921 SM(R92C_TXDW0_OFFSET, sizeof(*txd)) |
2922 R92C_TXDW0_OWN | R92C_TXDW0_FSG | R92C_TXDW0_LSG);
2923 if (ismcast)
2924 txd->txdw0 |= htole32(R92C_TXDW0_BMCAST);
2925
2926 if (!ismcast) {
2927 /* Unicast frame, check if an ACK is expected. */
2928 if (!qos || (qos & IEEE80211_QOS_ACKPOLICY) !=
2929 IEEE80211_QOS_ACKPOLICY_NOACK) {
2930 txd->txdw5 |= htole32(R92C_TXDW5_RTY_LMT_ENA);
2931 txd->txdw5 |= htole32(SM(R92C_TXDW5_RTY_LMT,
2932 tp->maxretry));
2933 }
2934
2935 if (sc->chip & URTWN_CHIP_88E) {
2936 struct urtwn_node *un = URTWN_NODE(ni);
2937 macid = un->id;
2938 } else
2939 macid = URTWN_MACID_BSS;
2940
2941 if (type == IEEE80211_FC0_TYPE_DATA) {
2942 qsel = tid % URTWN_MAX_TID;
2943
2944 if (sc->chip & URTWN_CHIP_88E) {
2945 txd->txdw2 |= htole32(
2946 R88E_TXDW2_AGGBK |
2947 R88E_TXDW2_CCX_RPT);
2948 } else
2949 txd->txdw1 |= htole32(R92C_TXDW1_AGGBK);
2950
2951 /* protmode, non-HT */
2952 /* XXX TODO: noack frames? */
2953 if ((rate & 0x80) == 0 &&
2954 (ic->ic_flags & IEEE80211_F_USEPROT)) {
2955 switch (ic->ic_protmode) {
2956 case IEEE80211_PROT_CTSONLY:
2957 txd->txdw4 |= htole32(
2958 R92C_TXDW4_CTS2SELF |
2959 R92C_TXDW4_HWRTSEN);
2960 break;
2961 case IEEE80211_PROT_RTSCTS:
2962 txd->txdw4 |= htole32(
2963 R92C_TXDW4_RTSEN |
2964 R92C_TXDW4_HWRTSEN);
2965 break;
2966 default:
2967 break;
2968 }
2969 }
2970
2971 /* protmode, HT */
2972 /* XXX TODO: noack frames? */
2973 if ((rate & 0x80) &&
2974 (ic->ic_htprotmode == IEEE80211_PROT_RTSCTS)) {
2975 txd->txdw4 |= htole32(
2976 R92C_TXDW4_RTSEN |
2977 R92C_TXDW4_HWRTSEN);
2978 }
2979
2980 /* XXX TODO: rtsrate is configurable? 24mbit may
2981 * be a bit high for RTS rate? */
2982 txd->txdw4 |= htole32(SM(R92C_TXDW4_RTSRATE,
2983 URTWN_RIDX_OFDM24));
2984
2985 txd->txdw5 |= htole32(0x0001ff00);
2986 } else /* IEEE80211_FC0_TYPE_MGT */
2987 qsel = R92C_TXDW1_QSEL_MGNT;
2988 } else {
2989 macid = URTWN_MACID_BC;
2990 qsel = R92C_TXDW1_QSEL_MGNT;
2991 }
2992
2993 txd->txdw1 |= htole32(
2994 SM(R92C_TXDW1_QSEL, qsel) |
2995 SM(R92C_TXDW1_RAID, raid));
2996
2997 /* XXX TODO: 40MHZ flag? */
2998 /* XXX TODO: AMPDU flag? (AGG_ENABLE or AGG_BREAK?) Density shift? */
2999 /* XXX Short preamble? */
3000 /* XXX Short-GI? */
3001
3002 if (sc->chip & URTWN_CHIP_88E)
3003 txd->txdw1 |= htole32(SM(R88E_TXDW1_MACID, macid));
3004 else
3005 txd->txdw1 |= htole32(SM(R92C_TXDW1_MACID, macid));
3006
3007 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, ridx));
3008
3009 /* Force this rate if needed. */
3010 if (URTWN_CHIP_HAS_RATECTL(sc) || ismcast ||
3011 (tp->ucastrate != IEEE80211_FIXED_RATE_NONE) ||
3012 (m->m_flags & M_EAPOL) || type != IEEE80211_FC0_TYPE_DATA)
3013 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE);
3014
3015 if (!hasqos) {
3016 /* Use HW sequence numbering for non-QoS frames. */
3017 if (sc->chip & URTWN_CHIP_88E)
3018 txd->txdseq = htole16(R88E_TXDSEQ_HWSEQ_EN);
3019 else
3020 txd->txdw4 |= htole32(R92C_TXDW4_HWSEQ_EN);
3021 } else {
3022 /* Set sequence number. */
3023 txd->txdseq = htole16(M_SEQNO_GET(m) % IEEE80211_SEQ_RANGE);
3024 }
3025
3026 if (k != NULL && !(k->wk_flags & IEEE80211_KEY_SWCRYPT)) {
3027 uint8_t cipher;
3028
3029 switch (k->wk_cipher->ic_cipher) {
3030 case IEEE80211_CIPHER_WEP:
3031 case IEEE80211_CIPHER_TKIP:
3032 cipher = R92C_TXDW1_CIPHER_RC4;
3033 break;
3034 case IEEE80211_CIPHER_AES_CCM:
3035 cipher = R92C_TXDW1_CIPHER_AES;
3036 break;
3037 default:
3038 device_printf(sc->sc_dev, "%s: unknown cipher %d\n",
3039 __func__, k->wk_cipher->ic_cipher);
3040 return (EINVAL);
3041 }
3042
3043 txd->txdw1 |= htole32(SM(R92C_TXDW1_CIPHER, cipher));
3044 }
3045
3046 if (ieee80211_radiotap_active_vap(vap)) {
3047 struct urtwn_tx_radiotap_header *tap = &sc->sc_txtap;
3048
3049 tap->wt_flags = 0;
3050 if (k != NULL)
3051 tap->wt_flags |= IEEE80211_RADIOTAP_F_WEP;
3052 ieee80211_radiotap_tx(vap, m);
3053 }
3054
3055 data->ni = ni;
3056
3057 urtwn_tx_start(sc, m, type, data);
3058
3059 return (0);
3060}
3061
3062static int
3063urtwn_tx_raw(struct urtwn_softc *sc, struct ieee80211_node *ni,
3064 struct mbuf *m, struct urtwn_data *data,
3065 const struct ieee80211_bpf_params *params)
3066{
3067 struct ieee80211vap *vap = ni->ni_vap;
3068 struct ieee80211_key *k = NULL;
3069 struct ieee80211_frame *wh;
3070 struct r92c_tx_desc *txd;
3071 uint8_t cipher, ridx, type;
3072
3073 /* Encrypt the frame if need be. */
3074 cipher = R92C_TXDW1_CIPHER_NONE;
3075 if (params->ibp_flags & IEEE80211_BPF_CRYPTO) {
3076 /* Retrieve key for TX. */
3077 k = ieee80211_crypto_encap(ni, m);
3078 if (k == NULL)
3079 return (ENOBUFS);
3080
3081 if (!(k->wk_flags & IEEE80211_KEY_SWCRYPT)) {
3082 switch (k->wk_cipher->ic_cipher) {
3083 case IEEE80211_CIPHER_WEP:
3084 case IEEE80211_CIPHER_TKIP:
3085 cipher = R92C_TXDW1_CIPHER_RC4;
3086 break;
3087 case IEEE80211_CIPHER_AES_CCM:
3088 cipher = R92C_TXDW1_CIPHER_AES;
3089 break;
3090 default:
3091 device_printf(sc->sc_dev,
3092 "%s: unknown cipher %d\n",
3093 __func__, k->wk_cipher->ic_cipher);
3094 return (EINVAL);
3095 }
3096 }
3097 }
3098
3099 /* XXX TODO: 11n checks, matching urtwn_tx_data() */
3100
3101 wh = mtod(m, struct ieee80211_frame *);
3102 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK;
3103
3104 /* Fill Tx descriptor. */
3105 txd = (struct r92c_tx_desc *)data->buf;
3106 memset(txd, 0, sizeof(*txd));
3107
3108 txd->txdw0 |= htole32(
3109 SM(R92C_TXDW0_OFFSET, sizeof(*txd)) |
3110 R92C_TXDW0_OWN | R92C_TXDW0_FSG | R92C_TXDW0_LSG);
3111 if (IEEE80211_IS_MULTICAST(wh->i_addr1))
3112 txd->txdw0 |= htole32(R92C_TXDW0_BMCAST);
3113
3114 if ((params->ibp_flags & IEEE80211_BPF_NOACK) == 0) {
3115 txd->txdw5 |= htole32(R92C_TXDW5_RTY_LMT_ENA);
3116 txd->txdw5 |= htole32(SM(R92C_TXDW5_RTY_LMT,
3117 params->ibp_try0));
3118 }
3119 if (params->ibp_flags & IEEE80211_BPF_RTS)
3120 txd->txdw4 |= htole32(R92C_TXDW4_RTSEN);
3121 if (params->ibp_flags & IEEE80211_BPF_CTS)
3122 txd->txdw4 |= htole32(R92C_TXDW4_CTS2SELF);
3123 if (txd->txdw4 & htole32(R92C_TXDW4_RTSEN | R92C_TXDW4_CTS2SELF)) {
3124 txd->txdw4 |= htole32(R92C_TXDW4_HWRTSEN);
3125 txd->txdw4 |= htole32(SM(R92C_TXDW4_RTSRATE,
3126 URTWN_RIDX_OFDM24));
3127 }
3128
3129 if (sc->chip & URTWN_CHIP_88E)
3130 txd->txdw1 |= htole32(SM(R88E_TXDW1_MACID, URTWN_MACID_BC));
3131 else
3132 txd->txdw1 |= htole32(SM(R92C_TXDW1_MACID, URTWN_MACID_BC));
3133
3134 /* XXX TODO: rate index/config (RAID) for 11n? */
3135 txd->txdw1 |= htole32(SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_MGNT));
3136 txd->txdw1 |= htole32(SM(R92C_TXDW1_CIPHER, cipher));
3137
3138 /* Choose a TX rate index. */
3139 ridx = rate2ridx(params->ibp_rate0);
3140 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, ridx));
3141 txd->txdw5 |= htole32(0x0001ff00);
3142 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE);
3143
3144 if (!IEEE80211_QOS_HAS_SEQ(wh)) {
3145 /* Use HW sequence numbering for non-QoS frames. */
3146 if (sc->chip & URTWN_CHIP_88E)
3147 txd->txdseq = htole16(R88E_TXDSEQ_HWSEQ_EN);
3148 else
3149 txd->txdw4 |= htole32(R92C_TXDW4_HWSEQ_EN);
3150 } else {
3151 /* Set sequence number. */
3152 txd->txdseq = htole16(M_SEQNO_GET(m) % IEEE80211_SEQ_RANGE);
3153 }
3154
3155 if (ieee80211_radiotap_active_vap(vap)) {
3156 struct urtwn_tx_radiotap_header *tap = &sc->sc_txtap;
3157
3158 tap->wt_flags = 0;
3159 if (k != NULL)
3160 tap->wt_flags |= IEEE80211_RADIOTAP_F_WEP;
3161 ieee80211_radiotap_tx(vap, m);
3162 }
3163
3164 data->ni = ni;
3165
3166 urtwn_tx_start(sc, m, type, data);
3167
3168 return (0);
3169}
3170
3171static void
3172urtwn_tx_start(struct urtwn_softc *sc, struct mbuf *m, uint8_t type,
3173 struct urtwn_data *data)
3174{
3175 struct usb_xfer *xfer;
3176 struct r92c_tx_desc *txd;
3177 uint16_t ac, sum;
3178 int i, xferlen;
3179
3180 URTWN_ASSERT_LOCKED(sc);
3181
3182 ac = M_WME_GETAC(m);
3183
3184 switch (type) {
3185 case IEEE80211_FC0_TYPE_CTL:
3186 case IEEE80211_FC0_TYPE_MGT:
3187 xfer = sc->sc_xfer[URTWN_BULK_TX_VO];
3188 break;
3189 default:
3190 xfer = sc->sc_xfer[wme2queue[ac].qid];
3191 break;
3192 }
3193
3194 txd = (struct r92c_tx_desc *)data->buf;
3195 txd->txdw0 |= htole32(SM(R92C_TXDW0_PKTLEN, m->m_pkthdr.len));
3196
3197 /* Compute Tx descriptor checksum. */
3198 sum = 0;
3199 for (i = 0; i < sizeof(*txd) / 2; i++)
3200 sum ^= ((uint16_t *)txd)[i];
3201 txd->txdsum = sum; /* NB: already little endian. */
3202
3203 xferlen = sizeof(*txd) + m->m_pkthdr.len;
3204 m_copydata(m, 0, m->m_pkthdr.len, (caddr_t)&txd[1]);
3205
3206 data->buflen = xferlen;
3207 data->m = m;
3208
3209 STAILQ_INSERT_TAIL(&sc->sc_tx_pending, data, next);
3210 usbd_transfer_start(xfer);
3211}
3212
3213static int
3214urtwn_transmit(struct ieee80211com *ic, struct mbuf *m)
3215{
3216 struct urtwn_softc *sc = ic->ic_softc;
3217 int error;
3218
3219 URTWN_LOCK(sc);
3220 if ((sc->sc_flags & URTWN_RUNNING) == 0) {
3221 URTWN_UNLOCK(sc);
3222 return (ENXIO);
3223 }
3224 error = mbufq_enqueue(&sc->sc_snd, m);
3225 if (error) {
3226 URTWN_UNLOCK(sc);
3227 return (error);
3228 }
3229 urtwn_start(sc);
3230 URTWN_UNLOCK(sc);
3231
3232 return (0);
3233}
3234
3235static void
3236urtwn_start(struct urtwn_softc *sc)
3237{
3238 struct ieee80211_node *ni;
3239 struct mbuf *m;
3240 struct urtwn_data *bf;
3241
3242 URTWN_ASSERT_LOCKED(sc);
3243 while ((m = mbufq_dequeue(&sc->sc_snd)) != NULL) {
3244 bf = urtwn_getbuf(sc);
3245 if (bf == NULL) {
3246 mbufq_prepend(&sc->sc_snd, m);
3247 break;
3248 }
3249 ni = (struct ieee80211_node *)m->m_pkthdr.rcvif;
3250 m->m_pkthdr.rcvif = NULL;
3251
3252 URTWN_DPRINTF(sc, URTWN_DEBUG_XMIT, "%s: called; m=%p\n",
3253 __func__,
3254 m);
3255
3256 if (urtwn_tx_data(sc, ni, m, bf) != 0) {
3257 if_inc_counter(ni->ni_vap->iv_ifp,
3258 IFCOUNTER_OERRORS, 1);
3259 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, bf, next);
3260 m_freem(m);
3261 ieee80211_free_node(ni);
3262 break;
3263 }
3264 sc->sc_txtimer = 5;
3265 callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc);
3266 }
3267}
3268
3269static void
3270urtwn_parent(struct ieee80211com *ic)
3271{
3272 struct urtwn_softc *sc = ic->ic_softc;
3273
3274 URTWN_LOCK(sc);
3275 if (sc->sc_flags & URTWN_DETACHED) {
3276 URTWN_UNLOCK(sc);
3277 return;
3278 }
3279 URTWN_UNLOCK(sc);
3280
3281 if (ic->ic_nrunning > 0) {
3282 if (urtwn_init(sc) != 0) {
3283 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps);
3284 if (vap != NULL)
3285 ieee80211_stop(vap);
3286 } else
3287 ieee80211_start_all(ic);
3288 } else
3289 urtwn_stop(sc);
3290}
3291
3292static __inline int
3293urtwn_power_on(struct urtwn_softc *sc)
3294{
3295
3296 return sc->sc_power_on(sc);
3297}
3298
3299static int
3300urtwn_r92c_power_on(struct urtwn_softc *sc)
3301{
3302 uint32_t reg;
3303 usb_error_t error;
3304 int ntries;
3305
3306 /* Wait for autoload done bit. */
3307 for (ntries = 0; ntries < 1000; ntries++) {
3308 if (urtwn_read_1(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_PFM_ALDN)
3309 break;
3310 urtwn_ms_delay(sc);
3311 }
3312 if (ntries == 1000) {
3313 device_printf(sc->sc_dev,
3314 "timeout waiting for chip autoload\n");
3315 return (ETIMEDOUT);
3316 }
3317
3318 /* Unlock ISO/CLK/Power control register. */
3319 error = urtwn_write_1(sc, R92C_RSV_CTRL, 0);
3320 if (error != USB_ERR_NORMAL_COMPLETION)
3321 return (EIO);
3322 /* Move SPS into PWM mode. */
3323 error = urtwn_write_1(sc, R92C_SPS0_CTRL, 0x2b);
3324 if (error != USB_ERR_NORMAL_COMPLETION)
3325 return (EIO);
3326 urtwn_ms_delay(sc);
3327
3328 reg = urtwn_read_1(sc, R92C_LDOV12D_CTRL);
3329 if (!(reg & R92C_LDOV12D_CTRL_LDV12_EN)) {
3330 error = urtwn_write_1(sc, R92C_LDOV12D_CTRL,
3331 reg | R92C_LDOV12D_CTRL_LDV12_EN);
3332 if (error != USB_ERR_NORMAL_COMPLETION)
3333 return (EIO);
3334 urtwn_ms_delay(sc);
3335 error = urtwn_write_1(sc, R92C_SYS_ISO_CTRL,
3336 urtwn_read_1(sc, R92C_SYS_ISO_CTRL) &
3337 ~R92C_SYS_ISO_CTRL_MD2PP);
3338 if (error != USB_ERR_NORMAL_COMPLETION)
3339 return (EIO);
3340 }
3341
3342 /* Auto enable WLAN. */
3343 error = urtwn_write_2(sc, R92C_APS_FSMCO,
3344 urtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC);
3345 if (error != USB_ERR_NORMAL_COMPLETION)
3346 return (EIO);
3347 for (ntries = 0; ntries < 1000; ntries++) {
3348 if (!(urtwn_read_2(sc, R92C_APS_FSMCO) &
3349 R92C_APS_FSMCO_APFM_ONMAC))
3350 break;
3351 urtwn_ms_delay(sc);
3352 }
3353 if (ntries == 1000) {
3354 device_printf(sc->sc_dev,
3355 "timeout waiting for MAC auto ON\n");
3356 return (ETIMEDOUT);
3357 }
3358
3359 /* Enable radio, GPIO and LED functions. */
3360 error = urtwn_write_2(sc, R92C_APS_FSMCO,
3361 R92C_APS_FSMCO_AFSM_HSUS |
3362 R92C_APS_FSMCO_PDN_EN |
3363 R92C_APS_FSMCO_PFM_ALDN);
3364 if (error != USB_ERR_NORMAL_COMPLETION)
3365 return (EIO);
3366 /* Release RF digital isolation. */
3367 error = urtwn_write_2(sc, R92C_SYS_ISO_CTRL,
3368 urtwn_read_2(sc, R92C_SYS_ISO_CTRL) & ~R92C_SYS_ISO_CTRL_DIOR);
3369 if (error != USB_ERR_NORMAL_COMPLETION)
3370 return (EIO);
3371
3372 /* Initialize MAC. */
3373 error = urtwn_write_1(sc, R92C_APSD_CTRL,
3374 urtwn_read_1(sc, R92C_APSD_CTRL) & ~R92C_APSD_CTRL_OFF);
3375 if (error != USB_ERR_NORMAL_COMPLETION)
3376 return (EIO);
3377 for (ntries = 0; ntries < 200; ntries++) {
3378 if (!(urtwn_read_1(sc, R92C_APSD_CTRL) &
3379 R92C_APSD_CTRL_OFF_STATUS))
3380 break;
3381 urtwn_ms_delay(sc);
3382 }
3383 if (ntries == 200) {
3384 device_printf(sc->sc_dev,
3385 "timeout waiting for MAC initialization\n");
3386 return (ETIMEDOUT);
3387 }
3388
3389 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */
3390 reg = urtwn_read_2(sc, R92C_CR);
3391 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN |
3392 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN |
3393 R92C_CR_SCHEDULE_EN | R92C_CR_MACTXEN | R92C_CR_MACRXEN |
3394 R92C_CR_ENSEC;
3395 error = urtwn_write_2(sc, R92C_CR, reg);
3396 if (error != USB_ERR_NORMAL_COMPLETION)
3397 return (EIO);
3398
3399 error = urtwn_write_1(sc, 0xfe10, 0x19);
3400 if (error != USB_ERR_NORMAL_COMPLETION)
3401 return (EIO);
3402 return (0);
3403}
3404
3405static int
3406urtwn_r88e_power_on(struct urtwn_softc *sc)
3407{
3408 uint32_t reg;
3409 usb_error_t error;
3410 int ntries;
3411
3412 /* Wait for power ready bit. */
3413 for (ntries = 0; ntries < 5000; ntries++) {
3414 if (urtwn_read_4(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_SUS_HOST)
3415 break;
3416 urtwn_ms_delay(sc);
3417 }
3418 if (ntries == 5000) {
3419 device_printf(sc->sc_dev,
3420 "timeout waiting for chip power up\n");
3421 return (ETIMEDOUT);
3422 }
3423
3424 /* Reset BB. */
3425 error = urtwn_write_1(sc, R92C_SYS_FUNC_EN,
3426 urtwn_read_1(sc, R92C_SYS_FUNC_EN) & ~(R92C_SYS_FUNC_EN_BBRSTB |
3427 R92C_SYS_FUNC_EN_BB_GLB_RST));
3428 if (error != USB_ERR_NORMAL_COMPLETION)
3429 return (EIO);
3430
3431 error = urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 2,
3432 urtwn_read_1(sc, R92C_AFE_XTAL_CTRL + 2) | 0x80);
3433 if (error != USB_ERR_NORMAL_COMPLETION)
3434 return (EIO);
3435
3436 /* Disable HWPDN. */
3437 error = urtwn_write_2(sc, R92C_APS_FSMCO,
3438 urtwn_read_2(sc, R92C_APS_FSMCO) & ~R92C_APS_FSMCO_APDM_HPDN);
3439 if (error != USB_ERR_NORMAL_COMPLETION)
3440 return (EIO);
3441
3442 /* Disable WL suspend. */
3443 error = urtwn_write_2(sc, R92C_APS_FSMCO,
3444 urtwn_read_2(sc, R92C_APS_FSMCO) &
3445 ~(R92C_APS_FSMCO_AFSM_HSUS | R92C_APS_FSMCO_AFSM_PCIE));
3446 if (error != USB_ERR_NORMAL_COMPLETION)
3447 return (EIO);
3448
3449 error = urtwn_write_2(sc, R92C_APS_FSMCO,
3450 urtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC);
3451 if (error != USB_ERR_NORMAL_COMPLETION)
3452 return (EIO);
3453 for (ntries = 0; ntries < 5000; ntries++) {
3454 if (!(urtwn_read_2(sc, R92C_APS_FSMCO) &
3455 R92C_APS_FSMCO_APFM_ONMAC))
3456 break;
3457 urtwn_ms_delay(sc);
3458 }
3459 if (ntries == 5000)
3460 return (ETIMEDOUT);
3461
3462 /* Enable LDO normal mode. */
3463 error = urtwn_write_1(sc, R92C_LPLDO_CTRL,
3464 urtwn_read_1(sc, R92C_LPLDO_CTRL) & ~R92C_LPLDO_CTRL_SLEEP);
3465 if (error != USB_ERR_NORMAL_COMPLETION)
3466 return (EIO);
3467
3468 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */
3469 error = urtwn_write_2(sc, R92C_CR, 0);
3470 if (error != USB_ERR_NORMAL_COMPLETION)
3471 return (EIO);
3472 reg = urtwn_read_2(sc, R92C_CR);
3473 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN |
3474 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN |
3475 R92C_CR_SCHEDULE_EN | R92C_CR_ENSEC | R92C_CR_CALTMR_EN;
3476 error = urtwn_write_2(sc, R92C_CR, reg);
3477 if (error != USB_ERR_NORMAL_COMPLETION)
3478 return (EIO);
3479
3480 return (0);
3481}
3482
3483static __inline void
3484urtwn_power_off(struct urtwn_softc *sc)
3485{
3486
3487 return sc->sc_power_off(sc);
3488}
3489
3490static void
3491urtwn_r92c_power_off(struct urtwn_softc *sc)
3492{
3493 uint32_t reg;
3494
3495 /* Block all Tx queues. */
3496 urtwn_write_1(sc, R92C_TXPAUSE, R92C_TX_QUEUE_ALL);
3497
3498 /* Disable RF */
3499 urtwn_rf_write(sc, 0, 0, 0);
3500
3501 urtwn_write_1(sc, R92C_APSD_CTRL, R92C_APSD_CTRL_OFF);
3502
3503 /* Reset BB state machine */
3504 urtwn_write_1(sc, R92C_SYS_FUNC_EN,
3505 R92C_SYS_FUNC_EN_USBD | R92C_SYS_FUNC_EN_USBA |
3506 R92C_SYS_FUNC_EN_BB_GLB_RST);
3507 urtwn_write_1(sc, R92C_SYS_FUNC_EN,
3508 R92C_SYS_FUNC_EN_USBD | R92C_SYS_FUNC_EN_USBA);
3509
3510 /*
3511 * Reset digital sequence
3512 */
3513#ifndef URTWN_WITHOUT_UCODE
3514 if (urtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RDY) {
3515 /* Reset MCU ready status */
3516 urtwn_write_1(sc, R92C_MCUFWDL, 0);
3517
3518 /* If firmware in ram code, do reset */
3519 urtwn_fw_reset(sc);
3520 }
3521#endif
3522
3523 /* Reset MAC and Enable 8051 */
3524 urtwn_write_1(sc, R92C_SYS_FUNC_EN + 1,
3525 (R92C_SYS_FUNC_EN_CPUEN |
3526 R92C_SYS_FUNC_EN_ELDR |
3527 R92C_SYS_FUNC_EN_HWPDN) >> 8);
3528
3529 /* Reset MCU ready status */
3530 urtwn_write_1(sc, R92C_MCUFWDL, 0);
3531
3532 /* Disable MAC clock */
3533 urtwn_write_2(sc, R92C_SYS_CLKR,
3534 R92C_SYS_CLKR_ANAD16V_EN |
3535 R92C_SYS_CLKR_ANA8M |
3536 R92C_SYS_CLKR_LOADER_EN |
3537 R92C_SYS_CLKR_80M_SSC_DIS |
3538 R92C_SYS_CLKR_SYS_EN |
3539 R92C_SYS_CLKR_RING_EN |
3540 0x4000);
3541
3542 /* Disable AFE PLL */
3543 urtwn_write_1(sc, R92C_AFE_PLL_CTRL, 0x80);
3544
3545 /* Gated AFE DIG_CLOCK */
3546 urtwn_write_2(sc, R92C_AFE_XTAL_CTRL, 0x880F);
3547
3548 /* Isolated digital to PON */
3549 urtwn_write_1(sc, R92C_SYS_ISO_CTRL,
3550 R92C_SYS_ISO_CTRL_MD2PP |
3551 R92C_SYS_ISO_CTRL_PA2PCIE |
3552 R92C_SYS_ISO_CTRL_PD2CORE |
3553 R92C_SYS_ISO_CTRL_IP2MAC |
3554 R92C_SYS_ISO_CTRL_DIOP |
3555 R92C_SYS_ISO_CTRL_DIOE);
3556
3557 /*
3558 * Pull GPIO PIN to balance level and LED control
3559 */
3560 /* 1. Disable GPIO[7:0] */
3561 urtwn_write_2(sc, R92C_GPIO_IOSEL, 0x0000);
3562
3563 reg = urtwn_read_4(sc, R92C_GPIO_PIN_CTRL) & ~0x0000ff00;
3564 reg |= ((reg << 8) & 0x0000ff00) | 0x00ff0000;
3565 urtwn_write_4(sc, R92C_GPIO_PIN_CTRL, reg);
3566
3567 /* Disable GPIO[10:8] */
3568 urtwn_write_1(sc, R92C_MAC_PINMUX_CFG, 0x00);
3569
3570 reg = urtwn_read_2(sc, R92C_GPIO_IO_SEL) & ~0x00f0;
3571 reg |= (((reg & 0x000f) << 4) | 0x0780);
3572 urtwn_write_2(sc, R92C_GPIO_IO_SEL, reg);
3573
3574 /* Disable LED0 & 1 */
3575 urtwn_write_2(sc, R92C_LEDCFG0, 0x8080);
3576
3577 /*
3578 * Reset digital sequence
3579 */
3580 /* Disable ELDR clock */
3581 urtwn_write_2(sc, R92C_SYS_CLKR,
3582 R92C_SYS_CLKR_ANAD16V_EN |
3583 R92C_SYS_CLKR_ANA8M |
3584 R92C_SYS_CLKR_LOADER_EN |
3585 R92C_SYS_CLKR_80M_SSC_DIS |
3586 R92C_SYS_CLKR_SYS_EN |
3587 R92C_SYS_CLKR_RING_EN |
3588 0x4000);
3589
3590 /* Isolated ELDR to PON */
3591 urtwn_write_1(sc, R92C_SYS_ISO_CTRL + 1,
3592 (R92C_SYS_ISO_CTRL_DIOR |
3593 R92C_SYS_ISO_CTRL_PWC_EV12V) >> 8);
3594
3595 /*
3596 * Disable analog sequence
3597 */
3598 /* Disable A15 power */
3599 urtwn_write_1(sc, R92C_LDOA15_CTRL, R92C_LDOA15_CTRL_OBUF);
3600 /* Disable digital core power */
3601 urtwn_write_1(sc, R92C_LDOV12D_CTRL,
3602 urtwn_read_1(sc, R92C_LDOV12D_CTRL) &
3603 ~R92C_LDOV12D_CTRL_LDV12_EN);
3604
3605 /* Enter PFM mode */
3606 urtwn_write_1(sc, R92C_SPS0_CTRL, 0x23);
3607
3608 /* Set USB suspend */
3609 urtwn_write_2(sc, R92C_APS_FSMCO,
3610 R92C_APS_FSMCO_APDM_HOST |
3611 R92C_APS_FSMCO_AFSM_HSUS |
3612 R92C_APS_FSMCO_PFM_ALDN);
3613
3614 /* Lock ISO/CLK/Power control register. */
3615 urtwn_write_1(sc, R92C_RSV_CTRL, 0x0E);
3616}
3617
3618static void
3619urtwn_r88e_power_off(struct urtwn_softc *sc)
3620{
3621 uint8_t reg;
3622 int ntries;
3623
3624 /* Disable any kind of TX reports. */
3625 urtwn_write_1(sc, R88E_TX_RPT_CTRL,
3626 urtwn_read_1(sc, R88E_TX_RPT_CTRL) &
3627 ~(R88E_TX_RPT1_ENA | R88E_TX_RPT2_ENA));
3628
3629 /* Stop Rx. */
3630 urtwn_write_1(sc, R92C_CR, 0);
3631
3632 /* Move card to Low Power State. */
3633 /* Block all Tx queues. */
3634 urtwn_write_1(sc, R92C_TXPAUSE, R92C_TX_QUEUE_ALL);
3635
3636 for (ntries = 0; ntries < 20; ntries++) {
3637 /* Should be zero if no packet is transmitting. */
3638 if (urtwn_read_4(sc, R88E_SCH_TXCMD) == 0)
3639 break;
3640
3641 urtwn_ms_delay(sc);
3642 }
3643 if (ntries == 20) {
3644 device_printf(sc->sc_dev, "%s: failed to block Tx queues\n",
3645 __func__);
3646 return;
3647 }
3648
3649 /* CCK and OFDM are disabled, and clock are gated. */
3650 urtwn_write_1(sc, R92C_SYS_FUNC_EN,
3651 urtwn_read_1(sc, R92C_SYS_FUNC_EN) & ~R92C_SYS_FUNC_EN_BBRSTB);
3652
3653 urtwn_ms_delay(sc);
3654
3655 /* Reset MAC TRX */
3656 urtwn_write_1(sc, R92C_CR,
3657 R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN |
3658 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN |
3659 R92C_CR_PROTOCOL_EN | R92C_CR_SCHEDULE_EN);
3660
3661 /* check if removed later */
3662 urtwn_write_1(sc, R92C_CR + 1,
3663 urtwn_read_1(sc, R92C_CR + 1) & ~(R92C_CR_ENSEC >> 8));
3664
3665 /* Respond TxOK to scheduler */
3666 urtwn_write_1(sc, R92C_DUAL_TSF_RST,
3667 urtwn_read_1(sc, R92C_DUAL_TSF_RST) | 0x20);
3668
3669 /* If firmware in ram code, do reset. */
3670#ifndef URTWN_WITHOUT_UCODE
3671 if (urtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RDY)
3672 urtwn_r88e_fw_reset(sc);
3673#endif
3674
3675 /* Reset MCU ready status. */
3676 urtwn_write_1(sc, R92C_MCUFWDL, 0x00);
3677
3678 /* Disable 32k. */
3679 urtwn_write_1(sc, R88E_32K_CTRL,
3680 urtwn_read_1(sc, R88E_32K_CTRL) & ~0x01);
3681
3682 /* Move card to Disabled state. */
3683 /* Turn off RF. */
3684 urtwn_write_1(sc, R92C_RF_CTRL, 0);
3685
3686 /* LDO Sleep mode. */
3687 urtwn_write_1(sc, R92C_LPLDO_CTRL,
3688 urtwn_read_1(sc, R92C_LPLDO_CTRL) | R92C_LPLDO_CTRL_SLEEP);
3689
3690 /* Turn off MAC by HW state machine */
3691 urtwn_write_1(sc, R92C_APS_FSMCO + 1,
3692 urtwn_read_1(sc, R92C_APS_FSMCO + 1) |
3693 (R92C_APS_FSMCO_APFM_OFF >> 8));
3694
3695 for (ntries = 0; ntries < 20; ntries++) {
3696 /* Wait until it will be disabled. */
3697 if ((urtwn_read_1(sc, R92C_APS_FSMCO + 1) &
3698 (R92C_APS_FSMCO_APFM_OFF >> 8)) == 0)
3699 break;
3700
3701 urtwn_ms_delay(sc);
3702 }
3703 if (ntries == 20) {
3704 device_printf(sc->sc_dev, "%s: could not turn off MAC\n",
3705 __func__);
3706 return;
3707 }
3708
3709 /* schmit trigger */
3710 urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 2,
3711 urtwn_read_1(sc, R92C_AFE_XTAL_CTRL + 2) | 0x80);
3712
3713 /* Enable WL suspend. */
3714 urtwn_write_1(sc, R92C_APS_FSMCO + 1,
3715 (urtwn_read_1(sc, R92C_APS_FSMCO + 1) & ~0x10) | 0x08);
3716
3717 /* Enable bandgap mbias in suspend. */
3718 urtwn_write_1(sc, R92C_APS_FSMCO + 3, 0);
3719
3720 /* Clear SIC_EN register. */
3721 urtwn_write_1(sc, R92C_GPIO_MUXCFG + 1,
3722 urtwn_read_1(sc, R92C_GPIO_MUXCFG + 1) & ~0x10);
3723
3724 /* Set USB suspend enable local register */
3725 urtwn_write_1(sc, R92C_USB_SUSPEND,
3726 urtwn_read_1(sc, R92C_USB_SUSPEND) | 0x10);
3727
3728 /* Reset MCU IO Wrapper. */
3729 reg = urtwn_read_1(sc, R92C_RSV_CTRL + 1);
3730 urtwn_write_1(sc, R92C_RSV_CTRL + 1, reg & ~0x08);
3731 urtwn_write_1(sc, R92C_RSV_CTRL + 1, reg | 0x08);
3732
3733 /* marked as 'For Power Consumption' code. */
3734 urtwn_write_1(sc, R92C_GPIO_OUT, urtwn_read_1(sc, R92C_GPIO_IN));
3735 urtwn_write_1(sc, R92C_GPIO_IOSEL, 0xff);
3736
3737 urtwn_write_1(sc, R92C_GPIO_IO_SEL,
3738 urtwn_read_1(sc, R92C_GPIO_IO_SEL) << 4);
3739 urtwn_write_1(sc, R92C_GPIO_MOD,
3740 urtwn_read_1(sc, R92C_GPIO_MOD) | 0x0f);
3741
3742 /* Set LNA, TRSW, EX_PA Pin to output mode. */
3743 urtwn_write_4(sc, R88E_BB_PAD_CTRL, 0x00080808);
3744}
3745
3746static int
3747urtwn_llt_init(struct urtwn_softc *sc)
3748{
3749 int i, error, page_count, pktbuf_count;
3750
3751 page_count = (sc->chip & URTWN_CHIP_88E) ?
3752 R88E_TX_PAGE_COUNT : R92C_TX_PAGE_COUNT;
3753 pktbuf_count = (sc->chip & URTWN_CHIP_88E) ?
3754 R88E_TXPKTBUF_COUNT : R92C_TXPKTBUF_COUNT;
3755
3756 /* Reserve pages [0; page_count]. */
3757 for (i = 0; i < page_count; i++) {
3758 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0)
3759 return (error);
3760 }
3761 /* NB: 0xff indicates end-of-list. */
3762 if ((error = urtwn_llt_write(sc, i, 0xff)) != 0)
3763 return (error);
3764 /*
3765 * Use pages [page_count + 1; pktbuf_count - 1]
3766 * as ring buffer.
3767 */
3768 for (++i; i < pktbuf_count - 1; i++) {
3769 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0)
3770 return (error);
3771 }
3772 /* Make the last page point to the beginning of the ring buffer. */
3773 error = urtwn_llt_write(sc, i, page_count + 1);
3774 return (error);
3775}
3776
3777#ifndef URTWN_WITHOUT_UCODE
3778static void
3779urtwn_fw_reset(struct urtwn_softc *sc)
3780{
3781 uint16_t reg;
3782 int ntries;
3783
3784 /* Tell 8051 to reset itself. */
3785 urtwn_write_1(sc, R92C_HMETFR + 3, 0x20);
3786
3787 /* Wait until 8051 resets by itself. */
3788 for (ntries = 0; ntries < 100; ntries++) {
3789 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN);
3790 if (!(reg & R92C_SYS_FUNC_EN_CPUEN))
3791 return;
3792 urtwn_ms_delay(sc);
3793 }
3794 /* Force 8051 reset. */
3795 urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg & ~R92C_SYS_FUNC_EN_CPUEN);
3796}
3797
3798static void
3799urtwn_r88e_fw_reset(struct urtwn_softc *sc)
3800{
3801 uint16_t reg;
3802
3803 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN);
3804 urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg & ~R92C_SYS_FUNC_EN_CPUEN);
3805 urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg | R92C_SYS_FUNC_EN_CPUEN);
3806}
3807
3808static int
3809urtwn_fw_loadpage(struct urtwn_softc *sc, int page, const uint8_t *buf, int len)
3810{
3811 uint32_t reg;
3812 usb_error_t error = USB_ERR_NORMAL_COMPLETION;
3813 int off, mlen;
3814
3815 reg = urtwn_read_4(sc, R92C_MCUFWDL);
3816 reg = RW(reg, R92C_MCUFWDL_PAGE, page);
3817 urtwn_write_4(sc, R92C_MCUFWDL, reg);
3818
3819 off = R92C_FW_START_ADDR;
3820 while (len > 0) {
3821 if (len > 196)
3822 mlen = 196;
3823 else if (len > 4)
3824 mlen = 4;
3825 else
3826 mlen = 1;
3827 /* XXX fix this deconst */
3828 error = urtwn_write_region_1(sc, off,
3829 __DECONST(uint8_t *, buf), mlen);
3830 if (error != USB_ERR_NORMAL_COMPLETION)
3831 break;
3832 off += mlen;
3833 buf += mlen;
3834 len -= mlen;
3835 }
3836 return (error);
3837}
3838
3839static int
3840urtwn_load_firmware(struct urtwn_softc *sc)
3841{
3842 const struct firmware *fw;
3843 const struct r92c_fw_hdr *hdr;
3844 const char *imagename;
3845 const u_char *ptr;
3846 size_t len;
3847 uint32_t reg;
3848 int mlen, ntries, page, error;
3849
3850 URTWN_UNLOCK(sc);
3851 /* Read firmware image from the filesystem. */
3852 if (sc->chip & URTWN_CHIP_88E)
3853 imagename = "urtwn-rtl8188eufw";
3854 else if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) ==
3855 URTWN_CHIP_UMC_A_CUT)
3856 imagename = "urtwn-rtl8192cfwU";
3857 else
3858 imagename = "urtwn-rtl8192cfwT";
3859
3860 fw = firmware_get(imagename);
3861 URTWN_LOCK(sc);
3862 if (fw == NULL) {
3863 device_printf(sc->sc_dev,
3864 "failed loadfirmware of file %s\n", imagename);
3865 return (ENOENT);
3866 }
3867
3868 len = fw->datasize;
3869
3870 if (len < sizeof(*hdr)) {
3871 device_printf(sc->sc_dev, "firmware too short\n");
3872 error = EINVAL;
3873 goto fail;
3874 }
3875 ptr = fw->data;
3876 hdr = (const struct r92c_fw_hdr *)ptr;
3877 /* Check if there is a valid FW header and skip it. */
3878 if ((le16toh(hdr->signature) >> 4) == 0x88c ||
3879 (le16toh(hdr->signature) >> 4) == 0x88e ||
3880 (le16toh(hdr->signature) >> 4) == 0x92c) {
3881 URTWN_DPRINTF(sc, URTWN_DEBUG_FIRMWARE,
3882 "FW V%d.%d %02d-%02d %02d:%02d\n",
3883 le16toh(hdr->version), le16toh(hdr->subversion),
3884 hdr->month, hdr->date, hdr->hour, hdr->minute);
3885 ptr += sizeof(*hdr);
3886 len -= sizeof(*hdr);
3887 }
3888
3889 if (urtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RAM_DL_SEL) {
3890 if (sc->chip & URTWN_CHIP_88E)
3891 urtwn_r88e_fw_reset(sc);
3892 else
3893 urtwn_fw_reset(sc);
3894 urtwn_write_1(sc, R92C_MCUFWDL, 0);
3895 }
3896
3897 if (!(sc->chip & URTWN_CHIP_88E)) {
3898 urtwn_write_2(sc, R92C_SYS_FUNC_EN,
3899 urtwn_read_2(sc, R92C_SYS_FUNC_EN) |
3900 R92C_SYS_FUNC_EN_CPUEN);
3901 }
3902 urtwn_write_1(sc, R92C_MCUFWDL,
3903 urtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_EN);
3904 urtwn_write_1(sc, R92C_MCUFWDL + 2,
3905 urtwn_read_1(sc, R92C_MCUFWDL + 2) & ~0x08);
3906
3907 /* Reset the FWDL checksum. */
3908 urtwn_write_1(sc, R92C_MCUFWDL,
3909 urtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_CHKSUM_RPT);
3910
3911 for (page = 0; len > 0; page++) {
3912 mlen = min(len, R92C_FW_PAGE_SIZE);
3913 error = urtwn_fw_loadpage(sc, page, ptr, mlen);
3914 if (error != 0) {
3915 device_printf(sc->sc_dev,
3916 "could not load firmware page\n");
3917 goto fail;
3918 }
3919 ptr += mlen;
3920 len -= mlen;
3921 }
3922 urtwn_write_1(sc, R92C_MCUFWDL,
3923 urtwn_read_1(sc, R92C_MCUFWDL) & ~R92C_MCUFWDL_EN);
3924 urtwn_write_1(sc, R92C_MCUFWDL + 1, 0);
3925
3926 /* Wait for checksum report. */
3927 for (ntries = 0; ntries < 1000; ntries++) {
3928 if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_CHKSUM_RPT)
3929 break;
3930 urtwn_ms_delay(sc);
3931 }
3932 if (ntries == 1000) {
3933 device_printf(sc->sc_dev,
3934 "timeout waiting for checksum report\n");
3935 error = ETIMEDOUT;
3936 goto fail;
3937 }
3938
3939 reg = urtwn_read_4(sc, R92C_MCUFWDL);
3940 reg = (reg & ~R92C_MCUFWDL_WINTINI_RDY) | R92C_MCUFWDL_RDY;
3941 urtwn_write_4(sc, R92C_MCUFWDL, reg);
3942 if (sc->chip & URTWN_CHIP_88E)
3943 urtwn_r88e_fw_reset(sc);
3944 /* Wait for firmware readiness. */
3945 for (ntries = 0; ntries < 1000; ntries++) {
3946 if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_WINTINI_RDY)
3947 break;
3948 urtwn_ms_delay(sc);
3949 }
3950 if (ntries == 1000) {
3951 device_printf(sc->sc_dev,
3952 "timeout waiting for firmware readiness\n");
3953 error = ETIMEDOUT;
3954 goto fail;
3955 }
3956fail:
3957 firmware_put(fw, FIRMWARE_UNLOAD);
3958 return (error);
3959}
3960#endif
3961
3962static int
3963urtwn_dma_init(struct urtwn_softc *sc)
3964{
3965 struct usb_endpoint *ep, *ep_end;
3966 usb_error_t usb_err;
3967 uint32_t reg;
3968 int hashq, hasnq, haslq, nqueues, ntx;
3969 int error, pagecount, npubqpages, nqpages, nrempages, tx_boundary;
3970
3971 /* Initialize LLT table. */
3972 error = urtwn_llt_init(sc);
3973 if (error != 0)
3974 return (error);
3975
3976 /* Determine the number of bulk-out pipes. */
3977 ntx = 0;
3978 ep = sc->sc_udev->endpoints;
3979 ep_end = sc->sc_udev->endpoints + sc->sc_udev->endpoints_max;
3980 for (; ep != ep_end; ep++) {
3981 if ((ep->edesc == NULL) ||
3982 (ep->iface_index != sc->sc_iface_index))
3983 continue;
3984 if (UE_GET_DIR(ep->edesc->bEndpointAddress) == UE_DIR_OUT)
3985 ntx++;
3986 }
3987 if (ntx == 0) {
3988 device_printf(sc->sc_dev,
3989 "%d: invalid number of Tx bulk pipes\n", ntx);
3990 return (EIO);
3991 }
3992
3993 /* Get Tx queues to USB endpoints mapping. */
3994 hashq = hasnq = haslq = nqueues = 0;
3995 switch (ntx) {
3996 case 1: hashq = 1; break;
3997 case 2: hashq = hasnq = 1; break;
3998 case 3: case 4: hashq = hasnq = haslq = 1; break;
3999 }
4000 nqueues = hashq + hasnq + haslq;
4001 if (nqueues == 0)
4002 return (EIO);
4003
4004 npubqpages = nqpages = nrempages = pagecount = 0;
4005 if (sc->chip & URTWN_CHIP_88E)
4006 tx_boundary = R88E_TX_PAGE_BOUNDARY;
4007 else {
4008 pagecount = R92C_TX_PAGE_COUNT;
4009 npubqpages = R92C_PUBQ_NPAGES;
4010 tx_boundary = R92C_TX_PAGE_BOUNDARY;
4011 }
4012
4013 /* Set number of pages for normal priority queue. */
4014 if (sc->chip & URTWN_CHIP_88E) {
4015 usb_err = urtwn_write_2(sc, R92C_RQPN_NPQ, 0xd);
4016 if (usb_err != USB_ERR_NORMAL_COMPLETION)
4017 return (EIO);
4018 usb_err = urtwn_write_4(sc, R92C_RQPN, 0x808e000d);
4019 if (usb_err != USB_ERR_NORMAL_COMPLETION)
4020 return (EIO);
4021 } else {
4022 /* Get the number of pages for each queue. */
4023 nqpages = (pagecount - npubqpages) / nqueues;
4024 /*
4025 * The remaining pages are assigned to the high priority
4026 * queue.
4027 */
4028 nrempages = (pagecount - npubqpages) % nqueues;
4029 usb_err = urtwn_write_1(sc, R92C_RQPN_NPQ, hasnq ? nqpages : 0);
4030 if (usb_err != USB_ERR_NORMAL_COMPLETION)
4031 return (EIO);
4032 usb_err = urtwn_write_4(sc, R92C_RQPN,
4033 /* Set number of pages for public queue. */
4034 SM(R92C_RQPN_PUBQ, npubqpages) |
4035 /* Set number of pages for high priority queue. */
4036 SM(R92C_RQPN_HPQ, hashq ? nqpages + nrempages : 0) |
4037 /* Set number of pages for low priority queue. */
4038 SM(R92C_RQPN_LPQ, haslq ? nqpages : 0) |
4039 /* Load values. */
4040 R92C_RQPN_LD);
4041 if (usb_err != USB_ERR_NORMAL_COMPLETION)
4042 return (EIO);
4043 }
4044
4045 usb_err = urtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, tx_boundary);
4046 if (usb_err != USB_ERR_NORMAL_COMPLETION)
4047 return (EIO);
4048 usb_err = urtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, tx_boundary);
4049 if (usb_err != USB_ERR_NORMAL_COMPLETION)
4050 return (EIO);
4051 usb_err = urtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, tx_boundary);
4052 if (usb_err != USB_ERR_NORMAL_COMPLETION)
4053 return (EIO);
4054 usb_err = urtwn_write_1(sc, R92C_TRXFF_BNDY, tx_boundary);
4055 if (usb_err != USB_ERR_NORMAL_COMPLETION)
4056 return (EIO);
4057 usb_err = urtwn_write_1(sc, R92C_TDECTRL + 1, tx_boundary);
4058 if (usb_err != USB_ERR_NORMAL_COMPLETION)
4059 return (EIO);
4060
4061 /* Set queue to USB pipe mapping. */
4062 reg = urtwn_read_2(sc, R92C_TRXDMA_CTRL);
4063 reg &= ~R92C_TRXDMA_CTRL_QMAP_M;
4064 if (nqueues == 1) {
4065 if (hashq)
4066 reg |= R92C_TRXDMA_CTRL_QMAP_HQ;
4067 else if (hasnq)
4068 reg |= R92C_TRXDMA_CTRL_QMAP_NQ;
4069 else
4070 reg |= R92C_TRXDMA_CTRL_QMAP_LQ;
4071 } else if (nqueues == 2) {
4072 /*
4073 * All 2-endpoints configs have high and normal
4074 * priority queues.
4075 */
4076 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_NQ;
4077 } else
4078 reg |= R92C_TRXDMA_CTRL_QMAP_3EP;
4079 usb_err = urtwn_write_2(sc, R92C_TRXDMA_CTRL, reg);
4080 if (usb_err != USB_ERR_NORMAL_COMPLETION)
4081 return (EIO);
4082
4083 /* Set Tx/Rx transfer page boundary. */
4084 usb_err = urtwn_write_2(sc, R92C_TRXFF_BNDY + 2,
4085 (sc->chip & URTWN_CHIP_88E) ? 0x23ff : 0x27ff);
4086 if (usb_err != USB_ERR_NORMAL_COMPLETION)
4087 return (EIO);
4088
4089 /* Set Tx/Rx transfer page size. */
4090 usb_err = urtwn_write_1(sc, R92C_PBP,
4091 SM(R92C_PBP_PSRX, R92C_PBP_128) |
4092 SM(R92C_PBP_PSTX, R92C_PBP_128));
4093 if (usb_err != USB_ERR_NORMAL_COMPLETION)
4094 return (EIO);
4095
4096 return (0);
4097}
4098
4099static int
4100urtwn_mac_init(struct urtwn_softc *sc)
4101{
4102 usb_error_t error;
4103 int i;
4104
4105 /* Write MAC initialization values. */
4106 if (sc->chip & URTWN_CHIP_88E) {
4107 for (i = 0; i < nitems(rtl8188eu_mac); i++) {
4108 error = urtwn_write_1(sc, rtl8188eu_mac[i].reg,
4109 rtl8188eu_mac[i].val);
4110 if (error != USB_ERR_NORMAL_COMPLETION)
4111 return (EIO);
4112 }
4113 urtwn_write_1(sc, R92C_MAX_AGGR_NUM, 0x07);
4114 } else {
4115 for (i = 0; i < nitems(rtl8192cu_mac); i++)
4116 error = urtwn_write_1(sc, rtl8192cu_mac[i].reg,
4117 rtl8192cu_mac[i].val);
4118 if (error != USB_ERR_NORMAL_COMPLETION)
4119 return (EIO);
4120 }
4121
4122 return (0);
4123}
4124
4125static void
4126urtwn_bb_init(struct urtwn_softc *sc)
4127{
4128 const struct urtwn_bb_prog *prog;
4129 uint32_t reg;
4130 uint8_t crystalcap;
4131 int i;
4132
4133 /* Enable BB and RF. */
4134 urtwn_write_2(sc, R92C_SYS_FUNC_EN,
4135 urtwn_read_2(sc, R92C_SYS_FUNC_EN) |
4136 R92C_SYS_FUNC_EN_BBRSTB | R92C_SYS_FUNC_EN_BB_GLB_RST |
4137 R92C_SYS_FUNC_EN_DIO_RF);
4138
4139 if (!(sc->chip & URTWN_CHIP_88E))
4140 urtwn_write_2(sc, R92C_AFE_PLL_CTRL, 0xdb83);
4141
4142 urtwn_write_1(sc, R92C_RF_CTRL,
4143 R92C_RF_CTRL_EN | R92C_RF_CTRL_RSTB | R92C_RF_CTRL_SDMRSTB);
4144 urtwn_write_1(sc, R92C_SYS_FUNC_EN,
4145 R92C_SYS_FUNC_EN_USBA | R92C_SYS_FUNC_EN_USBD |
4146 R92C_SYS_FUNC_EN_BB_GLB_RST | R92C_SYS_FUNC_EN_BBRSTB);
4147
4148 if (!(sc->chip & URTWN_CHIP_88E)) {
4149 urtwn_write_1(sc, R92C_LDOHCI12_CTRL, 0x0f);
4150 urtwn_write_1(sc, 0x15, 0xe9);
4151 urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 1, 0x80);
4152 }
4153
4154 /* Select BB programming based on board type. */
4155 if (sc->chip & URTWN_CHIP_88E)
4156 prog = &rtl8188eu_bb_prog;
4157 else if (!(sc->chip & URTWN_CHIP_92C)) {
4158 if (sc->board_type == R92C_BOARD_TYPE_MINICARD)
4159 prog = &rtl8188ce_bb_prog;
4160 else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA)
4161 prog = &rtl8188ru_bb_prog;
4162 else
4163 prog = &rtl8188cu_bb_prog;
4164 } else {
4165 if (sc->board_type == R92C_BOARD_TYPE_MINICARD)
4166 prog = &rtl8192ce_bb_prog;
4167 else
4168 prog = &rtl8192cu_bb_prog;
4169 }
4170 /* Write BB initialization values. */
4171 for (i = 0; i < prog->count; i++) {
4172 urtwn_bb_write(sc, prog->regs[i], prog->vals[i]);
4173 urtwn_ms_delay(sc);
4174 }
4175
4176 if (sc->chip & URTWN_CHIP_92C_1T2R) {
4177 /* 8192C 1T only configuration. */
4178 reg = urtwn_bb_read(sc, R92C_FPGA0_TXINFO);
4179 reg = (reg & ~0x00000003) | 0x2;
4180 urtwn_bb_write(sc, R92C_FPGA0_TXINFO, reg);
4181
4182 reg = urtwn_bb_read(sc, R92C_FPGA1_TXINFO);
4183 reg = (reg & ~0x00300033) | 0x00200022;
4184 urtwn_bb_write(sc, R92C_FPGA1_TXINFO, reg);
4185
4186 reg = urtwn_bb_read(sc, R92C_CCK0_AFESETTING);
4187 reg = (reg & ~0xff000000) | 0x45 << 24;
4188 urtwn_bb_write(sc, R92C_CCK0_AFESETTING, reg);
4189
4190 reg = urtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA);
4191 reg = (reg & ~0x000000ff) | 0x23;
4192 urtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, reg);
4193
4194 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCPARAM1);
4195 reg = (reg & ~0x00000030) | 1 << 4;
4196 urtwn_bb_write(sc, R92C_OFDM0_AGCPARAM1, reg);
4197
4198 reg = urtwn_bb_read(sc, 0xe74);
4199 reg = (reg & ~0x0c000000) | 2 << 26;
4200 urtwn_bb_write(sc, 0xe74, reg);
4201 reg = urtwn_bb_read(sc, 0xe78);
4202 reg = (reg & ~0x0c000000) | 2 << 26;
4203 urtwn_bb_write(sc, 0xe78, reg);
4204 reg = urtwn_bb_read(sc, 0xe7c);
4205 reg = (reg & ~0x0c000000) | 2 << 26;
4206 urtwn_bb_write(sc, 0xe7c, reg);
4207 reg = urtwn_bb_read(sc, 0xe80);
4208 reg = (reg & ~0x0c000000) | 2 << 26;
4209 urtwn_bb_write(sc, 0xe80, reg);
4210 reg = urtwn_bb_read(sc, 0xe88);
4211 reg = (reg & ~0x0c000000) | 2 << 26;
4212 urtwn_bb_write(sc, 0xe88, reg);
4213 }
4214
4215 /* Write AGC values. */
4216 for (i = 0; i < prog->agccount; i++) {
4217 urtwn_bb_write(sc, R92C_OFDM0_AGCRSSITABLE,
4218 prog->agcvals[i]);
4219 urtwn_ms_delay(sc);
4220 }
4221
4222 if (sc->chip & URTWN_CHIP_88E) {
4223 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553422);
4224 urtwn_ms_delay(sc);
4225 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553420);
4226 urtwn_ms_delay(sc);
4227
4228 crystalcap = sc->rom.r88e_rom.crystalcap;
4229 if (crystalcap == 0xff)
4230 crystalcap = 0x20;
4231 crystalcap &= 0x3f;
4232 reg = urtwn_bb_read(sc, R92C_AFE_XTAL_CTRL);
4233 urtwn_bb_write(sc, R92C_AFE_XTAL_CTRL,
4234 RW(reg, R92C_AFE_XTAL_CTRL_ADDR,
4235 crystalcap | crystalcap << 6));
4236 } else {
4237 if (urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)) &
4238 R92C_HSSI_PARAM2_CCK_HIPWR)
4239 sc->sc_flags |= URTWN_FLAG_CCK_HIPWR;
4240 }
4241}
4242
4243static void
4244urtwn_rf_init(struct urtwn_softc *sc)
4245{
4246 const struct urtwn_rf_prog *prog;
4247 uint32_t reg, type;
4248 int i, j, idx, off;
4249
4250 /* Select RF programming based on board type. */
4251 if (sc->chip & URTWN_CHIP_88E)
4252 prog = rtl8188eu_rf_prog;
4253 else if (!(sc->chip & URTWN_CHIP_92C)) {
4254 if (sc->board_type == R92C_BOARD_TYPE_MINICARD)
4255 prog = rtl8188ce_rf_prog;
4256 else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA)
4257 prog = rtl8188ru_rf_prog;
4258 else
4259 prog = rtl8188cu_rf_prog;
4260 } else
4261 prog = rtl8192ce_rf_prog;
4262
4263 for (i = 0; i < sc->nrxchains; i++) {
4264 /* Save RF_ENV control type. */
4265 idx = i / 2;
4266 off = (i % 2) * 16;
4267 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx));
4268 type = (reg >> off) & 0x10;
4269
4270 /* Set RF_ENV enable. */
4271 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i));
4272 reg |= 0x100000;
4273 urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg);
4274 urtwn_ms_delay(sc);
4275 /* Set RF_ENV output high. */
4276 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i));
4277 reg |= 0x10;
4278 urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg);
4279 urtwn_ms_delay(sc);
4280 /* Set address and data lengths of RF registers. */
4281 reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i));
4282 reg &= ~R92C_HSSI_PARAM2_ADDR_LENGTH;
4283 urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg);
4284 urtwn_ms_delay(sc);
4285 reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i));
4286 reg &= ~R92C_HSSI_PARAM2_DATA_LENGTH;
4287 urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg);
4288 urtwn_ms_delay(sc);
4289
4290 /* Write RF initialization values for this chain. */
4291 for (j = 0; j < prog[i].count; j++) {
4292 if (prog[i].regs[j] >= 0xf9 &&
4293 prog[i].regs[j] <= 0xfe) {
4294 /*
4295 * These are fake RF registers offsets that
4296 * indicate a delay is required.
4297 */
4298 usb_pause_mtx(&sc->sc_mtx, hz / 20); /* 50ms */
4299 continue;
4300 }
4301 urtwn_rf_write(sc, i, prog[i].regs[j],
4302 prog[i].vals[j]);
4303 urtwn_ms_delay(sc);
4304 }
4305
4306 /* Restore RF_ENV control type. */
4307 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx));
4308 reg &= ~(0x10 << off) | (type << off);
4309 urtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(idx), reg);
4310
4311 /* Cache RF register CHNLBW. */
4312 sc->rf_chnlbw[i] = urtwn_rf_read(sc, i, R92C_RF_CHNLBW);
4313 }
4314
4315 if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) ==
4316 URTWN_CHIP_UMC_A_CUT) {
4317 urtwn_rf_write(sc, 0, R92C_RF_RX_G1, 0x30255);
4318 urtwn_rf_write(sc, 0, R92C_RF_RX_G2, 0x50a00);
4319 }
4320}
4321
4322static void
4323urtwn_cam_init(struct urtwn_softc *sc)
4324{
4325 /* Invalidate all CAM entries. */
4326 urtwn_write_4(sc, R92C_CAMCMD,
4327 R92C_CAMCMD_POLLING | R92C_CAMCMD_CLR);
4328}
4329
4330static int
4331urtwn_cam_write(struct urtwn_softc *sc, uint32_t addr, uint32_t data)
4332{
4333 usb_error_t error;
4334
4335 error = urtwn_write_4(sc, R92C_CAMWRITE, data);
4336 if (error != USB_ERR_NORMAL_COMPLETION)
4337 return (EIO);
4338 error = urtwn_write_4(sc, R92C_CAMCMD,
4339 R92C_CAMCMD_POLLING | R92C_CAMCMD_WRITE |
4340 SM(R92C_CAMCMD_ADDR, addr));
4341 if (error != USB_ERR_NORMAL_COMPLETION)
4342 return (EIO);
4343
4344 return (0);
4345}
4346
4347static void
4348urtwn_pa_bias_init(struct urtwn_softc *sc)
4349{
4350 uint8_t reg;
4351 int i;
4352
4353 for (i = 0; i < sc->nrxchains; i++) {
4354 if (sc->pa_setting & (1 << i))
4355 continue;
4356 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x0f406);
4357 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x4f406);
4358 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x8f406);
4359 urtwn_rf_write(sc, i, R92C_RF_IPA, 0xcf406);
4360 }
4361 if (!(sc->pa_setting & 0x10)) {
4362 reg = urtwn_read_1(sc, 0x16);
4363 reg = (reg & ~0xf0) | 0x90;
4364 urtwn_write_1(sc, 0x16, reg);
4365 }
4366}
4367
4368static void
4369urtwn_rxfilter_init(struct urtwn_softc *sc)
4370{
4371 struct ieee80211com *ic = &sc->sc_ic;
4372 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps);
4373 uint32_t rcr;
4374 uint16_t filter;
4375
4376 URTWN_ASSERT_LOCKED(sc);
4377
4378 /* Setup multicast filter. */
4379 urtwn_set_multi(sc);
4380
4381 /* Filter for management frames. */
4382 filter = 0x7f3f;
4383 switch (vap->iv_opmode) {
4384 case IEEE80211_M_STA:
4385 filter &= ~(
4386 R92C_RXFLTMAP_SUBTYPE(IEEE80211_FC0_SUBTYPE_ASSOC_REQ) |
4387 R92C_RXFLTMAP_SUBTYPE(IEEE80211_FC0_SUBTYPE_REASSOC_REQ) |
4388 R92C_RXFLTMAP_SUBTYPE(IEEE80211_FC0_SUBTYPE_PROBE_REQ));
4389 break;
4390 case IEEE80211_M_HOSTAP:
4391 filter &= ~(
4392 R92C_RXFLTMAP_SUBTYPE(IEEE80211_FC0_SUBTYPE_ASSOC_RESP) |
4393 R92C_RXFLTMAP_SUBTYPE(IEEE80211_FC0_SUBTYPE_REASSOC_RESP));
4394 break;
4395 case IEEE80211_M_MONITOR:
4396 case IEEE80211_M_IBSS:
4397 break;
4398 default:
4399 device_printf(sc->sc_dev, "%s: undefined opmode %d\n",
4400 __func__, vap->iv_opmode);
4401 break;
4402 }
4403 urtwn_write_2(sc, R92C_RXFLTMAP0, filter);
4404
4405 /* Reject all control frames. */
4406 urtwn_write_2(sc, R92C_RXFLTMAP1, 0x0000);
4407
4408 /* Reject all data frames. */
4409 urtwn_write_2(sc, R92C_RXFLTMAP2, 0x0000);
4410
4411 rcr = R92C_RCR_AM | R92C_RCR_AB | R92C_RCR_APM |
4412 R92C_RCR_HTC_LOC_CTRL | R92C_RCR_APP_PHYSTS |
4413 R92C_RCR_APP_ICV | R92C_RCR_APP_MIC;
4414
4415 if (vap->iv_opmode == IEEE80211_M_MONITOR) {
4416 /* Accept all frames. */
4417 rcr |= R92C_RCR_ACF | R92C_RCR_ADF | R92C_RCR_AMF |
4418 R92C_RCR_AAP;
4419 }
4420
4421 /* Set Rx filter. */
4422 urtwn_write_4(sc, R92C_RCR, rcr);
4423
4424 if (ic->ic_promisc != 0) {
4425 /* Update Rx filter. */
4426 urtwn_set_promisc(sc);
4427 }
4428}
4429
4430static void
4431urtwn_edca_init(struct urtwn_softc *sc)
4432{
4433 urtwn_write_2(sc, R92C_SPEC_SIFS, 0x100a);
4434 urtwn_write_2(sc, R92C_MAC_SPEC_SIFS, 0x100a);
4435 urtwn_write_2(sc, R92C_SIFS_CCK, 0x100a);
4436 urtwn_write_2(sc, R92C_SIFS_OFDM, 0x100a);
4437 urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x005ea42b);
4438 urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a44f);
4439 urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005ea324);
4440 urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002fa226);
4441}
4442
4443static void
4444urtwn_write_txpower(struct urtwn_softc *sc, int chain,
4445 uint16_t power[URTWN_RIDX_COUNT])
4446{
4447 uint32_t reg;
4448
4449 /* Write per-CCK rate Tx power. */
4450 if (chain == 0) {
4451 reg = urtwn_bb_read(sc, R92C_TXAGC_A_CCK1_MCS32);
4452 reg = RW(reg, R92C_TXAGC_A_CCK1, power[0]);
4453 urtwn_bb_write(sc, R92C_TXAGC_A_CCK1_MCS32, reg);
4454 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11);
4455 reg = RW(reg, R92C_TXAGC_A_CCK2, power[1]);
4456 reg = RW(reg, R92C_TXAGC_A_CCK55, power[2]);
4457 reg = RW(reg, R92C_TXAGC_A_CCK11, power[3]);
4458 urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg);
4459 } else {
4460 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK1_55_MCS32);
4461 reg = RW(reg, R92C_TXAGC_B_CCK1, power[0]);
4462 reg = RW(reg, R92C_TXAGC_B_CCK2, power[1]);
4463 reg = RW(reg, R92C_TXAGC_B_CCK55, power[2]);
4464 urtwn_bb_write(sc, R92C_TXAGC_B_CCK1_55_MCS32, reg);
4465 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11);
4466 reg = RW(reg, R92C_TXAGC_B_CCK11, power[3]);
4467 urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg);
4468 }
4469 /* Write per-OFDM rate Tx power. */
4470 urtwn_bb_write(sc, R92C_TXAGC_RATE18_06(chain),
4471 SM(R92C_TXAGC_RATE06, power[ 4]) |
4472 SM(R92C_TXAGC_RATE09, power[ 5]) |
4473 SM(R92C_TXAGC_RATE12, power[ 6]) |
4474 SM(R92C_TXAGC_RATE18, power[ 7]));
4475 urtwn_bb_write(sc, R92C_TXAGC_RATE54_24(chain),
4476 SM(R92C_TXAGC_RATE24, power[ 8]) |
4477 SM(R92C_TXAGC_RATE36, power[ 9]) |
4478 SM(R92C_TXAGC_RATE48, power[10]) |
4479 SM(R92C_TXAGC_RATE54, power[11]));
4480 /* Write per-MCS Tx power. */
4481 urtwn_bb_write(sc, R92C_TXAGC_MCS03_MCS00(chain),
4482 SM(R92C_TXAGC_MCS00, power[12]) |
4483 SM(R92C_TXAGC_MCS01, power[13]) |
4484 SM(R92C_TXAGC_MCS02, power[14]) |
4485 SM(R92C_TXAGC_MCS03, power[15]));
4486 urtwn_bb_write(sc, R92C_TXAGC_MCS07_MCS04(chain),
4487 SM(R92C_TXAGC_MCS04, power[16]) |
4488 SM(R92C_TXAGC_MCS05, power[17]) |
4489 SM(R92C_TXAGC_MCS06, power[18]) |
4490 SM(R92C_TXAGC_MCS07, power[19]));
4491 urtwn_bb_write(sc, R92C_TXAGC_MCS11_MCS08(chain),
4492 SM(R92C_TXAGC_MCS08, power[20]) |
4493 SM(R92C_TXAGC_MCS09, power[21]) |
4494 SM(R92C_TXAGC_MCS10, power[22]) |
4495 SM(R92C_TXAGC_MCS11, power[23]));
4496 urtwn_bb_write(sc, R92C_TXAGC_MCS15_MCS12(chain),
4497 SM(R92C_TXAGC_MCS12, power[24]) |
4498 SM(R92C_TXAGC_MCS13, power[25]) |
4499 SM(R92C_TXAGC_MCS14, power[26]) |
4500 SM(R92C_TXAGC_MCS15, power[27]));
4501}
4502
4503static void
4504urtwn_get_txpower(struct urtwn_softc *sc, int chain,
4505 struct ieee80211_channel *c, struct ieee80211_channel *extc,
4506 uint16_t power[URTWN_RIDX_COUNT])
4507{
4508 struct ieee80211com *ic = &sc->sc_ic;
4509 struct r92c_rom *rom = &sc->rom.r92c_rom;
4510 uint16_t cckpow, ofdmpow, htpow, diff, max;
4511 const struct urtwn_txpwr *base;
4512 int ridx, chan, group;
4513
4514 /* Determine channel group. */
4515 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */
4516 if (chan <= 3)
4517 group = 0;
4518 else if (chan <= 9)
4519 group = 1;
4520 else
4521 group = 2;
4522
4523 /* Get original Tx power based on board type and RF chain. */
4524 if (!(sc->chip & URTWN_CHIP_92C)) {
4525 if (sc->board_type == R92C_BOARD_TYPE_HIGHPA)
4526 base = &rtl8188ru_txagc[chain];
4527 else
4528 base = &rtl8192cu_txagc[chain];
4529 } else
4530 base = &rtl8192cu_txagc[chain];
4531
4532 memset(power, 0, URTWN_RIDX_COUNT * sizeof(power[0]));
4533 if (sc->regulatory == 0) {
4534 for (ridx = URTWN_RIDX_CCK1; ridx <= URTWN_RIDX_CCK11; ridx++)
4535 power[ridx] = base->pwr[0][ridx];
4536 }
4537 for (ridx = URTWN_RIDX_OFDM6; ridx < URTWN_RIDX_COUNT; ridx++) {
4538 if (sc->regulatory == 3) {
4539 power[ridx] = base->pwr[0][ridx];
4540 /* Apply vendor limits. */
4541 if (extc != NULL)
4542 max = rom->ht40_max_pwr[group];
4543 else
4544 max = rom->ht20_max_pwr[group];
4545 max = (max >> (chain * 4)) & 0xf;
4546 if (power[ridx] > max)
4547 power[ridx] = max;
4548 } else if (sc->regulatory == 1) {
4549 if (extc == NULL)
4550 power[ridx] = base->pwr[group][ridx];
4551 } else if (sc->regulatory != 2)
4552 power[ridx] = base->pwr[0][ridx];
4553 }
4554
4555 /* Compute per-CCK rate Tx power. */
4556 cckpow = rom->cck_tx_pwr[chain][group];
4557 for (ridx = URTWN_RIDX_CCK1; ridx <= URTWN_RIDX_CCK11; ridx++) {
4558 power[ridx] += cckpow;
4559 if (power[ridx] > R92C_MAX_TX_PWR)
4560 power[ridx] = R92C_MAX_TX_PWR;
4561 }
4562
4563 htpow = rom->ht40_1s_tx_pwr[chain][group];
4564 if (sc->ntxchains > 1) {
4565 /* Apply reduction for 2 spatial streams. */
4566 diff = rom->ht40_2s_tx_pwr_diff[group];
4567 diff = (diff >> (chain * 4)) & 0xf;
4568 htpow = (htpow > diff) ? htpow - diff : 0;
4569 }
4570
4571 /* Compute per-OFDM rate Tx power. */
4572 diff = rom->ofdm_tx_pwr_diff[group];
4573 diff = (diff >> (chain * 4)) & 0xf;
4574 ofdmpow = htpow + diff; /* HT->OFDM correction. */
4575 for (ridx = URTWN_RIDX_OFDM6; ridx <= URTWN_RIDX_OFDM54; ridx++) {
4576 power[ridx] += ofdmpow;
4577 if (power[ridx] > R92C_MAX_TX_PWR)
4578 power[ridx] = R92C_MAX_TX_PWR;
4579 }
4580
4581 /* Compute per-MCS Tx power. */
4582 if (extc == NULL) {
4583 diff = rom->ht20_tx_pwr_diff[group];
4584 diff = (diff >> (chain * 4)) & 0xf;
4585 htpow += diff; /* HT40->HT20 correction. */
4586 }
4587 for (ridx = 12; ridx <= 27; ridx++) {
4588 power[ridx] += htpow;
4589 if (power[ridx] > R92C_MAX_TX_PWR)
4590 power[ridx] = R92C_MAX_TX_PWR;
4591 }
4592#ifdef USB_DEBUG
4593 if (sc->sc_debug & URTWN_DEBUG_TXPWR) {
4594 /* Dump per-rate Tx power values. */
4595 printf("Tx power for chain %d:\n", chain);
4596 for (ridx = URTWN_RIDX_CCK1; ridx < URTWN_RIDX_COUNT; ridx++)
4597 printf("Rate %d = %u\n", ridx, power[ridx]);
4598 }
4599#endif
4600}
4601
4602static void
4603urtwn_r88e_get_txpower(struct urtwn_softc *sc, int chain,
4604 struct ieee80211_channel *c, struct ieee80211_channel *extc,
4605 uint16_t power[URTWN_RIDX_COUNT])
4606{
4607 struct ieee80211com *ic = &sc->sc_ic;
4608 struct r88e_rom *rom = &sc->rom.r88e_rom;
4609 uint16_t cckpow, ofdmpow, bw20pow, htpow;
4610 const struct urtwn_r88e_txpwr *base;
4611 int ridx, chan, group;
4612
4613 /* Determine channel group. */
4614 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */
4615 if (chan <= 2)
4616 group = 0;
4617 else if (chan <= 5)
4618 group = 1;
4619 else if (chan <= 8)
4620 group = 2;
4621 else if (chan <= 11)
4622 group = 3;
4623 else if (chan <= 13)
4624 group = 4;
4625 else
4626 group = 5;
4627
4628 /* Get original Tx power based on board type and RF chain. */
4629 base = &rtl8188eu_txagc[chain];
4630
4631 memset(power, 0, URTWN_RIDX_COUNT * sizeof(power[0]));
4632 if (sc->regulatory == 0) {
4633 for (ridx = URTWN_RIDX_CCK1; ridx <= URTWN_RIDX_CCK11; ridx++)
4634 power[ridx] = base->pwr[0][ridx];
4635 }
4636 for (ridx = URTWN_RIDX_OFDM6; ridx < URTWN_RIDX_COUNT; ridx++) {
4637 if (sc->regulatory == 3)
4638 power[ridx] = base->pwr[0][ridx];
4639 else if (sc->regulatory == 1) {
4640 if (extc == NULL)
4641 power[ridx] = base->pwr[group][ridx];
4642 } else if (sc->regulatory != 2)
4643 power[ridx] = base->pwr[0][ridx];
4644 }
4645
4646 /* Compute per-CCK rate Tx power. */
4647 cckpow = rom->cck_tx_pwr[group];
4648 for (ridx = URTWN_RIDX_CCK1; ridx <= URTWN_RIDX_CCK11; ridx++) {
4649 power[ridx] += cckpow;
4650 if (power[ridx] > R92C_MAX_TX_PWR)
4651 power[ridx] = R92C_MAX_TX_PWR;
4652 }
4653
4654 htpow = rom->ht40_tx_pwr[group];
4655
4656 /* Compute per-OFDM rate Tx power. */
4657 ofdmpow = htpow + sc->ofdm_tx_pwr_diff;
4658 for (ridx = URTWN_RIDX_OFDM6; ridx <= URTWN_RIDX_OFDM54; ridx++) {
4659 power[ridx] += ofdmpow;
4660 if (power[ridx] > R92C_MAX_TX_PWR)
4661 power[ridx] = R92C_MAX_TX_PWR;
4662 }
4663
4664 bw20pow = htpow + sc->bw20_tx_pwr_diff;
4665 for (ridx = 12; ridx <= 27; ridx++) {
4666 power[ridx] += bw20pow;
4667 if (power[ridx] > R92C_MAX_TX_PWR)
4668 power[ridx] = R92C_MAX_TX_PWR;
4669 }
4670}
4671
4672static void
4673urtwn_set_txpower(struct urtwn_softc *sc, struct ieee80211_channel *c,
4674 struct ieee80211_channel *extc)
4675{
4676 uint16_t power[URTWN_RIDX_COUNT];
4677 int i;
4678
4679 for (i = 0; i < sc->ntxchains; i++) {
4680 /* Compute per-rate Tx power values. */
4681 if (sc->chip & URTWN_CHIP_88E)
4682 urtwn_r88e_get_txpower(sc, i, c, extc, power);
4683 else
4684 urtwn_get_txpower(sc, i, c, extc, power);
4685 /* Write per-rate Tx power values to hardware. */
4686 urtwn_write_txpower(sc, i, power);
4687 }
4688}
4689
4690static void
4691urtwn_set_rx_bssid_all(struct urtwn_softc *sc, int enable)
4692{
4693 uint32_t reg;
4694
4695 reg = urtwn_read_4(sc, R92C_RCR);
4696 if (enable)
4697 reg &= ~R92C_RCR_CBSSID_BCN;
4698 else
4699 reg |= R92C_RCR_CBSSID_BCN;
4700 urtwn_write_4(sc, R92C_RCR, reg);
4701}
4702
4703static void
4704urtwn_set_gain(struct urtwn_softc *sc, uint8_t gain)
4705{
4706 uint32_t reg;
4707
4708 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0));
4709 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, gain);
4710 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg);
4711
4712 if (!(sc->chip & URTWN_CHIP_88E)) {
4713 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1));
4714 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, gain);
4715 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg);
4716 }
4717}
4718
4719static void
4720urtwn_scan_start(struct ieee80211com *ic)
4721{
4722 struct urtwn_softc *sc = ic->ic_softc;
4723
4724 URTWN_LOCK(sc);
4725 /* Receive beacons / probe responses from any BSSID. */
4726 if (ic->ic_opmode != IEEE80211_M_IBSS)
4727 urtwn_set_rx_bssid_all(sc, 1);
4728
4729 /* Set gain for scanning. */
4730 urtwn_set_gain(sc, 0x20);
4731 URTWN_UNLOCK(sc);
4732}
4733
4734static void
4735urtwn_scan_end(struct ieee80211com *ic)
4736{
4737 struct urtwn_softc *sc = ic->ic_softc;
4738
4739 URTWN_LOCK(sc);
4740 /* Restore limitations. */
4741 if (ic->ic_promisc == 0 && ic->ic_opmode != IEEE80211_M_IBSS)
4742 urtwn_set_rx_bssid_all(sc, 0);
4743
4744 /* Set gain under link. */
4745 urtwn_set_gain(sc, 0x32);
4746 URTWN_UNLOCK(sc);
4747}
4748
4749static void
|
4747urtwn_set_channel(struct ieee80211com *ic)
4748{
4749 struct urtwn_softc *sc = ic->ic_softc;
4750 struct ieee80211_channel *c = ic->ic_curchan;
4751 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps);
4752
4753 URTWN_LOCK(sc);
4754 if (vap->iv_state == IEEE80211_S_SCAN) {
4755 /* Make link LED blink during scan. */
4756 urtwn_set_led(sc, URTWN_LED_LINK, !sc->ledlink);
4757 }
4758 urtwn_set_chan(sc, c, NULL);
4759 sc->sc_rxtap.wr_chan_freq = htole16(c->ic_freq);
4760 sc->sc_rxtap.wr_chan_flags = htole16(c->ic_flags);
4761 sc->sc_txtap.wt_chan_freq = htole16(c->ic_freq);
4762 sc->sc_txtap.wt_chan_flags = htole16(c->ic_flags);
4763 URTWN_UNLOCK(sc);
4764}
4765
4766static int
4767urtwn_wme_update(struct ieee80211com *ic)
4768{
4769 const struct wmeParams *wmep =
4770 ic->ic_wme.wme_chanParams.cap_wmeParams;
4771 struct urtwn_softc *sc = ic->ic_softc;
4772 uint8_t aifs, acm, slottime;
4773 int ac;
4774
4775 acm = 0;
4776 slottime = IEEE80211_GET_SLOTTIME(ic);
4777
4778 URTWN_LOCK(sc);
4779 for (ac = WME_AC_BE; ac < WME_NUM_AC; ac++) {
4780 /* AIFS[AC] = AIFSN[AC] * aSlotTime + aSIFSTime. */
4781 aifs = wmep[ac].wmep_aifsn * slottime + IEEE80211_DUR_SIFS;
4782 urtwn_write_4(sc, wme2queue[ac].reg,
4783 SM(R92C_EDCA_PARAM_TXOP, wmep[ac].wmep_txopLimit) |
4784 SM(R92C_EDCA_PARAM_ECWMIN, wmep[ac].wmep_logcwmin) |
4785 SM(R92C_EDCA_PARAM_ECWMAX, wmep[ac].wmep_logcwmax) |
4786 SM(R92C_EDCA_PARAM_AIFS, aifs));
4787 if (ac != WME_AC_BE)
4788 acm |= wmep[ac].wmep_acm << ac;
4789 }
4790
4791 if (acm != 0)
4792 acm |= R92C_ACMHWCTRL_EN;
4793 urtwn_write_1(sc, R92C_ACMHWCTRL,
4794 (urtwn_read_1(sc, R92C_ACMHWCTRL) & ~R92C_ACMHWCTRL_ACM_MASK) |
4795 acm);
4796
4797 URTWN_UNLOCK(sc);
4798
4799 return 0;
4800}
4801
4802static void
4803urtwn_update_slot(struct ieee80211com *ic)
4804{
4805 urtwn_cmd_sleepable(ic->ic_softc, NULL, 0, urtwn_update_slot_cb);
4806}
4807
4808static void
4809urtwn_update_slot_cb(struct urtwn_softc *sc, union sec_param *data)
4810{
4811 struct ieee80211com *ic = &sc->sc_ic;
4812 uint8_t slottime;
4813
4814 slottime = IEEE80211_GET_SLOTTIME(ic);
4815
4816 URTWN_DPRINTF(sc, URTWN_DEBUG_ANY, "%s: setting slot time to %uus\n",
4817 __func__, slottime);
4818
4819 urtwn_write_1(sc, R92C_SLOT, slottime);
4820 urtwn_update_aifs(sc, slottime);
4821}
4822
4823static void
4824urtwn_update_aifs(struct urtwn_softc *sc, uint8_t slottime)
4825{
4826 const struct wmeParams *wmep =
4827 sc->sc_ic.ic_wme.wme_chanParams.cap_wmeParams;
4828 uint8_t aifs, ac;
4829
4830 for (ac = WME_AC_BE; ac < WME_NUM_AC; ac++) {
4831 /* AIFS[AC] = AIFSN[AC] * aSlotTime + aSIFSTime. */
4832 aifs = wmep[ac].wmep_aifsn * slottime + IEEE80211_DUR_SIFS;
4833 urtwn_write_1(sc, wme2queue[ac].reg, aifs);
4834 }
4835}
4836
4837static uint8_t
4838urtwn_get_multi_pos(const uint8_t maddr[])
4839{
4840 uint64_t mask = 0x00004d101df481b4;
4841 uint8_t pos = 0x27; /* initial value */
4842 int i, j;
4843
4844 for (i = 0; i < IEEE80211_ADDR_LEN; i++)
4845 for (j = (i == 0) ? 1 : 0; j < 8; j++)
4846 if ((maddr[i] >> j) & 1)
4847 pos ^= (mask >> (i * 8 + j - 1));
4848
4849 pos &= 0x3f;
4850
4851 return (pos);
4852}
4853
4854static void
4855urtwn_set_multi(struct urtwn_softc *sc)
4856{
4857 struct ieee80211com *ic = &sc->sc_ic;
4858 uint32_t mfilt[2];
4859
4860 URTWN_ASSERT_LOCKED(sc);
4861
4862 /* general structure was copied from ath(4). */
4863 if (ic->ic_allmulti == 0) {
4864 struct ieee80211vap *vap;
4865 struct ifnet *ifp;
4866 struct ifmultiaddr *ifma;
4867
4868 /*
4869 * Merge multicast addresses to form the hardware filter.
4870 */
4871 mfilt[0] = mfilt[1] = 0;
4872 TAILQ_FOREACH(vap, &ic->ic_vaps, iv_next) {
4873 ifp = vap->iv_ifp;
4874 if_maddr_rlock(ifp);
4875 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
4876 caddr_t dl;
4877 uint8_t pos;
4878
4879 dl = LLADDR((struct sockaddr_dl *)
4880 ifma->ifma_addr);
4881 pos = urtwn_get_multi_pos(dl);
4882
4883 mfilt[pos / 32] |= (1 << (pos % 32));
4884 }
4885 if_maddr_runlock(ifp);
4886 }
4887 } else
4888 mfilt[0] = mfilt[1] = ~0;
4889
4890
4891 urtwn_write_4(sc, R92C_MAR + 0, mfilt[0]);
4892 urtwn_write_4(sc, R92C_MAR + 4, mfilt[1]);
4893
4894 URTWN_DPRINTF(sc, URTWN_DEBUG_STATE, "%s: MC filter %08x:%08x\n",
4895 __func__, mfilt[0], mfilt[1]);
4896}
4897
4898static void
4899urtwn_set_promisc(struct urtwn_softc *sc)
4900{
4901 struct ieee80211com *ic = &sc->sc_ic;
4902 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps);
4903 uint32_t rcr, mask1, mask2;
4904
4905 URTWN_ASSERT_LOCKED(sc);
4906
4907 if (vap->iv_opmode == IEEE80211_M_MONITOR)
4908 return;
4909
4910 mask1 = R92C_RCR_ACF | R92C_RCR_ADF | R92C_RCR_AMF | R92C_RCR_AAP;
4911 mask2 = R92C_RCR_APM;
4912
4913 if (vap->iv_state == IEEE80211_S_RUN) {
4914 switch (vap->iv_opmode) {
4915 case IEEE80211_M_STA:
4916 mask2 |= R92C_RCR_CBSSID_DATA;
4917 /* FALLTHROUGH */
4918 case IEEE80211_M_HOSTAP:
4919 mask2 |= R92C_RCR_CBSSID_BCN;
4920 break;
4921 case IEEE80211_M_IBSS:
4922 mask2 |= R92C_RCR_CBSSID_DATA;
4923 break;
4924 default:
4925 device_printf(sc->sc_dev, "%s: undefined opmode %d\n",
4926 __func__, vap->iv_opmode);
4927 return;
4928 }
4929 }
4930
4931 rcr = urtwn_read_4(sc, R92C_RCR);
4932 if (ic->ic_promisc == 0)
4933 rcr = (rcr & ~mask1) | mask2;
4934 else
4935 rcr = (rcr & ~mask2) | mask1;
4936 urtwn_write_4(sc, R92C_RCR, rcr);
4937}
4938
4939static void
4940urtwn_update_promisc(struct ieee80211com *ic)
4941{
4942 struct urtwn_softc *sc = ic->ic_softc;
4943
4944 URTWN_LOCK(sc);
4945 if (sc->sc_flags & URTWN_RUNNING)
4946 urtwn_set_promisc(sc);
4947 URTWN_UNLOCK(sc);
4948}
4949
4950static void
4951urtwn_update_mcast(struct ieee80211com *ic)
4952{
4953 struct urtwn_softc *sc = ic->ic_softc;
4954
4955 URTWN_LOCK(sc);
4956 if (sc->sc_flags & URTWN_RUNNING)
4957 urtwn_set_multi(sc);
4958 URTWN_UNLOCK(sc);
4959}
4960
4961static struct ieee80211_node *
4962urtwn_node_alloc(struct ieee80211vap *vap,
4963 const uint8_t mac[IEEE80211_ADDR_LEN])
4964{
4965 struct urtwn_node *un;
4966
4967 un = malloc(sizeof (struct urtwn_node), M_80211_NODE,
4968 M_NOWAIT | M_ZERO);
4969
4970 if (un == NULL)
4971 return NULL;
4972
4973 un->id = URTWN_MACID_UNDEFINED;
4974
4975 return &un->ni;
4976}
4977
4978static void
4979urtwn_newassoc(struct ieee80211_node *ni, int isnew)
4980{
4981 struct urtwn_softc *sc = ni->ni_ic->ic_softc;
4982 struct urtwn_node *un = URTWN_NODE(ni);
4983 uint8_t id;
4984
4985 /* Only do this bit for R88E chips */
4986 if (! (sc->chip & URTWN_CHIP_88E))
4987 return;
4988
4989 if (!isnew)
4990 return;
4991
4992 URTWN_NT_LOCK(sc);
4993 for (id = 0; id <= URTWN_MACID_MAX(sc); id++) {
4994 if (id != URTWN_MACID_BC && sc->node_list[id] == NULL) {
4995 un->id = id;
4996 sc->node_list[id] = ni;
4997 break;
4998 }
4999 }
5000 URTWN_NT_UNLOCK(sc);
5001
5002 if (id > URTWN_MACID_MAX(sc)) {
5003 device_printf(sc->sc_dev, "%s: node table is full\n",
5004 __func__);
5005 }
5006}
5007
5008static void
5009urtwn_node_free(struct ieee80211_node *ni)
5010{
5011 struct urtwn_softc *sc = ni->ni_ic->ic_softc;
5012 struct urtwn_node *un = URTWN_NODE(ni);
5013
5014 URTWN_NT_LOCK(sc);
5015 if (un->id != URTWN_MACID_UNDEFINED)
5016 sc->node_list[un->id] = NULL;
5017 URTWN_NT_UNLOCK(sc);
5018
5019 sc->sc_node_free(ni);
5020}
5021
5022static void
5023urtwn_set_chan(struct urtwn_softc *sc, struct ieee80211_channel *c,
5024 struct ieee80211_channel *extc)
5025{
5026 struct ieee80211com *ic = &sc->sc_ic;
5027 uint32_t reg;
5028 u_int chan;
5029 int i;
5030
5031 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */
5032 if (chan == 0 || chan == IEEE80211_CHAN_ANY) {
5033 device_printf(sc->sc_dev,
5034 "%s: invalid channel %x\n", __func__, chan);
5035 return;
5036 }
5037
5038 /* Set Tx power for this new channel. */
5039 urtwn_set_txpower(sc, c, extc);
5040
5041 for (i = 0; i < sc->nrxchains; i++) {
5042 urtwn_rf_write(sc, i, R92C_RF_CHNLBW,
5043 RW(sc->rf_chnlbw[i], R92C_RF_CHNLBW_CHNL, chan));
5044 }
5045#ifndef IEEE80211_NO_HT
5046 if (extc != NULL) {
5047 /* Is secondary channel below or above primary? */
5048 int prichlo = c->ic_freq < extc->ic_freq;
5049
5050 urtwn_write_1(sc, R92C_BWOPMODE,
5051 urtwn_read_1(sc, R92C_BWOPMODE) & ~R92C_BWOPMODE_20MHZ);
5052
5053 reg = urtwn_read_1(sc, R92C_RRSR + 2);
5054 reg = (reg & ~0x6f) | (prichlo ? 1 : 2) << 5;
5055 urtwn_write_1(sc, R92C_RRSR + 2, reg);
5056
5057 urtwn_bb_write(sc, R92C_FPGA0_RFMOD,
5058 urtwn_bb_read(sc, R92C_FPGA0_RFMOD) | R92C_RFMOD_40MHZ);
5059 urtwn_bb_write(sc, R92C_FPGA1_RFMOD,
5060 urtwn_bb_read(sc, R92C_FPGA1_RFMOD) | R92C_RFMOD_40MHZ);
5061
5062 /* Set CCK side band. */
5063 reg = urtwn_bb_read(sc, R92C_CCK0_SYSTEM);
5064 reg = (reg & ~0x00000010) | (prichlo ? 0 : 1) << 4;
5065 urtwn_bb_write(sc, R92C_CCK0_SYSTEM, reg);
5066
5067 reg = urtwn_bb_read(sc, R92C_OFDM1_LSTF);
5068 reg = (reg & ~0x00000c00) | (prichlo ? 1 : 2) << 10;
5069 urtwn_bb_write(sc, R92C_OFDM1_LSTF, reg);
5070
5071 urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2,
5072 urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) &
5073 ~R92C_FPGA0_ANAPARAM2_CBW20);
5074
5075 reg = urtwn_bb_read(sc, 0x818);
5076 reg = (reg & ~0x0c000000) | (prichlo ? 2 : 1) << 26;
5077 urtwn_bb_write(sc, 0x818, reg);
5078
5079 /* Select 40MHz bandwidth. */
5080 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW,
5081 (sc->rf_chnlbw[0] & ~0xfff) | chan);
5082 } else
5083#endif
5084 {
5085 urtwn_write_1(sc, R92C_BWOPMODE,
5086 urtwn_read_1(sc, R92C_BWOPMODE) | R92C_BWOPMODE_20MHZ);
5087
5088 urtwn_bb_write(sc, R92C_FPGA0_RFMOD,
5089 urtwn_bb_read(sc, R92C_FPGA0_RFMOD) & ~R92C_RFMOD_40MHZ);
5090 urtwn_bb_write(sc, R92C_FPGA1_RFMOD,
5091 urtwn_bb_read(sc, R92C_FPGA1_RFMOD) & ~R92C_RFMOD_40MHZ);
5092
5093 if (!(sc->chip & URTWN_CHIP_88E)) {
5094 urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2,
5095 urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) |
5096 R92C_FPGA0_ANAPARAM2_CBW20);
5097 }
5098
5099 /* Select 20MHz bandwidth. */
5100 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW,
5101 (sc->rf_chnlbw[0] & ~0xfff) | chan |
5102 ((sc->chip & URTWN_CHIP_88E) ? R88E_RF_CHNLBW_BW20 :
5103 R92C_RF_CHNLBW_BW20));
5104 }
5105}
5106
5107static void
5108urtwn_iq_calib(struct urtwn_softc *sc)
5109{
5110 /* TODO */
5111}
5112
5113static void
5114urtwn_lc_calib(struct urtwn_softc *sc)
5115{
5116 uint32_t rf_ac[2];
5117 uint8_t txmode;
5118 int i;
5119
5120 txmode = urtwn_read_1(sc, R92C_OFDM1_LSTF + 3);
5121 if ((txmode & 0x70) != 0) {
5122 /* Disable all continuous Tx. */
5123 urtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode & ~0x70);
5124
5125 /* Set RF mode to standby mode. */
5126 for (i = 0; i < sc->nrxchains; i++) {
5127 rf_ac[i] = urtwn_rf_read(sc, i, R92C_RF_AC);
5128 urtwn_rf_write(sc, i, R92C_RF_AC,
5129 RW(rf_ac[i], R92C_RF_AC_MODE,
5130 R92C_RF_AC_MODE_STANDBY));
5131 }
5132 } else {
5133 /* Block all Tx queues. */
5134 urtwn_write_1(sc, R92C_TXPAUSE, R92C_TX_QUEUE_ALL);
5135 }
5136 /* Start calibration. */
5137 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW,
5138 urtwn_rf_read(sc, 0, R92C_RF_CHNLBW) | R92C_RF_CHNLBW_LCSTART);
5139
5140 /* Give calibration the time to complete. */
5141 usb_pause_mtx(&sc->sc_mtx, hz / 10); /* 100ms */
5142
5143 /* Restore configuration. */
5144 if ((txmode & 0x70) != 0) {
5145 /* Restore Tx mode. */
5146 urtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode);
5147 /* Restore RF mode. */
5148 for (i = 0; i < sc->nrxchains; i++)
5149 urtwn_rf_write(sc, i, R92C_RF_AC, rf_ac[i]);
5150 } else {
5151 /* Unblock all Tx queues. */
5152 urtwn_write_1(sc, R92C_TXPAUSE, 0x00);
5153 }
5154}
5155
5156static void
5157urtwn_temp_calib(struct urtwn_softc *sc)
5158{
5159 uint8_t temp;
5160
5161 URTWN_ASSERT_LOCKED(sc);
5162
5163 if (!(sc->sc_flags & URTWN_TEMP_MEASURED)) {
5164 /* Start measuring temperature. */
5165 URTWN_DPRINTF(sc, URTWN_DEBUG_TEMP,
5166 "%s: start measuring temperature\n", __func__);
5167 if (sc->chip & URTWN_CHIP_88E) {
5168 urtwn_rf_write(sc, 0, R88E_RF_T_METER,
5169 R88E_RF_T_METER_START);
5170 } else {
5171 urtwn_rf_write(sc, 0, R92C_RF_T_METER,
5172 R92C_RF_T_METER_START);
5173 }
5174 sc->sc_flags |= URTWN_TEMP_MEASURED;
5175 return;
5176 }
5177 sc->sc_flags &= ~URTWN_TEMP_MEASURED;
5178
5179 /* Read measured temperature. */
5180 if (sc->chip & URTWN_CHIP_88E) {
5181 temp = MS(urtwn_rf_read(sc, 0, R88E_RF_T_METER),
5182 R88E_RF_T_METER_VAL);
5183 } else {
5184 temp = MS(urtwn_rf_read(sc, 0, R92C_RF_T_METER),
5185 R92C_RF_T_METER_VAL);
5186 }
5187 if (temp == 0) { /* Read failed, skip. */
5188 URTWN_DPRINTF(sc, URTWN_DEBUG_TEMP,
5189 "%s: temperature read failed, skipping\n", __func__);
5190 return;
5191 }
5192
5193 URTWN_DPRINTF(sc, URTWN_DEBUG_TEMP,
5194 "%s: temperature: previous %u, current %u\n",
5195 __func__, sc->thcal_lctemp, temp);
5196
5197 /*
5198 * Redo LC calibration if temperature changed significantly since
5199 * last calibration.
5200 */
5201 if (sc->thcal_lctemp == 0) {
5202 /* First LC calibration is performed in urtwn_init(). */
5203 sc->thcal_lctemp = temp;
5204 } else if (abs(temp - sc->thcal_lctemp) > 1) {
5205 URTWN_DPRINTF(sc, URTWN_DEBUG_TEMP,
5206 "%s: LC calib triggered by temp: %u -> %u\n",
5207 __func__, sc->thcal_lctemp, temp);
5208 urtwn_lc_calib(sc);
5209 /* Record temperature of last LC calibration. */
5210 sc->thcal_lctemp = temp;
5211 }
5212}
5213
5214static int
5215urtwn_init(struct urtwn_softc *sc)
5216{
5217 struct ieee80211com *ic = &sc->sc_ic;
5218 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps);
5219 uint8_t macaddr[IEEE80211_ADDR_LEN];
5220 uint32_t reg;
5221 usb_error_t usb_err = USB_ERR_NORMAL_COMPLETION;
5222 int error;
5223
5224 URTWN_LOCK(sc);
5225 if (sc->sc_flags & URTWN_RUNNING) {
5226 URTWN_UNLOCK(sc);
5227 return (0);
5228 }
5229
5230 /* Init firmware commands ring. */
5231 sc->fwcur = 0;
5232
5233 /* Allocate Tx/Rx buffers. */
5234 error = urtwn_alloc_rx_list(sc);
5235 if (error != 0)
5236 goto fail;
5237
5238 error = urtwn_alloc_tx_list(sc);
5239 if (error != 0)
5240 goto fail;
5241
5242 /* Power on adapter. */
5243 error = urtwn_power_on(sc);
5244 if (error != 0)
5245 goto fail;
5246
5247 /* Initialize DMA. */
5248 error = urtwn_dma_init(sc);
5249 if (error != 0)
5250 goto fail;
5251
5252 /* Set info size in Rx descriptors (in 64-bit words). */
5253 urtwn_write_1(sc, R92C_RX_DRVINFO_SZ, 4);
5254
5255 /* Init interrupts. */
5256 if (sc->chip & URTWN_CHIP_88E) {
5257 usb_err = urtwn_write_4(sc, R88E_HISR, 0xffffffff);
5258 if (usb_err != USB_ERR_NORMAL_COMPLETION)
5259 goto fail;
5260 usb_err = urtwn_write_4(sc, R88E_HIMR, R88E_HIMR_CPWM | R88E_HIMR_CPWM2 |
5261 R88E_HIMR_TBDER | R88E_HIMR_PSTIMEOUT);
5262 if (usb_err != USB_ERR_NORMAL_COMPLETION)
5263 goto fail;
5264 usb_err = urtwn_write_4(sc, R88E_HIMRE, R88E_HIMRE_RXFOVW |
5265 R88E_HIMRE_TXFOVW | R88E_HIMRE_RXERR | R88E_HIMRE_TXERR);
5266 if (usb_err != USB_ERR_NORMAL_COMPLETION)
5267 goto fail;
5268 usb_err = urtwn_write_1(sc, R92C_USB_SPECIAL_OPTION,
5269 urtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) |
5270 R92C_USB_SPECIAL_OPTION_INT_BULK_SEL);
5271 if (usb_err != USB_ERR_NORMAL_COMPLETION)
5272 goto fail;
5273 } else {
5274 usb_err = urtwn_write_4(sc, R92C_HISR, 0xffffffff);
5275 if (usb_err != USB_ERR_NORMAL_COMPLETION)
5276 goto fail;
5277 usb_err = urtwn_write_4(sc, R92C_HIMR, 0xffffffff);
5278 if (usb_err != USB_ERR_NORMAL_COMPLETION)
5279 goto fail;
5280 }
5281
5282 /* Set MAC address. */
5283 IEEE80211_ADDR_COPY(macaddr, vap ? vap->iv_myaddr : ic->ic_macaddr);
5284 usb_err = urtwn_write_region_1(sc, R92C_MACID, macaddr, IEEE80211_ADDR_LEN);
5285 if (usb_err != USB_ERR_NORMAL_COMPLETION)
5286 goto fail;
5287
5288 /* Set initial network type. */
5289 urtwn_set_mode(sc, R92C_MSR_INFRA);
5290
5291 /* Initialize Rx filter. */
5292 urtwn_rxfilter_init(sc);
5293
5294 /* Set response rate. */
5295 reg = urtwn_read_4(sc, R92C_RRSR);
5296 reg = RW(reg, R92C_RRSR_RATE_BITMAP, R92C_RRSR_RATE_CCK_ONLY_1M);
5297 urtwn_write_4(sc, R92C_RRSR, reg);
5298
5299 /* Set short/long retry limits. */
5300 urtwn_write_2(sc, R92C_RL,
5301 SM(R92C_RL_SRL, 0x30) | SM(R92C_RL_LRL, 0x30));
5302
5303 /* Initialize EDCA parameters. */
5304 urtwn_edca_init(sc);
5305
5306 /* Setup rate fallback. */
5307 if (!(sc->chip & URTWN_CHIP_88E)) {
5308 urtwn_write_4(sc, R92C_DARFRC + 0, 0x00000000);
5309 urtwn_write_4(sc, R92C_DARFRC + 4, 0x10080404);
5310 urtwn_write_4(sc, R92C_RARFRC + 0, 0x04030201);
5311 urtwn_write_4(sc, R92C_RARFRC + 4, 0x08070605);
5312 }
5313
5314 urtwn_write_1(sc, R92C_FWHW_TXQ_CTRL,
5315 urtwn_read_1(sc, R92C_FWHW_TXQ_CTRL) |
5316 R92C_FWHW_TXQ_CTRL_AMPDU_RTY_NEW);
5317 /* Set ACK timeout. */
5318 urtwn_write_1(sc, R92C_ACKTO, 0x40);
5319
5320 /* Setup USB aggregation. */
5321 reg = urtwn_read_4(sc, R92C_TDECTRL);
5322 reg = RW(reg, R92C_TDECTRL_BLK_DESC_NUM, 6);
5323 urtwn_write_4(sc, R92C_TDECTRL, reg);
5324 urtwn_write_1(sc, R92C_TRXDMA_CTRL,
5325 urtwn_read_1(sc, R92C_TRXDMA_CTRL) |
5326 R92C_TRXDMA_CTRL_RXDMA_AGG_EN);
5327 urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH, 48);
5328 if (sc->chip & URTWN_CHIP_88E)
5329 urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH + 1, 4);
5330 else {
5331 urtwn_write_1(sc, R92C_USB_DMA_AGG_TO, 4);
5332 urtwn_write_1(sc, R92C_USB_SPECIAL_OPTION,
5333 urtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) |
5334 R92C_USB_SPECIAL_OPTION_AGG_EN);
5335 urtwn_write_1(sc, R92C_USB_AGG_TH, 8);
5336 urtwn_write_1(sc, R92C_USB_AGG_TO, 6);
5337 }
5338
5339 /* Initialize beacon parameters. */
5340 urtwn_write_2(sc, R92C_BCN_CTRL, 0x1010);
5341 urtwn_write_2(sc, R92C_TBTT_PROHIBIT, 0x6404);
5342 urtwn_write_1(sc, R92C_DRVERLYINT, 0x05);
5343 urtwn_write_1(sc, R92C_BCNDMATIM, 0x02);
5344 urtwn_write_2(sc, R92C_BCNTCFG, 0x660f);
5345
5346 if (!(sc->chip & URTWN_CHIP_88E)) {
5347 /* Setup AMPDU aggregation. */
5348 urtwn_write_4(sc, R92C_AGGLEN_LMT, 0x99997631); /* MCS7~0 */
5349 urtwn_write_1(sc, R92C_AGGR_BREAK_TIME, 0x16);
5350 urtwn_write_2(sc, R92C_MAX_AGGR_NUM, 0x0708);
5351
5352 urtwn_write_1(sc, R92C_BCN_MAX_ERR, 0xff);
5353 }
5354
5355#ifndef URTWN_WITHOUT_UCODE
5356 /* Load 8051 microcode. */
5357 error = urtwn_load_firmware(sc);
5358 if (error == 0)
5359 sc->sc_flags |= URTWN_FW_LOADED;
5360#endif
5361
5362 /* Initialize MAC/BB/RF blocks. */
5363 error = urtwn_mac_init(sc);
5364 if (error != 0) {
5365 device_printf(sc->sc_dev,
5366 "%s: error while initializing MAC block\n", __func__);
5367 goto fail;
5368 }
5369 urtwn_bb_init(sc);
5370 urtwn_rf_init(sc);
5371
5372 /* Reinitialize Rx filter (D3845 is not committed yet). */
5373 urtwn_rxfilter_init(sc);
5374
5375 if (sc->chip & URTWN_CHIP_88E) {
5376 urtwn_write_2(sc, R92C_CR,
5377 urtwn_read_2(sc, R92C_CR) | R92C_CR_MACTXEN |
5378 R92C_CR_MACRXEN);
5379 }
5380
5381 /* Turn CCK and OFDM blocks on. */
5382 reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD);
5383 reg |= R92C_RFMOD_CCK_EN;
5384 usb_err = urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg);
5385 if (usb_err != USB_ERR_NORMAL_COMPLETION)
5386 goto fail;
5387 reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD);
5388 reg |= R92C_RFMOD_OFDM_EN;
5389 usb_err = urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg);
5390 if (usb_err != USB_ERR_NORMAL_COMPLETION)
5391 goto fail;
5392
5393 /* Clear per-station keys table. */
5394 urtwn_cam_init(sc);
5395
5396 /* Enable decryption / encryption. */
5397 urtwn_write_2(sc, R92C_SECCFG,
5398 R92C_SECCFG_TXUCKEY_DEF | R92C_SECCFG_RXUCKEY_DEF |
5399 R92C_SECCFG_TXENC_ENA | R92C_SECCFG_RXDEC_ENA |
5400 R92C_SECCFG_TXBCKEY_DEF | R92C_SECCFG_RXBCKEY_DEF);
5401
5402 /*
5403 * Install static keys (if any).
5404 * Must be called after urtwn_cam_init().
5405 */
5406 ieee80211_runtask(ic, &sc->cmdq_task);
5407
5408 /* Enable hardware sequence numbering. */
5409 urtwn_write_1(sc, R92C_HWSEQ_CTRL, R92C_TX_QUEUE_ALL);
5410
5411 /* Enable per-packet TX report. */
5412 if (sc->chip & URTWN_CHIP_88E) {
5413 urtwn_write_1(sc, R88E_TX_RPT_CTRL,
5414 urtwn_read_1(sc, R88E_TX_RPT_CTRL) | R88E_TX_RPT1_ENA);
5415 }
5416
5417 /* Perform LO and IQ calibrations. */
5418 urtwn_iq_calib(sc);
5419 /* Perform LC calibration. */
5420 urtwn_lc_calib(sc);
5421
5422 /* Fix USB interference issue. */
5423 if (!(sc->chip & URTWN_CHIP_88E)) {
5424 urtwn_write_1(sc, 0xfe40, 0xe0);
5425 urtwn_write_1(sc, 0xfe41, 0x8d);
5426 urtwn_write_1(sc, 0xfe42, 0x80);
5427
5428 urtwn_pa_bias_init(sc);
5429 }
5430
5431 /* Initialize GPIO setting. */
5432 urtwn_write_1(sc, R92C_GPIO_MUXCFG,
5433 urtwn_read_1(sc, R92C_GPIO_MUXCFG) & ~R92C_GPIO_MUXCFG_ENBT);
5434
5435 /* Fix for lower temperature. */
5436 if (!(sc->chip & URTWN_CHIP_88E))
5437 urtwn_write_1(sc, 0x15, 0xe9);
5438
5439 usbd_transfer_start(sc->sc_xfer[URTWN_BULK_RX]);
5440
5441 sc->sc_flags |= URTWN_RUNNING;
5442
5443 callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc);
5444fail:
5445 if (usb_err != USB_ERR_NORMAL_COMPLETION)
5446 error = EIO;
5447
5448 URTWN_UNLOCK(sc);
5449
5450 return (error);
5451}
5452
5453static void
5454urtwn_stop(struct urtwn_softc *sc)
5455{
5456
5457 URTWN_LOCK(sc);
5458 if (!(sc->sc_flags & URTWN_RUNNING)) {
5459 URTWN_UNLOCK(sc);
5460 return;
5461 }
5462
5463 sc->sc_flags &= ~(URTWN_RUNNING | URTWN_FW_LOADED |
5464 URTWN_TEMP_MEASURED);
5465 sc->thcal_lctemp = 0;
5466 callout_stop(&sc->sc_watchdog_ch);
5467
5468 urtwn_abort_xfers(sc);
5469 urtwn_drain_mbufq(sc);
5470 urtwn_power_off(sc);
5471 URTWN_UNLOCK(sc);
5472}
5473
5474static void
5475urtwn_abort_xfers(struct urtwn_softc *sc)
5476{
5477 int i;
5478
5479 URTWN_ASSERT_LOCKED(sc);
5480
5481 /* abort any pending transfers */
5482 for (i = 0; i < URTWN_N_TRANSFER; i++)
5483 usbd_transfer_stop(sc->sc_xfer[i]);
5484}
5485
5486static int
5487urtwn_raw_xmit(struct ieee80211_node *ni, struct mbuf *m,
5488 const struct ieee80211_bpf_params *params)
5489{
5490 struct ieee80211com *ic = ni->ni_ic;
5491 struct urtwn_softc *sc = ic->ic_softc;
5492 struct urtwn_data *bf;
5493 int error;
5494
5495 URTWN_DPRINTF(sc, URTWN_DEBUG_XMIT, "%s: called; m=%p\n",
5496 __func__,
5497 m);
5498
5499 /* prevent management frames from being sent if we're not ready */
5500 URTWN_LOCK(sc);
5501 if (!(sc->sc_flags & URTWN_RUNNING)) {
5502 error = ENETDOWN;
5503 goto end;
5504 }
5505
5506 bf = urtwn_getbuf(sc);
5507 if (bf == NULL) {
5508 error = ENOBUFS;
5509 goto end;
5510 }
5511
5512 if (params == NULL) {
5513 /*
5514 * Legacy path; interpret frame contents to decide
5515 * precisely how to send the frame.
5516 */
5517 error = urtwn_tx_data(sc, ni, m, bf);
5518 } else {
5519 /*
5520 * Caller supplied explicit parameters to use in
5521 * sending the frame.
5522 */
5523 error = urtwn_tx_raw(sc, ni, m, bf, params);
5524 }
5525 if (error != 0) {
5526 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, bf, next);
5527 goto end;
5528 }
5529
5530 sc->sc_txtimer = 5;
5531 callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc);
5532
5533end:
5534 if (error != 0)
5535 m_freem(m);
5536
5537 URTWN_UNLOCK(sc);
5538
5539 return (error);
5540}
5541
5542static void
5543urtwn_ms_delay(struct urtwn_softc *sc)
5544{
5545 usb_pause_mtx(&sc->sc_mtx, hz / 1000);
5546}
5547
5548static device_method_t urtwn_methods[] = {
5549 /* Device interface */
5550 DEVMETHOD(device_probe, urtwn_match),
5551 DEVMETHOD(device_attach, urtwn_attach),
5552 DEVMETHOD(device_detach, urtwn_detach),
5553
5554 DEVMETHOD_END
5555};
5556
5557static driver_t urtwn_driver = {
5558 "urtwn",
5559 urtwn_methods,
5560 sizeof(struct urtwn_softc)
5561};
5562
5563static devclass_t urtwn_devclass;
5564
5565DRIVER_MODULE(urtwn, uhub, urtwn_driver, urtwn_devclass, NULL, NULL);
5566MODULE_DEPEND(urtwn, usb, 1, 1, 1);
5567MODULE_DEPEND(urtwn, wlan, 1, 1, 1);
5568#ifndef URTWN_WITHOUT_UCODE
5569MODULE_DEPEND(urtwn, firmware, 1, 1, 1);
5570#endif
5571MODULE_VERSION(urtwn, 1);
5572USB_PNP_HOST_INFO(urtwn_devs);
| 4765urtwn_set_channel(struct ieee80211com *ic)
4766{
4767 struct urtwn_softc *sc = ic->ic_softc;
4768 struct ieee80211_channel *c = ic->ic_curchan;
4769 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps);
4770
4771 URTWN_LOCK(sc);
4772 if (vap->iv_state == IEEE80211_S_SCAN) {
4773 /* Make link LED blink during scan. */
4774 urtwn_set_led(sc, URTWN_LED_LINK, !sc->ledlink);
4775 }
4776 urtwn_set_chan(sc, c, NULL);
4777 sc->sc_rxtap.wr_chan_freq = htole16(c->ic_freq);
4778 sc->sc_rxtap.wr_chan_flags = htole16(c->ic_flags);
4779 sc->sc_txtap.wt_chan_freq = htole16(c->ic_freq);
4780 sc->sc_txtap.wt_chan_flags = htole16(c->ic_flags);
4781 URTWN_UNLOCK(sc);
4782}
4783
4784static int
4785urtwn_wme_update(struct ieee80211com *ic)
4786{
4787 const struct wmeParams *wmep =
4788 ic->ic_wme.wme_chanParams.cap_wmeParams;
4789 struct urtwn_softc *sc = ic->ic_softc;
4790 uint8_t aifs, acm, slottime;
4791 int ac;
4792
4793 acm = 0;
4794 slottime = IEEE80211_GET_SLOTTIME(ic);
4795
4796 URTWN_LOCK(sc);
4797 for (ac = WME_AC_BE; ac < WME_NUM_AC; ac++) {
4798 /* AIFS[AC] = AIFSN[AC] * aSlotTime + aSIFSTime. */
4799 aifs = wmep[ac].wmep_aifsn * slottime + IEEE80211_DUR_SIFS;
4800 urtwn_write_4(sc, wme2queue[ac].reg,
4801 SM(R92C_EDCA_PARAM_TXOP, wmep[ac].wmep_txopLimit) |
4802 SM(R92C_EDCA_PARAM_ECWMIN, wmep[ac].wmep_logcwmin) |
4803 SM(R92C_EDCA_PARAM_ECWMAX, wmep[ac].wmep_logcwmax) |
4804 SM(R92C_EDCA_PARAM_AIFS, aifs));
4805 if (ac != WME_AC_BE)
4806 acm |= wmep[ac].wmep_acm << ac;
4807 }
4808
4809 if (acm != 0)
4810 acm |= R92C_ACMHWCTRL_EN;
4811 urtwn_write_1(sc, R92C_ACMHWCTRL,
4812 (urtwn_read_1(sc, R92C_ACMHWCTRL) & ~R92C_ACMHWCTRL_ACM_MASK) |
4813 acm);
4814
4815 URTWN_UNLOCK(sc);
4816
4817 return 0;
4818}
4819
4820static void
4821urtwn_update_slot(struct ieee80211com *ic)
4822{
4823 urtwn_cmd_sleepable(ic->ic_softc, NULL, 0, urtwn_update_slot_cb);
4824}
4825
4826static void
4827urtwn_update_slot_cb(struct urtwn_softc *sc, union sec_param *data)
4828{
4829 struct ieee80211com *ic = &sc->sc_ic;
4830 uint8_t slottime;
4831
4832 slottime = IEEE80211_GET_SLOTTIME(ic);
4833
4834 URTWN_DPRINTF(sc, URTWN_DEBUG_ANY, "%s: setting slot time to %uus\n",
4835 __func__, slottime);
4836
4837 urtwn_write_1(sc, R92C_SLOT, slottime);
4838 urtwn_update_aifs(sc, slottime);
4839}
4840
4841static void
4842urtwn_update_aifs(struct urtwn_softc *sc, uint8_t slottime)
4843{
4844 const struct wmeParams *wmep =
4845 sc->sc_ic.ic_wme.wme_chanParams.cap_wmeParams;
4846 uint8_t aifs, ac;
4847
4848 for (ac = WME_AC_BE; ac < WME_NUM_AC; ac++) {
4849 /* AIFS[AC] = AIFSN[AC] * aSlotTime + aSIFSTime. */
4850 aifs = wmep[ac].wmep_aifsn * slottime + IEEE80211_DUR_SIFS;
4851 urtwn_write_1(sc, wme2queue[ac].reg, aifs);
4852 }
4853}
4854
4855static uint8_t
4856urtwn_get_multi_pos(const uint8_t maddr[])
4857{
4858 uint64_t mask = 0x00004d101df481b4;
4859 uint8_t pos = 0x27; /* initial value */
4860 int i, j;
4861
4862 for (i = 0; i < IEEE80211_ADDR_LEN; i++)
4863 for (j = (i == 0) ? 1 : 0; j < 8; j++)
4864 if ((maddr[i] >> j) & 1)
4865 pos ^= (mask >> (i * 8 + j - 1));
4866
4867 pos &= 0x3f;
4868
4869 return (pos);
4870}
4871
4872static void
4873urtwn_set_multi(struct urtwn_softc *sc)
4874{
4875 struct ieee80211com *ic = &sc->sc_ic;
4876 uint32_t mfilt[2];
4877
4878 URTWN_ASSERT_LOCKED(sc);
4879
4880 /* general structure was copied from ath(4). */
4881 if (ic->ic_allmulti == 0) {
4882 struct ieee80211vap *vap;
4883 struct ifnet *ifp;
4884 struct ifmultiaddr *ifma;
4885
4886 /*
4887 * Merge multicast addresses to form the hardware filter.
4888 */
4889 mfilt[0] = mfilt[1] = 0;
4890 TAILQ_FOREACH(vap, &ic->ic_vaps, iv_next) {
4891 ifp = vap->iv_ifp;
4892 if_maddr_rlock(ifp);
4893 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
4894 caddr_t dl;
4895 uint8_t pos;
4896
4897 dl = LLADDR((struct sockaddr_dl *)
4898 ifma->ifma_addr);
4899 pos = urtwn_get_multi_pos(dl);
4900
4901 mfilt[pos / 32] |= (1 << (pos % 32));
4902 }
4903 if_maddr_runlock(ifp);
4904 }
4905 } else
4906 mfilt[0] = mfilt[1] = ~0;
4907
4908
4909 urtwn_write_4(sc, R92C_MAR + 0, mfilt[0]);
4910 urtwn_write_4(sc, R92C_MAR + 4, mfilt[1]);
4911
4912 URTWN_DPRINTF(sc, URTWN_DEBUG_STATE, "%s: MC filter %08x:%08x\n",
4913 __func__, mfilt[0], mfilt[1]);
4914}
4915
4916static void
4917urtwn_set_promisc(struct urtwn_softc *sc)
4918{
4919 struct ieee80211com *ic = &sc->sc_ic;
4920 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps);
4921 uint32_t rcr, mask1, mask2;
4922
4923 URTWN_ASSERT_LOCKED(sc);
4924
4925 if (vap->iv_opmode == IEEE80211_M_MONITOR)
4926 return;
4927
4928 mask1 = R92C_RCR_ACF | R92C_RCR_ADF | R92C_RCR_AMF | R92C_RCR_AAP;
4929 mask2 = R92C_RCR_APM;
4930
4931 if (vap->iv_state == IEEE80211_S_RUN) {
4932 switch (vap->iv_opmode) {
4933 case IEEE80211_M_STA:
4934 mask2 |= R92C_RCR_CBSSID_DATA;
4935 /* FALLTHROUGH */
4936 case IEEE80211_M_HOSTAP:
4937 mask2 |= R92C_RCR_CBSSID_BCN;
4938 break;
4939 case IEEE80211_M_IBSS:
4940 mask2 |= R92C_RCR_CBSSID_DATA;
4941 break;
4942 default:
4943 device_printf(sc->sc_dev, "%s: undefined opmode %d\n",
4944 __func__, vap->iv_opmode);
4945 return;
4946 }
4947 }
4948
4949 rcr = urtwn_read_4(sc, R92C_RCR);
4950 if (ic->ic_promisc == 0)
4951 rcr = (rcr & ~mask1) | mask2;
4952 else
4953 rcr = (rcr & ~mask2) | mask1;
4954 urtwn_write_4(sc, R92C_RCR, rcr);
4955}
4956
4957static void
4958urtwn_update_promisc(struct ieee80211com *ic)
4959{
4960 struct urtwn_softc *sc = ic->ic_softc;
4961
4962 URTWN_LOCK(sc);
4963 if (sc->sc_flags & URTWN_RUNNING)
4964 urtwn_set_promisc(sc);
4965 URTWN_UNLOCK(sc);
4966}
4967
4968static void
4969urtwn_update_mcast(struct ieee80211com *ic)
4970{
4971 struct urtwn_softc *sc = ic->ic_softc;
4972
4973 URTWN_LOCK(sc);
4974 if (sc->sc_flags & URTWN_RUNNING)
4975 urtwn_set_multi(sc);
4976 URTWN_UNLOCK(sc);
4977}
4978
4979static struct ieee80211_node *
4980urtwn_node_alloc(struct ieee80211vap *vap,
4981 const uint8_t mac[IEEE80211_ADDR_LEN])
4982{
4983 struct urtwn_node *un;
4984
4985 un = malloc(sizeof (struct urtwn_node), M_80211_NODE,
4986 M_NOWAIT | M_ZERO);
4987
4988 if (un == NULL)
4989 return NULL;
4990
4991 un->id = URTWN_MACID_UNDEFINED;
4992
4993 return &un->ni;
4994}
4995
4996static void
4997urtwn_newassoc(struct ieee80211_node *ni, int isnew)
4998{
4999 struct urtwn_softc *sc = ni->ni_ic->ic_softc;
5000 struct urtwn_node *un = URTWN_NODE(ni);
5001 uint8_t id;
5002
5003 /* Only do this bit for R88E chips */
5004 if (! (sc->chip & URTWN_CHIP_88E))
5005 return;
5006
5007 if (!isnew)
5008 return;
5009
5010 URTWN_NT_LOCK(sc);
5011 for (id = 0; id <= URTWN_MACID_MAX(sc); id++) {
5012 if (id != URTWN_MACID_BC && sc->node_list[id] == NULL) {
5013 un->id = id;
5014 sc->node_list[id] = ni;
5015 break;
5016 }
5017 }
5018 URTWN_NT_UNLOCK(sc);
5019
5020 if (id > URTWN_MACID_MAX(sc)) {
5021 device_printf(sc->sc_dev, "%s: node table is full\n",
5022 __func__);
5023 }
5024}
5025
5026static void
5027urtwn_node_free(struct ieee80211_node *ni)
5028{
5029 struct urtwn_softc *sc = ni->ni_ic->ic_softc;
5030 struct urtwn_node *un = URTWN_NODE(ni);
5031
5032 URTWN_NT_LOCK(sc);
5033 if (un->id != URTWN_MACID_UNDEFINED)
5034 sc->node_list[un->id] = NULL;
5035 URTWN_NT_UNLOCK(sc);
5036
5037 sc->sc_node_free(ni);
5038}
5039
5040static void
5041urtwn_set_chan(struct urtwn_softc *sc, struct ieee80211_channel *c,
5042 struct ieee80211_channel *extc)
5043{
5044 struct ieee80211com *ic = &sc->sc_ic;
5045 uint32_t reg;
5046 u_int chan;
5047 int i;
5048
5049 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */
5050 if (chan == 0 || chan == IEEE80211_CHAN_ANY) {
5051 device_printf(sc->sc_dev,
5052 "%s: invalid channel %x\n", __func__, chan);
5053 return;
5054 }
5055
5056 /* Set Tx power for this new channel. */
5057 urtwn_set_txpower(sc, c, extc);
5058
5059 for (i = 0; i < sc->nrxchains; i++) {
5060 urtwn_rf_write(sc, i, R92C_RF_CHNLBW,
5061 RW(sc->rf_chnlbw[i], R92C_RF_CHNLBW_CHNL, chan));
5062 }
5063#ifndef IEEE80211_NO_HT
5064 if (extc != NULL) {
5065 /* Is secondary channel below or above primary? */
5066 int prichlo = c->ic_freq < extc->ic_freq;
5067
5068 urtwn_write_1(sc, R92C_BWOPMODE,
5069 urtwn_read_1(sc, R92C_BWOPMODE) & ~R92C_BWOPMODE_20MHZ);
5070
5071 reg = urtwn_read_1(sc, R92C_RRSR + 2);
5072 reg = (reg & ~0x6f) | (prichlo ? 1 : 2) << 5;
5073 urtwn_write_1(sc, R92C_RRSR + 2, reg);
5074
5075 urtwn_bb_write(sc, R92C_FPGA0_RFMOD,
5076 urtwn_bb_read(sc, R92C_FPGA0_RFMOD) | R92C_RFMOD_40MHZ);
5077 urtwn_bb_write(sc, R92C_FPGA1_RFMOD,
5078 urtwn_bb_read(sc, R92C_FPGA1_RFMOD) | R92C_RFMOD_40MHZ);
5079
5080 /* Set CCK side band. */
5081 reg = urtwn_bb_read(sc, R92C_CCK0_SYSTEM);
5082 reg = (reg & ~0x00000010) | (prichlo ? 0 : 1) << 4;
5083 urtwn_bb_write(sc, R92C_CCK0_SYSTEM, reg);
5084
5085 reg = urtwn_bb_read(sc, R92C_OFDM1_LSTF);
5086 reg = (reg & ~0x00000c00) | (prichlo ? 1 : 2) << 10;
5087 urtwn_bb_write(sc, R92C_OFDM1_LSTF, reg);
5088
5089 urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2,
5090 urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) &
5091 ~R92C_FPGA0_ANAPARAM2_CBW20);
5092
5093 reg = urtwn_bb_read(sc, 0x818);
5094 reg = (reg & ~0x0c000000) | (prichlo ? 2 : 1) << 26;
5095 urtwn_bb_write(sc, 0x818, reg);
5096
5097 /* Select 40MHz bandwidth. */
5098 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW,
5099 (sc->rf_chnlbw[0] & ~0xfff) | chan);
5100 } else
5101#endif
5102 {
5103 urtwn_write_1(sc, R92C_BWOPMODE,
5104 urtwn_read_1(sc, R92C_BWOPMODE) | R92C_BWOPMODE_20MHZ);
5105
5106 urtwn_bb_write(sc, R92C_FPGA0_RFMOD,
5107 urtwn_bb_read(sc, R92C_FPGA0_RFMOD) & ~R92C_RFMOD_40MHZ);
5108 urtwn_bb_write(sc, R92C_FPGA1_RFMOD,
5109 urtwn_bb_read(sc, R92C_FPGA1_RFMOD) & ~R92C_RFMOD_40MHZ);
5110
5111 if (!(sc->chip & URTWN_CHIP_88E)) {
5112 urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2,
5113 urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) |
5114 R92C_FPGA0_ANAPARAM2_CBW20);
5115 }
5116
5117 /* Select 20MHz bandwidth. */
5118 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW,
5119 (sc->rf_chnlbw[0] & ~0xfff) | chan |
5120 ((sc->chip & URTWN_CHIP_88E) ? R88E_RF_CHNLBW_BW20 :
5121 R92C_RF_CHNLBW_BW20));
5122 }
5123}
5124
5125static void
5126urtwn_iq_calib(struct urtwn_softc *sc)
5127{
5128 /* TODO */
5129}
5130
5131static void
5132urtwn_lc_calib(struct urtwn_softc *sc)
5133{
5134 uint32_t rf_ac[2];
5135 uint8_t txmode;
5136 int i;
5137
5138 txmode = urtwn_read_1(sc, R92C_OFDM1_LSTF + 3);
5139 if ((txmode & 0x70) != 0) {
5140 /* Disable all continuous Tx. */
5141 urtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode & ~0x70);
5142
5143 /* Set RF mode to standby mode. */
5144 for (i = 0; i < sc->nrxchains; i++) {
5145 rf_ac[i] = urtwn_rf_read(sc, i, R92C_RF_AC);
5146 urtwn_rf_write(sc, i, R92C_RF_AC,
5147 RW(rf_ac[i], R92C_RF_AC_MODE,
5148 R92C_RF_AC_MODE_STANDBY));
5149 }
5150 } else {
5151 /* Block all Tx queues. */
5152 urtwn_write_1(sc, R92C_TXPAUSE, R92C_TX_QUEUE_ALL);
5153 }
5154 /* Start calibration. */
5155 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW,
5156 urtwn_rf_read(sc, 0, R92C_RF_CHNLBW) | R92C_RF_CHNLBW_LCSTART);
5157
5158 /* Give calibration the time to complete. */
5159 usb_pause_mtx(&sc->sc_mtx, hz / 10); /* 100ms */
5160
5161 /* Restore configuration. */
5162 if ((txmode & 0x70) != 0) {
5163 /* Restore Tx mode. */
5164 urtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode);
5165 /* Restore RF mode. */
5166 for (i = 0; i < sc->nrxchains; i++)
5167 urtwn_rf_write(sc, i, R92C_RF_AC, rf_ac[i]);
5168 } else {
5169 /* Unblock all Tx queues. */
5170 urtwn_write_1(sc, R92C_TXPAUSE, 0x00);
5171 }
5172}
5173
5174static void
5175urtwn_temp_calib(struct urtwn_softc *sc)
5176{
5177 uint8_t temp;
5178
5179 URTWN_ASSERT_LOCKED(sc);
5180
5181 if (!(sc->sc_flags & URTWN_TEMP_MEASURED)) {
5182 /* Start measuring temperature. */
5183 URTWN_DPRINTF(sc, URTWN_DEBUG_TEMP,
5184 "%s: start measuring temperature\n", __func__);
5185 if (sc->chip & URTWN_CHIP_88E) {
5186 urtwn_rf_write(sc, 0, R88E_RF_T_METER,
5187 R88E_RF_T_METER_START);
5188 } else {
5189 urtwn_rf_write(sc, 0, R92C_RF_T_METER,
5190 R92C_RF_T_METER_START);
5191 }
5192 sc->sc_flags |= URTWN_TEMP_MEASURED;
5193 return;
5194 }
5195 sc->sc_flags &= ~URTWN_TEMP_MEASURED;
5196
5197 /* Read measured temperature. */
5198 if (sc->chip & URTWN_CHIP_88E) {
5199 temp = MS(urtwn_rf_read(sc, 0, R88E_RF_T_METER),
5200 R88E_RF_T_METER_VAL);
5201 } else {
5202 temp = MS(urtwn_rf_read(sc, 0, R92C_RF_T_METER),
5203 R92C_RF_T_METER_VAL);
5204 }
5205 if (temp == 0) { /* Read failed, skip. */
5206 URTWN_DPRINTF(sc, URTWN_DEBUG_TEMP,
5207 "%s: temperature read failed, skipping\n", __func__);
5208 return;
5209 }
5210
5211 URTWN_DPRINTF(sc, URTWN_DEBUG_TEMP,
5212 "%s: temperature: previous %u, current %u\n",
5213 __func__, sc->thcal_lctemp, temp);
5214
5215 /*
5216 * Redo LC calibration if temperature changed significantly since
5217 * last calibration.
5218 */
5219 if (sc->thcal_lctemp == 0) {
5220 /* First LC calibration is performed in urtwn_init(). */
5221 sc->thcal_lctemp = temp;
5222 } else if (abs(temp - sc->thcal_lctemp) > 1) {
5223 URTWN_DPRINTF(sc, URTWN_DEBUG_TEMP,
5224 "%s: LC calib triggered by temp: %u -> %u\n",
5225 __func__, sc->thcal_lctemp, temp);
5226 urtwn_lc_calib(sc);
5227 /* Record temperature of last LC calibration. */
5228 sc->thcal_lctemp = temp;
5229 }
5230}
5231
5232static int
5233urtwn_init(struct urtwn_softc *sc)
5234{
5235 struct ieee80211com *ic = &sc->sc_ic;
5236 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps);
5237 uint8_t macaddr[IEEE80211_ADDR_LEN];
5238 uint32_t reg;
5239 usb_error_t usb_err = USB_ERR_NORMAL_COMPLETION;
5240 int error;
5241
5242 URTWN_LOCK(sc);
5243 if (sc->sc_flags & URTWN_RUNNING) {
5244 URTWN_UNLOCK(sc);
5245 return (0);
5246 }
5247
5248 /* Init firmware commands ring. */
5249 sc->fwcur = 0;
5250
5251 /* Allocate Tx/Rx buffers. */
5252 error = urtwn_alloc_rx_list(sc);
5253 if (error != 0)
5254 goto fail;
5255
5256 error = urtwn_alloc_tx_list(sc);
5257 if (error != 0)
5258 goto fail;
5259
5260 /* Power on adapter. */
5261 error = urtwn_power_on(sc);
5262 if (error != 0)
5263 goto fail;
5264
5265 /* Initialize DMA. */
5266 error = urtwn_dma_init(sc);
5267 if (error != 0)
5268 goto fail;
5269
5270 /* Set info size in Rx descriptors (in 64-bit words). */
5271 urtwn_write_1(sc, R92C_RX_DRVINFO_SZ, 4);
5272
5273 /* Init interrupts. */
5274 if (sc->chip & URTWN_CHIP_88E) {
5275 usb_err = urtwn_write_4(sc, R88E_HISR, 0xffffffff);
5276 if (usb_err != USB_ERR_NORMAL_COMPLETION)
5277 goto fail;
5278 usb_err = urtwn_write_4(sc, R88E_HIMR, R88E_HIMR_CPWM | R88E_HIMR_CPWM2 |
5279 R88E_HIMR_TBDER | R88E_HIMR_PSTIMEOUT);
5280 if (usb_err != USB_ERR_NORMAL_COMPLETION)
5281 goto fail;
5282 usb_err = urtwn_write_4(sc, R88E_HIMRE, R88E_HIMRE_RXFOVW |
5283 R88E_HIMRE_TXFOVW | R88E_HIMRE_RXERR | R88E_HIMRE_TXERR);
5284 if (usb_err != USB_ERR_NORMAL_COMPLETION)
5285 goto fail;
5286 usb_err = urtwn_write_1(sc, R92C_USB_SPECIAL_OPTION,
5287 urtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) |
5288 R92C_USB_SPECIAL_OPTION_INT_BULK_SEL);
5289 if (usb_err != USB_ERR_NORMAL_COMPLETION)
5290 goto fail;
5291 } else {
5292 usb_err = urtwn_write_4(sc, R92C_HISR, 0xffffffff);
5293 if (usb_err != USB_ERR_NORMAL_COMPLETION)
5294 goto fail;
5295 usb_err = urtwn_write_4(sc, R92C_HIMR, 0xffffffff);
5296 if (usb_err != USB_ERR_NORMAL_COMPLETION)
5297 goto fail;
5298 }
5299
5300 /* Set MAC address. */
5301 IEEE80211_ADDR_COPY(macaddr, vap ? vap->iv_myaddr : ic->ic_macaddr);
5302 usb_err = urtwn_write_region_1(sc, R92C_MACID, macaddr, IEEE80211_ADDR_LEN);
5303 if (usb_err != USB_ERR_NORMAL_COMPLETION)
5304 goto fail;
5305
5306 /* Set initial network type. */
5307 urtwn_set_mode(sc, R92C_MSR_INFRA);
5308
5309 /* Initialize Rx filter. */
5310 urtwn_rxfilter_init(sc);
5311
5312 /* Set response rate. */
5313 reg = urtwn_read_4(sc, R92C_RRSR);
5314 reg = RW(reg, R92C_RRSR_RATE_BITMAP, R92C_RRSR_RATE_CCK_ONLY_1M);
5315 urtwn_write_4(sc, R92C_RRSR, reg);
5316
5317 /* Set short/long retry limits. */
5318 urtwn_write_2(sc, R92C_RL,
5319 SM(R92C_RL_SRL, 0x30) | SM(R92C_RL_LRL, 0x30));
5320
5321 /* Initialize EDCA parameters. */
5322 urtwn_edca_init(sc);
5323
5324 /* Setup rate fallback. */
5325 if (!(sc->chip & URTWN_CHIP_88E)) {
5326 urtwn_write_4(sc, R92C_DARFRC + 0, 0x00000000);
5327 urtwn_write_4(sc, R92C_DARFRC + 4, 0x10080404);
5328 urtwn_write_4(sc, R92C_RARFRC + 0, 0x04030201);
5329 urtwn_write_4(sc, R92C_RARFRC + 4, 0x08070605);
5330 }
5331
5332 urtwn_write_1(sc, R92C_FWHW_TXQ_CTRL,
5333 urtwn_read_1(sc, R92C_FWHW_TXQ_CTRL) |
5334 R92C_FWHW_TXQ_CTRL_AMPDU_RTY_NEW);
5335 /* Set ACK timeout. */
5336 urtwn_write_1(sc, R92C_ACKTO, 0x40);
5337
5338 /* Setup USB aggregation. */
5339 reg = urtwn_read_4(sc, R92C_TDECTRL);
5340 reg = RW(reg, R92C_TDECTRL_BLK_DESC_NUM, 6);
5341 urtwn_write_4(sc, R92C_TDECTRL, reg);
5342 urtwn_write_1(sc, R92C_TRXDMA_CTRL,
5343 urtwn_read_1(sc, R92C_TRXDMA_CTRL) |
5344 R92C_TRXDMA_CTRL_RXDMA_AGG_EN);
5345 urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH, 48);
5346 if (sc->chip & URTWN_CHIP_88E)
5347 urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH + 1, 4);
5348 else {
5349 urtwn_write_1(sc, R92C_USB_DMA_AGG_TO, 4);
5350 urtwn_write_1(sc, R92C_USB_SPECIAL_OPTION,
5351 urtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) |
5352 R92C_USB_SPECIAL_OPTION_AGG_EN);
5353 urtwn_write_1(sc, R92C_USB_AGG_TH, 8);
5354 urtwn_write_1(sc, R92C_USB_AGG_TO, 6);
5355 }
5356
5357 /* Initialize beacon parameters. */
5358 urtwn_write_2(sc, R92C_BCN_CTRL, 0x1010);
5359 urtwn_write_2(sc, R92C_TBTT_PROHIBIT, 0x6404);
5360 urtwn_write_1(sc, R92C_DRVERLYINT, 0x05);
5361 urtwn_write_1(sc, R92C_BCNDMATIM, 0x02);
5362 urtwn_write_2(sc, R92C_BCNTCFG, 0x660f);
5363
5364 if (!(sc->chip & URTWN_CHIP_88E)) {
5365 /* Setup AMPDU aggregation. */
5366 urtwn_write_4(sc, R92C_AGGLEN_LMT, 0x99997631); /* MCS7~0 */
5367 urtwn_write_1(sc, R92C_AGGR_BREAK_TIME, 0x16);
5368 urtwn_write_2(sc, R92C_MAX_AGGR_NUM, 0x0708);
5369
5370 urtwn_write_1(sc, R92C_BCN_MAX_ERR, 0xff);
5371 }
5372
5373#ifndef URTWN_WITHOUT_UCODE
5374 /* Load 8051 microcode. */
5375 error = urtwn_load_firmware(sc);
5376 if (error == 0)
5377 sc->sc_flags |= URTWN_FW_LOADED;
5378#endif
5379
5380 /* Initialize MAC/BB/RF blocks. */
5381 error = urtwn_mac_init(sc);
5382 if (error != 0) {
5383 device_printf(sc->sc_dev,
5384 "%s: error while initializing MAC block\n", __func__);
5385 goto fail;
5386 }
5387 urtwn_bb_init(sc);
5388 urtwn_rf_init(sc);
5389
5390 /* Reinitialize Rx filter (D3845 is not committed yet). */
5391 urtwn_rxfilter_init(sc);
5392
5393 if (sc->chip & URTWN_CHIP_88E) {
5394 urtwn_write_2(sc, R92C_CR,
5395 urtwn_read_2(sc, R92C_CR) | R92C_CR_MACTXEN |
5396 R92C_CR_MACRXEN);
5397 }
5398
5399 /* Turn CCK and OFDM blocks on. */
5400 reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD);
5401 reg |= R92C_RFMOD_CCK_EN;
5402 usb_err = urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg);
5403 if (usb_err != USB_ERR_NORMAL_COMPLETION)
5404 goto fail;
5405 reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD);
5406 reg |= R92C_RFMOD_OFDM_EN;
5407 usb_err = urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg);
5408 if (usb_err != USB_ERR_NORMAL_COMPLETION)
5409 goto fail;
5410
5411 /* Clear per-station keys table. */
5412 urtwn_cam_init(sc);
5413
5414 /* Enable decryption / encryption. */
5415 urtwn_write_2(sc, R92C_SECCFG,
5416 R92C_SECCFG_TXUCKEY_DEF | R92C_SECCFG_RXUCKEY_DEF |
5417 R92C_SECCFG_TXENC_ENA | R92C_SECCFG_RXDEC_ENA |
5418 R92C_SECCFG_TXBCKEY_DEF | R92C_SECCFG_RXBCKEY_DEF);
5419
5420 /*
5421 * Install static keys (if any).
5422 * Must be called after urtwn_cam_init().
5423 */
5424 ieee80211_runtask(ic, &sc->cmdq_task);
5425
5426 /* Enable hardware sequence numbering. */
5427 urtwn_write_1(sc, R92C_HWSEQ_CTRL, R92C_TX_QUEUE_ALL);
5428
5429 /* Enable per-packet TX report. */
5430 if (sc->chip & URTWN_CHIP_88E) {
5431 urtwn_write_1(sc, R88E_TX_RPT_CTRL,
5432 urtwn_read_1(sc, R88E_TX_RPT_CTRL) | R88E_TX_RPT1_ENA);
5433 }
5434
5435 /* Perform LO and IQ calibrations. */
5436 urtwn_iq_calib(sc);
5437 /* Perform LC calibration. */
5438 urtwn_lc_calib(sc);
5439
5440 /* Fix USB interference issue. */
5441 if (!(sc->chip & URTWN_CHIP_88E)) {
5442 urtwn_write_1(sc, 0xfe40, 0xe0);
5443 urtwn_write_1(sc, 0xfe41, 0x8d);
5444 urtwn_write_1(sc, 0xfe42, 0x80);
5445
5446 urtwn_pa_bias_init(sc);
5447 }
5448
5449 /* Initialize GPIO setting. */
5450 urtwn_write_1(sc, R92C_GPIO_MUXCFG,
5451 urtwn_read_1(sc, R92C_GPIO_MUXCFG) & ~R92C_GPIO_MUXCFG_ENBT);
5452
5453 /* Fix for lower temperature. */
5454 if (!(sc->chip & URTWN_CHIP_88E))
5455 urtwn_write_1(sc, 0x15, 0xe9);
5456
5457 usbd_transfer_start(sc->sc_xfer[URTWN_BULK_RX]);
5458
5459 sc->sc_flags |= URTWN_RUNNING;
5460
5461 callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc);
5462fail:
5463 if (usb_err != USB_ERR_NORMAL_COMPLETION)
5464 error = EIO;
5465
5466 URTWN_UNLOCK(sc);
5467
5468 return (error);
5469}
5470
5471static void
5472urtwn_stop(struct urtwn_softc *sc)
5473{
5474
5475 URTWN_LOCK(sc);
5476 if (!(sc->sc_flags & URTWN_RUNNING)) {
5477 URTWN_UNLOCK(sc);
5478 return;
5479 }
5480
5481 sc->sc_flags &= ~(URTWN_RUNNING | URTWN_FW_LOADED |
5482 URTWN_TEMP_MEASURED);
5483 sc->thcal_lctemp = 0;
5484 callout_stop(&sc->sc_watchdog_ch);
5485
5486 urtwn_abort_xfers(sc);
5487 urtwn_drain_mbufq(sc);
5488 urtwn_power_off(sc);
5489 URTWN_UNLOCK(sc);
5490}
5491
5492static void
5493urtwn_abort_xfers(struct urtwn_softc *sc)
5494{
5495 int i;
5496
5497 URTWN_ASSERT_LOCKED(sc);
5498
5499 /* abort any pending transfers */
5500 for (i = 0; i < URTWN_N_TRANSFER; i++)
5501 usbd_transfer_stop(sc->sc_xfer[i]);
5502}
5503
5504static int
5505urtwn_raw_xmit(struct ieee80211_node *ni, struct mbuf *m,
5506 const struct ieee80211_bpf_params *params)
5507{
5508 struct ieee80211com *ic = ni->ni_ic;
5509 struct urtwn_softc *sc = ic->ic_softc;
5510 struct urtwn_data *bf;
5511 int error;
5512
5513 URTWN_DPRINTF(sc, URTWN_DEBUG_XMIT, "%s: called; m=%p\n",
5514 __func__,
5515 m);
5516
5517 /* prevent management frames from being sent if we're not ready */
5518 URTWN_LOCK(sc);
5519 if (!(sc->sc_flags & URTWN_RUNNING)) {
5520 error = ENETDOWN;
5521 goto end;
5522 }
5523
5524 bf = urtwn_getbuf(sc);
5525 if (bf == NULL) {
5526 error = ENOBUFS;
5527 goto end;
5528 }
5529
5530 if (params == NULL) {
5531 /*
5532 * Legacy path; interpret frame contents to decide
5533 * precisely how to send the frame.
5534 */
5535 error = urtwn_tx_data(sc, ni, m, bf);
5536 } else {
5537 /*
5538 * Caller supplied explicit parameters to use in
5539 * sending the frame.
5540 */
5541 error = urtwn_tx_raw(sc, ni, m, bf, params);
5542 }
5543 if (error != 0) {
5544 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, bf, next);
5545 goto end;
5546 }
5547
5548 sc->sc_txtimer = 5;
5549 callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc);
5550
5551end:
5552 if (error != 0)
5553 m_freem(m);
5554
5555 URTWN_UNLOCK(sc);
5556
5557 return (error);
5558}
5559
5560static void
5561urtwn_ms_delay(struct urtwn_softc *sc)
5562{
5563 usb_pause_mtx(&sc->sc_mtx, hz / 1000);
5564}
5565
5566static device_method_t urtwn_methods[] = {
5567 /* Device interface */
5568 DEVMETHOD(device_probe, urtwn_match),
5569 DEVMETHOD(device_attach, urtwn_attach),
5570 DEVMETHOD(device_detach, urtwn_detach),
5571
5572 DEVMETHOD_END
5573};
5574
5575static driver_t urtwn_driver = {
5576 "urtwn",
5577 urtwn_methods,
5578 sizeof(struct urtwn_softc)
5579};
5580
5581static devclass_t urtwn_devclass;
5582
5583DRIVER_MODULE(urtwn, uhub, urtwn_driver, urtwn_devclass, NULL, NULL);
5584MODULE_DEPEND(urtwn, usb, 1, 1, 1);
5585MODULE_DEPEND(urtwn, wlan, 1, 1, 1);
5586#ifndef URTWN_WITHOUT_UCODE
5587MODULE_DEPEND(urtwn, firmware, 1, 1, 1);
5588#endif
5589MODULE_VERSION(urtwn, 1);
5590USB_PNP_HOST_INFO(urtwn_devs);
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