1/*-
2 * Copyright (c) 2003 Marcel Moolenaar
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 */
26
27#include <sys/cdefs.h>
28__FBSDID("$FreeBSD: head/sys/dev/uart/uart_dev_sab82532.c 166100 2007-01-18 22:01:19Z marius $");
29
30#include <sys/param.h>
31#include <sys/systm.h>
32#include <sys/bus.h>
33#include <sys/conf.h>
34#include <machine/bus.h>
35
36#include <dev/uart/uart.h>
37#include <dev/uart/uart_cpu.h>
38#include <dev/uart/uart_bus.h>
39
40#include <dev/ic/sab82532.h>
41
42#include "uart_if.h"
43
44#define DEFAULT_RCLK 29491200
45
46/*
47 * NOTE: To allow us to read the baudrate divisor from the chip, we
48 * copy the value written to the write-only BGR register to an unused
49 * read-write register. We use TCR for that.
50 */
51
52static int
53sab82532_delay(struct uart_bas *bas)
54{
55 int divisor, m, n;
56 uint8_t bgr, ccr2;
57
58 bgr = uart_getreg(bas, SAB_TCR);
59 ccr2 = uart_getreg(bas, SAB_CCR2);
60 n = (bgr & 0x3f) + 1;
61 m = (bgr >> 6) | ((ccr2 >> 4) & 0xC);
62 divisor = n * (1<<m);
63
64 /* 1/10th the time to transmit 1 character (estimate). */
65 return (16000000 * divisor / bas->rclk);
66}
67
68static int
69sab82532_divisor(int rclk, int baudrate)
70{
71 int act_baud, act_div, divisor;
72 int error, m, n;
73
74 if (baudrate == 0)
75 return (0);
76
77 divisor = (rclk / (baudrate << 3) + 1) >> 1;
78 if (divisor < 2 || divisor >= 1048576)
79 return (0);
80
81 /* Find the best (N+1,M) pair. */
82 for (m = 1; m < 15; m++) {
83 n = divisor / (1<<m);
84 if (n < 1 || n > 63)
85 continue;
86 act_div = n * (1<<m);
87 act_baud = rclk / (act_div << 4);
88
89 /* 10 times error in percent: */
90 error = ((act_baud - baudrate) * 2000 / baudrate + 1) >> 1;
91
92 /* 3.0% maximum error tolerance: */
93 if (error < -30 || error > 30)
94 continue;
95
96 /* Got it. */
97 return ((n - 1) | (m << 6));
98 }
99
100 return (0);
101}
102
103static void
104sab82532_flush(struct uart_bas *bas, int what)
105{
106
107 if (what & UART_FLUSH_TRANSMITTER) {
108 while (uart_getreg(bas, SAB_STAR) & SAB_STAR_CEC)
109 ;
110 uart_setreg(bas, SAB_CMDR, SAB_CMDR_XRES);
111 uart_barrier(bas);
112 }
113 if (what & UART_FLUSH_RECEIVER) {
114 while (uart_getreg(bas, SAB_STAR) & SAB_STAR_CEC)
115 ;
116 uart_setreg(bas, SAB_CMDR, SAB_CMDR_RRES);
117 uart_barrier(bas);
118 }
119}
120
121static int
122sab82532_param(struct uart_bas *bas, int baudrate, int databits, int stopbits,
123 int parity)
124{
125 int divisor;
126 uint8_t ccr2, dafo;
127
128 if (databits >= 8)
129 dafo = SAB_DAFO_CHL_CS8;
130 else if (databits == 7)
131 dafo = SAB_DAFO_CHL_CS7;
132 else if (databits == 6)
133 dafo = SAB_DAFO_CHL_CS6;
134 else
135 dafo = SAB_DAFO_CHL_CS5;
136 if (stopbits > 1)
137 dafo |= SAB_DAFO_STOP;
138 switch (parity) {
139 case UART_PARITY_EVEN: dafo |= SAB_DAFO_PAR_EVEN; break;
140 case UART_PARITY_MARK: dafo |= SAB_DAFO_PAR_MARK; break;
141 case UART_PARITY_NONE: dafo |= SAB_DAFO_PAR_NONE; break;
142 case UART_PARITY_ODD: dafo |= SAB_DAFO_PAR_ODD; break;
143 case UART_PARITY_SPACE: dafo |= SAB_DAFO_PAR_SPACE; break;
144 default: return (EINVAL);
145 }
146
147 /* Set baudrate. */
148 if (baudrate > 0) {
149 divisor = sab82532_divisor(bas->rclk, baudrate);
150 if (divisor == 0)
151 return (EINVAL);
152 uart_setreg(bas, SAB_BGR, divisor & 0xff);
153 uart_barrier(bas);
154 /* Allow reading the (n-1,m) tuple from the chip. */
155 uart_setreg(bas, SAB_TCR, divisor & 0xff);
156 uart_barrier(bas);
157 ccr2 = uart_getreg(bas, SAB_CCR2);
158 ccr2 &= ~(SAB_CCR2_BR9 | SAB_CCR2_BR8);
159 ccr2 |= (divisor >> 2) & (SAB_CCR2_BR9 | SAB_CCR2_BR8);
160 uart_setreg(bas, SAB_CCR2, ccr2);
161 uart_barrier(bas);
162 }
163
164 uart_setreg(bas, SAB_DAFO, dafo);
165 uart_barrier(bas);
166 return (0);
167}
168
169/*
170 * Low-level UART interface.
171 */
172static int sab82532_probe(struct uart_bas *bas);
173static void sab82532_init(struct uart_bas *bas, int, int, int, int);
174static void sab82532_term(struct uart_bas *bas);
175static void sab82532_putc(struct uart_bas *bas, int);
176static int sab82532_rxready(struct uart_bas *bas);
177static int sab82532_getc(struct uart_bas *bas, struct mtx *);
178
179struct uart_ops uart_sab82532_ops = {
180 .probe = sab82532_probe,
181 .init = sab82532_init,
182 .term = sab82532_term,
183 .putc = sab82532_putc,
184 .rxready = sab82532_rxready,
185 .getc = sab82532_getc,
186};
187
188static int
189sab82532_probe(struct uart_bas *bas)
190{
191
192 return (0);
193}
194
195static void
196sab82532_init(struct uart_bas *bas, int baudrate, int databits, int stopbits,
197 int parity)
198{
199 uint8_t ccr0, pvr;
200
201 if (bas->rclk == 0)
202 bas->rclk = DEFAULT_RCLK;
203
204 /*
205 * Set all pins, except the DTR pins (pin 1 and 2) to be inputs.
206 * Pin 4 is magical, meaning that I don't know what it does, but
207 * it too has to be set to output.
208 */
209 uart_setreg(bas, SAB_PCR,
210 ~(SAB_PVR_DTR_A|SAB_PVR_DTR_B|SAB_PVR_MAGIC));
211 uart_barrier(bas);
212 /* Disable port interrupts. */
213 uart_setreg(bas, SAB_PIM, 0xff);
214 uart_barrier(bas);
215 /* Interrupts are active low. */
216 uart_setreg(bas, SAB_IPC, SAB_IPC_ICPL);
217 uart_barrier(bas);
218 /* Set DTR. */
219 pvr = uart_getreg(bas, SAB_PVR);
220 switch (bas->chan) {
221 case 1:
222 pvr &= ~SAB_PVR_DTR_A;
223 break;
224 case 2:
225 pvr &= ~SAB_PVR_DTR_B;
226 break;
227 }
228 uart_setreg(bas, SAB_PVR, pvr | SAB_PVR_MAGIC);
229 uart_barrier(bas);
230
231 /* power down */
232 uart_setreg(bas, SAB_CCR0, 0);
233 uart_barrier(bas);
234
235 /* set basic configuration */
236 ccr0 = SAB_CCR0_MCE|SAB_CCR0_SC_NRZ|SAB_CCR0_SM_ASYNC;
237 uart_setreg(bas, SAB_CCR0, ccr0);
238 uart_barrier(bas);
239 uart_setreg(bas, SAB_CCR1, SAB_CCR1_ODS|SAB_CCR1_BCR|SAB_CCR1_CM_7);
240 uart_barrier(bas);
241 uart_setreg(bas, SAB_CCR2, SAB_CCR2_BDF|SAB_CCR2_SSEL|SAB_CCR2_TOE);
242 uart_barrier(bas);
243 uart_setreg(bas, SAB_CCR3, 0);
244 uart_barrier(bas);
245 uart_setreg(bas, SAB_CCR4, SAB_CCR4_MCK4|SAB_CCR4_EBRG|SAB_CCR4_ICD);
246 uart_barrier(bas);
247 uart_setreg(bas, SAB_MODE, SAB_MODE_FCTS|SAB_MODE_RTS|SAB_MODE_RAC);
248 uart_barrier(bas);
249 uart_setreg(bas, SAB_RFC, SAB_RFC_DPS|SAB_RFC_RFDF|
250 SAB_RFC_RFTH_32CHAR);
251 uart_barrier(bas);
252
253 sab82532_param(bas, baudrate, databits, stopbits, parity);
254
255 /* Clear interrupts. */
256 uart_setreg(bas, SAB_IMR0, (unsigned char)~SAB_IMR0_TCD);
257 uart_setreg(bas, SAB_IMR1, 0xff);
258 uart_barrier(bas);
259 uart_getreg(bas, SAB_ISR0);
260 uart_getreg(bas, SAB_ISR1);
261 uart_barrier(bas);
262
263 sab82532_flush(bas, UART_FLUSH_TRANSMITTER|UART_FLUSH_RECEIVER);
264
265 /* Power up. */
266 uart_setreg(bas, SAB_CCR0, ccr0|SAB_CCR0_PU);
267 uart_barrier(bas);
268}
269
270static void
271sab82532_term(struct uart_bas *bas)
272{
273 uint8_t pvr;
274
275 pvr = uart_getreg(bas, SAB_PVR);
276 switch (bas->chan) {
277 case 1:
278 pvr |= SAB_PVR_DTR_A;
279 break;
280 case 2:
281 pvr |= SAB_PVR_DTR_B;
282 break;
283 }
284 uart_setreg(bas, SAB_PVR, pvr);
285 uart_barrier(bas);
286}
287
288static void
289sab82532_putc(struct uart_bas *bas, int c)
290{
291 int delay, limit;
292
293 /* 1/10th the time to transmit 1 character (estimate). */
294 delay = sab82532_delay(bas);
295
296 limit = 20;
297 while ((uart_getreg(bas, SAB_STAR) & SAB_STAR_TEC) && --limit)
298 DELAY(delay);
299 uart_setreg(bas, SAB_TIC, c);
300 limit = 20;
301 while ((uart_getreg(bas, SAB_STAR) & SAB_STAR_TEC) && --limit)
302 DELAY(delay);
303}
304
305static int
306sab82532_rxready(struct uart_bas *bas)
307{
308
309 return ((uart_getreg(bas, SAB_STAR) & SAB_STAR_RFNE) != 0 ? 1 : 0);
310}
311
312static int
313sab82532_getc(struct uart_bas *bas, struct mtx *hwmtx)
314{
315 int c, delay;
316
317 uart_lock(hwmtx);
318
319 /* 1/10th the time to transmit 1 character (estimate). */
320 delay = sab82532_delay(bas);
321
322 while (!(uart_getreg(bas, SAB_STAR) & SAB_STAR_RFNE)) {
323 uart_unlock(hwmtx);
324 DELAY(delay);
325 uart_lock(hwmtx);
326 }
327
328 while (uart_getreg(bas, SAB_STAR) & SAB_STAR_CEC)
329 ;
330 uart_setreg(bas, SAB_CMDR, SAB_CMDR_RFRD);
331 uart_barrier(bas);
332
333 while (!(uart_getreg(bas, SAB_ISR0) & SAB_ISR0_TCD))
334 DELAY(delay);
335
336 c = uart_getreg(bas, SAB_RFIFO);
337 uart_barrier(bas);
338
339 /* Blow away everything left in the FIFO... */
340 while (uart_getreg(bas, SAB_STAR) & SAB_STAR_CEC)
341 ;
342 uart_setreg(bas, SAB_CMDR, SAB_CMDR_RMC);
343 uart_barrier(bas);
344
345 uart_unlock(hwmtx);
346
347 return (c);
348}
349
350/*
351 * High-level UART interface.
352 */
353struct sab82532_softc {
354 struct uart_softc base;
355};
356
357static int sab82532_bus_attach(struct uart_softc *);
358static int sab82532_bus_detach(struct uart_softc *);
359static int sab82532_bus_flush(struct uart_softc *, int);
360static int sab82532_bus_getsig(struct uart_softc *);
361static int sab82532_bus_ioctl(struct uart_softc *, int, intptr_t);
362static int sab82532_bus_ipend(struct uart_softc *);
363static int sab82532_bus_param(struct uart_softc *, int, int, int, int);
364static int sab82532_bus_probe(struct uart_softc *);
365static int sab82532_bus_receive(struct uart_softc *);
366static int sab82532_bus_setsig(struct uart_softc *, int);
367static int sab82532_bus_transmit(struct uart_softc *);
368
369static kobj_method_t sab82532_methods[] = {
370 KOBJMETHOD(uart_attach, sab82532_bus_attach),
371 KOBJMETHOD(uart_detach, sab82532_bus_detach),
372 KOBJMETHOD(uart_flush, sab82532_bus_flush),
373 KOBJMETHOD(uart_getsig, sab82532_bus_getsig),
374 KOBJMETHOD(uart_ioctl, sab82532_bus_ioctl),
375 KOBJMETHOD(uart_ipend, sab82532_bus_ipend),
376 KOBJMETHOD(uart_param, sab82532_bus_param),
377 KOBJMETHOD(uart_probe, sab82532_bus_probe),
378 KOBJMETHOD(uart_receive, sab82532_bus_receive),
379 KOBJMETHOD(uart_setsig, sab82532_bus_setsig),
380 KOBJMETHOD(uart_transmit, sab82532_bus_transmit),
381 { 0, 0 }
382};
383
384struct uart_class uart_sab82532_class = {
385 "sab82532 class",
386 sab82532_methods,
387 sizeof(struct sab82532_softc),
388 .uc_range = 64,
389 .uc_rclk = DEFAULT_RCLK
390};
391
392#define SIGCHG(c, i, s, d) \
393 if (c) { \
394 i |= (i & s) ? s : s | d; \
395 } else { \
396 i = (i & s) ? (i & ~s) | d : i; \
397 }
398
399static int
400sab82532_bus_attach(struct uart_softc *sc)
401{
402 struct uart_bas *bas;
403 uint8_t imr0, imr1;
404
405 bas = &sc->sc_bas;
406 if (sc->sc_sysdev == NULL)
407 sab82532_init(bas, 9600, 8, 1, UART_PARITY_NONE);
408
409 sc->sc_rxfifosz = 32;
410 sc->sc_txfifosz = 32;
411
412 imr0 = SAB_IMR0_TCD|SAB_IMR0_TIME|SAB_IMR0_CDSC|SAB_IMR0_RFO|
413 SAB_IMR0_RPF;
414 uart_setreg(bas, SAB_IMR0, 0xff & ~imr0);
415 imr1 = SAB_IMR1_BRKT|SAB_IMR1_ALLS|SAB_IMR1_CSC;
416 uart_setreg(bas, SAB_IMR1, 0xff & ~imr1);
417 uart_barrier(bas);
418
419 if (sc->sc_sysdev == NULL)
420 sab82532_bus_setsig(sc, SER_DDTR|SER_DRTS);
421 (void)sab82532_bus_getsig(sc);
422 return (0);
423}
424
425static int
426sab82532_bus_detach(struct uart_softc *sc)
427{
428 struct uart_bas *bas;
429
430 bas = &sc->sc_bas;
431 uart_setreg(bas, SAB_IMR0, 0xff);
432 uart_setreg(bas, SAB_IMR1, 0xff);
433 uart_barrier(bas);
434 uart_getreg(bas, SAB_ISR0);
435 uart_getreg(bas, SAB_ISR1);
436 uart_barrier(bas);
437 uart_setreg(bas, SAB_CCR0, 0);
438 uart_barrier(bas);
439 return (0);
440}
441
442static int
443sab82532_bus_flush(struct uart_softc *sc, int what)
444{
445
446 uart_lock(sc->sc_hwmtx);
447 sab82532_flush(&sc->sc_bas, what);
448 uart_unlock(sc->sc_hwmtx);
449 return (0);
450}
451
452static int
453sab82532_bus_getsig(struct uart_softc *sc)
454{
455 struct uart_bas *bas;
456 uint32_t new, old, sig;
457 uint8_t pvr, star, vstr;
458
459 bas = &sc->sc_bas;
460 do {
461 old = sc->sc_hwsig;
462 sig = old;
463 uart_lock(sc->sc_hwmtx);
464 star = uart_getreg(bas, SAB_STAR);
465 SIGCHG(star & SAB_STAR_CTS, sig, SER_CTS, SER_DCTS);
466 vstr = uart_getreg(bas, SAB_VSTR);
467 SIGCHG(vstr & SAB_VSTR_CD, sig, SER_DCD, SER_DDCD);
468 pvr = ~uart_getreg(bas, SAB_PVR);
469 switch (bas->chan) {
470 case 1:
471 pvr &= SAB_PVR_DSR_A;
472 break;
473 case 2:
474 pvr &= SAB_PVR_DSR_B;
475 break;
476 }
477 SIGCHG(pvr, sig, SER_DSR, SER_DDSR);
478 uart_unlock(sc->sc_hwmtx);
479 new = sig & ~SER_MASK_DELTA;
480 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
481 return (sig);
482}
483
484static int
485sab82532_bus_ioctl(struct uart_softc *sc, int request, intptr_t data)
486{
487 struct uart_bas *bas;
488 uint8_t dafo, mode;
489 int error;
490
491 bas = &sc->sc_bas;
492 error = 0;
493 uart_lock(sc->sc_hwmtx);
494 switch (request) {
495 case UART_IOCTL_BREAK:
496 dafo = uart_getreg(bas, SAB_DAFO);
497 if (data)
498 dafo |= SAB_DAFO_XBRK;
499 else
500 dafo &= ~SAB_DAFO_XBRK;
501 uart_setreg(bas, SAB_DAFO, dafo);
502 uart_barrier(bas);
503 break;
504 case UART_IOCTL_IFLOW:
505 mode = uart_getreg(bas, SAB_MODE);
506 if (data) {
507 mode &= ~SAB_MODE_RTS;
508 mode |= SAB_MODE_FRTS;
509 } else {
510 mode |= SAB_MODE_RTS;
511 mode &= ~SAB_MODE_FRTS;
512 }
513 uart_setreg(bas, SAB_MODE, mode);
514 uart_barrier(bas);
515 break;
516 case UART_IOCTL_OFLOW:
517 mode = uart_getreg(bas, SAB_MODE);
518 if (data)
519 mode &= ~SAB_MODE_FCTS;
520 else
521 mode |= SAB_MODE_FCTS;
522 uart_setreg(bas, SAB_MODE, mode);
523 uart_barrier(bas);
524 break;
525 default:
526 error = EINVAL;
527 break;
528 }
529 uart_unlock(sc->sc_hwmtx);
530 return (error);
531}
532
533static int
534sab82532_bus_ipend(struct uart_softc *sc)
535{
536 struct uart_bas *bas;
537 int ipend;
538 uint8_t isr0, isr1;
539
540 bas = &sc->sc_bas;
541 uart_lock(sc->sc_hwmtx);
542 isr0 = uart_getreg(bas, SAB_ISR0);
543 isr1 = uart_getreg(bas, SAB_ISR1);
544 uart_barrier(bas);
545 if (isr0 & SAB_ISR0_TIME) {
546 while (uart_getreg(bas, SAB_STAR) & SAB_STAR_CEC)
547 ;
548 uart_setreg(bas, SAB_CMDR, SAB_CMDR_RFRD);
549 uart_barrier(bas);
550 }
551 uart_unlock(sc->sc_hwmtx);
552
553 ipend = 0;
554 if (isr1 & SAB_ISR1_BRKT)
555 ipend |= SER_INT_BREAK;
556 if (isr0 & SAB_ISR0_RFO)
557 ipend |= SER_INT_OVERRUN;
558 if (isr0 & (SAB_ISR0_TCD|SAB_ISR0_RPF))
559 ipend |= SER_INT_RXREADY;
560 if ((isr0 & SAB_ISR0_CDSC) || (isr1 & SAB_ISR1_CSC))
561 ipend |= SER_INT_SIGCHG;
562 if (isr1 & SAB_ISR1_ALLS)
563 ipend |= SER_INT_TXIDLE;
564
565 return (ipend);
566}
567
568static int
569sab82532_bus_param(struct uart_softc *sc, int baudrate, int databits,
570 int stopbits, int parity)
571{
572 struct uart_bas *bas;
573 int error;
574
575 bas = &sc->sc_bas;
576 uart_lock(sc->sc_hwmtx);
577 error = sab82532_param(bas, baudrate, databits, stopbits, parity);
578 uart_unlock(sc->sc_hwmtx);
579 return (error);
580}
581
582static int
583sab82532_bus_probe(struct uart_softc *sc)
584{
585 char buf[80];
586 const char *vstr;
587 int error;
588 char ch;
589
590 error = sab82532_probe(&sc->sc_bas);
591 if (error)
592 return (error);
593
594 ch = sc->sc_bas.chan - 1 + 'A';
595
596 switch (uart_getreg(&sc->sc_bas, SAB_VSTR) & SAB_VSTR_VMASK) {
597 case SAB_VSTR_V_1:
598 vstr = "v1";
599 break;
600 case SAB_VSTR_V_2:
601 vstr = "v2";
602 break;
603 case SAB_VSTR_V_32:
604 vstr = "v3.2";
605 sc->sc_hwiflow = 0; /* CTS doesn't work with RFC:RFDF. */
606 sc->sc_hwoflow = 1;
607 break;
608 default:
609 vstr = "v4?";
610 break;
611 }
612
613 snprintf(buf, sizeof(buf), "SAB 82532 %s, channel %c", vstr, ch);
614 device_set_desc_copy(sc->sc_dev, buf);
615 return (0);
616}
617
618static int
619sab82532_bus_receive(struct uart_softc *sc)
620{
621 struct uart_bas *bas;
622 int i, rbcl, xc;
623 uint8_t s;
624
625 bas = &sc->sc_bas;
626 uart_lock(sc->sc_hwmtx);
627 if (uart_getreg(bas, SAB_STAR) & SAB_STAR_RFNE) {
628 rbcl = uart_getreg(bas, SAB_RBCL) & 31;
629 if (rbcl == 0)
630 rbcl = 32;
631 for (i = 0; i < rbcl; i += 2) {
632 if (uart_rx_full(sc)) {
633 sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN;
634 break;
635 }
636 xc = uart_getreg(bas, SAB_RFIFO);
637 s = uart_getreg(bas, SAB_RFIFO + 1);
638 if (s & SAB_RSTAT_FE)
639 xc |= UART_STAT_FRAMERR;
640 if (s & SAB_RSTAT_PE)
641 xc |= UART_STAT_PARERR;
642 uart_rx_put(sc, xc);
643 }
644 }
645
646 while (uart_getreg(bas, SAB_STAR) & SAB_STAR_CEC)
647 ;
648 uart_setreg(bas, SAB_CMDR, SAB_CMDR_RMC);
649 uart_barrier(bas);
650 uart_unlock(sc->sc_hwmtx);
651 return (0);
652}
653
654static int
655sab82532_bus_setsig(struct uart_softc *sc, int sig)
656{
657 struct uart_bas *bas;
658 uint32_t new, old;
659 uint8_t mode, pvr;
660
661 bas = &sc->sc_bas;
662 do {
663 old = sc->sc_hwsig;
664 new = old;
665 if (sig & SER_DDTR) {
666 SIGCHG(sig & SER_DTR, new, SER_DTR,
667 SER_DDTR);
668 }
669 if (sig & SER_DRTS) {
670 SIGCHG(sig & SER_RTS, new, SER_RTS,
671 SER_DRTS);
672 }
673 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
674
675 uart_lock(sc->sc_hwmtx);
676 /* Set DTR pin. */
677 pvr = uart_getreg(bas, SAB_PVR);
678 switch (bas->chan) {
679 case 1:
680 if (new & SER_DTR)
681 pvr &= ~SAB_PVR_DTR_A;
682 else
683 pvr |= SAB_PVR_DTR_A;
684 break;
685 case 2:
686 if (new & SER_DTR)
687 pvr &= ~SAB_PVR_DTR_B;
688 else
689 pvr |= SAB_PVR_DTR_B;
690 break;
691 }
692 uart_setreg(bas, SAB_PVR, pvr);
693
694 /* Set RTS pin. */
695 mode = uart_getreg(bas, SAB_MODE);
696 if (new & SER_RTS)
697 mode &= ~SAB_MODE_FRTS;
698 else
699 mode |= SAB_MODE_FRTS;
700 uart_setreg(bas, SAB_MODE, mode);
701 uart_barrier(bas);
702 uart_unlock(sc->sc_hwmtx);
703 return (0);
704}
705
706static int
707sab82532_bus_transmit(struct uart_softc *sc)
708{
709 struct uart_bas *bas;
710 int i;
711
712 bas = &sc->sc_bas;
713 uart_lock(sc->sc_hwmtx);
714 while (!(uart_getreg(bas, SAB_STAR) & SAB_STAR_XFW))
715 ;
716 for (i = 0; i < sc->sc_txdatasz; i++)
717 uart_setreg(bas, SAB_XFIFO + i, sc->sc_txbuf[i]);
718 uart_barrier(bas);
719 while (uart_getreg(bas, SAB_STAR) & SAB_STAR_CEC)
720 ;
721 uart_setreg(bas, SAB_CMDR, SAB_CMDR_XF);
722 sc->sc_txbusy = 1;
723 uart_unlock(sc->sc_hwmtx);
724 return (0);
725}
2 * Copyright (c) 2003 Marcel Moolenaar
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 */
26
27#include <sys/cdefs.h>
28__FBSDID("$FreeBSD: head/sys/dev/uart/uart_dev_sab82532.c 166100 2007-01-18 22:01:19Z marius $");
29
30#include <sys/param.h>
31#include <sys/systm.h>
32#include <sys/bus.h>
33#include <sys/conf.h>
34#include <machine/bus.h>
35
36#include <dev/uart/uart.h>
37#include <dev/uart/uart_cpu.h>
38#include <dev/uart/uart_bus.h>
39
40#include <dev/ic/sab82532.h>
41
42#include "uart_if.h"
43
44#define DEFAULT_RCLK 29491200
45
46/*
47 * NOTE: To allow us to read the baudrate divisor from the chip, we
48 * copy the value written to the write-only BGR register to an unused
49 * read-write register. We use TCR for that.
50 */
51
52static int
53sab82532_delay(struct uart_bas *bas)
54{
55 int divisor, m, n;
56 uint8_t bgr, ccr2;
57
58 bgr = uart_getreg(bas, SAB_TCR);
59 ccr2 = uart_getreg(bas, SAB_CCR2);
60 n = (bgr & 0x3f) + 1;
61 m = (bgr >> 6) | ((ccr2 >> 4) & 0xC);
62 divisor = n * (1<<m);
63
64 /* 1/10th the time to transmit 1 character (estimate). */
65 return (16000000 * divisor / bas->rclk);
66}
67
68static int
69sab82532_divisor(int rclk, int baudrate)
70{
71 int act_baud, act_div, divisor;
72 int error, m, n;
73
74 if (baudrate == 0)
75 return (0);
76
77 divisor = (rclk / (baudrate << 3) + 1) >> 1;
78 if (divisor < 2 || divisor >= 1048576)
79 return (0);
80
81 /* Find the best (N+1,M) pair. */
82 for (m = 1; m < 15; m++) {
83 n = divisor / (1<<m);
84 if (n < 1 || n > 63)
85 continue;
86 act_div = n * (1<<m);
87 act_baud = rclk / (act_div << 4);
88
89 /* 10 times error in percent: */
90 error = ((act_baud - baudrate) * 2000 / baudrate + 1) >> 1;
91
92 /* 3.0% maximum error tolerance: */
93 if (error < -30 || error > 30)
94 continue;
95
96 /* Got it. */
97 return ((n - 1) | (m << 6));
98 }
99
100 return (0);
101}
102
103static void
104sab82532_flush(struct uart_bas *bas, int what)
105{
106
107 if (what & UART_FLUSH_TRANSMITTER) {
108 while (uart_getreg(bas, SAB_STAR) & SAB_STAR_CEC)
109 ;
110 uart_setreg(bas, SAB_CMDR, SAB_CMDR_XRES);
111 uart_barrier(bas);
112 }
113 if (what & UART_FLUSH_RECEIVER) {
114 while (uart_getreg(bas, SAB_STAR) & SAB_STAR_CEC)
115 ;
116 uart_setreg(bas, SAB_CMDR, SAB_CMDR_RRES);
117 uart_barrier(bas);
118 }
119}
120
121static int
122sab82532_param(struct uart_bas *bas, int baudrate, int databits, int stopbits,
123 int parity)
124{
125 int divisor;
126 uint8_t ccr2, dafo;
127
128 if (databits >= 8)
129 dafo = SAB_DAFO_CHL_CS8;
130 else if (databits == 7)
131 dafo = SAB_DAFO_CHL_CS7;
132 else if (databits == 6)
133 dafo = SAB_DAFO_CHL_CS6;
134 else
135 dafo = SAB_DAFO_CHL_CS5;
136 if (stopbits > 1)
137 dafo |= SAB_DAFO_STOP;
138 switch (parity) {
139 case UART_PARITY_EVEN: dafo |= SAB_DAFO_PAR_EVEN; break;
140 case UART_PARITY_MARK: dafo |= SAB_DAFO_PAR_MARK; break;
141 case UART_PARITY_NONE: dafo |= SAB_DAFO_PAR_NONE; break;
142 case UART_PARITY_ODD: dafo |= SAB_DAFO_PAR_ODD; break;
143 case UART_PARITY_SPACE: dafo |= SAB_DAFO_PAR_SPACE; break;
144 default: return (EINVAL);
145 }
146
147 /* Set baudrate. */
148 if (baudrate > 0) {
149 divisor = sab82532_divisor(bas->rclk, baudrate);
150 if (divisor == 0)
151 return (EINVAL);
152 uart_setreg(bas, SAB_BGR, divisor & 0xff);
153 uart_barrier(bas);
154 /* Allow reading the (n-1,m) tuple from the chip. */
155 uart_setreg(bas, SAB_TCR, divisor & 0xff);
156 uart_barrier(bas);
157 ccr2 = uart_getreg(bas, SAB_CCR2);
158 ccr2 &= ~(SAB_CCR2_BR9 | SAB_CCR2_BR8);
159 ccr2 |= (divisor >> 2) & (SAB_CCR2_BR9 | SAB_CCR2_BR8);
160 uart_setreg(bas, SAB_CCR2, ccr2);
161 uart_barrier(bas);
162 }
163
164 uart_setreg(bas, SAB_DAFO, dafo);
165 uart_barrier(bas);
166 return (0);
167}
168
169/*
170 * Low-level UART interface.
171 */
172static int sab82532_probe(struct uart_bas *bas);
173static void sab82532_init(struct uart_bas *bas, int, int, int, int);
174static void sab82532_term(struct uart_bas *bas);
175static void sab82532_putc(struct uart_bas *bas, int);
176static int sab82532_rxready(struct uart_bas *bas);
177static int sab82532_getc(struct uart_bas *bas, struct mtx *);
178
179struct uart_ops uart_sab82532_ops = {
180 .probe = sab82532_probe,
181 .init = sab82532_init,
182 .term = sab82532_term,
183 .putc = sab82532_putc,
184 .rxready = sab82532_rxready,
185 .getc = sab82532_getc,
186};
187
188static int
189sab82532_probe(struct uart_bas *bas)
190{
191
192 return (0);
193}
194
195static void
196sab82532_init(struct uart_bas *bas, int baudrate, int databits, int stopbits,
197 int parity)
198{
199 uint8_t ccr0, pvr;
200
201 if (bas->rclk == 0)
202 bas->rclk = DEFAULT_RCLK;
203
204 /*
205 * Set all pins, except the DTR pins (pin 1 and 2) to be inputs.
206 * Pin 4 is magical, meaning that I don't know what it does, but
207 * it too has to be set to output.
208 */
209 uart_setreg(bas, SAB_PCR,
210 ~(SAB_PVR_DTR_A|SAB_PVR_DTR_B|SAB_PVR_MAGIC));
211 uart_barrier(bas);
212 /* Disable port interrupts. */
213 uart_setreg(bas, SAB_PIM, 0xff);
214 uart_barrier(bas);
215 /* Interrupts are active low. */
216 uart_setreg(bas, SAB_IPC, SAB_IPC_ICPL);
217 uart_barrier(bas);
218 /* Set DTR. */
219 pvr = uart_getreg(bas, SAB_PVR);
220 switch (bas->chan) {
221 case 1:
222 pvr &= ~SAB_PVR_DTR_A;
223 break;
224 case 2:
225 pvr &= ~SAB_PVR_DTR_B;
226 break;
227 }
228 uart_setreg(bas, SAB_PVR, pvr | SAB_PVR_MAGIC);
229 uart_barrier(bas);
230
231 /* power down */
232 uart_setreg(bas, SAB_CCR0, 0);
233 uart_barrier(bas);
234
235 /* set basic configuration */
236 ccr0 = SAB_CCR0_MCE|SAB_CCR0_SC_NRZ|SAB_CCR0_SM_ASYNC;
237 uart_setreg(bas, SAB_CCR0, ccr0);
238 uart_barrier(bas);
239 uart_setreg(bas, SAB_CCR1, SAB_CCR1_ODS|SAB_CCR1_BCR|SAB_CCR1_CM_7);
240 uart_barrier(bas);
241 uart_setreg(bas, SAB_CCR2, SAB_CCR2_BDF|SAB_CCR2_SSEL|SAB_CCR2_TOE);
242 uart_barrier(bas);
243 uart_setreg(bas, SAB_CCR3, 0);
244 uart_barrier(bas);
245 uart_setreg(bas, SAB_CCR4, SAB_CCR4_MCK4|SAB_CCR4_EBRG|SAB_CCR4_ICD);
246 uart_barrier(bas);
247 uart_setreg(bas, SAB_MODE, SAB_MODE_FCTS|SAB_MODE_RTS|SAB_MODE_RAC);
248 uart_barrier(bas);
249 uart_setreg(bas, SAB_RFC, SAB_RFC_DPS|SAB_RFC_RFDF|
250 SAB_RFC_RFTH_32CHAR);
251 uart_barrier(bas);
252
253 sab82532_param(bas, baudrate, databits, stopbits, parity);
254
255 /* Clear interrupts. */
256 uart_setreg(bas, SAB_IMR0, (unsigned char)~SAB_IMR0_TCD);
257 uart_setreg(bas, SAB_IMR1, 0xff);
258 uart_barrier(bas);
259 uart_getreg(bas, SAB_ISR0);
260 uart_getreg(bas, SAB_ISR1);
261 uart_barrier(bas);
262
263 sab82532_flush(bas, UART_FLUSH_TRANSMITTER|UART_FLUSH_RECEIVER);
264
265 /* Power up. */
266 uart_setreg(bas, SAB_CCR0, ccr0|SAB_CCR0_PU);
267 uart_barrier(bas);
268}
269
270static void
271sab82532_term(struct uart_bas *bas)
272{
273 uint8_t pvr;
274
275 pvr = uart_getreg(bas, SAB_PVR);
276 switch (bas->chan) {
277 case 1:
278 pvr |= SAB_PVR_DTR_A;
279 break;
280 case 2:
281 pvr |= SAB_PVR_DTR_B;
282 break;
283 }
284 uart_setreg(bas, SAB_PVR, pvr);
285 uart_barrier(bas);
286}
287
288static void
289sab82532_putc(struct uart_bas *bas, int c)
290{
291 int delay, limit;
292
293 /* 1/10th the time to transmit 1 character (estimate). */
294 delay = sab82532_delay(bas);
295
296 limit = 20;
297 while ((uart_getreg(bas, SAB_STAR) & SAB_STAR_TEC) && --limit)
298 DELAY(delay);
299 uart_setreg(bas, SAB_TIC, c);
300 limit = 20;
301 while ((uart_getreg(bas, SAB_STAR) & SAB_STAR_TEC) && --limit)
302 DELAY(delay);
303}
304
305static int
306sab82532_rxready(struct uart_bas *bas)
307{
308
309 return ((uart_getreg(bas, SAB_STAR) & SAB_STAR_RFNE) != 0 ? 1 : 0);
310}
311
312static int
313sab82532_getc(struct uart_bas *bas, struct mtx *hwmtx)
314{
315 int c, delay;
316
317 uart_lock(hwmtx);
318
319 /* 1/10th the time to transmit 1 character (estimate). */
320 delay = sab82532_delay(bas);
321
322 while (!(uart_getreg(bas, SAB_STAR) & SAB_STAR_RFNE)) {
323 uart_unlock(hwmtx);
324 DELAY(delay);
325 uart_lock(hwmtx);
326 }
327
328 while (uart_getreg(bas, SAB_STAR) & SAB_STAR_CEC)
329 ;
330 uart_setreg(bas, SAB_CMDR, SAB_CMDR_RFRD);
331 uart_barrier(bas);
332
333 while (!(uart_getreg(bas, SAB_ISR0) & SAB_ISR0_TCD))
334 DELAY(delay);
335
336 c = uart_getreg(bas, SAB_RFIFO);
337 uart_barrier(bas);
338
339 /* Blow away everything left in the FIFO... */
340 while (uart_getreg(bas, SAB_STAR) & SAB_STAR_CEC)
341 ;
342 uart_setreg(bas, SAB_CMDR, SAB_CMDR_RMC);
343 uart_barrier(bas);
344
345 uart_unlock(hwmtx);
346
347 return (c);
348}
349
350/*
351 * High-level UART interface.
352 */
353struct sab82532_softc {
354 struct uart_softc base;
355};
356
357static int sab82532_bus_attach(struct uart_softc *);
358static int sab82532_bus_detach(struct uart_softc *);
359static int sab82532_bus_flush(struct uart_softc *, int);
360static int sab82532_bus_getsig(struct uart_softc *);
361static int sab82532_bus_ioctl(struct uart_softc *, int, intptr_t);
362static int sab82532_bus_ipend(struct uart_softc *);
363static int sab82532_bus_param(struct uart_softc *, int, int, int, int);
364static int sab82532_bus_probe(struct uart_softc *);
365static int sab82532_bus_receive(struct uart_softc *);
366static int sab82532_bus_setsig(struct uart_softc *, int);
367static int sab82532_bus_transmit(struct uart_softc *);
368
369static kobj_method_t sab82532_methods[] = {
370 KOBJMETHOD(uart_attach, sab82532_bus_attach),
371 KOBJMETHOD(uart_detach, sab82532_bus_detach),
372 KOBJMETHOD(uart_flush, sab82532_bus_flush),
373 KOBJMETHOD(uart_getsig, sab82532_bus_getsig),
374 KOBJMETHOD(uart_ioctl, sab82532_bus_ioctl),
375 KOBJMETHOD(uart_ipend, sab82532_bus_ipend),
376 KOBJMETHOD(uart_param, sab82532_bus_param),
377 KOBJMETHOD(uart_probe, sab82532_bus_probe),
378 KOBJMETHOD(uart_receive, sab82532_bus_receive),
379 KOBJMETHOD(uart_setsig, sab82532_bus_setsig),
380 KOBJMETHOD(uart_transmit, sab82532_bus_transmit),
381 { 0, 0 }
382};
383
384struct uart_class uart_sab82532_class = {
385 "sab82532 class",
386 sab82532_methods,
387 sizeof(struct sab82532_softc),
388 .uc_range = 64,
389 .uc_rclk = DEFAULT_RCLK
390};
391
392#define SIGCHG(c, i, s, d) \
393 if (c) { \
394 i |= (i & s) ? s : s | d; \
395 } else { \
396 i = (i & s) ? (i & ~s) | d : i; \
397 }
398
399static int
400sab82532_bus_attach(struct uart_softc *sc)
401{
402 struct uart_bas *bas;
403 uint8_t imr0, imr1;
404
405 bas = &sc->sc_bas;
406 if (sc->sc_sysdev == NULL)
407 sab82532_init(bas, 9600, 8, 1, UART_PARITY_NONE);
408
409 sc->sc_rxfifosz = 32;
410 sc->sc_txfifosz = 32;
411
412 imr0 = SAB_IMR0_TCD|SAB_IMR0_TIME|SAB_IMR0_CDSC|SAB_IMR0_RFO|
413 SAB_IMR0_RPF;
414 uart_setreg(bas, SAB_IMR0, 0xff & ~imr0);
415 imr1 = SAB_IMR1_BRKT|SAB_IMR1_ALLS|SAB_IMR1_CSC;
416 uart_setreg(bas, SAB_IMR1, 0xff & ~imr1);
417 uart_barrier(bas);
418
419 if (sc->sc_sysdev == NULL)
420 sab82532_bus_setsig(sc, SER_DDTR|SER_DRTS);
421 (void)sab82532_bus_getsig(sc);
422 return (0);
423}
424
425static int
426sab82532_bus_detach(struct uart_softc *sc)
427{
428 struct uart_bas *bas;
429
430 bas = &sc->sc_bas;
431 uart_setreg(bas, SAB_IMR0, 0xff);
432 uart_setreg(bas, SAB_IMR1, 0xff);
433 uart_barrier(bas);
434 uart_getreg(bas, SAB_ISR0);
435 uart_getreg(bas, SAB_ISR1);
436 uart_barrier(bas);
437 uart_setreg(bas, SAB_CCR0, 0);
438 uart_barrier(bas);
439 return (0);
440}
441
442static int
443sab82532_bus_flush(struct uart_softc *sc, int what)
444{
445
446 uart_lock(sc->sc_hwmtx);
447 sab82532_flush(&sc->sc_bas, what);
448 uart_unlock(sc->sc_hwmtx);
449 return (0);
450}
451
452static int
453sab82532_bus_getsig(struct uart_softc *sc)
454{
455 struct uart_bas *bas;
456 uint32_t new, old, sig;
457 uint8_t pvr, star, vstr;
458
459 bas = &sc->sc_bas;
460 do {
461 old = sc->sc_hwsig;
462 sig = old;
463 uart_lock(sc->sc_hwmtx);
464 star = uart_getreg(bas, SAB_STAR);
465 SIGCHG(star & SAB_STAR_CTS, sig, SER_CTS, SER_DCTS);
466 vstr = uart_getreg(bas, SAB_VSTR);
467 SIGCHG(vstr & SAB_VSTR_CD, sig, SER_DCD, SER_DDCD);
468 pvr = ~uart_getreg(bas, SAB_PVR);
469 switch (bas->chan) {
470 case 1:
471 pvr &= SAB_PVR_DSR_A;
472 break;
473 case 2:
474 pvr &= SAB_PVR_DSR_B;
475 break;
476 }
477 SIGCHG(pvr, sig, SER_DSR, SER_DDSR);
478 uart_unlock(sc->sc_hwmtx);
479 new = sig & ~SER_MASK_DELTA;
480 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
481 return (sig);
482}
483
484static int
485sab82532_bus_ioctl(struct uart_softc *sc, int request, intptr_t data)
486{
487 struct uart_bas *bas;
488 uint8_t dafo, mode;
489 int error;
490
491 bas = &sc->sc_bas;
492 error = 0;
493 uart_lock(sc->sc_hwmtx);
494 switch (request) {
495 case UART_IOCTL_BREAK:
496 dafo = uart_getreg(bas, SAB_DAFO);
497 if (data)
498 dafo |= SAB_DAFO_XBRK;
499 else
500 dafo &= ~SAB_DAFO_XBRK;
501 uart_setreg(bas, SAB_DAFO, dafo);
502 uart_barrier(bas);
503 break;
504 case UART_IOCTL_IFLOW:
505 mode = uart_getreg(bas, SAB_MODE);
506 if (data) {
507 mode &= ~SAB_MODE_RTS;
508 mode |= SAB_MODE_FRTS;
509 } else {
510 mode |= SAB_MODE_RTS;
511 mode &= ~SAB_MODE_FRTS;
512 }
513 uart_setreg(bas, SAB_MODE, mode);
514 uart_barrier(bas);
515 break;
516 case UART_IOCTL_OFLOW:
517 mode = uart_getreg(bas, SAB_MODE);
518 if (data)
519 mode &= ~SAB_MODE_FCTS;
520 else
521 mode |= SAB_MODE_FCTS;
522 uart_setreg(bas, SAB_MODE, mode);
523 uart_barrier(bas);
524 break;
525 default:
526 error = EINVAL;
527 break;
528 }
529 uart_unlock(sc->sc_hwmtx);
530 return (error);
531}
532
533static int
534sab82532_bus_ipend(struct uart_softc *sc)
535{
536 struct uart_bas *bas;
537 int ipend;
538 uint8_t isr0, isr1;
539
540 bas = &sc->sc_bas;
541 uart_lock(sc->sc_hwmtx);
542 isr0 = uart_getreg(bas, SAB_ISR0);
543 isr1 = uart_getreg(bas, SAB_ISR1);
544 uart_barrier(bas);
545 if (isr0 & SAB_ISR0_TIME) {
546 while (uart_getreg(bas, SAB_STAR) & SAB_STAR_CEC)
547 ;
548 uart_setreg(bas, SAB_CMDR, SAB_CMDR_RFRD);
549 uart_barrier(bas);
550 }
551 uart_unlock(sc->sc_hwmtx);
552
553 ipend = 0;
554 if (isr1 & SAB_ISR1_BRKT)
555 ipend |= SER_INT_BREAK;
556 if (isr0 & SAB_ISR0_RFO)
557 ipend |= SER_INT_OVERRUN;
558 if (isr0 & (SAB_ISR0_TCD|SAB_ISR0_RPF))
559 ipend |= SER_INT_RXREADY;
560 if ((isr0 & SAB_ISR0_CDSC) || (isr1 & SAB_ISR1_CSC))
561 ipend |= SER_INT_SIGCHG;
562 if (isr1 & SAB_ISR1_ALLS)
563 ipend |= SER_INT_TXIDLE;
564
565 return (ipend);
566}
567
568static int
569sab82532_bus_param(struct uart_softc *sc, int baudrate, int databits,
570 int stopbits, int parity)
571{
572 struct uart_bas *bas;
573 int error;
574
575 bas = &sc->sc_bas;
576 uart_lock(sc->sc_hwmtx);
577 error = sab82532_param(bas, baudrate, databits, stopbits, parity);
578 uart_unlock(sc->sc_hwmtx);
579 return (error);
580}
581
582static int
583sab82532_bus_probe(struct uart_softc *sc)
584{
585 char buf[80];
586 const char *vstr;
587 int error;
588 char ch;
589
590 error = sab82532_probe(&sc->sc_bas);
591 if (error)
592 return (error);
593
594 ch = sc->sc_bas.chan - 1 + 'A';
595
596 switch (uart_getreg(&sc->sc_bas, SAB_VSTR) & SAB_VSTR_VMASK) {
597 case SAB_VSTR_V_1:
598 vstr = "v1";
599 break;
600 case SAB_VSTR_V_2:
601 vstr = "v2";
602 break;
603 case SAB_VSTR_V_32:
604 vstr = "v3.2";
605 sc->sc_hwiflow = 0; /* CTS doesn't work with RFC:RFDF. */
606 sc->sc_hwoflow = 1;
607 break;
608 default:
609 vstr = "v4?";
610 break;
611 }
612
613 snprintf(buf, sizeof(buf), "SAB 82532 %s, channel %c", vstr, ch);
614 device_set_desc_copy(sc->sc_dev, buf);
615 return (0);
616}
617
618static int
619sab82532_bus_receive(struct uart_softc *sc)
620{
621 struct uart_bas *bas;
622 int i, rbcl, xc;
623 uint8_t s;
624
625 bas = &sc->sc_bas;
626 uart_lock(sc->sc_hwmtx);
627 if (uart_getreg(bas, SAB_STAR) & SAB_STAR_RFNE) {
628 rbcl = uart_getreg(bas, SAB_RBCL) & 31;
629 if (rbcl == 0)
630 rbcl = 32;
631 for (i = 0; i < rbcl; i += 2) {
632 if (uart_rx_full(sc)) {
633 sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN;
634 break;
635 }
636 xc = uart_getreg(bas, SAB_RFIFO);
637 s = uart_getreg(bas, SAB_RFIFO + 1);
638 if (s & SAB_RSTAT_FE)
639 xc |= UART_STAT_FRAMERR;
640 if (s & SAB_RSTAT_PE)
641 xc |= UART_STAT_PARERR;
642 uart_rx_put(sc, xc);
643 }
644 }
645
646 while (uart_getreg(bas, SAB_STAR) & SAB_STAR_CEC)
647 ;
648 uart_setreg(bas, SAB_CMDR, SAB_CMDR_RMC);
649 uart_barrier(bas);
650 uart_unlock(sc->sc_hwmtx);
651 return (0);
652}
653
654static int
655sab82532_bus_setsig(struct uart_softc *sc, int sig)
656{
657 struct uart_bas *bas;
658 uint32_t new, old;
659 uint8_t mode, pvr;
660
661 bas = &sc->sc_bas;
662 do {
663 old = sc->sc_hwsig;
664 new = old;
665 if (sig & SER_DDTR) {
666 SIGCHG(sig & SER_DTR, new, SER_DTR,
667 SER_DDTR);
668 }
669 if (sig & SER_DRTS) {
670 SIGCHG(sig & SER_RTS, new, SER_RTS,
671 SER_DRTS);
672 }
673 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
674
675 uart_lock(sc->sc_hwmtx);
676 /* Set DTR pin. */
677 pvr = uart_getreg(bas, SAB_PVR);
678 switch (bas->chan) {
679 case 1:
680 if (new & SER_DTR)
681 pvr &= ~SAB_PVR_DTR_A;
682 else
683 pvr |= SAB_PVR_DTR_A;
684 break;
685 case 2:
686 if (new & SER_DTR)
687 pvr &= ~SAB_PVR_DTR_B;
688 else
689 pvr |= SAB_PVR_DTR_B;
690 break;
691 }
692 uart_setreg(bas, SAB_PVR, pvr);
693
694 /* Set RTS pin. */
695 mode = uart_getreg(bas, SAB_MODE);
696 if (new & SER_RTS)
697 mode &= ~SAB_MODE_FRTS;
698 else
699 mode |= SAB_MODE_FRTS;
700 uart_setreg(bas, SAB_MODE, mode);
701 uart_barrier(bas);
702 uart_unlock(sc->sc_hwmtx);
703 return (0);
704}
705
706static int
707sab82532_bus_transmit(struct uart_softc *sc)
708{
709 struct uart_bas *bas;
710 int i;
711
712 bas = &sc->sc_bas;
713 uart_lock(sc->sc_hwmtx);
714 while (!(uart_getreg(bas, SAB_STAR) & SAB_STAR_XFW))
715 ;
716 for (i = 0; i < sc->sc_txdatasz; i++)
717 uart_setreg(bas, SAB_XFIFO + i, sc->sc_txbuf[i]);
718 uart_barrier(bas);
719 while (uart_getreg(bas, SAB_STAR) & SAB_STAR_CEC)
720 ;
721 uart_setreg(bas, SAB_CMDR, SAB_CMDR_XF);
722 sc->sc_txbusy = 1;
723 uart_unlock(sc->sc_hwmtx);
724 return (0);
725}