| twereg.h (76340) | twereg.h (91790) |
|---|---|
| 1/*- 2 * Copyright (c) 2000 Michael Smith 3 * Copyright (c) 2000 BSDi 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: --- 10 unchanged lines hidden (view full) --- 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * | 1/*- 2 * Copyright (c) 2000 Michael Smith 3 * Copyright (c) 2000 BSDi 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: --- 10 unchanged lines hidden (view full) --- 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * |
| 27 * $FreeBSD: head/sys/dev/twe/twereg.h 76340 2001-05-07 21:46:44Z msmith $ | 27 * $FreeBSD: head/sys/dev/twe/twereg.h 91790 2002-03-07 09:55:41Z msmith $ |
| 28 */ 29 30/* 31 * Register names, bit definitions, structure names and members are 32 * identical with those in the Linux driver where possible and sane 33 * for simplicity's sake. (The TW_ prefix has become TWE_) 34 * Some defines that are clearly irrelevant to FreeBSD have been 35 * removed. --- 6 unchanged lines hidden (view full) --- 42#define TWE_CONTROL_MASK_RESPONSE_INTERRUPT 0x00010000 43#define TWE_CONTROL_UNMASK_COMMAND_INTERRUPT 0x00008000 44#define TWE_CONTROL_UNMASK_RESPONSE_INTERRUPT 0x00004000 45#define TWE_CONTROL_CLEAR_ERROR_STATUS 0x00000200 46#define TWE_CONTROL_ISSUE_SOFT_RESET 0x00000100 47#define TWE_CONTROL_ENABLE_INTERRUPTS 0x00000080 48#define TWE_CONTROL_DISABLE_INTERRUPTS 0x00000040 49#define TWE_CONTROL_ISSUE_HOST_INTERRUPT 0x00000020 | 28 */ 29 30/* 31 * Register names, bit definitions, structure names and members are 32 * identical with those in the Linux driver where possible and sane 33 * for simplicity's sake. (The TW_ prefix has become TWE_) 34 * Some defines that are clearly irrelevant to FreeBSD have been 35 * removed. --- 6 unchanged lines hidden (view full) --- 42#define TWE_CONTROL_MASK_RESPONSE_INTERRUPT 0x00010000 43#define TWE_CONTROL_UNMASK_COMMAND_INTERRUPT 0x00008000 44#define TWE_CONTROL_UNMASK_RESPONSE_INTERRUPT 0x00004000 45#define TWE_CONTROL_CLEAR_ERROR_STATUS 0x00000200 46#define TWE_CONTROL_ISSUE_SOFT_RESET 0x00000100 47#define TWE_CONTROL_ENABLE_INTERRUPTS 0x00000080 48#define TWE_CONTROL_DISABLE_INTERRUPTS 0x00000040 49#define TWE_CONTROL_ISSUE_HOST_INTERRUPT 0x00000020 |
| 50#define TWE_CONTROL_CLEAR_PARITY_ERROR 0x00800000 51#define TWE_CONTROL_CLEAR_PCI_ABORT 0x00100000 |
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| 50 51#define TWE_SOFT_RESET(sc) TWE_CONTROL(sc, TWE_CONTROL_ISSUE_SOFT_RESET | \ 52 TWE_CONTROL_CLEAR_HOST_INTERRUPT | \ 53 TWE_CONTROL_CLEAR_ATTENTION_INTERRUPT | \ 54 TWE_CONTROL_MASK_COMMAND_INTERRUPT | \ 55 TWE_CONTROL_MASK_RESPONSE_INTERRUPT | \ 56 TWE_CONTROL_CLEAR_ERROR_STATUS | \ 57 TWE_CONTROL_DISABLE_INTERRUPTS) --- 37 unchanged lines hidden (view full) --- 95#define TWE_RESPONSE_ID_MASK 0x00000FF0 96 97/* PCI related defines */ 98#define TWE_IO_CONFIG_REG 0x10 99#define TWE_DEVICE_NAME "3ware Storage Controller" 100#define TWE_VENDOR_ID 0x13C1 101#define TWE_DEVICE_ID 0x1000 102#define TWE_DEVICE_ID_ASIC 0x1001 | 52 53#define TWE_SOFT_RESET(sc) TWE_CONTROL(sc, TWE_CONTROL_ISSUE_SOFT_RESET | \ 54 TWE_CONTROL_CLEAR_HOST_INTERRUPT | \ 55 TWE_CONTROL_CLEAR_ATTENTION_INTERRUPT | \ 56 TWE_CONTROL_MASK_COMMAND_INTERRUPT | \ 57 TWE_CONTROL_MASK_RESPONSE_INTERRUPT | \ 58 TWE_CONTROL_CLEAR_ERROR_STATUS | \ 59 TWE_CONTROL_DISABLE_INTERRUPTS) --- 37 unchanged lines hidden (view full) --- 97#define TWE_RESPONSE_ID_MASK 0x00000FF0 98 99/* PCI related defines */ 100#define TWE_IO_CONFIG_REG 0x10 101#define TWE_DEVICE_NAME "3ware Storage Controller" 102#define TWE_VENDOR_ID 0x13C1 103#define TWE_DEVICE_ID 0x1000 104#define TWE_DEVICE_ID_ASIC 0x1001 |
| 105#define TWE_PCI_CLEAR_PARITY_ERROR 0xc100 106#define TWE_PCI_CLEAR_PCI_ABORT 0x2000 |
|
| 103 104/* command packet opcodes */ 105#define TWE_OP_NOP 0x00 106#define TWE_OP_INIT_CONNECTION 0x01 107#define TWE_OP_READ 0x02 108#define TWE_OP_WRITE 0x03 109#define TWE_OP_READVERIFY 0x04 110#define TWE_OP_VERIFY 0x05 --- 7 unchanged lines hidden (view full) --- 118#define TWE_OP_GET_PARAM 0x12 119#define TWE_OP_SET_PARAM 0x13 120#define TWE_OP_CREATEUNIT 0x14 121#define TWE_OP_DELETEUNIT 0x15 122#define TWE_OP_REBUILDUNIT 0x17 123#define TWE_OP_SECTOR_INFO 0x1a 124#define TWE_OP_AEN_LISTEN 0x1c 125#define TWE_OP_CMD_PACKET 0x1d | 107 108/* command packet opcodes */ 109#define TWE_OP_NOP 0x00 110#define TWE_OP_INIT_CONNECTION 0x01 111#define TWE_OP_READ 0x02 112#define TWE_OP_WRITE 0x03 113#define TWE_OP_READVERIFY 0x04 114#define TWE_OP_VERIFY 0x05 --- 7 unchanged lines hidden (view full) --- 122#define TWE_OP_GET_PARAM 0x12 123#define TWE_OP_SET_PARAM 0x13 124#define TWE_OP_CREATEUNIT 0x14 125#define TWE_OP_DELETEUNIT 0x15 126#define TWE_OP_REBUILDUNIT 0x17 127#define TWE_OP_SECTOR_INFO 0x1a 128#define TWE_OP_AEN_LISTEN 0x1c 129#define TWE_OP_CMD_PACKET 0x1d |
| 130#define TWE_OP_ATA_PASSTHROUGH 0x1e 131#define TWE_OP_CMD_WITH_DATA 0x1f |
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| 126 127/* command status values */ 128#define TWE_STATUS_RESET 0xff /* controller requests reset */ 129#define TWE_STATUS_FATAL 0xc0 /* fatal errors not requiring reset */ 130#define TWE_STATUS_WARNING 0x80 /* warnings */ 131#define TWE_STAUS_INFO 0x40 /* informative status */ 132 133/* misc defines */ 134#define TWE_ALIGNMENT 0x200 135#define TWE_MAX_UNITS 16 136#define TWE_COMMAND_ALIGNMENT_MASK 0x1ff 137#define TWE_INIT_MESSAGE_CREDITS 0xff /* older firmware has issues with 256 commands */ 138#define TWE_SHUTDOWN_MESSAGE_CREDITS 0x001 139#define TWE_INIT_COMMAND_PACKET_SIZE 0x3 140#define TWE_MAX_SGL_LENGTH 62 | 132 133/* command status values */ 134#define TWE_STATUS_RESET 0xff /* controller requests reset */ 135#define TWE_STATUS_FATAL 0xc0 /* fatal errors not requiring reset */ 136#define TWE_STATUS_WARNING 0x80 /* warnings */ 137#define TWE_STAUS_INFO 0x40 /* informative status */ 138 139/* misc defines */ 140#define TWE_ALIGNMENT 0x200 141#define TWE_MAX_UNITS 16 142#define TWE_COMMAND_ALIGNMENT_MASK 0x1ff 143#define TWE_INIT_MESSAGE_CREDITS 0xff /* older firmware has issues with 256 commands */ 144#define TWE_SHUTDOWN_MESSAGE_CREDITS 0x001 145#define TWE_INIT_COMMAND_PACKET_SIZE 0x3 146#define TWE_MAX_SGL_LENGTH 62 |
| 147#define TWE_MAX_ATA_SGL_LENGTH 60 148#define TWE_MAX_PASSTHROUGH 4096 |
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| 141#define TWE_Q_LENGTH TWE_INIT_MESSAGE_CREDITS 142#define TWE_Q_START 0 143#define TWE_MAX_RESET_TRIES 3 144#define TWE_BLOCK_SIZE 0x200 /* 512-byte blocks */ 145#define TWE_SECTOR_SIZE 0x200 /* generic I/O bufffer */ 146#define TWE_IOCTL 0x80 147#define TWE_MAX_AEN_TRIES 100 148#define TWE_UNIT_ONLINE 1 --- 118 unchanged lines hidden (view full) --- 267{ 268 u_int8_t opcode:5; 269 u_int8_t sgl_offset:3; 270 u_int8_t size; 271 u_int8_t request_id; 272 u_int8_t unit:4; 273 u_int8_t host_id:4; 274 u_int8_t status; | 149#define TWE_Q_LENGTH TWE_INIT_MESSAGE_CREDITS 150#define TWE_Q_START 0 151#define TWE_MAX_RESET_TRIES 3 152#define TWE_BLOCK_SIZE 0x200 /* 512-byte blocks */ 153#define TWE_SECTOR_SIZE 0x200 /* generic I/O bufffer */ 154#define TWE_IOCTL 0x80 155#define TWE_MAX_AEN_TRIES 100 156#define TWE_UNIT_ONLINE 1 --- 118 unchanged lines hidden (view full) --- 275{ 276 u_int8_t opcode:5; 277 u_int8_t sgl_offset:3; 278 u_int8_t size; 279 u_int8_t request_id; 280 u_int8_t unit:4; 281 u_int8_t host_id:4; 282 u_int8_t status; |
| 283 u_int16_t param; 284 u_int16_t features; 285 u_int16_t sector_count; 286 u_int16_t sector_num; 287 u_int16_t cylinder_lo; 288 u_int16_t cylinder_hi; 289 u_int8_t drive_head; 290 u_int8_t command; 291 TWE_SG_Entry sgl[TWE_MAX_ATA_SGL_LENGTH]; 292} TWE_Command_ATA __attribute__ ((packed)); 293 294typedef struct 295{ 296 u_int8_t opcode:5; 297 u_int8_t sgl_offset:3; 298 u_int8_t size; 299 u_int8_t request_id; 300 u_int8_t unit:4; 301 u_int8_t host_id:4; 302 u_int8_t status; |
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| 275 u_int8_t flags; 276#define TWE_FLAGS_SUCCESS 0x00 277#define TWE_FLAGS_INFORMATIONAL 0x01 278#define TWE_FLAGS_WARNING 0x02 279#define TWE_FLAGS_FATAL 0x03 280#define TWE_FLAGS_PERCENTAGE (1<<8) /* bits 0-6 indicate completion percentage */ 281 u_int16_t count; /* block count, parameter count, message credits */ 282} TWE_Command_Generic __attribute__ ((packed)); 283 284/* command packet - must be TWE_ALIGNMENT aligned */ 285typedef union 286{ 287 TWE_Command_INITCONNECTION initconnection; 288 TWE_Command_IO io; 289 TWE_Command_PARAM param; 290 TWE_Command_CHECKSTATUS checkstatus; 291 TWE_Command_REBUILDUNIT rebuildunit; 292 TWE_Command_SETATAFEATURE setatafeature; | 303 u_int8_t flags; 304#define TWE_FLAGS_SUCCESS 0x00 305#define TWE_FLAGS_INFORMATIONAL 0x01 306#define TWE_FLAGS_WARNING 0x02 307#define TWE_FLAGS_FATAL 0x03 308#define TWE_FLAGS_PERCENTAGE (1<<8) /* bits 0-6 indicate completion percentage */ 309 u_int16_t count; /* block count, parameter count, message credits */ 310} TWE_Command_Generic __attribute__ ((packed)); 311 312/* command packet - must be TWE_ALIGNMENT aligned */ 313typedef union 314{ 315 TWE_Command_INITCONNECTION initconnection; 316 TWE_Command_IO io; 317 TWE_Command_PARAM param; 318 TWE_Command_CHECKSTATUS checkstatus; 319 TWE_Command_REBUILDUNIT rebuildunit; 320 TWE_Command_SETATAFEATURE setatafeature; |
| 321 TWE_Command_ATA ata; |
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| 293 TWE_Command_Generic generic; 294 u_int8_t pad[512]; 295} TWE_Command; 296 297/* response queue entry */ 298typedef union 299{ 300 struct --- 154 unchanged lines hidden (view full) --- 455 456typedef struct 457{ 458 u_int16_t table_id; 459 u_int8_t parameter_id; 460 u_int8_t parameter_size_bytes; 461 u_int8_t data[0]; 462} TWE_Param __attribute__ ((packed)); | 322 TWE_Command_Generic generic; 323 u_int8_t pad[512]; 324} TWE_Command; 325 326/* response queue entry */ 327typedef union 328{ 329 struct --- 154 unchanged lines hidden (view full) --- 484 485typedef struct 486{ 487 u_int16_t table_id; 488 u_int8_t parameter_id; 489 u_int8_t parameter_size_bytes; 490 u_int8_t data[0]; 491} TWE_Param __attribute__ ((packed)); |
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