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twereg.h (66992) twereg.h (67555)
1/*-
2 * Copyright (c) 2000 Michael Smith
3 * Copyright (c) 2000 BSDi
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:

--- 10 unchanged lines hidden (view full) ---

19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
1/*-
2 * Copyright (c) 2000 Michael Smith
3 * Copyright (c) 2000 BSDi
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:

--- 10 unchanged lines hidden (view full) ---

19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 * $FreeBSD: head/sys/dev/twe/twereg.h 66992 2000-10-12 01:43:40Z msmith $
27 * $FreeBSD: head/sys/dev/twe/twereg.h 67555 2000-10-25 06:59:06Z msmith $
28 */
29
30/*
31 * Register names, bit definitions, structure names and members are
32 * identical with those in the Linux driver where possible and sane
33 * for simplicity's sake. (The TW_ prefix has become TWE_)
34 * Some defines that are clearly irrelevant to FreeBSD have been
35 * removed.

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71#define TWE_STATUS_RESPONSE_QUEUE_EMPTY 0x00004000
72#define TWE_STATUS_MICROCONTROLLER_READY 0x00002000
73#define TWE_STATUS_COMMAND_QUEUE_EMPTY 0x00001000
74#define TWE_STATUS_ALL_INTERRUPTS 0x000F0000
75#define TWE_STATUS_CLEARABLE_BITS 0x00D00000
76#define TWE_STATUS_EXPECTED_BITS 0x00002000
77#define TWE_STATUS_UNEXPECTED_BITS 0x00F80000
78
28 */
29
30/*
31 * Register names, bit definitions, structure names and members are
32 * identical with those in the Linux driver where possible and sane
33 * for simplicity's sake. (The TW_ prefix has become TWE_)
34 * Some defines that are clearly irrelevant to FreeBSD have been
35 * removed.

--- 35 unchanged lines hidden (view full) ---

71#define TWE_STATUS_RESPONSE_QUEUE_EMPTY 0x00004000
72#define TWE_STATUS_MICROCONTROLLER_READY 0x00002000
73#define TWE_STATUS_COMMAND_QUEUE_EMPTY 0x00001000
74#define TWE_STATUS_ALL_INTERRUPTS 0x000F0000
75#define TWE_STATUS_CLEARABLE_BITS 0x00D00000
76#define TWE_STATUS_EXPECTED_BITS 0x00002000
77#define TWE_STATUS_UNEXPECTED_BITS 0x00F80000
78
79/* XXX this is a little harsh, but necessary to chase down firmware problems */
80#define TWE_STATUS_PANIC_BITS (TWE_STATUS_MICROCONTROLLER_ERROR)
81
79/* for use with the %b printf format */
80#define TWE_STATUS_BITS_DESCRIPTION \
81 "\20\15CQEMPTY\16UCREADY\17RQEMPTY\20CQFULL\21RINTR\22CINTR\23AINTR\24HINTR\25PCIABRT\26MCERR\27QERR\30PCIPERR\n"
82
83/* detect inconsistencies in the status register */
84#define TWE_STATUS_ERRORS(x) \
85 (((x & TWE_STATUS_PCI_ABORT) || \
86 (x & TWE_STATUS_PCI_PARITY_ERROR) || \

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93
94/* PCI related defines */
95#define TWE_IO_CONFIG_REG 0x10
96#define TWE_DEVICE_NAME "3ware Storage Controller"
97#define TWE_VENDOR_ID 0x13C1
98#define TWE_DEVICE_ID 0x1000
99
100/* command packet opcodes */
82/* for use with the %b printf format */
83#define TWE_STATUS_BITS_DESCRIPTION \
84 "\20\15CQEMPTY\16UCREADY\17RQEMPTY\20CQFULL\21RINTR\22CINTR\23AINTR\24HINTR\25PCIABRT\26MCERR\27QERR\30PCIPERR\n"
85
86/* detect inconsistencies in the status register */
87#define TWE_STATUS_ERRORS(x) \
88 (((x & TWE_STATUS_PCI_ABORT) || \
89 (x & TWE_STATUS_PCI_PARITY_ERROR) || \

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96
97/* PCI related defines */
98#define TWE_IO_CONFIG_REG 0x10
99#define TWE_DEVICE_NAME "3ware Storage Controller"
100#define TWE_VENDOR_ID 0x13C1
101#define TWE_DEVICE_ID 0x1000
102
103/* command packet opcodes */
101#define TWE_OP_NOP 0x0
102#define TWE_OP_INIT_CONNECTION 0x1
103#define TWE_OP_READ 0x2
104#define TWE_OP_WRITE 0x3
105#define TWE_OP_VERIFY 0x4
104#define TWE_OP_NOP 0x00
105#define TWE_OP_INIT_CONNECTION 0x01
106#define TWE_OP_READ 0x02
107#define TWE_OP_WRITE 0x03
108#define TWE_OP_READVERIFY 0x04
109#define TWE_OP_VERIFY 0x05
110#define TWE_OP_ZEROUNIT 0x08
111#define TWE_OP_REPLACEUNIT 0x09
112#define TWE_OP_HOTSWAP 0x0a
113#define TWE_OP_SETATAFEATURE 0x0c
114#define TWE_OP_FLUSH 0x0e
115#define TWE_OP_ABORT 0x0f
116#define TWE_OP_CHECKSTATUS 0x10
106#define TWE_OP_GET_PARAM 0x12
107#define TWE_OP_SET_PARAM 0x13
117#define TWE_OP_GET_PARAM 0x12
118#define TWE_OP_SET_PARAM 0x13
119#define TWE_OP_CREATEUNIT 0x14
120#define TWE_OP_DELETEUNIT 0x15
121#define TWE_OP_REBUILDUNIT 0x17
108#define TWE_OP_SECTOR_INFO 0x1a
109#define TWE_OP_AEN_LISTEN 0x1c
122#define TWE_OP_SECTOR_INFO 0x1a
123#define TWE_OP_AEN_LISTEN 0x1c
124#define TWE_OP_CMD_PACKET 0x1d
110
125
111/* asynchronous event notification (AEN) codes */
112#define TWE_AEN_QUEUE_EMPTY 0x0000
113#define TWE_AEN_SOFT_RESET 0x0001
114#define TWE_AEN_DEGRADED_MIRROR 0x0002
115#define TWE_AEN_CONTROLLER_ERROR 0x0003
116#define TWE_AEN_REBUILD_FAIL 0x0004
117#define TWE_AEN_REBUILD_DONE 0x0005
118#define TWE_AEN_QUEUE_FULL 0x00ff
119#define TWE_AEN_TABLE_UNDEFINED 0x15
120
121/* misc defines */
122#define TWE_ALIGNMENT 0x200
123#define TWE_MAX_UNITS 16
124#define TWE_COMMAND_ALIGNMENT_MASK 0x1ff
126/* misc defines */
127#define TWE_ALIGNMENT 0x200
128#define TWE_MAX_UNITS 16
129#define TWE_COMMAND_ALIGNMENT_MASK 0x1ff
125#define TWE_INIT_MESSAGE_CREDITS 0x100
130#define TWE_INIT_MESSAGE_CREDITS 0xff /* older firmware has issues with 256 commands */
131#define TWE_SHUTDOWN_MESSAGE_CREDITS 0x001
126#define TWE_INIT_COMMAND_PACKET_SIZE 0x3
127#define TWE_MAX_SGL_LENGTH 62
132#define TWE_INIT_COMMAND_PACKET_SIZE 0x3
133#define TWE_MAX_SGL_LENGTH 62
128#define TWE_Q_LENGTH 50
134#define TWE_Q_LENGTH TWE_INIT_MESSAGE_CREDITS
129#define TWE_Q_START 0
130#define TWE_MAX_RESET_TRIES 3
135#define TWE_Q_START 0
136#define TWE_MAX_RESET_TRIES 3
131#define TWE_UNIT_INFORMATION_TABLE_BASE 0x300
132#define TWE_BLOCK_SIZE 0x200 /* 512-byte blocks */
133#define TWE_SECTOR_SIZE 0x200 /* generic I/O bufffer */
134#define TWE_IOCTL 0x80
135#define TWE_MAX_AEN_TRIES 100
137#define TWE_BLOCK_SIZE 0x200 /* 512-byte blocks */
138#define TWE_SECTOR_SIZE 0x200 /* generic I/O bufffer */
139#define TWE_IOCTL 0x80
140#define TWE_MAX_AEN_TRIES 100
141#define TWE_UNIT_ONLINE 1
136
142
137/* wrappers for bus-space actions */
138#define TWE_CONTROL(sc, val) bus_space_write_4(sc->twe_btag, sc->twe_bhandle, 0x0, (u_int32_t)val)
139#define TWE_STATUS(sc) (u_int32_t)bus_space_read_4(sc->twe_btag, sc->twe_bhandle, 0x4)
140#define TWE_COMMAND_QUEUE(sc, val) bus_space_write_4(sc->twe_btag, sc->twe_bhandle, 0x8, (u_int32_t)val)
141#define TWE_RESPONSE_QUEUE(sc) (TWE_Response_Queue)bus_space_read_4(sc->twe_btag, sc->twe_bhandle, 0xc)
142
143/* scatter/gather list entry */
144typedef struct
145{
146 u_int32_t address;
147 u_int32_t length;
148} TWE_SG_Entry __attribute__ ((packed));
149
143/* scatter/gather list entry */
144typedef struct
145{
146 u_int32_t address;
147 u_int32_t length;
148} TWE_SG_Entry __attribute__ ((packed));
149
150/* command packet - must be TWE_ALIGNMENT aligned */
150typedef struct {
151 u_int8_t opcode:5; /* TWE_OP_INITCONNECTION */
152 u_int8_t res1:3;
153 u_int8_t size;
154 u_int8_t request_id;
155 u_int8_t res2:4;
156 u_int8_t host_id:4;
157 u_int8_t status;
158 u_int8_t flags;
159 u_int16_t message_credits;
160 u_int32_t response_queue_pointer;
161} TWE_Command_INITCONNECTION __attribute__ ((packed));
162
151typedef struct
152{
163typedef struct
164{
165 u_int8_t opcode:5; /* TWE_OP_READ/TWE_OP_WRITE */
166 u_int8_t res1:3;
167 u_int8_t size;
168 u_int8_t request_id;
169 u_int8_t unit:4;
170 u_int8_t host_id:4;
171 u_int8_t status;
172 u_int8_t flags;
173 u_int16_t block_count;
174 u_int32_t lba;
175 TWE_SG_Entry sgl[TWE_MAX_SGL_LENGTH];
176} TWE_Command_IO __attribute__ ((packed));
177
178typedef struct
179{
180 u_int8_t opcode:5; /* TWE_OP_HOTSWAP */
181 u_int8_t res1:3;
182 u_int8_t size;
183 u_int8_t request_id;
184 u_int8_t unit:4;
185 u_int8_t host_id:4;
186 u_int8_t status;
187 u_int8_t flags;
188 u_int8_t action;
189#define TWE_OP_HOTSWAP_REMOVE 0x00 /* remove assumed-degraded unit */
190#define TWE_OP_HOTSWAP_ADD_CBOD 0x01 /* add CBOD to empty port */
191#define TWE_OP_HOTSWAP_ADD_SPARE 0x02 /* add spare to empty port */
192 u_int8_t aport;
193} TWE_Command_HOTSWAP __attribute__ ((packed));
194
195typedef struct
196{
197 u_int8_t opcode:5; /* TWE_OP_SETATAFEATURE */
198 u_int8_t res1:3;
199 u_int8_t size;
200 u_int8_t request_id;
201 u_int8_t unit:4;
202 u_int8_t host_id:4;
203 u_int8_t status;
204 u_int8_t flags;
205 u_int8_t feature;
206#define TWE_OP_SETATAFEATURE_WCE 0x02
207#define TWE_OP_SETATAFEATURE_DIS_WCE 0x82
208 u_int8_t feature_mode;
209 u_int16_t all_units;
210 u_int16_t persistence;
211} TWE_Command_SETATAFEATURE __attribute__ ((packed));
212
213typedef struct
214{
215 u_int8_t opcode:5; /* TWE_OP_CHECKSTATUS */
216 u_int8_t res1:3;
217 u_int8_t size;
218 u_int8_t request_id;
219 u_int8_t unit:4;
220 u_int8_t res2:4;
221 u_int8_t status;
222 u_int8_t flags;
223 u_int16_t target_status; /* set low byte to target request's ID */
224} TWE_Command_CHECKSTATUS __attribute__ ((packed));
225
226typedef struct
227{
228 u_int8_t opcode:5; /* TWE_OP_GETPARAM, TWE_OP_SETPARAM */
229 u_int8_t res1:3;
230 u_int8_t size;
231 u_int8_t request_id;
232 u_int8_t unit:4;
233 u_int8_t host_id:4;
234 u_int8_t status;
235 u_int8_t flags;
236 u_int16_t param_count;
237 TWE_SG_Entry sgl[TWE_MAX_SGL_LENGTH];
238} TWE_Command_PARAM __attribute__ ((packed));
239
240typedef struct
241{
242 u_int8_t opcode:5; /* TWE_OP_REBUILDUNIT */
243 u_int8_t res1:3;
244 u_int8_t size;
245 u_int8_t request_id;
246 u_int8_t src_unit:4;
247 u_int8_t host_id:4;
248 u_int8_t status;
249 u_int8_t flags;
250 u_int8_t action:7;
251#define TWE_OP_REBUILDUNIT_NOP 0
252#define TWE_OP_REBUILDUNIT_STOP 2 /* stop all rebuilds */
253#define TWE_OP_REBUILDUNIT_START 4 /* start rebuild with lowest unit */
254#define TWE_OP_REBUILDUNIT_STARTUNIT 5 /* rebuild src_unit (not supported) */
255 u_int8_t cs:1; /* request state change on src_unit */
256 u_int8_t logical_subunit; /* for RAID10 rebuild of logical subunit */
257} TWE_Command_REBUILDUNIT __attribute__ ((packed));
258
259typedef struct
260{
153 u_int8_t opcode:5;
154 u_int8_t sgl_offset:3;
155 u_int8_t size;
156 u_int8_t request_id;
157 u_int8_t unit:4;
158 u_int8_t host_id:4;
159 u_int8_t status;
160 u_int8_t flags;
261 u_int8_t opcode:5;
262 u_int8_t sgl_offset:3;
263 u_int8_t size;
264 u_int8_t request_id;
265 u_int8_t unit:4;
266 u_int8_t host_id:4;
267 u_int8_t status;
268 u_int8_t flags;
269#define TWE_FLAGS_SUCCESS 0x00
270#define TWE_FLAGS_INFORMATIONAL 0x01
271#define TWE_FLAGS_WARNING 0x02
272#define TWE_FLAGS_FATAL 0x03
273#define TWE_FLAGS_PERCENTAGE (1<<8) /* bits 0-6 indicate completion percentage */
161 u_int16_t count; /* block count, parameter count, message credits */
274 u_int16_t count; /* block count, parameter count, message credits */
162 union {
163 struct {
164 u_int32_t lba;
165 TWE_SG_Entry sgl[TWE_MAX_SGL_LENGTH];
166 } io __attribute__ ((packed));
167 struct {
168 TWE_SG_Entry sgl[TWE_MAX_SGL_LENGTH];
169 } param;
170 struct {
171 u_int32_t response_queue_pointer;
172 } init_connection;
173 } args;
174} TWE_Command __attribute__ ((packed));
275} TWE_Command_Generic __attribute__ ((packed));
175
276
176/* argument to TWE_OP_GET/SET_PARAM */
177typedef struct
277/* command packet - must be TWE_ALIGNMENT aligned */
278typedef union
178{
279{
179 u_int16_t table_id;
180 u_int8_t parameter_id;
181 u_int8_t parameter_size_bytes;
182 u_int8_t data[1];
183} TWE_Param __attribute__ ((packed));
280 TWE_Command_INITCONNECTION initconnection;
281 TWE_Command_IO io;
282 TWE_Command_PARAM param;
283 TWE_Command_CHECKSTATUS checkstatus;
284 TWE_Command_REBUILDUNIT rebuildunit;
285 TWE_Command_SETATAFEATURE setatafeature;
286 TWE_Command_Generic generic;
287 u_int8_t pad[512];
288} TWE_Command;
184
185/* response queue entry */
186typedef union
187{
188 struct
189 {
190 u_int32_t undefined_1:4;
191 u_int32_t response_id:8;
192 u_int32_t undefined_2:20;
193 } u;
194 u_int32_t value;
195} TWE_Response_Queue;
196
289
290/* response queue entry */
291typedef union
292{
293 struct
294 {
295 u_int32_t undefined_1:4;
296 u_int32_t response_id:8;
297 u_int32_t undefined_2:20;
298 } u;
299 u_int32_t value;
300} TWE_Response_Queue;
301
197#if 0 /* no idea what these will be useful for yet */
302/*
303 * From 3ware's documentation:
304 * All parameters maintained by the controller are grouped into related tables.
305 * Tables are are accessed indirectly via get and set parameter commands.
306 * To access a specific parameter in a table, the table ID and parameter index
307 * are used to uniquely identify a parameter. Table 0xffff is the directory
308 * table and provides a list of the table IDs and sizes of all other tables.
309 * Index zero in each table specifies the entire table, and index one specifies
310 * the size of the table. An entire table can be read or set by using index zero.
311 */
312
313#define TWE_PARAM_PARAM_ALL 0
314#define TWE_PARAM_PARAM_SIZE 1
315
316#define TWE_PARAM_DIRECTORY 0xffff /* size is 4 * number of tables */
317#define TWE_PARAM_DIRECTORY_TABLES 2 /* 16 bits * number of tables */
318#define TWE_PARAM_DIRECTORY_SIZES 3 /* 16 bits * number of tables */
319
320#define TWE_PARAM_DRIVESUMMARY 0x0002
321#define TWE_PARAM_DRIVESUMMARY_Num 2 /* number of physical drives [2] */
322#define TWE_PARAM_DRIVESUMMARY_Status 3 /* array giving drive status per aport */
323#define TWE_PARAM_DRIVESTATUS_Missing 0x00
324#define TWE_PARAM_DRIVESTATUS_NotSupp 0xfe
325#define TWE_PARAM_DRIVESTATUS_Present 0xff
326
327#define TWE_PARAM_UNITSUMMARY 0x0003
328#define TWE_PARAM_UNITSUMMARY_Num 2 /* number of logical units [2] */
329#define TWE_PARAM_UNITSUMMARY_Status 3 /* array giving unit status [16] */
330#define TWE_PARAM_UNITSTATUS_Online (1<<0)
331#define TWE_PARAM_UNITSTATUS_Complete (1<<1)
332#define TWE_PARAM_UNITSTATUS_MASK 0xfc
333#define TWE_PARAM_UNITSTATUS_Normal 0xfc
334#define TWE_PARAM_UNITSTATUS_Initialising 0xf4 /* cannot be incomplete */
335#define TWE_PARAM_UNITSTATUS_Degraded 0xec
336#define TWE_PARAM_UNITSTATUS_Rebuilding 0xdc /* cannot be incomplete */
337#define TWE_PARAM_UNITSTATUS_Verifying 0xcc /* cannot be incomplete */
338#define TWE_PARAM_UNITSTATUS_Corrupt 0xbc /* cannot be complete */
339#define TWE_PARAM_UNITSTATUS_Missing 0x00 /* cannot be complete or online */
340
341#define TWE_PARAM_DRIVEINFO 0x0200 /* add drive number 0x00-0x0f XXX docco confused 0x0100 vs 0x0200 */
342#define TWE_PARAM_DRIVEINFO_Size 2 /* size in blocks [4] */
343#define TWE_PARAM_DRIVEINFO_Model 3 /* drive model string [40] */
344#define TWE_PARAM_DRIVEINFO_Serial 4 /* drive serial number [20] */
345#define TWE_PARAM_DRIVEINFO_PhysCylNum 5 /* physical geometry [2] */
346#define TWE_PARAM_DRIVEINFO_PhysHeadNum 6 /* [2] */
347#define TWE_PARAM_DRIVEINFO_PhysSectorNym 7 /* [2] */
348#define TWE_PARAM_DRIVEINFO_LogCylNum 8 /* logical geometry [2] */
349#define TWE_PARAM_DRIVEINFO_LogHeadNum 9 /* [2] */
350#define TWE_PARAM_DRIVEINFO_LogSectorNum 10 /* [2] */
351#define TWE_PARAM_DRIVEINFO_UnitNum 11 /* unit number this drive is associated with or 0xff [1] */
352#define TWE_PARAM_DRIVEINFO_DriveFlags 12 /* N/A [1] */
353
354#define TWE_PARAM_APORTTIMEOUT 0x02c0 /* add (aport_number * 3) to parameter index */
355#define TWE_PARAM_APORTTIMEOUT_READ 2 /* read timeouts last 24hrs [2] */
356#define TWE_PARAM_APORTTIMEOUT_WRITE 3 /* write timeouts last 24hrs [2] */
357#define TWE_PARAM_APORTTIMEOUT_DEGRADE 4 /* degrade threshold [2] */
358
359#define TWE_PARAM_UNITINFO 0x0300 /* add unit number 0x00-0x0f */
360#define TWE_PARAM_UNITINFO_Number 2 /* unit number [1] */
361#define TWE_PARAM_UNITINFO_Status 3 /* unit status [1] */
362#define TWE_PARAM_UNITINFO_Capacity 4 /* unit capacity in blocks [4] */
363#define TWE_PARAM_UNITINFO_DescriptorSize 5 /* unit descriptor size + 3 bytes [2] */
364#define TWE_PARAM_UNITINFO_Descriptor 6 /* unit descriptor, TWE_UnitDescriptor or TWE_Array_Descriptor */
365#define TWE_PARAM_UNITINFO_Flags 7 /* unit flags [1] */
366#define TWE_PARAM_UNITFLAGS_WCE (1<<0)
367
368#define TWE_PARAM_AEN 0x0401
369#define TWE_PARAM_AEN_UnitCode 2 /* (unit number << 8) | AEN code [2] */
370#define TWE_AEN_QUEUE_EMPTY 0x00
371#define TWE_AEN_SOFT_RESET 0x01
372#define TWE_AEN_DEGRADED_MIRROR 0x02 /* reports unit */
373#define TWE_AEN_CONTROLLER_ERROR 0x03
374#define TWE_AEN_REBUILD_FAIL 0x04 /* reports unit */
375#define TWE_AEN_REBUILD_DONE 0x05 /* reports unit */
376#define TWE_AEN_INCOMP_UNIT 0x06 /* reports unit */
377#define TWE_AEN_INIT_DONE 0x07 /* reports unit */
378#define TWE_AEN_UNCLEAN_SHUTDOWN 0x08 /* reports unit */
379#define TWE_AEN_APORT_TIMEOUT 0x09 /* reports unit, rate limited to 1 per 2^16 errors */
380#define TWE_AEN_DRIVE_ERROR 0x0a /* reports unit */
381#define TWE_AEN_REBUILD_STARTED 0x0b /* reports unit */
382#define TWE_AEN_QUEUE_FULL 0xff
383#define TWE_AEN_TABLE_UNDEFINED 0x15
384#define TWE_AEN_CODE(x) ((x) & 0xff)
385#define TWE_AEN_UNIT(x) ((x) >> 8)
386
387#define TWE_PARAM_VERSION 0x0402
388#define TWE_PARAM_VERSION_Mon 2 /* monitor version [16] */
389#define TWE_PARAM_VERSION_FW 3 /* firmware version [16] */
390#define TWE_PARAM_VERSION_BIOS 4 /* BIOSs version [16] */
391#define TWE_PARAM_VERSION_PCB 5 /* PCB version [8] */
392#define TWE_PARAM_VERSION_ATA 6 /* A-chip version [8] */
393#define TWE_PARAM_VERSION_PCI 7 /* P-chip version [8] */
394#define TWE_PARAM_VERSION_CtrlModel 8 /* N/A */
395#define TWE_PARAM_VERSION_CtrlSerial 9 /* N/A */
396#define TWE_PARAM_VERSION_SBufSize 10 /* N/A */
397#define TWE_PARAM_VERSION_CompCode 11 /* compatibility code [4] */
398
399#define TWE_PARAM_CONTROLLER 0x0403
400#define TWE_PARAM_CONTROLLER_DCBSectors 2 /* # sectors reserved for DCB per drive [2] */
401#define TWE_PARAM_CONTROLLER_PortCount 3 /* number of drive ports [1] */
402
403#define TWE_PARAM_FEATURES 0x404
404#define TWE_PARAM_FEATURES_DriverShutdown 2 /* set to 1 if driver supports shutdown notification [1] */
405
198typedef struct
199{
406typedef struct
407{
200 int32_t buffer;
201 u_int8_t opcode;
202 u_int16_t table_id;
203 u_int8_t parameter_id;
204 u_int8_t parameter_size_bytes;
205 u_int8_t data[1];
206} TWE_Ioctl __attribute__ ((packed));
408 u_int8_t num_subunits; /* must be zero */
409 u_int8_t configuration;
410#define TWE_UD_CONFIG_CBOD 0x0c /* JBOD with DCB, used for mirrors */
411#define TWE_UD_CONFIG_SPARE 0x0d /* same as CBOD, but firmware will use as spare */
412#define TWE_UD_CONFIG_SUBUNIT 0x0e /* drive is a subunit in an array */
413#define TWE_UD_CONFIG_JBOD 0x0f /* plain drive */
414 u_int8_t phys_drv_num; /* may be 0xff if port can't be determined at runtime */
415 u_int8_t log_drv_num; /* must be zero for configuration == 0x0f */
416 u_int32_t start_lba;
417 u_int32_t block_count; /* actual drive size if configuration == 0x0f, otherwise less DCB size */
418} TWE_Unit_Descriptor __attribute__ ((packed));
207
208typedef struct
209{
419
420typedef struct
421{
210 u_int32_t base_addr;
211 u_int32_t control_reg_addr;
212 u_int32_t status_reg_addr;
213 u_int32_t command_que_addr;
214 u_int32_t response_que_addr;
215} TWE_Registers __attribute__ ((packed));
422 u_int8_t flag; /* must be 0xff */
423 u_int8_t res1;
424 u_int8_t mirunit_status[4]; /* bitmap of functional subunits in each mirror */
425 u_int8_t res2[6];
426} TWE_Mirror_Descriptor __attribute__ ((packed));
216
217typedef struct
218{
427
428typedef struct
429{
219 char *buffer;
220 int32_t length;
221 int32_t offset;
222 int32_t position;
223} TWE_Info __attribute__ ((packed));
224#endif
430 u_int8_t num_subunits; /* number of subunits, or number of mirror units in RAID10 */
431 u_int8_t configuration;
432#define TWE_UD_CONFIG_RAID0 0x00
433#define TWE_UD_CONFIG_RAID1 0x01
434#define TWE_UD_CONFIG_TwinStor 0x02
435#define TWE_UD_CONFIG_RAID5 0x05
436#define TWE_UD_CONFIG_RAID10 0x06
437 u_int8_t stripe_size;
438#define TWE_UD_STRIPE_4k 0x03
439#define TWE_UD_STRIPE_8k 0x04
440#define TWE_UD_STRIPE_16k 0x05
441#define TWE_UD_STRIPE_32k 0x06
442#define TWE_UD_STRIPE_64k 0x07
443 u_int8_t log_drv_status; /* bitmap of functional subunits, or mirror units in RAID10 */
444 u_int32_t start_lba;
445 u_int32_t block_count; /* actual drive size if configuration == 0x0f, otherwise less DCB size */
446 TWE_Unit_Descriptor subunit[0]; /* subunit descriptors, in RAID10 mode is [mirunit][subunit] */
447} TWE_Array_Descriptor __attribute__ ((packed));
225
448
226
449typedef struct
450{
451 u_int16_t table_id;
452 u_int8_t parameter_id;
453 u_int8_t parameter_size_bytes;
454 u_int8_t data[0];
455} TWE_Param __attribute__ ((packed));