1/*-
2 * Copyright (c) 2000 Michael Smith
3 * Copyright (c) 2000 BSDi
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
--- 10 unchanged lines hidden (view full) ---
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 * $FreeBSD: head/sys/dev/twe/twereg.h 66992 2000-10-12 01:43:40Z msmith $
28 */
29
30/*
31 * Register names, bit definitions, structure names and members are
32 * identical with those in the Linux driver where possible and sane
33 * for simplicity's sake. (The TW_ prefix has become TWE_)
34 * Some defines that are clearly irrelevant to FreeBSD have been
35 * removed.
--- 35 unchanged lines hidden (view full) ---
71#define TWE_STATUS_RESPONSE_QUEUE_EMPTY 0x00004000
72#define TWE_STATUS_MICROCONTROLLER_READY 0x00002000
73#define TWE_STATUS_COMMAND_QUEUE_EMPTY 0x00001000
74#define TWE_STATUS_ALL_INTERRUPTS 0x000F0000
75#define TWE_STATUS_CLEARABLE_BITS 0x00D00000
76#define TWE_STATUS_EXPECTED_BITS 0x00002000
77#define TWE_STATUS_UNEXPECTED_BITS 0x00F80000
78
79/* for use with the %b printf format */
80#define TWE_STATUS_BITS_DESCRIPTION \
81 "\20\15CQEMPTY\16UCREADY\17RQEMPTY\20CQFULL\21RINTR\22CINTR\23AINTR\24HINTR\25PCIABRT\26MCERR\27QERR\30PCIPERR\n"
82
83/* detect inconsistencies in the status register */
84#define TWE_STATUS_ERRORS(x) \
85 (((x & TWE_STATUS_PCI_ABORT) || \
86 (x & TWE_STATUS_PCI_PARITY_ERROR) || \
--- 6 unchanged lines hidden (view full) ---
93
94/* PCI related defines */
95#define TWE_IO_CONFIG_REG 0x10
96#define TWE_DEVICE_NAME "3ware Storage Controller"
97#define TWE_VENDOR_ID 0x13C1
98#define TWE_DEVICE_ID 0x1000
99
100/* command packet opcodes */
101#define TWE_OP_NOP 0x0
102#define TWE_OP_INIT_CONNECTION 0x1
103#define TWE_OP_READ 0x2
104#define TWE_OP_WRITE 0x3
105#define TWE_OP_VERIFY 0x4
106#define TWE_OP_GET_PARAM 0x12
107#define TWE_OP_SET_PARAM 0x13
108#define TWE_OP_SECTOR_INFO 0x1a
109#define TWE_OP_AEN_LISTEN 0x1c
110
111/* asynchronous event notification (AEN) codes */
112#define TWE_AEN_QUEUE_EMPTY 0x0000
113#define TWE_AEN_SOFT_RESET 0x0001
114#define TWE_AEN_DEGRADED_MIRROR 0x0002
115#define TWE_AEN_CONTROLLER_ERROR 0x0003
116#define TWE_AEN_REBUILD_FAIL 0x0004
117#define TWE_AEN_REBUILD_DONE 0x0005
118#define TWE_AEN_QUEUE_FULL 0x00ff
119#define TWE_AEN_TABLE_UNDEFINED 0x15
120
121/* misc defines */
122#define TWE_ALIGNMENT 0x200
123#define TWE_MAX_UNITS 16
124#define TWE_COMMAND_ALIGNMENT_MASK 0x1ff
125#define TWE_INIT_MESSAGE_CREDITS 0x100
126#define TWE_INIT_COMMAND_PACKET_SIZE 0x3
127#define TWE_MAX_SGL_LENGTH 62
128#define TWE_Q_LENGTH 50
129#define TWE_Q_START 0
130#define TWE_MAX_RESET_TRIES 3
131#define TWE_UNIT_INFORMATION_TABLE_BASE 0x300
132#define TWE_BLOCK_SIZE 0x200 /* 512-byte blocks */
133#define TWE_SECTOR_SIZE 0x200 /* generic I/O bufffer */
134#define TWE_IOCTL 0x80
135#define TWE_MAX_AEN_TRIES 100
136
137/* wrappers for bus-space actions */
138#define TWE_CONTROL(sc, val) bus_space_write_4(sc->twe_btag, sc->twe_bhandle, 0x0, (u_int32_t)val)
139#define TWE_STATUS(sc) (u_int32_t)bus_space_read_4(sc->twe_btag, sc->twe_bhandle, 0x4)
140#define TWE_COMMAND_QUEUE(sc, val) bus_space_write_4(sc->twe_btag, sc->twe_bhandle, 0x8, (u_int32_t)val)
141#define TWE_RESPONSE_QUEUE(sc) (TWE_Response_Queue)bus_space_read_4(sc->twe_btag, sc->twe_bhandle, 0xc)
142
143/* scatter/gather list entry */
144typedef struct
145{
146 u_int32_t address;
147 u_int32_t length;
148} TWE_SG_Entry __attribute__ ((packed));
149
150/* command packet - must be TWE_ALIGNMENT aligned */
151typedef struct
152{
153 u_int8_t opcode:5;
154 u_int8_t sgl_offset:3;
155 u_int8_t size;
156 u_int8_t request_id;
157 u_int8_t unit:4;
158 u_int8_t host_id:4;
159 u_int8_t status;
160 u_int8_t flags;
161 u_int16_t count; /* block count, parameter count, message credits */
162 union {
163 struct {
164 u_int32_t lba;
165 TWE_SG_Entry sgl[TWE_MAX_SGL_LENGTH];
166 } io __attribute__ ((packed));
167 struct {
168 TWE_SG_Entry sgl[TWE_MAX_SGL_LENGTH];
169 } param;
170 struct {
171 u_int32_t response_queue_pointer;
172 } init_connection;
173 } args;
174} TWE_Command __attribute__ ((packed));
175
176/* argument to TWE_OP_GET/SET_PARAM */
177typedef struct
178{
179 u_int16_t table_id;
180 u_int8_t parameter_id;
181 u_int8_t parameter_size_bytes;
182 u_int8_t data[1];
183} TWE_Param __attribute__ ((packed));
184
185/* response queue entry */
186typedef union
187{
188 struct
189 {
190 u_int32_t undefined_1:4;
191 u_int32_t response_id:8;
192 u_int32_t undefined_2:20;
193 } u;
194 u_int32_t value;
195} TWE_Response_Queue;
196
197#if 0 /* no idea what these will be useful for yet */
198typedef struct
199{
200 int32_t buffer;
201 u_int8_t opcode;
202 u_int16_t table_id;
203 u_int8_t parameter_id;
204 u_int8_t parameter_size_bytes;
205 u_int8_t data[1];
206} TWE_Ioctl __attribute__ ((packed));
207
208typedef struct
209{
210 u_int32_t base_addr;
211 u_int32_t control_reg_addr;
212 u_int32_t status_reg_addr;
213 u_int32_t command_que_addr;
214 u_int32_t response_que_addr;
215} TWE_Registers __attribute__ ((packed));
216
217typedef struct
218{
219 char *buffer;
220 int32_t length;
221 int32_t offset;
222 int32_t position;
223} TWE_Info __attribute__ ((packed));
224#endif
225
226
2 * Copyright (c) 2000 Michael Smith
3 * Copyright (c) 2000 BSDi
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
--- 10 unchanged lines hidden (view full) ---
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 * $FreeBSD: head/sys/dev/twe/twereg.h 66992 2000-10-12 01:43:40Z msmith $
28 */
29
30/*
31 * Register names, bit definitions, structure names and members are
32 * identical with those in the Linux driver where possible and sane
33 * for simplicity's sake. (The TW_ prefix has become TWE_)
34 * Some defines that are clearly irrelevant to FreeBSD have been
35 * removed.
--- 35 unchanged lines hidden (view full) ---
71#define TWE_STATUS_RESPONSE_QUEUE_EMPTY 0x00004000
72#define TWE_STATUS_MICROCONTROLLER_READY 0x00002000
73#define TWE_STATUS_COMMAND_QUEUE_EMPTY 0x00001000
74#define TWE_STATUS_ALL_INTERRUPTS 0x000F0000
75#define TWE_STATUS_CLEARABLE_BITS 0x00D00000
76#define TWE_STATUS_EXPECTED_BITS 0x00002000
77#define TWE_STATUS_UNEXPECTED_BITS 0x00F80000
78
79/* for use with the %b printf format */
80#define TWE_STATUS_BITS_DESCRIPTION \
81 "\20\15CQEMPTY\16UCREADY\17RQEMPTY\20CQFULL\21RINTR\22CINTR\23AINTR\24HINTR\25PCIABRT\26MCERR\27QERR\30PCIPERR\n"
82
83/* detect inconsistencies in the status register */
84#define TWE_STATUS_ERRORS(x) \
85 (((x & TWE_STATUS_PCI_ABORT) || \
86 (x & TWE_STATUS_PCI_PARITY_ERROR) || \
--- 6 unchanged lines hidden (view full) ---
93
94/* PCI related defines */
95#define TWE_IO_CONFIG_REG 0x10
96#define TWE_DEVICE_NAME "3ware Storage Controller"
97#define TWE_VENDOR_ID 0x13C1
98#define TWE_DEVICE_ID 0x1000
99
100/* command packet opcodes */
101#define TWE_OP_NOP 0x0
102#define TWE_OP_INIT_CONNECTION 0x1
103#define TWE_OP_READ 0x2
104#define TWE_OP_WRITE 0x3
105#define TWE_OP_VERIFY 0x4
106#define TWE_OP_GET_PARAM 0x12
107#define TWE_OP_SET_PARAM 0x13
108#define TWE_OP_SECTOR_INFO 0x1a
109#define TWE_OP_AEN_LISTEN 0x1c
110
111/* asynchronous event notification (AEN) codes */
112#define TWE_AEN_QUEUE_EMPTY 0x0000
113#define TWE_AEN_SOFT_RESET 0x0001
114#define TWE_AEN_DEGRADED_MIRROR 0x0002
115#define TWE_AEN_CONTROLLER_ERROR 0x0003
116#define TWE_AEN_REBUILD_FAIL 0x0004
117#define TWE_AEN_REBUILD_DONE 0x0005
118#define TWE_AEN_QUEUE_FULL 0x00ff
119#define TWE_AEN_TABLE_UNDEFINED 0x15
120
121/* misc defines */
122#define TWE_ALIGNMENT 0x200
123#define TWE_MAX_UNITS 16
124#define TWE_COMMAND_ALIGNMENT_MASK 0x1ff
125#define TWE_INIT_MESSAGE_CREDITS 0x100
126#define TWE_INIT_COMMAND_PACKET_SIZE 0x3
127#define TWE_MAX_SGL_LENGTH 62
128#define TWE_Q_LENGTH 50
129#define TWE_Q_START 0
130#define TWE_MAX_RESET_TRIES 3
131#define TWE_UNIT_INFORMATION_TABLE_BASE 0x300
132#define TWE_BLOCK_SIZE 0x200 /* 512-byte blocks */
133#define TWE_SECTOR_SIZE 0x200 /* generic I/O bufffer */
134#define TWE_IOCTL 0x80
135#define TWE_MAX_AEN_TRIES 100
136
137/* wrappers for bus-space actions */
138#define TWE_CONTROL(sc, val) bus_space_write_4(sc->twe_btag, sc->twe_bhandle, 0x0, (u_int32_t)val)
139#define TWE_STATUS(sc) (u_int32_t)bus_space_read_4(sc->twe_btag, sc->twe_bhandle, 0x4)
140#define TWE_COMMAND_QUEUE(sc, val) bus_space_write_4(sc->twe_btag, sc->twe_bhandle, 0x8, (u_int32_t)val)
141#define TWE_RESPONSE_QUEUE(sc) (TWE_Response_Queue)bus_space_read_4(sc->twe_btag, sc->twe_bhandle, 0xc)
142
143/* scatter/gather list entry */
144typedef struct
145{
146 u_int32_t address;
147 u_int32_t length;
148} TWE_SG_Entry __attribute__ ((packed));
149
150/* command packet - must be TWE_ALIGNMENT aligned */
151typedef struct
152{
153 u_int8_t opcode:5;
154 u_int8_t sgl_offset:3;
155 u_int8_t size;
156 u_int8_t request_id;
157 u_int8_t unit:4;
158 u_int8_t host_id:4;
159 u_int8_t status;
160 u_int8_t flags;
161 u_int16_t count; /* block count, parameter count, message credits */
162 union {
163 struct {
164 u_int32_t lba;
165 TWE_SG_Entry sgl[TWE_MAX_SGL_LENGTH];
166 } io __attribute__ ((packed));
167 struct {
168 TWE_SG_Entry sgl[TWE_MAX_SGL_LENGTH];
169 } param;
170 struct {
171 u_int32_t response_queue_pointer;
172 } init_connection;
173 } args;
174} TWE_Command __attribute__ ((packed));
175
176/* argument to TWE_OP_GET/SET_PARAM */
177typedef struct
178{
179 u_int16_t table_id;
180 u_int8_t parameter_id;
181 u_int8_t parameter_size_bytes;
182 u_int8_t data[1];
183} TWE_Param __attribute__ ((packed));
184
185/* response queue entry */
186typedef union
187{
188 struct
189 {
190 u_int32_t undefined_1:4;
191 u_int32_t response_id:8;
192 u_int32_t undefined_2:20;
193 } u;
194 u_int32_t value;
195} TWE_Response_Queue;
196
197#if 0 /* no idea what these will be useful for yet */
198typedef struct
199{
200 int32_t buffer;
201 u_int8_t opcode;
202 u_int16_t table_id;
203 u_int8_t parameter_id;
204 u_int8_t parameter_size_bytes;
205 u_int8_t data[1];
206} TWE_Ioctl __attribute__ ((packed));
207
208typedef struct
209{
210 u_int32_t base_addr;
211 u_int32_t control_reg_addr;
212 u_int32_t status_reg_addr;
213 u_int32_t command_que_addr;
214 u_int32_t response_que_addr;
215} TWE_Registers __attribute__ ((packed));
216
217typedef struct
218{
219 char *buffer;
220 int32_t length;
221 int32_t offset;
222 int32_t position;
223} TWE_Info __attribute__ ((packed));
224#endif
225
226