30 */ 31 32/* 33 * FreeBSD-specific code. 34 */ 35 36#include <dev/twe/twe_compat.h> 37#include <dev/twe/twereg.h> 38#include <dev/twe/tweio.h> 39#include <dev/twe/twevar.h> 40#include <dev/twe/twe_tables.h> 41 42#include <vm/vm.h> 43 44static devclass_t twe_devclass; 45 46#ifdef TWE_DEBUG 47static u_int32_t twed_bio_in; 48#define TWED_BIO_IN twed_bio_in++ 49static u_int32_t twed_bio_out; 50#define TWED_BIO_OUT twed_bio_out++ 51#else 52#define TWED_BIO_IN 53#define TWED_BIO_OUT 54#endif 55 56static void twe_setup_data_dmamap(void *arg, bus_dma_segment_t *segs, int nsegments, int error); 57static void twe_setup_request_dmamap(void *arg, bus_dma_segment_t *segs, int nsegments, int error); 58 59/******************************************************************************** 60 ******************************************************************************** 61 Control device interface 62 ******************************************************************************** 63 ********************************************************************************/ 64 65static d_open_t twe_open; 66static d_close_t twe_close; 67static d_ioctl_t twe_ioctl_wrapper; 68 69static struct cdevsw twe_cdevsw = { 70 .d_open = twe_open, 71 .d_close = twe_close, 72 .d_ioctl = twe_ioctl_wrapper, 73 .d_name = "twe", 74 .d_maj = TWE_CDEV_MAJOR, 75}; 76 77/******************************************************************************** 78 * Accept an open operation on the control device. 79 */ 80static int 81twe_open(dev_t dev, int flags, int fmt, d_thread_t *td) 82{ 83 int unit = minor(dev); 84 struct twe_softc *sc = devclass_get_softc(twe_devclass, unit); 85 86 sc->twe_state |= TWE_STATE_OPEN; 87 return(0); 88} 89 90/******************************************************************************** 91 * Accept the last close on the control device. 92 */ 93static int 94twe_close(dev_t dev, int flags, int fmt, d_thread_t *td) 95{ 96 int unit = minor(dev); 97 struct twe_softc *sc = devclass_get_softc(twe_devclass, unit); 98 99 sc->twe_state &= ~TWE_STATE_OPEN; 100 return (0); 101} 102 103/******************************************************************************** 104 * Handle controller-specific control operations. 105 */ 106static int 107twe_ioctl_wrapper(dev_t dev, u_long cmd, caddr_t addr, int32_t flag, d_thread_t *td) 108{ 109 struct twe_softc *sc = (struct twe_softc *)dev->si_drv1; 110 111 return(twe_ioctl(sc, cmd, addr)); 112} 113 114/******************************************************************************** 115 ******************************************************************************** 116 PCI device interface 117 ******************************************************************************** 118 ********************************************************************************/ 119 120static int twe_probe(device_t dev); 121static int twe_attach(device_t dev); 122static void twe_free(struct twe_softc *sc); 123static int twe_detach(device_t dev); 124static int twe_shutdown(device_t dev); 125static int twe_suspend(device_t dev); 126static int twe_resume(device_t dev); 127static void twe_pci_intr(void *arg); 128static void twe_intrhook(void *arg); 129 130static device_method_t twe_methods[] = { 131 /* Device interface */ 132 DEVMETHOD(device_probe, twe_probe), 133 DEVMETHOD(device_attach, twe_attach), 134 DEVMETHOD(device_detach, twe_detach), 135 DEVMETHOD(device_shutdown, twe_shutdown), 136 DEVMETHOD(device_suspend, twe_suspend), 137 DEVMETHOD(device_resume, twe_resume), 138 139 DEVMETHOD(bus_print_child, bus_generic_print_child), 140 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 141 { 0, 0 } 142}; 143 144static driver_t twe_pci_driver = { 145 "twe", 146 twe_methods, 147 sizeof(struct twe_softc) 148}; 149 150DRIVER_MODULE(twe, pci, twe_pci_driver, twe_devclass, 0, 0); 151 152/******************************************************************************** 153 * Match a 3ware Escalade ATA RAID controller. 154 */ 155static int 156twe_probe(device_t dev) 157{ 158 159 debug_called(4); 160 161 if ((pci_get_vendor(dev) == TWE_VENDOR_ID) && 162 ((pci_get_device(dev) == TWE_DEVICE_ID) || 163 (pci_get_device(dev) == TWE_DEVICE_ID_ASIC))) { 164 device_set_desc_copy(dev, TWE_DEVICE_NAME ". Driver version " TWE_DRIVER_VERSION_STRING); 165 return(0); 166 } 167 return(ENXIO); 168} 169 170/******************************************************************************** 171 * Allocate resources, initialise the controller. 172 */ 173static int 174twe_attach(device_t dev) 175{ 176 struct twe_softc *sc; 177 int rid, error; 178 u_int32_t command; 179 180 debug_called(4); 181 182 /* 183 * Initialise the softc structure. 184 */ 185 sc = device_get_softc(dev); 186 sc->twe_dev = dev; 187 188 sysctl_ctx_init(&sc->sysctl_ctx); 189 sc->sysctl_tree = SYSCTL_ADD_NODE(&sc->sysctl_ctx, 190 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO, 191 device_get_nameunit(dev), CTLFLAG_RD, 0, ""); 192 if (sc->sysctl_tree == NULL) { 193 twe_printf(sc, "cannot add sysctl tree node\n"); 194 return (ENXIO); 195 } 196 SYSCTL_ADD_STRING(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 197 OID_AUTO, "driver_version", CTLFLAG_RD, TWE_DRIVER_VERSION_STRING, 0, 198 "TWE driver version"); 199 200 /* 201 * Make sure we are going to be able to talk to this board. 202 */ 203 command = pci_read_config(dev, PCIR_COMMAND, 2); 204 if ((command & PCIM_CMD_PORTEN) == 0) { 205 twe_printf(sc, "register window not available\n"); 206 return(ENXIO); 207 } 208 /* 209 * Force the busmaster enable bit on, in case the BIOS forgot. 210 */ 211 command |= PCIM_CMD_BUSMASTEREN; 212 pci_write_config(dev, PCIR_COMMAND, command, 2); 213 214 /* 215 * Allocate the PCI register window. 216 */ 217 rid = TWE_IO_CONFIG_REG; 218 if ((sc->twe_io = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, 0, ~0, 1, RF_ACTIVE)) == NULL) { 219 twe_printf(sc, "can't allocate register window\n"); 220 twe_free(sc); 221 return(ENXIO); 222 } 223 sc->twe_btag = rman_get_bustag(sc->twe_io); 224 sc->twe_bhandle = rman_get_bushandle(sc->twe_io); 225 226 /* 227 * Allocate the parent bus DMA tag appropriate for PCI. 228 */ 229 if (bus_dma_tag_create(NULL, /* parent */ 230 1, 0, /* alignment, boundary */ 231 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 232 BUS_SPACE_MAXADDR, /* highaddr */ 233 NULL, NULL, /* filter, filterarg */ 234 MAXBSIZE, TWE_MAX_SGL_LENGTH, /* maxsize, nsegments */ 235 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 236 BUS_DMA_ALLOCNOW, /* flags */ 237 NULL, /* lockfunc */ 238 NULL, /* lockarg */ 239 &sc->twe_parent_dmat)) { 240 twe_printf(sc, "can't allocate parent DMA tag\n"); 241 twe_free(sc); 242 return(ENOMEM); 243 } 244 245 /* 246 * Allocate and connect our interrupt. 247 */ 248 rid = 0; 249 if ((sc->twe_irq = bus_alloc_resource(sc->twe_dev, SYS_RES_IRQ, &rid, 0, ~0, 1, RF_SHAREABLE | RF_ACTIVE)) == NULL) { 250 twe_printf(sc, "can't allocate interrupt\n"); 251 twe_free(sc); 252 return(ENXIO); 253 } 254 if (bus_setup_intr(sc->twe_dev, sc->twe_irq, INTR_TYPE_BIO | INTR_ENTROPY, twe_pci_intr, sc, &sc->twe_intr)) { 255 twe_printf(sc, "can't set up interrupt\n"); 256 twe_free(sc); 257 return(ENXIO); 258 } 259 260 /* 261 * Create DMA tag for mapping command's into controller-addressable space. 262 */ 263 if (bus_dma_tag_create(sc->twe_parent_dmat, /* parent */ 264 1, 0, /* alignment, boundary */ 265 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 266 BUS_SPACE_MAXADDR, /* highaddr */ 267 NULL, NULL, /* filter, filterarg */ 268 sizeof(TWE_Command) * 269 TWE_Q_LENGTH, 1, /* maxsize, nsegments */ 270 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 271 BUS_DMA_ALLOCNOW, /* flags */ 272 NULL, /* lockfunc */ 273 NULL, /* lockarg */ 274 &sc->twe_cmd_dmat)) { 275 twe_printf(sc, "can't allocate data buffer DMA tag\n"); 276 twe_free(sc); 277 return(ENOMEM); 278 } 279 /* 280 * Allocate memory and make it available for DMA. 281 */ 282 if (bus_dmamem_alloc(sc->twe_cmd_dmat, (void **)&sc->twe_cmd, 283 BUS_DMA_NOWAIT, &sc->twe_cmdmap)) { 284 twe_printf(sc, "can't allocate command memory\n"); 285 return(ENOMEM); 286 } 287 bus_dmamap_load(sc->twe_cmd_dmat, sc->twe_cmdmap, sc->twe_cmd, 288 sizeof(TWE_Command) * TWE_Q_LENGTH, 289 twe_setup_request_dmamap, sc, 0); 290 bzero(sc->twe_cmd, sizeof(TWE_Command) * TWE_Q_LENGTH); 291 292 /* 293 * Create DMA tag for mapping objects into controller-addressable space. 294 */ 295 if (bus_dma_tag_create(sc->twe_parent_dmat, /* parent */ 296 1, 0, /* alignment, boundary */ 297 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 298 BUS_SPACE_MAXADDR, /* highaddr */ 299 NULL, NULL, /* filter, filterarg */ 300 MAXBSIZE, TWE_MAX_SGL_LENGTH,/* maxsize, nsegments */ 301 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 302 0, /* flags */ 303 busdma_lock_mutex, /* lockfunc */ 304 &Giant, /* lockarg */ 305 &sc->twe_buffer_dmat)) { 306 twe_printf(sc, "can't allocate data buffer DMA tag\n"); 307 twe_free(sc); 308 return(ENOMEM); 309 } 310 311 /* 312 * Create DMA tag for mapping objects into controller-addressable space. 313 */ 314 if (bus_dma_tag_create(sc->twe_parent_dmat, /* parent */ 315 1, 0, /* alignment, boundary */ 316 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 317 BUS_SPACE_MAXADDR, /* highaddr */ 318 NULL, NULL, /* filter, filterarg */ 319 MAXBSIZE, 1, /* maxsize, nsegments */ 320 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 321 BUS_DMA_ALLOCNOW, /* flags */ 322 NULL, /* lockfunc */ 323 NULL, /* lockarg */ 324 &sc->twe_immediate_dmat)) { 325 twe_printf(sc, "can't allocate data buffer DMA tag\n"); 326 twe_free(sc); 327 return(ENOMEM); 328 } 329 /* 330 * Allocate memory for requests which cannot sleep or support continuation. 331 */ 332 if (bus_dmamem_alloc(sc->twe_immediate_dmat, (void **)&sc->twe_immediate, 333 BUS_DMA_NOWAIT, &sc->twe_immediate_map)) { 334 twe_printf(sc, "can't allocate memory for immediate requests\n"); 335 return(ENOMEM); 336 } 337 338 /* 339 * Initialise the controller and driver core. 340 */ 341 if ((error = twe_setup(sc))) { 342 twe_free(sc); 343 return(error); 344 } 345 346 /* 347 * Print some information about the controller and configuration. 348 */ 349 twe_describe_controller(sc); 350 351 /* 352 * Create the control device. 353 */ 354 sc->twe_dev_t = make_dev(&twe_cdevsw, device_get_unit(sc->twe_dev), UID_ROOT, GID_OPERATOR, 355 S_IRUSR | S_IWUSR, "twe%d", device_get_unit(sc->twe_dev)); 356 sc->twe_dev_t->si_drv1 = sc; 357 /* 358 * Schedule ourselves to bring the controller up once interrupts are available. 359 * This isn't strictly necessary, since we disable interrupts while probing the 360 * controller, but it is more in keeping with common practice for other disk 361 * devices. 362 */ 363 sc->twe_ich.ich_func = twe_intrhook; 364 sc->twe_ich.ich_arg = sc; 365 if (config_intrhook_establish(&sc->twe_ich) != 0) { 366 twe_printf(sc, "can't establish configuration hook\n"); 367 twe_free(sc); 368 return(ENXIO); 369 } 370 371 return(0); 372} 373 374/******************************************************************************** 375 * Free all of the resources associated with (sc). 376 * 377 * Should not be called if the controller is active. 378 */ 379static void 380twe_free(struct twe_softc *sc) 381{ 382 struct twe_request *tr; 383 384 debug_called(4); 385 386 /* throw away any command buffers */ 387 while ((tr = twe_dequeue_free(sc)) != NULL) 388 twe_free_request(tr); 389 390 if (sc->twe_cmd != NULL) { 391 bus_dmamap_unload(sc->twe_cmd_dmat, sc->twe_cmdmap); 392 bus_dmamem_free(sc->twe_cmd_dmat, sc->twe_cmd, sc->twe_cmdmap); 393 } 394 395 if (sc->twe_immediate != NULL) { 396 bus_dmamap_unload(sc->twe_immediate_dmat, sc->twe_immediate_map); 397 bus_dmamem_free(sc->twe_immediate_dmat, sc->twe_immediate, 398 sc->twe_immediate_map); 399 } 400 401 if (sc->twe_immediate_dmat) 402 bus_dma_tag_destroy(sc->twe_immediate_dmat); 403 404 /* destroy the data-transfer DMA tag */ 405 if (sc->twe_buffer_dmat) 406 bus_dma_tag_destroy(sc->twe_buffer_dmat); 407 408 /* disconnect the interrupt handler */ 409 if (sc->twe_intr) 410 bus_teardown_intr(sc->twe_dev, sc->twe_irq, sc->twe_intr); 411 if (sc->twe_irq != NULL) 412 bus_release_resource(sc->twe_dev, SYS_RES_IRQ, 0, sc->twe_irq); 413 414 /* destroy the parent DMA tag */ 415 if (sc->twe_parent_dmat) 416 bus_dma_tag_destroy(sc->twe_parent_dmat); 417 418 /* release the register window mapping */ 419 if (sc->twe_io != NULL) 420 bus_release_resource(sc->twe_dev, SYS_RES_IOPORT, TWE_IO_CONFIG_REG, sc->twe_io); 421 422 /* destroy control device */ 423 if (sc->twe_dev_t != (dev_t)NULL) 424 destroy_dev(sc->twe_dev_t); 425 426 sysctl_ctx_free(&sc->sysctl_ctx); 427} 428 429/******************************************************************************** 430 * Disconnect from the controller completely, in preparation for unload. 431 */ 432static int 433twe_detach(device_t dev) 434{ 435 struct twe_softc *sc = device_get_softc(dev); 436 int s, error; 437 438 debug_called(4); 439 440 error = EBUSY; 441 s = splbio(); 442 if (sc->twe_state & TWE_STATE_OPEN) 443 goto out; 444 445 /* 446 * Shut the controller down. 447 */ 448 if (twe_shutdown(dev)) 449 goto out; 450 451 twe_free(sc); 452 453 error = 0; 454 out: 455 splx(s); 456 return(error); 457} 458 459/******************************************************************************** 460 * Bring the controller down to a dormant state and detach all child devices. 461 * 462 * Note that we can assume that the bioq on the controller is empty, as we won't 463 * allow shutdown if any device is open. 464 */ 465static int 466twe_shutdown(device_t dev) 467{ 468 struct twe_softc *sc = device_get_softc(dev); 469 int i, s, error = 0; 470 471 debug_called(4); 472 473 s = splbio(); 474 475 /* 476 * Delete all our child devices. 477 */ 478 for (i = 0; i < TWE_MAX_UNITS; i++) { 479 if (sc->twe_drive[i].td_disk != 0) { 480 if ((error = twe_detach_drive(sc, i)) != 0) 481 goto out; 482 } 483 } 484 485 /* 486 * Bring the controller down. 487 */ 488 twe_deinit(sc); 489 490out: 491 splx(s); 492 return(error); 493} 494 495/******************************************************************************** 496 * Bring the controller to a quiescent state, ready for system suspend. 497 */ 498static int 499twe_suspend(device_t dev) 500{ 501 struct twe_softc *sc = device_get_softc(dev); 502 int s; 503 504 debug_called(4); 505 506 s = splbio(); 507 sc->twe_state |= TWE_STATE_SUSPEND; 508 509 twe_disable_interrupts(sc); 510 splx(s); 511 512 return(0); 513} 514 515/******************************************************************************** 516 * Bring the controller back to a state ready for operation. 517 */ 518static int 519twe_resume(device_t dev) 520{ 521 struct twe_softc *sc = device_get_softc(dev); 522 523 debug_called(4); 524 525 sc->twe_state &= ~TWE_STATE_SUSPEND; 526 twe_enable_interrupts(sc); 527 528 return(0); 529} 530 531/******************************************************************************* 532 * Take an interrupt, or be poked by other code to look for interrupt-worthy 533 * status. 534 */ 535static void 536twe_pci_intr(void *arg) 537{ 538 twe_intr((struct twe_softc *)arg); 539} 540 541/******************************************************************************** 542 * Delayed-startup hook 543 */ 544static void 545twe_intrhook(void *arg) 546{ 547 struct twe_softc *sc = (struct twe_softc *)arg; 548 549 /* pull ourselves off the intrhook chain */ 550 config_intrhook_disestablish(&sc->twe_ich); 551 552 /* call core startup routine */ 553 twe_init(sc); 554} 555 556/******************************************************************************** 557 * Given a detected drive, attach it to the bio interface. 558 * 559 * This is called from twe_add_unit. 560 */ 561int 562twe_attach_drive(struct twe_softc *sc, struct twe_drive *dr) 563{ 564 char buf[80]; 565 int error; 566 567 dr->td_disk = device_add_child(sc->twe_dev, NULL, -1); 568 if (dr->td_disk == NULL) { 569 twe_printf(sc, "Cannot add unit\n"); 570 return (EIO); 571 } 572 device_set_ivars(dr->td_disk, dr); 573 574 /* 575 * XXX It would make sense to test the online/initialising bits, but they seem to be 576 * always set... 577 */ 578 sprintf(buf, "Unit %d, %s, %s", 579 dr->td_twe_unit, 580 twe_describe_code(twe_table_unittype, dr->td_type), 581 twe_describe_code(twe_table_unitstate, dr->td_state & TWE_PARAM_UNITSTATUS_MASK)); 582 device_set_desc_copy(dr->td_disk, buf); 583 584 if ((error = bus_generic_attach(sc->twe_dev)) != 0) { 585 twe_printf(sc, "Cannot attach unit to controller. error = %d\n", error); 586 return (EIO); 587 } 588 return (0); 589} 590 591/******************************************************************************** 592 * Detach the specified unit if it exsists 593 * 594 * This is called from twe_del_unit. 595 */ 596int 597twe_detach_drive(struct twe_softc *sc, int unit) 598{ 599 int error = 0; 600 601 if ((error = device_delete_child(sc->twe_dev, sc->twe_drive[unit].td_disk)) != 0) { 602 twe_printf(sc, "failed to delete unit %d\n", unit); 603 return(error); 604 } 605 bzero(&sc->twe_drive[unit], sizeof(sc->twe_drive[unit])); 606 return(error); 607} 608 609/******************************************************************************** 610 * Clear a PCI parity error. 611 */ 612void 613twe_clear_pci_parity_error(struct twe_softc *sc) 614{ 615 TWE_CONTROL(sc, TWE_CONTROL_CLEAR_PARITY_ERROR); 616 pci_write_config(sc->twe_dev, PCIR_STATUS, TWE_PCI_CLEAR_PARITY_ERROR, 2); 617} 618 619/******************************************************************************** 620 * Clear a PCI abort. 621 */ 622void 623twe_clear_pci_abort(struct twe_softc *sc) 624{ 625 TWE_CONTROL(sc, TWE_CONTROL_CLEAR_PCI_ABORT); 626 pci_write_config(sc->twe_dev, PCIR_STATUS, TWE_PCI_CLEAR_PCI_ABORT, 2); 627} 628 629/******************************************************************************** 630 ******************************************************************************** 631 Disk device 632 ******************************************************************************** 633 ********************************************************************************/ 634 635/* 636 * Disk device softc 637 */ 638struct twed_softc 639{ 640 device_t twed_dev; 641 struct twe_softc *twed_controller; /* parent device softc */ 642 struct twe_drive *twed_drive; /* drive data in parent softc */
| 30 */ 31 32/* 33 * FreeBSD-specific code. 34 */ 35 36#include <dev/twe/twe_compat.h> 37#include <dev/twe/twereg.h> 38#include <dev/twe/tweio.h> 39#include <dev/twe/twevar.h> 40#include <dev/twe/twe_tables.h> 41 42#include <vm/vm.h> 43 44static devclass_t twe_devclass; 45 46#ifdef TWE_DEBUG 47static u_int32_t twed_bio_in; 48#define TWED_BIO_IN twed_bio_in++ 49static u_int32_t twed_bio_out; 50#define TWED_BIO_OUT twed_bio_out++ 51#else 52#define TWED_BIO_IN 53#define TWED_BIO_OUT 54#endif 55 56static void twe_setup_data_dmamap(void *arg, bus_dma_segment_t *segs, int nsegments, int error); 57static void twe_setup_request_dmamap(void *arg, bus_dma_segment_t *segs, int nsegments, int error); 58 59/******************************************************************************** 60 ******************************************************************************** 61 Control device interface 62 ******************************************************************************** 63 ********************************************************************************/ 64 65static d_open_t twe_open; 66static d_close_t twe_close; 67static d_ioctl_t twe_ioctl_wrapper; 68 69static struct cdevsw twe_cdevsw = { 70 .d_open = twe_open, 71 .d_close = twe_close, 72 .d_ioctl = twe_ioctl_wrapper, 73 .d_name = "twe", 74 .d_maj = TWE_CDEV_MAJOR, 75}; 76 77/******************************************************************************** 78 * Accept an open operation on the control device. 79 */ 80static int 81twe_open(dev_t dev, int flags, int fmt, d_thread_t *td) 82{ 83 int unit = minor(dev); 84 struct twe_softc *sc = devclass_get_softc(twe_devclass, unit); 85 86 sc->twe_state |= TWE_STATE_OPEN; 87 return(0); 88} 89 90/******************************************************************************** 91 * Accept the last close on the control device. 92 */ 93static int 94twe_close(dev_t dev, int flags, int fmt, d_thread_t *td) 95{ 96 int unit = minor(dev); 97 struct twe_softc *sc = devclass_get_softc(twe_devclass, unit); 98 99 sc->twe_state &= ~TWE_STATE_OPEN; 100 return (0); 101} 102 103/******************************************************************************** 104 * Handle controller-specific control operations. 105 */ 106static int 107twe_ioctl_wrapper(dev_t dev, u_long cmd, caddr_t addr, int32_t flag, d_thread_t *td) 108{ 109 struct twe_softc *sc = (struct twe_softc *)dev->si_drv1; 110 111 return(twe_ioctl(sc, cmd, addr)); 112} 113 114/******************************************************************************** 115 ******************************************************************************** 116 PCI device interface 117 ******************************************************************************** 118 ********************************************************************************/ 119 120static int twe_probe(device_t dev); 121static int twe_attach(device_t dev); 122static void twe_free(struct twe_softc *sc); 123static int twe_detach(device_t dev); 124static int twe_shutdown(device_t dev); 125static int twe_suspend(device_t dev); 126static int twe_resume(device_t dev); 127static void twe_pci_intr(void *arg); 128static void twe_intrhook(void *arg); 129 130static device_method_t twe_methods[] = { 131 /* Device interface */ 132 DEVMETHOD(device_probe, twe_probe), 133 DEVMETHOD(device_attach, twe_attach), 134 DEVMETHOD(device_detach, twe_detach), 135 DEVMETHOD(device_shutdown, twe_shutdown), 136 DEVMETHOD(device_suspend, twe_suspend), 137 DEVMETHOD(device_resume, twe_resume), 138 139 DEVMETHOD(bus_print_child, bus_generic_print_child), 140 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 141 { 0, 0 } 142}; 143 144static driver_t twe_pci_driver = { 145 "twe", 146 twe_methods, 147 sizeof(struct twe_softc) 148}; 149 150DRIVER_MODULE(twe, pci, twe_pci_driver, twe_devclass, 0, 0); 151 152/******************************************************************************** 153 * Match a 3ware Escalade ATA RAID controller. 154 */ 155static int 156twe_probe(device_t dev) 157{ 158 159 debug_called(4); 160 161 if ((pci_get_vendor(dev) == TWE_VENDOR_ID) && 162 ((pci_get_device(dev) == TWE_DEVICE_ID) || 163 (pci_get_device(dev) == TWE_DEVICE_ID_ASIC))) { 164 device_set_desc_copy(dev, TWE_DEVICE_NAME ". Driver version " TWE_DRIVER_VERSION_STRING); 165 return(0); 166 } 167 return(ENXIO); 168} 169 170/******************************************************************************** 171 * Allocate resources, initialise the controller. 172 */ 173static int 174twe_attach(device_t dev) 175{ 176 struct twe_softc *sc; 177 int rid, error; 178 u_int32_t command; 179 180 debug_called(4); 181 182 /* 183 * Initialise the softc structure. 184 */ 185 sc = device_get_softc(dev); 186 sc->twe_dev = dev; 187 188 sysctl_ctx_init(&sc->sysctl_ctx); 189 sc->sysctl_tree = SYSCTL_ADD_NODE(&sc->sysctl_ctx, 190 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO, 191 device_get_nameunit(dev), CTLFLAG_RD, 0, ""); 192 if (sc->sysctl_tree == NULL) { 193 twe_printf(sc, "cannot add sysctl tree node\n"); 194 return (ENXIO); 195 } 196 SYSCTL_ADD_STRING(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 197 OID_AUTO, "driver_version", CTLFLAG_RD, TWE_DRIVER_VERSION_STRING, 0, 198 "TWE driver version"); 199 200 /* 201 * Make sure we are going to be able to talk to this board. 202 */ 203 command = pci_read_config(dev, PCIR_COMMAND, 2); 204 if ((command & PCIM_CMD_PORTEN) == 0) { 205 twe_printf(sc, "register window not available\n"); 206 return(ENXIO); 207 } 208 /* 209 * Force the busmaster enable bit on, in case the BIOS forgot. 210 */ 211 command |= PCIM_CMD_BUSMASTEREN; 212 pci_write_config(dev, PCIR_COMMAND, command, 2); 213 214 /* 215 * Allocate the PCI register window. 216 */ 217 rid = TWE_IO_CONFIG_REG; 218 if ((sc->twe_io = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, 0, ~0, 1, RF_ACTIVE)) == NULL) { 219 twe_printf(sc, "can't allocate register window\n"); 220 twe_free(sc); 221 return(ENXIO); 222 } 223 sc->twe_btag = rman_get_bustag(sc->twe_io); 224 sc->twe_bhandle = rman_get_bushandle(sc->twe_io); 225 226 /* 227 * Allocate the parent bus DMA tag appropriate for PCI. 228 */ 229 if (bus_dma_tag_create(NULL, /* parent */ 230 1, 0, /* alignment, boundary */ 231 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 232 BUS_SPACE_MAXADDR, /* highaddr */ 233 NULL, NULL, /* filter, filterarg */ 234 MAXBSIZE, TWE_MAX_SGL_LENGTH, /* maxsize, nsegments */ 235 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 236 BUS_DMA_ALLOCNOW, /* flags */ 237 NULL, /* lockfunc */ 238 NULL, /* lockarg */ 239 &sc->twe_parent_dmat)) { 240 twe_printf(sc, "can't allocate parent DMA tag\n"); 241 twe_free(sc); 242 return(ENOMEM); 243 } 244 245 /* 246 * Allocate and connect our interrupt. 247 */ 248 rid = 0; 249 if ((sc->twe_irq = bus_alloc_resource(sc->twe_dev, SYS_RES_IRQ, &rid, 0, ~0, 1, RF_SHAREABLE | RF_ACTIVE)) == NULL) { 250 twe_printf(sc, "can't allocate interrupt\n"); 251 twe_free(sc); 252 return(ENXIO); 253 } 254 if (bus_setup_intr(sc->twe_dev, sc->twe_irq, INTR_TYPE_BIO | INTR_ENTROPY, twe_pci_intr, sc, &sc->twe_intr)) { 255 twe_printf(sc, "can't set up interrupt\n"); 256 twe_free(sc); 257 return(ENXIO); 258 } 259 260 /* 261 * Create DMA tag for mapping command's into controller-addressable space. 262 */ 263 if (bus_dma_tag_create(sc->twe_parent_dmat, /* parent */ 264 1, 0, /* alignment, boundary */ 265 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 266 BUS_SPACE_MAXADDR, /* highaddr */ 267 NULL, NULL, /* filter, filterarg */ 268 sizeof(TWE_Command) * 269 TWE_Q_LENGTH, 1, /* maxsize, nsegments */ 270 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 271 BUS_DMA_ALLOCNOW, /* flags */ 272 NULL, /* lockfunc */ 273 NULL, /* lockarg */ 274 &sc->twe_cmd_dmat)) { 275 twe_printf(sc, "can't allocate data buffer DMA tag\n"); 276 twe_free(sc); 277 return(ENOMEM); 278 } 279 /* 280 * Allocate memory and make it available for DMA. 281 */ 282 if (bus_dmamem_alloc(sc->twe_cmd_dmat, (void **)&sc->twe_cmd, 283 BUS_DMA_NOWAIT, &sc->twe_cmdmap)) { 284 twe_printf(sc, "can't allocate command memory\n"); 285 return(ENOMEM); 286 } 287 bus_dmamap_load(sc->twe_cmd_dmat, sc->twe_cmdmap, sc->twe_cmd, 288 sizeof(TWE_Command) * TWE_Q_LENGTH, 289 twe_setup_request_dmamap, sc, 0); 290 bzero(sc->twe_cmd, sizeof(TWE_Command) * TWE_Q_LENGTH); 291 292 /* 293 * Create DMA tag for mapping objects into controller-addressable space. 294 */ 295 if (bus_dma_tag_create(sc->twe_parent_dmat, /* parent */ 296 1, 0, /* alignment, boundary */ 297 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 298 BUS_SPACE_MAXADDR, /* highaddr */ 299 NULL, NULL, /* filter, filterarg */ 300 MAXBSIZE, TWE_MAX_SGL_LENGTH,/* maxsize, nsegments */ 301 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 302 0, /* flags */ 303 busdma_lock_mutex, /* lockfunc */ 304 &Giant, /* lockarg */ 305 &sc->twe_buffer_dmat)) { 306 twe_printf(sc, "can't allocate data buffer DMA tag\n"); 307 twe_free(sc); 308 return(ENOMEM); 309 } 310 311 /* 312 * Create DMA tag for mapping objects into controller-addressable space. 313 */ 314 if (bus_dma_tag_create(sc->twe_parent_dmat, /* parent */ 315 1, 0, /* alignment, boundary */ 316 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 317 BUS_SPACE_MAXADDR, /* highaddr */ 318 NULL, NULL, /* filter, filterarg */ 319 MAXBSIZE, 1, /* maxsize, nsegments */ 320 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 321 BUS_DMA_ALLOCNOW, /* flags */ 322 NULL, /* lockfunc */ 323 NULL, /* lockarg */ 324 &sc->twe_immediate_dmat)) { 325 twe_printf(sc, "can't allocate data buffer DMA tag\n"); 326 twe_free(sc); 327 return(ENOMEM); 328 } 329 /* 330 * Allocate memory for requests which cannot sleep or support continuation. 331 */ 332 if (bus_dmamem_alloc(sc->twe_immediate_dmat, (void **)&sc->twe_immediate, 333 BUS_DMA_NOWAIT, &sc->twe_immediate_map)) { 334 twe_printf(sc, "can't allocate memory for immediate requests\n"); 335 return(ENOMEM); 336 } 337 338 /* 339 * Initialise the controller and driver core. 340 */ 341 if ((error = twe_setup(sc))) { 342 twe_free(sc); 343 return(error); 344 } 345 346 /* 347 * Print some information about the controller and configuration. 348 */ 349 twe_describe_controller(sc); 350 351 /* 352 * Create the control device. 353 */ 354 sc->twe_dev_t = make_dev(&twe_cdevsw, device_get_unit(sc->twe_dev), UID_ROOT, GID_OPERATOR, 355 S_IRUSR | S_IWUSR, "twe%d", device_get_unit(sc->twe_dev)); 356 sc->twe_dev_t->si_drv1 = sc; 357 /* 358 * Schedule ourselves to bring the controller up once interrupts are available. 359 * This isn't strictly necessary, since we disable interrupts while probing the 360 * controller, but it is more in keeping with common practice for other disk 361 * devices. 362 */ 363 sc->twe_ich.ich_func = twe_intrhook; 364 sc->twe_ich.ich_arg = sc; 365 if (config_intrhook_establish(&sc->twe_ich) != 0) { 366 twe_printf(sc, "can't establish configuration hook\n"); 367 twe_free(sc); 368 return(ENXIO); 369 } 370 371 return(0); 372} 373 374/******************************************************************************** 375 * Free all of the resources associated with (sc). 376 * 377 * Should not be called if the controller is active. 378 */ 379static void 380twe_free(struct twe_softc *sc) 381{ 382 struct twe_request *tr; 383 384 debug_called(4); 385 386 /* throw away any command buffers */ 387 while ((tr = twe_dequeue_free(sc)) != NULL) 388 twe_free_request(tr); 389 390 if (sc->twe_cmd != NULL) { 391 bus_dmamap_unload(sc->twe_cmd_dmat, sc->twe_cmdmap); 392 bus_dmamem_free(sc->twe_cmd_dmat, sc->twe_cmd, sc->twe_cmdmap); 393 } 394 395 if (sc->twe_immediate != NULL) { 396 bus_dmamap_unload(sc->twe_immediate_dmat, sc->twe_immediate_map); 397 bus_dmamem_free(sc->twe_immediate_dmat, sc->twe_immediate, 398 sc->twe_immediate_map); 399 } 400 401 if (sc->twe_immediate_dmat) 402 bus_dma_tag_destroy(sc->twe_immediate_dmat); 403 404 /* destroy the data-transfer DMA tag */ 405 if (sc->twe_buffer_dmat) 406 bus_dma_tag_destroy(sc->twe_buffer_dmat); 407 408 /* disconnect the interrupt handler */ 409 if (sc->twe_intr) 410 bus_teardown_intr(sc->twe_dev, sc->twe_irq, sc->twe_intr); 411 if (sc->twe_irq != NULL) 412 bus_release_resource(sc->twe_dev, SYS_RES_IRQ, 0, sc->twe_irq); 413 414 /* destroy the parent DMA tag */ 415 if (sc->twe_parent_dmat) 416 bus_dma_tag_destroy(sc->twe_parent_dmat); 417 418 /* release the register window mapping */ 419 if (sc->twe_io != NULL) 420 bus_release_resource(sc->twe_dev, SYS_RES_IOPORT, TWE_IO_CONFIG_REG, sc->twe_io); 421 422 /* destroy control device */ 423 if (sc->twe_dev_t != (dev_t)NULL) 424 destroy_dev(sc->twe_dev_t); 425 426 sysctl_ctx_free(&sc->sysctl_ctx); 427} 428 429/******************************************************************************** 430 * Disconnect from the controller completely, in preparation for unload. 431 */ 432static int 433twe_detach(device_t dev) 434{ 435 struct twe_softc *sc = device_get_softc(dev); 436 int s, error; 437 438 debug_called(4); 439 440 error = EBUSY; 441 s = splbio(); 442 if (sc->twe_state & TWE_STATE_OPEN) 443 goto out; 444 445 /* 446 * Shut the controller down. 447 */ 448 if (twe_shutdown(dev)) 449 goto out; 450 451 twe_free(sc); 452 453 error = 0; 454 out: 455 splx(s); 456 return(error); 457} 458 459/******************************************************************************** 460 * Bring the controller down to a dormant state and detach all child devices. 461 * 462 * Note that we can assume that the bioq on the controller is empty, as we won't 463 * allow shutdown if any device is open. 464 */ 465static int 466twe_shutdown(device_t dev) 467{ 468 struct twe_softc *sc = device_get_softc(dev); 469 int i, s, error = 0; 470 471 debug_called(4); 472 473 s = splbio(); 474 475 /* 476 * Delete all our child devices. 477 */ 478 for (i = 0; i < TWE_MAX_UNITS; i++) { 479 if (sc->twe_drive[i].td_disk != 0) { 480 if ((error = twe_detach_drive(sc, i)) != 0) 481 goto out; 482 } 483 } 484 485 /* 486 * Bring the controller down. 487 */ 488 twe_deinit(sc); 489 490out: 491 splx(s); 492 return(error); 493} 494 495/******************************************************************************** 496 * Bring the controller to a quiescent state, ready for system suspend. 497 */ 498static int 499twe_suspend(device_t dev) 500{ 501 struct twe_softc *sc = device_get_softc(dev); 502 int s; 503 504 debug_called(4); 505 506 s = splbio(); 507 sc->twe_state |= TWE_STATE_SUSPEND; 508 509 twe_disable_interrupts(sc); 510 splx(s); 511 512 return(0); 513} 514 515/******************************************************************************** 516 * Bring the controller back to a state ready for operation. 517 */ 518static int 519twe_resume(device_t dev) 520{ 521 struct twe_softc *sc = device_get_softc(dev); 522 523 debug_called(4); 524 525 sc->twe_state &= ~TWE_STATE_SUSPEND; 526 twe_enable_interrupts(sc); 527 528 return(0); 529} 530 531/******************************************************************************* 532 * Take an interrupt, or be poked by other code to look for interrupt-worthy 533 * status. 534 */ 535static void 536twe_pci_intr(void *arg) 537{ 538 twe_intr((struct twe_softc *)arg); 539} 540 541/******************************************************************************** 542 * Delayed-startup hook 543 */ 544static void 545twe_intrhook(void *arg) 546{ 547 struct twe_softc *sc = (struct twe_softc *)arg; 548 549 /* pull ourselves off the intrhook chain */ 550 config_intrhook_disestablish(&sc->twe_ich); 551 552 /* call core startup routine */ 553 twe_init(sc); 554} 555 556/******************************************************************************** 557 * Given a detected drive, attach it to the bio interface. 558 * 559 * This is called from twe_add_unit. 560 */ 561int 562twe_attach_drive(struct twe_softc *sc, struct twe_drive *dr) 563{ 564 char buf[80]; 565 int error; 566 567 dr->td_disk = device_add_child(sc->twe_dev, NULL, -1); 568 if (dr->td_disk == NULL) { 569 twe_printf(sc, "Cannot add unit\n"); 570 return (EIO); 571 } 572 device_set_ivars(dr->td_disk, dr); 573 574 /* 575 * XXX It would make sense to test the online/initialising bits, but they seem to be 576 * always set... 577 */ 578 sprintf(buf, "Unit %d, %s, %s", 579 dr->td_twe_unit, 580 twe_describe_code(twe_table_unittype, dr->td_type), 581 twe_describe_code(twe_table_unitstate, dr->td_state & TWE_PARAM_UNITSTATUS_MASK)); 582 device_set_desc_copy(dr->td_disk, buf); 583 584 if ((error = bus_generic_attach(sc->twe_dev)) != 0) { 585 twe_printf(sc, "Cannot attach unit to controller. error = %d\n", error); 586 return (EIO); 587 } 588 return (0); 589} 590 591/******************************************************************************** 592 * Detach the specified unit if it exsists 593 * 594 * This is called from twe_del_unit. 595 */ 596int 597twe_detach_drive(struct twe_softc *sc, int unit) 598{ 599 int error = 0; 600 601 if ((error = device_delete_child(sc->twe_dev, sc->twe_drive[unit].td_disk)) != 0) { 602 twe_printf(sc, "failed to delete unit %d\n", unit); 603 return(error); 604 } 605 bzero(&sc->twe_drive[unit], sizeof(sc->twe_drive[unit])); 606 return(error); 607} 608 609/******************************************************************************** 610 * Clear a PCI parity error. 611 */ 612void 613twe_clear_pci_parity_error(struct twe_softc *sc) 614{ 615 TWE_CONTROL(sc, TWE_CONTROL_CLEAR_PARITY_ERROR); 616 pci_write_config(sc->twe_dev, PCIR_STATUS, TWE_PCI_CLEAR_PARITY_ERROR, 2); 617} 618 619/******************************************************************************** 620 * Clear a PCI abort. 621 */ 622void 623twe_clear_pci_abort(struct twe_softc *sc) 624{ 625 TWE_CONTROL(sc, TWE_CONTROL_CLEAR_PCI_ABORT); 626 pci_write_config(sc->twe_dev, PCIR_STATUS, TWE_PCI_CLEAR_PCI_ABORT, 2); 627} 628 629/******************************************************************************** 630 ******************************************************************************** 631 Disk device 632 ******************************************************************************** 633 ********************************************************************************/ 634 635/* 636 * Disk device softc 637 */ 638struct twed_softc 639{ 640 device_t twed_dev; 641 struct twe_softc *twed_controller; /* parent device softc */ 642 struct twe_drive *twed_drive; /* drive data in parent softc */
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844 845#ifdef FREEBSD_4 846 if (--disks_registered == 0) 847 cdevsw_remove(&tweddisk_cdevsw); 848#endif 849 return(0); 850} 851 852/******************************************************************************** 853 ******************************************************************************** 854 Misc 855 ******************************************************************************** 856 ********************************************************************************/ 857 858/******************************************************************************** 859 * Allocate a command buffer 860 */ 861MALLOC_DEFINE(TWE_MALLOC_CLASS, "twe commands", "twe commands"); 862 863struct twe_request * 864twe_allocate_request(struct twe_softc *sc, int tag) 865{ 866 struct twe_request *tr; 867 868 if ((tr = malloc(sizeof(struct twe_request), TWE_MALLOC_CLASS, M_WAITOK)) == NULL) { 869 twe_printf(sc, "unable to allocate memory for tag %d\n", tag); 870 return(NULL); 871 } 872 bzero(tr, sizeof(*tr)); 873 tr->tr_sc = sc; 874 tr->tr_tag = tag; 875 if (bus_dmamap_create(sc->twe_buffer_dmat, 0, &tr->tr_dmamap)) { 876 twe_free_request(tr); 877 twe_printf(sc, "unable to allocate dmamap for tag %d\n", tag); 878 return(NULL); 879 } 880 return(tr); 881} 882 883/******************************************************************************** 884 * Permanently discard a command buffer. 885 */ 886void 887twe_free_request(struct twe_request *tr) 888{ 889 struct twe_softc *sc = tr->tr_sc; 890 891 debug_called(4); 892 893 bus_dmamap_destroy(sc->twe_buffer_dmat, tr->tr_dmamap); 894 free(tr, TWE_MALLOC_CLASS); 895} 896 897/******************************************************************************** 898 * Map/unmap (tr)'s command and data in the controller's addressable space. 899 * 900 * These routines ensure that the data which the controller is going to try to 901 * access is actually visible to the controller, in a machine-independant 902 * fashion. Due to a hardware limitation, I/O buffers must be 512-byte aligned 903 * and we take care of that here as well. 904 */ 905static void 906twe_fillin_sgl(TWE_SG_Entry *sgl, bus_dma_segment_t *segs, int nsegments, int max_sgl) 907{ 908 int i; 909 910 for (i = 0; i < nsegments; i++) { 911 sgl[i].address = segs[i].ds_addr; 912 sgl[i].length = segs[i].ds_len; 913 } 914 for (; i < max_sgl; i++) { /* XXX necessary? */ 915 sgl[i].address = 0; 916 sgl[i].length = 0; 917 } 918} 919 920static void 921twe_setup_data_dmamap(void *arg, bus_dma_segment_t *segs, int nsegments, int error) 922{ 923 struct twe_request *tr = (struct twe_request *)arg; 924 struct twe_softc *sc = tr->tr_sc; 925 TWE_Command *cmd = TWE_FIND_COMMAND(tr); 926 927 debug_called(4); 928 929 if (tr->tr_flags & TWE_CMD_MAPPED) 930 panic("already mapped command"); 931 932 tr->tr_flags |= TWE_CMD_MAPPED; 933 934 /* save base of first segment in command (applicable if there only one segment) */ 935 tr->tr_dataphys = segs[0].ds_addr; 936 937 /* correct command size for s/g list size */ 938 cmd->generic.size += 2 * nsegments; 939 940 /* 941 * Due to the fact that parameter and I/O commands have the scatter/gather list in 942 * different places, we need to determine which sort of command this actually is 943 * before we can populate it correctly. 944 */ 945 switch(cmd->generic.opcode) { 946 case TWE_OP_GET_PARAM: 947 case TWE_OP_SET_PARAM: 948 cmd->generic.sgl_offset = 2; 949 twe_fillin_sgl(&cmd->param.sgl[0], segs, nsegments, TWE_MAX_SGL_LENGTH); 950 break; 951 case TWE_OP_READ: 952 case TWE_OP_WRITE: 953 cmd->generic.sgl_offset = 3; 954 twe_fillin_sgl(&cmd->io.sgl[0], segs, nsegments, TWE_MAX_SGL_LENGTH); 955 break; 956 case TWE_OP_ATA_PASSTHROUGH: 957 cmd->generic.sgl_offset = 5; 958 twe_fillin_sgl(&cmd->ata.sgl[0], segs, nsegments, TWE_MAX_ATA_SGL_LENGTH); 959 break; 960 default: 961 /* 962 * Fall back to what the linux driver does. 963 * Do this because the API may send an opcode 964 * the driver knows nothing about and this will 965 * at least stop PCIABRT's from hosing us. 966 */ 967 switch (cmd->generic.sgl_offset) { 968 case 2: 969 twe_fillin_sgl(&cmd->param.sgl[0], segs, nsegments, TWE_MAX_SGL_LENGTH); 970 break; 971 case 3: 972 twe_fillin_sgl(&cmd->io.sgl[0], segs, nsegments, TWE_MAX_SGL_LENGTH); 973 break; 974 case 5: 975 twe_fillin_sgl(&cmd->ata.sgl[0], segs, nsegments, TWE_MAX_ATA_SGL_LENGTH); 976 break; 977 } 978 } 979 980 if (tr->tr_flags & TWE_CMD_DATAIN) { 981 if (tr->tr_flags & TWE_CMD_IMMEDIATE) { 982 bus_dmamap_sync(sc->twe_immediate_dmat, sc->twe_immediate_map, 983 BUS_DMASYNC_PREREAD); 984 } else { 985 bus_dmamap_sync(sc->twe_buffer_dmat, tr->tr_dmamap, 986 BUS_DMASYNC_PREREAD); 987 } 988 } 989 990 if (tr->tr_flags & TWE_CMD_DATAOUT) { 991 /* 992 * if we're using an alignment buffer, and we're writing data 993 * copy the real data out 994 */ 995 if (tr->tr_flags & TWE_CMD_ALIGNBUF) 996 bcopy(tr->tr_realdata, tr->tr_data, tr->tr_length); 997 998 if (tr->tr_flags & TWE_CMD_IMMEDIATE) { 999 bus_dmamap_sync(sc->twe_immediate_dmat, sc->twe_immediate_map, 1000 BUS_DMASYNC_PREWRITE); 1001 } else { 1002 bus_dmamap_sync(sc->twe_buffer_dmat, tr->tr_dmamap, 1003 BUS_DMASYNC_PREWRITE); 1004 } 1005 } 1006 1007 if (twe_start(tr) == EBUSY) 1008 twe_requeue_ready(tr); 1009} 1010 1011static void 1012twe_setup_request_dmamap(void *arg, bus_dma_segment_t *segs, int nsegments, int error) 1013{ 1014 struct twe_softc *sc = (struct twe_softc *)arg; 1015 1016 debug_called(4); 1017 1018 /* command can't cross a page boundary */ 1019 sc->twe_cmdphys = segs[0].ds_addr; 1020} 1021 1022int 1023twe_map_request(struct twe_request *tr) 1024{ 1025 struct twe_softc *sc = tr->tr_sc; 1026 int error = 0; 1027 1028 debug_called(4); 1029 1030 if (sc->twe_state & TWE_STATE_FRZN) 1031 return (EBUSY); 1032 1033 bus_dmamap_sync(sc->twe_cmd_dmat, sc->twe_cmdmap, BUS_DMASYNC_PREWRITE); 1034 1035 /* 1036 * If the command involves data, map that too. 1037 */ 1038 if (tr->tr_data != NULL && ((tr->tr_flags & TWE_CMD_MAPPED) == 0)) { 1039 1040 /* 1041 * Data must be 64-byte aligned; allocate a fixup buffer if it's not. 1042 */ 1043 if (((vm_offset_t)tr->tr_data % TWE_ALIGNMENT) != 0) { 1044 tr->tr_realdata = tr->tr_data; /* save pointer to 'real' data */ 1045 tr->tr_flags |= TWE_CMD_ALIGNBUF; 1046 tr->tr_data = malloc(tr->tr_length, TWE_MALLOC_CLASS, M_NOWAIT); /* XXX check result here */ 1047 } 1048 1049 /* 1050 * Map the data buffer into bus space and build the s/g list. 1051 */ 1052 if (tr->tr_flags & TWE_CMD_IMMEDIATE) { 1053 bcopy(tr->tr_data, sc->twe_immediate, tr->tr_length); 1054 bus_dmamap_load(sc->twe_immediate_dmat, sc->twe_immediate_map, sc->twe_immediate, 1055 tr->tr_length, twe_setup_data_dmamap, tr, 0); 1056 } else { 1057 error = bus_dmamap_load(sc->twe_buffer_dmat, tr->tr_dmamap, tr->tr_data, tr->tr_length, 1058 twe_setup_data_dmamap, tr, 0); 1059 } 1060 if (error == EINPROGRESS) { 1061 sc->twe_state |= TWE_STATE_FRZN; 1062 error = 0; 1063 } 1064 } else 1065 error = twe_start(tr); 1066 1067 return(error); 1068} 1069 1070void 1071twe_unmap_request(struct twe_request *tr) 1072{ 1073 struct twe_softc *sc = tr->tr_sc; 1074 1075 debug_called(4); 1076 1077 bus_dmamap_sync(sc->twe_cmd_dmat, sc->twe_cmdmap, BUS_DMASYNC_POSTWRITE); 1078 1079 /* 1080 * If the command involved data, unmap that too. 1081 */ 1082 if (tr->tr_data != NULL) { 1083 if (tr->tr_flags & TWE_CMD_DATAIN) { 1084 if (tr->tr_flags & TWE_CMD_IMMEDIATE) { 1085 bus_dmamap_sync(sc->twe_immediate_dmat, sc->twe_immediate_map, 1086 BUS_DMASYNC_POSTREAD); 1087 } else { 1088 bus_dmamap_sync(sc->twe_buffer_dmat, tr->tr_dmamap, 1089 BUS_DMASYNC_POSTREAD); 1090 } 1091 1092 /* if we're using an alignment buffer, and we're reading data, copy the real data in */ 1093 if (tr->tr_flags & TWE_CMD_ALIGNBUF) 1094 bcopy(tr->tr_data, tr->tr_realdata, tr->tr_length); 1095 } 1096 if (tr->tr_flags & TWE_CMD_DATAOUT) { 1097 if (tr->tr_flags & TWE_CMD_IMMEDIATE) { 1098 bus_dmamap_sync(sc->twe_immediate_dmat, sc->twe_immediate_map, 1099 BUS_DMASYNC_POSTWRITE); 1100 } else { 1101 bus_dmamap_sync(sc->twe_buffer_dmat, tr->tr_dmamap, 1102 BUS_DMASYNC_POSTWRITE); 1103 } 1104 } 1105 1106 if (tr->tr_flags & TWE_CMD_IMMEDIATE) { 1107 bcopy(sc->twe_immediate, tr->tr_data, tr->tr_length); 1108 bus_dmamap_unload(sc->twe_immediate_dmat, sc->twe_immediate_map); 1109 } else { 1110 bus_dmamap_unload(sc->twe_buffer_dmat, tr->tr_dmamap); 1111 } 1112 } 1113 1114 /* free alignment buffer if it was used */ 1115 if (tr->tr_flags & TWE_CMD_ALIGNBUF) { 1116 free(tr->tr_data, TWE_MALLOC_CLASS); 1117 tr->tr_data = tr->tr_realdata; /* restore 'real' data pointer */ 1118 } 1119} 1120 1121#ifdef TWE_DEBUG 1122/******************************************************************************** 1123 * Print current controller status, call from DDB. 1124 */ 1125void 1126twe_report(void) 1127{ 1128 struct twe_softc *sc; 1129 int i, s; 1130 1131 s = splbio(); 1132 for (i = 0; (sc = devclass_get_softc(twe_devclass, i)) != NULL; i++) 1133 twe_print_controller(sc); 1134 printf("twed: total bio count in %u out %u\n", twed_bio_in, twed_bio_out); 1135 splx(s); 1136} 1137#endif
| 849 850#ifdef FREEBSD_4 851 if (--disks_registered == 0) 852 cdevsw_remove(&tweddisk_cdevsw); 853#endif 854 return(0); 855} 856 857/******************************************************************************** 858 ******************************************************************************** 859 Misc 860 ******************************************************************************** 861 ********************************************************************************/ 862 863/******************************************************************************** 864 * Allocate a command buffer 865 */ 866MALLOC_DEFINE(TWE_MALLOC_CLASS, "twe commands", "twe commands"); 867 868struct twe_request * 869twe_allocate_request(struct twe_softc *sc, int tag) 870{ 871 struct twe_request *tr; 872 873 if ((tr = malloc(sizeof(struct twe_request), TWE_MALLOC_CLASS, M_WAITOK)) == NULL) { 874 twe_printf(sc, "unable to allocate memory for tag %d\n", tag); 875 return(NULL); 876 } 877 bzero(tr, sizeof(*tr)); 878 tr->tr_sc = sc; 879 tr->tr_tag = tag; 880 if (bus_dmamap_create(sc->twe_buffer_dmat, 0, &tr->tr_dmamap)) { 881 twe_free_request(tr); 882 twe_printf(sc, "unable to allocate dmamap for tag %d\n", tag); 883 return(NULL); 884 } 885 return(tr); 886} 887 888/******************************************************************************** 889 * Permanently discard a command buffer. 890 */ 891void 892twe_free_request(struct twe_request *tr) 893{ 894 struct twe_softc *sc = tr->tr_sc; 895 896 debug_called(4); 897 898 bus_dmamap_destroy(sc->twe_buffer_dmat, tr->tr_dmamap); 899 free(tr, TWE_MALLOC_CLASS); 900} 901 902/******************************************************************************** 903 * Map/unmap (tr)'s command and data in the controller's addressable space. 904 * 905 * These routines ensure that the data which the controller is going to try to 906 * access is actually visible to the controller, in a machine-independant 907 * fashion. Due to a hardware limitation, I/O buffers must be 512-byte aligned 908 * and we take care of that here as well. 909 */ 910static void 911twe_fillin_sgl(TWE_SG_Entry *sgl, bus_dma_segment_t *segs, int nsegments, int max_sgl) 912{ 913 int i; 914 915 for (i = 0; i < nsegments; i++) { 916 sgl[i].address = segs[i].ds_addr; 917 sgl[i].length = segs[i].ds_len; 918 } 919 for (; i < max_sgl; i++) { /* XXX necessary? */ 920 sgl[i].address = 0; 921 sgl[i].length = 0; 922 } 923} 924 925static void 926twe_setup_data_dmamap(void *arg, bus_dma_segment_t *segs, int nsegments, int error) 927{ 928 struct twe_request *tr = (struct twe_request *)arg; 929 struct twe_softc *sc = tr->tr_sc; 930 TWE_Command *cmd = TWE_FIND_COMMAND(tr); 931 932 debug_called(4); 933 934 if (tr->tr_flags & TWE_CMD_MAPPED) 935 panic("already mapped command"); 936 937 tr->tr_flags |= TWE_CMD_MAPPED; 938 939 /* save base of first segment in command (applicable if there only one segment) */ 940 tr->tr_dataphys = segs[0].ds_addr; 941 942 /* correct command size for s/g list size */ 943 cmd->generic.size += 2 * nsegments; 944 945 /* 946 * Due to the fact that parameter and I/O commands have the scatter/gather list in 947 * different places, we need to determine which sort of command this actually is 948 * before we can populate it correctly. 949 */ 950 switch(cmd->generic.opcode) { 951 case TWE_OP_GET_PARAM: 952 case TWE_OP_SET_PARAM: 953 cmd->generic.sgl_offset = 2; 954 twe_fillin_sgl(&cmd->param.sgl[0], segs, nsegments, TWE_MAX_SGL_LENGTH); 955 break; 956 case TWE_OP_READ: 957 case TWE_OP_WRITE: 958 cmd->generic.sgl_offset = 3; 959 twe_fillin_sgl(&cmd->io.sgl[0], segs, nsegments, TWE_MAX_SGL_LENGTH); 960 break; 961 case TWE_OP_ATA_PASSTHROUGH: 962 cmd->generic.sgl_offset = 5; 963 twe_fillin_sgl(&cmd->ata.sgl[0], segs, nsegments, TWE_MAX_ATA_SGL_LENGTH); 964 break; 965 default: 966 /* 967 * Fall back to what the linux driver does. 968 * Do this because the API may send an opcode 969 * the driver knows nothing about and this will 970 * at least stop PCIABRT's from hosing us. 971 */ 972 switch (cmd->generic.sgl_offset) { 973 case 2: 974 twe_fillin_sgl(&cmd->param.sgl[0], segs, nsegments, TWE_MAX_SGL_LENGTH); 975 break; 976 case 3: 977 twe_fillin_sgl(&cmd->io.sgl[0], segs, nsegments, TWE_MAX_SGL_LENGTH); 978 break; 979 case 5: 980 twe_fillin_sgl(&cmd->ata.sgl[0], segs, nsegments, TWE_MAX_ATA_SGL_LENGTH); 981 break; 982 } 983 } 984 985 if (tr->tr_flags & TWE_CMD_DATAIN) { 986 if (tr->tr_flags & TWE_CMD_IMMEDIATE) { 987 bus_dmamap_sync(sc->twe_immediate_dmat, sc->twe_immediate_map, 988 BUS_DMASYNC_PREREAD); 989 } else { 990 bus_dmamap_sync(sc->twe_buffer_dmat, tr->tr_dmamap, 991 BUS_DMASYNC_PREREAD); 992 } 993 } 994 995 if (tr->tr_flags & TWE_CMD_DATAOUT) { 996 /* 997 * if we're using an alignment buffer, and we're writing data 998 * copy the real data out 999 */ 1000 if (tr->tr_flags & TWE_CMD_ALIGNBUF) 1001 bcopy(tr->tr_realdata, tr->tr_data, tr->tr_length); 1002 1003 if (tr->tr_flags & TWE_CMD_IMMEDIATE) { 1004 bus_dmamap_sync(sc->twe_immediate_dmat, sc->twe_immediate_map, 1005 BUS_DMASYNC_PREWRITE); 1006 } else { 1007 bus_dmamap_sync(sc->twe_buffer_dmat, tr->tr_dmamap, 1008 BUS_DMASYNC_PREWRITE); 1009 } 1010 } 1011 1012 if (twe_start(tr) == EBUSY) 1013 twe_requeue_ready(tr); 1014} 1015 1016static void 1017twe_setup_request_dmamap(void *arg, bus_dma_segment_t *segs, int nsegments, int error) 1018{ 1019 struct twe_softc *sc = (struct twe_softc *)arg; 1020 1021 debug_called(4); 1022 1023 /* command can't cross a page boundary */ 1024 sc->twe_cmdphys = segs[0].ds_addr; 1025} 1026 1027int 1028twe_map_request(struct twe_request *tr) 1029{ 1030 struct twe_softc *sc = tr->tr_sc; 1031 int error = 0; 1032 1033 debug_called(4); 1034 1035 if (sc->twe_state & TWE_STATE_FRZN) 1036 return (EBUSY); 1037 1038 bus_dmamap_sync(sc->twe_cmd_dmat, sc->twe_cmdmap, BUS_DMASYNC_PREWRITE); 1039 1040 /* 1041 * If the command involves data, map that too. 1042 */ 1043 if (tr->tr_data != NULL && ((tr->tr_flags & TWE_CMD_MAPPED) == 0)) { 1044 1045 /* 1046 * Data must be 64-byte aligned; allocate a fixup buffer if it's not. 1047 */ 1048 if (((vm_offset_t)tr->tr_data % TWE_ALIGNMENT) != 0) { 1049 tr->tr_realdata = tr->tr_data; /* save pointer to 'real' data */ 1050 tr->tr_flags |= TWE_CMD_ALIGNBUF; 1051 tr->tr_data = malloc(tr->tr_length, TWE_MALLOC_CLASS, M_NOWAIT); /* XXX check result here */ 1052 } 1053 1054 /* 1055 * Map the data buffer into bus space and build the s/g list. 1056 */ 1057 if (tr->tr_flags & TWE_CMD_IMMEDIATE) { 1058 bcopy(tr->tr_data, sc->twe_immediate, tr->tr_length); 1059 bus_dmamap_load(sc->twe_immediate_dmat, sc->twe_immediate_map, sc->twe_immediate, 1060 tr->tr_length, twe_setup_data_dmamap, tr, 0); 1061 } else { 1062 error = bus_dmamap_load(sc->twe_buffer_dmat, tr->tr_dmamap, tr->tr_data, tr->tr_length, 1063 twe_setup_data_dmamap, tr, 0); 1064 } 1065 if (error == EINPROGRESS) { 1066 sc->twe_state |= TWE_STATE_FRZN; 1067 error = 0; 1068 } 1069 } else 1070 error = twe_start(tr); 1071 1072 return(error); 1073} 1074 1075void 1076twe_unmap_request(struct twe_request *tr) 1077{ 1078 struct twe_softc *sc = tr->tr_sc; 1079 1080 debug_called(4); 1081 1082 bus_dmamap_sync(sc->twe_cmd_dmat, sc->twe_cmdmap, BUS_DMASYNC_POSTWRITE); 1083 1084 /* 1085 * If the command involved data, unmap that too. 1086 */ 1087 if (tr->tr_data != NULL) { 1088 if (tr->tr_flags & TWE_CMD_DATAIN) { 1089 if (tr->tr_flags & TWE_CMD_IMMEDIATE) { 1090 bus_dmamap_sync(sc->twe_immediate_dmat, sc->twe_immediate_map, 1091 BUS_DMASYNC_POSTREAD); 1092 } else { 1093 bus_dmamap_sync(sc->twe_buffer_dmat, tr->tr_dmamap, 1094 BUS_DMASYNC_POSTREAD); 1095 } 1096 1097 /* if we're using an alignment buffer, and we're reading data, copy the real data in */ 1098 if (tr->tr_flags & TWE_CMD_ALIGNBUF) 1099 bcopy(tr->tr_data, tr->tr_realdata, tr->tr_length); 1100 } 1101 if (tr->tr_flags & TWE_CMD_DATAOUT) { 1102 if (tr->tr_flags & TWE_CMD_IMMEDIATE) { 1103 bus_dmamap_sync(sc->twe_immediate_dmat, sc->twe_immediate_map, 1104 BUS_DMASYNC_POSTWRITE); 1105 } else { 1106 bus_dmamap_sync(sc->twe_buffer_dmat, tr->tr_dmamap, 1107 BUS_DMASYNC_POSTWRITE); 1108 } 1109 } 1110 1111 if (tr->tr_flags & TWE_CMD_IMMEDIATE) { 1112 bcopy(sc->twe_immediate, tr->tr_data, tr->tr_length); 1113 bus_dmamap_unload(sc->twe_immediate_dmat, sc->twe_immediate_map); 1114 } else { 1115 bus_dmamap_unload(sc->twe_buffer_dmat, tr->tr_dmamap); 1116 } 1117 } 1118 1119 /* free alignment buffer if it was used */ 1120 if (tr->tr_flags & TWE_CMD_ALIGNBUF) { 1121 free(tr->tr_data, TWE_MALLOC_CLASS); 1122 tr->tr_data = tr->tr_realdata; /* restore 'real' data pointer */ 1123 } 1124} 1125 1126#ifdef TWE_DEBUG 1127/******************************************************************************** 1128 * Print current controller status, call from DDB. 1129 */ 1130void 1131twe_report(void) 1132{ 1133 struct twe_softc *sc; 1134 int i, s; 1135 1136 s = splbio(); 1137 for (i = 0; (sc = devclass_get_softc(twe_devclass, i)) != NULL; i++) 1138 twe_print_controller(sc); 1139 printf("twed: total bio count in %u out %u\n", twed_bio_in, twed_bio_out); 1140 splx(s); 1141} 1142#endif
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