1/*
2 * Copyright (c) 2004-07 Applied Micro Circuits Corporation.
3 * Copyright (c) 2004-05 Vinod Kashyap
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:

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19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 * $FreeBSD: head/sys/dev/twa/tw_cl_misc.c 169400 2007-05-09 04:16:32Z scottl $
28 */
29
30/*
31 * AMCC'S 3ware driver for 9000 series storage controllers.
32 *
33 * Author: Vinod Kashyap
34 * Modifications by: Adam Radford
35 */
36
37
38/*
39 * Common Layer miscellaneous functions.
40 */
41
42

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755 }
756 }
757
758 /* Check if any error bits are set. */
759 if ((status_reg & TWA_STATUS_UNEXPECTED_BITS) != 0) {
760 TW_INT8 desc[200];
761
762 tw_osl_memzero(desc, 200);
763 tw_cl_create_event(ctlr_handle, TW_CL_TRUE,
764 TW_CL_MESSAGE_SOURCE_COMMON_LAYER_EVENT,
765 0x1302, 0x1, TW_CL_SEVERITY_ERROR_STRING,
766 "Unexpected status bit(s)",
767 "status reg = 0x%x Unexpected bits: %s",
768 status_reg & TWA_STATUS_UNEXPECTED_BITS,
769 tw_cli_describe_bits(status_reg &
770 TWA_STATUS_UNEXPECTED_BITS, desc));

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804 tw_osl_write_pci_config(ctlr->ctlr_handle,
805 TW_CLI_PCI_CONFIG_STATUS_OFFSET,
806 TWA_PCI_CONFIG_CLEAR_PCI_ABORT, 2);
807#endif /* TW_OSL_PCI_CONFIG_ACCESSIBLE */
808
809 }
810
811 if (status_reg & TWA_STATUS_QUEUE_ERROR_INTERRUPT) {
812 if (ctlr->device_id != TW_CL_DEVICE_ID_9K_E)
813 tw_cl_create_event(ctlr_handle, TW_CL_TRUE,
814 TW_CL_MESSAGE_SOURCE_COMMON_LAYER_EVENT,
815 0x1305, 0x1, TW_CL_SEVERITY_ERROR_STRING,
816 "Controller queue error: clearing... ",
817 "status reg = 0x%x %s",
818 status_reg,
819 tw_cli_describe_bits(status_reg, desc));
820 TW_CLI_WRITE_CONTROL_REGISTER(ctlr->ctlr_handle,

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