| tw_cl.h (209860) | tw_cl.h (212008) |
|---|---|
| 1/* 2 * Copyright (c) 2004-07 Applied Micro Circuits Corporation. 3 * Copyright (c) 2004-05 Vinod Kashyap 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: --- 10 unchanged lines hidden (view full) --- 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * | 1/* 2 * Copyright (c) 2004-07 Applied Micro Circuits Corporation. 3 * Copyright (c) 2004-05 Vinod Kashyap 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: --- 10 unchanged lines hidden (view full) --- 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * |
| 27 * $FreeBSD: head/sys/dev/twa/tw_cl.h 209860 2010-07-09 17:38:15Z delphij $ | 27 * $FreeBSD: head/sys/dev/twa/tw_cl.h 212008 2010-08-30 19:15:04Z delphij $ |
| 28 */ 29 30/* 31 * AMCC'S 3ware driver for 9000 series storage controllers. 32 * 33 * Author: Vinod Kashyap 34 * Modifications by: Adam Radford 35 */ --- 47 unchanged lines hidden (view full) --- 83#endif /* TW_OSL_DEBUG */ 84 85 86/* Queues of CL internal request context packets. */ 87#define TW_CLI_FREE_Q 0 /* free q */ 88#define TW_CLI_BUSY_Q 1 /* q of reqs submitted to fw */ 89#define TW_CLI_PENDING_Q 2 /* q of reqs deferred due to 'q full' */ 90#define TW_CLI_COMPLETE_Q 3 /* q of reqs completed by fw */ | 28 */ 29 30/* 31 * AMCC'S 3ware driver for 9000 series storage controllers. 32 * 33 * Author: Vinod Kashyap 34 * Modifications by: Adam Radford 35 */ --- 47 unchanged lines hidden (view full) --- 83#endif /* TW_OSL_DEBUG */ 84 85 86/* Queues of CL internal request context packets. */ 87#define TW_CLI_FREE_Q 0 /* free q */ 88#define TW_CLI_BUSY_Q 1 /* q of reqs submitted to fw */ 89#define TW_CLI_PENDING_Q 2 /* q of reqs deferred due to 'q full' */ 90#define TW_CLI_COMPLETE_Q 3 /* q of reqs completed by fw */ |
| 91#define TW_CLI_Q_COUNT 4 /* total number of queues */ | 91#define TW_CLI_RESET_Q 4 /* q of reqs reset by timeout */ 92#define TW_CLI_Q_COUNT 5 /* total number of queues */ |
| 92 93 94/* CL's internal request context. */ 95struct tw_cli_req_context { 96 struct tw_cl_req_handle *req_handle;/* handle to track requests between 97 OSL & CL */ 98 struct tw_cli_ctlr_context *ctlr; /* ptr to CL's controller context */ 99 struct tw_cl_command_packet *cmd_pkt;/* ptr to ctlr cmd pkt */ --- 28 unchanged lines hidden (view full) --- 128 TW_UINT64 cmd_pkt_phys; /* phys addr of cmd_pkt_buf */ 129 130 TW_UINT32 device_id; /* controller device id */ 131 TW_UINT32 arch_id; /* controller architecture id */ 132 TW_UINT8 active; /* Initialization done, and controller is active. */ 133 TW_UINT8 interrupts_enabled; /* Interrupts on controller enabled. */ 134 TW_UINT8 internal_req_busy; /* Data buffer for internal requests in use. */ 135 TW_UINT8 get_more_aens; /* More AEN's need to be retrieved. */ | 93 94 95/* CL's internal request context. */ 96struct tw_cli_req_context { 97 struct tw_cl_req_handle *req_handle;/* handle to track requests between 98 OSL & CL */ 99 struct tw_cli_ctlr_context *ctlr; /* ptr to CL's controller context */ 100 struct tw_cl_command_packet *cmd_pkt;/* ptr to ctlr cmd pkt */ --- 28 unchanged lines hidden (view full) --- 129 TW_UINT64 cmd_pkt_phys; /* phys addr of cmd_pkt_buf */ 130 131 TW_UINT32 device_id; /* controller device id */ 132 TW_UINT32 arch_id; /* controller architecture id */ 133 TW_UINT8 active; /* Initialization done, and controller is active. */ 134 TW_UINT8 interrupts_enabled; /* Interrupts on controller enabled. */ 135 TW_UINT8 internal_req_busy; /* Data buffer for internal requests in use. */ 136 TW_UINT8 get_more_aens; /* More AEN's need to be retrieved. */ |
| 137 TW_UINT8 reset_needed; /* Controller needs a soft reset. */ |
|
| 136 TW_UINT8 reset_in_progress; /* Controller is being reset. */ 137 TW_UINT8 reset_phase1_in_progress; /* In 'phase 1' of reset. */ 138 TW_UINT32 flags; /* controller settings */ 139 TW_UINT32 sg_size_factor; /* SG element size should be a 140 multiple of this */ 141 142 /* Request queues and arrays. */ 143 struct tw_cl_link req_q_head[TW_CLI_Q_COUNT]; --- 202 unchanged lines hidden --- | 138 TW_UINT8 reset_in_progress; /* Controller is being reset. */ 139 TW_UINT8 reset_phase1_in_progress; /* In 'phase 1' of reset. */ 140 TW_UINT32 flags; /* controller settings */ 141 TW_UINT32 sg_size_factor; /* SG element size should be a 142 multiple of this */ 143 144 /* Request queues and arrays. */ 145 struct tw_cl_link req_q_head[TW_CLI_Q_COUNT]; --- 202 unchanged lines hidden --- |