32
33#ifdef HAVE_KERNEL_OPTION_HEADERS
34#include "opt_device_polling.h"
35#endif
36
37#include <sys/param.h>
38#include <sys/systm.h>
39#include <sys/bus.h>
40#include <sys/endian.h>
41#include <sys/mbuf.h>
42#include <sys/kernel.h>
43#include <sys/module.h>
44#include <sys/socket.h>
45#include <sys/sockio.h>
46#include <sys/sysctl.h>
47
48#include <net/bpf.h>
49#include <net/ethernet.h>
50#include <net/if.h>
51#include <net/if_arp.h>
52#include <net/if_dl.h>
53#include <net/if_media.h>
54#include <net/if_types.h>
55#include <net/if_vlan_var.h>
56
57#include <netinet/in_systm.h>
58#include <netinet/in.h>
59#include <netinet/ip.h>
60
61#include <machine/bus.h>
62
63#include <dev/mii/mii.h>
64#include <dev/mii/miivar.h>
65
66#include <dev/tsec/if_tsec.h>
67#include <dev/tsec/if_tsecreg.h>
68
69static int tsec_alloc_dma_desc(device_t dev, bus_dma_tag_t *dtag,
70 bus_dmamap_t *dmap, bus_size_t dsize, void **vaddr, void *raddr,
71 const char *dname);
72static void tsec_dma_ctl(struct tsec_softc *sc, int state);
73static int tsec_encap(struct tsec_softc *sc, struct mbuf *m_head,
74 int fcb_inserted);
75static void tsec_free_dma(struct tsec_softc *sc);
76static void tsec_free_dma_desc(bus_dma_tag_t dtag, bus_dmamap_t dmap, void *vaddr);
77static int tsec_ifmedia_upd(struct ifnet *ifp);
78static void tsec_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr);
79static int tsec_new_rxbuf(bus_dma_tag_t tag, bus_dmamap_t map,
80 struct mbuf **mbufp, uint32_t *paddr);
81static void tsec_map_dma_addr(void *arg, bus_dma_segment_t *segs,
82 int nseg, int error);
83static void tsec_intrs_ctl(struct tsec_softc *sc, int state);
84static void tsec_init(void *xsc);
85static void tsec_init_locked(struct tsec_softc *sc);
86static int tsec_ioctl(struct ifnet *ifp, u_long command, caddr_t data);
87static void tsec_reset_mac(struct tsec_softc *sc);
88static void tsec_setfilter(struct tsec_softc *sc);
89static void tsec_set_mac_address(struct tsec_softc *sc);
90static void tsec_start(struct ifnet *ifp);
91static void tsec_start_locked(struct ifnet *ifp);
92static void tsec_stop(struct tsec_softc *sc);
93static void tsec_tick(void *arg);
94static void tsec_watchdog(struct tsec_softc *sc);
95static void tsec_add_sysctls(struct tsec_softc *sc);
96static int tsec_sysctl_ic_time(SYSCTL_HANDLER_ARGS);
97static int tsec_sysctl_ic_count(SYSCTL_HANDLER_ARGS);
98static void tsec_set_rxic(struct tsec_softc *sc);
99static void tsec_set_txic(struct tsec_softc *sc);
100static int tsec_receive_intr_locked(struct tsec_softc *sc, int count);
101static void tsec_transmit_intr_locked(struct tsec_softc *sc);
102static void tsec_error_intr_locked(struct tsec_softc *sc, int count);
103static void tsec_offload_setup(struct tsec_softc *sc);
104static void tsec_offload_process_frame(struct tsec_softc *sc,
105 struct mbuf *m);
106static void tsec_setup_multicast(struct tsec_softc *sc);
107static int tsec_set_mtu(struct tsec_softc *sc, unsigned int mtu);
108
109struct tsec_softc *tsec0_sc = NULL; /* XXX ugly hack! */
110
111devclass_t tsec_devclass;
112DRIVER_MODULE(miibus, tsec, miibus_driver, miibus_devclass, 0, 0);
113MODULE_DEPEND(tsec, ether, 1, 1, 1);
114MODULE_DEPEND(tsec, miibus, 1, 1, 1);
115
116int
117tsec_attach(struct tsec_softc *sc)
118{
119 uint8_t hwaddr[ETHER_ADDR_LEN];
120 struct ifnet *ifp;
121 bus_dmamap_t *map_ptr;
122 bus_dmamap_t **map_pptr;
123 int error = 0;
124 int i;
125
126 /* Reset all TSEC counters */
127 TSEC_TX_RX_COUNTERS_INIT(sc);
128
129 /* Stop DMA engine if enabled by firmware */
130 tsec_dma_ctl(sc, 0);
131
132 /* Reset MAC */
133 tsec_reset_mac(sc);
134
135 /* Disable interrupts for now */
136 tsec_intrs_ctl(sc, 0);
137
138 /* Configure defaults for interrupts coalescing */
139 sc->rx_ic_time = 768;
140 sc->rx_ic_count = 16;
141 sc->tx_ic_time = 768;
142 sc->tx_ic_count = 16;
143 tsec_set_rxic(sc);
144 tsec_set_txic(sc);
145 tsec_add_sysctls(sc);
146
147 /* Allocate a busdma tag and DMA safe memory for TX descriptors. */
148 error = tsec_alloc_dma_desc(sc->dev, &sc->tsec_tx_dtag,
149 &sc->tsec_tx_dmap, sizeof(*sc->tsec_tx_vaddr) * TSEC_TX_NUM_DESC,
150 (void **)&sc->tsec_tx_vaddr, &sc->tsec_tx_raddr, "TX");
151
152 if (error) {
153 tsec_detach(sc);
154 return (ENXIO);
155 }
156
157 /* Allocate a busdma tag and DMA safe memory for RX descriptors. */
158 error = tsec_alloc_dma_desc(sc->dev, &sc->tsec_rx_dtag,
159 &sc->tsec_rx_dmap, sizeof(*sc->tsec_rx_vaddr) * TSEC_RX_NUM_DESC,
160 (void **)&sc->tsec_rx_vaddr, &sc->tsec_rx_raddr, "RX");
161 if (error) {
162 tsec_detach(sc);
163 return (ENXIO);
164 }
165
166 /* Allocate a busdma tag for TX mbufs. */
167 error = bus_dma_tag_create(NULL, /* parent */
168 TSEC_TXBUFFER_ALIGNMENT, 0, /* alignment, boundary */
169 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
170 BUS_SPACE_MAXADDR, /* highaddr */
171 NULL, NULL, /* filtfunc, filtfuncarg */
172 MCLBYTES * (TSEC_TX_NUM_DESC - 1), /* maxsize */
173 TSEC_TX_NUM_DESC - 1, /* nsegments */
174 MCLBYTES, 0, /* maxsegsz, flags */
175 NULL, NULL, /* lockfunc, lockfuncarg */
176 &sc->tsec_tx_mtag); /* dmat */
177 if (error) {
178 device_printf(sc->dev, "failed to allocate busdma tag "
179 "(tx mbufs)\n");
180 tsec_detach(sc);
181 return (ENXIO);
182 }
183
184 /* Allocate a busdma tag for RX mbufs. */
185 error = bus_dma_tag_create(NULL, /* parent */
186 TSEC_RXBUFFER_ALIGNMENT, 0, /* alignment, boundary */
187 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
188 BUS_SPACE_MAXADDR, /* highaddr */
189 NULL, NULL, /* filtfunc, filtfuncarg */
190 MCLBYTES, /* maxsize */
191 1, /* nsegments */
192 MCLBYTES, 0, /* maxsegsz, flags */
193 NULL, NULL, /* lockfunc, lockfuncarg */
194 &sc->tsec_rx_mtag); /* dmat */
195 if (error) {
196 device_printf(sc->dev, "failed to allocate busdma tag "
197 "(rx mbufs)\n");
198 tsec_detach(sc);
199 return (ENXIO);
200 }
201
202 /* Create TX busdma maps */
203 map_ptr = sc->tx_map_data;
204 map_pptr = sc->tx_map_unused_data;
205
206 for (i = 0; i < TSEC_TX_NUM_DESC; i++) {
207 map_pptr[i] = &map_ptr[i];
208 error = bus_dmamap_create(sc->tsec_tx_mtag, 0, map_pptr[i]);
209 if (error) {
210 device_printf(sc->dev, "failed to init TX ring\n");
211 tsec_detach(sc);
212 return (ENXIO);
213 }
214 }
215
216 /* Create RX busdma maps and zero mbuf handlers */
217 for (i = 0; i < TSEC_RX_NUM_DESC; i++) {
218 error = bus_dmamap_create(sc->tsec_rx_mtag, 0,
219 &sc->rx_data[i].map);
220 if (error) {
221 device_printf(sc->dev, "failed to init RX ring\n");
222 tsec_detach(sc);
223 return (ENXIO);
224 }
225 sc->rx_data[i].mbuf = NULL;
226 }
227
228 /* Create mbufs for RX buffers */
229 for (i = 0; i < TSEC_RX_NUM_DESC; i++) {
230 error = tsec_new_rxbuf(sc->tsec_rx_mtag, sc->rx_data[i].map,
231 &sc->rx_data[i].mbuf, &sc->rx_data[i].paddr);
232 if (error) {
233 device_printf(sc->dev, "can't load rx DMA map %d, "
234 "error = %d\n", i, error);
235 tsec_detach(sc);
236 return (error);
237 }
238 }
239
240 /* Create network interface for upper layers */
241 ifp = sc->tsec_ifp = if_alloc(IFT_ETHER);
242 if (ifp == NULL) {
243 device_printf(sc->dev, "if_alloc() failed\n");
244 tsec_detach(sc);
245 return (ENOMEM);
246 }
247
248 ifp->if_softc = sc;
249 if_initname(ifp, device_get_name(sc->dev), device_get_unit(sc->dev));
250 ifp->if_mtu = ETHERMTU;
251 ifp->if_flags = IFF_SIMPLEX | IFF_MULTICAST | IFF_BROADCAST;
252 ifp->if_init = tsec_init;
253 ifp->if_start = tsec_start;
254 ifp->if_ioctl = tsec_ioctl;
255
256 IFQ_SET_MAXLEN(&ifp->if_snd, TSEC_TX_NUM_DESC - 1);
257 ifp->if_snd.ifq_drv_maxlen = TSEC_TX_NUM_DESC - 1;
258 IFQ_SET_READY(&ifp->if_snd);
259
260 ifp->if_capabilities = IFCAP_VLAN_MTU;
261 if (sc->is_etsec)
262 ifp->if_capabilities |= IFCAP_HWCSUM;
263
264 ifp->if_capenable = ifp->if_capabilities;
265
266#ifdef DEVICE_POLLING
267 /* Advertise that polling is supported */
268 ifp->if_capabilities |= IFCAP_POLLING;
269#endif
270
271 /* Probe PHY(s) */
272 error = mii_phy_probe(sc->dev, &sc->tsec_miibus, tsec_ifmedia_upd,
273 tsec_ifmedia_sts);
274 if (error) {
275 device_printf(sc->dev, "MII failed to find PHY!\n");
276 if_free(ifp);
277 sc->tsec_ifp = NULL;
278 tsec_detach(sc);
279 return (error);
280 }
281 sc->tsec_mii = device_get_softc(sc->tsec_miibus);
282
283 /* Set MAC address */
284 tsec_get_hwaddr(sc, hwaddr);
285 ether_ifattach(ifp, hwaddr);
286
287 return (0);
288}
289
290int
291tsec_detach(struct tsec_softc *sc)
292{
293
294#ifdef DEVICE_POLLING
295 if (sc->tsec_ifp->if_capenable & IFCAP_POLLING)
296 ether_poll_deregister(sc->tsec_ifp);
297#endif
298
299 /* Stop TSEC controller and free TX queue */
300 if (sc->sc_rres && sc->tsec_ifp)
301 tsec_shutdown(sc->dev);
302
303 /* Detach network interface */
304 if (sc->tsec_ifp) {
305 ether_ifdetach(sc->tsec_ifp);
306 if_free(sc->tsec_ifp);
307 sc->tsec_ifp = NULL;
308 }
309
310 /* Free DMA resources */
311 tsec_free_dma(sc);
312
313 return (0);
314}
315
|
327}
328
329int
330tsec_suspend(device_t dev)
331{
332
333 /* TODO not implemented! */
334 return (0);
335}
336
337int
338tsec_resume(device_t dev)
339{
340
341 /* TODO not implemented! */
342 return (0);
343}
344
345static void
346tsec_init(void *xsc)
347{
348 struct tsec_softc *sc = xsc;
349
350 TSEC_GLOBAL_LOCK(sc);
351 tsec_init_locked(sc);
352 TSEC_GLOBAL_UNLOCK(sc);
353}
354
355static void
356tsec_init_locked(struct tsec_softc *sc)
357{
358 struct tsec_desc *tx_desc = sc->tsec_tx_vaddr;
359 struct tsec_desc *rx_desc = sc->tsec_rx_vaddr;
360 struct ifnet *ifp = sc->tsec_ifp;
361 uint32_t timeout, val, i;
362
363 TSEC_GLOBAL_LOCK_ASSERT(sc);
364 tsec_stop(sc);
365
366 /*
367 * These steps are according to the MPC8555E PowerQUICCIII RM:
368 * 14.7 Initialization/Application Information
369 */
370
371 /* Step 1: soft reset MAC */
372 tsec_reset_mac(sc);
373
374 /* Step 2: Initialize MACCFG2 */
375 TSEC_WRITE(sc, TSEC_REG_MACCFG2,
376 TSEC_MACCFG2_FULLDUPLEX | /* Full Duplex = 1 */
377 TSEC_MACCFG2_PADCRC | /* PAD/CRC append */
378 TSEC_MACCFG2_GMII | /* I/F Mode bit */
379 TSEC_MACCFG2_PRECNT /* Preamble count = 7 */
380 );
381
382 /* Step 3: Initialize ECNTRL
383 * While the documentation states that R100M is ignored if RPM is
384 * not set, it does seem to be needed to get the orange boxes to
385 * work (which have a Marvell 88E1111 PHY). Go figure.
386 */
387
388 /*
389 * XXX kludge - use circumstancial evidence to program ECNTRL
390 * correctly. Ideally we need some board information to guide
391 * us here.
392 */
393 i = TSEC_READ(sc, TSEC_REG_ID2);
394 val = (i & 0xffff)
395 ? (TSEC_ECNTRL_TBIM | TSEC_ECNTRL_SGMIIM) /* Sumatra */
396 : TSEC_ECNTRL_R100M; /* Orange + CDS */
397 TSEC_WRITE(sc, TSEC_REG_ECNTRL, TSEC_ECNTRL_STEN | val);
398
399 /* Step 4: Initialize MAC station address */
400 tsec_set_mac_address(sc);
401
402 /*
403 * Step 5: Assign a Physical address to the TBI so as to not conflict
404 * with the external PHY physical address
405 */
406 TSEC_WRITE(sc, TSEC_REG_TBIPA, 5);
407
408 /* Step 6: Reset the management interface */
409 TSEC_WRITE(tsec0_sc, TSEC_REG_MIIMCFG, TSEC_MIIMCFG_RESETMGMT);
410
411 /* Step 7: Setup the MII Mgmt clock speed */
412 TSEC_WRITE(tsec0_sc, TSEC_REG_MIIMCFG, TSEC_MIIMCFG_CLKDIV28);
413
414 /* Step 8: Read MII Mgmt indicator register and check for Busy = 0 */
415 timeout = TSEC_READ_RETRY;
416 while (--timeout && (TSEC_READ(tsec0_sc, TSEC_REG_MIIMIND) &
417 TSEC_MIIMIND_BUSY))
418 DELAY(TSEC_READ_DELAY);
419 if (timeout == 0) {
420 if_printf(ifp, "tsec_init_locked(): Mgmt busy timeout\n");
421 return;
422 }
423
424 /* Step 9: Setup the MII Mgmt */
425 mii_mediachg(sc->tsec_mii);
426
427 /* Step 10: Clear IEVENT register */
428 TSEC_WRITE(sc, TSEC_REG_IEVENT, 0xffffffff);
429
430 /* Step 11: Enable interrupts */
431#ifdef DEVICE_POLLING
432 /*
433 * ...only if polling is not turned on. Disable interrupts explicitly
434 * if polling is enabled.
435 */
436 if (ifp->if_capenable & IFCAP_POLLING )
437 tsec_intrs_ctl(sc, 0);
438 else
439#endif /* DEVICE_POLLING */
440 tsec_intrs_ctl(sc, 1);
441
442 /* Step 12: Initialize IADDRn */
443 TSEC_WRITE(sc, TSEC_REG_IADDR0, 0);
444 TSEC_WRITE(sc, TSEC_REG_IADDR1, 0);
445 TSEC_WRITE(sc, TSEC_REG_IADDR2, 0);
446 TSEC_WRITE(sc, TSEC_REG_IADDR3, 0);
447 TSEC_WRITE(sc, TSEC_REG_IADDR4, 0);
448 TSEC_WRITE(sc, TSEC_REG_IADDR5, 0);
449 TSEC_WRITE(sc, TSEC_REG_IADDR6, 0);
450 TSEC_WRITE(sc, TSEC_REG_IADDR7, 0);
451
452 /* Step 13: Initialize GADDRn */
453 TSEC_WRITE(sc, TSEC_REG_GADDR0, 0);
454 TSEC_WRITE(sc, TSEC_REG_GADDR1, 0);
455 TSEC_WRITE(sc, TSEC_REG_GADDR2, 0);
456 TSEC_WRITE(sc, TSEC_REG_GADDR3, 0);
457 TSEC_WRITE(sc, TSEC_REG_GADDR4, 0);
458 TSEC_WRITE(sc, TSEC_REG_GADDR5, 0);
459 TSEC_WRITE(sc, TSEC_REG_GADDR6, 0);
460 TSEC_WRITE(sc, TSEC_REG_GADDR7, 0);
461
462 /* Step 14: Initialize RCTRL */
463 TSEC_WRITE(sc, TSEC_REG_RCTRL, 0);
464
465 /* Step 15: Initialize DMACTRL */
466 tsec_dma_ctl(sc, 1);
467
468 /* Step 16: Initialize FIFO_PAUSE_CTRL */
469 TSEC_WRITE(sc, TSEC_REG_FIFO_PAUSE_CTRL, TSEC_FIFO_PAUSE_CTRL_EN);
470
471 /*
472 * Step 17: Initialize transmit/receive descriptor rings.
473 * Initialize TBASE and RBASE.
474 */
475 TSEC_WRITE(sc, TSEC_REG_TBASE, sc->tsec_tx_raddr);
476 TSEC_WRITE(sc, TSEC_REG_RBASE, sc->tsec_rx_raddr);
477
478 for (i = 0; i < TSEC_TX_NUM_DESC; i++) {
479 tx_desc[i].bufptr = 0;
480 tx_desc[i].length = 0;
481 tx_desc[i].flags = ((i == TSEC_TX_NUM_DESC - 1) ?
482 TSEC_TXBD_W : 0);
483 }
484 bus_dmamap_sync(sc->tsec_tx_dtag, sc->tsec_tx_dmap,
485 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
486
487 for (i = 0; i < TSEC_RX_NUM_DESC; i++) {
488 rx_desc[i].bufptr = sc->rx_data[i].paddr;
489 rx_desc[i].length = 0;
490 rx_desc[i].flags = TSEC_RXBD_E | TSEC_RXBD_I |
491 ((i == TSEC_RX_NUM_DESC - 1) ? TSEC_RXBD_W : 0);
492 }
493 bus_dmamap_sync(sc->tsec_rx_dtag, sc->tsec_rx_dmap,
494 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
495
496 /* Step 18: Initialize the maximum receive buffer length */
497 TSEC_WRITE(sc, TSEC_REG_MRBLR, MCLBYTES);
498
499 /* Step 19: Configure ethernet frame sizes */
500 TSEC_WRITE(sc, TSEC_REG_MINFLR, TSEC_MIN_FRAME_SIZE);
501 tsec_set_mtu(sc, ifp->if_mtu);
502
503 /* Step 20: Enable Rx and RxBD sdata snooping */
504 TSEC_WRITE(sc, TSEC_REG_ATTR, TSEC_ATTR_RDSEN | TSEC_ATTR_RBDSEN);
505 TSEC_WRITE(sc, TSEC_REG_ATTRELI, 0);
506
507 /* Step 21: Reset collision counters in hardware */
508 TSEC_WRITE(sc, TSEC_REG_MON_TSCL, 0);
509 TSEC_WRITE(sc, TSEC_REG_MON_TMCL, 0);
510 TSEC_WRITE(sc, TSEC_REG_MON_TLCL, 0);
511 TSEC_WRITE(sc, TSEC_REG_MON_TXCL, 0);
512 TSEC_WRITE(sc, TSEC_REG_MON_TNCL, 0);
513
514 /* Step 22: Mask all CAM interrupts */
515 TSEC_WRITE(sc, TSEC_REG_MON_CAM1, 0xffffffff);
516 TSEC_WRITE(sc, TSEC_REG_MON_CAM2, 0xffffffff);
517
518 /* Step 23: Enable Rx and Tx */
519 val = TSEC_READ(sc, TSEC_REG_MACCFG1);
520 val |= (TSEC_MACCFG1_RX_EN | TSEC_MACCFG1_TX_EN);
521 TSEC_WRITE(sc, TSEC_REG_MACCFG1, val);
522
523 /* Step 24: Reset TSEC counters for Tx and Rx rings */
524 TSEC_TX_RX_COUNTERS_INIT(sc);
525
526 /* Step 25: Setup TCP/IP Off-Load engine */
527 if (sc->is_etsec)
528 tsec_offload_setup(sc);
529
530 /* Step 26: Setup multicast filters */
531 tsec_setup_multicast(sc);
532
533 /* Step 27: Activate network interface */
534 ifp->if_drv_flags |= IFF_DRV_RUNNING;
535 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
536 sc->tsec_if_flags = ifp->if_flags;
537 sc->tsec_watchdog = 0;
538
539 /* Schedule watchdog timeout */
540 callout_reset(&sc->tsec_callout, hz, tsec_tick, sc);
541}
542
543static void
544tsec_set_mac_address(struct tsec_softc *sc)
545{
546 uint32_t macbuf[2] = { 0, 0 };
547 char *macbufp, *curmac;
548 int i;
549
550 TSEC_GLOBAL_LOCK_ASSERT(sc);
551
552 KASSERT((ETHER_ADDR_LEN <= sizeof(macbuf)),
553 ("tsec_set_mac_address: (%d <= %d", ETHER_ADDR_LEN,
554 sizeof(macbuf)));
555
556 macbufp = (char *)macbuf;
557 curmac = (char *)IF_LLADDR(sc->tsec_ifp);
558
559 /* Correct order of MAC address bytes */
560 for (i = 1; i <= ETHER_ADDR_LEN; i++)
561 macbufp[ETHER_ADDR_LEN-i] = curmac[i-1];
562
563 /* Initialize MAC station address MACSTNADDR2 and MACSTNADDR1 */
564 TSEC_WRITE(sc, TSEC_REG_MACSTNADDR2, macbuf[1]);
565 TSEC_WRITE(sc, TSEC_REG_MACSTNADDR1, macbuf[0]);
566}
567
568/*
569 * DMA control function, if argument state is:
570 * 0 - DMA engine will be disabled
571 * 1 - DMA engine will be enabled
572 */
573static void
574tsec_dma_ctl(struct tsec_softc *sc, int state)
575{
576 device_t dev;
577 uint32_t dma_flags, timeout;
578
579 dev = sc->dev;
580
581 dma_flags = TSEC_READ(sc, TSEC_REG_DMACTRL);
582
583 switch (state) {
584 case 0:
585 /* Temporarily clear stop graceful stop bits. */
586 tsec_dma_ctl(sc, 1000);
587
588 /* Set it again */
589 dma_flags |= (TSEC_DMACTRL_GRS | TSEC_DMACTRL_GTS);
590 break;
591 case 1000:
592 case 1:
593 /* Set write with response (WWR), wait (WOP) and snoop bits */
594 dma_flags |= (TSEC_DMACTRL_TDSEN | TSEC_DMACTRL_TBDSEN |
595 DMACTRL_WWR | DMACTRL_WOP);
596
597 /* Clear graceful stop bits */
598 dma_flags &= ~(TSEC_DMACTRL_GRS | TSEC_DMACTRL_GTS);
599 break;
600 default:
601 device_printf(dev, "tsec_dma_ctl(): unknown state value: %d\n",
602 state);
603 }
604
605 TSEC_WRITE(sc, TSEC_REG_DMACTRL, dma_flags);
606
607 switch (state) {
608 case 0:
609 /* Wait for DMA stop */
610 timeout = TSEC_READ_RETRY;
611 while (--timeout && (!(TSEC_READ(sc, TSEC_REG_IEVENT) &
612 (TSEC_IEVENT_GRSC | TSEC_IEVENT_GTSC))))
613 DELAY(TSEC_READ_DELAY);
614
615 if (timeout == 0)
616 device_printf(dev, "tsec_dma_ctl(): timeout!\n");
617 break;
618 case 1:
619 /* Restart transmission function */
620 TSEC_WRITE(sc, TSEC_REG_TSTAT, TSEC_TSTAT_THLT);
621 }
622}
623
624/*
625 * Interrupts control function, if argument state is:
626 * 0 - all TSEC interrupts will be masked
627 * 1 - all TSEC interrupts will be unmasked
628 */
629static void
630tsec_intrs_ctl(struct tsec_softc *sc, int state)
631{
632 device_t dev;
633
634 dev = sc->dev;
635
636 switch (state) {
637 case 0:
638 TSEC_WRITE(sc, TSEC_REG_IMASK, 0);
639 break;
640 case 1:
641 TSEC_WRITE(sc, TSEC_REG_IMASK, TSEC_IMASK_BREN |
642 TSEC_IMASK_RXCEN | TSEC_IMASK_BSYEN | TSEC_IMASK_EBERREN |
643 TSEC_IMASK_BTEN | TSEC_IMASK_TXEEN | TSEC_IMASK_TXBEN |
644 TSEC_IMASK_TXFEN | TSEC_IMASK_XFUNEN | TSEC_IMASK_RXFEN);
645 break;
646 default:
647 device_printf(dev, "tsec_intrs_ctl(): unknown state value: %d\n",
648 state);
649 }
650}
651
652static void
653tsec_reset_mac(struct tsec_softc *sc)
654{
655 uint32_t maccfg1_flags;
656
657 /* Set soft reset bit */
658 maccfg1_flags = TSEC_READ(sc, TSEC_REG_MACCFG1);
659 maccfg1_flags |= TSEC_MACCFG1_SOFT_RESET;
660 TSEC_WRITE(sc, TSEC_REG_MACCFG1, maccfg1_flags);
661
662 /* Clear soft reset bit */
663 maccfg1_flags = TSEC_READ(sc, TSEC_REG_MACCFG1);
664 maccfg1_flags &= ~TSEC_MACCFG1_SOFT_RESET;
665 TSEC_WRITE(sc, TSEC_REG_MACCFG1, maccfg1_flags);
666}
667
668static void
669tsec_watchdog(struct tsec_softc *sc)
670{
671 struct ifnet *ifp;
672
673 TSEC_GLOBAL_LOCK_ASSERT(sc);
674
675 if (sc->tsec_watchdog == 0 || --sc->tsec_watchdog > 0)
676 return;
677
678 ifp = sc->tsec_ifp;
679 ifp->if_oerrors++;
680 if_printf(ifp, "watchdog timeout\n");
681
682 tsec_stop(sc);
683 tsec_init_locked(sc);
684}
685
686static void
687tsec_start(struct ifnet *ifp)
688{
689 struct tsec_softc *sc = ifp->if_softc;
690
691 TSEC_TRANSMIT_LOCK(sc);
692 tsec_start_locked(ifp);
693 TSEC_TRANSMIT_UNLOCK(sc);
694}
695
696static void
697tsec_start_locked(struct ifnet *ifp)
698{
699 struct tsec_softc *sc;
700 struct mbuf *m0, *mtmp;
701 struct tsec_tx_fcb *tx_fcb;
702 unsigned int queued = 0;
703 int csum_flags, fcb_inserted = 0;
704
705 sc = ifp->if_softc;
706
707 TSEC_TRANSMIT_LOCK_ASSERT(sc);
708
709 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
710 IFF_DRV_RUNNING)
711 return;
712
713 if (sc->tsec_link == 0)
714 return;
715
716 bus_dmamap_sync(sc->tsec_tx_dtag, sc->tsec_tx_dmap,
717 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
718
719 for (;;) {
720 /* Get packet from the queue */
721 IF_DEQUEUE(&ifp->if_snd, m0);
722 if (m0 == NULL)
723 break;
724
725 /* Insert TCP/IP Off-load frame control block */
726 csum_flags = m0->m_pkthdr.csum_flags;
727 if (csum_flags) {
728
729 M_PREPEND(m0, sizeof(struct tsec_tx_fcb), M_DONTWAIT);
730 if (m0 == NULL)
731 break;
732
733 tx_fcb = mtod(m0, struct tsec_tx_fcb *);
734 tx_fcb->flags = 0;
735 tx_fcb->l3_offset = ETHER_HDR_LEN;
736 tx_fcb->l4_offset = sizeof(struct ip);
737
738 if (csum_flags & CSUM_IP)
739 tx_fcb->flags |= TSEC_TX_FCB_IP4 |
740 TSEC_TX_FCB_CSUM_IP;
741
742 if (csum_flags & CSUM_TCP)
743 tx_fcb->flags |= TSEC_TX_FCB_TCP |
744 TSEC_TX_FCB_CSUM_TCP_UDP;
745
746 if (csum_flags & CSUM_UDP)
747 tx_fcb->flags |= TSEC_TX_FCB_UDP |
748 TSEC_TX_FCB_CSUM_TCP_UDP;
749
750 fcb_inserted = 1;
751 }
752
753 mtmp = m_defrag(m0, M_DONTWAIT);
754 if (mtmp)
755 m0 = mtmp;
756
757 if (tsec_encap(sc, m0, fcb_inserted)) {
758 IF_PREPEND(&ifp->if_snd, m0);
759 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
760 break;
761 }
762 queued++;
763 BPF_MTAP(ifp, m0);
764 }
765 bus_dmamap_sync(sc->tsec_tx_dtag, sc->tsec_tx_dmap,
766 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
767
768 if (queued) {
769 /* Enable transmitter and watchdog timer */
770 TSEC_WRITE(sc, TSEC_REG_TSTAT, TSEC_TSTAT_THLT);
771 sc->tsec_watchdog = 5;
772 }
773}
774
775static int
776tsec_encap(struct tsec_softc *sc, struct mbuf *m0, int fcb_inserted)
777{
778 struct tsec_desc *tx_desc = NULL;
779 struct ifnet *ifp;
780 bus_dma_segment_t segs[TSEC_TX_NUM_DESC];
781 bus_dmamap_t *mapp;
782 int csum_flag = 0, error, seg, nsegs;
783
784 TSEC_TRANSMIT_LOCK_ASSERT(sc);
785
786 ifp = sc->tsec_ifp;
787
788 if (TSEC_FREE_TX_DESC(sc) == 0) {
789 /* No free descriptors */
790 return (-1);
791 }
792
793 /* Fetch unused map */
794 mapp = TSEC_ALLOC_TX_MAP(sc);
795
796 /* Create mapping in DMA memory */
797 error = bus_dmamap_load_mbuf_sg(sc->tsec_tx_mtag,
798 *mapp, m0, segs, &nsegs, BUS_DMA_NOWAIT);
799 if (error != 0 || nsegs > TSEC_FREE_TX_DESC(sc) || nsegs <= 0) {
800 bus_dmamap_unload(sc->tsec_tx_mtag, *mapp);
801 TSEC_FREE_TX_MAP(sc, mapp);
802 return ((error != 0) ? error : -1);
803 }
804 bus_dmamap_sync(sc->tsec_tx_mtag, *mapp, BUS_DMASYNC_PREWRITE);
805
806 if ((ifp->if_flags & IFF_DEBUG) && (nsegs > 1))
807 if_printf(ifp, "TX buffer has %d segments\n", nsegs);
808
809 if (fcb_inserted)
810 csum_flag = TSEC_TXBD_TOE;
811
812 /* Everything is ok, now we can send buffers */
813 for (seg = 0; seg < nsegs; seg++) {
814 tx_desc = TSEC_GET_CUR_TX_DESC(sc);
815
816 tx_desc->length = segs[seg].ds_len;
817 tx_desc->bufptr = segs[seg].ds_addr;
818
819 /*
820 * Set flags:
821 * - wrap
822 * - checksum
823 * - ready to send
824 * - transmit the CRC sequence after the last data byte
825 * - interrupt after the last buffer
826 */
827 tx_desc->flags =
828 (tx_desc->flags & TSEC_TXBD_W) |
829 ((seg == 0) ? csum_flag : 0) | TSEC_TXBD_R | TSEC_TXBD_TC |
830 ((seg == nsegs - 1) ? TSEC_TXBD_L | TSEC_TXBD_I : 0);
831 }
832
833 /* Save mbuf and DMA mapping for release at later stage */
834 TSEC_PUT_TX_MBUF(sc, m0);
835 TSEC_PUT_TX_MAP(sc, mapp);
836
837 return (0);
838}
839
840static void
841tsec_setfilter(struct tsec_softc *sc)
842{
843 struct ifnet *ifp;
844 uint32_t flags;
845
846 ifp = sc->tsec_ifp;
847 flags = TSEC_READ(sc, TSEC_REG_RCTRL);
848
849 /* Promiscuous mode */
850 if (ifp->if_flags & IFF_PROMISC)
851 flags |= TSEC_RCTRL_PROM;
852 else
853 flags &= ~TSEC_RCTRL_PROM;
854
855 TSEC_WRITE(sc, TSEC_REG_RCTRL, flags);
856}
857
858#ifdef DEVICE_POLLING
859static poll_handler_t tsec_poll;
860
861static int
862tsec_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
863{
864 uint32_t ie;
865 struct tsec_softc *sc = ifp->if_softc;
866 int rx_npkts;
867
868 rx_npkts = 0;
869
870 TSEC_GLOBAL_LOCK(sc);
871 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
872 TSEC_GLOBAL_UNLOCK(sc);
873 return (rx_npkts);
874 }
875
876 if (cmd == POLL_AND_CHECK_STATUS) {
877 tsec_error_intr_locked(sc, count);
878
879 /* Clear all events reported */
880 ie = TSEC_READ(sc, TSEC_REG_IEVENT);
881 TSEC_WRITE(sc, TSEC_REG_IEVENT, ie);
882 }
883
884 tsec_transmit_intr_locked(sc);
885
886 TSEC_GLOBAL_TO_RECEIVE_LOCK(sc);
887
888 rx_npkts = tsec_receive_intr_locked(sc, count);
889
890 TSEC_RECEIVE_UNLOCK(sc);
891
892 return (rx_npkts);
893}
894#endif /* DEVICE_POLLING */
895
896static int
897tsec_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
898{
899 struct tsec_softc *sc = ifp->if_softc;
900 struct ifreq *ifr = (struct ifreq *)data;
901 device_t dev;
902 int mask, error = 0;
903
904 dev = sc->dev;
905
906 switch (command) {
907 case SIOCSIFMTU:
908 TSEC_GLOBAL_LOCK(sc);
909 if (tsec_set_mtu(sc, ifr->ifr_mtu))
910 ifp->if_mtu = ifr->ifr_mtu;
911 else
912 error = EINVAL;
913 TSEC_GLOBAL_UNLOCK(sc);
914 break;
915 case SIOCSIFFLAGS:
916 TSEC_GLOBAL_LOCK(sc);
917 if (ifp->if_flags & IFF_UP) {
918 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
919 if ((sc->tsec_if_flags ^ ifp->if_flags) &
920 IFF_PROMISC)
921 tsec_setfilter(sc);
922
923 if ((sc->tsec_if_flags ^ ifp->if_flags) &
924 IFF_ALLMULTI)
925 tsec_setup_multicast(sc);
926 } else
927 tsec_init_locked(sc);
928 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING)
929 tsec_stop(sc);
930
931 sc->tsec_if_flags = ifp->if_flags;
932 TSEC_GLOBAL_UNLOCK(sc);
933 break;
934 case SIOCADDMULTI:
935 case SIOCDELMULTI:
936 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
937 TSEC_GLOBAL_LOCK(sc);
938 tsec_setup_multicast(sc);
939 TSEC_GLOBAL_UNLOCK(sc);
940 }
941 case SIOCGIFMEDIA:
942 case SIOCSIFMEDIA:
943 error = ifmedia_ioctl(ifp, ifr, &sc->tsec_mii->mii_media,
944 command);
945 break;
946 case SIOCSIFCAP:
947 mask = ifp->if_capenable ^ ifr->ifr_reqcap;
948 if ((mask & IFCAP_HWCSUM) && sc->is_etsec) {
949 TSEC_GLOBAL_LOCK(sc);
950 ifp->if_capenable &= ~IFCAP_HWCSUM;
951 ifp->if_capenable |= IFCAP_HWCSUM & ifr->ifr_reqcap;
952 tsec_offload_setup(sc);
953 TSEC_GLOBAL_UNLOCK(sc);
954 }
955#ifdef DEVICE_POLLING
956 if (mask & IFCAP_POLLING) {
957 if (ifr->ifr_reqcap & IFCAP_POLLING) {
958 error = ether_poll_register(tsec_poll, ifp);
959 if (error)
960 return (error);
961
962 TSEC_GLOBAL_LOCK(sc);
963 /* Disable interrupts */
964 tsec_intrs_ctl(sc, 0);
965 ifp->if_capenable |= IFCAP_POLLING;
966 TSEC_GLOBAL_UNLOCK(sc);
967 } else {
968 error = ether_poll_deregister(ifp);
969 TSEC_GLOBAL_LOCK(sc);
970 /* Enable interrupts */
971 tsec_intrs_ctl(sc, 1);
972 ifp->if_capenable &= ~IFCAP_POLLING;
973 TSEC_GLOBAL_UNLOCK(sc);
974 }
975 }
976#endif
977 break;
978
979 default:
980 error = ether_ioctl(ifp, command, data);
981 }
982
983 /* Flush buffers if not empty */
984 if (ifp->if_flags & IFF_UP)
985 tsec_start(ifp);
986 return (error);
987}
988
989static int
990tsec_ifmedia_upd(struct ifnet *ifp)
991{
992 struct tsec_softc *sc = ifp->if_softc;
993 struct mii_data *mii;
994
995 TSEC_TRANSMIT_LOCK(sc);
996
997 mii = sc->tsec_mii;
998 mii_mediachg(mii);
999
1000 TSEC_TRANSMIT_UNLOCK(sc);
1001 return (0);
1002}
1003
1004static void
1005tsec_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1006{
1007 struct tsec_softc *sc = ifp->if_softc;
1008 struct mii_data *mii;
1009
1010 TSEC_TRANSMIT_LOCK(sc);
1011
1012 mii = sc->tsec_mii;
1013 mii_pollstat(mii);
1014
1015 ifmr->ifm_active = mii->mii_media_active;
1016 ifmr->ifm_status = mii->mii_media_status;
1017
1018 TSEC_TRANSMIT_UNLOCK(sc);
1019}
1020
1021static int
1022tsec_new_rxbuf(bus_dma_tag_t tag, bus_dmamap_t map, struct mbuf **mbufp,
1023 uint32_t *paddr)
1024{
1025 struct mbuf *new_mbuf;
1026 bus_dma_segment_t seg[1];
1027 int error, nsegs;
1028
1029 KASSERT(mbufp != NULL, ("NULL mbuf pointer!"));
1030
1031 new_mbuf = m_getjcl(M_DONTWAIT, MT_DATA, M_PKTHDR, MCLBYTES);
1032 if (new_mbuf == NULL)
1033 return (ENOBUFS);
1034 new_mbuf->m_len = new_mbuf->m_pkthdr.len = new_mbuf->m_ext.ext_size;
1035
1036 if (*mbufp) {
1037 bus_dmamap_sync(tag, map, BUS_DMASYNC_POSTREAD);
1038 bus_dmamap_unload(tag, map);
1039 }
1040
1041 error = bus_dmamap_load_mbuf_sg(tag, map, new_mbuf, seg, &nsegs,
1042 BUS_DMA_NOWAIT);
1043 KASSERT(nsegs == 1, ("Too many segments returned!"));
1044 if (nsegs != 1 || error)
1045 panic("tsec_new_rxbuf(): nsegs(%d), error(%d)", nsegs, error);
1046
1047#if 0
1048 if (error) {
1049 printf("tsec: bus_dmamap_load_mbuf_sg() returned: %d!\n",
1050 error);
1051 m_freem(new_mbuf);
1052 return (ENOBUFS);
1053 }
1054#endif
1055
1056#if 0
1057 KASSERT(((seg->ds_addr) & (TSEC_RXBUFFER_ALIGNMENT-1)) == 0,
1058 ("Wrong alignment of RX buffer!"));
1059#endif
1060 bus_dmamap_sync(tag, map, BUS_DMASYNC_PREREAD);
1061
1062 (*mbufp) = new_mbuf;
1063 (*paddr) = seg->ds_addr;
1064 return (0);
1065}
1066
1067static void
1068tsec_map_dma_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
1069{
1070 u_int32_t *paddr;
1071
1072 KASSERT(nseg == 1, ("wrong number of segments, should be 1"));
1073 paddr = arg;
1074 *paddr = segs->ds_addr;
1075}
1076
1077static int
1078tsec_alloc_dma_desc(device_t dev, bus_dma_tag_t *dtag, bus_dmamap_t *dmap,
1079 bus_size_t dsize, void **vaddr, void *raddr, const char *dname)
1080{
1081 int error;
1082
1083 /* Allocate a busdma tag and DMA safe memory for TX/RX descriptors. */
1084 error = bus_dma_tag_create(NULL, /* parent */
1085 PAGE_SIZE, 0, /* alignment, boundary */
1086 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
1087 BUS_SPACE_MAXADDR, /* highaddr */
1088 NULL, NULL, /* filtfunc, filtfuncarg */
1089 dsize, 1, /* maxsize, nsegments */
1090 dsize, 0, /* maxsegsz, flags */
1091 NULL, NULL, /* lockfunc, lockfuncarg */
1092 dtag); /* dmat */
1093
1094 if (error) {
1095 device_printf(dev, "failed to allocate busdma %s tag\n",
1096 dname);
1097 (*vaddr) = NULL;
1098 return (ENXIO);
1099 }
1100
1101 error = bus_dmamem_alloc(*dtag, vaddr, BUS_DMA_NOWAIT | BUS_DMA_ZERO,
1102 dmap);
1103 if (error) {
1104 device_printf(dev, "failed to allocate %s DMA safe memory\n",
1105 dname);
1106 bus_dma_tag_destroy(*dtag);
1107 (*vaddr) = NULL;
1108 return (ENXIO);
1109 }
1110
1111 error = bus_dmamap_load(*dtag, *dmap, *vaddr, dsize,
1112 tsec_map_dma_addr, raddr, BUS_DMA_NOWAIT);
1113 if (error) {
1114 device_printf(dev, "cannot get address of the %s "
1115 "descriptors\n", dname);
1116 bus_dmamem_free(*dtag, *vaddr, *dmap);
1117 bus_dma_tag_destroy(*dtag);
1118 (*vaddr) = NULL;
1119 return (ENXIO);
1120 }
1121
1122 return (0);
1123}
1124
1125static void
1126tsec_free_dma_desc(bus_dma_tag_t dtag, bus_dmamap_t dmap, void *vaddr)
1127{
1128
1129 if (vaddr == NULL)
1130 return;
1131
1132 /* Unmap descriptors from DMA memory */
1133 bus_dmamap_sync(dtag, dmap, BUS_DMASYNC_POSTREAD |
1134 BUS_DMASYNC_POSTWRITE);
1135 bus_dmamap_unload(dtag, dmap);
1136
1137 /* Free descriptors memory */
1138 bus_dmamem_free(dtag, vaddr, dmap);
1139
1140 /* Destroy descriptors tag */
1141 bus_dma_tag_destroy(dtag);
1142}
1143
1144static void
1145tsec_free_dma(struct tsec_softc *sc)
1146{
1147 int i;
1148
1149 /* Free TX maps */
1150 for (i = 0; i < TSEC_TX_NUM_DESC; i++)
1151 if (sc->tx_map_data[i] != NULL)
1152 bus_dmamap_destroy(sc->tsec_tx_mtag,
1153 sc->tx_map_data[i]);
1154 /* Destroy tag for TX mbufs */
1155 bus_dma_tag_destroy(sc->tsec_tx_mtag);
1156
1157 /* Free RX mbufs and maps */
1158 for (i = 0; i < TSEC_RX_NUM_DESC; i++) {
1159 if (sc->rx_data[i].mbuf) {
1160 /* Unload buffer from DMA */
1161 bus_dmamap_sync(sc->tsec_rx_mtag, sc->rx_data[i].map,
1162 BUS_DMASYNC_POSTREAD);
1163 bus_dmamap_unload(sc->tsec_rx_mtag,
1164 sc->rx_data[i].map);
1165
1166 /* Free buffer */
1167 m_freem(sc->rx_data[i].mbuf);
1168 }
1169 /* Destroy map for this buffer */
1170 if (sc->rx_data[i].map != NULL)
1171 bus_dmamap_destroy(sc->tsec_rx_mtag,
1172 sc->rx_data[i].map);
1173 }
1174 /* Destroy tag for RX mbufs */
1175 bus_dma_tag_destroy(sc->tsec_rx_mtag);
1176
1177 /* Unload TX/RX descriptors */
1178 tsec_free_dma_desc(sc->tsec_tx_dtag, sc->tsec_tx_dmap,
1179 sc->tsec_tx_vaddr);
1180 tsec_free_dma_desc(sc->tsec_rx_dtag, sc->tsec_rx_dmap,
1181 sc->tsec_rx_vaddr);
1182}
1183
1184static void
1185tsec_stop(struct tsec_softc *sc)
1186{
1187 struct ifnet *ifp;
1188 struct mbuf *m0;
1189 bus_dmamap_t *mapp;
1190 uint32_t tmpval;
1191
1192 TSEC_GLOBAL_LOCK_ASSERT(sc);
1193
1194 ifp = sc->tsec_ifp;
1195
1196 /* Disable interface and watchdog timer */
1197 callout_stop(&sc->tsec_callout);
1198 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
1199 sc->tsec_watchdog = 0;
1200
1201 /* Disable all interrupts and stop DMA */
1202 tsec_intrs_ctl(sc, 0);
1203 tsec_dma_ctl(sc, 0);
1204
1205 /* Remove pending data from TX queue */
1206 while (!TSEC_EMPTYQ_TX_MBUF(sc)) {
1207 m0 = TSEC_GET_TX_MBUF(sc);
1208 mapp = TSEC_GET_TX_MAP(sc);
1209
1210 bus_dmamap_sync(sc->tsec_tx_mtag, *mapp,
1211 BUS_DMASYNC_POSTWRITE);
1212 bus_dmamap_unload(sc->tsec_tx_mtag, *mapp);
1213
1214 TSEC_FREE_TX_MAP(sc, mapp);
1215 m_freem(m0);
1216 }
1217
1218 /* Disable RX and TX */
1219 tmpval = TSEC_READ(sc, TSEC_REG_MACCFG1);
1220 tmpval &= ~(TSEC_MACCFG1_RX_EN | TSEC_MACCFG1_TX_EN);
1221 TSEC_WRITE(sc, TSEC_REG_MACCFG1, tmpval);
1222 DELAY(10);
1223}
1224
1225static void
1226tsec_tick(void *arg)
1227{
1228 struct tsec_softc *sc = arg;
1229 struct ifnet *ifp;
1230 int link;
1231
1232 TSEC_GLOBAL_LOCK(sc);
1233
1234 tsec_watchdog(sc);
1235
1236 ifp = sc->tsec_ifp;
1237 link = sc->tsec_link;
1238
1239 mii_tick(sc->tsec_mii);
1240
1241 if (link == 0 && sc->tsec_link == 1 &&
1242 (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)))
1243 tsec_start_locked(ifp);
1244
1245 /* Schedule another timeout one second from now. */
1246 callout_reset(&sc->tsec_callout, hz, tsec_tick, sc);
1247
1248 TSEC_GLOBAL_UNLOCK(sc);
1249}
1250
1251/*
1252 * This is the core RX routine. It replenishes mbufs in the descriptor and
1253 * sends data which have been dma'ed into host memory to upper layer.
1254 *
1255 * Loops at most count times if count is > 0, or until done if count < 0.
1256 */
1257static int
1258tsec_receive_intr_locked(struct tsec_softc *sc, int count)
1259{
1260 struct tsec_desc *rx_desc;
1261 struct ifnet *ifp;
1262 struct rx_data_type *rx_data;
1263 struct mbuf *m;
1264 device_t dev;
1265 uint32_t i;
1266 int c, rx_npkts;
1267 uint16_t flags;
1268
1269 TSEC_RECEIVE_LOCK_ASSERT(sc);
1270
1271 ifp = sc->tsec_ifp;
1272 rx_data = sc->rx_data;
1273 dev = sc->dev;
1274 rx_npkts = 0;
1275
1276 bus_dmamap_sync(sc->tsec_rx_dtag, sc->tsec_rx_dmap,
1277 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1278
1279 for (c = 0; ; c++) {
1280 if (count >= 0 && count-- == 0)
1281 break;
1282
1283 rx_desc = TSEC_GET_CUR_RX_DESC(sc);
1284 flags = rx_desc->flags;
1285
1286 /* Check if there is anything to receive */
1287 if ((flags & TSEC_RXBD_E) || (c >= TSEC_RX_NUM_DESC)) {
1288 /*
1289 * Avoid generating another interrupt
1290 */
1291 if (flags & TSEC_RXBD_E)
1292 TSEC_WRITE(sc, TSEC_REG_IEVENT,
1293 TSEC_IEVENT_RXB | TSEC_IEVENT_RXF);
1294 /*
1295 * We didn't consume current descriptor and have to
1296 * return it to the queue
1297 */
1298 TSEC_BACK_CUR_RX_DESC(sc);
1299 break;
1300 }
1301
1302 if (flags & (TSEC_RXBD_LG | TSEC_RXBD_SH | TSEC_RXBD_NO |
1303 TSEC_RXBD_CR | TSEC_RXBD_OV | TSEC_RXBD_TR)) {
1304
1305 rx_desc->length = 0;
1306 rx_desc->flags = (rx_desc->flags &
1307 ~TSEC_RXBD_ZEROONINIT) | TSEC_RXBD_E | TSEC_RXBD_I;
1308
1309 if (sc->frame != NULL) {
1310 m_free(sc->frame);
1311 sc->frame = NULL;
1312 }
1313
1314 continue;
1315 }
1316
1317 /* Ok... process frame */
1318 i = TSEC_GET_CUR_RX_DESC_CNT(sc);
1319 m = rx_data[i].mbuf;
1320 m->m_len = rx_desc->length;
1321
1322 if (sc->frame != NULL) {
1323 if ((flags & TSEC_RXBD_L) != 0)
1324 m->m_len -= m_length(sc->frame, NULL);
1325
1326 m->m_flags &= ~M_PKTHDR;
1327 m_cat(sc->frame, m);
1328 } else {
1329 sc->frame = m;
1330 }
1331
1332 m = NULL;
1333
1334 if ((flags & TSEC_RXBD_L) != 0) {
1335 m = sc->frame;
1336 sc->frame = NULL;
1337 }
1338
1339 if (tsec_new_rxbuf(sc->tsec_rx_mtag, rx_data[i].map,
1340 &rx_data[i].mbuf, &rx_data[i].paddr)) {
1341 ifp->if_ierrors++;
1342 /*
1343 * We ran out of mbufs; didn't consume current
1344 * descriptor and have to return it to the queue.
1345 */
1346 TSEC_BACK_CUR_RX_DESC(sc);
1347 break;
1348 }
1349
1350 /* Attach new buffer to descriptor and clear flags */
1351 rx_desc->bufptr = rx_data[i].paddr;
1352 rx_desc->length = 0;
1353 rx_desc->flags = (rx_desc->flags & ~TSEC_RXBD_ZEROONINIT) |
1354 TSEC_RXBD_E | TSEC_RXBD_I;
1355
1356 if (m != NULL) {
1357 m->m_pkthdr.rcvif = ifp;
1358
1359 m_fixhdr(m);
1360 m_adj(m, -ETHER_CRC_LEN);
1361
1362 if (sc->is_etsec)
1363 tsec_offload_process_frame(sc, m);
1364
1365 TSEC_RECEIVE_UNLOCK(sc);
1366 (*ifp->if_input)(ifp, m);
1367 TSEC_RECEIVE_LOCK(sc);
1368 rx_npkts++;
1369 }
1370 }
1371
1372 bus_dmamap_sync(sc->tsec_rx_dtag, sc->tsec_rx_dmap,
1373 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1374
1375 /*
1376 * Make sure TSEC receiver is not halted.
1377 *
1378 * Various conditions can stop the TSEC receiver, but not all are
1379 * signaled and handled by error interrupt, so make sure the receiver
1380 * is running. Writing to TSEC_REG_RSTAT restarts the receiver when
1381 * halted, and is harmless if already running.
1382 */
1383 TSEC_WRITE(sc, TSEC_REG_RSTAT, TSEC_RSTAT_QHLT);
1384 return (rx_npkts);
1385}
1386
1387void
1388tsec_receive_intr(void *arg)
1389{
1390 struct tsec_softc *sc = arg;
1391
1392 TSEC_RECEIVE_LOCK(sc);
1393
1394#ifdef DEVICE_POLLING
1395 if (sc->tsec_ifp->if_capenable & IFCAP_POLLING) {
1396 TSEC_RECEIVE_UNLOCK(sc);
1397 return;
1398 }
1399#endif
1400
1401 /* Confirm the interrupt was received by driver */
1402 TSEC_WRITE(sc, TSEC_REG_IEVENT, TSEC_IEVENT_RXB | TSEC_IEVENT_RXF);
1403 tsec_receive_intr_locked(sc, -1);
1404
1405 TSEC_RECEIVE_UNLOCK(sc);
1406}
1407
1408static void
1409tsec_transmit_intr_locked(struct tsec_softc *sc)
1410{
1411 struct tsec_desc *tx_desc;
1412 struct ifnet *ifp;
1413 struct mbuf *m0;
1414 bus_dmamap_t *mapp;
1415 int send = 0;
1416
1417 TSEC_TRANSMIT_LOCK_ASSERT(sc);
1418
1419 ifp = sc->tsec_ifp;
1420
1421 /* Update collision statistics */
1422 ifp->if_collisions += TSEC_READ(sc, TSEC_REG_MON_TNCL);
1423
1424 /* Reset collision counters in hardware */
1425 TSEC_WRITE(sc, TSEC_REG_MON_TSCL, 0);
1426 TSEC_WRITE(sc, TSEC_REG_MON_TMCL, 0);
1427 TSEC_WRITE(sc, TSEC_REG_MON_TLCL, 0);
1428 TSEC_WRITE(sc, TSEC_REG_MON_TXCL, 0);
1429 TSEC_WRITE(sc, TSEC_REG_MON_TNCL, 0);
1430
1431 bus_dmamap_sync(sc->tsec_tx_dtag, sc->tsec_tx_dmap,
1432 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1433
1434 while (TSEC_CUR_DIFF_DIRTY_TX_DESC(sc)) {
1435 tx_desc = TSEC_GET_DIRTY_TX_DESC(sc);
1436 if (tx_desc->flags & TSEC_TXBD_R) {
1437 TSEC_BACK_DIRTY_TX_DESC(sc);
1438 break;
1439 }
1440
1441 if ((tx_desc->flags & TSEC_TXBD_L) == 0)
1442 continue;
1443
1444 /*
1445 * This is the last buf in this packet, so unmap and free it.
1446 */
1447 m0 = TSEC_GET_TX_MBUF(sc);
1448 mapp = TSEC_GET_TX_MAP(sc);
1449
1450 bus_dmamap_sync(sc->tsec_tx_mtag, *mapp,
1451 BUS_DMASYNC_POSTWRITE);
1452 bus_dmamap_unload(sc->tsec_tx_mtag, *mapp);
1453
1454 TSEC_FREE_TX_MAP(sc, mapp);
1455 m_freem(m0);
1456
1457 ifp->if_opackets++;
1458 send = 1;
1459 }
1460 bus_dmamap_sync(sc->tsec_tx_dtag, sc->tsec_tx_dmap,
1461 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1462
1463 if (send) {
1464 /* Now send anything that was pending */
1465 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1466 tsec_start_locked(ifp);
1467
1468 /* Stop wathdog if all sent */
1469 if (TSEC_EMPTYQ_TX_MBUF(sc))
1470 sc->tsec_watchdog = 0;
1471 }
1472}
1473
1474void
1475tsec_transmit_intr(void *arg)
1476{
1477 struct tsec_softc *sc = arg;
1478
1479 TSEC_TRANSMIT_LOCK(sc);
1480
1481#ifdef DEVICE_POLLING
1482 if (sc->tsec_ifp->if_capenable & IFCAP_POLLING) {
1483 TSEC_TRANSMIT_UNLOCK(sc);
1484 return;
1485 }
1486#endif
1487 /* Confirm the interrupt was received by driver */
1488 TSEC_WRITE(sc, TSEC_REG_IEVENT, TSEC_IEVENT_TXB | TSEC_IEVENT_TXF);
1489 tsec_transmit_intr_locked(sc);
1490
1491 TSEC_TRANSMIT_UNLOCK(sc);
1492}
1493
1494static void
1495tsec_error_intr_locked(struct tsec_softc *sc, int count)
1496{
1497 struct ifnet *ifp;
1498 uint32_t eflags;
1499
1500 TSEC_GLOBAL_LOCK_ASSERT(sc);
1501
1502 ifp = sc->tsec_ifp;
1503
1504 eflags = TSEC_READ(sc, TSEC_REG_IEVENT);
1505
1506 /* Clear events bits in hardware */
1507 TSEC_WRITE(sc, TSEC_REG_IEVENT, TSEC_IEVENT_RXC | TSEC_IEVENT_BSY |
1508 TSEC_IEVENT_EBERR | TSEC_IEVENT_MSRO | TSEC_IEVENT_BABT |
1509 TSEC_IEVENT_TXC | TSEC_IEVENT_TXE | TSEC_IEVENT_LC |
1510 TSEC_IEVENT_CRL | TSEC_IEVENT_XFUN);
1511
1512 /* Check transmitter errors */
1513 if (eflags & TSEC_IEVENT_TXE) {
1514 ifp->if_oerrors++;
1515
1516 if (eflags & TSEC_IEVENT_LC)
1517 ifp->if_collisions++;
1518
1519 TSEC_WRITE(sc, TSEC_REG_TSTAT, TSEC_TSTAT_THLT);
1520 }
1521
1522 /* Check receiver errors */
1523 if (eflags & TSEC_IEVENT_BSY) {
1524 ifp->if_ierrors++;
1525 ifp->if_iqdrops++;
1526
1527 /* Get data from RX buffers */
1528 tsec_receive_intr_locked(sc, count);
1529 }
1530
1531 if (ifp->if_flags & IFF_DEBUG)
1532 if_printf(ifp, "tsec_error_intr(): event flags: 0x%x\n",
1533 eflags);
1534
1535 if (eflags & TSEC_IEVENT_EBERR) {
1536 if_printf(ifp, "System bus error occurred during"
1537 "DMA transaction (flags: 0x%x)\n", eflags);
1538 tsec_init_locked(sc);
1539 }
1540
1541 if (eflags & TSEC_IEVENT_BABT)
1542 ifp->if_oerrors++;
1543
1544 if (eflags & TSEC_IEVENT_BABR)
1545 ifp->if_ierrors++;
1546}
1547
1548void
1549tsec_error_intr(void *arg)
1550{
1551 struct tsec_softc *sc = arg;
1552
1553 TSEC_GLOBAL_LOCK(sc);
1554 tsec_error_intr_locked(sc, -1);
1555 TSEC_GLOBAL_UNLOCK(sc);
1556}
1557
1558int
1559tsec_miibus_readreg(device_t dev, int phy, int reg)
1560{
1561 struct tsec_softc *sc;
1562 uint32_t timeout;
1563
1564 sc = device_get_softc(dev);
1565
1566 if (device_get_unit(dev) != phy)
1567 return (0);
1568
1569 sc = tsec0_sc;
1570
1571 TSEC_WRITE(sc, TSEC_REG_MIIMADD, (phy << 8) | reg);
1572 TSEC_WRITE(sc, TSEC_REG_MIIMCOM, 0);
1573 TSEC_WRITE(sc, TSEC_REG_MIIMCOM, TSEC_MIIMCOM_READCYCLE);
1574
1575 timeout = TSEC_READ_RETRY;
1576 while (--timeout && TSEC_READ(sc, TSEC_REG_MIIMIND) &
1577 (TSEC_MIIMIND_NOTVALID | TSEC_MIIMIND_BUSY))
1578 DELAY(TSEC_READ_DELAY);
1579
1580 if (timeout == 0)
1581 device_printf(dev, "Timeout while reading from PHY!\n");
1582
1583 return (TSEC_READ(sc, TSEC_REG_MIIMSTAT));
1584}
1585
|
1612}
1613
1614void
1615tsec_miibus_statchg(device_t dev)
1616{
1617 struct tsec_softc *sc;
1618 struct mii_data *mii;
1619 uint32_t ecntrl, id, tmp;
1620 int link;
1621
1622 sc = device_get_softc(dev);
1623 mii = sc->tsec_mii;
1624 link = ((mii->mii_media_status & IFM_ACTIVE) ? 1 : 0);
1625
1626 tmp = TSEC_READ(sc, TSEC_REG_MACCFG2) & ~TSEC_MACCFG2_IF;
1627
1628 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX)
1629 tmp |= TSEC_MACCFG2_FULLDUPLEX;
1630 else
1631 tmp &= ~TSEC_MACCFG2_FULLDUPLEX;
1632
1633 switch (IFM_SUBTYPE(mii->mii_media_active)) {
1634 case IFM_1000_T:
1635 case IFM_1000_SX:
1636 tmp |= TSEC_MACCFG2_GMII;
1637 sc->tsec_link = link;
1638 break;
1639 case IFM_100_TX:
1640 case IFM_10_T:
1641 tmp |= TSEC_MACCFG2_MII;
1642 sc->tsec_link = link;
1643 break;
1644 case IFM_NONE:
1645 if (link)
1646 device_printf(dev, "No speed selected but link "
1647 "active!\n");
1648 sc->tsec_link = 0;
1649 return;
1650 default:
1651 sc->tsec_link = 0;
1652 device_printf(dev, "Unknown speed (%d), link %s!\n",
1653 IFM_SUBTYPE(mii->mii_media_active),
1654 ((link) ? "up" : "down"));
1655 return;
1656 }
1657 TSEC_WRITE(sc, TSEC_REG_MACCFG2, tmp);
1658
1659 /* XXX kludge - use circumstantial evidence for reduced mode. */
1660 id = TSEC_READ(sc, TSEC_REG_ID2);
1661 if (id & 0xffff) {
1662 ecntrl = TSEC_READ(sc, TSEC_REG_ECNTRL) & ~TSEC_ECNTRL_R100M;
1663 ecntrl |= (tmp & TSEC_MACCFG2_MII) ? TSEC_ECNTRL_R100M : 0;
1664 TSEC_WRITE(sc, TSEC_REG_ECNTRL, ecntrl);
1665 }
1666}
1667
1668static void
1669tsec_add_sysctls(struct tsec_softc *sc)
1670{
1671 struct sysctl_ctx_list *ctx;
1672 struct sysctl_oid_list *children;
1673 struct sysctl_oid *tree;
1674
1675 ctx = device_get_sysctl_ctx(sc->dev);
1676 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev));
1677 tree = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "int_coal",
1678 CTLFLAG_RD, 0, "TSEC Interrupts coalescing");
1679 children = SYSCTL_CHILDREN(tree);
1680
1681 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rx_time",
1682 CTLTYPE_UINT | CTLFLAG_RW, sc, TSEC_IC_RX, tsec_sysctl_ic_time,
1683 "I", "IC RX time threshold (0-65535)");
1684 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rx_count",
1685 CTLTYPE_UINT | CTLFLAG_RW, sc, TSEC_IC_RX, tsec_sysctl_ic_count,
1686 "I", "IC RX frame count threshold (0-255)");
1687
1688 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_time",
1689 CTLTYPE_UINT | CTLFLAG_RW, sc, TSEC_IC_TX, tsec_sysctl_ic_time,
1690 "I", "IC TX time threshold (0-65535)");
1691 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_count",
1692 CTLTYPE_UINT | CTLFLAG_RW, sc, TSEC_IC_TX, tsec_sysctl_ic_count,
1693 "I", "IC TX frame count threshold (0-255)");
1694}
1695
1696/*
1697 * With Interrupt Coalescing (IC) active, a transmit/receive frame
1698 * interrupt is raised either upon:
1699 *
1700 * - threshold-defined period of time elapsed, or
1701 * - threshold-defined number of frames is received/transmitted,
1702 * whichever occurs first.
1703 *
1704 * The following sysctls regulate IC behaviour (for TX/RX separately):
1705 *
1706 * dev.tsec.<unit>.int_coal.rx_time
1707 * dev.tsec.<unit>.int_coal.rx_count
1708 * dev.tsec.<unit>.int_coal.tx_time
1709 * dev.tsec.<unit>.int_coal.tx_count
1710 *
1711 * Values:
1712 *
1713 * - 0 for either time or count disables IC on the given TX/RX path
1714 *
1715 * - count: 1-255 (expresses frame count number; note that value of 1 is
1716 * effectively IC off)
1717 *
1718 * - time: 1-65535 (value corresponds to a real time period and is
1719 * expressed in units equivalent to 64 TSEC interface clocks, i.e. one timer
1720 * threshold unit is 26.5 us, 2.56 us, or 512 ns, corresponding to 10 Mbps,
1721 * 100 Mbps, or 1Gbps, respectively. For detailed discussion consult the
1722 * TSEC reference manual.
1723 */
1724static int
1725tsec_sysctl_ic_time(SYSCTL_HANDLER_ARGS)
1726{
1727 int error;
1728 uint32_t time;
1729 struct tsec_softc *sc = (struct tsec_softc *)arg1;
1730
1731 time = (arg2 == TSEC_IC_RX) ? sc->rx_ic_time : sc->tx_ic_time;
1732
1733 error = sysctl_handle_int(oidp, &time, 0, req);
1734 if (error != 0)
1735 return (error);
1736
1737 if (time > 65535)
1738 return (EINVAL);
1739
1740 TSEC_IC_LOCK(sc);
1741 if (arg2 == TSEC_IC_RX) {
1742 sc->rx_ic_time = time;
1743 tsec_set_rxic(sc);
1744 } else {
1745 sc->tx_ic_time = time;
1746 tsec_set_txic(sc);
1747 }
1748 TSEC_IC_UNLOCK(sc);
1749
1750 return (0);
1751}
1752
1753static int
1754tsec_sysctl_ic_count(SYSCTL_HANDLER_ARGS)
1755{
1756 int error;
1757 uint32_t count;
1758 struct tsec_softc *sc = (struct tsec_softc *)arg1;
1759
1760 count = (arg2 == TSEC_IC_RX) ? sc->rx_ic_count : sc->tx_ic_count;
1761
1762 error = sysctl_handle_int(oidp, &count, 0, req);
1763 if (error != 0)
1764 return (error);
1765
1766 if (count > 255)
1767 return (EINVAL);
1768
1769 TSEC_IC_LOCK(sc);
1770 if (arg2 == TSEC_IC_RX) {
1771 sc->rx_ic_count = count;
1772 tsec_set_rxic(sc);
1773 } else {
1774 sc->tx_ic_count = count;
1775 tsec_set_txic(sc);
1776 }
1777 TSEC_IC_UNLOCK(sc);
1778
1779 return (0);
1780}
1781
1782static void
1783tsec_set_rxic(struct tsec_softc *sc)
1784{
1785 uint32_t rxic_val;
1786
1787 if (sc->rx_ic_count == 0 || sc->rx_ic_time == 0)
1788 /* Disable RX IC */
1789 rxic_val = 0;
1790 else {
1791 rxic_val = 0x80000000;
1792 rxic_val |= (sc->rx_ic_count << 21);
1793 rxic_val |= sc->rx_ic_time;
1794 }
1795
1796 TSEC_WRITE(sc, TSEC_REG_RXIC, rxic_val);
1797}
1798
1799static void
1800tsec_set_txic(struct tsec_softc *sc)
1801{
1802 uint32_t txic_val;
1803
1804 if (sc->tx_ic_count == 0 || sc->tx_ic_time == 0)
1805 /* Disable TX IC */
1806 txic_val = 0;
1807 else {
1808 txic_val = 0x80000000;
1809 txic_val |= (sc->tx_ic_count << 21);
1810 txic_val |= sc->tx_ic_time;
1811 }
1812
1813 TSEC_WRITE(sc, TSEC_REG_TXIC, txic_val);
1814}
1815
1816static void
1817tsec_offload_setup(struct tsec_softc *sc)
1818{
1819 struct ifnet *ifp = sc->tsec_ifp;
1820 uint32_t reg;
1821
1822 TSEC_GLOBAL_LOCK_ASSERT(sc);
1823
1824 reg = TSEC_READ(sc, TSEC_REG_TCTRL);
1825 reg |= TSEC_TCTRL_IPCSEN | TSEC_TCTRL_TUCSEN;
1826
1827 if (ifp->if_capenable & IFCAP_TXCSUM)
1828 ifp->if_hwassist = TSEC_CHECKSUM_FEATURES;
1829 else
1830 ifp->if_hwassist = 0;
1831
1832 TSEC_WRITE(sc, TSEC_REG_TCTRL, reg);
1833
1834 reg = TSEC_READ(sc, TSEC_REG_RCTRL);
1835 reg &= ~(TSEC_RCTRL_IPCSEN | TSEC_RCTRL_TUCSEN | TSEC_RCTRL_PRSDEP);
1836 reg |= TSEC_RCTRL_PRSDEP_PARSE_L2 | TSEC_RCTRL_VLEX;
1837
1838 if (ifp->if_capenable & IFCAP_RXCSUM)
1839 reg |= TSEC_RCTRL_IPCSEN | TSEC_RCTRL_TUCSEN |
1840 TSEC_RCTRL_PRSDEP_PARSE_L234;
1841
1842 TSEC_WRITE(sc, TSEC_REG_RCTRL, reg);
1843}
1844
1845
1846static void
1847tsec_offload_process_frame(struct tsec_softc *sc, struct mbuf *m)
1848{
1849 struct tsec_rx_fcb rx_fcb;
1850 int csum_flags = 0;
1851 int protocol, flags;
1852
1853 TSEC_RECEIVE_LOCK_ASSERT(sc);
1854
1855 m_copydata(m, 0, sizeof(struct tsec_rx_fcb), (caddr_t)(&rx_fcb));
1856 flags = rx_fcb.flags;
1857 protocol = rx_fcb.protocol;
1858
1859 if (TSEC_RX_FCB_IP_CSUM_CHECKED(flags)) {
1860 csum_flags |= CSUM_IP_CHECKED;
1861
1862 if ((flags & TSEC_RX_FCB_IP_CSUM_ERROR) == 0)
1863 csum_flags |= CSUM_IP_VALID;
1864 }
1865
1866 if ((protocol == IPPROTO_TCP || protocol == IPPROTO_UDP) &&
1867 TSEC_RX_FCB_TCP_UDP_CSUM_CHECKED(flags) &&
1868 (flags & TSEC_RX_FCB_TCP_UDP_CSUM_ERROR) == 0) {
1869
1870 csum_flags |= CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
1871 m->m_pkthdr.csum_data = 0xFFFF;
1872 }
1873
1874 m->m_pkthdr.csum_flags = csum_flags;
1875
1876 if (flags & TSEC_RX_FCB_VLAN) {
1877 m->m_pkthdr.ether_vtag = rx_fcb.vlan;
1878 m->m_flags |= M_VLANTAG;
1879 }
1880
1881 m_adj(m, sizeof(struct tsec_rx_fcb));
1882}
1883
1884static void
1885tsec_setup_multicast(struct tsec_softc *sc)
1886{
1887 uint32_t hashtable[8] = { 0, 0, 0, 0, 0, 0, 0, 0 };
1888 struct ifnet *ifp = sc->tsec_ifp;
1889 struct ifmultiaddr *ifma;
1890 uint32_t h;
1891 int i;
1892
1893 TSEC_GLOBAL_LOCK_ASSERT(sc);
1894
1895 if (ifp->if_flags & IFF_ALLMULTI) {
1896 for (i = 0; i < 8; i++)
1897 TSEC_WRITE(sc, TSEC_REG_GADDR(i), 0xFFFFFFFF);
1898
1899 return;
1900 }
1901
1902 IF_ADDR_LOCK(ifp);
1903 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1904
1905 if (ifma->ifma_addr->sa_family != AF_LINK)
1906 continue;
1907
1908 h = (ether_crc32_be(LLADDR((struct sockaddr_dl *)
1909 ifma->ifma_addr), ETHER_ADDR_LEN) >> 24) & 0xFF;
1910
1911 hashtable[(h >> 5)] |= 1 << (0x1F - (h & 0x1F));
1912 }
1913 IF_ADDR_UNLOCK(ifp);
1914
1915 for (i = 0; i < 8; i++)
1916 TSEC_WRITE(sc, TSEC_REG_GADDR(i), hashtable[i]);
1917}
1918
1919static int
1920tsec_set_mtu(struct tsec_softc *sc, unsigned int mtu)
1921{
1922
1923 mtu += ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + ETHER_CRC_LEN;
1924
1925 TSEC_GLOBAL_LOCK_ASSERT(sc);
1926
1927 if (mtu >= TSEC_MIN_FRAME_SIZE && mtu <= TSEC_MAX_FRAME_SIZE) {
1928 TSEC_WRITE(sc, TSEC_REG_MAXFRM, mtu);
1929 return (mtu);
1930 }
1931
1932 return (0);
1933}
|