1/*-
2 * Copyright (C) 2007-2008 Semihalf, Rafal Jaworowski
3 * Copyright (C) 2006-2007 Semihalf, Piotr Kruszynski
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
18 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
19 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
20 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
21 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
22 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
23 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
24 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 */
26
27/*
28 * Freescale integrated Three-Speed Ethernet Controller (TSEC) driver.
29 */
30#include <sys/cdefs.h>
31__FBSDID("$FreeBSD: head/sys/dev/tsec/if_tsec.c 271849 2014-09-19 03:51:26Z glebius $");
32
33#ifdef HAVE_KERNEL_OPTION_HEADERS
34#include "opt_device_polling.h"
35#endif
36
37#include <sys/param.h>
38#include <sys/systm.h>
39#include <sys/bus.h>
40#include <sys/endian.h>
41#include <sys/mbuf.h>
42#include <sys/kernel.h>
43#include <sys/module.h>
44#include <sys/socket.h>
45#include <sys/sockio.h>
46#include <sys/sysctl.h>
47
48#include <net/bpf.h>
49#include <net/ethernet.h>
50#include <net/if.h>
51#include <net/if_var.h>
52#include <net/if_arp.h>
53#include <net/if_dl.h>
54#include <net/if_media.h>
55#include <net/if_types.h>
56#include <net/if_vlan_var.h>
57
58#include <netinet/in_systm.h>
59#include <netinet/in.h>
60#include <netinet/ip.h>
61
62#include <machine/bus.h>
63
64#include <dev/mii/mii.h>
65#include <dev/mii/miivar.h>
66
67#include <dev/tsec/if_tsec.h>
68#include <dev/tsec/if_tsecreg.h>
69
70static int tsec_alloc_dma_desc(device_t dev, bus_dma_tag_t *dtag,
71 bus_dmamap_t *dmap, bus_size_t dsize, void **vaddr, void *raddr,
72 const char *dname);
73static void tsec_dma_ctl(struct tsec_softc *sc, int state);
74static int tsec_encap(struct tsec_softc *sc, struct mbuf *m_head,
75 int fcb_inserted);
76static void tsec_free_dma(struct tsec_softc *sc);
77static void tsec_free_dma_desc(bus_dma_tag_t dtag, bus_dmamap_t dmap, void *vaddr);
78static int tsec_ifmedia_upd(struct ifnet *ifp);
79static void tsec_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr);
80static int tsec_new_rxbuf(bus_dma_tag_t tag, bus_dmamap_t map,
81 struct mbuf **mbufp, uint32_t *paddr);
82static void tsec_map_dma_addr(void *arg, bus_dma_segment_t *segs,
83 int nseg, int error);
84static void tsec_intrs_ctl(struct tsec_softc *sc, int state);
85static void tsec_init(void *xsc);
86static void tsec_init_locked(struct tsec_softc *sc);
87static int tsec_ioctl(struct ifnet *ifp, u_long command, caddr_t data);
88static void tsec_reset_mac(struct tsec_softc *sc);
89static void tsec_setfilter(struct tsec_softc *sc);
90static void tsec_set_mac_address(struct tsec_softc *sc);
91static void tsec_start(struct ifnet *ifp);
92static void tsec_start_locked(struct ifnet *ifp);
93static void tsec_stop(struct tsec_softc *sc);
94static void tsec_tick(void *arg);
95static void tsec_watchdog(struct tsec_softc *sc);
96static void tsec_add_sysctls(struct tsec_softc *sc);
97static int tsec_sysctl_ic_time(SYSCTL_HANDLER_ARGS);
98static int tsec_sysctl_ic_count(SYSCTL_HANDLER_ARGS);
99static void tsec_set_rxic(struct tsec_softc *sc);
100static void tsec_set_txic(struct tsec_softc *sc);
101static int tsec_receive_intr_locked(struct tsec_softc *sc, int count);
102static void tsec_transmit_intr_locked(struct tsec_softc *sc);
103static void tsec_error_intr_locked(struct tsec_softc *sc, int count);
104static void tsec_offload_setup(struct tsec_softc *sc);
105static void tsec_offload_process_frame(struct tsec_softc *sc,
106 struct mbuf *m);
107static void tsec_setup_multicast(struct tsec_softc *sc);
108static int tsec_set_mtu(struct tsec_softc *sc, unsigned int mtu);
109
110devclass_t tsec_devclass;
111DRIVER_MODULE(miibus, tsec, miibus_driver, miibus_devclass, 0, 0);
112MODULE_DEPEND(tsec, ether, 1, 1, 1);
113MODULE_DEPEND(tsec, miibus, 1, 1, 1);
114
115struct mtx tsec_phy_mtx;
116
117int
118tsec_attach(struct tsec_softc *sc)
119{
120 uint8_t hwaddr[ETHER_ADDR_LEN];
121 struct ifnet *ifp;
122 bus_dmamap_t *map_ptr;
123 bus_dmamap_t **map_pptr;
124 int error = 0;
125 int i;
126
127 /* Initialize global (because potentially shared) MII lock */
128 if (!mtx_initialized(&tsec_phy_mtx))
129 mtx_init(&tsec_phy_mtx, "tsec mii", NULL, MTX_DEF);
130
131 /* Reset all TSEC counters */
132 TSEC_TX_RX_COUNTERS_INIT(sc);
133
134 /* Stop DMA engine if enabled by firmware */
135 tsec_dma_ctl(sc, 0);
136
137 /* Reset MAC */
138 tsec_reset_mac(sc);
139
140 /* Disable interrupts for now */
141 tsec_intrs_ctl(sc, 0);
142
143 /* Configure defaults for interrupts coalescing */
144 sc->rx_ic_time = 768;
145 sc->rx_ic_count = 16;
146 sc->tx_ic_time = 768;
147 sc->tx_ic_count = 16;
148 tsec_set_rxic(sc);
149 tsec_set_txic(sc);
150 tsec_add_sysctls(sc);
151
152 /* Allocate a busdma tag and DMA safe memory for TX descriptors. */
153 error = tsec_alloc_dma_desc(sc->dev, &sc->tsec_tx_dtag,
154 &sc->tsec_tx_dmap, sizeof(*sc->tsec_tx_vaddr) * TSEC_TX_NUM_DESC,
155 (void **)&sc->tsec_tx_vaddr, &sc->tsec_tx_raddr, "TX");
156
157 if (error) {
158 tsec_detach(sc);
159 return (ENXIO);
160 }
161
162 /* Allocate a busdma tag and DMA safe memory for RX descriptors. */
163 error = tsec_alloc_dma_desc(sc->dev, &sc->tsec_rx_dtag,
164 &sc->tsec_rx_dmap, sizeof(*sc->tsec_rx_vaddr) * TSEC_RX_NUM_DESC,
165 (void **)&sc->tsec_rx_vaddr, &sc->tsec_rx_raddr, "RX");
166 if (error) {
167 tsec_detach(sc);
168 return (ENXIO);
169 }
170
171 /* Allocate a busdma tag for TX mbufs. */
172 error = bus_dma_tag_create(NULL, /* parent */
173 TSEC_TXBUFFER_ALIGNMENT, 0, /* alignment, boundary */
174 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
175 BUS_SPACE_MAXADDR, /* highaddr */
176 NULL, NULL, /* filtfunc, filtfuncarg */
177 MCLBYTES * (TSEC_TX_NUM_DESC - 1), /* maxsize */
178 TSEC_TX_NUM_DESC - 1, /* nsegments */
179 MCLBYTES, 0, /* maxsegsz, flags */
180 NULL, NULL, /* lockfunc, lockfuncarg */
181 &sc->tsec_tx_mtag); /* dmat */
182 if (error) {
183 device_printf(sc->dev, "failed to allocate busdma tag "
184 "(tx mbufs)\n");
185 tsec_detach(sc);
186 return (ENXIO);
187 }
188
189 /* Allocate a busdma tag for RX mbufs. */
190 error = bus_dma_tag_create(NULL, /* parent */
191 TSEC_RXBUFFER_ALIGNMENT, 0, /* alignment, boundary */
192 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
193 BUS_SPACE_MAXADDR, /* highaddr */
194 NULL, NULL, /* filtfunc, filtfuncarg */
195 MCLBYTES, /* maxsize */
196 1, /* nsegments */
197 MCLBYTES, 0, /* maxsegsz, flags */
198 NULL, NULL, /* lockfunc, lockfuncarg */
199 &sc->tsec_rx_mtag); /* dmat */
200 if (error) {
201 device_printf(sc->dev, "failed to allocate busdma tag "
202 "(rx mbufs)\n");
203 tsec_detach(sc);
204 return (ENXIO);
205 }
206
207 /* Create TX busdma maps */
208 map_ptr = sc->tx_map_data;
209 map_pptr = sc->tx_map_unused_data;
210
211 for (i = 0; i < TSEC_TX_NUM_DESC; i++) {
212 map_pptr[i] = &map_ptr[i];
213 error = bus_dmamap_create(sc->tsec_tx_mtag, 0, map_pptr[i]);
214 if (error) {
215 device_printf(sc->dev, "failed to init TX ring\n");
216 tsec_detach(sc);
217 return (ENXIO);
218 }
219 }
220
221 /* Create RX busdma maps and zero mbuf handlers */
222 for (i = 0; i < TSEC_RX_NUM_DESC; i++) {
223 error = bus_dmamap_create(sc->tsec_rx_mtag, 0,
224 &sc->rx_data[i].map);
225 if (error) {
226 device_printf(sc->dev, "failed to init RX ring\n");
227 tsec_detach(sc);
228 return (ENXIO);
229 }
230 sc->rx_data[i].mbuf = NULL;
231 }
232
233 /* Create mbufs for RX buffers */
234 for (i = 0; i < TSEC_RX_NUM_DESC; i++) {
235 error = tsec_new_rxbuf(sc->tsec_rx_mtag, sc->rx_data[i].map,
236 &sc->rx_data[i].mbuf, &sc->rx_data[i].paddr);
237 if (error) {
238 device_printf(sc->dev, "can't load rx DMA map %d, "
239 "error = %d\n", i, error);
240 tsec_detach(sc);
241 return (error);
242 }
243 }
244
245 /* Create network interface for upper layers */
246 ifp = sc->tsec_ifp = if_alloc(IFT_ETHER);
247 if (ifp == NULL) {
248 device_printf(sc->dev, "if_alloc() failed\n");
249 tsec_detach(sc);
250 return (ENOMEM);
251 }
252
253 ifp->if_softc = sc;
254 if_initname(ifp, device_get_name(sc->dev), device_get_unit(sc->dev));
255 ifp->if_flags = IFF_SIMPLEX | IFF_MULTICAST | IFF_BROADCAST;
256 ifp->if_init = tsec_init;
257 ifp->if_start = tsec_start;
258 ifp->if_ioctl = tsec_ioctl;
259
260 IFQ_SET_MAXLEN(&ifp->if_snd, TSEC_TX_NUM_DESC - 1);
261 ifp->if_snd.ifq_drv_maxlen = TSEC_TX_NUM_DESC - 1;
262 IFQ_SET_READY(&ifp->if_snd);
263
264 ifp->if_capabilities = IFCAP_VLAN_MTU;
265 if (sc->is_etsec)
266 ifp->if_capabilities |= IFCAP_HWCSUM;
267
268 ifp->if_capenable = ifp->if_capabilities;
269
270#ifdef DEVICE_POLLING
271 /* Advertise that polling is supported */
272 ifp->if_capabilities |= IFCAP_POLLING;
273#endif
274
275 /* Attach PHY(s) */
276 error = mii_attach(sc->dev, &sc->tsec_miibus, ifp, tsec_ifmedia_upd,
277 tsec_ifmedia_sts, BMSR_DEFCAPMASK, sc->phyaddr, MII_OFFSET_ANY,
278 0);
279 if (error) {
280 device_printf(sc->dev, "attaching PHYs failed\n");
281 if_free(ifp);
282 sc->tsec_ifp = NULL;
283 tsec_detach(sc);
284 return (error);
285 }
286 sc->tsec_mii = device_get_softc(sc->tsec_miibus);
287
288 /* Set MAC address */
289 tsec_get_hwaddr(sc, hwaddr);
290 ether_ifattach(ifp, hwaddr);
291
292 return (0);
293}
294
295int
296tsec_detach(struct tsec_softc *sc)
297{
298
299 if (sc->tsec_ifp != NULL) {
300#ifdef DEVICE_POLLING
301 if (sc->tsec_ifp->if_capenable & IFCAP_POLLING)
302 ether_poll_deregister(sc->tsec_ifp);
303#endif
304
305 /* Stop TSEC controller and free TX queue */
306 if (sc->sc_rres)
307 tsec_shutdown(sc->dev);
308
309 /* Detach network interface */
310 ether_ifdetach(sc->tsec_ifp);
311 if_free(sc->tsec_ifp);
312 sc->tsec_ifp = NULL;
313 }
314
315 /* Free DMA resources */
316 tsec_free_dma(sc);
317
318 return (0);
319}
320
321int
322tsec_shutdown(device_t dev)
323{
324 struct tsec_softc *sc;
325
326 sc = device_get_softc(dev);
327
328 TSEC_GLOBAL_LOCK(sc);
329 tsec_stop(sc);
330 TSEC_GLOBAL_UNLOCK(sc);
331 return (0);
332}
333
334int
335tsec_suspend(device_t dev)
336{
337
338 /* TODO not implemented! */
339 return (0);
340}
341
342int
343tsec_resume(device_t dev)
344{
345
346 /* TODO not implemented! */
347 return (0);
348}
349
350static void
351tsec_init(void *xsc)
352{
353 struct tsec_softc *sc = xsc;
354
355 TSEC_GLOBAL_LOCK(sc);
356 tsec_init_locked(sc);
357 TSEC_GLOBAL_UNLOCK(sc);
358}
359
360static void
361tsec_init_locked(struct tsec_softc *sc)
362{
363 struct tsec_desc *tx_desc = sc->tsec_tx_vaddr;
364 struct tsec_desc *rx_desc = sc->tsec_rx_vaddr;
365 struct ifnet *ifp = sc->tsec_ifp;
366 uint32_t timeout, val, i;
367
368 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
369 return;
370
371 TSEC_GLOBAL_LOCK_ASSERT(sc);
372 tsec_stop(sc);
373
374 /*
375 * These steps are according to the MPC8555E PowerQUICCIII RM:
376 * 14.7 Initialization/Application Information
377 */
378
379 /* Step 1: soft reset MAC */
380 tsec_reset_mac(sc);
381
382 /* Step 2: Initialize MACCFG2 */
383 TSEC_WRITE(sc, TSEC_REG_MACCFG2,
384 TSEC_MACCFG2_FULLDUPLEX | /* Full Duplex = 1 */
385 TSEC_MACCFG2_PADCRC | /* PAD/CRC append */
386 TSEC_MACCFG2_GMII | /* I/F Mode bit */
387 TSEC_MACCFG2_PRECNT /* Preamble count = 7 */
388 );
389
390 /* Step 3: Initialize ECNTRL
391 * While the documentation states that R100M is ignored if RPM is
392 * not set, it does seem to be needed to get the orange boxes to
393 * work (which have a Marvell 88E1111 PHY). Go figure.
394 */
395
396 /*
397 * XXX kludge - use circumstancial evidence to program ECNTRL
398 * correctly. Ideally we need some board information to guide
399 * us here.
400 */
401 i = TSEC_READ(sc, TSEC_REG_ID2);
402 val = (i & 0xffff)
403 ? (TSEC_ECNTRL_TBIM | TSEC_ECNTRL_SGMIIM) /* Sumatra */
404 : TSEC_ECNTRL_R100M; /* Orange + CDS */
405 TSEC_WRITE(sc, TSEC_REG_ECNTRL, TSEC_ECNTRL_STEN | val);
406
407 /* Step 4: Initialize MAC station address */
408 tsec_set_mac_address(sc);
409
410 /*
411 * Step 5: Assign a Physical address to the TBI so as to not conflict
412 * with the external PHY physical address
413 */
414 TSEC_WRITE(sc, TSEC_REG_TBIPA, 5);
415
416 TSEC_PHY_LOCK(sc);
417
418 /* Step 6: Reset the management interface */
419 TSEC_PHY_WRITE(sc, TSEC_REG_MIIMCFG, TSEC_MIIMCFG_RESETMGMT);
420
421 /* Step 7: Setup the MII Mgmt clock speed */
422 TSEC_PHY_WRITE(sc, TSEC_REG_MIIMCFG, TSEC_MIIMCFG_CLKDIV28);
423
424 /* Step 8: Read MII Mgmt indicator register and check for Busy = 0 */
425 timeout = TSEC_READ_RETRY;
426 while (--timeout && (TSEC_PHY_READ(sc, TSEC_REG_MIIMIND) &
427 TSEC_MIIMIND_BUSY))
428 DELAY(TSEC_READ_DELAY);
429 if (timeout == 0) {
430 if_printf(ifp, "tsec_init_locked(): Mgmt busy timeout\n");
431 return;
432 }
433 TSEC_PHY_UNLOCK(sc);
434
435 /* Step 9: Setup the MII Mgmt */
436 mii_mediachg(sc->tsec_mii);
437
438 /* Step 10: Clear IEVENT register */
439 TSEC_WRITE(sc, TSEC_REG_IEVENT, 0xffffffff);
440
441 /* Step 11: Enable interrupts */
442#ifdef DEVICE_POLLING
443 /*
444 * ...only if polling is not turned on. Disable interrupts explicitly
445 * if polling is enabled.
446 */
447 if (ifp->if_capenable & IFCAP_POLLING )
448 tsec_intrs_ctl(sc, 0);
449 else
450#endif /* DEVICE_POLLING */
451 tsec_intrs_ctl(sc, 1);
452
453 /* Step 12: Initialize IADDRn */
454 TSEC_WRITE(sc, TSEC_REG_IADDR0, 0);
455 TSEC_WRITE(sc, TSEC_REG_IADDR1, 0);
456 TSEC_WRITE(sc, TSEC_REG_IADDR2, 0);
457 TSEC_WRITE(sc, TSEC_REG_IADDR3, 0);
458 TSEC_WRITE(sc, TSEC_REG_IADDR4, 0);
459 TSEC_WRITE(sc, TSEC_REG_IADDR5, 0);
460 TSEC_WRITE(sc, TSEC_REG_IADDR6, 0);
461 TSEC_WRITE(sc, TSEC_REG_IADDR7, 0);
462
463 /* Step 13: Initialize GADDRn */
464 TSEC_WRITE(sc, TSEC_REG_GADDR0, 0);
465 TSEC_WRITE(sc, TSEC_REG_GADDR1, 0);
466 TSEC_WRITE(sc, TSEC_REG_GADDR2, 0);
467 TSEC_WRITE(sc, TSEC_REG_GADDR3, 0);
468 TSEC_WRITE(sc, TSEC_REG_GADDR4, 0);
469 TSEC_WRITE(sc, TSEC_REG_GADDR5, 0);
470 TSEC_WRITE(sc, TSEC_REG_GADDR6, 0);
471 TSEC_WRITE(sc, TSEC_REG_GADDR7, 0);
472
473 /* Step 14: Initialize RCTRL */
474 TSEC_WRITE(sc, TSEC_REG_RCTRL, 0);
475
476 /* Step 15: Initialize DMACTRL */
477 tsec_dma_ctl(sc, 1);
478
479 /* Step 16: Initialize FIFO_PAUSE_CTRL */
480 TSEC_WRITE(sc, TSEC_REG_FIFO_PAUSE_CTRL, TSEC_FIFO_PAUSE_CTRL_EN);
481
482 /*
483 * Step 17: Initialize transmit/receive descriptor rings.
484 * Initialize TBASE and RBASE.
485 */
486 TSEC_WRITE(sc, TSEC_REG_TBASE, sc->tsec_tx_raddr);
487 TSEC_WRITE(sc, TSEC_REG_RBASE, sc->tsec_rx_raddr);
488
489 for (i = 0; i < TSEC_TX_NUM_DESC; i++) {
490 tx_desc[i].bufptr = 0;
491 tx_desc[i].length = 0;
492 tx_desc[i].flags = ((i == TSEC_TX_NUM_DESC - 1) ?
493 TSEC_TXBD_W : 0);
494 }
495 bus_dmamap_sync(sc->tsec_tx_dtag, sc->tsec_tx_dmap,
496 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
497
498 for (i = 0; i < TSEC_RX_NUM_DESC; i++) {
499 rx_desc[i].bufptr = sc->rx_data[i].paddr;
500 rx_desc[i].length = 0;
501 rx_desc[i].flags = TSEC_RXBD_E | TSEC_RXBD_I |
502 ((i == TSEC_RX_NUM_DESC - 1) ? TSEC_RXBD_W : 0);
503 }
504 bus_dmamap_sync(sc->tsec_rx_dtag, sc->tsec_rx_dmap,
505 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
506
507 /* Step 18: Initialize the maximum receive buffer length */
508 TSEC_WRITE(sc, TSEC_REG_MRBLR, MCLBYTES);
509
510 /* Step 19: Configure ethernet frame sizes */
511 TSEC_WRITE(sc, TSEC_REG_MINFLR, TSEC_MIN_FRAME_SIZE);
512 tsec_set_mtu(sc, ifp->if_mtu);
513
514 /* Step 20: Enable Rx and RxBD sdata snooping */
515 TSEC_WRITE(sc, TSEC_REG_ATTR, TSEC_ATTR_RDSEN | TSEC_ATTR_RBDSEN);
516 TSEC_WRITE(sc, TSEC_REG_ATTRELI, 0);
517
518 /* Step 21: Reset collision counters in hardware */
519 TSEC_WRITE(sc, TSEC_REG_MON_TSCL, 0);
520 TSEC_WRITE(sc, TSEC_REG_MON_TMCL, 0);
521 TSEC_WRITE(sc, TSEC_REG_MON_TLCL, 0);
522 TSEC_WRITE(sc, TSEC_REG_MON_TXCL, 0);
523 TSEC_WRITE(sc, TSEC_REG_MON_TNCL, 0);
524
525 /* Step 22: Mask all CAM interrupts */
526 TSEC_WRITE(sc, TSEC_REG_MON_CAM1, 0xffffffff);
527 TSEC_WRITE(sc, TSEC_REG_MON_CAM2, 0xffffffff);
528
529 /* Step 23: Enable Rx and Tx */
530 val = TSEC_READ(sc, TSEC_REG_MACCFG1);
531 val |= (TSEC_MACCFG1_RX_EN | TSEC_MACCFG1_TX_EN);
532 TSEC_WRITE(sc, TSEC_REG_MACCFG1, val);
533
534 /* Step 24: Reset TSEC counters for Tx and Rx rings */
535 TSEC_TX_RX_COUNTERS_INIT(sc);
536
537 /* Step 25: Setup TCP/IP Off-Load engine */
538 if (sc->is_etsec)
539 tsec_offload_setup(sc);
540
541 /* Step 26: Setup multicast filters */
542 tsec_setup_multicast(sc);
543
544 /* Step 27: Activate network interface */
545 ifp->if_drv_flags |= IFF_DRV_RUNNING;
546 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
547 sc->tsec_if_flags = ifp->if_flags;
548 sc->tsec_watchdog = 0;
549
550 /* Schedule watchdog timeout */
551 callout_reset(&sc->tsec_callout, hz, tsec_tick, sc);
552}
553
554static void
555tsec_set_mac_address(struct tsec_softc *sc)
556{
557 uint32_t macbuf[2] = { 0, 0 };
558 char *macbufp, *curmac;
559 int i;
560
561 TSEC_GLOBAL_LOCK_ASSERT(sc);
562
563 KASSERT((ETHER_ADDR_LEN <= sizeof(macbuf)),
564 ("tsec_set_mac_address: (%d <= %d", ETHER_ADDR_LEN,
565 sizeof(macbuf)));
566
567 macbufp = (char *)macbuf;
568 curmac = (char *)IF_LLADDR(sc->tsec_ifp);
569
570 /* Correct order of MAC address bytes */
571 for (i = 1; i <= ETHER_ADDR_LEN; i++)
572 macbufp[ETHER_ADDR_LEN-i] = curmac[i-1];
573
574 /* Initialize MAC station address MACSTNADDR2 and MACSTNADDR1 */
575 TSEC_WRITE(sc, TSEC_REG_MACSTNADDR2, macbuf[1]);
576 TSEC_WRITE(sc, TSEC_REG_MACSTNADDR1, macbuf[0]);
577}
578
579/*
580 * DMA control function, if argument state is:
581 * 0 - DMA engine will be disabled
582 * 1 - DMA engine will be enabled
583 */
584static void
585tsec_dma_ctl(struct tsec_softc *sc, int state)
586{
587 device_t dev;
588 uint32_t dma_flags, timeout;
589
590 dev = sc->dev;
591
592 dma_flags = TSEC_READ(sc, TSEC_REG_DMACTRL);
593
594 switch (state) {
595 case 0:
596 /* Temporarily clear stop graceful stop bits. */
597 tsec_dma_ctl(sc, 1000);
598
599 /* Set it again */
600 dma_flags |= (TSEC_DMACTRL_GRS | TSEC_DMACTRL_GTS);
601 break;
602 case 1000:
603 case 1:
604 /* Set write with response (WWR), wait (WOP) and snoop bits */
605 dma_flags |= (TSEC_DMACTRL_TDSEN | TSEC_DMACTRL_TBDSEN |
606 DMACTRL_WWR | DMACTRL_WOP);
607
608 /* Clear graceful stop bits */
609 dma_flags &= ~(TSEC_DMACTRL_GRS | TSEC_DMACTRL_GTS);
610 break;
611 default:
612 device_printf(dev, "tsec_dma_ctl(): unknown state value: %d\n",
613 state);
614 }
615
616 TSEC_WRITE(sc, TSEC_REG_DMACTRL, dma_flags);
617
618 switch (state) {
619 case 0:
620 /* Wait for DMA stop */
621 timeout = TSEC_READ_RETRY;
622 while (--timeout && (!(TSEC_READ(sc, TSEC_REG_IEVENT) &
623 (TSEC_IEVENT_GRSC | TSEC_IEVENT_GTSC))))
624 DELAY(TSEC_READ_DELAY);
625
626 if (timeout == 0)
627 device_printf(dev, "tsec_dma_ctl(): timeout!\n");
628 break;
629 case 1:
630 /* Restart transmission function */
631 TSEC_WRITE(sc, TSEC_REG_TSTAT, TSEC_TSTAT_THLT);
632 }
633}
634
635/*
636 * Interrupts control function, if argument state is:
637 * 0 - all TSEC interrupts will be masked
638 * 1 - all TSEC interrupts will be unmasked
639 */
640static void
641tsec_intrs_ctl(struct tsec_softc *sc, int state)
642{
643 device_t dev;
644
645 dev = sc->dev;
646
647 switch (state) {
648 case 0:
649 TSEC_WRITE(sc, TSEC_REG_IMASK, 0);
650 break;
651 case 1:
652 TSEC_WRITE(sc, TSEC_REG_IMASK, TSEC_IMASK_BREN |
653 TSEC_IMASK_RXCEN | TSEC_IMASK_BSYEN | TSEC_IMASK_EBERREN |
654 TSEC_IMASK_BTEN | TSEC_IMASK_TXEEN | TSEC_IMASK_TXBEN |
655 TSEC_IMASK_TXFEN | TSEC_IMASK_XFUNEN | TSEC_IMASK_RXFEN);
656 break;
657 default:
658 device_printf(dev, "tsec_intrs_ctl(): unknown state value: %d\n",
659 state);
660 }
661}
662
663static void
664tsec_reset_mac(struct tsec_softc *sc)
665{
666 uint32_t maccfg1_flags;
667
668 /* Set soft reset bit */
669 maccfg1_flags = TSEC_READ(sc, TSEC_REG_MACCFG1);
670 maccfg1_flags |= TSEC_MACCFG1_SOFT_RESET;
671 TSEC_WRITE(sc, TSEC_REG_MACCFG1, maccfg1_flags);
672
673 /* Clear soft reset bit */
674 maccfg1_flags = TSEC_READ(sc, TSEC_REG_MACCFG1);
675 maccfg1_flags &= ~TSEC_MACCFG1_SOFT_RESET;
676 TSEC_WRITE(sc, TSEC_REG_MACCFG1, maccfg1_flags);
677}
678
679static void
680tsec_watchdog(struct tsec_softc *sc)
681{
682 struct ifnet *ifp;
683
684 TSEC_GLOBAL_LOCK_ASSERT(sc);
685
686 if (sc->tsec_watchdog == 0 || --sc->tsec_watchdog > 0)
687 return;
688
689 ifp = sc->tsec_ifp;
690 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
691 if_printf(ifp, "watchdog timeout\n");
692
693 tsec_stop(sc);
694 tsec_init_locked(sc);
695}
696
697static void
698tsec_start(struct ifnet *ifp)
699{
700 struct tsec_softc *sc = ifp->if_softc;
701
702 TSEC_TRANSMIT_LOCK(sc);
703 tsec_start_locked(ifp);
704 TSEC_TRANSMIT_UNLOCK(sc);
705}
706
707static void
708tsec_start_locked(struct ifnet *ifp)
709{
710 struct tsec_softc *sc;
711 struct mbuf *m0, *mtmp;
712 struct tsec_tx_fcb *tx_fcb;
713 unsigned int queued = 0;
714 int csum_flags, fcb_inserted = 0;
715
716 sc = ifp->if_softc;
717
718 TSEC_TRANSMIT_LOCK_ASSERT(sc);
719
720 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
721 IFF_DRV_RUNNING)
722 return;
723
724 if (sc->tsec_link == 0)
725 return;
726
727 bus_dmamap_sync(sc->tsec_tx_dtag, sc->tsec_tx_dmap,
728 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
729
730 while (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) {
731 /* Get packet from the queue */
732 IFQ_DRV_DEQUEUE(&ifp->if_snd, m0);
733 if (m0 == NULL)
734 break;
735
736 /* Insert TCP/IP Off-load frame control block */
737 csum_flags = m0->m_pkthdr.csum_flags;
738 if (csum_flags) {
739
740 M_PREPEND(m0, sizeof(struct tsec_tx_fcb), M_NOWAIT);
741 if (m0 == NULL)
742 break;
743
744 tx_fcb = mtod(m0, struct tsec_tx_fcb *);
745 tx_fcb->flags = 0;
746 tx_fcb->l3_offset = ETHER_HDR_LEN;
747 tx_fcb->l4_offset = sizeof(struct ip);
748
749 if (csum_flags & CSUM_IP)
750 tx_fcb->flags |= TSEC_TX_FCB_IP4 |
751 TSEC_TX_FCB_CSUM_IP;
752
753 if (csum_flags & CSUM_TCP)
754 tx_fcb->flags |= TSEC_TX_FCB_TCP |
755 TSEC_TX_FCB_CSUM_TCP_UDP;
756
757 if (csum_flags & CSUM_UDP)
758 tx_fcb->flags |= TSEC_TX_FCB_UDP |
759 TSEC_TX_FCB_CSUM_TCP_UDP;
760
761 fcb_inserted = 1;
762 }
763
764 mtmp = m_defrag(m0, M_NOWAIT);
765 if (mtmp)
766 m0 = mtmp;
767
768 if (tsec_encap(sc, m0, fcb_inserted)) {
769 IFQ_DRV_PREPEND(&ifp->if_snd, m0);
770 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
771 break;
772 }
773 queued++;
774 BPF_MTAP(ifp, m0);
775 }
776 bus_dmamap_sync(sc->tsec_tx_dtag, sc->tsec_tx_dmap,
777 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
778
779 if (queued) {
780 /* Enable transmitter and watchdog timer */
781 TSEC_WRITE(sc, TSEC_REG_TSTAT, TSEC_TSTAT_THLT);
782 sc->tsec_watchdog = 5;
783 }
784}
785
786static int
787tsec_encap(struct tsec_softc *sc, struct mbuf *m0, int fcb_inserted)
788{
789 struct tsec_desc *tx_desc = NULL;
790 struct ifnet *ifp;
791 bus_dma_segment_t segs[TSEC_TX_NUM_DESC];
792 bus_dmamap_t *mapp;
793 int csum_flag = 0, error, seg, nsegs;
794
795 TSEC_TRANSMIT_LOCK_ASSERT(sc);
796
797 ifp = sc->tsec_ifp;
798
799 if (TSEC_FREE_TX_DESC(sc) == 0) {
800 /* No free descriptors */
801 return (-1);
802 }
803
804 /* Fetch unused map */
805 mapp = TSEC_ALLOC_TX_MAP(sc);
806
807 /* Create mapping in DMA memory */
808 error = bus_dmamap_load_mbuf_sg(sc->tsec_tx_mtag,
809 *mapp, m0, segs, &nsegs, BUS_DMA_NOWAIT);
810 if (error != 0 || nsegs > TSEC_FREE_TX_DESC(sc) || nsegs <= 0) {
811 bus_dmamap_unload(sc->tsec_tx_mtag, *mapp);
812 TSEC_FREE_TX_MAP(sc, mapp);
813 return ((error != 0) ? error : -1);
814 }
815 bus_dmamap_sync(sc->tsec_tx_mtag, *mapp, BUS_DMASYNC_PREWRITE);
816
817 if ((ifp->if_flags & IFF_DEBUG) && (nsegs > 1))
818 if_printf(ifp, "TX buffer has %d segments\n", nsegs);
819
820 if (fcb_inserted)
821 csum_flag = TSEC_TXBD_TOE;
822
823 /* Everything is ok, now we can send buffers */
824 for (seg = 0; seg < nsegs; seg++) {
825 tx_desc = TSEC_GET_CUR_TX_DESC(sc);
826
827 tx_desc->length = segs[seg].ds_len;
828 tx_desc->bufptr = segs[seg].ds_addr;
829
830 /*
831 * Set flags:
832 * - wrap
833 * - checksum
834 * - ready to send
835 * - transmit the CRC sequence after the last data byte
836 * - interrupt after the last buffer
837 */
838 tx_desc->flags =
839 (tx_desc->flags & TSEC_TXBD_W) |
840 ((seg == 0) ? csum_flag : 0) | TSEC_TXBD_R | TSEC_TXBD_TC |
841 ((seg == nsegs - 1) ? TSEC_TXBD_L | TSEC_TXBD_I : 0);
842 }
843
844 /* Save mbuf and DMA mapping for release at later stage */
845 TSEC_PUT_TX_MBUF(sc, m0);
846 TSEC_PUT_TX_MAP(sc, mapp);
847
848 return (0);
849}
850
851static void
852tsec_setfilter(struct tsec_softc *sc)
853{
854 struct ifnet *ifp;
855 uint32_t flags;
856
857 ifp = sc->tsec_ifp;
858 flags = TSEC_READ(sc, TSEC_REG_RCTRL);
859
860 /* Promiscuous mode */
861 if (ifp->if_flags & IFF_PROMISC)
862 flags |= TSEC_RCTRL_PROM;
863 else
864 flags &= ~TSEC_RCTRL_PROM;
865
866 TSEC_WRITE(sc, TSEC_REG_RCTRL, flags);
867}
868
869#ifdef DEVICE_POLLING
870static poll_handler_t tsec_poll;
871
872static int
873tsec_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
874{
875 uint32_t ie;
876 struct tsec_softc *sc = ifp->if_softc;
877 int rx_npkts;
878
879 rx_npkts = 0;
880
881 TSEC_GLOBAL_LOCK(sc);
882 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
883 TSEC_GLOBAL_UNLOCK(sc);
884 return (rx_npkts);
885 }
886
887 if (cmd == POLL_AND_CHECK_STATUS) {
888 tsec_error_intr_locked(sc, count);
889
890 /* Clear all events reported */
891 ie = TSEC_READ(sc, TSEC_REG_IEVENT);
892 TSEC_WRITE(sc, TSEC_REG_IEVENT, ie);
893 }
894
895 tsec_transmit_intr_locked(sc);
896
897 TSEC_GLOBAL_TO_RECEIVE_LOCK(sc);
898
899 rx_npkts = tsec_receive_intr_locked(sc, count);
900
901 TSEC_RECEIVE_UNLOCK(sc);
902
903 return (rx_npkts);
904}
905#endif /* DEVICE_POLLING */
906
907static int
908tsec_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
909{
910 struct tsec_softc *sc = ifp->if_softc;
911 struct ifreq *ifr = (struct ifreq *)data;
912 device_t dev;
913 int mask, error = 0;
914
915 dev = sc->dev;
916
917 switch (command) {
918 case SIOCSIFMTU:
919 TSEC_GLOBAL_LOCK(sc);
920 if (tsec_set_mtu(sc, ifr->ifr_mtu))
921 ifp->if_mtu = ifr->ifr_mtu;
922 else
923 error = EINVAL;
924 TSEC_GLOBAL_UNLOCK(sc);
925 break;
926 case SIOCSIFFLAGS:
927 TSEC_GLOBAL_LOCK(sc);
928 if (ifp->if_flags & IFF_UP) {
929 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
930 if ((sc->tsec_if_flags ^ ifp->if_flags) &
931 IFF_PROMISC)
932 tsec_setfilter(sc);
933
934 if ((sc->tsec_if_flags ^ ifp->if_flags) &
935 IFF_ALLMULTI)
936 tsec_setup_multicast(sc);
937 } else
938 tsec_init_locked(sc);
939 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING)
940 tsec_stop(sc);
941
942 sc->tsec_if_flags = ifp->if_flags;
943 TSEC_GLOBAL_UNLOCK(sc);
944 break;
945 case SIOCADDMULTI:
946 case SIOCDELMULTI:
947 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
948 TSEC_GLOBAL_LOCK(sc);
949 tsec_setup_multicast(sc);
950 TSEC_GLOBAL_UNLOCK(sc);
951 }
952 case SIOCGIFMEDIA:
953 case SIOCSIFMEDIA:
954 error = ifmedia_ioctl(ifp, ifr, &sc->tsec_mii->mii_media,
955 command);
956 break;
957 case SIOCSIFCAP:
958 mask = ifp->if_capenable ^ ifr->ifr_reqcap;
959 if ((mask & IFCAP_HWCSUM) && sc->is_etsec) {
960 TSEC_GLOBAL_LOCK(sc);
961 ifp->if_capenable &= ~IFCAP_HWCSUM;
962 ifp->if_capenable |= IFCAP_HWCSUM & ifr->ifr_reqcap;
963 tsec_offload_setup(sc);
964 TSEC_GLOBAL_UNLOCK(sc);
965 }
966#ifdef DEVICE_POLLING
967 if (mask & IFCAP_POLLING) {
968 if (ifr->ifr_reqcap & IFCAP_POLLING) {
969 error = ether_poll_register(tsec_poll, ifp);
970 if (error)
971 return (error);
972
973 TSEC_GLOBAL_LOCK(sc);
974 /* Disable interrupts */
975 tsec_intrs_ctl(sc, 0);
976 ifp->if_capenable |= IFCAP_POLLING;
977 TSEC_GLOBAL_UNLOCK(sc);
978 } else {
979 error = ether_poll_deregister(ifp);
980 TSEC_GLOBAL_LOCK(sc);
981 /* Enable interrupts */
982 tsec_intrs_ctl(sc, 1);
983 ifp->if_capenable &= ~IFCAP_POLLING;
984 TSEC_GLOBAL_UNLOCK(sc);
985 }
986 }
987#endif
988 break;
989
990 default:
991 error = ether_ioctl(ifp, command, data);
992 }
993
994 /* Flush buffers if not empty */
995 if (ifp->if_flags & IFF_UP)
996 tsec_start(ifp);
997 return (error);
998}
999
1000static int
1001tsec_ifmedia_upd(struct ifnet *ifp)
1002{
1003 struct tsec_softc *sc = ifp->if_softc;
1004 struct mii_data *mii;
1005
1006 TSEC_TRANSMIT_LOCK(sc);
1007
1008 mii = sc->tsec_mii;
1009 mii_mediachg(mii);
1010
1011 TSEC_TRANSMIT_UNLOCK(sc);
1012 return (0);
1013}
1014
1015static void
1016tsec_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1017{
1018 struct tsec_softc *sc = ifp->if_softc;
1019 struct mii_data *mii;
1020
1021 TSEC_TRANSMIT_LOCK(sc);
1022
1023 mii = sc->tsec_mii;
1024 mii_pollstat(mii);
1025
1026 ifmr->ifm_active = mii->mii_media_active;
1027 ifmr->ifm_status = mii->mii_media_status;
1028
1029 TSEC_TRANSMIT_UNLOCK(sc);
1030}
1031
1032static int
1033tsec_new_rxbuf(bus_dma_tag_t tag, bus_dmamap_t map, struct mbuf **mbufp,
1034 uint32_t *paddr)
1035{
1036 struct mbuf *new_mbuf;
1037 bus_dma_segment_t seg[1];
1038 int error, nsegs;
1039
1040 KASSERT(mbufp != NULL, ("NULL mbuf pointer!"));
1041
1042 new_mbuf = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, MCLBYTES);
1043 if (new_mbuf == NULL)
1044 return (ENOBUFS);
1045 new_mbuf->m_len = new_mbuf->m_pkthdr.len = new_mbuf->m_ext.ext_size;
1046
1047 if (*mbufp) {
1048 bus_dmamap_sync(tag, map, BUS_DMASYNC_POSTREAD);
1049 bus_dmamap_unload(tag, map);
1050 }
1051
1052 error = bus_dmamap_load_mbuf_sg(tag, map, new_mbuf, seg, &nsegs,
1053 BUS_DMA_NOWAIT);
1054 KASSERT(nsegs == 1, ("Too many segments returned!"));
1055 if (nsegs != 1 || error)
1056 panic("tsec_new_rxbuf(): nsegs(%d), error(%d)", nsegs, error);
1057
1058#if 0
1059 if (error) {
1060 printf("tsec: bus_dmamap_load_mbuf_sg() returned: %d!\n",
1061 error);
1062 m_freem(new_mbuf);
1063 return (ENOBUFS);
1064 }
1065#endif
1066
1067#if 0
1068 KASSERT(((seg->ds_addr) & (TSEC_RXBUFFER_ALIGNMENT-1)) == 0,
1069 ("Wrong alignment of RX buffer!"));
1070#endif
1071 bus_dmamap_sync(tag, map, BUS_DMASYNC_PREREAD);
1072
1073 (*mbufp) = new_mbuf;
1074 (*paddr) = seg->ds_addr;
1075 return (0);
1076}
1077
1078static void
1079tsec_map_dma_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
1080{
1081 u_int32_t *paddr;
1082
1083 KASSERT(nseg == 1, ("wrong number of segments, should be 1"));
1084 paddr = arg;
1085 *paddr = segs->ds_addr;
1086}
1087
1088static int
1089tsec_alloc_dma_desc(device_t dev, bus_dma_tag_t *dtag, bus_dmamap_t *dmap,
1090 bus_size_t dsize, void **vaddr, void *raddr, const char *dname)
1091{
1092 int error;
1093
1094 /* Allocate a busdma tag and DMA safe memory for TX/RX descriptors. */
1095 error = bus_dma_tag_create(NULL, /* parent */
1096 PAGE_SIZE, 0, /* alignment, boundary */
1097 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
1098 BUS_SPACE_MAXADDR, /* highaddr */
1099 NULL, NULL, /* filtfunc, filtfuncarg */
1100 dsize, 1, /* maxsize, nsegments */
1101 dsize, 0, /* maxsegsz, flags */
1102 NULL, NULL, /* lockfunc, lockfuncarg */
1103 dtag); /* dmat */
1104
1105 if (error) {
1106 device_printf(dev, "failed to allocate busdma %s tag\n",
1107 dname);
1108 (*vaddr) = NULL;
1109 return (ENXIO);
1110 }
1111
1112 error = bus_dmamem_alloc(*dtag, vaddr, BUS_DMA_NOWAIT | BUS_DMA_ZERO,
1113 dmap);
1114 if (error) {
1115 device_printf(dev, "failed to allocate %s DMA safe memory\n",
1116 dname);
1117 bus_dma_tag_destroy(*dtag);
1118 (*vaddr) = NULL;
1119 return (ENXIO);
1120 }
1121
1122 error = bus_dmamap_load(*dtag, *dmap, *vaddr, dsize,
1123 tsec_map_dma_addr, raddr, BUS_DMA_NOWAIT);
1124 if (error) {
1125 device_printf(dev, "cannot get address of the %s "
1126 "descriptors\n", dname);
1127 bus_dmamem_free(*dtag, *vaddr, *dmap);
1128 bus_dma_tag_destroy(*dtag);
1129 (*vaddr) = NULL;
1130 return (ENXIO);
1131 }
1132
1133 return (0);
1134}
1135
1136static void
1137tsec_free_dma_desc(bus_dma_tag_t dtag, bus_dmamap_t dmap, void *vaddr)
1138{
1139
1140 if (vaddr == NULL)
1141 return;
1142
1143 /* Unmap descriptors from DMA memory */
1144 bus_dmamap_sync(dtag, dmap, BUS_DMASYNC_POSTREAD |
1145 BUS_DMASYNC_POSTWRITE);
1146 bus_dmamap_unload(dtag, dmap);
1147
1148 /* Free descriptors memory */
1149 bus_dmamem_free(dtag, vaddr, dmap);
1150
1151 /* Destroy descriptors tag */
1152 bus_dma_tag_destroy(dtag);
1153}
1154
1155static void
1156tsec_free_dma(struct tsec_softc *sc)
1157{
1158 int i;
1159
1160 /* Free TX maps */
1161 for (i = 0; i < TSEC_TX_NUM_DESC; i++)
1162 if (sc->tx_map_data[i] != NULL)
1163 bus_dmamap_destroy(sc->tsec_tx_mtag,
1164 sc->tx_map_data[i]);
1165 /* Destroy tag for TX mbufs */
1166 bus_dma_tag_destroy(sc->tsec_tx_mtag);
1167
1168 /* Free RX mbufs and maps */
1169 for (i = 0; i < TSEC_RX_NUM_DESC; i++) {
1170 if (sc->rx_data[i].mbuf) {
1171 /* Unload buffer from DMA */
1172 bus_dmamap_sync(sc->tsec_rx_mtag, sc->rx_data[i].map,
1173 BUS_DMASYNC_POSTREAD);
1174 bus_dmamap_unload(sc->tsec_rx_mtag,
1175 sc->rx_data[i].map);
1176
1177 /* Free buffer */
1178 m_freem(sc->rx_data[i].mbuf);
1179 }
1180 /* Destroy map for this buffer */
1181 if (sc->rx_data[i].map != NULL)
1182 bus_dmamap_destroy(sc->tsec_rx_mtag,
1183 sc->rx_data[i].map);
1184 }
1185 /* Destroy tag for RX mbufs */
1186 bus_dma_tag_destroy(sc->tsec_rx_mtag);
1187
1188 /* Unload TX/RX descriptors */
1189 tsec_free_dma_desc(sc->tsec_tx_dtag, sc->tsec_tx_dmap,
1190 sc->tsec_tx_vaddr);
1191 tsec_free_dma_desc(sc->tsec_rx_dtag, sc->tsec_rx_dmap,
1192 sc->tsec_rx_vaddr);
1193}
1194
1195static void
1196tsec_stop(struct tsec_softc *sc)
1197{
1198 struct ifnet *ifp;
1199 struct mbuf *m0;
1200 bus_dmamap_t *mapp;
1201 uint32_t tmpval;
1202
1203 TSEC_GLOBAL_LOCK_ASSERT(sc);
1204
1205 ifp = sc->tsec_ifp;
1206
1207 /* Disable interface and watchdog timer */
1208 callout_stop(&sc->tsec_callout);
1209 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
1210 sc->tsec_watchdog = 0;
1211
1212 /* Disable all interrupts and stop DMA */
1213 tsec_intrs_ctl(sc, 0);
1214 tsec_dma_ctl(sc, 0);
1215
1216 /* Remove pending data from TX queue */
1217 while (!TSEC_EMPTYQ_TX_MBUF(sc)) {
1218 m0 = TSEC_GET_TX_MBUF(sc);
1219 mapp = TSEC_GET_TX_MAP(sc);
1220
1221 bus_dmamap_sync(sc->tsec_tx_mtag, *mapp,
1222 BUS_DMASYNC_POSTWRITE);
1223 bus_dmamap_unload(sc->tsec_tx_mtag, *mapp);
1224
1225 TSEC_FREE_TX_MAP(sc, mapp);
1226 m_freem(m0);
1227 }
1228
1229 /* Disable RX and TX */
1230 tmpval = TSEC_READ(sc, TSEC_REG_MACCFG1);
1231 tmpval &= ~(TSEC_MACCFG1_RX_EN | TSEC_MACCFG1_TX_EN);
1232 TSEC_WRITE(sc, TSEC_REG_MACCFG1, tmpval);
1233 DELAY(10);
1234}
1235
1236static void
1237tsec_tick(void *arg)
1238{
1239 struct tsec_softc *sc = arg;
1240 struct ifnet *ifp;
1241 int link;
1242
1243 TSEC_GLOBAL_LOCK(sc);
1244
1245 tsec_watchdog(sc);
1246
1247 ifp = sc->tsec_ifp;
1248 link = sc->tsec_link;
1249
1250 mii_tick(sc->tsec_mii);
1251
1252 if (link == 0 && sc->tsec_link == 1 &&
1253 (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)))
1254 tsec_start_locked(ifp);
1255
1256 /* Schedule another timeout one second from now. */
1257 callout_reset(&sc->tsec_callout, hz, tsec_tick, sc);
1258
1259 TSEC_GLOBAL_UNLOCK(sc);
1260}
1261
1262/*
1263 * This is the core RX routine. It replenishes mbufs in the descriptor and
1264 * sends data which have been dma'ed into host memory to upper layer.
1265 *
1266 * Loops at most count times if count is > 0, or until done if count < 0.
1267 */
1268static int
1269tsec_receive_intr_locked(struct tsec_softc *sc, int count)
1270{
1271 struct tsec_desc *rx_desc;
1272 struct ifnet *ifp;
1273 struct rx_data_type *rx_data;
1274 struct mbuf *m;
1275 device_t dev;
1276 uint32_t i;
1277 int c, rx_npkts;
1278 uint16_t flags;
1279
1280 TSEC_RECEIVE_LOCK_ASSERT(sc);
1281
1282 ifp = sc->tsec_ifp;
1283 rx_data = sc->rx_data;
1284 dev = sc->dev;
1285 rx_npkts = 0;
1286
1287 bus_dmamap_sync(sc->tsec_rx_dtag, sc->tsec_rx_dmap,
1288 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1289
1290 for (c = 0; ; c++) {
1291 if (count >= 0 && count-- == 0)
1292 break;
1293
1294 rx_desc = TSEC_GET_CUR_RX_DESC(sc);
1295 flags = rx_desc->flags;
1296
1297 /* Check if there is anything to receive */
1298 if ((flags & TSEC_RXBD_E) || (c >= TSEC_RX_NUM_DESC)) {
1299 /*
1300 * Avoid generating another interrupt
1301 */
1302 if (flags & TSEC_RXBD_E)
1303 TSEC_WRITE(sc, TSEC_REG_IEVENT,
1304 TSEC_IEVENT_RXB | TSEC_IEVENT_RXF);
1305 /*
1306 * We didn't consume current descriptor and have to
1307 * return it to the queue
1308 */
1309 TSEC_BACK_CUR_RX_DESC(sc);
1310 break;
1311 }
1312
1313 if (flags & (TSEC_RXBD_LG | TSEC_RXBD_SH | TSEC_RXBD_NO |
1314 TSEC_RXBD_CR | TSEC_RXBD_OV | TSEC_RXBD_TR)) {
1315
1316 rx_desc->length = 0;
1317 rx_desc->flags = (rx_desc->flags &
1318 ~TSEC_RXBD_ZEROONINIT) | TSEC_RXBD_E | TSEC_RXBD_I;
1319
1320 if (sc->frame != NULL) {
1321 m_free(sc->frame);
1322 sc->frame = NULL;
1323 }
1324
1325 continue;
1326 }
1327
1328 /* Ok... process frame */
1329 i = TSEC_GET_CUR_RX_DESC_CNT(sc);
1330 m = rx_data[i].mbuf;
1331 m->m_len = rx_desc->length;
1332
1333 if (sc->frame != NULL) {
1334 if ((flags & TSEC_RXBD_L) != 0)
1335 m->m_len -= m_length(sc->frame, NULL);
1336
1337 m->m_flags &= ~M_PKTHDR;
1338 m_cat(sc->frame, m);
1339 } else {
1340 sc->frame = m;
1341 }
1342
1343 m = NULL;
1344
1345 if ((flags & TSEC_RXBD_L) != 0) {
1346 m = sc->frame;
1347 sc->frame = NULL;
1348 }
1349
1350 if (tsec_new_rxbuf(sc->tsec_rx_mtag, rx_data[i].map,
1351 &rx_data[i].mbuf, &rx_data[i].paddr)) {
1352 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
1353 /*
1354 * We ran out of mbufs; didn't consume current
1355 * descriptor and have to return it to the queue.
1356 */
1357 TSEC_BACK_CUR_RX_DESC(sc);
1358 break;
1359 }
1360
1361 /* Attach new buffer to descriptor and clear flags */
1362 rx_desc->bufptr = rx_data[i].paddr;
1363 rx_desc->length = 0;
1364 rx_desc->flags = (rx_desc->flags & ~TSEC_RXBD_ZEROONINIT) |
1365 TSEC_RXBD_E | TSEC_RXBD_I;
1366
1367 if (m != NULL) {
1368 m->m_pkthdr.rcvif = ifp;
1369
1370 m_fixhdr(m);
1371 m_adj(m, -ETHER_CRC_LEN);
1372
1373 if (sc->is_etsec)
1374 tsec_offload_process_frame(sc, m);
1375
1376 TSEC_RECEIVE_UNLOCK(sc);
1377 (*ifp->if_input)(ifp, m);
1378 TSEC_RECEIVE_LOCK(sc);
1379 rx_npkts++;
1380 }
1381 }
1382
1383 bus_dmamap_sync(sc->tsec_rx_dtag, sc->tsec_rx_dmap,
1384 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1385
1386 /*
1387 * Make sure TSEC receiver is not halted.
1388 *
1389 * Various conditions can stop the TSEC receiver, but not all are
1390 * signaled and handled by error interrupt, so make sure the receiver
1391 * is running. Writing to TSEC_REG_RSTAT restarts the receiver when
1392 * halted, and is harmless if already running.
1393 */
1394 TSEC_WRITE(sc, TSEC_REG_RSTAT, TSEC_RSTAT_QHLT);
1395 return (rx_npkts);
1396}
1397
1398void
1399tsec_receive_intr(void *arg)
1400{
1401 struct tsec_softc *sc = arg;
1402
1403 TSEC_RECEIVE_LOCK(sc);
1404
1405#ifdef DEVICE_POLLING
1406 if (sc->tsec_ifp->if_capenable & IFCAP_POLLING) {
1407 TSEC_RECEIVE_UNLOCK(sc);
1408 return;
1409 }
1410#endif
1411
1412 /* Confirm the interrupt was received by driver */
1413 TSEC_WRITE(sc, TSEC_REG_IEVENT, TSEC_IEVENT_RXB | TSEC_IEVENT_RXF);
1414 tsec_receive_intr_locked(sc, -1);
1415
1416 TSEC_RECEIVE_UNLOCK(sc);
1417}
1418
1419static void
1420tsec_transmit_intr_locked(struct tsec_softc *sc)
1421{
1422 struct tsec_desc *tx_desc;
1423 struct ifnet *ifp;
1424 struct mbuf *m0;
1425 bus_dmamap_t *mapp;
1426 int send = 0;
1427
1428 TSEC_TRANSMIT_LOCK_ASSERT(sc);
1429
1430 ifp = sc->tsec_ifp;
1431
1432 /* Update collision statistics */
1433 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, TSEC_READ(sc, TSEC_REG_MON_TNCL));
1434
1435 /* Reset collision counters in hardware */
1436 TSEC_WRITE(sc, TSEC_REG_MON_TSCL, 0);
1437 TSEC_WRITE(sc, TSEC_REG_MON_TMCL, 0);
1438 TSEC_WRITE(sc, TSEC_REG_MON_TLCL, 0);
1439 TSEC_WRITE(sc, TSEC_REG_MON_TXCL, 0);
1440 TSEC_WRITE(sc, TSEC_REG_MON_TNCL, 0);
1441
1442 bus_dmamap_sync(sc->tsec_tx_dtag, sc->tsec_tx_dmap,
1443 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1444
1445 while (TSEC_CUR_DIFF_DIRTY_TX_DESC(sc)) {
1446 tx_desc = TSEC_GET_DIRTY_TX_DESC(sc);
1447 if (tx_desc->flags & TSEC_TXBD_R) {
1448 TSEC_BACK_DIRTY_TX_DESC(sc);
1449 break;
1450 }
1451
1452 if ((tx_desc->flags & TSEC_TXBD_L) == 0)
1453 continue;
1454
1455 /*
1456 * This is the last buf in this packet, so unmap and free it.
1457 */
1458 m0 = TSEC_GET_TX_MBUF(sc);
1459 mapp = TSEC_GET_TX_MAP(sc);
1460
1461 bus_dmamap_sync(sc->tsec_tx_mtag, *mapp,
1462 BUS_DMASYNC_POSTWRITE);
1463 bus_dmamap_unload(sc->tsec_tx_mtag, *mapp);
1464
1465 TSEC_FREE_TX_MAP(sc, mapp);
1466 m_freem(m0);
1467
1468 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
1469 send = 1;
1470 }
1471 bus_dmamap_sync(sc->tsec_tx_dtag, sc->tsec_tx_dmap,
1472 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1473
1474 if (send) {
1475 /* Now send anything that was pending */
1476 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1477 tsec_start_locked(ifp);
1478
1479 /* Stop wathdog if all sent */
1480 if (TSEC_EMPTYQ_TX_MBUF(sc))
1481 sc->tsec_watchdog = 0;
1482 }
1483}
1484
1485void
1486tsec_transmit_intr(void *arg)
1487{
1488 struct tsec_softc *sc = arg;
1489
1490 TSEC_TRANSMIT_LOCK(sc);
1491
1492#ifdef DEVICE_POLLING
1493 if (sc->tsec_ifp->if_capenable & IFCAP_POLLING) {
1494 TSEC_TRANSMIT_UNLOCK(sc);
1495 return;
1496 }
1497#endif
1498 /* Confirm the interrupt was received by driver */
1499 TSEC_WRITE(sc, TSEC_REG_IEVENT, TSEC_IEVENT_TXB | TSEC_IEVENT_TXF);
1500 tsec_transmit_intr_locked(sc);
1501
1502 TSEC_TRANSMIT_UNLOCK(sc);
1503}
1504
1505static void
1506tsec_error_intr_locked(struct tsec_softc *sc, int count)
1507{
1508 struct ifnet *ifp;
1509 uint32_t eflags;
1510
1511 TSEC_GLOBAL_LOCK_ASSERT(sc);
1512
1513 ifp = sc->tsec_ifp;
1514
1515 eflags = TSEC_READ(sc, TSEC_REG_IEVENT);
1516
1517 /* Clear events bits in hardware */
1518 TSEC_WRITE(sc, TSEC_REG_IEVENT, TSEC_IEVENT_RXC | TSEC_IEVENT_BSY |
1519 TSEC_IEVENT_EBERR | TSEC_IEVENT_MSRO | TSEC_IEVENT_BABT |
1520 TSEC_IEVENT_TXC | TSEC_IEVENT_TXE | TSEC_IEVENT_LC |
1521 TSEC_IEVENT_CRL | TSEC_IEVENT_XFUN);
1522
1523 /* Check transmitter errors */
1524 if (eflags & TSEC_IEVENT_TXE) {
1525 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
1526
1527 if (eflags & TSEC_IEVENT_LC)
1528 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 1);
1529
1530 TSEC_WRITE(sc, TSEC_REG_TSTAT, TSEC_TSTAT_THLT);
1531 }
1532
1533 /* Check receiver errors */
1534 if (eflags & TSEC_IEVENT_BSY) {
1535 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
1536 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
1537
1538 /* Get data from RX buffers */
1539 tsec_receive_intr_locked(sc, count);
1540 }
1541
1542 if (ifp->if_flags & IFF_DEBUG)
1543 if_printf(ifp, "tsec_error_intr(): event flags: 0x%x\n",
1544 eflags);
1545
1546 if (eflags & TSEC_IEVENT_EBERR) {
1547 if_printf(ifp, "System bus error occurred during"
1548 "DMA transaction (flags: 0x%x)\n", eflags);
1549 tsec_init_locked(sc);
1550 }
1551
1552 if (eflags & TSEC_IEVENT_BABT)
1553 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
1554
1555 if (eflags & TSEC_IEVENT_BABR)
1556 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
1557}
1558
1559void
1560tsec_error_intr(void *arg)
1561{
1562 struct tsec_softc *sc = arg;
1563
1564 TSEC_GLOBAL_LOCK(sc);
1565 tsec_error_intr_locked(sc, -1);
1566 TSEC_GLOBAL_UNLOCK(sc);
1567}
1568
1569int
1570tsec_miibus_readreg(device_t dev, int phy, int reg)
1571{
1572 struct tsec_softc *sc;
1573 uint32_t timeout;
1574 int rv;
1575
1576 sc = device_get_softc(dev);
1577
1578 TSEC_PHY_LOCK();
1579 TSEC_PHY_WRITE(sc, TSEC_REG_MIIMADD, (phy << 8) | reg);
1580 TSEC_PHY_WRITE(sc, TSEC_REG_MIIMCOM, 0);
1581 TSEC_PHY_WRITE(sc, TSEC_REG_MIIMCOM, TSEC_MIIMCOM_READCYCLE);
1582
1583 timeout = TSEC_READ_RETRY;
1584 while (--timeout && TSEC_PHY_READ(sc, TSEC_REG_MIIMIND) &
1585 (TSEC_MIIMIND_NOTVALID | TSEC_MIIMIND_BUSY))
1586 DELAY(TSEC_READ_DELAY);
1587
1588 if (timeout == 0)
1589 device_printf(dev, "Timeout while reading from PHY!\n");
1590
1591 rv = TSEC_PHY_READ(sc, TSEC_REG_MIIMSTAT);
1592 TSEC_PHY_UNLOCK();
1593
1594 return (rv);
1595}
1596
1597int
1598tsec_miibus_writereg(device_t dev, int phy, int reg, int value)
1599{
1600 struct tsec_softc *sc;
1601 uint32_t timeout;
1602
1603 sc = device_get_softc(dev);
1604
1605 TSEC_PHY_LOCK();
1606 TSEC_PHY_WRITE(sc, TSEC_REG_MIIMADD, (phy << 8) | reg);
1607 TSEC_PHY_WRITE(sc, TSEC_REG_MIIMCON, value);
1608
1609 timeout = TSEC_READ_RETRY;
1610 while (--timeout && (TSEC_READ(sc, TSEC_REG_MIIMIND) &
1611 TSEC_MIIMIND_BUSY))
1612 DELAY(TSEC_READ_DELAY);
1613 TSEC_PHY_UNLOCK();
1614
1615 if (timeout == 0)
1616 device_printf(dev, "Timeout while writing to PHY!\n");
1617
1618 return (0);
1619}
1620
1621void
1622tsec_miibus_statchg(device_t dev)
1623{
1624 struct tsec_softc *sc;
1625 struct mii_data *mii;
1626 uint32_t ecntrl, id, tmp;
1627 int link;
1628
1629 sc = device_get_softc(dev);
1630 mii = sc->tsec_mii;
1631 link = ((mii->mii_media_status & IFM_ACTIVE) ? 1 : 0);
1632
1633 tmp = TSEC_READ(sc, TSEC_REG_MACCFG2) & ~TSEC_MACCFG2_IF;
1634
1635 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX)
1636 tmp |= TSEC_MACCFG2_FULLDUPLEX;
1637 else
1638 tmp &= ~TSEC_MACCFG2_FULLDUPLEX;
1639
1640 switch (IFM_SUBTYPE(mii->mii_media_active)) {
1641 case IFM_1000_T:
1642 case IFM_1000_SX:
1643 tmp |= TSEC_MACCFG2_GMII;
1644 sc->tsec_link = link;
1645 break;
1646 case IFM_100_TX:
1647 case IFM_10_T:
1648 tmp |= TSEC_MACCFG2_MII;
1649 sc->tsec_link = link;
1650 break;
1651 case IFM_NONE:
1652 if (link)
1653 device_printf(dev, "No speed selected but link "
1654 "active!\n");
1655 sc->tsec_link = 0;
1656 return;
1657 default:
1658 sc->tsec_link = 0;
1659 device_printf(dev, "Unknown speed (%d), link %s!\n",
1660 IFM_SUBTYPE(mii->mii_media_active),
1661 ((link) ? "up" : "down"));
1662 return;
1663 }
1664 TSEC_WRITE(sc, TSEC_REG_MACCFG2, tmp);
1665
1666 /* XXX kludge - use circumstantial evidence for reduced mode. */
1667 id = TSEC_READ(sc, TSEC_REG_ID2);
1668 if (id & 0xffff) {
1669 ecntrl = TSEC_READ(sc, TSEC_REG_ECNTRL) & ~TSEC_ECNTRL_R100M;
1670 ecntrl |= (tmp & TSEC_MACCFG2_MII) ? TSEC_ECNTRL_R100M : 0;
1671 TSEC_WRITE(sc, TSEC_REG_ECNTRL, ecntrl);
1672 }
1673}
1674
1675static void
1676tsec_add_sysctls(struct tsec_softc *sc)
1677{
1678 struct sysctl_ctx_list *ctx;
1679 struct sysctl_oid_list *children;
1680 struct sysctl_oid *tree;
1681
1682 ctx = device_get_sysctl_ctx(sc->dev);
1683 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev));
1684 tree = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "int_coal",
1685 CTLFLAG_RD, 0, "TSEC Interrupts coalescing");
1686 children = SYSCTL_CHILDREN(tree);
1687
1688 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rx_time",
1689 CTLTYPE_UINT | CTLFLAG_RW, sc, TSEC_IC_RX, tsec_sysctl_ic_time,
1690 "I", "IC RX time threshold (0-65535)");
1691 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rx_count",
1692 CTLTYPE_UINT | CTLFLAG_RW, sc, TSEC_IC_RX, tsec_sysctl_ic_count,
1693 "I", "IC RX frame count threshold (0-255)");
1694
1695 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_time",
1696 CTLTYPE_UINT | CTLFLAG_RW, sc, TSEC_IC_TX, tsec_sysctl_ic_time,
1697 "I", "IC TX time threshold (0-65535)");
1698 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_count",
1699 CTLTYPE_UINT | CTLFLAG_RW, sc, TSEC_IC_TX, tsec_sysctl_ic_count,
1700 "I", "IC TX frame count threshold (0-255)");
1701}
1702
1703/*
1704 * With Interrupt Coalescing (IC) active, a transmit/receive frame
1705 * interrupt is raised either upon:
1706 *
1707 * - threshold-defined period of time elapsed, or
1708 * - threshold-defined number of frames is received/transmitted,
1709 * whichever occurs first.
1710 *
1711 * The following sysctls regulate IC behaviour (for TX/RX separately):
1712 *
1713 * dev.tsec.<unit>.int_coal.rx_time
1714 * dev.tsec.<unit>.int_coal.rx_count
1715 * dev.tsec.<unit>.int_coal.tx_time
1716 * dev.tsec.<unit>.int_coal.tx_count
1717 *
1718 * Values:
1719 *
1720 * - 0 for either time or count disables IC on the given TX/RX path
1721 *
1722 * - count: 1-255 (expresses frame count number; note that value of 1 is
1723 * effectively IC off)
1724 *
1725 * - time: 1-65535 (value corresponds to a real time period and is
1726 * expressed in units equivalent to 64 TSEC interface clocks, i.e. one timer
1727 * threshold unit is 26.5 us, 2.56 us, or 512 ns, corresponding to 10 Mbps,
1728 * 100 Mbps, or 1Gbps, respectively. For detailed discussion consult the
1729 * TSEC reference manual.
1730 */
1731static int
1732tsec_sysctl_ic_time(SYSCTL_HANDLER_ARGS)
1733{
1734 int error;
1735 uint32_t time;
1736 struct tsec_softc *sc = (struct tsec_softc *)arg1;
1737
1738 time = (arg2 == TSEC_IC_RX) ? sc->rx_ic_time : sc->tx_ic_time;
1739
1740 error = sysctl_handle_int(oidp, &time, 0, req);
1741 if (error != 0)
1742 return (error);
1743
1744 if (time > 65535)
1745 return (EINVAL);
1746
1747 TSEC_IC_LOCK(sc);
1748 if (arg2 == TSEC_IC_RX) {
1749 sc->rx_ic_time = time;
1750 tsec_set_rxic(sc);
1751 } else {
1752 sc->tx_ic_time = time;
1753 tsec_set_txic(sc);
1754 }
1755 TSEC_IC_UNLOCK(sc);
1756
1757 return (0);
1758}
1759
1760static int
1761tsec_sysctl_ic_count(SYSCTL_HANDLER_ARGS)
1762{
1763 int error;
1764 uint32_t count;
1765 struct tsec_softc *sc = (struct tsec_softc *)arg1;
1766
1767 count = (arg2 == TSEC_IC_RX) ? sc->rx_ic_count : sc->tx_ic_count;
1768
1769 error = sysctl_handle_int(oidp, &count, 0, req);
1770 if (error != 0)
1771 return (error);
1772
1773 if (count > 255)
1774 return (EINVAL);
1775
1776 TSEC_IC_LOCK(sc);
1777 if (arg2 == TSEC_IC_RX) {
1778 sc->rx_ic_count = count;
1779 tsec_set_rxic(sc);
1780 } else {
1781 sc->tx_ic_count = count;
1782 tsec_set_txic(sc);
1783 }
1784 TSEC_IC_UNLOCK(sc);
1785
1786 return (0);
1787}
1788
1789static void
1790tsec_set_rxic(struct tsec_softc *sc)
1791{
1792 uint32_t rxic_val;
1793
1794 if (sc->rx_ic_count == 0 || sc->rx_ic_time == 0)
1795 /* Disable RX IC */
1796 rxic_val = 0;
1797 else {
1798 rxic_val = 0x80000000;
1799 rxic_val |= (sc->rx_ic_count << 21);
1800 rxic_val |= sc->rx_ic_time;
1801 }
1802
1803 TSEC_WRITE(sc, TSEC_REG_RXIC, rxic_val);
1804}
1805
1806static void
1807tsec_set_txic(struct tsec_softc *sc)
1808{
1809 uint32_t txic_val;
1810
1811 if (sc->tx_ic_count == 0 || sc->tx_ic_time == 0)
1812 /* Disable TX IC */
1813 txic_val = 0;
1814 else {
1815 txic_val = 0x80000000;
1816 txic_val |= (sc->tx_ic_count << 21);
1817 txic_val |= sc->tx_ic_time;
1818 }
1819
1820 TSEC_WRITE(sc, TSEC_REG_TXIC, txic_val);
1821}
1822
1823static void
1824tsec_offload_setup(struct tsec_softc *sc)
1825{
1826 struct ifnet *ifp = sc->tsec_ifp;
1827 uint32_t reg;
1828
1829 TSEC_GLOBAL_LOCK_ASSERT(sc);
1830
1831 reg = TSEC_READ(sc, TSEC_REG_TCTRL);
1832 reg |= TSEC_TCTRL_IPCSEN | TSEC_TCTRL_TUCSEN;
1833
1834 if (ifp->if_capenable & IFCAP_TXCSUM)
1835 ifp->if_hwassist = TSEC_CHECKSUM_FEATURES;
1836 else
1837 ifp->if_hwassist = 0;
1838
1839 TSEC_WRITE(sc, TSEC_REG_TCTRL, reg);
1840
1841 reg = TSEC_READ(sc, TSEC_REG_RCTRL);
1842 reg &= ~(TSEC_RCTRL_IPCSEN | TSEC_RCTRL_TUCSEN | TSEC_RCTRL_PRSDEP);
1843 reg |= TSEC_RCTRL_PRSDEP_PARSE_L2 | TSEC_RCTRL_VLEX;
1844
1845 if (ifp->if_capenable & IFCAP_RXCSUM)
1846 reg |= TSEC_RCTRL_IPCSEN | TSEC_RCTRL_TUCSEN |
1847 TSEC_RCTRL_PRSDEP_PARSE_L234;
1848
1849 TSEC_WRITE(sc, TSEC_REG_RCTRL, reg);
1850}
1851
1852
1853static void
1854tsec_offload_process_frame(struct tsec_softc *sc, struct mbuf *m)
1855{
1856 struct tsec_rx_fcb rx_fcb;
1857 int csum_flags = 0;
1858 int protocol, flags;
1859
1860 TSEC_RECEIVE_LOCK_ASSERT(sc);
1861
1862 m_copydata(m, 0, sizeof(struct tsec_rx_fcb), (caddr_t)(&rx_fcb));
1863 flags = rx_fcb.flags;
1864 protocol = rx_fcb.protocol;
1865
1866 if (TSEC_RX_FCB_IP_CSUM_CHECKED(flags)) {
1867 csum_flags |= CSUM_IP_CHECKED;
1868
1869 if ((flags & TSEC_RX_FCB_IP_CSUM_ERROR) == 0)
1870 csum_flags |= CSUM_IP_VALID;
1871 }
1872
1873 if ((protocol == IPPROTO_TCP || protocol == IPPROTO_UDP) &&
1874 TSEC_RX_FCB_TCP_UDP_CSUM_CHECKED(flags) &&
1875 (flags & TSEC_RX_FCB_TCP_UDP_CSUM_ERROR) == 0) {
1876
1877 csum_flags |= CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
1878 m->m_pkthdr.csum_data = 0xFFFF;
1879 }
1880
1881 m->m_pkthdr.csum_flags = csum_flags;
1882
1883 if (flags & TSEC_RX_FCB_VLAN) {
1884 m->m_pkthdr.ether_vtag = rx_fcb.vlan;
1885 m->m_flags |= M_VLANTAG;
1886 }
1887
1888 m_adj(m, sizeof(struct tsec_rx_fcb));
1889}
1890
1891static void
1892tsec_setup_multicast(struct tsec_softc *sc)
1893{
1894 uint32_t hashtable[8] = { 0, 0, 0, 0, 0, 0, 0, 0 };
1895 struct ifnet *ifp = sc->tsec_ifp;
1896 struct ifmultiaddr *ifma;
1897 uint32_t h;
1898 int i;
1899
1900 TSEC_GLOBAL_LOCK_ASSERT(sc);
1901
1902 if (ifp->if_flags & IFF_ALLMULTI) {
1903 for (i = 0; i < 8; i++)
1904 TSEC_WRITE(sc, TSEC_REG_GADDR(i), 0xFFFFFFFF);
1905
1906 return;
1907 }
1908
1909 if_maddr_rlock(ifp);
1910 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1911
1912 if (ifma->ifma_addr->sa_family != AF_LINK)
1913 continue;
1914
1915 h = (ether_crc32_be(LLADDR((struct sockaddr_dl *)
1916 ifma->ifma_addr), ETHER_ADDR_LEN) >> 24) & 0xFF;
1917
1918 hashtable[(h >> 5)] |= 1 << (0x1F - (h & 0x1F));
1919 }
1920 if_maddr_runlock(ifp);
1921
1922 for (i = 0; i < 8; i++)
1923 TSEC_WRITE(sc, TSEC_REG_GADDR(i), hashtable[i]);
1924}
1925
1926static int
1927tsec_set_mtu(struct tsec_softc *sc, unsigned int mtu)
1928{
1929
1930 mtu += ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + ETHER_CRC_LEN;
1931
1932 TSEC_GLOBAL_LOCK_ASSERT(sc);
1933
1934 if (mtu >= TSEC_MIN_FRAME_SIZE && mtu <= TSEC_MAX_FRAME_SIZE) {
1935 TSEC_WRITE(sc, TSEC_REG_MAXFRM, mtu);
1936 return (mtu);
1937 }
1938
1939 return (0);
1940}
2 * Copyright (C) 2007-2008 Semihalf, Rafal Jaworowski
3 * Copyright (C) 2006-2007 Semihalf, Piotr Kruszynski
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
18 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
19 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
20 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
21 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
22 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
23 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
24 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 */
26
27/*
28 * Freescale integrated Three-Speed Ethernet Controller (TSEC) driver.
29 */
30#include <sys/cdefs.h>
31__FBSDID("$FreeBSD: head/sys/dev/tsec/if_tsec.c 271849 2014-09-19 03:51:26Z glebius $");
32
33#ifdef HAVE_KERNEL_OPTION_HEADERS
34#include "opt_device_polling.h"
35#endif
36
37#include <sys/param.h>
38#include <sys/systm.h>
39#include <sys/bus.h>
40#include <sys/endian.h>
41#include <sys/mbuf.h>
42#include <sys/kernel.h>
43#include <sys/module.h>
44#include <sys/socket.h>
45#include <sys/sockio.h>
46#include <sys/sysctl.h>
47
48#include <net/bpf.h>
49#include <net/ethernet.h>
50#include <net/if.h>
51#include <net/if_var.h>
52#include <net/if_arp.h>
53#include <net/if_dl.h>
54#include <net/if_media.h>
55#include <net/if_types.h>
56#include <net/if_vlan_var.h>
57
58#include <netinet/in_systm.h>
59#include <netinet/in.h>
60#include <netinet/ip.h>
61
62#include <machine/bus.h>
63
64#include <dev/mii/mii.h>
65#include <dev/mii/miivar.h>
66
67#include <dev/tsec/if_tsec.h>
68#include <dev/tsec/if_tsecreg.h>
69
70static int tsec_alloc_dma_desc(device_t dev, bus_dma_tag_t *dtag,
71 bus_dmamap_t *dmap, bus_size_t dsize, void **vaddr, void *raddr,
72 const char *dname);
73static void tsec_dma_ctl(struct tsec_softc *sc, int state);
74static int tsec_encap(struct tsec_softc *sc, struct mbuf *m_head,
75 int fcb_inserted);
76static void tsec_free_dma(struct tsec_softc *sc);
77static void tsec_free_dma_desc(bus_dma_tag_t dtag, bus_dmamap_t dmap, void *vaddr);
78static int tsec_ifmedia_upd(struct ifnet *ifp);
79static void tsec_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr);
80static int tsec_new_rxbuf(bus_dma_tag_t tag, bus_dmamap_t map,
81 struct mbuf **mbufp, uint32_t *paddr);
82static void tsec_map_dma_addr(void *arg, bus_dma_segment_t *segs,
83 int nseg, int error);
84static void tsec_intrs_ctl(struct tsec_softc *sc, int state);
85static void tsec_init(void *xsc);
86static void tsec_init_locked(struct tsec_softc *sc);
87static int tsec_ioctl(struct ifnet *ifp, u_long command, caddr_t data);
88static void tsec_reset_mac(struct tsec_softc *sc);
89static void tsec_setfilter(struct tsec_softc *sc);
90static void tsec_set_mac_address(struct tsec_softc *sc);
91static void tsec_start(struct ifnet *ifp);
92static void tsec_start_locked(struct ifnet *ifp);
93static void tsec_stop(struct tsec_softc *sc);
94static void tsec_tick(void *arg);
95static void tsec_watchdog(struct tsec_softc *sc);
96static void tsec_add_sysctls(struct tsec_softc *sc);
97static int tsec_sysctl_ic_time(SYSCTL_HANDLER_ARGS);
98static int tsec_sysctl_ic_count(SYSCTL_HANDLER_ARGS);
99static void tsec_set_rxic(struct tsec_softc *sc);
100static void tsec_set_txic(struct tsec_softc *sc);
101static int tsec_receive_intr_locked(struct tsec_softc *sc, int count);
102static void tsec_transmit_intr_locked(struct tsec_softc *sc);
103static void tsec_error_intr_locked(struct tsec_softc *sc, int count);
104static void tsec_offload_setup(struct tsec_softc *sc);
105static void tsec_offload_process_frame(struct tsec_softc *sc,
106 struct mbuf *m);
107static void tsec_setup_multicast(struct tsec_softc *sc);
108static int tsec_set_mtu(struct tsec_softc *sc, unsigned int mtu);
109
110devclass_t tsec_devclass;
111DRIVER_MODULE(miibus, tsec, miibus_driver, miibus_devclass, 0, 0);
112MODULE_DEPEND(tsec, ether, 1, 1, 1);
113MODULE_DEPEND(tsec, miibus, 1, 1, 1);
114
115struct mtx tsec_phy_mtx;
116
117int
118tsec_attach(struct tsec_softc *sc)
119{
120 uint8_t hwaddr[ETHER_ADDR_LEN];
121 struct ifnet *ifp;
122 bus_dmamap_t *map_ptr;
123 bus_dmamap_t **map_pptr;
124 int error = 0;
125 int i;
126
127 /* Initialize global (because potentially shared) MII lock */
128 if (!mtx_initialized(&tsec_phy_mtx))
129 mtx_init(&tsec_phy_mtx, "tsec mii", NULL, MTX_DEF);
130
131 /* Reset all TSEC counters */
132 TSEC_TX_RX_COUNTERS_INIT(sc);
133
134 /* Stop DMA engine if enabled by firmware */
135 tsec_dma_ctl(sc, 0);
136
137 /* Reset MAC */
138 tsec_reset_mac(sc);
139
140 /* Disable interrupts for now */
141 tsec_intrs_ctl(sc, 0);
142
143 /* Configure defaults for interrupts coalescing */
144 sc->rx_ic_time = 768;
145 sc->rx_ic_count = 16;
146 sc->tx_ic_time = 768;
147 sc->tx_ic_count = 16;
148 tsec_set_rxic(sc);
149 tsec_set_txic(sc);
150 tsec_add_sysctls(sc);
151
152 /* Allocate a busdma tag and DMA safe memory for TX descriptors. */
153 error = tsec_alloc_dma_desc(sc->dev, &sc->tsec_tx_dtag,
154 &sc->tsec_tx_dmap, sizeof(*sc->tsec_tx_vaddr) * TSEC_TX_NUM_DESC,
155 (void **)&sc->tsec_tx_vaddr, &sc->tsec_tx_raddr, "TX");
156
157 if (error) {
158 tsec_detach(sc);
159 return (ENXIO);
160 }
161
162 /* Allocate a busdma tag and DMA safe memory for RX descriptors. */
163 error = tsec_alloc_dma_desc(sc->dev, &sc->tsec_rx_dtag,
164 &sc->tsec_rx_dmap, sizeof(*sc->tsec_rx_vaddr) * TSEC_RX_NUM_DESC,
165 (void **)&sc->tsec_rx_vaddr, &sc->tsec_rx_raddr, "RX");
166 if (error) {
167 tsec_detach(sc);
168 return (ENXIO);
169 }
170
171 /* Allocate a busdma tag for TX mbufs. */
172 error = bus_dma_tag_create(NULL, /* parent */
173 TSEC_TXBUFFER_ALIGNMENT, 0, /* alignment, boundary */
174 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
175 BUS_SPACE_MAXADDR, /* highaddr */
176 NULL, NULL, /* filtfunc, filtfuncarg */
177 MCLBYTES * (TSEC_TX_NUM_DESC - 1), /* maxsize */
178 TSEC_TX_NUM_DESC - 1, /* nsegments */
179 MCLBYTES, 0, /* maxsegsz, flags */
180 NULL, NULL, /* lockfunc, lockfuncarg */
181 &sc->tsec_tx_mtag); /* dmat */
182 if (error) {
183 device_printf(sc->dev, "failed to allocate busdma tag "
184 "(tx mbufs)\n");
185 tsec_detach(sc);
186 return (ENXIO);
187 }
188
189 /* Allocate a busdma tag for RX mbufs. */
190 error = bus_dma_tag_create(NULL, /* parent */
191 TSEC_RXBUFFER_ALIGNMENT, 0, /* alignment, boundary */
192 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
193 BUS_SPACE_MAXADDR, /* highaddr */
194 NULL, NULL, /* filtfunc, filtfuncarg */
195 MCLBYTES, /* maxsize */
196 1, /* nsegments */
197 MCLBYTES, 0, /* maxsegsz, flags */
198 NULL, NULL, /* lockfunc, lockfuncarg */
199 &sc->tsec_rx_mtag); /* dmat */
200 if (error) {
201 device_printf(sc->dev, "failed to allocate busdma tag "
202 "(rx mbufs)\n");
203 tsec_detach(sc);
204 return (ENXIO);
205 }
206
207 /* Create TX busdma maps */
208 map_ptr = sc->tx_map_data;
209 map_pptr = sc->tx_map_unused_data;
210
211 for (i = 0; i < TSEC_TX_NUM_DESC; i++) {
212 map_pptr[i] = &map_ptr[i];
213 error = bus_dmamap_create(sc->tsec_tx_mtag, 0, map_pptr[i]);
214 if (error) {
215 device_printf(sc->dev, "failed to init TX ring\n");
216 tsec_detach(sc);
217 return (ENXIO);
218 }
219 }
220
221 /* Create RX busdma maps and zero mbuf handlers */
222 for (i = 0; i < TSEC_RX_NUM_DESC; i++) {
223 error = bus_dmamap_create(sc->tsec_rx_mtag, 0,
224 &sc->rx_data[i].map);
225 if (error) {
226 device_printf(sc->dev, "failed to init RX ring\n");
227 tsec_detach(sc);
228 return (ENXIO);
229 }
230 sc->rx_data[i].mbuf = NULL;
231 }
232
233 /* Create mbufs for RX buffers */
234 for (i = 0; i < TSEC_RX_NUM_DESC; i++) {
235 error = tsec_new_rxbuf(sc->tsec_rx_mtag, sc->rx_data[i].map,
236 &sc->rx_data[i].mbuf, &sc->rx_data[i].paddr);
237 if (error) {
238 device_printf(sc->dev, "can't load rx DMA map %d, "
239 "error = %d\n", i, error);
240 tsec_detach(sc);
241 return (error);
242 }
243 }
244
245 /* Create network interface for upper layers */
246 ifp = sc->tsec_ifp = if_alloc(IFT_ETHER);
247 if (ifp == NULL) {
248 device_printf(sc->dev, "if_alloc() failed\n");
249 tsec_detach(sc);
250 return (ENOMEM);
251 }
252
253 ifp->if_softc = sc;
254 if_initname(ifp, device_get_name(sc->dev), device_get_unit(sc->dev));
255 ifp->if_flags = IFF_SIMPLEX | IFF_MULTICAST | IFF_BROADCAST;
256 ifp->if_init = tsec_init;
257 ifp->if_start = tsec_start;
258 ifp->if_ioctl = tsec_ioctl;
259
260 IFQ_SET_MAXLEN(&ifp->if_snd, TSEC_TX_NUM_DESC - 1);
261 ifp->if_snd.ifq_drv_maxlen = TSEC_TX_NUM_DESC - 1;
262 IFQ_SET_READY(&ifp->if_snd);
263
264 ifp->if_capabilities = IFCAP_VLAN_MTU;
265 if (sc->is_etsec)
266 ifp->if_capabilities |= IFCAP_HWCSUM;
267
268 ifp->if_capenable = ifp->if_capabilities;
269
270#ifdef DEVICE_POLLING
271 /* Advertise that polling is supported */
272 ifp->if_capabilities |= IFCAP_POLLING;
273#endif
274
275 /* Attach PHY(s) */
276 error = mii_attach(sc->dev, &sc->tsec_miibus, ifp, tsec_ifmedia_upd,
277 tsec_ifmedia_sts, BMSR_DEFCAPMASK, sc->phyaddr, MII_OFFSET_ANY,
278 0);
279 if (error) {
280 device_printf(sc->dev, "attaching PHYs failed\n");
281 if_free(ifp);
282 sc->tsec_ifp = NULL;
283 tsec_detach(sc);
284 return (error);
285 }
286 sc->tsec_mii = device_get_softc(sc->tsec_miibus);
287
288 /* Set MAC address */
289 tsec_get_hwaddr(sc, hwaddr);
290 ether_ifattach(ifp, hwaddr);
291
292 return (0);
293}
294
295int
296tsec_detach(struct tsec_softc *sc)
297{
298
299 if (sc->tsec_ifp != NULL) {
300#ifdef DEVICE_POLLING
301 if (sc->tsec_ifp->if_capenable & IFCAP_POLLING)
302 ether_poll_deregister(sc->tsec_ifp);
303#endif
304
305 /* Stop TSEC controller and free TX queue */
306 if (sc->sc_rres)
307 tsec_shutdown(sc->dev);
308
309 /* Detach network interface */
310 ether_ifdetach(sc->tsec_ifp);
311 if_free(sc->tsec_ifp);
312 sc->tsec_ifp = NULL;
313 }
314
315 /* Free DMA resources */
316 tsec_free_dma(sc);
317
318 return (0);
319}
320
321int
322tsec_shutdown(device_t dev)
323{
324 struct tsec_softc *sc;
325
326 sc = device_get_softc(dev);
327
328 TSEC_GLOBAL_LOCK(sc);
329 tsec_stop(sc);
330 TSEC_GLOBAL_UNLOCK(sc);
331 return (0);
332}
333
334int
335tsec_suspend(device_t dev)
336{
337
338 /* TODO not implemented! */
339 return (0);
340}
341
342int
343tsec_resume(device_t dev)
344{
345
346 /* TODO not implemented! */
347 return (0);
348}
349
350static void
351tsec_init(void *xsc)
352{
353 struct tsec_softc *sc = xsc;
354
355 TSEC_GLOBAL_LOCK(sc);
356 tsec_init_locked(sc);
357 TSEC_GLOBAL_UNLOCK(sc);
358}
359
360static void
361tsec_init_locked(struct tsec_softc *sc)
362{
363 struct tsec_desc *tx_desc = sc->tsec_tx_vaddr;
364 struct tsec_desc *rx_desc = sc->tsec_rx_vaddr;
365 struct ifnet *ifp = sc->tsec_ifp;
366 uint32_t timeout, val, i;
367
368 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
369 return;
370
371 TSEC_GLOBAL_LOCK_ASSERT(sc);
372 tsec_stop(sc);
373
374 /*
375 * These steps are according to the MPC8555E PowerQUICCIII RM:
376 * 14.7 Initialization/Application Information
377 */
378
379 /* Step 1: soft reset MAC */
380 tsec_reset_mac(sc);
381
382 /* Step 2: Initialize MACCFG2 */
383 TSEC_WRITE(sc, TSEC_REG_MACCFG2,
384 TSEC_MACCFG2_FULLDUPLEX | /* Full Duplex = 1 */
385 TSEC_MACCFG2_PADCRC | /* PAD/CRC append */
386 TSEC_MACCFG2_GMII | /* I/F Mode bit */
387 TSEC_MACCFG2_PRECNT /* Preamble count = 7 */
388 );
389
390 /* Step 3: Initialize ECNTRL
391 * While the documentation states that R100M is ignored if RPM is
392 * not set, it does seem to be needed to get the orange boxes to
393 * work (which have a Marvell 88E1111 PHY). Go figure.
394 */
395
396 /*
397 * XXX kludge - use circumstancial evidence to program ECNTRL
398 * correctly. Ideally we need some board information to guide
399 * us here.
400 */
401 i = TSEC_READ(sc, TSEC_REG_ID2);
402 val = (i & 0xffff)
403 ? (TSEC_ECNTRL_TBIM | TSEC_ECNTRL_SGMIIM) /* Sumatra */
404 : TSEC_ECNTRL_R100M; /* Orange + CDS */
405 TSEC_WRITE(sc, TSEC_REG_ECNTRL, TSEC_ECNTRL_STEN | val);
406
407 /* Step 4: Initialize MAC station address */
408 tsec_set_mac_address(sc);
409
410 /*
411 * Step 5: Assign a Physical address to the TBI so as to not conflict
412 * with the external PHY physical address
413 */
414 TSEC_WRITE(sc, TSEC_REG_TBIPA, 5);
415
416 TSEC_PHY_LOCK(sc);
417
418 /* Step 6: Reset the management interface */
419 TSEC_PHY_WRITE(sc, TSEC_REG_MIIMCFG, TSEC_MIIMCFG_RESETMGMT);
420
421 /* Step 7: Setup the MII Mgmt clock speed */
422 TSEC_PHY_WRITE(sc, TSEC_REG_MIIMCFG, TSEC_MIIMCFG_CLKDIV28);
423
424 /* Step 8: Read MII Mgmt indicator register and check for Busy = 0 */
425 timeout = TSEC_READ_RETRY;
426 while (--timeout && (TSEC_PHY_READ(sc, TSEC_REG_MIIMIND) &
427 TSEC_MIIMIND_BUSY))
428 DELAY(TSEC_READ_DELAY);
429 if (timeout == 0) {
430 if_printf(ifp, "tsec_init_locked(): Mgmt busy timeout\n");
431 return;
432 }
433 TSEC_PHY_UNLOCK(sc);
434
435 /* Step 9: Setup the MII Mgmt */
436 mii_mediachg(sc->tsec_mii);
437
438 /* Step 10: Clear IEVENT register */
439 TSEC_WRITE(sc, TSEC_REG_IEVENT, 0xffffffff);
440
441 /* Step 11: Enable interrupts */
442#ifdef DEVICE_POLLING
443 /*
444 * ...only if polling is not turned on. Disable interrupts explicitly
445 * if polling is enabled.
446 */
447 if (ifp->if_capenable & IFCAP_POLLING )
448 tsec_intrs_ctl(sc, 0);
449 else
450#endif /* DEVICE_POLLING */
451 tsec_intrs_ctl(sc, 1);
452
453 /* Step 12: Initialize IADDRn */
454 TSEC_WRITE(sc, TSEC_REG_IADDR0, 0);
455 TSEC_WRITE(sc, TSEC_REG_IADDR1, 0);
456 TSEC_WRITE(sc, TSEC_REG_IADDR2, 0);
457 TSEC_WRITE(sc, TSEC_REG_IADDR3, 0);
458 TSEC_WRITE(sc, TSEC_REG_IADDR4, 0);
459 TSEC_WRITE(sc, TSEC_REG_IADDR5, 0);
460 TSEC_WRITE(sc, TSEC_REG_IADDR6, 0);
461 TSEC_WRITE(sc, TSEC_REG_IADDR7, 0);
462
463 /* Step 13: Initialize GADDRn */
464 TSEC_WRITE(sc, TSEC_REG_GADDR0, 0);
465 TSEC_WRITE(sc, TSEC_REG_GADDR1, 0);
466 TSEC_WRITE(sc, TSEC_REG_GADDR2, 0);
467 TSEC_WRITE(sc, TSEC_REG_GADDR3, 0);
468 TSEC_WRITE(sc, TSEC_REG_GADDR4, 0);
469 TSEC_WRITE(sc, TSEC_REG_GADDR5, 0);
470 TSEC_WRITE(sc, TSEC_REG_GADDR6, 0);
471 TSEC_WRITE(sc, TSEC_REG_GADDR7, 0);
472
473 /* Step 14: Initialize RCTRL */
474 TSEC_WRITE(sc, TSEC_REG_RCTRL, 0);
475
476 /* Step 15: Initialize DMACTRL */
477 tsec_dma_ctl(sc, 1);
478
479 /* Step 16: Initialize FIFO_PAUSE_CTRL */
480 TSEC_WRITE(sc, TSEC_REG_FIFO_PAUSE_CTRL, TSEC_FIFO_PAUSE_CTRL_EN);
481
482 /*
483 * Step 17: Initialize transmit/receive descriptor rings.
484 * Initialize TBASE and RBASE.
485 */
486 TSEC_WRITE(sc, TSEC_REG_TBASE, sc->tsec_tx_raddr);
487 TSEC_WRITE(sc, TSEC_REG_RBASE, sc->tsec_rx_raddr);
488
489 for (i = 0; i < TSEC_TX_NUM_DESC; i++) {
490 tx_desc[i].bufptr = 0;
491 tx_desc[i].length = 0;
492 tx_desc[i].flags = ((i == TSEC_TX_NUM_DESC - 1) ?
493 TSEC_TXBD_W : 0);
494 }
495 bus_dmamap_sync(sc->tsec_tx_dtag, sc->tsec_tx_dmap,
496 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
497
498 for (i = 0; i < TSEC_RX_NUM_DESC; i++) {
499 rx_desc[i].bufptr = sc->rx_data[i].paddr;
500 rx_desc[i].length = 0;
501 rx_desc[i].flags = TSEC_RXBD_E | TSEC_RXBD_I |
502 ((i == TSEC_RX_NUM_DESC - 1) ? TSEC_RXBD_W : 0);
503 }
504 bus_dmamap_sync(sc->tsec_rx_dtag, sc->tsec_rx_dmap,
505 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
506
507 /* Step 18: Initialize the maximum receive buffer length */
508 TSEC_WRITE(sc, TSEC_REG_MRBLR, MCLBYTES);
509
510 /* Step 19: Configure ethernet frame sizes */
511 TSEC_WRITE(sc, TSEC_REG_MINFLR, TSEC_MIN_FRAME_SIZE);
512 tsec_set_mtu(sc, ifp->if_mtu);
513
514 /* Step 20: Enable Rx and RxBD sdata snooping */
515 TSEC_WRITE(sc, TSEC_REG_ATTR, TSEC_ATTR_RDSEN | TSEC_ATTR_RBDSEN);
516 TSEC_WRITE(sc, TSEC_REG_ATTRELI, 0);
517
518 /* Step 21: Reset collision counters in hardware */
519 TSEC_WRITE(sc, TSEC_REG_MON_TSCL, 0);
520 TSEC_WRITE(sc, TSEC_REG_MON_TMCL, 0);
521 TSEC_WRITE(sc, TSEC_REG_MON_TLCL, 0);
522 TSEC_WRITE(sc, TSEC_REG_MON_TXCL, 0);
523 TSEC_WRITE(sc, TSEC_REG_MON_TNCL, 0);
524
525 /* Step 22: Mask all CAM interrupts */
526 TSEC_WRITE(sc, TSEC_REG_MON_CAM1, 0xffffffff);
527 TSEC_WRITE(sc, TSEC_REG_MON_CAM2, 0xffffffff);
528
529 /* Step 23: Enable Rx and Tx */
530 val = TSEC_READ(sc, TSEC_REG_MACCFG1);
531 val |= (TSEC_MACCFG1_RX_EN | TSEC_MACCFG1_TX_EN);
532 TSEC_WRITE(sc, TSEC_REG_MACCFG1, val);
533
534 /* Step 24: Reset TSEC counters for Tx and Rx rings */
535 TSEC_TX_RX_COUNTERS_INIT(sc);
536
537 /* Step 25: Setup TCP/IP Off-Load engine */
538 if (sc->is_etsec)
539 tsec_offload_setup(sc);
540
541 /* Step 26: Setup multicast filters */
542 tsec_setup_multicast(sc);
543
544 /* Step 27: Activate network interface */
545 ifp->if_drv_flags |= IFF_DRV_RUNNING;
546 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
547 sc->tsec_if_flags = ifp->if_flags;
548 sc->tsec_watchdog = 0;
549
550 /* Schedule watchdog timeout */
551 callout_reset(&sc->tsec_callout, hz, tsec_tick, sc);
552}
553
554static void
555tsec_set_mac_address(struct tsec_softc *sc)
556{
557 uint32_t macbuf[2] = { 0, 0 };
558 char *macbufp, *curmac;
559 int i;
560
561 TSEC_GLOBAL_LOCK_ASSERT(sc);
562
563 KASSERT((ETHER_ADDR_LEN <= sizeof(macbuf)),
564 ("tsec_set_mac_address: (%d <= %d", ETHER_ADDR_LEN,
565 sizeof(macbuf)));
566
567 macbufp = (char *)macbuf;
568 curmac = (char *)IF_LLADDR(sc->tsec_ifp);
569
570 /* Correct order of MAC address bytes */
571 for (i = 1; i <= ETHER_ADDR_LEN; i++)
572 macbufp[ETHER_ADDR_LEN-i] = curmac[i-1];
573
574 /* Initialize MAC station address MACSTNADDR2 and MACSTNADDR1 */
575 TSEC_WRITE(sc, TSEC_REG_MACSTNADDR2, macbuf[1]);
576 TSEC_WRITE(sc, TSEC_REG_MACSTNADDR1, macbuf[0]);
577}
578
579/*
580 * DMA control function, if argument state is:
581 * 0 - DMA engine will be disabled
582 * 1 - DMA engine will be enabled
583 */
584static void
585tsec_dma_ctl(struct tsec_softc *sc, int state)
586{
587 device_t dev;
588 uint32_t dma_flags, timeout;
589
590 dev = sc->dev;
591
592 dma_flags = TSEC_READ(sc, TSEC_REG_DMACTRL);
593
594 switch (state) {
595 case 0:
596 /* Temporarily clear stop graceful stop bits. */
597 tsec_dma_ctl(sc, 1000);
598
599 /* Set it again */
600 dma_flags |= (TSEC_DMACTRL_GRS | TSEC_DMACTRL_GTS);
601 break;
602 case 1000:
603 case 1:
604 /* Set write with response (WWR), wait (WOP) and snoop bits */
605 dma_flags |= (TSEC_DMACTRL_TDSEN | TSEC_DMACTRL_TBDSEN |
606 DMACTRL_WWR | DMACTRL_WOP);
607
608 /* Clear graceful stop bits */
609 dma_flags &= ~(TSEC_DMACTRL_GRS | TSEC_DMACTRL_GTS);
610 break;
611 default:
612 device_printf(dev, "tsec_dma_ctl(): unknown state value: %d\n",
613 state);
614 }
615
616 TSEC_WRITE(sc, TSEC_REG_DMACTRL, dma_flags);
617
618 switch (state) {
619 case 0:
620 /* Wait for DMA stop */
621 timeout = TSEC_READ_RETRY;
622 while (--timeout && (!(TSEC_READ(sc, TSEC_REG_IEVENT) &
623 (TSEC_IEVENT_GRSC | TSEC_IEVENT_GTSC))))
624 DELAY(TSEC_READ_DELAY);
625
626 if (timeout == 0)
627 device_printf(dev, "tsec_dma_ctl(): timeout!\n");
628 break;
629 case 1:
630 /* Restart transmission function */
631 TSEC_WRITE(sc, TSEC_REG_TSTAT, TSEC_TSTAT_THLT);
632 }
633}
634
635/*
636 * Interrupts control function, if argument state is:
637 * 0 - all TSEC interrupts will be masked
638 * 1 - all TSEC interrupts will be unmasked
639 */
640static void
641tsec_intrs_ctl(struct tsec_softc *sc, int state)
642{
643 device_t dev;
644
645 dev = sc->dev;
646
647 switch (state) {
648 case 0:
649 TSEC_WRITE(sc, TSEC_REG_IMASK, 0);
650 break;
651 case 1:
652 TSEC_WRITE(sc, TSEC_REG_IMASK, TSEC_IMASK_BREN |
653 TSEC_IMASK_RXCEN | TSEC_IMASK_BSYEN | TSEC_IMASK_EBERREN |
654 TSEC_IMASK_BTEN | TSEC_IMASK_TXEEN | TSEC_IMASK_TXBEN |
655 TSEC_IMASK_TXFEN | TSEC_IMASK_XFUNEN | TSEC_IMASK_RXFEN);
656 break;
657 default:
658 device_printf(dev, "tsec_intrs_ctl(): unknown state value: %d\n",
659 state);
660 }
661}
662
663static void
664tsec_reset_mac(struct tsec_softc *sc)
665{
666 uint32_t maccfg1_flags;
667
668 /* Set soft reset bit */
669 maccfg1_flags = TSEC_READ(sc, TSEC_REG_MACCFG1);
670 maccfg1_flags |= TSEC_MACCFG1_SOFT_RESET;
671 TSEC_WRITE(sc, TSEC_REG_MACCFG1, maccfg1_flags);
672
673 /* Clear soft reset bit */
674 maccfg1_flags = TSEC_READ(sc, TSEC_REG_MACCFG1);
675 maccfg1_flags &= ~TSEC_MACCFG1_SOFT_RESET;
676 TSEC_WRITE(sc, TSEC_REG_MACCFG1, maccfg1_flags);
677}
678
679static void
680tsec_watchdog(struct tsec_softc *sc)
681{
682 struct ifnet *ifp;
683
684 TSEC_GLOBAL_LOCK_ASSERT(sc);
685
686 if (sc->tsec_watchdog == 0 || --sc->tsec_watchdog > 0)
687 return;
688
689 ifp = sc->tsec_ifp;
690 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
691 if_printf(ifp, "watchdog timeout\n");
692
693 tsec_stop(sc);
694 tsec_init_locked(sc);
695}
696
697static void
698tsec_start(struct ifnet *ifp)
699{
700 struct tsec_softc *sc = ifp->if_softc;
701
702 TSEC_TRANSMIT_LOCK(sc);
703 tsec_start_locked(ifp);
704 TSEC_TRANSMIT_UNLOCK(sc);
705}
706
707static void
708tsec_start_locked(struct ifnet *ifp)
709{
710 struct tsec_softc *sc;
711 struct mbuf *m0, *mtmp;
712 struct tsec_tx_fcb *tx_fcb;
713 unsigned int queued = 0;
714 int csum_flags, fcb_inserted = 0;
715
716 sc = ifp->if_softc;
717
718 TSEC_TRANSMIT_LOCK_ASSERT(sc);
719
720 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
721 IFF_DRV_RUNNING)
722 return;
723
724 if (sc->tsec_link == 0)
725 return;
726
727 bus_dmamap_sync(sc->tsec_tx_dtag, sc->tsec_tx_dmap,
728 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
729
730 while (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) {
731 /* Get packet from the queue */
732 IFQ_DRV_DEQUEUE(&ifp->if_snd, m0);
733 if (m0 == NULL)
734 break;
735
736 /* Insert TCP/IP Off-load frame control block */
737 csum_flags = m0->m_pkthdr.csum_flags;
738 if (csum_flags) {
739
740 M_PREPEND(m0, sizeof(struct tsec_tx_fcb), M_NOWAIT);
741 if (m0 == NULL)
742 break;
743
744 tx_fcb = mtod(m0, struct tsec_tx_fcb *);
745 tx_fcb->flags = 0;
746 tx_fcb->l3_offset = ETHER_HDR_LEN;
747 tx_fcb->l4_offset = sizeof(struct ip);
748
749 if (csum_flags & CSUM_IP)
750 tx_fcb->flags |= TSEC_TX_FCB_IP4 |
751 TSEC_TX_FCB_CSUM_IP;
752
753 if (csum_flags & CSUM_TCP)
754 tx_fcb->flags |= TSEC_TX_FCB_TCP |
755 TSEC_TX_FCB_CSUM_TCP_UDP;
756
757 if (csum_flags & CSUM_UDP)
758 tx_fcb->flags |= TSEC_TX_FCB_UDP |
759 TSEC_TX_FCB_CSUM_TCP_UDP;
760
761 fcb_inserted = 1;
762 }
763
764 mtmp = m_defrag(m0, M_NOWAIT);
765 if (mtmp)
766 m0 = mtmp;
767
768 if (tsec_encap(sc, m0, fcb_inserted)) {
769 IFQ_DRV_PREPEND(&ifp->if_snd, m0);
770 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
771 break;
772 }
773 queued++;
774 BPF_MTAP(ifp, m0);
775 }
776 bus_dmamap_sync(sc->tsec_tx_dtag, sc->tsec_tx_dmap,
777 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
778
779 if (queued) {
780 /* Enable transmitter and watchdog timer */
781 TSEC_WRITE(sc, TSEC_REG_TSTAT, TSEC_TSTAT_THLT);
782 sc->tsec_watchdog = 5;
783 }
784}
785
786static int
787tsec_encap(struct tsec_softc *sc, struct mbuf *m0, int fcb_inserted)
788{
789 struct tsec_desc *tx_desc = NULL;
790 struct ifnet *ifp;
791 bus_dma_segment_t segs[TSEC_TX_NUM_DESC];
792 bus_dmamap_t *mapp;
793 int csum_flag = 0, error, seg, nsegs;
794
795 TSEC_TRANSMIT_LOCK_ASSERT(sc);
796
797 ifp = sc->tsec_ifp;
798
799 if (TSEC_FREE_TX_DESC(sc) == 0) {
800 /* No free descriptors */
801 return (-1);
802 }
803
804 /* Fetch unused map */
805 mapp = TSEC_ALLOC_TX_MAP(sc);
806
807 /* Create mapping in DMA memory */
808 error = bus_dmamap_load_mbuf_sg(sc->tsec_tx_mtag,
809 *mapp, m0, segs, &nsegs, BUS_DMA_NOWAIT);
810 if (error != 0 || nsegs > TSEC_FREE_TX_DESC(sc) || nsegs <= 0) {
811 bus_dmamap_unload(sc->tsec_tx_mtag, *mapp);
812 TSEC_FREE_TX_MAP(sc, mapp);
813 return ((error != 0) ? error : -1);
814 }
815 bus_dmamap_sync(sc->tsec_tx_mtag, *mapp, BUS_DMASYNC_PREWRITE);
816
817 if ((ifp->if_flags & IFF_DEBUG) && (nsegs > 1))
818 if_printf(ifp, "TX buffer has %d segments\n", nsegs);
819
820 if (fcb_inserted)
821 csum_flag = TSEC_TXBD_TOE;
822
823 /* Everything is ok, now we can send buffers */
824 for (seg = 0; seg < nsegs; seg++) {
825 tx_desc = TSEC_GET_CUR_TX_DESC(sc);
826
827 tx_desc->length = segs[seg].ds_len;
828 tx_desc->bufptr = segs[seg].ds_addr;
829
830 /*
831 * Set flags:
832 * - wrap
833 * - checksum
834 * - ready to send
835 * - transmit the CRC sequence after the last data byte
836 * - interrupt after the last buffer
837 */
838 tx_desc->flags =
839 (tx_desc->flags & TSEC_TXBD_W) |
840 ((seg == 0) ? csum_flag : 0) | TSEC_TXBD_R | TSEC_TXBD_TC |
841 ((seg == nsegs - 1) ? TSEC_TXBD_L | TSEC_TXBD_I : 0);
842 }
843
844 /* Save mbuf and DMA mapping for release at later stage */
845 TSEC_PUT_TX_MBUF(sc, m0);
846 TSEC_PUT_TX_MAP(sc, mapp);
847
848 return (0);
849}
850
851static void
852tsec_setfilter(struct tsec_softc *sc)
853{
854 struct ifnet *ifp;
855 uint32_t flags;
856
857 ifp = sc->tsec_ifp;
858 flags = TSEC_READ(sc, TSEC_REG_RCTRL);
859
860 /* Promiscuous mode */
861 if (ifp->if_flags & IFF_PROMISC)
862 flags |= TSEC_RCTRL_PROM;
863 else
864 flags &= ~TSEC_RCTRL_PROM;
865
866 TSEC_WRITE(sc, TSEC_REG_RCTRL, flags);
867}
868
869#ifdef DEVICE_POLLING
870static poll_handler_t tsec_poll;
871
872static int
873tsec_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
874{
875 uint32_t ie;
876 struct tsec_softc *sc = ifp->if_softc;
877 int rx_npkts;
878
879 rx_npkts = 0;
880
881 TSEC_GLOBAL_LOCK(sc);
882 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
883 TSEC_GLOBAL_UNLOCK(sc);
884 return (rx_npkts);
885 }
886
887 if (cmd == POLL_AND_CHECK_STATUS) {
888 tsec_error_intr_locked(sc, count);
889
890 /* Clear all events reported */
891 ie = TSEC_READ(sc, TSEC_REG_IEVENT);
892 TSEC_WRITE(sc, TSEC_REG_IEVENT, ie);
893 }
894
895 tsec_transmit_intr_locked(sc);
896
897 TSEC_GLOBAL_TO_RECEIVE_LOCK(sc);
898
899 rx_npkts = tsec_receive_intr_locked(sc, count);
900
901 TSEC_RECEIVE_UNLOCK(sc);
902
903 return (rx_npkts);
904}
905#endif /* DEVICE_POLLING */
906
907static int
908tsec_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
909{
910 struct tsec_softc *sc = ifp->if_softc;
911 struct ifreq *ifr = (struct ifreq *)data;
912 device_t dev;
913 int mask, error = 0;
914
915 dev = sc->dev;
916
917 switch (command) {
918 case SIOCSIFMTU:
919 TSEC_GLOBAL_LOCK(sc);
920 if (tsec_set_mtu(sc, ifr->ifr_mtu))
921 ifp->if_mtu = ifr->ifr_mtu;
922 else
923 error = EINVAL;
924 TSEC_GLOBAL_UNLOCK(sc);
925 break;
926 case SIOCSIFFLAGS:
927 TSEC_GLOBAL_LOCK(sc);
928 if (ifp->if_flags & IFF_UP) {
929 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
930 if ((sc->tsec_if_flags ^ ifp->if_flags) &
931 IFF_PROMISC)
932 tsec_setfilter(sc);
933
934 if ((sc->tsec_if_flags ^ ifp->if_flags) &
935 IFF_ALLMULTI)
936 tsec_setup_multicast(sc);
937 } else
938 tsec_init_locked(sc);
939 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING)
940 tsec_stop(sc);
941
942 sc->tsec_if_flags = ifp->if_flags;
943 TSEC_GLOBAL_UNLOCK(sc);
944 break;
945 case SIOCADDMULTI:
946 case SIOCDELMULTI:
947 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
948 TSEC_GLOBAL_LOCK(sc);
949 tsec_setup_multicast(sc);
950 TSEC_GLOBAL_UNLOCK(sc);
951 }
952 case SIOCGIFMEDIA:
953 case SIOCSIFMEDIA:
954 error = ifmedia_ioctl(ifp, ifr, &sc->tsec_mii->mii_media,
955 command);
956 break;
957 case SIOCSIFCAP:
958 mask = ifp->if_capenable ^ ifr->ifr_reqcap;
959 if ((mask & IFCAP_HWCSUM) && sc->is_etsec) {
960 TSEC_GLOBAL_LOCK(sc);
961 ifp->if_capenable &= ~IFCAP_HWCSUM;
962 ifp->if_capenable |= IFCAP_HWCSUM & ifr->ifr_reqcap;
963 tsec_offload_setup(sc);
964 TSEC_GLOBAL_UNLOCK(sc);
965 }
966#ifdef DEVICE_POLLING
967 if (mask & IFCAP_POLLING) {
968 if (ifr->ifr_reqcap & IFCAP_POLLING) {
969 error = ether_poll_register(tsec_poll, ifp);
970 if (error)
971 return (error);
972
973 TSEC_GLOBAL_LOCK(sc);
974 /* Disable interrupts */
975 tsec_intrs_ctl(sc, 0);
976 ifp->if_capenable |= IFCAP_POLLING;
977 TSEC_GLOBAL_UNLOCK(sc);
978 } else {
979 error = ether_poll_deregister(ifp);
980 TSEC_GLOBAL_LOCK(sc);
981 /* Enable interrupts */
982 tsec_intrs_ctl(sc, 1);
983 ifp->if_capenable &= ~IFCAP_POLLING;
984 TSEC_GLOBAL_UNLOCK(sc);
985 }
986 }
987#endif
988 break;
989
990 default:
991 error = ether_ioctl(ifp, command, data);
992 }
993
994 /* Flush buffers if not empty */
995 if (ifp->if_flags & IFF_UP)
996 tsec_start(ifp);
997 return (error);
998}
999
1000static int
1001tsec_ifmedia_upd(struct ifnet *ifp)
1002{
1003 struct tsec_softc *sc = ifp->if_softc;
1004 struct mii_data *mii;
1005
1006 TSEC_TRANSMIT_LOCK(sc);
1007
1008 mii = sc->tsec_mii;
1009 mii_mediachg(mii);
1010
1011 TSEC_TRANSMIT_UNLOCK(sc);
1012 return (0);
1013}
1014
1015static void
1016tsec_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1017{
1018 struct tsec_softc *sc = ifp->if_softc;
1019 struct mii_data *mii;
1020
1021 TSEC_TRANSMIT_LOCK(sc);
1022
1023 mii = sc->tsec_mii;
1024 mii_pollstat(mii);
1025
1026 ifmr->ifm_active = mii->mii_media_active;
1027 ifmr->ifm_status = mii->mii_media_status;
1028
1029 TSEC_TRANSMIT_UNLOCK(sc);
1030}
1031
1032static int
1033tsec_new_rxbuf(bus_dma_tag_t tag, bus_dmamap_t map, struct mbuf **mbufp,
1034 uint32_t *paddr)
1035{
1036 struct mbuf *new_mbuf;
1037 bus_dma_segment_t seg[1];
1038 int error, nsegs;
1039
1040 KASSERT(mbufp != NULL, ("NULL mbuf pointer!"));
1041
1042 new_mbuf = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, MCLBYTES);
1043 if (new_mbuf == NULL)
1044 return (ENOBUFS);
1045 new_mbuf->m_len = new_mbuf->m_pkthdr.len = new_mbuf->m_ext.ext_size;
1046
1047 if (*mbufp) {
1048 bus_dmamap_sync(tag, map, BUS_DMASYNC_POSTREAD);
1049 bus_dmamap_unload(tag, map);
1050 }
1051
1052 error = bus_dmamap_load_mbuf_sg(tag, map, new_mbuf, seg, &nsegs,
1053 BUS_DMA_NOWAIT);
1054 KASSERT(nsegs == 1, ("Too many segments returned!"));
1055 if (nsegs != 1 || error)
1056 panic("tsec_new_rxbuf(): nsegs(%d), error(%d)", nsegs, error);
1057
1058#if 0
1059 if (error) {
1060 printf("tsec: bus_dmamap_load_mbuf_sg() returned: %d!\n",
1061 error);
1062 m_freem(new_mbuf);
1063 return (ENOBUFS);
1064 }
1065#endif
1066
1067#if 0
1068 KASSERT(((seg->ds_addr) & (TSEC_RXBUFFER_ALIGNMENT-1)) == 0,
1069 ("Wrong alignment of RX buffer!"));
1070#endif
1071 bus_dmamap_sync(tag, map, BUS_DMASYNC_PREREAD);
1072
1073 (*mbufp) = new_mbuf;
1074 (*paddr) = seg->ds_addr;
1075 return (0);
1076}
1077
1078static void
1079tsec_map_dma_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
1080{
1081 u_int32_t *paddr;
1082
1083 KASSERT(nseg == 1, ("wrong number of segments, should be 1"));
1084 paddr = arg;
1085 *paddr = segs->ds_addr;
1086}
1087
1088static int
1089tsec_alloc_dma_desc(device_t dev, bus_dma_tag_t *dtag, bus_dmamap_t *dmap,
1090 bus_size_t dsize, void **vaddr, void *raddr, const char *dname)
1091{
1092 int error;
1093
1094 /* Allocate a busdma tag and DMA safe memory for TX/RX descriptors. */
1095 error = bus_dma_tag_create(NULL, /* parent */
1096 PAGE_SIZE, 0, /* alignment, boundary */
1097 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
1098 BUS_SPACE_MAXADDR, /* highaddr */
1099 NULL, NULL, /* filtfunc, filtfuncarg */
1100 dsize, 1, /* maxsize, nsegments */
1101 dsize, 0, /* maxsegsz, flags */
1102 NULL, NULL, /* lockfunc, lockfuncarg */
1103 dtag); /* dmat */
1104
1105 if (error) {
1106 device_printf(dev, "failed to allocate busdma %s tag\n",
1107 dname);
1108 (*vaddr) = NULL;
1109 return (ENXIO);
1110 }
1111
1112 error = bus_dmamem_alloc(*dtag, vaddr, BUS_DMA_NOWAIT | BUS_DMA_ZERO,
1113 dmap);
1114 if (error) {
1115 device_printf(dev, "failed to allocate %s DMA safe memory\n",
1116 dname);
1117 bus_dma_tag_destroy(*dtag);
1118 (*vaddr) = NULL;
1119 return (ENXIO);
1120 }
1121
1122 error = bus_dmamap_load(*dtag, *dmap, *vaddr, dsize,
1123 tsec_map_dma_addr, raddr, BUS_DMA_NOWAIT);
1124 if (error) {
1125 device_printf(dev, "cannot get address of the %s "
1126 "descriptors\n", dname);
1127 bus_dmamem_free(*dtag, *vaddr, *dmap);
1128 bus_dma_tag_destroy(*dtag);
1129 (*vaddr) = NULL;
1130 return (ENXIO);
1131 }
1132
1133 return (0);
1134}
1135
1136static void
1137tsec_free_dma_desc(bus_dma_tag_t dtag, bus_dmamap_t dmap, void *vaddr)
1138{
1139
1140 if (vaddr == NULL)
1141 return;
1142
1143 /* Unmap descriptors from DMA memory */
1144 bus_dmamap_sync(dtag, dmap, BUS_DMASYNC_POSTREAD |
1145 BUS_DMASYNC_POSTWRITE);
1146 bus_dmamap_unload(dtag, dmap);
1147
1148 /* Free descriptors memory */
1149 bus_dmamem_free(dtag, vaddr, dmap);
1150
1151 /* Destroy descriptors tag */
1152 bus_dma_tag_destroy(dtag);
1153}
1154
1155static void
1156tsec_free_dma(struct tsec_softc *sc)
1157{
1158 int i;
1159
1160 /* Free TX maps */
1161 for (i = 0; i < TSEC_TX_NUM_DESC; i++)
1162 if (sc->tx_map_data[i] != NULL)
1163 bus_dmamap_destroy(sc->tsec_tx_mtag,
1164 sc->tx_map_data[i]);
1165 /* Destroy tag for TX mbufs */
1166 bus_dma_tag_destroy(sc->tsec_tx_mtag);
1167
1168 /* Free RX mbufs and maps */
1169 for (i = 0; i < TSEC_RX_NUM_DESC; i++) {
1170 if (sc->rx_data[i].mbuf) {
1171 /* Unload buffer from DMA */
1172 bus_dmamap_sync(sc->tsec_rx_mtag, sc->rx_data[i].map,
1173 BUS_DMASYNC_POSTREAD);
1174 bus_dmamap_unload(sc->tsec_rx_mtag,
1175 sc->rx_data[i].map);
1176
1177 /* Free buffer */
1178 m_freem(sc->rx_data[i].mbuf);
1179 }
1180 /* Destroy map for this buffer */
1181 if (sc->rx_data[i].map != NULL)
1182 bus_dmamap_destroy(sc->tsec_rx_mtag,
1183 sc->rx_data[i].map);
1184 }
1185 /* Destroy tag for RX mbufs */
1186 bus_dma_tag_destroy(sc->tsec_rx_mtag);
1187
1188 /* Unload TX/RX descriptors */
1189 tsec_free_dma_desc(sc->tsec_tx_dtag, sc->tsec_tx_dmap,
1190 sc->tsec_tx_vaddr);
1191 tsec_free_dma_desc(sc->tsec_rx_dtag, sc->tsec_rx_dmap,
1192 sc->tsec_rx_vaddr);
1193}
1194
1195static void
1196tsec_stop(struct tsec_softc *sc)
1197{
1198 struct ifnet *ifp;
1199 struct mbuf *m0;
1200 bus_dmamap_t *mapp;
1201 uint32_t tmpval;
1202
1203 TSEC_GLOBAL_LOCK_ASSERT(sc);
1204
1205 ifp = sc->tsec_ifp;
1206
1207 /* Disable interface and watchdog timer */
1208 callout_stop(&sc->tsec_callout);
1209 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
1210 sc->tsec_watchdog = 0;
1211
1212 /* Disable all interrupts and stop DMA */
1213 tsec_intrs_ctl(sc, 0);
1214 tsec_dma_ctl(sc, 0);
1215
1216 /* Remove pending data from TX queue */
1217 while (!TSEC_EMPTYQ_TX_MBUF(sc)) {
1218 m0 = TSEC_GET_TX_MBUF(sc);
1219 mapp = TSEC_GET_TX_MAP(sc);
1220
1221 bus_dmamap_sync(sc->tsec_tx_mtag, *mapp,
1222 BUS_DMASYNC_POSTWRITE);
1223 bus_dmamap_unload(sc->tsec_tx_mtag, *mapp);
1224
1225 TSEC_FREE_TX_MAP(sc, mapp);
1226 m_freem(m0);
1227 }
1228
1229 /* Disable RX and TX */
1230 tmpval = TSEC_READ(sc, TSEC_REG_MACCFG1);
1231 tmpval &= ~(TSEC_MACCFG1_RX_EN | TSEC_MACCFG1_TX_EN);
1232 TSEC_WRITE(sc, TSEC_REG_MACCFG1, tmpval);
1233 DELAY(10);
1234}
1235
1236static void
1237tsec_tick(void *arg)
1238{
1239 struct tsec_softc *sc = arg;
1240 struct ifnet *ifp;
1241 int link;
1242
1243 TSEC_GLOBAL_LOCK(sc);
1244
1245 tsec_watchdog(sc);
1246
1247 ifp = sc->tsec_ifp;
1248 link = sc->tsec_link;
1249
1250 mii_tick(sc->tsec_mii);
1251
1252 if (link == 0 && sc->tsec_link == 1 &&
1253 (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)))
1254 tsec_start_locked(ifp);
1255
1256 /* Schedule another timeout one second from now. */
1257 callout_reset(&sc->tsec_callout, hz, tsec_tick, sc);
1258
1259 TSEC_GLOBAL_UNLOCK(sc);
1260}
1261
1262/*
1263 * This is the core RX routine. It replenishes mbufs in the descriptor and
1264 * sends data which have been dma'ed into host memory to upper layer.
1265 *
1266 * Loops at most count times if count is > 0, or until done if count < 0.
1267 */
1268static int
1269tsec_receive_intr_locked(struct tsec_softc *sc, int count)
1270{
1271 struct tsec_desc *rx_desc;
1272 struct ifnet *ifp;
1273 struct rx_data_type *rx_data;
1274 struct mbuf *m;
1275 device_t dev;
1276 uint32_t i;
1277 int c, rx_npkts;
1278 uint16_t flags;
1279
1280 TSEC_RECEIVE_LOCK_ASSERT(sc);
1281
1282 ifp = sc->tsec_ifp;
1283 rx_data = sc->rx_data;
1284 dev = sc->dev;
1285 rx_npkts = 0;
1286
1287 bus_dmamap_sync(sc->tsec_rx_dtag, sc->tsec_rx_dmap,
1288 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1289
1290 for (c = 0; ; c++) {
1291 if (count >= 0 && count-- == 0)
1292 break;
1293
1294 rx_desc = TSEC_GET_CUR_RX_DESC(sc);
1295 flags = rx_desc->flags;
1296
1297 /* Check if there is anything to receive */
1298 if ((flags & TSEC_RXBD_E) || (c >= TSEC_RX_NUM_DESC)) {
1299 /*
1300 * Avoid generating another interrupt
1301 */
1302 if (flags & TSEC_RXBD_E)
1303 TSEC_WRITE(sc, TSEC_REG_IEVENT,
1304 TSEC_IEVENT_RXB | TSEC_IEVENT_RXF);
1305 /*
1306 * We didn't consume current descriptor and have to
1307 * return it to the queue
1308 */
1309 TSEC_BACK_CUR_RX_DESC(sc);
1310 break;
1311 }
1312
1313 if (flags & (TSEC_RXBD_LG | TSEC_RXBD_SH | TSEC_RXBD_NO |
1314 TSEC_RXBD_CR | TSEC_RXBD_OV | TSEC_RXBD_TR)) {
1315
1316 rx_desc->length = 0;
1317 rx_desc->flags = (rx_desc->flags &
1318 ~TSEC_RXBD_ZEROONINIT) | TSEC_RXBD_E | TSEC_RXBD_I;
1319
1320 if (sc->frame != NULL) {
1321 m_free(sc->frame);
1322 sc->frame = NULL;
1323 }
1324
1325 continue;
1326 }
1327
1328 /* Ok... process frame */
1329 i = TSEC_GET_CUR_RX_DESC_CNT(sc);
1330 m = rx_data[i].mbuf;
1331 m->m_len = rx_desc->length;
1332
1333 if (sc->frame != NULL) {
1334 if ((flags & TSEC_RXBD_L) != 0)
1335 m->m_len -= m_length(sc->frame, NULL);
1336
1337 m->m_flags &= ~M_PKTHDR;
1338 m_cat(sc->frame, m);
1339 } else {
1340 sc->frame = m;
1341 }
1342
1343 m = NULL;
1344
1345 if ((flags & TSEC_RXBD_L) != 0) {
1346 m = sc->frame;
1347 sc->frame = NULL;
1348 }
1349
1350 if (tsec_new_rxbuf(sc->tsec_rx_mtag, rx_data[i].map,
1351 &rx_data[i].mbuf, &rx_data[i].paddr)) {
1352 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
1353 /*
1354 * We ran out of mbufs; didn't consume current
1355 * descriptor and have to return it to the queue.
1356 */
1357 TSEC_BACK_CUR_RX_DESC(sc);
1358 break;
1359 }
1360
1361 /* Attach new buffer to descriptor and clear flags */
1362 rx_desc->bufptr = rx_data[i].paddr;
1363 rx_desc->length = 0;
1364 rx_desc->flags = (rx_desc->flags & ~TSEC_RXBD_ZEROONINIT) |
1365 TSEC_RXBD_E | TSEC_RXBD_I;
1366
1367 if (m != NULL) {
1368 m->m_pkthdr.rcvif = ifp;
1369
1370 m_fixhdr(m);
1371 m_adj(m, -ETHER_CRC_LEN);
1372
1373 if (sc->is_etsec)
1374 tsec_offload_process_frame(sc, m);
1375
1376 TSEC_RECEIVE_UNLOCK(sc);
1377 (*ifp->if_input)(ifp, m);
1378 TSEC_RECEIVE_LOCK(sc);
1379 rx_npkts++;
1380 }
1381 }
1382
1383 bus_dmamap_sync(sc->tsec_rx_dtag, sc->tsec_rx_dmap,
1384 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1385
1386 /*
1387 * Make sure TSEC receiver is not halted.
1388 *
1389 * Various conditions can stop the TSEC receiver, but not all are
1390 * signaled and handled by error interrupt, so make sure the receiver
1391 * is running. Writing to TSEC_REG_RSTAT restarts the receiver when
1392 * halted, and is harmless if already running.
1393 */
1394 TSEC_WRITE(sc, TSEC_REG_RSTAT, TSEC_RSTAT_QHLT);
1395 return (rx_npkts);
1396}
1397
1398void
1399tsec_receive_intr(void *arg)
1400{
1401 struct tsec_softc *sc = arg;
1402
1403 TSEC_RECEIVE_LOCK(sc);
1404
1405#ifdef DEVICE_POLLING
1406 if (sc->tsec_ifp->if_capenable & IFCAP_POLLING) {
1407 TSEC_RECEIVE_UNLOCK(sc);
1408 return;
1409 }
1410#endif
1411
1412 /* Confirm the interrupt was received by driver */
1413 TSEC_WRITE(sc, TSEC_REG_IEVENT, TSEC_IEVENT_RXB | TSEC_IEVENT_RXF);
1414 tsec_receive_intr_locked(sc, -1);
1415
1416 TSEC_RECEIVE_UNLOCK(sc);
1417}
1418
1419static void
1420tsec_transmit_intr_locked(struct tsec_softc *sc)
1421{
1422 struct tsec_desc *tx_desc;
1423 struct ifnet *ifp;
1424 struct mbuf *m0;
1425 bus_dmamap_t *mapp;
1426 int send = 0;
1427
1428 TSEC_TRANSMIT_LOCK_ASSERT(sc);
1429
1430 ifp = sc->tsec_ifp;
1431
1432 /* Update collision statistics */
1433 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, TSEC_READ(sc, TSEC_REG_MON_TNCL));
1434
1435 /* Reset collision counters in hardware */
1436 TSEC_WRITE(sc, TSEC_REG_MON_TSCL, 0);
1437 TSEC_WRITE(sc, TSEC_REG_MON_TMCL, 0);
1438 TSEC_WRITE(sc, TSEC_REG_MON_TLCL, 0);
1439 TSEC_WRITE(sc, TSEC_REG_MON_TXCL, 0);
1440 TSEC_WRITE(sc, TSEC_REG_MON_TNCL, 0);
1441
1442 bus_dmamap_sync(sc->tsec_tx_dtag, sc->tsec_tx_dmap,
1443 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1444
1445 while (TSEC_CUR_DIFF_DIRTY_TX_DESC(sc)) {
1446 tx_desc = TSEC_GET_DIRTY_TX_DESC(sc);
1447 if (tx_desc->flags & TSEC_TXBD_R) {
1448 TSEC_BACK_DIRTY_TX_DESC(sc);
1449 break;
1450 }
1451
1452 if ((tx_desc->flags & TSEC_TXBD_L) == 0)
1453 continue;
1454
1455 /*
1456 * This is the last buf in this packet, so unmap and free it.
1457 */
1458 m0 = TSEC_GET_TX_MBUF(sc);
1459 mapp = TSEC_GET_TX_MAP(sc);
1460
1461 bus_dmamap_sync(sc->tsec_tx_mtag, *mapp,
1462 BUS_DMASYNC_POSTWRITE);
1463 bus_dmamap_unload(sc->tsec_tx_mtag, *mapp);
1464
1465 TSEC_FREE_TX_MAP(sc, mapp);
1466 m_freem(m0);
1467
1468 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
1469 send = 1;
1470 }
1471 bus_dmamap_sync(sc->tsec_tx_dtag, sc->tsec_tx_dmap,
1472 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1473
1474 if (send) {
1475 /* Now send anything that was pending */
1476 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1477 tsec_start_locked(ifp);
1478
1479 /* Stop wathdog if all sent */
1480 if (TSEC_EMPTYQ_TX_MBUF(sc))
1481 sc->tsec_watchdog = 0;
1482 }
1483}
1484
1485void
1486tsec_transmit_intr(void *arg)
1487{
1488 struct tsec_softc *sc = arg;
1489
1490 TSEC_TRANSMIT_LOCK(sc);
1491
1492#ifdef DEVICE_POLLING
1493 if (sc->tsec_ifp->if_capenable & IFCAP_POLLING) {
1494 TSEC_TRANSMIT_UNLOCK(sc);
1495 return;
1496 }
1497#endif
1498 /* Confirm the interrupt was received by driver */
1499 TSEC_WRITE(sc, TSEC_REG_IEVENT, TSEC_IEVENT_TXB | TSEC_IEVENT_TXF);
1500 tsec_transmit_intr_locked(sc);
1501
1502 TSEC_TRANSMIT_UNLOCK(sc);
1503}
1504
1505static void
1506tsec_error_intr_locked(struct tsec_softc *sc, int count)
1507{
1508 struct ifnet *ifp;
1509 uint32_t eflags;
1510
1511 TSEC_GLOBAL_LOCK_ASSERT(sc);
1512
1513 ifp = sc->tsec_ifp;
1514
1515 eflags = TSEC_READ(sc, TSEC_REG_IEVENT);
1516
1517 /* Clear events bits in hardware */
1518 TSEC_WRITE(sc, TSEC_REG_IEVENT, TSEC_IEVENT_RXC | TSEC_IEVENT_BSY |
1519 TSEC_IEVENT_EBERR | TSEC_IEVENT_MSRO | TSEC_IEVENT_BABT |
1520 TSEC_IEVENT_TXC | TSEC_IEVENT_TXE | TSEC_IEVENT_LC |
1521 TSEC_IEVENT_CRL | TSEC_IEVENT_XFUN);
1522
1523 /* Check transmitter errors */
1524 if (eflags & TSEC_IEVENT_TXE) {
1525 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
1526
1527 if (eflags & TSEC_IEVENT_LC)
1528 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 1);
1529
1530 TSEC_WRITE(sc, TSEC_REG_TSTAT, TSEC_TSTAT_THLT);
1531 }
1532
1533 /* Check receiver errors */
1534 if (eflags & TSEC_IEVENT_BSY) {
1535 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
1536 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
1537
1538 /* Get data from RX buffers */
1539 tsec_receive_intr_locked(sc, count);
1540 }
1541
1542 if (ifp->if_flags & IFF_DEBUG)
1543 if_printf(ifp, "tsec_error_intr(): event flags: 0x%x\n",
1544 eflags);
1545
1546 if (eflags & TSEC_IEVENT_EBERR) {
1547 if_printf(ifp, "System bus error occurred during"
1548 "DMA transaction (flags: 0x%x)\n", eflags);
1549 tsec_init_locked(sc);
1550 }
1551
1552 if (eflags & TSEC_IEVENT_BABT)
1553 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
1554
1555 if (eflags & TSEC_IEVENT_BABR)
1556 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
1557}
1558
1559void
1560tsec_error_intr(void *arg)
1561{
1562 struct tsec_softc *sc = arg;
1563
1564 TSEC_GLOBAL_LOCK(sc);
1565 tsec_error_intr_locked(sc, -1);
1566 TSEC_GLOBAL_UNLOCK(sc);
1567}
1568
1569int
1570tsec_miibus_readreg(device_t dev, int phy, int reg)
1571{
1572 struct tsec_softc *sc;
1573 uint32_t timeout;
1574 int rv;
1575
1576 sc = device_get_softc(dev);
1577
1578 TSEC_PHY_LOCK();
1579 TSEC_PHY_WRITE(sc, TSEC_REG_MIIMADD, (phy << 8) | reg);
1580 TSEC_PHY_WRITE(sc, TSEC_REG_MIIMCOM, 0);
1581 TSEC_PHY_WRITE(sc, TSEC_REG_MIIMCOM, TSEC_MIIMCOM_READCYCLE);
1582
1583 timeout = TSEC_READ_RETRY;
1584 while (--timeout && TSEC_PHY_READ(sc, TSEC_REG_MIIMIND) &
1585 (TSEC_MIIMIND_NOTVALID | TSEC_MIIMIND_BUSY))
1586 DELAY(TSEC_READ_DELAY);
1587
1588 if (timeout == 0)
1589 device_printf(dev, "Timeout while reading from PHY!\n");
1590
1591 rv = TSEC_PHY_READ(sc, TSEC_REG_MIIMSTAT);
1592 TSEC_PHY_UNLOCK();
1593
1594 return (rv);
1595}
1596
1597int
1598tsec_miibus_writereg(device_t dev, int phy, int reg, int value)
1599{
1600 struct tsec_softc *sc;
1601 uint32_t timeout;
1602
1603 sc = device_get_softc(dev);
1604
1605 TSEC_PHY_LOCK();
1606 TSEC_PHY_WRITE(sc, TSEC_REG_MIIMADD, (phy << 8) | reg);
1607 TSEC_PHY_WRITE(sc, TSEC_REG_MIIMCON, value);
1608
1609 timeout = TSEC_READ_RETRY;
1610 while (--timeout && (TSEC_READ(sc, TSEC_REG_MIIMIND) &
1611 TSEC_MIIMIND_BUSY))
1612 DELAY(TSEC_READ_DELAY);
1613 TSEC_PHY_UNLOCK();
1614
1615 if (timeout == 0)
1616 device_printf(dev, "Timeout while writing to PHY!\n");
1617
1618 return (0);
1619}
1620
1621void
1622tsec_miibus_statchg(device_t dev)
1623{
1624 struct tsec_softc *sc;
1625 struct mii_data *mii;
1626 uint32_t ecntrl, id, tmp;
1627 int link;
1628
1629 sc = device_get_softc(dev);
1630 mii = sc->tsec_mii;
1631 link = ((mii->mii_media_status & IFM_ACTIVE) ? 1 : 0);
1632
1633 tmp = TSEC_READ(sc, TSEC_REG_MACCFG2) & ~TSEC_MACCFG2_IF;
1634
1635 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX)
1636 tmp |= TSEC_MACCFG2_FULLDUPLEX;
1637 else
1638 tmp &= ~TSEC_MACCFG2_FULLDUPLEX;
1639
1640 switch (IFM_SUBTYPE(mii->mii_media_active)) {
1641 case IFM_1000_T:
1642 case IFM_1000_SX:
1643 tmp |= TSEC_MACCFG2_GMII;
1644 sc->tsec_link = link;
1645 break;
1646 case IFM_100_TX:
1647 case IFM_10_T:
1648 tmp |= TSEC_MACCFG2_MII;
1649 sc->tsec_link = link;
1650 break;
1651 case IFM_NONE:
1652 if (link)
1653 device_printf(dev, "No speed selected but link "
1654 "active!\n");
1655 sc->tsec_link = 0;
1656 return;
1657 default:
1658 sc->tsec_link = 0;
1659 device_printf(dev, "Unknown speed (%d), link %s!\n",
1660 IFM_SUBTYPE(mii->mii_media_active),
1661 ((link) ? "up" : "down"));
1662 return;
1663 }
1664 TSEC_WRITE(sc, TSEC_REG_MACCFG2, tmp);
1665
1666 /* XXX kludge - use circumstantial evidence for reduced mode. */
1667 id = TSEC_READ(sc, TSEC_REG_ID2);
1668 if (id & 0xffff) {
1669 ecntrl = TSEC_READ(sc, TSEC_REG_ECNTRL) & ~TSEC_ECNTRL_R100M;
1670 ecntrl |= (tmp & TSEC_MACCFG2_MII) ? TSEC_ECNTRL_R100M : 0;
1671 TSEC_WRITE(sc, TSEC_REG_ECNTRL, ecntrl);
1672 }
1673}
1674
1675static void
1676tsec_add_sysctls(struct tsec_softc *sc)
1677{
1678 struct sysctl_ctx_list *ctx;
1679 struct sysctl_oid_list *children;
1680 struct sysctl_oid *tree;
1681
1682 ctx = device_get_sysctl_ctx(sc->dev);
1683 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev));
1684 tree = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "int_coal",
1685 CTLFLAG_RD, 0, "TSEC Interrupts coalescing");
1686 children = SYSCTL_CHILDREN(tree);
1687
1688 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rx_time",
1689 CTLTYPE_UINT | CTLFLAG_RW, sc, TSEC_IC_RX, tsec_sysctl_ic_time,
1690 "I", "IC RX time threshold (0-65535)");
1691 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rx_count",
1692 CTLTYPE_UINT | CTLFLAG_RW, sc, TSEC_IC_RX, tsec_sysctl_ic_count,
1693 "I", "IC RX frame count threshold (0-255)");
1694
1695 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_time",
1696 CTLTYPE_UINT | CTLFLAG_RW, sc, TSEC_IC_TX, tsec_sysctl_ic_time,
1697 "I", "IC TX time threshold (0-65535)");
1698 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_count",
1699 CTLTYPE_UINT | CTLFLAG_RW, sc, TSEC_IC_TX, tsec_sysctl_ic_count,
1700 "I", "IC TX frame count threshold (0-255)");
1701}
1702
1703/*
1704 * With Interrupt Coalescing (IC) active, a transmit/receive frame
1705 * interrupt is raised either upon:
1706 *
1707 * - threshold-defined period of time elapsed, or
1708 * - threshold-defined number of frames is received/transmitted,
1709 * whichever occurs first.
1710 *
1711 * The following sysctls regulate IC behaviour (for TX/RX separately):
1712 *
1713 * dev.tsec.<unit>.int_coal.rx_time
1714 * dev.tsec.<unit>.int_coal.rx_count
1715 * dev.tsec.<unit>.int_coal.tx_time
1716 * dev.tsec.<unit>.int_coal.tx_count
1717 *
1718 * Values:
1719 *
1720 * - 0 for either time or count disables IC on the given TX/RX path
1721 *
1722 * - count: 1-255 (expresses frame count number; note that value of 1 is
1723 * effectively IC off)
1724 *
1725 * - time: 1-65535 (value corresponds to a real time period and is
1726 * expressed in units equivalent to 64 TSEC interface clocks, i.e. one timer
1727 * threshold unit is 26.5 us, 2.56 us, or 512 ns, corresponding to 10 Mbps,
1728 * 100 Mbps, or 1Gbps, respectively. For detailed discussion consult the
1729 * TSEC reference manual.
1730 */
1731static int
1732tsec_sysctl_ic_time(SYSCTL_HANDLER_ARGS)
1733{
1734 int error;
1735 uint32_t time;
1736 struct tsec_softc *sc = (struct tsec_softc *)arg1;
1737
1738 time = (arg2 == TSEC_IC_RX) ? sc->rx_ic_time : sc->tx_ic_time;
1739
1740 error = sysctl_handle_int(oidp, &time, 0, req);
1741 if (error != 0)
1742 return (error);
1743
1744 if (time > 65535)
1745 return (EINVAL);
1746
1747 TSEC_IC_LOCK(sc);
1748 if (arg2 == TSEC_IC_RX) {
1749 sc->rx_ic_time = time;
1750 tsec_set_rxic(sc);
1751 } else {
1752 sc->tx_ic_time = time;
1753 tsec_set_txic(sc);
1754 }
1755 TSEC_IC_UNLOCK(sc);
1756
1757 return (0);
1758}
1759
1760static int
1761tsec_sysctl_ic_count(SYSCTL_HANDLER_ARGS)
1762{
1763 int error;
1764 uint32_t count;
1765 struct tsec_softc *sc = (struct tsec_softc *)arg1;
1766
1767 count = (arg2 == TSEC_IC_RX) ? sc->rx_ic_count : sc->tx_ic_count;
1768
1769 error = sysctl_handle_int(oidp, &count, 0, req);
1770 if (error != 0)
1771 return (error);
1772
1773 if (count > 255)
1774 return (EINVAL);
1775
1776 TSEC_IC_LOCK(sc);
1777 if (arg2 == TSEC_IC_RX) {
1778 sc->rx_ic_count = count;
1779 tsec_set_rxic(sc);
1780 } else {
1781 sc->tx_ic_count = count;
1782 tsec_set_txic(sc);
1783 }
1784 TSEC_IC_UNLOCK(sc);
1785
1786 return (0);
1787}
1788
1789static void
1790tsec_set_rxic(struct tsec_softc *sc)
1791{
1792 uint32_t rxic_val;
1793
1794 if (sc->rx_ic_count == 0 || sc->rx_ic_time == 0)
1795 /* Disable RX IC */
1796 rxic_val = 0;
1797 else {
1798 rxic_val = 0x80000000;
1799 rxic_val |= (sc->rx_ic_count << 21);
1800 rxic_val |= sc->rx_ic_time;
1801 }
1802
1803 TSEC_WRITE(sc, TSEC_REG_RXIC, rxic_val);
1804}
1805
1806static void
1807tsec_set_txic(struct tsec_softc *sc)
1808{
1809 uint32_t txic_val;
1810
1811 if (sc->tx_ic_count == 0 || sc->tx_ic_time == 0)
1812 /* Disable TX IC */
1813 txic_val = 0;
1814 else {
1815 txic_val = 0x80000000;
1816 txic_val |= (sc->tx_ic_count << 21);
1817 txic_val |= sc->tx_ic_time;
1818 }
1819
1820 TSEC_WRITE(sc, TSEC_REG_TXIC, txic_val);
1821}
1822
1823static void
1824tsec_offload_setup(struct tsec_softc *sc)
1825{
1826 struct ifnet *ifp = sc->tsec_ifp;
1827 uint32_t reg;
1828
1829 TSEC_GLOBAL_LOCK_ASSERT(sc);
1830
1831 reg = TSEC_READ(sc, TSEC_REG_TCTRL);
1832 reg |= TSEC_TCTRL_IPCSEN | TSEC_TCTRL_TUCSEN;
1833
1834 if (ifp->if_capenable & IFCAP_TXCSUM)
1835 ifp->if_hwassist = TSEC_CHECKSUM_FEATURES;
1836 else
1837 ifp->if_hwassist = 0;
1838
1839 TSEC_WRITE(sc, TSEC_REG_TCTRL, reg);
1840
1841 reg = TSEC_READ(sc, TSEC_REG_RCTRL);
1842 reg &= ~(TSEC_RCTRL_IPCSEN | TSEC_RCTRL_TUCSEN | TSEC_RCTRL_PRSDEP);
1843 reg |= TSEC_RCTRL_PRSDEP_PARSE_L2 | TSEC_RCTRL_VLEX;
1844
1845 if (ifp->if_capenable & IFCAP_RXCSUM)
1846 reg |= TSEC_RCTRL_IPCSEN | TSEC_RCTRL_TUCSEN |
1847 TSEC_RCTRL_PRSDEP_PARSE_L234;
1848
1849 TSEC_WRITE(sc, TSEC_REG_RCTRL, reg);
1850}
1851
1852
1853static void
1854tsec_offload_process_frame(struct tsec_softc *sc, struct mbuf *m)
1855{
1856 struct tsec_rx_fcb rx_fcb;
1857 int csum_flags = 0;
1858 int protocol, flags;
1859
1860 TSEC_RECEIVE_LOCK_ASSERT(sc);
1861
1862 m_copydata(m, 0, sizeof(struct tsec_rx_fcb), (caddr_t)(&rx_fcb));
1863 flags = rx_fcb.flags;
1864 protocol = rx_fcb.protocol;
1865
1866 if (TSEC_RX_FCB_IP_CSUM_CHECKED(flags)) {
1867 csum_flags |= CSUM_IP_CHECKED;
1868
1869 if ((flags & TSEC_RX_FCB_IP_CSUM_ERROR) == 0)
1870 csum_flags |= CSUM_IP_VALID;
1871 }
1872
1873 if ((protocol == IPPROTO_TCP || protocol == IPPROTO_UDP) &&
1874 TSEC_RX_FCB_TCP_UDP_CSUM_CHECKED(flags) &&
1875 (flags & TSEC_RX_FCB_TCP_UDP_CSUM_ERROR) == 0) {
1876
1877 csum_flags |= CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
1878 m->m_pkthdr.csum_data = 0xFFFF;
1879 }
1880
1881 m->m_pkthdr.csum_flags = csum_flags;
1882
1883 if (flags & TSEC_RX_FCB_VLAN) {
1884 m->m_pkthdr.ether_vtag = rx_fcb.vlan;
1885 m->m_flags |= M_VLANTAG;
1886 }
1887
1888 m_adj(m, sizeof(struct tsec_rx_fcb));
1889}
1890
1891static void
1892tsec_setup_multicast(struct tsec_softc *sc)
1893{
1894 uint32_t hashtable[8] = { 0, 0, 0, 0, 0, 0, 0, 0 };
1895 struct ifnet *ifp = sc->tsec_ifp;
1896 struct ifmultiaddr *ifma;
1897 uint32_t h;
1898 int i;
1899
1900 TSEC_GLOBAL_LOCK_ASSERT(sc);
1901
1902 if (ifp->if_flags & IFF_ALLMULTI) {
1903 for (i = 0; i < 8; i++)
1904 TSEC_WRITE(sc, TSEC_REG_GADDR(i), 0xFFFFFFFF);
1905
1906 return;
1907 }
1908
1909 if_maddr_rlock(ifp);
1910 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1911
1912 if (ifma->ifma_addr->sa_family != AF_LINK)
1913 continue;
1914
1915 h = (ether_crc32_be(LLADDR((struct sockaddr_dl *)
1916 ifma->ifma_addr), ETHER_ADDR_LEN) >> 24) & 0xFF;
1917
1918 hashtable[(h >> 5)] |= 1 << (0x1F - (h & 0x1F));
1919 }
1920 if_maddr_runlock(ifp);
1921
1922 for (i = 0; i < 8; i++)
1923 TSEC_WRITE(sc, TSEC_REG_GADDR(i), hashtable[i]);
1924}
1925
1926static int
1927tsec_set_mtu(struct tsec_softc *sc, unsigned int mtu)
1928{
1929
1930 mtu += ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + ETHER_CRC_LEN;
1931
1932 TSEC_GLOBAL_LOCK_ASSERT(sc);
1933
1934 if (mtu >= TSEC_MIN_FRAME_SIZE && mtu <= TSEC_MAX_FRAME_SIZE) {
1935 TSEC_WRITE(sc, TSEC_REG_MAXFRM, mtu);
1936 return (mtu);
1937 }
1938
1939 return (0);
1940}