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1/*-
2 * Copyright (c) 1997, 1998
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

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26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
31 */
32
33#include <sys/cdefs.h>
34__FBSDID("$FreeBSD: head/sys/dev/tl/if_tl.c 214264 2010-10-24 12:51:02Z marius $");
34__FBSDID("$FreeBSD: head/sys/dev/tl/if_tl.c 226995 2011-11-01 16:13:59Z marius $");
35
36/*
37 * Texas Instruments ThunderLAN driver for FreeBSD 2.2.6 and 3.x.
38 * Supports many Compaq PCI NICs based on the ThunderLAN ethernet controller,
39 * the National Semiconductor DP83840A physical interface and the
40 * Microchip Technology 24Cxx series serial EEPROM.
41 *
42 * Written using the following four documents:

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198#include <vm/vm.h> /* for vtophys */
199#include <vm/pmap.h> /* for vtophys */
200#include <machine/bus.h>
201#include <machine/resource.h>
202#include <sys/bus.h>
203#include <sys/rman.h>
204
205#include <dev/mii/mii.h>
206#include <dev/mii/mii_bitbang.h>
207#include <dev/mii/miivar.h>
208
209#include <dev/pci/pcireg.h>
210#include <dev/pci/pcivar.h>
211
212/*
213 * Default to using PIO register access mode to pacify certain
214 * laptop docking stations with built-in ThunderLAN chips that

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224
225/* "device miibus" required. See GENERIC if you get errors here. */
226#include "miibus_if.h"
227
228/*
229 * Various supported device vendors/types and their names.
230 */
231
231static struct tl_type tl_devs[] = {
232static const struct tl_type const tl_devs[] = {
233 { TI_VENDORID, TI_DEVICEID_THUNDERLAN,
234 "Texas Instruments ThunderLAN" },
235 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10,
236 "Compaq Netelligent 10" },
237 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100,
238 "Compaq Netelligent 10/100" },
239 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100_PROLIANT,
240 "Compaq Netelligent 10/100 Proliant" },

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286static int tl_shutdown(device_t);
287static int tl_ifmedia_upd(struct ifnet *);
288static void tl_ifmedia_sts(struct ifnet *, struct ifmediareq *);
289
290static u_int8_t tl_eeprom_putbyte(struct tl_softc *, int);
291static u_int8_t tl_eeprom_getbyte(struct tl_softc *, int, u_int8_t *);
292static int tl_read_eeprom(struct tl_softc *, caddr_t, int, int);
293
293static void tl_mii_sync(struct tl_softc *);
294static void tl_mii_send(struct tl_softc *, u_int32_t, int);
295static int tl_mii_readreg(struct tl_softc *, struct tl_mii_frame *);
296static int tl_mii_writereg(struct tl_softc *, struct tl_mii_frame *);
294static int tl_miibus_readreg(device_t, int, int);
295static int tl_miibus_writereg(device_t, int, int, int);
296static void tl_miibus_statchg(device_t);
297
298static void tl_setmode(struct tl_softc *, int);
299static uint32_t tl_mchash(const uint8_t *);
300static void tl_setmulti(struct tl_softc *);
301static void tl_setfilt(struct tl_softc *, caddr_t, int);

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310static void tl_dio_write8(struct tl_softc *, int, int);
311static void tl_dio_write16(struct tl_softc *, int, int);
312static void tl_dio_write32(struct tl_softc *, int, int);
313static void tl_dio_setbit(struct tl_softc *, int, int);
314static void tl_dio_clrbit(struct tl_softc *, int, int);
315static void tl_dio_setbit16(struct tl_softc *, int, int);
316static void tl_dio_clrbit16(struct tl_softc *, int, int);
317
318/*
319 * MII bit-bang glue
320 */
321static uint32_t tl_mii_bitbang_read(device_t);
322static void tl_mii_bitbang_write(device_t, uint32_t);
323
324static const struct mii_bitbang_ops tl_mii_bitbang_ops = {
325 tl_mii_bitbang_read,
326 tl_mii_bitbang_write,
327 {
328 TL_SIO_MDATA, /* MII_BIT_MDO */
329 TL_SIO_MDATA, /* MII_BIT_MDI */
330 TL_SIO_MCLK, /* MII_BIT_MDC */
331 TL_SIO_MTXEN, /* MII_BIT_DIR_HOST_PHY */
332 0, /* MII_BIT_DIR_PHY_HOST */
333 }
334};
335
336#ifdef TL_USEIOSPACE
337#define TL_RES SYS_RES_IOPORT
338#define TL_RID TL_PCI_LOIO
339#else
340#define TL_RES SYS_RES_MEMORY
341#define TL_RID TL_PCI_LOMEM
342#endif
343

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370
371DRIVER_MODULE(tl, pci, tl_driver, tl_devclass, 0, 0);
372DRIVER_MODULE(miibus, tl, miibus_driver, miibus_devclass, 0, 0);
373
374static u_int8_t tl_dio_read8(sc, reg)
375 struct tl_softc *sc;
376 int reg;
377{
378
379 CSR_BARRIER(sc, TL_DIO_ADDR, 2,
380 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
381 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
382 CSR_BARRIER(sc, TL_DIO_ADDR, 2,
383 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
384 return(CSR_READ_1(sc, TL_DIO_DATA + (reg & 3)));
385}
386
387static u_int16_t tl_dio_read16(sc, reg)
388 struct tl_softc *sc;
389 int reg;
390{
391
392 CSR_BARRIER(sc, TL_DIO_ADDR, 2,
393 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
394 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
395 CSR_BARRIER(sc, TL_DIO_ADDR, 2,
396 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
397 return(CSR_READ_2(sc, TL_DIO_DATA + (reg & 3)));
398}
399
400static u_int32_t tl_dio_read32(sc, reg)
401 struct tl_softc *sc;
402 int reg;
403{
404
405 CSR_BARRIER(sc, TL_DIO_ADDR, 2,
406 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
407 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
408 CSR_BARRIER(sc, TL_DIO_ADDR, 2,
409 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
410 return(CSR_READ_4(sc, TL_DIO_DATA + (reg & 3)));
411}
412
413static void tl_dio_write8(sc, reg, val)
414 struct tl_softc *sc;
415 int reg;
416 int val;
417{
418
419 CSR_BARRIER(sc, TL_DIO_ADDR, 2,
420 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
421 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
422 CSR_BARRIER(sc, TL_DIO_ADDR, 2,
423 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
424 CSR_WRITE_1(sc, TL_DIO_DATA + (reg & 3), val);
390 return;
425}
426
427static void tl_dio_write16(sc, reg, val)
428 struct tl_softc *sc;
429 int reg;
430 int val;
431{
432
433 CSR_BARRIER(sc, TL_DIO_ADDR, 2,
434 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
435 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
436 CSR_BARRIER(sc, TL_DIO_ADDR, 2,
437 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
438 CSR_WRITE_2(sc, TL_DIO_DATA + (reg & 3), val);
400 return;
439}
440
441static void tl_dio_write32(sc, reg, val)
442 struct tl_softc *sc;
443 int reg;
444 int val;
445{
446
447 CSR_BARRIER(sc, TL_DIO_ADDR, 2,
448 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
449 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
450 CSR_BARRIER(sc, TL_DIO_ADDR, 2,
451 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
452 CSR_WRITE_4(sc, TL_DIO_DATA + (reg & 3), val);
410 return;
453}
454
455static void
456tl_dio_setbit(sc, reg, bit)
457 struct tl_softc *sc;
458 int reg;
459 int bit;
460{
461 u_int8_t f;
462
463 CSR_BARRIER(sc, TL_DIO_ADDR, 2,
464 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
465 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
466 CSR_BARRIER(sc, TL_DIO_ADDR, 2,
467 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
468 f = CSR_READ_1(sc, TL_DIO_DATA + (reg & 3));
469 f |= bit;
470 CSR_BARRIER(sc, TL_DIO_DATA + (reg & 3), 1,
471 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
472 CSR_WRITE_1(sc, TL_DIO_DATA + (reg & 3), f);
425
426 return;
473}
474
475static void
476tl_dio_clrbit(sc, reg, bit)
477 struct tl_softc *sc;
478 int reg;
479 int bit;
480{
481 u_int8_t f;
482
483 CSR_BARRIER(sc, TL_DIO_ADDR, 2,
484 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
485 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
486 CSR_BARRIER(sc, TL_DIO_ADDR, 2,
487 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
488 f = CSR_READ_1(sc, TL_DIO_DATA + (reg & 3));
489 f &= ~bit;
490 CSR_BARRIER(sc, TL_DIO_DATA + (reg & 3), 1,
491 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
492 CSR_WRITE_1(sc, TL_DIO_DATA + (reg & 3), f);
441
442 return;
493}
494
495static void tl_dio_setbit16(sc, reg, bit)
496 struct tl_softc *sc;
497 int reg;
498 int bit;
499{
500 u_int16_t f;
501
502 CSR_BARRIER(sc, TL_DIO_ADDR, 2,
503 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
504 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
505 CSR_BARRIER(sc, TL_DIO_ADDR, 2,
506 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
507 f = CSR_READ_2(sc, TL_DIO_DATA + (reg & 3));
508 f |= bit;
509 CSR_BARRIER(sc, TL_DIO_DATA + (reg & 3), 2,
510 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
511 CSR_WRITE_2(sc, TL_DIO_DATA + (reg & 3), f);
456
457 return;
512}
513
514static void tl_dio_clrbit16(sc, reg, bit)
515 struct tl_softc *sc;
516 int reg;
517 int bit;
518{
519 u_int16_t f;
520
521 CSR_BARRIER(sc, TL_DIO_ADDR, 2,
522 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
523 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
524 CSR_BARRIER(sc, TL_DIO_ADDR, 2,
525 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
526 f = CSR_READ_2(sc, TL_DIO_DATA + (reg & 3));
527 f &= ~bit;
528 CSR_BARRIER(sc, TL_DIO_DATA + (reg & 3), 2,
529 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
530 CSR_WRITE_2(sc, TL_DIO_DATA + (reg & 3), f);
471
472 return;
531}
532
533/*
534 * Send an instruction or address to the EEPROM, check for ACK.
535 */
536static u_int8_t tl_eeprom_putbyte(sc, byte)
537 struct tl_softc *sc;
538 int byte;

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661 if (err)
662 break;
663 *(dest + i) = byte;
664 }
665
666 return(err ? 1 : 0);
667}
668
611static void
612tl_mii_sync(sc)
613 struct tl_softc *sc;
669#define TL_SIO_MII (TL_SIO_MCLK | TL_SIO_MDATA | TL_SIO_MTXEN)
670
671/*
672 * Read the MII serial port for the MII bit-bang module.
673 */
674static uint32_t
675tl_mii_bitbang_read(device_t dev)
676{
615 register int i;
677 struct tl_softc *sc;
678 uint32_t val;
679
617 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MTXEN);
680 sc = device_get_softc(dev);
681
619 for (i = 0; i < 32; i++) {
620 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK);
621 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK);
622 }
682 val = tl_dio_read8(sc, TL_NETSIO) & TL_SIO_MII;
683 CSR_BARRIER(sc, TL_NETSIO, 1,
684 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
685
624 return;
686 return (val);
687}
688
689/*
690 * Write the MII serial port for the MII bit-bang module.
691 */
692static void
628tl_mii_send(sc, bits, cnt)
629 struct tl_softc *sc;
630 u_int32_t bits;
631 int cnt;
693tl_mii_bitbang_write(device_t dev, uint32_t val)
694{
633 int i;
695 struct tl_softc *sc;
696
635 for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
636 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK);
637 if (bits & i) {
638 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MDATA);
639 } else {
640 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MDATA);
641 }
642 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK);
643 }
697 sc = device_get_softc(dev);
698
699 val = (tl_dio_read8(sc, TL_NETSIO) & ~TL_SIO_MII) | val;
700 CSR_BARRIER(sc, TL_NETSIO, 1,
701 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
702 tl_dio_write8(sc, TL_NETSIO, val);
703 CSR_BARRIER(sc, TL_NETSIO, 1,
704 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
705}
706
707static int
647tl_mii_readreg(sc, frame)
648 struct tl_softc *sc;
649 struct tl_mii_frame *frame;
650
708tl_miibus_readreg(dev, phy, reg)
709 device_t dev;
710 int phy, reg;
711{
652 int i, ack;
653 int minten = 0;
712 struct tl_softc *sc;
713 int minten, val;
714
655 tl_mii_sync(sc);
715 sc = device_get_softc(dev);
716
717 /*
658 * Set up frame for RX.
659 */
660 frame->mii_stdelim = TL_MII_STARTDELIM;
661 frame->mii_opcode = TL_MII_READOP;
662 frame->mii_turnaround = 0;
663 frame->mii_data = 0;
664
665 /*
718 * Turn off MII interrupt by forcing MINTEN low.
719 */
720 minten = tl_dio_read8(sc, TL_NETSIO) & TL_SIO_MINTEN;
721 if (minten) {
722 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MINTEN);
723 }
724
673 /*
674 * Turn on data xmit.
675 */
676 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MTXEN);
725 val = mii_bitbang_readreg(dev, &tl_mii_bitbang_ops, phy, reg);
726
678 /*
679 * Send command/address info.
680 */
681 tl_mii_send(sc, frame->mii_stdelim, 2);
682 tl_mii_send(sc, frame->mii_opcode, 2);
683 tl_mii_send(sc, frame->mii_phyaddr, 5);
684 tl_mii_send(sc, frame->mii_regaddr, 5);
685
686 /*
687 * Turn off xmit.
688 */
689 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MTXEN);
690
691 /* Idle bit */
692 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK);
693 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK);
694
695 /* Check for ack */
696 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK);
697 ack = tl_dio_read8(sc, TL_NETSIO) & TL_SIO_MDATA;
698
699 /* Complete the cycle */
700 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK);
701
702 /*
703 * Now try reading data bits. If the ack failed, we still
704 * need to clock through 16 cycles to keep the PHYs in sync.
705 */
706 if (ack) {
707 for(i = 0; i < 16; i++) {
708 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK);
709 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK);
710 }
711 goto fail;
712 }
713
714 for (i = 0x8000; i; i >>= 1) {
715 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK);
716 if (!ack) {
717 if (tl_dio_read8(sc, TL_NETSIO) & TL_SIO_MDATA)
718 frame->mii_data |= i;
719 }
720 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK);
721 }
722
723fail:
724
725 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK);
726 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK);
727
728 /* Reenable interrupts */
727 /* Reenable interrupts. */
728 if (minten) {
729 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MINTEN);
730 }
731
733 if (ack)
734 return(1);
735 return(0);
732 return (val);
733}
734
735static int
739tl_mii_writereg(sc, frame)
740 struct tl_softc *sc;
741 struct tl_mii_frame *frame;
742
736tl_miibus_writereg(dev, phy, reg, data)
737 device_t dev;
738 int phy, reg, data;
739{
740 struct tl_softc *sc;
741 int minten;
742
746 tl_mii_sync(sc);
743 sc = device_get_softc(dev);
744
745 /*
749 * Set up frame for TX.
750 */
751
752 frame->mii_stdelim = TL_MII_STARTDELIM;
753 frame->mii_opcode = TL_MII_WRITEOP;
754 frame->mii_turnaround = TL_MII_TURNAROUND;
755
756 /*
746 * Turn off MII interrupt by forcing MINTEN low.
747 */
748 minten = tl_dio_read8(sc, TL_NETSIO) & TL_SIO_MINTEN;
749 if (minten) {
750 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MINTEN);
751 }
752
764 /*
765 * Turn on data output.
766 */
767 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MTXEN);
753 mii_bitbang_writereg(dev, &tl_mii_bitbang_ops, phy, reg, data);
754
769 tl_mii_send(sc, frame->mii_stdelim, 2);
770 tl_mii_send(sc, frame->mii_opcode, 2);
771 tl_mii_send(sc, frame->mii_phyaddr, 5);
772 tl_mii_send(sc, frame->mii_regaddr, 5);
773 tl_mii_send(sc, frame->mii_turnaround, 2);
774 tl_mii_send(sc, frame->mii_data, 16);
775
776 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK);
777 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK);
778
779 /*
780 * Turn off xmit.
781 */
782 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MTXEN);
783
784 /* Reenable interrupts */
785 if (minten)
755 /* Reenable interrupts. */
756 if (minten) {
757 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MINTEN);
758 }
759
760 return(0);
761}
762
791static int
792tl_miibus_readreg(dev, phy, reg)
793 device_t dev;
794 int phy, reg;
795{
796 struct tl_softc *sc;
797 struct tl_mii_frame frame;
798
799 sc = device_get_softc(dev);
800 bzero((char *)&frame, sizeof(frame));
801
802 frame.mii_phyaddr = phy;
803 frame.mii_regaddr = reg;
804 tl_mii_readreg(sc, &frame);
805
806 return(frame.mii_data);
807}
808
809static int
810tl_miibus_writereg(dev, phy, reg, data)
811 device_t dev;
812 int phy, reg, data;
813{
814 struct tl_softc *sc;
815 struct tl_mii_frame frame;
816
817 sc = device_get_softc(dev);
818 bzero((char *)&frame, sizeof(frame));
819
820 frame.mii_phyaddr = phy;
821 frame.mii_regaddr = reg;
822 frame.mii_data = data;
823
824 tl_mii_writereg(sc, &frame);
825
826 return(0);
827}
828
763static void
764tl_miibus_statchg(dev)
765 device_t dev;
766{
767 struct tl_softc *sc;
768 struct mii_data *mii;
769
770 sc = device_get_softc(dev);
771 mii = device_get_softc(sc->tl_miibus);
772
773 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
774 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_DUPLEX);
775 } else {
776 tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_DUPLEX);
777 }
844
845 return;
778}
779
780/*
781 * Set modes for bitrate devices.
782 */
783static void
784tl_setmode(sc, media)
785 struct tl_softc *sc;

--- 6 unchanged lines hidden (view full) ---

792 if ((media & IFM_GMASK) == IFM_FDX) {
793 tl_dio_clrbit(sc, TL_ACOMMIT, TL_AC_MTXD3);
794 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_DUPLEX);
795 } else {
796 tl_dio_setbit(sc, TL_ACOMMIT, TL_AC_MTXD3);
797 tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_DUPLEX);
798 }
799 }
868
869 return;
800}
801
802/*
803 * Calculate the hash of a MAC address for programming the multicast hash
804 * table. This hash is simply the address split into 6-bit chunks
805 * XOR'd, e.g.
806 * byte: 000000|00 1111|1111 22|222222|333333|33 4444|4444 55|555555
807 * bit: 765432|10 7654|3210 76|543210|765432|10 7654|3210 76|543210

--- 26 unchanged lines hidden (view full) ---

834{
835 int i;
836 u_int16_t regaddr;
837
838 regaddr = TL_AREG0_B5 + (slot * ETHER_ADDR_LEN);
839
840 for (i = 0; i < ETHER_ADDR_LEN; i++)
841 tl_dio_write8(sc, regaddr + i, *(addr + i));
912
913 return;
842}
843
844/*
845 * XXX In FreeBSD 3.0, multicast addresses are managed using a doubly
846 * linked list. This is fine, except addresses are added from the head
847 * end of the list. We want to arrange for 224.0.0.1 (the "all hosts")
848 * group to always be in the perfect filter, but as more groups are added,
849 * the 224.0.0.1 entry (which is always added first) gets pushed down

--- 53 unchanged lines hidden (view full) ---

903 else
904 hashes[1] |= (1 << (h - 32));
905 }
906 if_maddr_runlock(ifp);
907 }
908
909 tl_dio_write32(sc, TL_HASH1, hashes[0]);
910 tl_dio_write32(sc, TL_HASH2, hashes[1]);
983
984 return;
911}
912
913/*
914 * This routine is recommended by the ThunderLAN manual to insure that
915 * the internal PHY is powered up correctly. It also recommends a one
916 * second pause at the end to 'wait for the clocks to start' but in my
917 * experience this isn't necessary.
918 */
919static void
920tl_hardreset(dev)
921 device_t dev;
922{
923 struct tl_softc *sc;
924 int i;
925 u_int16_t flags;
926
927 sc = device_get_softc(dev);
928
1003 tl_mii_sync(sc);
929 mii_bitbang_sync(dev, &tl_mii_bitbang_ops);
930
931 flags = BMCR_LOOP|BMCR_ISO|BMCR_PDOWN;
932
933 for (i = 0; i < MII_NPHY; i++)
934 tl_miibus_writereg(dev, i, MII_BMCR, flags);
935
936 tl_miibus_writereg(dev, 31, MII_BMCR, BMCR_ISO);
937 DELAY(50000);
938 tl_miibus_writereg(dev, 31, MII_BMCR, BMCR_LOOP|BMCR_ISO);
1013 tl_mii_sync(sc);
939 mii_bitbang_sync(dev, &tl_mii_bitbang_ops);
940 while(tl_miibus_readreg(dev, 31, MII_BMCR) & BMCR_RESET);
941
942 DELAY(50000);
1017 return;
943}
944
945static void
946tl_softreset(sc, internal)
947 struct tl_softc *sc;
948 int internal;
949{
950 u_int32_t cmd, dummy, i;

--- 41 unchanged lines hidden (view full) ---

992 /* Unreset the MII */
993 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_NMRST);
994
995 /* Take the adapter out of reset */
996 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_NRESET|TL_CMD_NWRAP);
997
998 /* Wait for things to settle down a little. */
999 DELAY(500);
1075
1076 return;
1000}
1001
1002/*
1003 * Probe for a ThunderLAN chip. Check the PCI vendor and device IDs
1004 * against our list and return its name if we find a match.
1005 */
1006static int
1007tl_probe(dev)
1008 device_t dev;
1009{
1087 struct tl_type *t;
1010 const struct tl_type *t;
1011
1012 t = tl_devs;
1013
1014 while(t->tl_name != NULL) {
1015 if ((pci_get_vendor(dev) == t->tl_vid) &&
1016 (pci_get_device(dev) == t->tl_did)) {
1017 device_set_desc(dev, t->tl_name);
1018 return (BUS_PROBE_DEFAULT);

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1023 return(ENXIO);
1024}
1025
1026static int
1027tl_attach(dev)
1028 device_t dev;
1029{
1030 u_int16_t did, vid;
1108 struct tl_type *t;
1031 const struct tl_type *t;
1032 struct ifnet *ifp;
1033 struct tl_softc *sc;
1034 int error, flags, i, rid, unit;
1035 u_char eaddr[6];
1036
1037 vid = pci_get_vendor(dev);
1038 did = pci_get_device(dev);
1039 sc = device_get_softc(dev);

--- 293 unchanged lines hidden (view full) ---

1333
1334/*
1335 * Initialize the RX lists and allocate mbufs for them.
1336 */
1337static int
1338tl_list_rx_init(sc)
1339 struct tl_softc *sc;
1340{
1418 struct tl_chain_data *cd;
1419 struct tl_list_data *ld;
1420 int i;
1341 struct tl_chain_data *cd;
1342 struct tl_list_data *ld;
1343 int i;
1344
1345 cd = &sc->tl_cdata;
1346 ld = sc->tl_ldata;
1347
1348 for (i = 0; i < TL_RX_LIST_CNT; i++) {
1349 cd->tl_rx_chain[i].tl_ptr =
1350 (struct tl_list_onefrag *)&ld->tl_rx_list[i];
1351 if (tl_newbuf(sc, &cd->tl_rx_chain[i]) == ENOBUFS)

--- 349 unchanged lines hidden (view full) ---

1701 if (r) {
1702 CMD_PUT(sc, TL_CMD_ACK | r | type);
1703 }
1704
1705 if (ifp->if_snd.ifq_head != NULL)
1706 tl_start_locked(ifp);
1707
1708 TL_UNLOCK(sc);
1786
1787 return;
1709}
1710
1711static void
1712tl_stats_update(xsc)
1713 void *xsc;
1714{
1715 struct tl_softc *sc;
1716 struct ifnet *ifp;

--- 42 unchanged lines hidden (view full) ---

1759 tl_watchdog(sc);
1760
1761 callout_reset(&sc->tl_stat_callout, hz, tl_stats_update, sc);
1762
1763 if (!sc->tl_bitrate) {
1764 mii = device_get_softc(sc->tl_miibus);
1765 mii_tick(mii);
1766 }
1846
1847 return;
1767}
1768
1769/*
1770 * Encapsulate an mbuf chain in a list by coupling the mbuf data
1771 * pointers to the fragment pointers.
1772 */
1773static int
1774tl_encap(sc, c, m_head)

--- 185 unchanged lines hidden (view full) ---

1960 sc->tl_cdata.tl_tx_tail->tl_next = start_tx;
1961 sc->tl_cdata.tl_tx_tail = cur_tx;
1962 }
1963
1964 /*
1965 * Set a timeout in case the chip goes out to lunch.
1966 */
1967 sc->tl_timer = 5;
2049
2050 return;
1968}
1969
1970static void
1971tl_init(xsc)
1972 void *xsc;
1973{
1974 struct tl_softc *sc = xsc;
1975

--- 79 unchanged lines hidden (view full) ---

2055 /* Send the RX go command */
2056 CMD_SET(sc, TL_CMD_GO|TL_CMD_NES|TL_CMD_RT);
2057
2058 ifp->if_drv_flags |= IFF_DRV_RUNNING;
2059 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2060
2061 /* Start the stats update counter */
2062 callout_reset(&sc->tl_stat_callout, hz, tl_stats_update, sc);
2146
2147 return;
2063}
2064
2065/*
2066 * Set media options.
2067 */
2068static int
2069tl_ifmedia_upd(ifp)
2070 struct ifnet *ifp;

--- 43 unchanged lines hidden (view full) ---

2114 return;
2115 } else {
2116 mii = device_get_softc(sc->tl_miibus);
2117 mii_pollstat(mii);
2118 ifmr->ifm_active = mii->mii_media_active;
2119 ifmr->ifm_status = mii->mii_media_status;
2120 }
2121 TL_UNLOCK(sc);
2207
2208 return;
2122}
2123
2124static int
2125tl_ioctl(ifp, command, data)
2126 struct ifnet *ifp;
2127 u_long command;
2128 caddr_t data;
2129{

--- 62 unchanged lines hidden (view full) ---

2192 ifp = sc->tl_ifp;
2193
2194 if_printf(ifp, "device timeout\n");
2195
2196 ifp->if_oerrors++;
2197
2198 tl_softreset(sc, 1);
2199 tl_init_locked(sc);
2287
2288 return;
2200}
2201
2202/*
2203 * Stop the adapter and free any mbufs allocated to the
2204 * RX and TX lists.
2205 */
2206static void
2207tl_stop(sc)

--- 49 unchanged lines hidden (view full) ---

2257 m_freem(sc->tl_cdata.tl_tx_chain[i].tl_mbuf);
2258 sc->tl_cdata.tl_tx_chain[i].tl_mbuf = NULL;
2259 }
2260 }
2261 bzero((char *)&sc->tl_ldata->tl_tx_list,
2262 sizeof(sc->tl_ldata->tl_tx_list));
2263
2264 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
2354
2355 return;
2265}
2266
2267/*
2268 * Stop all chip I/O so that the kernel's probe routines don't
2269 * get confused by errant DMAs when rebooting.
2270 */
2271static int
2272tl_shutdown(dev)

--- 12 unchanged lines hidden ---