Deleted Added
full compact
34c34
< __FBSDID("$FreeBSD: head/sys/dev/tl/if_tl.c 214264 2010-10-24 12:51:02Z marius $");
---
> __FBSDID("$FreeBSD: head/sys/dev/tl/if_tl.c 226995 2011-11-01 16:13:59Z marius $");
205a206
> #include <dev/mii/mii_bitbang.h>
231c232
< static struct tl_type tl_devs[] = {
---
> static const struct tl_type const tl_devs[] = {
293,296d293
< static void tl_mii_sync(struct tl_softc *);
< static void tl_mii_send(struct tl_softc *, u_int32_t, int);
< static int tl_mii_readreg(struct tl_softc *, struct tl_mii_frame *);
< static int tl_mii_writereg(struct tl_softc *, struct tl_mii_frame *);
320a318,335
> /*
> * MII bit-bang glue
> */
> static uint32_t tl_mii_bitbang_read(device_t);
> static void tl_mii_bitbang_write(device_t, uint32_t);
>
> static const struct mii_bitbang_ops tl_mii_bitbang_ops = {
> tl_mii_bitbang_read,
> tl_mii_bitbang_write,
> {
> TL_SIO_MDATA, /* MII_BIT_MDO */
> TL_SIO_MDATA, /* MII_BIT_MDI */
> TL_SIO_MCLK, /* MII_BIT_MDC */
> TL_SIO_MTXEN, /* MII_BIT_DIR_HOST_PHY */
> 0, /* MII_BIT_DIR_PHY_HOST */
> }
> };
>
362a378,380
>
> CSR_BARRIER(sc, TL_DIO_ADDR, 2,
> BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
363a382,383
> CSR_BARRIER(sc, TL_DIO_ADDR, 2,
> BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
370a391,393
>
> CSR_BARRIER(sc, TL_DIO_ADDR, 2,
> BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
371a395,396
> CSR_BARRIER(sc, TL_DIO_ADDR, 2,
> BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
378a404,406
>
> CSR_BARRIER(sc, TL_DIO_ADDR, 2,
> BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
379a408,409
> CSR_BARRIER(sc, TL_DIO_ADDR, 2,
> BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
387a418,420
>
> CSR_BARRIER(sc, TL_DIO_ADDR, 2,
> BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
388a422,423
> CSR_BARRIER(sc, TL_DIO_ADDR, 2,
> BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
390d424
< return;
397a432,434
>
> CSR_BARRIER(sc, TL_DIO_ADDR, 2,
> BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
398a436,437
> CSR_BARRIER(sc, TL_DIO_ADDR, 2,
> BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
400d438
< return;
407a446,448
>
> CSR_BARRIER(sc, TL_DIO_ADDR, 2,
> BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
408a450,451
> CSR_BARRIER(sc, TL_DIO_ADDR, 2,
> BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
410d452
< return;
420a463,464
> CSR_BARRIER(sc, TL_DIO_ADDR, 2,
> BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
421a466,467
> CSR_BARRIER(sc, TL_DIO_ADDR, 2,
> BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
423a470,471
> CSR_BARRIER(sc, TL_DIO_DATA + (reg & 3), 1,
> BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
425,426d472
<
< return;
436a483,484
> CSR_BARRIER(sc, TL_DIO_ADDR, 2,
> BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
437a486,487
> CSR_BARRIER(sc, TL_DIO_ADDR, 2,
> BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
439a490,491
> CSR_BARRIER(sc, TL_DIO_DATA + (reg & 3), 1,
> BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
441,442d492
<
< return;
451a502,503
> CSR_BARRIER(sc, TL_DIO_ADDR, 2,
> BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
452a505,506
> CSR_BARRIER(sc, TL_DIO_ADDR, 2,
> BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
454a509,510
> CSR_BARRIER(sc, TL_DIO_DATA + (reg & 3), 2,
> BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
456,457d511
<
< return;
466a521,522
> CSR_BARRIER(sc, TL_DIO_ADDR, 2,
> BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
467a524,525
> CSR_BARRIER(sc, TL_DIO_ADDR, 2,
> BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
469a528,529
> CSR_BARRIER(sc, TL_DIO_DATA + (reg & 3), 2,
> BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
471,472d530
<
< return;
611,613c669,675
< static void
< tl_mii_sync(sc)
< struct tl_softc *sc;
---
> #define TL_SIO_MII (TL_SIO_MCLK | TL_SIO_MDATA | TL_SIO_MTXEN)
>
> /*
> * Read the MII serial port for the MII bit-bang module.
> */
> static uint32_t
> tl_mii_bitbang_read(device_t dev)
615c677,678
< register int i;
---
> struct tl_softc *sc;
> uint32_t val;
617c680
< tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MTXEN);
---
> sc = device_get_softc(dev);
619,622c682,684
< for (i = 0; i < 32; i++) {
< tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK);
< tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK);
< }
---
> val = tl_dio_read8(sc, TL_NETSIO) & TL_SIO_MII;
> CSR_BARRIER(sc, TL_NETSIO, 1,
> BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
624c686
< return;
---
> return (val);
626a689,691
> /*
> * Write the MII serial port for the MII bit-bang module.
> */
628,631c693
< tl_mii_send(sc, bits, cnt)
< struct tl_softc *sc;
< u_int32_t bits;
< int cnt;
---
> tl_mii_bitbang_write(device_t dev, uint32_t val)
633c695
< int i;
---
> struct tl_softc *sc;
635,643c697,704
< for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
< tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK);
< if (bits & i) {
< tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MDATA);
< } else {
< tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MDATA);
< }
< tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK);
< }
---
> sc = device_get_softc(dev);
>
> val = (tl_dio_read8(sc, TL_NETSIO) & ~TL_SIO_MII) | val;
> CSR_BARRIER(sc, TL_NETSIO, 1,
> BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
> tl_dio_write8(sc, TL_NETSIO, val);
> CSR_BARRIER(sc, TL_NETSIO, 1,
> BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
647,650c708,710
< tl_mii_readreg(sc, frame)
< struct tl_softc *sc;
< struct tl_mii_frame *frame;
<
---
> tl_miibus_readreg(dev, phy, reg)
> device_t dev;
> int phy, reg;
652,653c712,713
< int i, ack;
< int minten = 0;
---
> struct tl_softc *sc;
> int minten, val;
655c715
< tl_mii_sync(sc);
---
> sc = device_get_softc(dev);
658,665d717
< * Set up frame for RX.
< */
< frame->mii_stdelim = TL_MII_STARTDELIM;
< frame->mii_opcode = TL_MII_READOP;
< frame->mii_turnaround = 0;
< frame->mii_data = 0;
<
< /*
673,676c725
< /*
< * Turn on data xmit.
< */
< tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MTXEN);
---
> val = mii_bitbang_readreg(dev, &tl_mii_bitbang_ops, phy, reg);
678,728c727
< /*
< * Send command/address info.
< */
< tl_mii_send(sc, frame->mii_stdelim, 2);
< tl_mii_send(sc, frame->mii_opcode, 2);
< tl_mii_send(sc, frame->mii_phyaddr, 5);
< tl_mii_send(sc, frame->mii_regaddr, 5);
<
< /*
< * Turn off xmit.
< */
< tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MTXEN);
<
< /* Idle bit */
< tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK);
< tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK);
<
< /* Check for ack */
< tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK);
< ack = tl_dio_read8(sc, TL_NETSIO) & TL_SIO_MDATA;
<
< /* Complete the cycle */
< tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK);
<
< /*
< * Now try reading data bits. If the ack failed, we still
< * need to clock through 16 cycles to keep the PHYs in sync.
< */
< if (ack) {
< for(i = 0; i < 16; i++) {
< tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK);
< tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK);
< }
< goto fail;
< }
<
< for (i = 0x8000; i; i >>= 1) {
< tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK);
< if (!ack) {
< if (tl_dio_read8(sc, TL_NETSIO) & TL_SIO_MDATA)
< frame->mii_data |= i;
< }
< tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK);
< }
<
< fail:
<
< tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK);
< tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK);
<
< /* Reenable interrupts */
---
> /* Reenable interrupts. */
733,735c732
< if (ack)
< return(1);
< return(0);
---
> return (val);
739,742c736,738
< tl_mii_writereg(sc, frame)
< struct tl_softc *sc;
< struct tl_mii_frame *frame;
<
---
> tl_miibus_writereg(dev, phy, reg, data)
> device_t dev;
> int phy, reg, data;
743a740
> struct tl_softc *sc;
746c743
< tl_mii_sync(sc);
---
> sc = device_get_softc(dev);
749,756d745
< * Set up frame for TX.
< */
<
< frame->mii_stdelim = TL_MII_STARTDELIM;
< frame->mii_opcode = TL_MII_WRITEOP;
< frame->mii_turnaround = TL_MII_TURNAROUND;
<
< /*
764,767c753
< /*
< * Turn on data output.
< */
< tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MTXEN);
---
> mii_bitbang_writereg(dev, &tl_mii_bitbang_ops, phy, reg, data);
769,785c755,756
< tl_mii_send(sc, frame->mii_stdelim, 2);
< tl_mii_send(sc, frame->mii_opcode, 2);
< tl_mii_send(sc, frame->mii_phyaddr, 5);
< tl_mii_send(sc, frame->mii_regaddr, 5);
< tl_mii_send(sc, frame->mii_turnaround, 2);
< tl_mii_send(sc, frame->mii_data, 16);
<
< tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK);
< tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK);
<
< /*
< * Turn off xmit.
< */
< tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MTXEN);
<
< /* Reenable interrupts */
< if (minten)
---
> /* Reenable interrupts. */
> if (minten) {
786a758
> }
791,828d762
< static int
< tl_miibus_readreg(dev, phy, reg)
< device_t dev;
< int phy, reg;
< {
< struct tl_softc *sc;
< struct tl_mii_frame frame;
<
< sc = device_get_softc(dev);
< bzero((char *)&frame, sizeof(frame));
<
< frame.mii_phyaddr = phy;
< frame.mii_regaddr = reg;
< tl_mii_readreg(sc, &frame);
<
< return(frame.mii_data);
< }
<
< static int
< tl_miibus_writereg(dev, phy, reg, data)
< device_t dev;
< int phy, reg, data;
< {
< struct tl_softc *sc;
< struct tl_mii_frame frame;
<
< sc = device_get_softc(dev);
< bzero((char *)&frame, sizeof(frame));
<
< frame.mii_phyaddr = phy;
< frame.mii_regaddr = reg;
< frame.mii_data = data;
<
< tl_mii_writereg(sc, &frame);
<
< return(0);
< }
<
844,845d777
<
< return;
868,869d799
<
< return;
912,913d841
<
< return;
983,984d910
<
< return;
1003c929
< tl_mii_sync(sc);
---
> mii_bitbang_sync(dev, &tl_mii_bitbang_ops);
1013c939
< tl_mii_sync(sc);
---
> mii_bitbang_sync(dev, &tl_mii_bitbang_ops);
1017d942
< return;
1075,1076d999
<
< return;
1087c1010
< struct tl_type *t;
---
> const struct tl_type *t;
1108c1031
< struct tl_type *t;
---
> const struct tl_type *t;
1418,1420c1341,1343
< struct tl_chain_data *cd;
< struct tl_list_data *ld;
< int i;
---
> struct tl_chain_data *cd;
> struct tl_list_data *ld;
> int i;
1786,1787d1708
<
< return;
1846,1847d1766
<
< return;
2049,2050d1967
<
< return;
2146,2147d2062
<
< return;
2207,2208d2121
<
< return;
2287,2288d2199
<
< return;
2354,2355d2264
<
< return;