1/*-
2 * Copyright (c) 1997, 1998, 1999
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
31 *
| 1/*-
2 * Copyright (c) 1997, 1998, 1999
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
31 *
|
32 * $FreeBSD: head/sys/dev/ste/if_stereg.h 200950 2009-12-24 17:22:15Z yongari $
| 32 * $FreeBSD: head/sys/dev/ste/if_stereg.h 226995 2011-11-01 16:13:59Z marius $
|
33 */
34
35/*
36 * Sundance PCI device/vendor ID for the
37 * ST201 chip.
38 */
39#define ST_VENDORID 0x13F0
40#define ST_DEVICEID_ST201_1 0x0200
41#define ST_DEVICEID_ST201_2 0x0201
42
43/*
44 * D-Link PCI device/vendor ID for the DL10050[AB] chip
45 */
46#define DL_VENDORID 0x1186
47#define DL_DEVICEID_DL10050 0x1002
48
49/*
50 * Register definitions for the Sundance Technologies ST201 PCI
51 * fast ethernet controller. The register space is 128 bytes long and
52 * can be accessed using either PCI I/O space or PCI memory mapping.
53 * There are 32-bit, 16-bit and 8-bit registers.
54 */
55
56#define STE_DMACTL 0x00
57#define STE_TX_DMALIST_PTR 0x04
58#define STE_TX_DMABURST_THRESH 0x08
59#define STE_TX_DMAURG_THRESH 0x09
60#define STE_TX_DMAPOLL_PERIOD 0x0A
61#define STE_RX_DMASTATUS 0x0C
62#define STE_RX_DMALIST_PTR 0x10
63#define STE_RX_DMABURST_THRESH 0x14
64#define STE_RX_DMAURG_THRESH 0x15
65#define STE_RX_DMAPOLL_PERIOD 0x16
66#define STE_COUNTDOWN 0x18
67#define STE_DEBUGCTL 0x1A
68#define STE_ASICCTL 0x30
69#define STE_EEPROM_DATA 0x34
70#define STE_EEPROM_CTL 0x36
71#define STE_FIFOCTL 0x3A
72#define STE_TX_STARTTHRESH 0x3C
73#define STE_RX_EARLYTHRESH 0x3E
74#define STE_EXT_ROMADDR 0x40
75#define STE_EXT_ROMDATA 0x44
76#define STE_WAKE_EVENT 0x45
77#define STE_TX_STATUS 0x46
78#define STE_TX_FRAMEID 0x47
79#define STE_ISR_ACK 0x4A
80#define STE_IMR 0x4C
81#define STE_ISR 0x4E
82#define STE_MACCTL0 0x50
83#define STE_MACCTL1 0x52
84#define STE_PAR0 0x54
85#define STE_PAR1 0x56
86#define STE_PAR2 0x58
87#define STE_MAX_FRAMELEN 0x5A
88#define STE_RX_MODE 0x5C
89#define STE_TX_RECLAIM_THRESH 0x5D
90#define STE_PHYCTL 0x5E
91#define STE_MAR0 0x60
92#define STE_MAR1 0x62
93#define STE_MAR2 0x64
94#define STE_MAR3 0x66
95
96#define STE_STAT_RX_OCTETS_LO 0x68
97#define STE_STAT_RX_OCTETS_HI 0x6A
98#define STE_STAT_TX_OCTETS_LO 0x6C
99#define STE_STAT_TX_OCTETS_HI 0x6E
100#define STE_STAT_TX_FRAMES 0x70
101#define STE_STAT_RX_FRAMES 0x72
102#define STE_STAT_CARRIER_ERR 0x74
103#define STE_STAT_LATE_COLLS 0x75
104#define STE_STAT_MULTI_COLLS 0x76
105#define STE_STAT_SINGLE_COLLS 0x77
106#define STE_STAT_TX_DEFER 0x78
107#define STE_STAT_RX_LOST 0x79
108#define STE_STAT_TX_EXDEFER 0x7A
109#define STE_STAT_TX_ABORT 0x7B
110#define STE_STAT_TX_BCAST 0x7C
111#define STE_STAT_RX_BCAST 0x7D
112#define STE_STAT_TX_MCAST 0x7E
113#define STE_STAT_RX_MCAST 0x7F
114
115#define STE_DMACTL_RXDMA_STOPPED 0x00000001
116#define STE_DMACTL_TXDMA_CMPREQ 0x00000002
117#define STE_DMACTL_TXDMA_STOPPED 0x00000004
118#define STE_DMACTL_RXDMA_COMPLETE 0x00000008
119#define STE_DMACTL_TXDMA_COMPLETE 0x00000010
120#define STE_DMACTL_RXDMA_STALL 0x00000100
121#define STE_DMACTL_RXDMA_UNSTALL 0x00000200
122#define STE_DMACTL_TXDMA_STALL 0x00000400
123#define STE_DMACTL_TXDMA_UNSTALL 0x00000800
124#define STE_DMACTL_TXDMA_INPROG 0x00004000
125#define STE_DMACTL_DMA_HALTINPROG 0x00008000
126#define STE_DMACTL_RXEARLY_ENABLE 0x00020000
127#define STE_DMACTL_COUNTDOWN_SPEED 0x00040000
128#define STE_DMACTL_COUNTDOWN_MODE 0x00080000
129#define STE_DMACTL_MWI_DISABLE 0x00100000
130#define STE_DMACTL_RX_DISCARD_OFLOWS 0x00400000
131#define STE_DMACTL_COUNTDOWN_ENABLE 0x00800000
132#define STE_DMACTL_TARGET_ABORT 0x40000000
133#define STE_DMACTL_MASTER_ABORT 0x80000000
134
135/*
136 * TX DMA burst thresh is the number of 32-byte blocks that
137 * must be loaded into the TX Fifo before a TXDMA burst request
138 * will be issued.
139 */
140#define STE_TXDMABURST_THRESH 0x1F
141
142/*
143 * The number of 32-byte blocks in the TX FIFO falls below the
144 * TX DMA urgent threshold, a TX DMA urgent request will be
145 * generated.
146 */
147#define STE_TXDMAURG_THRESH 0x3F
148
149/*
150 * Number of 320ns intervals between polls of the TXDMA next
151 * descriptor pointer (if we're using polling mode).
152 */
153#define STE_TXDMA_POLL_PERIOD 0x7F
154
155#define STE_RX_DMASTATUS_FRAMELEN 0x00001FFF
156#define STE_RX_DMASTATUS_RXERR 0x00004000
157#define STE_RX_DMASTATUS_DMADONE 0x00008000
158#define STE_RX_DMASTATUS_FIFO_OFLOW 0x00010000
159#define STE_RX_DMASTATUS_RUNT 0x00020000
160#define STE_RX_DMASTATUS_ALIGNERR 0x00040000
161#define STE_RX_DMASTATUS_CRCERR 0x00080000
162#define STE_RX_DMASTATUS_GIANT 0x00100000
163#define STE_RX_DMASTATUS_DRIBBLE 0x00800000
164#define STE_RX_DMASTATUS_DMA_OFLOW 0x01000000
165
166/*
167 * RX DMA burst thresh is the number of 32-byte blocks that
168 * must be present in the RX FIFO before a RXDMA bus master
169 * request will be issued.
170 */
171#define STE_RXDMABURST_THRESH 0xFF
172
173/*
174 * The number of 32-byte blocks in the RX FIFO falls below the
175 * RX DMA urgent threshold, a RX DMA urgent request will be
176 * generated.
177 */
178#define STE_RXDMAURG_THRESH 0x1F
179
180/*
181 * Number of 320ns intervals between polls of the RXDMA complete
182 * bit in the status field on the current RX descriptor (if we're
183 * using polling mode).
184 */
185#define STE_RXDMA_POLL_PERIOD 0x7F
186
187#define STE_DEBUGCTL_GPIO0_CTL 0x0001
188#define STE_DEBUGCTL_GPIO1_CTL 0x0002
189#define STE_DEBUGCTL_GPIO0_DATA 0x0004
190#define STE_DEBUGCTL_GPIO1_DATA 0x0008
191
192#define STE_ASICCTL_ROMSIZE 0x00000002
193#define STE_ASICCTL_TX_LARGEPKTS 0x00000004
194#define STE_ASICCTL_RX_LARGEPKTS 0x00000008
195#define STE_ASICCTL_EXTROM_DISABLE 0x00000010
196#define STE_ASICCTL_PHYSPEED_10 0x00000020
197#define STE_ASICCTL_PHYSPEED_100 0x00000040
198#define STE_ASICCTL_PHYMEDIA 0x00000080
199#define STE_ASICCTL_FORCEDCONFIG 0x00000700
200#define STE_ASICCTL_D3RESET_DISABLE 0x00000800
201#define STE_ASICCTL_SPEEDUPMODE 0x00002000
202#define STE_ASICCTL_LEDMODE 0x00004000
203#define STE_ASICCTL_RSTOUT_POLARITY 0x00008000
204#define STE_ASICCTL_GLOBAL_RESET 0x00010000
205#define STE_ASICCTL_RX_RESET 0x00020000
206#define STE_ASICCTL_TX_RESET 0x00040000
207#define STE_ASICCTL_DMA_RESET 0x00080000
208#define STE_ASICCTL_FIFO_RESET 0x00100000
209#define STE_ASICCTL_NETWORK_RESET 0x00200000
210#define STE_ASICCTL_HOST_RESET 0x00400000
211#define STE_ASICCTL_AUTOINIT_RESET 0x00800000
212#define STE_ASICCTL_EXTRESET_RESET 0x01000000
213#define STE_ASICCTL_SOFTINTR 0x02000000
214#define STE_ASICCTL_RESET_BUSY 0x04000000
215
216#define STE_EECTL_ADDR 0x00FF
217#define STE_EECTL_OPCODE 0x0300
218#define STE_EECTL_BUSY 0x1000
219
220#define STE_EEOPCODE_WRITE 0x0100
221#define STE_EEOPCODE_READ 0x0200
222#define STE_EEOPCODE_ERASE 0x0300
223
224#define STE_FIFOCTL_RAMTESTMODE 0x0001
225#define STE_FIFOCTL_OVERRUNMODE 0x0200
226#define STE_FIFOCTL_RXFIFOFULL 0x0800
227#define STE_FIFOCTL_TX_BUSY 0x4000
228#define STE_FIFOCTL_RX_BUSY 0x8000
229
230/*
231 * The number of bytes that must in present in the TX FIFO before
232 * transmission begins. Value should be in increments of 4 bytes.
233 */
234#define STE_TXSTART_THRESH 0x1FFC
235
236/*
237 * Number of bytes that must be present in the RX FIFO before
238 * an RX EARLY interrupt is generated.
239 */
240#define STE_RXEARLY_THRESH 0x1FFC
241
242#define STE_WAKEEVENT_WAKEPKT_ENB 0x01
243#define STE_WAKEEVENT_MAGICPKT_ENB 0x02
244#define STE_WAKEEVENT_LINKEVT_ENB 0x04
245#define STE_WAKEEVENT_WAKEPOLARITY 0x08
246#define STE_WAKEEVENT_WAKEPKTEVENT 0x10
247#define STE_WAKEEVENT_MAGICPKTEVENT 0x20
248#define STE_WAKEEVENT_LINKEVENT 0x40
249#define STE_WAKEEVENT_WAKEONLAN_ENB 0x80
250
251#define STE_TXSTATUS_RECLAIMERR 0x02
252#define STE_TXSTATUS_STATSOFLOW 0x04
253#define STE_TXSTATUS_EXCESSCOLLS 0x08
254#define STE_TXSTATUS_UNDERRUN 0x10
255#define STE_TXSTATUS_TXINTR_REQ 0x40
256#define STE_TXSTATUS_TXDONE 0x80
257
258#define STE_ERR_BITS "\20" \
259 "\2RECLAIM\3STSOFLOW" \
260 "\4EXCESSCOLLS\5UNDERRUN" \
261 "\6INTREQ\7DONE"
262
263#define STE_ISRACK_INTLATCH 0x0001
264#define STE_ISRACK_HOSTERR 0x0002
265#define STE_ISRACK_TX_DONE 0x0004
266#define STE_ISRACK_MACCTL_FRAME 0x0008
267#define STE_ISRACK_RX_DONE 0x0010
268#define STE_ISRACK_RX_EARLY 0x0020
269#define STE_ISRACK_SOFTINTR 0x0040
270#define STE_ISRACK_STATS_OFLOW 0x0080
271#define STE_ISRACK_LINKEVENT 0x0100
272#define STE_ISRACK_TX_DMADONE 0x0200
273#define STE_ISRACK_RX_DMADONE 0x0400
274
275#define STE_IMR_HOSTERR 0x0002
276#define STE_IMR_TX_DONE 0x0004
277#define STE_IMR_MACCTL_FRAME 0x0008
278#define STE_IMR_RX_DONE 0x0010
279#define STE_IMR_RX_EARLY 0x0020
280#define STE_IMR_SOFTINTR 0x0040
281#define STE_IMR_STATS_OFLOW 0x0080
282#define STE_IMR_LINKEVENT 0x0100
283#define STE_IMR_TX_DMADONE 0x0200
284#define STE_IMR_RX_DMADONE 0x0400
285
286#define STE_INTRS \
287 (STE_IMR_RX_DMADONE|STE_IMR_TX_DMADONE| \
288 STE_IMR_TX_DONE|STE_IMR_SOFTINTR| \
289 STE_IMR_HOSTERR)
290
291#define STE_ISR_INTLATCH 0x0001
292#define STE_ISR_HOSTERR 0x0002
293#define STE_ISR_TX_DONE 0x0004
294#define STE_ISR_MACCTL_FRAME 0x0008
295#define STE_ISR_RX_DONE 0x0010
296#define STE_ISR_RX_EARLY 0x0020
297#define STE_ISR_SOFTINTR 0x0040
298#define STE_ISR_STATS_OFLOW 0x0080
299#define STE_ISR_LINKEVENT 0x0100
300#define STE_ISR_TX_DMADONE 0x0200
301#define STE_ISR_RX_DMADONE 0x0400
302
303/*
304 * Note: the Sundance manual gives the impression that the's
305 * only one 32-bit MACCTL register. In fact, there are two
306 * 16-bit registers side by side, and you have to access them
307 * separately.
308 */
309#define STE_MACCTL0_IPG 0x0003
310#define STE_MACCTL0_FULLDUPLEX 0x0020
311#define STE_MACCTL0_RX_GIANTS 0x0040
312#define STE_MACCTL0_FLOWCTL_ENABLE 0x0100
313#define STE_MACCTL0_RX_FCS 0x0200
314#define STE_MACCTL0_FIFOLOOPBK 0x0400
315#define STE_MACCTL0_MACLOOPBK 0x0800
316
317#define STE_MACCTL1_COLLDETECT 0x0001
318#define STE_MACCTL1_CARRSENSE 0x0002
319#define STE_MACCTL1_TX_BUSY 0x0004
320#define STE_MACCTL1_TX_ERROR 0x0008
321#define STE_MACCTL1_STATS_ENABLE 0x0020
322#define STE_MACCTL1_STATS_DISABLE 0x0040
323#define STE_MACCTL1_STATS_ENABLED 0x0080
324#define STE_MACCTL1_TX_ENABLE 0x0100
325#define STE_MACCTL1_TX_DISABLE 0x0200
326#define STE_MACCTL1_TX_ENABLED 0x0400
327#define STE_MACCTL1_RX_ENABLE 0x0800
328#define STE_MACCTL1_RX_DISABLE 0x1000
329#define STE_MACCTL1_RX_ENABLED 0x2000
330#define STE_MACCTL1_PAUSED 0x4000
331
332#define STE_IPG_96BT 0x00000000
333#define STE_IPG_128BT 0x00000001
334#define STE_IPG_224BT 0x00000002
335#define STE_IPG_544BT 0x00000003
336
337#define STE_RXMODE_UNICAST 0x01
338#define STE_RXMODE_ALLMULTI 0x02
339#define STE_RXMODE_BROADCAST 0x04
340#define STE_RXMODE_PROMISC 0x08
341#define STE_RXMODE_MULTIHASH 0x10
342#define STE_RXMODE_ALLIPMULTI 0x20
343
344#define STE_PHYCTL_MCLK 0x01
345#define STE_PHYCTL_MDATA 0x02
346#define STE_PHYCTL_MDIR 0x04
347#define STE_PHYCTL_CLK25_DISABLE 0x08
348#define STE_PHYCTL_DUPLEXPOLARITY 0x10
349#define STE_PHYCTL_DUPLEXSTAT 0x20
350#define STE_PHYCTL_SPEEDSTAT 0x40
351#define STE_PHYCTL_LINKSTAT 0x80
352
353#define STE_TIMER_TICKS 32
354#define STE_TIMER_USECS(x) ((x * 10) / STE_TIMER_TICKS)
355
356#define STE_IM_RX_TIMER_MIN 0
357#define STE_IM_RX_TIMER_MAX 209712
358#define STE_IM_RX_TIMER_DEFAULT 150
359
360/*
361 * EEPROM offsets.
362 */
363#define STE_EEADDR_CONFIGPARM 0x00
364#define STE_EEADDR_ASICCTL 0x02
365#define STE_EEADDR_SUBSYS_ID 0x04
366#define STE_EEADDR_SUBVEN_ID 0x08
367
368#define STE_EEADDR_NODE0 0x10
369#define STE_EEADDR_NODE1 0x12
370#define STE_EEADDR_NODE2 0x14
371
372/* PCI registers */
373#define STE_PCI_VENDOR_ID 0x00
374#define STE_PCI_DEVICE_ID 0x02
375#define STE_PCI_COMMAND 0x04
376#define STE_PCI_STATUS 0x06
377#define STE_PCI_CLASSCODE 0x09
378#define STE_PCI_LATENCY_TIMER 0x0D
379#define STE_PCI_HEADER_TYPE 0x0E
380#define STE_PCI_LOIO 0x10
381#define STE_PCI_LOMEM 0x14
382#define STE_PCI_BIOSROM 0x30
383#define STE_PCI_INTLINE 0x3C
384#define STE_PCI_INTPIN 0x3D
385#define STE_PCI_MINGNT 0x3E
386#define STE_PCI_MINLAT 0x0F
387
388#define STE_PCI_CAPID 0x50 /* 8 bits */
389#define STE_PCI_NEXTPTR 0x51 /* 8 bits */
390#define STE_PCI_PWRMGMTCAP 0x52 /* 16 bits */
391#define STE_PCI_PWRMGMTCTRL 0x54 /* 16 bits */
392
393#define STE_PSTATE_MASK 0x0003
394#define STE_PSTATE_D0 0x0000
395#define STE_PSTATE_D1 0x0002
396#define STE_PSTATE_D2 0x0002
397#define STE_PSTATE_D3 0x0003
398#define STE_PME_EN 0x0010
399#define STE_PME_STATUS 0x8000
400
401struct ste_hw_stats {
402 uint64_t rx_bytes;
403 uint32_t rx_frames;
404 uint32_t rx_bcast_frames;
405 uint32_t rx_mcast_frames;
406 uint32_t rx_lost_frames;
407 uint64_t tx_bytes;
408 uint32_t tx_frames;
409 uint32_t tx_bcast_frames;
410 uint32_t tx_mcast_frames;
411 uint32_t tx_carrsense_errs;
412 uint32_t tx_single_colls;
413 uint32_t tx_multi_colls;
414 uint32_t tx_late_colls;
415 uint32_t tx_frames_defered;
416 uint32_t tx_excess_defers;
417 uint32_t tx_abort;
418};
419
420struct ste_frag {
421 uint32_t ste_addr;
422 uint32_t ste_len;
423};
424
425#define STE_FRAG_LAST 0x80000000
426#define STE_FRAG_LEN 0x00001FFF
427
428/*
429 * A TFD is 16 to 512 bytes in length which means it can have up to 126
430 * fragments for a single Tx frame. Since most frames used in stack have
431 * 3-4 fragments supporting 8 fragments would be enough for normal
432 * operation. If we encounter more than 8 fragments we'll collapse them
433 * into a frame that has less than or equal to 8 fragments. Each buffer
434 * address of a fragment has no alignment limitation.
435 */
436#define STE_MAXFRAGS 8
437
438struct ste_desc {
439 uint32_t ste_next;
440 uint32_t ste_ctl;
441 struct ste_frag ste_frags[STE_MAXFRAGS];
442};
443
444/*
445 * A RFD has the same structure of TFD which in turn means hardware
446 * supports scatter operation in Rx buffer. Since we just allocate Rx
447 * buffer with m_getcl(9) there is no fragmentation at all so use
448 * single fragment for RFD.
449 */
450struct ste_desc_onefrag {
451 uint32_t ste_next;
452 uint32_t ste_status;
453 struct ste_frag ste_frag;
454};
455
456#define STE_TXCTL_WORDALIGN 0x00000003
457#define STE_TXCTL_ALIGN_DIS 0x00000001
458#define STE_TXCTL_FRAMEID 0x000003FC
459#define STE_TXCTL_NOCRC 0x00002000
460#define STE_TXCTL_TXINTR 0x00008000
461#define STE_TXCTL_DMADONE 0x00010000
462#define STE_TXCTL_DMAINTR 0x80000000
463
464#define STE_RXSTAT_FRAMELEN 0x00001FFF
465#define STE_RXSTAT_FRAME_ERR 0x00004000
466#define STE_RXSTAT_DMADONE 0x00008000
467#define STE_RXSTAT_FIFO_OFLOW 0x00010000
468#define STE_RXSTAT_RUNT 0x00020000
469#define STE_RXSTAT_ALIGNERR 0x00040000
470#define STE_RXSTAT_CRCERR 0x00080000
471#define STE_RXSTAT_GIANT 0x00100000
472#define STE_RXSTAT_DRIBBLEBITS 0x00800000
473#define STE_RXSTAT_DMA_OFLOW 0x01000000
474#define STE_RXATAT_ONEBUF 0x10000000
475
476#define STE_RX_BYTES(x) ((x) & STE_RXSTAT_FRAMELEN)
477
478/*
479 * register space access macros
480 */
481#define CSR_WRITE_4(sc, reg, val) \
482 bus_write_4((sc)->ste_res, reg, val)
483#define CSR_WRITE_2(sc, reg, val) \
484 bus_write_2((sc)->ste_res, reg, val)
485#define CSR_WRITE_1(sc, reg, val) \
486 bus_write_1((sc)->ste_res, reg, val)
487
488#define CSR_READ_4(sc, reg) \
489 bus_read_4((sc)->ste_res, reg)
490#define CSR_READ_2(sc, reg) \
491 bus_read_2((sc)->ste_res, reg)
492#define CSR_READ_1(sc, reg) \
493 bus_read_1((sc)->ste_res, reg)
494
| 33 */
34
35/*
36 * Sundance PCI device/vendor ID for the
37 * ST201 chip.
38 */
39#define ST_VENDORID 0x13F0
40#define ST_DEVICEID_ST201_1 0x0200
41#define ST_DEVICEID_ST201_2 0x0201
42
43/*
44 * D-Link PCI device/vendor ID for the DL10050[AB] chip
45 */
46#define DL_VENDORID 0x1186
47#define DL_DEVICEID_DL10050 0x1002
48
49/*
50 * Register definitions for the Sundance Technologies ST201 PCI
51 * fast ethernet controller. The register space is 128 bytes long and
52 * can be accessed using either PCI I/O space or PCI memory mapping.
53 * There are 32-bit, 16-bit and 8-bit registers.
54 */
55
56#define STE_DMACTL 0x00
57#define STE_TX_DMALIST_PTR 0x04
58#define STE_TX_DMABURST_THRESH 0x08
59#define STE_TX_DMAURG_THRESH 0x09
60#define STE_TX_DMAPOLL_PERIOD 0x0A
61#define STE_RX_DMASTATUS 0x0C
62#define STE_RX_DMALIST_PTR 0x10
63#define STE_RX_DMABURST_THRESH 0x14
64#define STE_RX_DMAURG_THRESH 0x15
65#define STE_RX_DMAPOLL_PERIOD 0x16
66#define STE_COUNTDOWN 0x18
67#define STE_DEBUGCTL 0x1A
68#define STE_ASICCTL 0x30
69#define STE_EEPROM_DATA 0x34
70#define STE_EEPROM_CTL 0x36
71#define STE_FIFOCTL 0x3A
72#define STE_TX_STARTTHRESH 0x3C
73#define STE_RX_EARLYTHRESH 0x3E
74#define STE_EXT_ROMADDR 0x40
75#define STE_EXT_ROMDATA 0x44
76#define STE_WAKE_EVENT 0x45
77#define STE_TX_STATUS 0x46
78#define STE_TX_FRAMEID 0x47
79#define STE_ISR_ACK 0x4A
80#define STE_IMR 0x4C
81#define STE_ISR 0x4E
82#define STE_MACCTL0 0x50
83#define STE_MACCTL1 0x52
84#define STE_PAR0 0x54
85#define STE_PAR1 0x56
86#define STE_PAR2 0x58
87#define STE_MAX_FRAMELEN 0x5A
88#define STE_RX_MODE 0x5C
89#define STE_TX_RECLAIM_THRESH 0x5D
90#define STE_PHYCTL 0x5E
91#define STE_MAR0 0x60
92#define STE_MAR1 0x62
93#define STE_MAR2 0x64
94#define STE_MAR3 0x66
95
96#define STE_STAT_RX_OCTETS_LO 0x68
97#define STE_STAT_RX_OCTETS_HI 0x6A
98#define STE_STAT_TX_OCTETS_LO 0x6C
99#define STE_STAT_TX_OCTETS_HI 0x6E
100#define STE_STAT_TX_FRAMES 0x70
101#define STE_STAT_RX_FRAMES 0x72
102#define STE_STAT_CARRIER_ERR 0x74
103#define STE_STAT_LATE_COLLS 0x75
104#define STE_STAT_MULTI_COLLS 0x76
105#define STE_STAT_SINGLE_COLLS 0x77
106#define STE_STAT_TX_DEFER 0x78
107#define STE_STAT_RX_LOST 0x79
108#define STE_STAT_TX_EXDEFER 0x7A
109#define STE_STAT_TX_ABORT 0x7B
110#define STE_STAT_TX_BCAST 0x7C
111#define STE_STAT_RX_BCAST 0x7D
112#define STE_STAT_TX_MCAST 0x7E
113#define STE_STAT_RX_MCAST 0x7F
114
115#define STE_DMACTL_RXDMA_STOPPED 0x00000001
116#define STE_DMACTL_TXDMA_CMPREQ 0x00000002
117#define STE_DMACTL_TXDMA_STOPPED 0x00000004
118#define STE_DMACTL_RXDMA_COMPLETE 0x00000008
119#define STE_DMACTL_TXDMA_COMPLETE 0x00000010
120#define STE_DMACTL_RXDMA_STALL 0x00000100
121#define STE_DMACTL_RXDMA_UNSTALL 0x00000200
122#define STE_DMACTL_TXDMA_STALL 0x00000400
123#define STE_DMACTL_TXDMA_UNSTALL 0x00000800
124#define STE_DMACTL_TXDMA_INPROG 0x00004000
125#define STE_DMACTL_DMA_HALTINPROG 0x00008000
126#define STE_DMACTL_RXEARLY_ENABLE 0x00020000
127#define STE_DMACTL_COUNTDOWN_SPEED 0x00040000
128#define STE_DMACTL_COUNTDOWN_MODE 0x00080000
129#define STE_DMACTL_MWI_DISABLE 0x00100000
130#define STE_DMACTL_RX_DISCARD_OFLOWS 0x00400000
131#define STE_DMACTL_COUNTDOWN_ENABLE 0x00800000
132#define STE_DMACTL_TARGET_ABORT 0x40000000
133#define STE_DMACTL_MASTER_ABORT 0x80000000
134
135/*
136 * TX DMA burst thresh is the number of 32-byte blocks that
137 * must be loaded into the TX Fifo before a TXDMA burst request
138 * will be issued.
139 */
140#define STE_TXDMABURST_THRESH 0x1F
141
142/*
143 * The number of 32-byte blocks in the TX FIFO falls below the
144 * TX DMA urgent threshold, a TX DMA urgent request will be
145 * generated.
146 */
147#define STE_TXDMAURG_THRESH 0x3F
148
149/*
150 * Number of 320ns intervals between polls of the TXDMA next
151 * descriptor pointer (if we're using polling mode).
152 */
153#define STE_TXDMA_POLL_PERIOD 0x7F
154
155#define STE_RX_DMASTATUS_FRAMELEN 0x00001FFF
156#define STE_RX_DMASTATUS_RXERR 0x00004000
157#define STE_RX_DMASTATUS_DMADONE 0x00008000
158#define STE_RX_DMASTATUS_FIFO_OFLOW 0x00010000
159#define STE_RX_DMASTATUS_RUNT 0x00020000
160#define STE_RX_DMASTATUS_ALIGNERR 0x00040000
161#define STE_RX_DMASTATUS_CRCERR 0x00080000
162#define STE_RX_DMASTATUS_GIANT 0x00100000
163#define STE_RX_DMASTATUS_DRIBBLE 0x00800000
164#define STE_RX_DMASTATUS_DMA_OFLOW 0x01000000
165
166/*
167 * RX DMA burst thresh is the number of 32-byte blocks that
168 * must be present in the RX FIFO before a RXDMA bus master
169 * request will be issued.
170 */
171#define STE_RXDMABURST_THRESH 0xFF
172
173/*
174 * The number of 32-byte blocks in the RX FIFO falls below the
175 * RX DMA urgent threshold, a RX DMA urgent request will be
176 * generated.
177 */
178#define STE_RXDMAURG_THRESH 0x1F
179
180/*
181 * Number of 320ns intervals between polls of the RXDMA complete
182 * bit in the status field on the current RX descriptor (if we're
183 * using polling mode).
184 */
185#define STE_RXDMA_POLL_PERIOD 0x7F
186
187#define STE_DEBUGCTL_GPIO0_CTL 0x0001
188#define STE_DEBUGCTL_GPIO1_CTL 0x0002
189#define STE_DEBUGCTL_GPIO0_DATA 0x0004
190#define STE_DEBUGCTL_GPIO1_DATA 0x0008
191
192#define STE_ASICCTL_ROMSIZE 0x00000002
193#define STE_ASICCTL_TX_LARGEPKTS 0x00000004
194#define STE_ASICCTL_RX_LARGEPKTS 0x00000008
195#define STE_ASICCTL_EXTROM_DISABLE 0x00000010
196#define STE_ASICCTL_PHYSPEED_10 0x00000020
197#define STE_ASICCTL_PHYSPEED_100 0x00000040
198#define STE_ASICCTL_PHYMEDIA 0x00000080
199#define STE_ASICCTL_FORCEDCONFIG 0x00000700
200#define STE_ASICCTL_D3RESET_DISABLE 0x00000800
201#define STE_ASICCTL_SPEEDUPMODE 0x00002000
202#define STE_ASICCTL_LEDMODE 0x00004000
203#define STE_ASICCTL_RSTOUT_POLARITY 0x00008000
204#define STE_ASICCTL_GLOBAL_RESET 0x00010000
205#define STE_ASICCTL_RX_RESET 0x00020000
206#define STE_ASICCTL_TX_RESET 0x00040000
207#define STE_ASICCTL_DMA_RESET 0x00080000
208#define STE_ASICCTL_FIFO_RESET 0x00100000
209#define STE_ASICCTL_NETWORK_RESET 0x00200000
210#define STE_ASICCTL_HOST_RESET 0x00400000
211#define STE_ASICCTL_AUTOINIT_RESET 0x00800000
212#define STE_ASICCTL_EXTRESET_RESET 0x01000000
213#define STE_ASICCTL_SOFTINTR 0x02000000
214#define STE_ASICCTL_RESET_BUSY 0x04000000
215
216#define STE_EECTL_ADDR 0x00FF
217#define STE_EECTL_OPCODE 0x0300
218#define STE_EECTL_BUSY 0x1000
219
220#define STE_EEOPCODE_WRITE 0x0100
221#define STE_EEOPCODE_READ 0x0200
222#define STE_EEOPCODE_ERASE 0x0300
223
224#define STE_FIFOCTL_RAMTESTMODE 0x0001
225#define STE_FIFOCTL_OVERRUNMODE 0x0200
226#define STE_FIFOCTL_RXFIFOFULL 0x0800
227#define STE_FIFOCTL_TX_BUSY 0x4000
228#define STE_FIFOCTL_RX_BUSY 0x8000
229
230/*
231 * The number of bytes that must in present in the TX FIFO before
232 * transmission begins. Value should be in increments of 4 bytes.
233 */
234#define STE_TXSTART_THRESH 0x1FFC
235
236/*
237 * Number of bytes that must be present in the RX FIFO before
238 * an RX EARLY interrupt is generated.
239 */
240#define STE_RXEARLY_THRESH 0x1FFC
241
242#define STE_WAKEEVENT_WAKEPKT_ENB 0x01
243#define STE_WAKEEVENT_MAGICPKT_ENB 0x02
244#define STE_WAKEEVENT_LINKEVT_ENB 0x04
245#define STE_WAKEEVENT_WAKEPOLARITY 0x08
246#define STE_WAKEEVENT_WAKEPKTEVENT 0x10
247#define STE_WAKEEVENT_MAGICPKTEVENT 0x20
248#define STE_WAKEEVENT_LINKEVENT 0x40
249#define STE_WAKEEVENT_WAKEONLAN_ENB 0x80
250
251#define STE_TXSTATUS_RECLAIMERR 0x02
252#define STE_TXSTATUS_STATSOFLOW 0x04
253#define STE_TXSTATUS_EXCESSCOLLS 0x08
254#define STE_TXSTATUS_UNDERRUN 0x10
255#define STE_TXSTATUS_TXINTR_REQ 0x40
256#define STE_TXSTATUS_TXDONE 0x80
257
258#define STE_ERR_BITS "\20" \
259 "\2RECLAIM\3STSOFLOW" \
260 "\4EXCESSCOLLS\5UNDERRUN" \
261 "\6INTREQ\7DONE"
262
263#define STE_ISRACK_INTLATCH 0x0001
264#define STE_ISRACK_HOSTERR 0x0002
265#define STE_ISRACK_TX_DONE 0x0004
266#define STE_ISRACK_MACCTL_FRAME 0x0008
267#define STE_ISRACK_RX_DONE 0x0010
268#define STE_ISRACK_RX_EARLY 0x0020
269#define STE_ISRACK_SOFTINTR 0x0040
270#define STE_ISRACK_STATS_OFLOW 0x0080
271#define STE_ISRACK_LINKEVENT 0x0100
272#define STE_ISRACK_TX_DMADONE 0x0200
273#define STE_ISRACK_RX_DMADONE 0x0400
274
275#define STE_IMR_HOSTERR 0x0002
276#define STE_IMR_TX_DONE 0x0004
277#define STE_IMR_MACCTL_FRAME 0x0008
278#define STE_IMR_RX_DONE 0x0010
279#define STE_IMR_RX_EARLY 0x0020
280#define STE_IMR_SOFTINTR 0x0040
281#define STE_IMR_STATS_OFLOW 0x0080
282#define STE_IMR_LINKEVENT 0x0100
283#define STE_IMR_TX_DMADONE 0x0200
284#define STE_IMR_RX_DMADONE 0x0400
285
286#define STE_INTRS \
287 (STE_IMR_RX_DMADONE|STE_IMR_TX_DMADONE| \
288 STE_IMR_TX_DONE|STE_IMR_SOFTINTR| \
289 STE_IMR_HOSTERR)
290
291#define STE_ISR_INTLATCH 0x0001
292#define STE_ISR_HOSTERR 0x0002
293#define STE_ISR_TX_DONE 0x0004
294#define STE_ISR_MACCTL_FRAME 0x0008
295#define STE_ISR_RX_DONE 0x0010
296#define STE_ISR_RX_EARLY 0x0020
297#define STE_ISR_SOFTINTR 0x0040
298#define STE_ISR_STATS_OFLOW 0x0080
299#define STE_ISR_LINKEVENT 0x0100
300#define STE_ISR_TX_DMADONE 0x0200
301#define STE_ISR_RX_DMADONE 0x0400
302
303/*
304 * Note: the Sundance manual gives the impression that the's
305 * only one 32-bit MACCTL register. In fact, there are two
306 * 16-bit registers side by side, and you have to access them
307 * separately.
308 */
309#define STE_MACCTL0_IPG 0x0003
310#define STE_MACCTL0_FULLDUPLEX 0x0020
311#define STE_MACCTL0_RX_GIANTS 0x0040
312#define STE_MACCTL0_FLOWCTL_ENABLE 0x0100
313#define STE_MACCTL0_RX_FCS 0x0200
314#define STE_MACCTL0_FIFOLOOPBK 0x0400
315#define STE_MACCTL0_MACLOOPBK 0x0800
316
317#define STE_MACCTL1_COLLDETECT 0x0001
318#define STE_MACCTL1_CARRSENSE 0x0002
319#define STE_MACCTL1_TX_BUSY 0x0004
320#define STE_MACCTL1_TX_ERROR 0x0008
321#define STE_MACCTL1_STATS_ENABLE 0x0020
322#define STE_MACCTL1_STATS_DISABLE 0x0040
323#define STE_MACCTL1_STATS_ENABLED 0x0080
324#define STE_MACCTL1_TX_ENABLE 0x0100
325#define STE_MACCTL1_TX_DISABLE 0x0200
326#define STE_MACCTL1_TX_ENABLED 0x0400
327#define STE_MACCTL1_RX_ENABLE 0x0800
328#define STE_MACCTL1_RX_DISABLE 0x1000
329#define STE_MACCTL1_RX_ENABLED 0x2000
330#define STE_MACCTL1_PAUSED 0x4000
331
332#define STE_IPG_96BT 0x00000000
333#define STE_IPG_128BT 0x00000001
334#define STE_IPG_224BT 0x00000002
335#define STE_IPG_544BT 0x00000003
336
337#define STE_RXMODE_UNICAST 0x01
338#define STE_RXMODE_ALLMULTI 0x02
339#define STE_RXMODE_BROADCAST 0x04
340#define STE_RXMODE_PROMISC 0x08
341#define STE_RXMODE_MULTIHASH 0x10
342#define STE_RXMODE_ALLIPMULTI 0x20
343
344#define STE_PHYCTL_MCLK 0x01
345#define STE_PHYCTL_MDATA 0x02
346#define STE_PHYCTL_MDIR 0x04
347#define STE_PHYCTL_CLK25_DISABLE 0x08
348#define STE_PHYCTL_DUPLEXPOLARITY 0x10
349#define STE_PHYCTL_DUPLEXSTAT 0x20
350#define STE_PHYCTL_SPEEDSTAT 0x40
351#define STE_PHYCTL_LINKSTAT 0x80
352
353#define STE_TIMER_TICKS 32
354#define STE_TIMER_USECS(x) ((x * 10) / STE_TIMER_TICKS)
355
356#define STE_IM_RX_TIMER_MIN 0
357#define STE_IM_RX_TIMER_MAX 209712
358#define STE_IM_RX_TIMER_DEFAULT 150
359
360/*
361 * EEPROM offsets.
362 */
363#define STE_EEADDR_CONFIGPARM 0x00
364#define STE_EEADDR_ASICCTL 0x02
365#define STE_EEADDR_SUBSYS_ID 0x04
366#define STE_EEADDR_SUBVEN_ID 0x08
367
368#define STE_EEADDR_NODE0 0x10
369#define STE_EEADDR_NODE1 0x12
370#define STE_EEADDR_NODE2 0x14
371
372/* PCI registers */
373#define STE_PCI_VENDOR_ID 0x00
374#define STE_PCI_DEVICE_ID 0x02
375#define STE_PCI_COMMAND 0x04
376#define STE_PCI_STATUS 0x06
377#define STE_PCI_CLASSCODE 0x09
378#define STE_PCI_LATENCY_TIMER 0x0D
379#define STE_PCI_HEADER_TYPE 0x0E
380#define STE_PCI_LOIO 0x10
381#define STE_PCI_LOMEM 0x14
382#define STE_PCI_BIOSROM 0x30
383#define STE_PCI_INTLINE 0x3C
384#define STE_PCI_INTPIN 0x3D
385#define STE_PCI_MINGNT 0x3E
386#define STE_PCI_MINLAT 0x0F
387
388#define STE_PCI_CAPID 0x50 /* 8 bits */
389#define STE_PCI_NEXTPTR 0x51 /* 8 bits */
390#define STE_PCI_PWRMGMTCAP 0x52 /* 16 bits */
391#define STE_PCI_PWRMGMTCTRL 0x54 /* 16 bits */
392
393#define STE_PSTATE_MASK 0x0003
394#define STE_PSTATE_D0 0x0000
395#define STE_PSTATE_D1 0x0002
396#define STE_PSTATE_D2 0x0002
397#define STE_PSTATE_D3 0x0003
398#define STE_PME_EN 0x0010
399#define STE_PME_STATUS 0x8000
400
401struct ste_hw_stats {
402 uint64_t rx_bytes;
403 uint32_t rx_frames;
404 uint32_t rx_bcast_frames;
405 uint32_t rx_mcast_frames;
406 uint32_t rx_lost_frames;
407 uint64_t tx_bytes;
408 uint32_t tx_frames;
409 uint32_t tx_bcast_frames;
410 uint32_t tx_mcast_frames;
411 uint32_t tx_carrsense_errs;
412 uint32_t tx_single_colls;
413 uint32_t tx_multi_colls;
414 uint32_t tx_late_colls;
415 uint32_t tx_frames_defered;
416 uint32_t tx_excess_defers;
417 uint32_t tx_abort;
418};
419
420struct ste_frag {
421 uint32_t ste_addr;
422 uint32_t ste_len;
423};
424
425#define STE_FRAG_LAST 0x80000000
426#define STE_FRAG_LEN 0x00001FFF
427
428/*
429 * A TFD is 16 to 512 bytes in length which means it can have up to 126
430 * fragments for a single Tx frame. Since most frames used in stack have
431 * 3-4 fragments supporting 8 fragments would be enough for normal
432 * operation. If we encounter more than 8 fragments we'll collapse them
433 * into a frame that has less than or equal to 8 fragments. Each buffer
434 * address of a fragment has no alignment limitation.
435 */
436#define STE_MAXFRAGS 8
437
438struct ste_desc {
439 uint32_t ste_next;
440 uint32_t ste_ctl;
441 struct ste_frag ste_frags[STE_MAXFRAGS];
442};
443
444/*
445 * A RFD has the same structure of TFD which in turn means hardware
446 * supports scatter operation in Rx buffer. Since we just allocate Rx
447 * buffer with m_getcl(9) there is no fragmentation at all so use
448 * single fragment for RFD.
449 */
450struct ste_desc_onefrag {
451 uint32_t ste_next;
452 uint32_t ste_status;
453 struct ste_frag ste_frag;
454};
455
456#define STE_TXCTL_WORDALIGN 0x00000003
457#define STE_TXCTL_ALIGN_DIS 0x00000001
458#define STE_TXCTL_FRAMEID 0x000003FC
459#define STE_TXCTL_NOCRC 0x00002000
460#define STE_TXCTL_TXINTR 0x00008000
461#define STE_TXCTL_DMADONE 0x00010000
462#define STE_TXCTL_DMAINTR 0x80000000
463
464#define STE_RXSTAT_FRAMELEN 0x00001FFF
465#define STE_RXSTAT_FRAME_ERR 0x00004000
466#define STE_RXSTAT_DMADONE 0x00008000
467#define STE_RXSTAT_FIFO_OFLOW 0x00010000
468#define STE_RXSTAT_RUNT 0x00020000
469#define STE_RXSTAT_ALIGNERR 0x00040000
470#define STE_RXSTAT_CRCERR 0x00080000
471#define STE_RXSTAT_GIANT 0x00100000
472#define STE_RXSTAT_DRIBBLEBITS 0x00800000
473#define STE_RXSTAT_DMA_OFLOW 0x01000000
474#define STE_RXATAT_ONEBUF 0x10000000
475
476#define STE_RX_BYTES(x) ((x) & STE_RXSTAT_FRAMELEN)
477
478/*
479 * register space access macros
480 */
481#define CSR_WRITE_4(sc, reg, val) \
482 bus_write_4((sc)->ste_res, reg, val)
483#define CSR_WRITE_2(sc, reg, val) \
484 bus_write_2((sc)->ste_res, reg, val)
485#define CSR_WRITE_1(sc, reg, val) \
486 bus_write_1((sc)->ste_res, reg, val)
487
488#define CSR_READ_4(sc, reg) \
489 bus_read_4((sc)->ste_res, reg)
490#define CSR_READ_2(sc, reg) \
491 bus_read_2((sc)->ste_res, reg)
492#define CSR_READ_1(sc, reg) \
493 bus_read_1((sc)->ste_res, reg)
494
|
| 495#define CSR_BARRIER(sc, reg, length, flags) \
496 bus_barrier((sc)->ste_res, reg, length, flags)
497
|
495#define STE_DESC_ALIGN 8
496#define STE_RX_LIST_CNT 128
497#define STE_TX_LIST_CNT 128
498#define STE_RX_LIST_SZ \
499 (sizeof(struct ste_desc_onefrag) * STE_RX_LIST_CNT)
500#define STE_TX_LIST_SZ \
501 (sizeof(struct ste_desc) * STE_TX_LIST_CNT)
502#define STE_ADDR_LO(x) ((uint64_t)(x) & 0xFFFFFFFF)
503#define STE_ADDR_HI(x) ((uint64_t)(x) >> 32)
504
505/*
506 * Since Tx status can hold up to 31 status bytes we should
507 * check Tx status before controller fills it up. Otherwise
508 * Tx MAC stalls.
509 */
510#define STE_TX_INTR_FRAMES 16
511#define STE_TX_TIMEOUT 5
512#define STE_TIMEOUT 1000
513#define STE_MIN_FRAMELEN 60
514#define STE_PACKET_SIZE 1536
515#define STE_INC(x, y) (x) = (x + 1) % y
516#define STE_DEC(x, y) (x) = ((x) + ((y) - 1)) % (y)
517#define STE_NEXT(x, y) (x + 1) % y
518
519struct ste_type {
520 uint16_t ste_vid;
521 uint16_t ste_did;
| 498#define STE_DESC_ALIGN 8
499#define STE_RX_LIST_CNT 128
500#define STE_TX_LIST_CNT 128
501#define STE_RX_LIST_SZ \
502 (sizeof(struct ste_desc_onefrag) * STE_RX_LIST_CNT)
503#define STE_TX_LIST_SZ \
504 (sizeof(struct ste_desc) * STE_TX_LIST_CNT)
505#define STE_ADDR_LO(x) ((uint64_t)(x) & 0xFFFFFFFF)
506#define STE_ADDR_HI(x) ((uint64_t)(x) >> 32)
507
508/*
509 * Since Tx status can hold up to 31 status bytes we should
510 * check Tx status before controller fills it up. Otherwise
511 * Tx MAC stalls.
512 */
513#define STE_TX_INTR_FRAMES 16
514#define STE_TX_TIMEOUT 5
515#define STE_TIMEOUT 1000
516#define STE_MIN_FRAMELEN 60
517#define STE_PACKET_SIZE 1536
518#define STE_INC(x, y) (x) = (x + 1) % y
519#define STE_DEC(x, y) (x) = ((x) + ((y) - 1)) % (y)
520#define STE_NEXT(x, y) (x + 1) % y
521
522struct ste_type {
523 uint16_t ste_vid;
524 uint16_t ste_did;
|
522 char *ste_name;
| 525 const char *ste_name;
|
523};
524
525struct ste_list_data {
526 struct ste_desc_onefrag *ste_rx_list;
527 bus_addr_t ste_rx_list_paddr;
528 struct ste_desc *ste_tx_list;
529 bus_addr_t ste_tx_list_paddr;
530};
531
532struct ste_chain {
533 struct ste_desc *ste_ptr;
534 struct mbuf *ste_mbuf;
535 struct ste_chain *ste_next;
536 uint32_t ste_phys;
537 bus_dmamap_t ste_map;
538};
539
540struct ste_chain_onefrag {
541 struct ste_desc_onefrag *ste_ptr;
542 struct mbuf *ste_mbuf;
543 struct ste_chain_onefrag *ste_next;
544 bus_dmamap_t ste_map;
545};
546
547struct ste_chain_data {
548 bus_dma_tag_t ste_parent_tag;
549 bus_dma_tag_t ste_rx_tag;
550 bus_dma_tag_t ste_tx_tag;
551 bus_dma_tag_t ste_rx_list_tag;
552 bus_dmamap_t ste_rx_list_map;
553 bus_dma_tag_t ste_tx_list_tag;
554 bus_dmamap_t ste_tx_list_map;
555 bus_dmamap_t ste_rx_sparemap;
556 struct ste_chain_onefrag ste_rx_chain[STE_RX_LIST_CNT];
557 struct ste_chain ste_tx_chain[STE_TX_LIST_CNT];
558 struct ste_chain_onefrag *ste_rx_head;
559 struct ste_chain *ste_last_tx;
560 int ste_tx_prod;
561 int ste_tx_cons;
562 int ste_tx_cnt;
563};
564
565struct ste_softc {
566 struct ifnet *ste_ifp;
567 struct resource *ste_res;
568 int ste_res_id;
569 int ste_res_type;
570 struct resource *ste_irq;
571 void *ste_intrhand;
572 struct ste_type *ste_info;
573 device_t ste_miibus;
574 device_t ste_dev;
575 int ste_tx_thresh;
576 int ste_flags;
577#define STE_FLAG_ONE_PHY 0x0001
578#define STE_FLAG_LINK 0x8000
579 int ste_if_flags;
580 int ste_timer;
581 int ste_int_rx_act;
582 int ste_int_rx_mod;
583 struct ste_list_data ste_ldata;
584 struct ste_chain_data ste_cdata;
585 struct callout ste_callout;
586 struct ste_hw_stats ste_stats;
587 struct mtx ste_mtx;
588};
589
590#define STE_LOCK(_sc) mtx_lock(&(_sc)->ste_mtx)
591#define STE_UNLOCK(_sc) mtx_unlock(&(_sc)->ste_mtx)
592#define STE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->ste_mtx, MA_OWNED)
| 526};
527
528struct ste_list_data {
529 struct ste_desc_onefrag *ste_rx_list;
530 bus_addr_t ste_rx_list_paddr;
531 struct ste_desc *ste_tx_list;
532 bus_addr_t ste_tx_list_paddr;
533};
534
535struct ste_chain {
536 struct ste_desc *ste_ptr;
537 struct mbuf *ste_mbuf;
538 struct ste_chain *ste_next;
539 uint32_t ste_phys;
540 bus_dmamap_t ste_map;
541};
542
543struct ste_chain_onefrag {
544 struct ste_desc_onefrag *ste_ptr;
545 struct mbuf *ste_mbuf;
546 struct ste_chain_onefrag *ste_next;
547 bus_dmamap_t ste_map;
548};
549
550struct ste_chain_data {
551 bus_dma_tag_t ste_parent_tag;
552 bus_dma_tag_t ste_rx_tag;
553 bus_dma_tag_t ste_tx_tag;
554 bus_dma_tag_t ste_rx_list_tag;
555 bus_dmamap_t ste_rx_list_map;
556 bus_dma_tag_t ste_tx_list_tag;
557 bus_dmamap_t ste_tx_list_map;
558 bus_dmamap_t ste_rx_sparemap;
559 struct ste_chain_onefrag ste_rx_chain[STE_RX_LIST_CNT];
560 struct ste_chain ste_tx_chain[STE_TX_LIST_CNT];
561 struct ste_chain_onefrag *ste_rx_head;
562 struct ste_chain *ste_last_tx;
563 int ste_tx_prod;
564 int ste_tx_cons;
565 int ste_tx_cnt;
566};
567
568struct ste_softc {
569 struct ifnet *ste_ifp;
570 struct resource *ste_res;
571 int ste_res_id;
572 int ste_res_type;
573 struct resource *ste_irq;
574 void *ste_intrhand;
575 struct ste_type *ste_info;
576 device_t ste_miibus;
577 device_t ste_dev;
578 int ste_tx_thresh;
579 int ste_flags;
580#define STE_FLAG_ONE_PHY 0x0001
581#define STE_FLAG_LINK 0x8000
582 int ste_if_flags;
583 int ste_timer;
584 int ste_int_rx_act;
585 int ste_int_rx_mod;
586 struct ste_list_data ste_ldata;
587 struct ste_chain_data ste_cdata;
588 struct callout ste_callout;
589 struct ste_hw_stats ste_stats;
590 struct mtx ste_mtx;
591};
592
593#define STE_LOCK(_sc) mtx_lock(&(_sc)->ste_mtx)
594#define STE_UNLOCK(_sc) mtx_unlock(&(_sc)->ste_mtx)
595#define STE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->ste_mtx, MA_OWNED)
|
593
594struct ste_mii_frame {
595 uint8_t mii_stdelim;
596 uint8_t mii_opcode;
597 uint8_t mii_phyaddr;
598 uint8_t mii_regaddr;
599 uint8_t mii_turnaround;
600 uint16_t mii_data;
601};
602
603/*
604 * MII constants
605 */
606#define STE_MII_STARTDELIM 0x01
607#define STE_MII_READOP 0x02
608#define STE_MII_WRITEOP 0x01
609#define STE_MII_TURNAROUND 0x02
| |
| |