36
37/* -------------------------------------------------------------------- */
38
39#define ICH_TIMEOUT 1000 /* semaphore timeout polling count */
40#define ICH_DTBL_LENGTH 32
41#define ICH_DEFAULT_BUFSZ 16384
42#define ICH_MAX_BUFSZ 65536
43
44#define SIS7012ID 0x70121039 /* SiS 7012 needs special handling */
45#define ICH4ID 0x24c58086 /* ICH4 needs special handling too */
46#define ICH5ID 0x24d58086 /* ICH5 needs to be treated as ICH4 */
47
48/* buffer descriptor */
49struct ich_desc {
50 volatile u_int32_t buffer;
51 volatile u_int32_t length;
52};
53
54struct sc_info;
55
56/* channel registers */
57struct sc_chinfo {
58 u_int32_t num:8, run:1, run_save:1;
59 u_int32_t blksz, blkcnt, spd;
60 u_int32_t regbase, spdreg;
61 u_int32_t imask;
62 u_int32_t civ;
63
64 struct snd_dbuf *buffer;
65 struct pcm_channel *channel;
66 struct sc_info *parent;
67
68 struct ich_desc *dtbl;
69 bus_addr_t desc_addr;
70};
71
72/* device private data */
73struct sc_info {
74 device_t dev;
75 int hasvra, hasvrm, hasmic;
76 unsigned int chnum, bufsz;
77 int sample_size, swap_reg;
78
79 struct resource *nambar, *nabmbar, *irq;
80 int regtype, nambarid, nabmbarid, irqid;
81 bus_space_tag_t nambart, nabmbart;
82 bus_space_handle_t nambarh, nabmbarh;
83 bus_dma_tag_t dmat;
84 bus_dmamap_t dtmap;
85 void *ih;
86
87 struct ac97_info *codec;
88 struct sc_chinfo ch[3];
89 int ac97rate;
90 struct ich_desc *dtbl;
91 bus_addr_t desc_addr;
92 struct intr_config_hook intrhook;
93 int use_intrhook;
94};
95
96/* -------------------------------------------------------------------- */
97
98static u_int32_t ich_fmt[] = {
99 AFMT_STEREO | AFMT_S16_LE,
100 0
101};
102static struct pcmchan_caps ich_vrcaps = {8000, 48000, ich_fmt, 0};
103static struct pcmchan_caps ich_caps = {48000, 48000, ich_fmt, 0};
104
105/* -------------------------------------------------------------------- */
106/* Hardware */
107static u_int32_t
108ich_rd(struct sc_info *sc, int regno, int size)
109{
110 switch (size) {
111 case 1:
112 return bus_space_read_1(sc->nabmbart, sc->nabmbarh, regno);
113 case 2:
114 return bus_space_read_2(sc->nabmbart, sc->nabmbarh, regno);
115 case 4:
116 return bus_space_read_4(sc->nabmbart, sc->nabmbarh, regno);
117 default:
118 return 0xffffffff;
119 }
120}
121
122static void
123ich_wr(struct sc_info *sc, int regno, u_int32_t data, int size)
124{
125 switch (size) {
126 case 1:
127 bus_space_write_1(sc->nabmbart, sc->nabmbarh, regno, data);
128 break;
129 case 2:
130 bus_space_write_2(sc->nabmbart, sc->nabmbarh, regno, data);
131 break;
132 case 4:
133 bus_space_write_4(sc->nabmbart, sc->nabmbarh, regno, data);
134 break;
135 }
136}
137
138/* ac97 codec */
139static int
140ich_waitcd(void *devinfo)
141{
142 int i;
143 u_int32_t data;
144 struct sc_info *sc = (struct sc_info *)devinfo;
145
146 for (i = 0; i < ICH_TIMEOUT; i++) {
147 data = ich_rd(sc, ICH_REG_ACC_SEMA, 1);
148 if ((data & 0x01) == 0)
149 return 0;
150 }
151 device_printf(sc->dev, "CODEC semaphore timeout\n");
152 return ETIMEDOUT;
153}
154
155static int
156ich_rdcd(kobj_t obj, void *devinfo, int regno)
157{
158 struct sc_info *sc = (struct sc_info *)devinfo;
159
160 regno &= 0xff;
161 ich_waitcd(sc);
162
163 return bus_space_read_2(sc->nambart, sc->nambarh, regno);
164}
165
166static int
167ich_wrcd(kobj_t obj, void *devinfo, int regno, u_int16_t data)
168{
169 struct sc_info *sc = (struct sc_info *)devinfo;
170
171 regno &= 0xff;
172 ich_waitcd(sc);
173 bus_space_write_2(sc->nambart, sc->nambarh, regno, data);
174
175 return 0;
176}
177
178static kobj_method_t ich_ac97_methods[] = {
179 KOBJMETHOD(ac97_read, ich_rdcd),
180 KOBJMETHOD(ac97_write, ich_wrcd),
181 { 0, 0 }
182};
183AC97_DECLARE(ich_ac97);
184
185/* -------------------------------------------------------------------- */
186/* common routines */
187
188static void
189ich_filldtbl(struct sc_chinfo *ch)
190{
191 u_int32_t base;
192 int i;
193
194 base = sndbuf_getbufaddr(ch->buffer);
195 ch->blkcnt = sndbuf_getsize(ch->buffer) / ch->blksz;
196 if (ch->blkcnt != 2 && ch->blkcnt != 4 && ch->blkcnt != 8 && ch->blkcnt != 16 && ch->blkcnt != 32) {
197 ch->blkcnt = 2;
198 ch->blksz = sndbuf_getsize(ch->buffer) / ch->blkcnt;
199 }
200
201 for (i = 0; i < ICH_DTBL_LENGTH; i++) {
202 ch->dtbl[i].buffer = base + (ch->blksz * (i % ch->blkcnt));
203 ch->dtbl[i].length = ICH_BDC_IOC
204 | (ch->blksz / ch->parent->sample_size);
205 }
206}
207
208static int
209ich_resetchan(struct sc_info *sc, int num)
210{
211 int i, cr, regbase;
212
213 if (num == 0)
214 regbase = ICH_REG_PO_BASE;
215 else if (num == 1)
216 regbase = ICH_REG_PI_BASE;
217 else if (num == 2)
218 regbase = ICH_REG_MC_BASE;
219 else
220 return ENXIO;
221
222 ich_wr(sc, regbase + ICH_REG_X_CR, 0, 1);
223 DELAY(100);
224 ich_wr(sc, regbase + ICH_REG_X_CR, ICH_X_CR_RR, 1);
225 for (i = 0; i < ICH_TIMEOUT; i++) {
226 cr = ich_rd(sc, regbase + ICH_REG_X_CR, 1);
227 if (cr == 0)
228 return 0;
229 }
230
231 device_printf(sc->dev, "cannot reset channel %d\n", num);
232 return ENXIO;
233}
234
235/* -------------------------------------------------------------------- */
236/* channel interface */
237
238static void *
239ichchan_init(kobj_t obj, void *devinfo, struct snd_dbuf *b, struct pcm_channel *c, int dir)
240{
241 struct sc_info *sc = devinfo;
242 struct sc_chinfo *ch;
243 unsigned int num;
244
245 num = sc->chnum++;
246 ch = &sc->ch[num];
247 ch->num = num;
248 ch->buffer = b;
249 ch->channel = c;
250 ch->parent = sc;
251 ch->run = 0;
252 ch->dtbl = sc->dtbl + (ch->num * ICH_DTBL_LENGTH);
253 ch->desc_addr = sc->desc_addr + (ch->num * ICH_DTBL_LENGTH) *
254 sizeof(struct ich_desc);
255 ch->blkcnt = 2;
256 ch->blksz = sc->bufsz / ch->blkcnt;
257
258 switch(ch->num) {
259 case 0: /* play */
260 KASSERT(dir == PCMDIR_PLAY, ("wrong direction"));
261 ch->regbase = ICH_REG_PO_BASE;
262 ch->spdreg = sc->hasvra? AC97_REGEXT_FDACRATE : 0;
263 ch->imask = ICH_GLOB_STA_POINT;
264 break;
265
266 case 1: /* record */
267 KASSERT(dir == PCMDIR_REC, ("wrong direction"));
268 ch->regbase = ICH_REG_PI_BASE;
269 ch->spdreg = sc->hasvra? AC97_REGEXT_LADCRATE : 0;
270 ch->imask = ICH_GLOB_STA_PIINT;
271 break;
272
273 case 2: /* mic */
274 KASSERT(dir == PCMDIR_REC, ("wrong direction"));
275 ch->regbase = ICH_REG_MC_BASE;
276 ch->spdreg = sc->hasvrm? AC97_REGEXT_MADCRATE : 0;
277 ch->imask = ICH_GLOB_STA_MINT;
278 break;
279
280 default:
281 return NULL;
282 }
283
284 if (sndbuf_alloc(ch->buffer, sc->dmat, sc->bufsz))
285 return NULL;
286
287 ich_wr(sc, ch->regbase + ICH_REG_X_BDBAR, (u_int32_t)(ch->desc_addr), 4);
288
289 return ch;
290}
291
292static int
293ichchan_setformat(kobj_t obj, void *data, u_int32_t format)
294{
295 return 0;
296}
297
298static int
299ichchan_setspeed(kobj_t obj, void *data, u_int32_t speed)
300{
301 struct sc_chinfo *ch = data;
302 struct sc_info *sc = ch->parent;
303
304 if (ch->spdreg) {
305 int r;
306 if (sc->ac97rate <= 32000 || sc->ac97rate >= 64000)
307 sc->ac97rate = 48000;
308 r = (speed * 48000) / sc->ac97rate;
309 /*
310 * Cast the return value of ac97_setrate() to u_int so that
311 * the math don't overflow into the negative range.
312 */
313 ch->spd = ((u_int)ac97_setrate(sc->codec, ch->spdreg, r) *
314 sc->ac97rate) / 48000;
315 } else {
316 ch->spd = 48000;
317 }
318 return ch->spd;
319}
320
321static int
322ichchan_setblocksize(kobj_t obj, void *data, u_int32_t blocksize)
323{
324 struct sc_chinfo *ch = data;
325 struct sc_info *sc = ch->parent;
326
327 ch->blksz = blocksize;
328 ich_filldtbl(ch);
329 ich_wr(sc, ch->regbase + ICH_REG_X_LVI, ch->blkcnt - 1, 1);
330
331 return ch->blksz;
332}
333
334static int
335ichchan_trigger(kobj_t obj, void *data, int go)
336{
337 struct sc_chinfo *ch = data;
338 struct sc_info *sc = ch->parent;
339
340 switch (go) {
341 case PCMTRIG_START:
342 ch->run = 1;
343 ich_wr(sc, ch->regbase + ICH_REG_X_BDBAR, (u_int32_t)(ch->desc_addr), 4);
344 ich_wr(sc, ch->regbase + ICH_REG_X_CR, ICH_X_CR_RPBM | ICH_X_CR_LVBIE | ICH_X_CR_IOCE, 1);
345 break;
346
347 case PCMTRIG_ABORT:
348 ich_resetchan(sc, ch->num);
349 ch->run = 0;
350 break;
351 }
352 return 0;
353}
354
355static int
356ichchan_getptr(kobj_t obj, void *data)
357{
358 struct sc_chinfo *ch = data;
359 struct sc_info *sc = ch->parent;
360 u_int32_t pos;
361
362 ch->civ = ich_rd(sc, ch->regbase + ICH_REG_X_CIV, 1) % ch->blkcnt;
363
364 pos = ch->civ * ch->blksz;
365
366 return pos;
367}
368
369static struct pcmchan_caps *
370ichchan_getcaps(kobj_t obj, void *data)
371{
372 struct sc_chinfo *ch = data;
373
374 return ch->spdreg? &ich_vrcaps : &ich_caps;
375}
376
377static kobj_method_t ichchan_methods[] = {
378 KOBJMETHOD(channel_init, ichchan_init),
379 KOBJMETHOD(channel_setformat, ichchan_setformat),
380 KOBJMETHOD(channel_setspeed, ichchan_setspeed),
381 KOBJMETHOD(channel_setblocksize, ichchan_setblocksize),
382 KOBJMETHOD(channel_trigger, ichchan_trigger),
383 KOBJMETHOD(channel_getptr, ichchan_getptr),
384 KOBJMETHOD(channel_getcaps, ichchan_getcaps),
385 { 0, 0 }
386};
387CHANNEL_DECLARE(ichchan);
388
389/* -------------------------------------------------------------------- */
390/* The interrupt handler */
391
392static void
393ich_intr(void *p)
394{
395 struct sc_info *sc = (struct sc_info *)p;
396 struct sc_chinfo *ch;
397 u_int32_t cbi, lbi, lvi, st, gs;
398 int i;
399
400 gs = ich_rd(sc, ICH_REG_GLOB_STA, 4) & ICH_GLOB_STA_IMASK;
401 if (gs & (ICH_GLOB_STA_PRES | ICH_GLOB_STA_SRES)) {
402 /* Clear resume interrupt(s) - nothing doing with them */
403 ich_wr(sc, ICH_REG_GLOB_STA, gs, 4);
404 }
405 gs &= ~(ICH_GLOB_STA_PRES | ICH_GLOB_STA_SRES);
406
407 for (i = 0; i < 3; i++) {
408 ch = &sc->ch[i];
409 if ((ch->imask & gs) == 0)
410 continue;
411 gs &= ~ch->imask;
412 st = ich_rd(sc, ch->regbase +
413 (sc->swap_reg ? ICH_REG_X_PICB : ICH_REG_X_SR),
414 2);
415 st &= ICH_X_SR_FIFOE | ICH_X_SR_BCIS | ICH_X_SR_LVBCI;
416 if (st & (ICH_X_SR_BCIS | ICH_X_SR_LVBCI)) {
417 /* block complete - update buffer */
418 if (ch->run)
419 chn_intr(ch->channel);
420 lvi = ich_rd(sc, ch->regbase + ICH_REG_X_LVI, 1);
421 cbi = ch->civ % ch->blkcnt;
422 if (cbi == 0)
423 cbi = ch->blkcnt - 1;
424 else
425 cbi--;
426 lbi = lvi % ch->blkcnt;
427 if (cbi >= lbi)
428 lvi += cbi - lbi;
429 else
430 lvi += cbi + ch->blkcnt - lbi;
431 lvi %= ICH_DTBL_LENGTH;
432 ich_wr(sc, ch->regbase + ICH_REG_X_LVI, lvi, 1);
433
434 }
435 /* clear status bit */
436 ich_wr(sc, ch->regbase +
437 (sc->swap_reg ? ICH_REG_X_PICB : ICH_REG_X_SR),
438 st, 2);
439 }
440 if (gs != 0) {
441 device_printf(sc->dev,
442 "Unhandled interrupt, gs_intr = %x\n", gs);
443 }
444}
445
446/* ------------------------------------------------------------------------- */
447/* Sysctl to control ac97 speed (some boards appear to end up using
448 * XTAL_IN rather than BIT_CLK for link timing).
449 */
450
451static int
452ich_initsys(struct sc_info* sc)
453{
454#ifdef SND_DYNSYSCTL
455 SYSCTL_ADD_INT(snd_sysctl_tree(sc->dev),
456 SYSCTL_CHILDREN(snd_sysctl_tree_top(sc->dev)),
457 OID_AUTO, "ac97rate", CTLFLAG_RW,
458 &sc->ac97rate, 48000,
459 "AC97 link rate (default = 48000)");
460#endif /* SND_DYNSYSCTL */
461 return 0;
462}
463
464/* -------------------------------------------------------------------- */
465/* Calibrate card to determine the clock source. The source maybe a
466 * function of the ac97 codec initialization code (to be investigated).
467 */
468
469static
470void ich_calibrate(void *arg)
471{
472 struct sc_info *sc;
473 struct sc_chinfo *ch;
474 struct timeval t1, t2;
475 u_int8_t ociv, nciv;
476 u_int32_t wait_us, actual_48k_rate, bytes;
477
478 sc = (struct sc_info *)arg;
479 ch = &sc->ch[1];
480
481 if (sc->use_intrhook)
482 config_intrhook_disestablish(&sc->intrhook);
483
484 /*
485 * Grab audio from input for fixed interval and compare how
486 * much we actually get with what we expect. Interval needs
487 * to be sufficiently short that no interrupts are
488 * generated.
489 */
490
491 KASSERT(ch->regbase == ICH_REG_PI_BASE, ("wrong direction"));
492
493 bytes = sndbuf_getsize(ch->buffer) / 2;
494 ichchan_setblocksize(0, ch, bytes);
495
496 /*
497 * our data format is stereo, 16 bit so each sample is 4 bytes.
498 * assuming we get 48000 samples per second, we get 192000 bytes/sec.
499 * we're going to start recording with interrupts disabled and measure
500 * the time taken for one block to complete. we know the block size,
501 * we know the time in microseconds, we calculate the sample rate:
502 *
503 * actual_rate [bps] = bytes / (time [s] * 4)
504 * actual_rate [bps] = (bytes * 1000000) / (time [us] * 4)
505 * actual_rate [Hz] = (bytes * 250000) / time [us]
506 */
507
508 /* prepare */
509 ociv = ich_rd(sc, ch->regbase + ICH_REG_X_CIV, 1);
510 nciv = ociv;
511 ich_wr(sc, ch->regbase + ICH_REG_X_BDBAR, (u_int32_t)(ch->desc_addr), 4);
512
513 /* start */
514 microtime(&t1);
515 ich_wr(sc, ch->regbase + ICH_REG_X_CR, ICH_X_CR_RPBM, 1);
516
517 /* wait */
518 while (nciv == ociv) {
519 microtime(&t2);
520 if (t2.tv_sec - t1.tv_sec > 1)
521 break;
522 nciv = ich_rd(sc, ch->regbase + ICH_REG_X_CIV, 1);
523 }
524 microtime(&t2);
525
526 /* stop */
527 ich_wr(sc, ch->regbase + ICH_REG_X_CR, 0, 1);
528
529 /* reset */
530 DELAY(100);
531 ich_wr(sc, ch->regbase + ICH_REG_X_CR, ICH_X_CR_RR, 1);
532
533 /* turn time delta into us */
534 wait_us = ((t2.tv_sec - t1.tv_sec) * 1000000) + t2.tv_usec - t1.tv_usec;
535
536 if (nciv == ociv) {
537 device_printf(sc->dev, "ac97 link rate calibration timed out after %d us\n", wait_us);
538 return;
539 }
540
541 actual_48k_rate = (bytes * 250000) / wait_us;
542
543 if (actual_48k_rate < 47500 || actual_48k_rate > 48500) {
544 sc->ac97rate = actual_48k_rate;
545 } else {
546 sc->ac97rate = 48000;
547 }
548
549 if (bootverbose || sc->ac97rate != 48000) {
550 device_printf(sc->dev, "measured ac97 link rate at %d Hz", actual_48k_rate);
551 if (sc->ac97rate != actual_48k_rate)
552 printf(", will use %d Hz", sc->ac97rate);
553 printf("\n");
554 }
555
556 return;
557}
558
559/* -------------------------------------------------------------------- */
560/* Probe and attach the card */
561
562static void
563ich_setmap(void *arg, bus_dma_segment_t *segs, int nseg, int error)
564{
565 struct sc_info *sc = (struct sc_info *)arg;
566 sc->desc_addr = segs->ds_addr;
567 return;
568}
569
570static int
571ich_init(struct sc_info *sc)
572{
573 u_int32_t stat;
574 int sz;
575
576 ich_wr(sc, ICH_REG_GLOB_CNT, ICH_GLOB_CTL_COLD, 4);
577 DELAY(600000);
578 stat = ich_rd(sc, ICH_REG_GLOB_STA, 4);
579
580 if ((stat & ICH_GLOB_STA_PCR) == 0) {
581 /* ICH4/ICH5 may fail when busmastering is enabled. Continue */
582 if ((pci_get_devid(sc->dev) != ICH4ID) &&
583 (pci_get_devid(sc->dev) != ICH5ID)) {
584 return ENXIO;
585 }
586 }
587
588 ich_wr(sc, ICH_REG_GLOB_CNT, ICH_GLOB_CTL_COLD | ICH_GLOB_CTL_PRES, 4);
589
590 if (ich_resetchan(sc, 0) || ich_resetchan(sc, 1))
591 return ENXIO;
592 if (sc->hasmic && ich_resetchan(sc, 2))
593 return ENXIO;
594
595 if (bus_dmamem_alloc(sc->dmat, (void **)&sc->dtbl, BUS_DMA_NOWAIT, &sc->dtmap))
596 return ENOSPC;
597
598 sz = sizeof(struct ich_desc) * ICH_DTBL_LENGTH * 3;
599 if (bus_dmamap_load(sc->dmat, sc->dtmap, sc->dtbl, sz, ich_setmap, sc, 0)) {
600 bus_dmamem_free(sc->dmat, (void **)&sc->dtbl, sc->dtmap);
601 return ENOSPC;
602 }
603
604 return 0;
605}
606
607static int
608ich_pci_probe(device_t dev)
609{
610 switch(pci_get_devid(dev)) {
611 case 0x71958086:
612 device_set_desc(dev, "Intel 443MX");
613 return 0;
614
615 case 0x24158086:
616 device_set_desc(dev, "Intel ICH (82801AA)");
617 return 0;
618
619 case 0x24258086:
620 device_set_desc(dev, "Intel ICH (82801AB)");
621 return 0;
622
623 case 0x24458086:
624 device_set_desc(dev, "Intel ICH2 (82801BA)");
625 return 0;
626
627 case 0x24858086:
628 device_set_desc(dev, "Intel ICH3 (82801CA)");
629 return 0;
630
631 case ICH4ID:
632 device_set_desc(dev, "Intel ICH4 (82801DB)");
633 return -1000; /* allow a better driver to override us */
634
635 case ICH5ID:
636 device_set_desc(dev, "Intel ICH5 (82801EB)");
637 return -1000; /* allow a better driver to override us */
638
639 case SIS7012ID:
640 device_set_desc(dev, "SiS 7012");
641 return 0;
642
643 case 0x01b110de:
644 device_set_desc(dev, "Nvidia nForce");
645 return 0;
646
647 case 0x006a10de:
648 device_set_desc(dev, "Nvidia nForce2");
649 return 0;
650
651 case 0x00da10de:
652 device_set_desc(dev, "Nvidia nForce3");
653 return 0;
654
655 case 0x74451022:
656 device_set_desc(dev, "AMD-768");
657 return 0;
658
659 case 0x746d1022:
660 device_set_desc(dev, "AMD-8111");
661 return 0;
662
663 default:
664 return ENXIO;
665 }
666}
667
668static int
669ich_pci_attach(device_t dev)
670{
671 u_int16_t extcaps;
672 struct sc_info *sc;
673 char status[SND_STATUSLEN];
674
675 if ((sc = malloc(sizeof(*sc), M_DEVBUF, M_NOWAIT)) == NULL) {
676 device_printf(dev, "cannot allocate softc\n");
677 return ENXIO;
678 }
679
680 bzero(sc, sizeof(*sc));
681 sc->dev = dev;
682
683 /*
684 * The SiS 7012 register set isn't quite like the standard ich.
685 * There really should be a general "quirks" mechanism.
686 */
687 if (pci_get_devid(dev) == SIS7012ID) {
688 sc->swap_reg = 1;
689 sc->sample_size = 1;
690 } else {
691 sc->swap_reg = 0;
692 sc->sample_size = 2;
693 }
694
695 /*
696 * Enable bus master. On ich4/5 this may prevent the detection of
697 * the primary codec becoming ready in ich_init().
698 */
699 pci_enable_busmaster(dev);
700
701 if ((pci_get_devid(dev) == ICH4ID) || (pci_get_devid(dev) == ICH5ID)) {
702 sc->nambarid = PCIR_MMBAR;
703 sc->nabmbarid = PCIR_MBBAR;
704 sc->regtype = SYS_RES_MEMORY;
705 } else {
706 sc->nambarid = PCIR_NAMBAR;
707 sc->nabmbarid = PCIR_NABMBAR;
708 sc->regtype = SYS_RES_IOPORT;
709 }
710
711 sc->nambar = bus_alloc_resource(dev, sc->regtype, &sc->nambarid, 0, ~0, 1, RF_ACTIVE);
712 sc->nabmbar = bus_alloc_resource(dev, sc->regtype, &sc->nabmbarid, 0, ~0, 1, RF_ACTIVE);
713
714 if (!sc->nambar || !sc->nabmbar) {
715 device_printf(dev, "unable to map IO port space\n");
716 goto bad;
717 }
718
719 sc->nambart = rman_get_bustag(sc->nambar);
720 sc->nambarh = rman_get_bushandle(sc->nambar);
721 sc->nabmbart = rman_get_bustag(sc->nabmbar);
722 sc->nabmbarh = rman_get_bushandle(sc->nabmbar);
723
724 sc->bufsz = pcm_getbuffersize(dev, 4096, ICH_DEFAULT_BUFSZ, ICH_MAX_BUFSZ);
725 if (bus_dma_tag_create(NULL, 8, 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR,
726 NULL, NULL, sc->bufsz, 1, 0x3ffff, 0,
727 busdma_lock_mutex, &Giant, &sc->dmat) != 0) {
728 device_printf(dev, "unable to create dma tag\n");
729 goto bad;
730 }
731
732 sc->irqid = 0;
733 sc->irq = bus_alloc_resource(dev, SYS_RES_IRQ, &sc->irqid, 0, ~0, 1, RF_ACTIVE | RF_SHAREABLE);
734 if (!sc->irq || snd_setup_intr(dev, sc->irq, INTR_MPSAFE, ich_intr, sc, &sc->ih)) {
735 device_printf(dev, "unable to map interrupt\n");
736 goto bad;
737 }
738
739 if (ich_init(sc)) {
740 device_printf(dev, "unable to initialize the card\n");
741 goto bad;
742 }
743
744 sc->codec = AC97_CREATE(dev, sc, ich_ac97);
745 if (sc->codec == NULL)
746 goto bad;
747 mixer_init(dev, ac97_getmixerclass(), sc->codec);
748
749 /* check and set VRA function */
750 extcaps = ac97_getextcaps(sc->codec);
751 sc->hasvra = extcaps & AC97_EXTCAP_VRA;
752 sc->hasvrm = extcaps & AC97_EXTCAP_VRM;
753 sc->hasmic = ac97_getcaps(sc->codec) & AC97_CAP_MICCHANNEL;
754 ac97_setextmode(sc->codec, sc->hasvra | sc->hasvrm);
755
756 if (pcm_register(dev, sc, 1, sc->hasmic? 2 : 1))
757 goto bad;
758
759 pcm_addchan(dev, PCMDIR_PLAY, &ichchan_class, sc); /* play */
760 pcm_addchan(dev, PCMDIR_REC, &ichchan_class, sc); /* record */
761 if (sc->hasmic)
762 pcm_addchan(dev, PCMDIR_REC, &ichchan_class, sc); /* record mic */
763
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766
767 pcm_setstatus(dev, status);
768
769 ich_initsys(sc);
770
771 sc->intrhook.ich_func = ich_calibrate;
772 sc->intrhook.ich_arg = sc;
773 sc->use_intrhook = 1;
774 if (config_intrhook_establish(&sc->intrhook) != 0) {
775 device_printf(dev, "Cannot establish calibration hook, will calibrate now\n");
776 sc->use_intrhook = 0;
777 ich_calibrate(sc);
778 }
779
780 return 0;
781
782bad:
783 if (sc->codec)
784 ac97_destroy(sc->codec);
785 if (sc->ih)
786 bus_teardown_intr(dev, sc->irq, sc->ih);
787 if (sc->irq)
788 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq);
789 if (sc->nambar)
790 bus_release_resource(dev, sc->regtype,
791 sc->nambarid, sc->nambar);
792 if (sc->nabmbar)
793 bus_release_resource(dev, sc->regtype,
794 sc->nabmbarid, sc->nabmbar);
795 free(sc, M_DEVBUF);
796 return ENXIO;
797}
798
799static int
800ich_pci_detach(device_t dev)
801{
802 struct sc_info *sc;
803 int r;
804
805 r = pcm_unregister(dev);
806 if (r)
807 return r;
808 sc = pcm_getdevinfo(dev);
809
810 bus_teardown_intr(dev, sc->irq, sc->ih);
811 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq);
812 bus_release_resource(dev, sc->regtype, sc->nambarid, sc->nambar);
813 bus_release_resource(dev, sc->regtype, sc->nabmbarid, sc->nabmbar);
814 bus_dma_tag_destroy(sc->dmat);
815 free(sc, M_DEVBUF);
816 return 0;
817}
818
819static void
820ich_pci_codec_reset(struct sc_info *sc)
821{
822 int i;
823 uint32_t control;
824
825 control = ich_rd(sc, ICH_REG_GLOB_CNT, 4);
826 control &= ~(ICH_GLOB_CTL_SHUT);
827 control |= (control & ICH_GLOB_CTL_COLD) ?
828 ICH_GLOB_CTL_WARM : ICH_GLOB_CTL_COLD;
829 ich_wr(sc, ICH_REG_GLOB_CNT, control, 4);
830
831 for (i = 500000; i; i--) {
832 if (ich_rd(sc, ICH_REG_GLOB_STA, 4) & ICH_GLOB_STA_PCR)
833 break; /* or ICH_SCR? */
834 DELAY(1);
835 }
836
837 if (i <= 0)
838 printf("%s: time out\n", __func__);
839}
840
841static int
842ich_pci_suspend(device_t dev)
843{
844 struct sc_info *sc;
845 int i;
846
847 sc = pcm_getdevinfo(dev);
848 for (i = 0 ; i < 3; i++) {
849 sc->ch[i].run_save = sc->ch[i].run;
850 if (sc->ch[i].run) {
851 ichchan_trigger(0, &sc->ch[i], PCMTRIG_ABORT);
852 }
853 }
854 return 0;
855}
856
857static int
858ich_pci_resume(device_t dev)
859{
860 struct sc_info *sc;
861 int i;
862
863 sc = pcm_getdevinfo(dev);
864
865 if (sc->regtype == SYS_RES_IOPORT)
866 pci_enable_io(dev, SYS_RES_IOPORT);
867 else
868 pci_enable_io(dev, SYS_RES_MEMORY);
869 pci_enable_busmaster(dev);
870
871 /* Reinit audio device */
872 if (ich_init(sc) == -1) {
873 device_printf(dev, "unable to reinitialize the card\n");
874 return ENXIO;
875 }
876 /* Reinit mixer */
877 ich_pci_codec_reset(sc);
878 ac97_setextmode(sc->codec, sc->hasvra | sc->hasvrm);
879 if (mixer_reinit(dev) == -1) {
880 device_printf(dev, "unable to reinitialize the mixer\n");
881 return ENXIO;
882 }
883 /* Re-start DMA engines */
884 for (i = 0 ; i < 3; i++) {
885 struct sc_chinfo *ch = &sc->ch[i];
886 if (sc->ch[i].run_save) {
887 ichchan_setblocksize(0, ch, ch->blksz);
888 ichchan_setspeed(0, ch, ch->spd);
889 ichchan_trigger(0, ch, PCMTRIG_START);
890 }
891 }
892 return 0;
893}
894
895static device_method_t ich_methods[] = {
896 /* Device interface */
897 DEVMETHOD(device_probe, ich_pci_probe),
898 DEVMETHOD(device_attach, ich_pci_attach),
899 DEVMETHOD(device_detach, ich_pci_detach),
900 DEVMETHOD(device_suspend, ich_pci_suspend),
901 DEVMETHOD(device_resume, ich_pci_resume),
902 { 0, 0 }
903};
904
905static driver_t ich_driver = {
906 "pcm",
907 ich_methods,
908 PCM_SOFTC_SIZE,
909};
910
911DRIVER_MODULE(snd_ich, pci, ich_driver, pcm_devclass, 0, 0);
912MODULE_DEPEND(snd_ich, snd_pcm, PCM_MINVER, PCM_PREFVER, PCM_MAXVER);
913MODULE_VERSION(snd_ich, 1);
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