87
88#define HDA_BOOTVERBOSE(stmt) do { \
89 if (bootverbose != 0 || snd_verbose > 3) { \
90 stmt \
91 } \
92} while(0)
93
94#if 1
95#undef HDAC_INTR_EXTRA
96#define HDAC_INTR_EXTRA 1
97#endif
98
99#define hdac_lock(sc) snd_mtxlock((sc)->lock)
100#define hdac_unlock(sc) snd_mtxunlock((sc)->lock)
101#define hdac_lockassert(sc) snd_mtxassert((sc)->lock)
102#define hdac_lockowned(sc) mtx_owned((sc)->lock)
103
104#define HDA_FLAG_MATCH(fl, v) (((fl) & (v)) == (v))
105#define HDA_DEV_MATCH(fl, v) ((fl) == (v) || \
106 (fl) == 0xffffffff || \
107 (((fl) & 0xffff0000) == 0xffff0000 && \
108 ((fl) & 0x0000ffff) == ((v) & 0x0000ffff)) || \
109 (((fl) & 0x0000ffff) == 0x0000ffff && \
110 ((fl) & 0xffff0000) == ((v) & 0xffff0000)))
111#define HDA_MATCH_ALL 0xffffffff
112#define HDAC_INVALID 0xffffffff
113
114/* Default controller / jack sense poll: 250ms */
115#define HDAC_POLL_INTERVAL max(hz >> 2, 1)
116
117#define HDA_MODEL_CONSTRUCT(vendor, model) \
118 (((uint32_t)(model) << 16) | ((vendor##_VENDORID) & 0xffff))
119
120/* Controller models */
121
122/* Intel */
123#define INTEL_VENDORID 0x8086
124#define HDA_INTEL_82801F HDA_MODEL_CONSTRUCT(INTEL, 0x2668)
125#define HDA_INTEL_82801G HDA_MODEL_CONSTRUCT(INTEL, 0x27d8)
126#define HDA_INTEL_82801H HDA_MODEL_CONSTRUCT(INTEL, 0x284b)
127#define HDA_INTEL_63XXESB HDA_MODEL_CONSTRUCT(INTEL, 0x269a)
128#define HDA_INTEL_ALL HDA_MODEL_CONSTRUCT(INTEL, 0xffff)
129
130/* Nvidia */
131#define NVIDIA_VENDORID 0x10de
132#define HDA_NVIDIA_MCP51 HDA_MODEL_CONSTRUCT(NVIDIA, 0x026c)
133#define HDA_NVIDIA_MCP55 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0371)
134#define HDA_NVIDIA_MCP61A HDA_MODEL_CONSTRUCT(NVIDIA, 0x03e4)
135#define HDA_NVIDIA_MCP61B HDA_MODEL_CONSTRUCT(NVIDIA, 0x03f0)
136#define HDA_NVIDIA_MCP65A HDA_MODEL_CONSTRUCT(NVIDIA, 0x044a)
137#define HDA_NVIDIA_MCP65B HDA_MODEL_CONSTRUCT(NVIDIA, 0x044b)
138#define HDA_NVIDIA_ALL HDA_MODEL_CONSTRUCT(NVIDIA, 0xffff)
139
140/* ATI */
141#define ATI_VENDORID 0x1002
142#define HDA_ATI_SB450 HDA_MODEL_CONSTRUCT(ATI, 0x437b)
143#define HDA_ATI_SB600 HDA_MODEL_CONSTRUCT(ATI, 0x4383)
144#define HDA_ATI_ALL HDA_MODEL_CONSTRUCT(ATI, 0xffff)
145
146/* VIA */
147#define VIA_VENDORID 0x1106
148#define HDA_VIA_VT82XX HDA_MODEL_CONSTRUCT(VIA, 0x3288)
149#define HDA_VIA_ALL HDA_MODEL_CONSTRUCT(VIA, 0xffff)
150
151/* SiS */
152#define SIS_VENDORID 0x1039
153#define HDA_SIS_966 HDA_MODEL_CONSTRUCT(SIS, 0x7502)
154#define HDA_SIS_ALL HDA_MODEL_CONSTRUCT(SIS, 0xffff)
155
156/* OEM/subvendors */
157
158/* Intel */
159#define INTEL_D101GGC_SUBVENDOR HDA_MODEL_CONSTRUCT(INTEL, 0xd600)
160
161/* HP/Compaq */
162#define HP_VENDORID 0x103c
163#define HP_V3000_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30b5)
164#define HP_NX7400_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30a2)
165#define HP_NX6310_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30aa)
166#define HP_NX6325_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30b0)
167#define HP_XW4300_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x3013)
168#define HP_3010_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x3010)
169#define HP_DV5000_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30a5)
170#define HP_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0xffff)
171/* What is wrong with XN 2563 anyway? (Got the picture ?) */
172#define HP_NX6325_SUBVENDORX 0x103c30b0
173
174/* Dell */
175#define DELL_VENDORID 0x1028
176#define DELL_D820_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01cc)
177#define DELL_I1300_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01c9)
178#define DELL_XPSM1210_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01d7)
179#define DELL_OPLX745_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01da)
180#define DELL_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0xffff)
181
182/* Clevo */
183#define CLEVO_VENDORID 0x1558
184#define CLEVO_D900T_SUBVENDOR HDA_MODEL_CONSTRUCT(CLEVO, 0x0900)
185#define CLEVO_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(CLEVO, 0xffff)
186
187/* Acer */
188#define ACER_VENDORID 0x1025
189#define ACER_A5050_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x010f)
190#define ACER_3681WXM_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x0110)
191#define ACER_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0xffff)
192
193/* Asus */
194#define ASUS_VENDORID 0x1043
195#define ASUS_M5200_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1993)
196#define ASUS_U5F_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1263)
197#define ASUS_A8JC_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1153)
198#define ASUS_P1AH2_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81cb)
199#define ASUS_A7M_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1323)
200#define ASUS_A7T_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x13c2)
201#define ASUS_W6F_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1263)
202#define ASUS_W2J_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1971)
203#define ASUS_F3JC_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1338)
204#define ASUS_M2V_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81e7)
205#define ASUS_M2N_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x8234)
206#define ASUS_M2NPVMX_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81cb)
207#define ASUS_P5BWD_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81ec)
208#define ASUS_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0xffff)
209
210/* IBM / Lenovo */
211#define IBM_VENDORID 0x1014
212#define IBM_M52_SUBVENDOR HDA_MODEL_CONSTRUCT(IBM, 0x02f6)
213#define IBM_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(IBM, 0xffff)
214
215/* Lenovo */
216#define LENOVO_VENDORID 0x17aa
217#define LENOVO_3KN100_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0x2066)
218#define LENOVO_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0xffff)
219
220/* Samsung */
221#define SAMSUNG_VENDORID 0x144d
222#define SAMSUNG_Q1_SUBVENDOR HDA_MODEL_CONSTRUCT(SAMSUNG, 0xc027)
223#define SAMSUNG_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(SAMSUNG, 0xffff)
224
225/* Medion ? */
226#define MEDION_VENDORID 0x161f
227#define MEDION_MD95257_SUBVENDOR HDA_MODEL_CONSTRUCT(MEDION, 0x203d)
228#define MEDION_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(MEDION, 0xffff)
229
230/*
231 * Apple Intel MacXXXX seems using Sigmatel codec/vendor id
232 * instead of their own, which is beyond my comprehension
233 * (see HDA_CODEC_STAC9221 below).
234 */
235#define APPLE_INTEL_MAC 0x76808384
236
237/* LG Electronics */
238#define LG_VENDORID 0x1854
239#define LG_LW20_SUBVENDOR HDA_MODEL_CONSTRUCT(LG, 0x0018)
240#define LG_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(LG, 0xffff)
241
242/* Fujitsu Siemens */
243#define FS_VENDORID 0x1734
244#define FS_PA1510_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0x10b8)
245#define FS_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0xffff)
246
247/* Toshiba */
248#define TOSHIBA_VENDORID 0x1179
249#define TOSHIBA_U200_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0x0001)
250#define TOSHIBA_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0xffff)
251
252/* Micro-Star International (MSI) */
253#define MSI_VENDORID 0x1462
254#define MSI_MS1034_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0x0349)
255#define MSI_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0xffff)
256
257/* Uniwill ? */
258#define UNIWILL_VENDORID 0x1584
259#define UNIWILL_9075_SUBVENDOR HDA_MODEL_CONSTRUCT(UNIWILL, 0x9075)
260
261
262/* Misc constants.. */
263#define HDA_AMP_MUTE_DEFAULT (0xffffffff)
264#define HDA_AMP_MUTE_NONE (0)
265#define HDA_AMP_MUTE_LEFT (1 << 0)
266#define HDA_AMP_MUTE_RIGHT (1 << 1)
267#define HDA_AMP_MUTE_ALL (HDA_AMP_MUTE_LEFT | HDA_AMP_MUTE_RIGHT)
268
269#define HDA_AMP_LEFT_MUTED(v) ((v) & (HDA_AMP_MUTE_LEFT))
270#define HDA_AMP_RIGHT_MUTED(v) (((v) & HDA_AMP_MUTE_RIGHT) >> 1)
271
272#define HDA_DAC_PATH (1 << 0)
273#define HDA_ADC_PATH (1 << 1)
274#define HDA_ADC_RECSEL (1 << 2)
275
276#define HDA_DAC_LOCKED (1 << 3)
277#define HDA_ADC_LOCKED (1 << 4)
278
279#define HDA_CTL_OUT (1 << 0)
280#define HDA_CTL_IN (1 << 1)
281#define HDA_CTL_BOTH (HDA_CTL_IN | HDA_CTL_OUT)
282
283#define HDA_GPIO_MAX 8
284/* 0 - 7 = GPIO , 8 = Flush */
285#define HDA_QUIRK_GPIO0 (1 << 0)
286#define HDA_QUIRK_GPIO1 (1 << 1)
287#define HDA_QUIRK_GPIO2 (1 << 2)
288#define HDA_QUIRK_GPIO3 (1 << 3)
289#define HDA_QUIRK_GPIO4 (1 << 4)
290#define HDA_QUIRK_GPIO5 (1 << 5)
291#define HDA_QUIRK_GPIO6 (1 << 6)
292#define HDA_QUIRK_GPIO7 (1 << 7)
293#define HDA_QUIRK_GPIOFLUSH (1 << 8)
294
295/* 9 - 25 = anything else */
296#define HDA_QUIRK_SOFTPCMVOL (1 << 9)
297#define HDA_QUIRK_FIXEDRATE (1 << 10)
298#define HDA_QUIRK_FORCESTEREO (1 << 11)
299#define HDA_QUIRK_EAPDINV (1 << 12)
300#define HDA_QUIRK_DMAPOS (1 << 13)
301
302/* 26 - 31 = vrefs */
303#define HDA_QUIRK_IVREF50 (1 << 26)
304#define HDA_QUIRK_IVREF80 (1 << 27)
305#define HDA_QUIRK_IVREF100 (1 << 28)
306#define HDA_QUIRK_OVREF50 (1 << 29)
307#define HDA_QUIRK_OVREF80 (1 << 30)
308#define HDA_QUIRK_OVREF100 (1 << 31)
309
310#define HDA_QUIRK_IVREF (HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF80 | \
311 HDA_QUIRK_IVREF100)
312#define HDA_QUIRK_OVREF (HDA_QUIRK_OVREF50 | HDA_QUIRK_OVREF80 | \
313 HDA_QUIRK_OVREF100)
314#define HDA_QUIRK_VREF (HDA_QUIRK_IVREF | HDA_QUIRK_OVREF)
315
316#define SOUND_MASK_SKIP (1 << 30)
317#define SOUND_MASK_DISABLE (1 << 31)
318
319static const struct {
320 char *key;
321 uint32_t value;
322} hdac_quirks_tab[] = {
323 { "gpio0", HDA_QUIRK_GPIO0 },
324 { "gpio1", HDA_QUIRK_GPIO1 },
325 { "gpio2", HDA_QUIRK_GPIO2 },
326 { "gpio3", HDA_QUIRK_GPIO3 },
327 { "gpio4", HDA_QUIRK_GPIO4 },
328 { "gpio5", HDA_QUIRK_GPIO5 },
329 { "gpio6", HDA_QUIRK_GPIO6 },
330 { "gpio7", HDA_QUIRK_GPIO7 },
331 { "gpioflush", HDA_QUIRK_GPIOFLUSH },
332 { "softpcmvol", HDA_QUIRK_SOFTPCMVOL },
333 { "fixedrate", HDA_QUIRK_FIXEDRATE },
334 { "forcestereo", HDA_QUIRK_FORCESTEREO },
335 { "eapdinv", HDA_QUIRK_EAPDINV },
336 { "dmapos", HDA_QUIRK_DMAPOS },
337 { "ivref50", HDA_QUIRK_IVREF50 },
338 { "ivref80", HDA_QUIRK_IVREF80 },
339 { "ivref100", HDA_QUIRK_IVREF100 },
340 { "ovref50", HDA_QUIRK_OVREF50 },
341 { "ovref80", HDA_QUIRK_OVREF80 },
342 { "ovref100", HDA_QUIRK_OVREF100 },
343 { "ivref", HDA_QUIRK_IVREF },
344 { "ovref", HDA_QUIRK_OVREF },
345 { "vref", HDA_QUIRK_VREF },
346};
347#define HDAC_QUIRKS_TAB_LEN \
348 (sizeof(hdac_quirks_tab) / sizeof(hdac_quirks_tab[0]))
349
350#define HDA_BDL_MIN 2
351#define HDA_BDL_MAX 256
352#define HDA_BDL_DEFAULT HDA_BDL_MIN
353
354#define HDA_BLK_MIN HDAC_DMA_ALIGNMENT
355#define HDA_BLK_ALIGN (~(HDA_BLK_MIN - 1))
356
357#define HDA_BUFSZ_MIN 4096
358#define HDA_BUFSZ_MAX 65536
359#define HDA_BUFSZ_DEFAULT 16384
360
361#define HDA_PARSE_MAXDEPTH 10
362
363#define HDAC_UNSOLTAG_EVENT_HP 0x00
364#define HDAC_UNSOLTAG_EVENT_TEST 0x01
365
366MALLOC_DEFINE(M_HDAC, "hdac", "High Definition Audio Controller");
367
368enum {
369 HDA_PARSE_MIXER,
370 HDA_PARSE_DIRECT
371};
372
373/* Default */
374static uint32_t hdac_fmt[] = {
375 AFMT_STEREO | AFMT_S16_LE,
376 0
377};
378
379static struct pcmchan_caps hdac_caps = {48000, 48000, hdac_fmt, 0};
380
381static const struct {
382 uint32_t model;
383 char *desc;
384} hdac_devices[] = {
385 { HDA_INTEL_82801F, "Intel 82801F" },
386 { HDA_INTEL_82801G, "Intel 82801G" },
387 { HDA_INTEL_82801H, "Intel 82801H" },
388 { HDA_INTEL_63XXESB, "Intel 631x/632xESB" },
389 { HDA_NVIDIA_MCP51, "NVidia MCP51" },
390 { HDA_NVIDIA_MCP55, "NVidia MCP55" },
391 { HDA_NVIDIA_MCP61A, "NVidia MCP61A" },
392 { HDA_NVIDIA_MCP61B, "NVidia MCP61B" },
393 { HDA_NVIDIA_MCP65A, "NVidia MCP65A" },
394 { HDA_NVIDIA_MCP65B, "NVidia MCP65B" },
395 { HDA_ATI_SB450, "ATI SB450" },
396 { HDA_ATI_SB600, "ATI SB600" },
397 { HDA_VIA_VT82XX, "VIA VT8251/8237A" },
398 { HDA_SIS_966, "SiS 966" },
399 /* Unknown */
400 { HDA_INTEL_ALL, "Intel (Unknown)" },
401 { HDA_NVIDIA_ALL, "NVidia (Unknown)" },
402 { HDA_ATI_ALL, "ATI (Unknown)" },
403 { HDA_VIA_ALL, "VIA (Unknown)" },
404 { HDA_SIS_ALL, "SiS (Unknown)" },
405};
406#define HDAC_DEVICES_LEN (sizeof(hdac_devices) / sizeof(hdac_devices[0]))
407
408static const struct {
409 uint16_t vendor;
410 uint8_t reg;
411 uint8_t mask;
412 uint8_t enable;
413} hdac_pcie_snoop[] = {
414 { INTEL_VENDORID, 0x00, 0x00, 0x00 },
415 { ATI_VENDORID, 0x42, 0xf8, 0x02 },
416 { NVIDIA_VENDORID, 0x4e, 0xf0, 0x0f },
417};
418#define HDAC_PCIESNOOP_LEN \
419 (sizeof(hdac_pcie_snoop) / sizeof(hdac_pcie_snoop[0]))
420
421static const struct {
422 uint32_t rate;
423 int valid;
424 uint16_t base;
425 uint16_t mul;
426 uint16_t div;
427} hda_rate_tab[] = {
428 { 8000, 1, 0x0000, 0x0000, 0x0500 }, /* (48000 * 1) / 6 */
429 { 9600, 0, 0x0000, 0x0000, 0x0400 }, /* (48000 * 1) / 5 */
430 { 12000, 0, 0x0000, 0x0000, 0x0300 }, /* (48000 * 1) / 4 */
431 { 16000, 1, 0x0000, 0x0000, 0x0200 }, /* (48000 * 1) / 3 */
432 { 18000, 0, 0x0000, 0x1000, 0x0700 }, /* (48000 * 3) / 8 */
433 { 19200, 0, 0x0000, 0x0800, 0x0400 }, /* (48000 * 2) / 5 */
434 { 24000, 0, 0x0000, 0x0000, 0x0100 }, /* (48000 * 1) / 2 */
435 { 28800, 0, 0x0000, 0x1000, 0x0400 }, /* (48000 * 3) / 5 */
436 { 32000, 1, 0x0000, 0x0800, 0x0200 }, /* (48000 * 2) / 3 */
437 { 36000, 0, 0x0000, 0x1000, 0x0300 }, /* (48000 * 3) / 4 */
438 { 38400, 0, 0x0000, 0x1800, 0x0400 }, /* (48000 * 4) / 5 */
439 { 48000, 1, 0x0000, 0x0000, 0x0000 }, /* (48000 * 1) / 1 */
440 { 64000, 0, 0x0000, 0x1800, 0x0200 }, /* (48000 * 4) / 3 */
441 { 72000, 0, 0x0000, 0x1000, 0x0100 }, /* (48000 * 3) / 2 */
442 { 96000, 1, 0x0000, 0x0800, 0x0000 }, /* (48000 * 2) / 1 */
443 { 144000, 0, 0x0000, 0x1000, 0x0000 }, /* (48000 * 3) / 1 */
444 { 192000, 1, 0x0000, 0x1800, 0x0000 }, /* (48000 * 4) / 1 */
445 { 8820, 0, 0x4000, 0x0000, 0x0400 }, /* (44100 * 1) / 5 */
446 { 11025, 1, 0x4000, 0x0000, 0x0300 }, /* (44100 * 1) / 4 */
447 { 12600, 0, 0x4000, 0x0800, 0x0600 }, /* (44100 * 2) / 7 */
448 { 14700, 0, 0x4000, 0x0000, 0x0200 }, /* (44100 * 1) / 3 */
449 { 17640, 0, 0x4000, 0x0800, 0x0400 }, /* (44100 * 2) / 5 */
450 { 18900, 0, 0x4000, 0x1000, 0x0600 }, /* (44100 * 3) / 7 */
451 { 22050, 1, 0x4000, 0x0000, 0x0100 }, /* (44100 * 1) / 2 */
452 { 25200, 0, 0x4000, 0x1800, 0x0600 }, /* (44100 * 4) / 7 */
453 { 26460, 0, 0x4000, 0x1000, 0x0400 }, /* (44100 * 3) / 5 */
454 { 29400, 0, 0x4000, 0x0800, 0x0200 }, /* (44100 * 2) / 3 */
455 { 33075, 0, 0x4000, 0x1000, 0x0300 }, /* (44100 * 3) / 4 */
456 { 35280, 0, 0x4000, 0x1800, 0x0400 }, /* (44100 * 4) / 5 */
457 { 44100, 1, 0x4000, 0x0000, 0x0000 }, /* (44100 * 1) / 1 */
458 { 58800, 0, 0x4000, 0x1800, 0x0200 }, /* (44100 * 4) / 3 */
459 { 66150, 0, 0x4000, 0x1000, 0x0100 }, /* (44100 * 3) / 2 */
460 { 88200, 1, 0x4000, 0x0800, 0x0000 }, /* (44100 * 2) / 1 */
461 { 132300, 0, 0x4000, 0x1000, 0x0000 }, /* (44100 * 3) / 1 */
462 { 176400, 1, 0x4000, 0x1800, 0x0000 }, /* (44100 * 4) / 1 */
463};
464#define HDA_RATE_TAB_LEN (sizeof(hda_rate_tab) / sizeof(hda_rate_tab[0]))
465
466/* All codecs you can eat... */
467#define HDA_CODEC_CONSTRUCT(vendor, id) \
468 (((uint32_t)(vendor##_VENDORID) << 16) | ((id) & 0xffff))
469
470/* Realtek */
471#define REALTEK_VENDORID 0x10ec
472#define HDA_CODEC_ALC260 HDA_CODEC_CONSTRUCT(REALTEK, 0x0260)
473#define HDA_CODEC_ALC262 HDA_CODEC_CONSTRUCT(REALTEK, 0x0262)
474#define HDA_CODEC_ALC660 HDA_CODEC_CONSTRUCT(REALTEK, 0x0660)
475#define HDA_CODEC_ALC861 HDA_CODEC_CONSTRUCT(REALTEK, 0x0861)
476#define HDA_CODEC_ALC861VD HDA_CODEC_CONSTRUCT(REALTEK, 0x0862)
477#define HDA_CODEC_ALC880 HDA_CODEC_CONSTRUCT(REALTEK, 0x0880)
478#define HDA_CODEC_ALC882 HDA_CODEC_CONSTRUCT(REALTEK, 0x0882)
479#define HDA_CODEC_ALC883 HDA_CODEC_CONSTRUCT(REALTEK, 0x0883)
480#define HDA_CODEC_ALC885 HDA_CODEC_CONSTRUCT(REALTEK, 0x0885)
481#define HDA_CODEC_ALC888 HDA_CODEC_CONSTRUCT(REALTEK, 0x0888)
482#define HDA_CODEC_ALCXXXX HDA_CODEC_CONSTRUCT(REALTEK, 0xffff)
483
484/* Analog Devices */
485#define ANALOGDEVICES_VENDORID 0x11d4
486#define HDA_CODEC_AD1981HD HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1981)
487#define HDA_CODEC_AD1983 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1983)
488#define HDA_CODEC_AD1986A HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1986)
489#define HDA_CODEC_AD1988 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1988)
490#define HDA_CODEC_AD1988B HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x198b)
491#define HDA_CODEC_ADXXXX HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0xffff)
492
493/* CMedia */
494#define CMEDIA_VENDORID 0x434d
495#define HDA_CODEC_CMI9880 HDA_CODEC_CONSTRUCT(CMEDIA, 0x4980)
496#define HDA_CODEC_CMIXXXX HDA_CODEC_CONSTRUCT(CMEDIA, 0xffff)
497
498/* Sigmatel */
499#define SIGMATEL_VENDORID 0x8384
500#define HDA_CODEC_STAC9221 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7680)
501#define HDA_CODEC_STAC9221D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7683)
502#define HDA_CODEC_STAC9220 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7690)
503#define HDA_CODEC_STAC922XD HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7681)
504#define HDA_CODEC_STAC9227 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7618)
505#define HDA_CODEC_STAC9271D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7627)
506#define HDA_CODEC_STACXXXX HDA_CODEC_CONSTRUCT(SIGMATEL, 0xffff)
507
508/*
509 * Conexant
510 *
511 * Ok, the truth is, I don't have any idea at all whether
512 * it is "Venice" or "Waikiki" or other unnamed CXyadayada. The only
513 * place that tell me it is "Venice" is from its Windows driver INF.
514 *
515 * Venice - CX?????
516 * Waikiki - CX20551-22
517 */
518#define CONEXANT_VENDORID 0x14f1
519#define HDA_CODEC_CXVENICE HDA_CODEC_CONSTRUCT(CONEXANT, 0x5045)
520#define HDA_CODEC_CXWAIKIKI HDA_CODEC_CONSTRUCT(CONEXANT, 0x5047)
521#define HDA_CODEC_CXXXXX HDA_CODEC_CONSTRUCT(CONEXANT, 0xffff)
522
523/* VIA */
524#define HDA_CODEC_VT1708_8 HDA_CODEC_CONSTRUCT(VIA, 0x1708)
525#define HDA_CODEC_VT1708_9 HDA_CODEC_CONSTRUCT(VIA, 0x1709)
526#define HDA_CODEC_VT1708_A HDA_CODEC_CONSTRUCT(VIA, 0x170a)
527#define HDA_CODEC_VT1708_B HDA_CODEC_CONSTRUCT(VIA, 0x170b)
528#define HDA_CODEC_VT1709_0 HDA_CODEC_CONSTRUCT(VIA, 0xe710)
529#define HDA_CODEC_VT1709_1 HDA_CODEC_CONSTRUCT(VIA, 0xe711)
530#define HDA_CODEC_VT1709_2 HDA_CODEC_CONSTRUCT(VIA, 0xe712)
531#define HDA_CODEC_VT1709_3 HDA_CODEC_CONSTRUCT(VIA, 0xe713)
532#define HDA_CODEC_VT1709_4 HDA_CODEC_CONSTRUCT(VIA, 0xe714)
533#define HDA_CODEC_VT1709_5 HDA_CODEC_CONSTRUCT(VIA, 0xe715)
534#define HDA_CODEC_VT1709_6 HDA_CODEC_CONSTRUCT(VIA, 0xe716)
535#define HDA_CODEC_VT1709_7 HDA_CODEC_CONSTRUCT(VIA, 0xe717)
536#define HDA_CODEC_VTXXXX HDA_CODEC_CONSTRUCT(VIA, 0xffff)
537
538
539/* Codecs */
540static const struct {
541 uint32_t id;
542 char *name;
543} hdac_codecs[] = {
544 { HDA_CODEC_ALC260, "Realtek ALC260" },
545 { HDA_CODEC_ALC262, "Realtek ALC262" },
546 { HDA_CODEC_ALC660, "Realtek ALC660" },
547 { HDA_CODEC_ALC861, "Realtek ALC861" },
548 { HDA_CODEC_ALC861VD, "Realtek ALC861-VD" },
549 { HDA_CODEC_ALC880, "Realtek ALC880" },
550 { HDA_CODEC_ALC882, "Realtek ALC882" },
551 { HDA_CODEC_ALC883, "Realtek ALC883" },
552 { HDA_CODEC_ALC885, "Realtek ALC885" },
553 { HDA_CODEC_ALC888, "Realtek ALC888" },
554 { HDA_CODEC_AD1981HD, "Analog Devices AD1981HD" },
555 { HDA_CODEC_AD1983, "Analog Devices AD1983" },
556 { HDA_CODEC_AD1986A, "Analog Devices AD1986A" },
557 { HDA_CODEC_AD1988, "Analog Devices AD1988" },
558 { HDA_CODEC_AD1988B, "Analog Devices AD1988B" },
559 { HDA_CODEC_CMI9880, "CMedia CMI9880" },
560 { HDA_CODEC_STAC9221, "Sigmatel STAC9221" },
561 { HDA_CODEC_STAC9221D, "Sigmatel STAC9221D" },
562 { HDA_CODEC_STAC9220, "Sigmatel STAC9220" },
563 { HDA_CODEC_STAC922XD, "Sigmatel STAC9220D/9223D" },
564 { HDA_CODEC_STAC9227, "Sigmatel STAC9227" },
565 { HDA_CODEC_STAC9271D, "Sigmatel STAC9271D" },
566 { HDA_CODEC_CXVENICE, "Conexant Venice" },
567 { HDA_CODEC_CXWAIKIKI, "Conexant Waikiki" },
568 { HDA_CODEC_VT1708_8, "VIA VT1708_8" },
569 { HDA_CODEC_VT1708_9, "VIA VT1708_9" },
570 { HDA_CODEC_VT1708_A, "VIA VT1708_A" },
571 { HDA_CODEC_VT1708_B, "VIA VT1708_B" },
572 { HDA_CODEC_VT1709_0, "VIA VT1709_0" },
573 { HDA_CODEC_VT1709_1, "VIA VT1709_1" },
574 { HDA_CODEC_VT1709_2, "VIA VT1709_2" },
575 { HDA_CODEC_VT1709_3, "VIA VT1709_3" },
576 { HDA_CODEC_VT1709_4, "VIA VT1709_4" },
577 { HDA_CODEC_VT1709_5, "VIA VT1709_5" },
578 { HDA_CODEC_VT1709_6, "VIA VT1709_6" },
579 { HDA_CODEC_VT1709_7, "VIA VT1709_7" },
580 /* Unknown codec */
581 { HDA_CODEC_ALCXXXX, "Realtek (Unknown)" },
582 { HDA_CODEC_ADXXXX, "Analog Devices (Unknown)" },
583 { HDA_CODEC_CMIXXXX, "CMedia (Unknown)" },
584 { HDA_CODEC_STACXXXX, "Sigmatel (Unknown)" },
585 { HDA_CODEC_CXXXXX, "Conexant (Unknown)" },
586 { HDA_CODEC_VTXXXX, "VIA (Unknown)" },
587};
588#define HDAC_CODECS_LEN (sizeof(hdac_codecs) / sizeof(hdac_codecs[0]))
589
590enum {
591 HDAC_HP_SWITCH_CTL,
592 HDAC_HP_SWITCH_CTRL,
593 HDAC_HP_SWITCH_DEBUG
594};
595
596static const struct {
597 uint32_t model;
598 uint32_t id;
599 int type;
600 int inverted;
601 int polling;
602 int execsense;
603 nid_t hpnid;
604 nid_t spkrnid[8];
605 nid_t eapdnid;
606} hdac_hp_switch[] = {
607 /* Specific OEM models */
608 { HP_V3000_SUBVENDOR, HDA_CODEC_CXVENICE, HDAC_HP_SWITCH_CTL,
609 0, 0, -1, 17, { 16, -1 }, 16 },
610 /* { HP_XW4300_SUBVENDOR, HDA_CODEC_ALC260, HDAC_HP_SWITCH_CTL,
611 0, 0, -1, 21, { 16, 17, -1 }, -1 } */
612 /*{ HP_3010_SUBVENDOR, HDA_CODEC_ALC260, HDAC_HP_SWITCH_DEBUG,
613 0, 1, 0, 16, { 15, 18, 19, 20, 21, -1 }, -1 },*/
614 { HP_NX7400_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL,
615 0, 0, -1, 6, { 5, -1 }, 5 },
616 { HP_NX6310_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL,
617 0, 0, -1, 6, { 5, -1 }, 5 },
618 { HP_NX6325_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL,
619 0, 0, -1, 6, { 5, -1 }, 5 },
620 { TOSHIBA_U200_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL,
621 0, 0, -1, 6, { 5, -1 }, -1 },
622 { DELL_D820_SUBVENDOR, HDA_CODEC_STAC9220, HDAC_HP_SWITCH_CTRL,
623 0, 0, -1, 13, { 14, -1 }, -1 },
624 { DELL_I1300_SUBVENDOR, HDA_CODEC_STAC9220, HDAC_HP_SWITCH_CTRL,
625 0, 0, -1, 13, { 14, -1 }, -1 },
626 { DELL_OPLX745_SUBVENDOR, HDA_CODEC_AD1983, HDAC_HP_SWITCH_CTL,
627 0, 0, -1, 6, { 5, 7, -1 }, -1 },
628 { APPLE_INTEL_MAC, HDA_CODEC_STAC9221, HDAC_HP_SWITCH_CTRL,
629 0, 0, -1, 10, { 13, -1 }, -1 },
630 { LENOVO_3KN100_SUBVENDOR, HDA_CODEC_AD1986A, HDAC_HP_SWITCH_CTL,
631 1, 0, -1, 26, { 27, -1 }, -1 },
632 { LG_LW20_SUBVENDOR, HDA_CODEC_ALC880, HDAC_HP_SWITCH_CTL,
633 0, 0, -1, 27, { 20, -1 }, -1 },
634 { ACER_A5050_SUBVENDOR, HDA_CODEC_ALC883, HDAC_HP_SWITCH_CTL,
635 0, 0, -1, 20, { 21, -1 }, -1 },
636 { ACER_3681WXM_SUBVENDOR, HDA_CODEC_ALC883, HDAC_HP_SWITCH_CTL,
637 0, 0, -1, 20, { 21, -1 }, -1 },
638 { MSI_MS1034_SUBVENDOR, HDA_CODEC_ALC883, HDAC_HP_SWITCH_CTL,
639 0, 0, -1, 20, { 27, -1 }, -1 },
640 /*
641 * All models that at least come from the same vendor with
642 * simmilar codec.
643 */
644 { HP_ALL_SUBVENDOR, HDA_CODEC_CXVENICE, HDAC_HP_SWITCH_CTL,
645 0, 0, -1, 17, { 16, -1 }, 16 },
646 { HP_ALL_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL,
647 0, 0, -1, 6, { 5, -1 }, 5 },
648 { TOSHIBA_ALL_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL,
649 0, 0, -1, 6, { 5, -1 }, -1 },
650 { DELL_ALL_SUBVENDOR, HDA_CODEC_STAC9220, HDAC_HP_SWITCH_CTRL,
651 0, 0, -1, 13, { 14, -1 }, -1 },
652 { LENOVO_ALL_SUBVENDOR, HDA_CODEC_AD1986A, HDAC_HP_SWITCH_CTL,
653 1, 0, -1, 26, { 27, -1 }, -1 },
654#if 0
655 { ACER_ALL_SUBVENDOR, HDA_CODEC_ALC883, HDAC_HP_SWITCH_CTL,
656 0, 0, -1, 20, { 21, -1 }, -1 },
657#endif
658};
659#define HDAC_HP_SWITCH_LEN \
660 (sizeof(hdac_hp_switch) / sizeof(hdac_hp_switch[0]))
661
662static const struct {
663 uint32_t model;
664 uint32_t id;
665 nid_t eapdnid;
666 int hp_switch;
667} hdac_eapd_switch[] = {
668 { HP_V3000_SUBVENDOR, HDA_CODEC_CXVENICE, 16, 1 },
669 { HP_NX7400_SUBVENDOR, HDA_CODEC_AD1981HD, 5, 1 },
670 { HP_NX6310_SUBVENDOR, HDA_CODEC_AD1981HD, 5, 1 },
671};
672#define HDAC_EAPD_SWITCH_LEN \
673 (sizeof(hdac_eapd_switch) / sizeof(hdac_eapd_switch[0]))
674
675/****************************************************************************
676 * Function prototypes
677 ****************************************************************************/
678static void hdac_intr_handler(void *);
679static int hdac_reset(struct hdac_softc *);
680static int hdac_get_capabilities(struct hdac_softc *);
681static void hdac_dma_cb(void *, bus_dma_segment_t *, int, int);
682static int hdac_dma_alloc(struct hdac_softc *,
683 struct hdac_dma *, bus_size_t);
684static void hdac_dma_free(struct hdac_softc *, struct hdac_dma *);
685static int hdac_mem_alloc(struct hdac_softc *);
686static void hdac_mem_free(struct hdac_softc *);
687static int hdac_irq_alloc(struct hdac_softc *);
688static void hdac_irq_free(struct hdac_softc *);
689static void hdac_corb_init(struct hdac_softc *);
690static void hdac_rirb_init(struct hdac_softc *);
691static void hdac_corb_start(struct hdac_softc *);
692static void hdac_rirb_start(struct hdac_softc *);
693static void hdac_scan_codecs(struct hdac_softc *);
694static int hdac_probe_codec(struct hdac_codec *);
695static struct hdac_devinfo *hdac_probe_function(struct hdac_codec *, nid_t);
696static void hdac_add_child(struct hdac_softc *, struct hdac_devinfo *);
697
698static void hdac_attach2(void *);
699
700static uint32_t hdac_command_sendone_internal(struct hdac_softc *,
701 uint32_t, int);
702static void hdac_command_send_internal(struct hdac_softc *,
703 struct hdac_command_list *, int);
704
705static int hdac_probe(device_t);
706static int hdac_attach(device_t);
707static int hdac_detach(device_t);
708static void hdac_widget_connection_select(struct hdac_widget *, uint8_t);
709static void hdac_audio_ctl_amp_set(struct hdac_audio_ctl *,
710 uint32_t, int, int);
711static struct hdac_audio_ctl *hdac_audio_ctl_amp_get(struct hdac_devinfo *,
712 nid_t, int, int);
713static void hdac_audio_ctl_amp_set_internal(struct hdac_softc *,
714 nid_t, nid_t, int, int, int, int, int, int);
715static int hdac_audio_ctl_ossmixer_getnextdev(struct hdac_devinfo *);
716static struct hdac_widget *hdac_widget_get(struct hdac_devinfo *, nid_t);
717
718static int hdac_rirb_flush(struct hdac_softc *sc);
719static int hdac_unsolq_flush(struct hdac_softc *sc);
720
721#define hdac_command(a1, a2, a3) \
722 hdac_command_sendone_internal(a1, a2, a3)
723
724#define hdac_codec_id(d) \
725 ((uint32_t)((d == NULL) ? 0x00000000 : \
726 ((((uint32_t)(d)->vendor_id & 0x0000ffff) << 16) | \
727 ((uint32_t)(d)->device_id & 0x0000ffff))))
728
729static char *
730hdac_codec_name(struct hdac_devinfo *devinfo)
731{
732 uint32_t id;
733 int i;
734
735 id = hdac_codec_id(devinfo);
736
737 for (i = 0; i < HDAC_CODECS_LEN; i++) {
738 if (HDA_DEV_MATCH(hdac_codecs[i].id, id))
739 return (hdac_codecs[i].name);
740 }
741
742 return ((id == 0x00000000) ? "NULL Codec" : "Unknown Codec");
743}
744
745static char *
746hdac_audio_ctl_ossmixer_mask2name(uint32_t devmask)
747{
748 static char *ossname[] = SOUND_DEVICE_NAMES;
749 static char *unknown = "???";
750 int i;
751
752 for (i = SOUND_MIXER_NRDEVICES - 1; i >= 0; i--) {
753 if (devmask & (1 << i))
754 return (ossname[i]);
755 }
756 return (unknown);
757}
758
759static void
760hdac_audio_ctl_ossmixer_mask2allname(uint32_t mask, char *buf, size_t len)
761{
762 static char *ossname[] = SOUND_DEVICE_NAMES;
763 int i, first = 1;
764
765 bzero(buf, len);
766 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) {
767 if (mask & (1 << i)) {
768 if (first == 0)
769 strlcat(buf, ", ", len);
770 strlcat(buf, ossname[i], len);
771 first = 0;
772 }
773 }
774}
775
776static struct hdac_audio_ctl *
777hdac_audio_ctl_each(struct hdac_devinfo *devinfo, int *index)
778{
779 if (devinfo == NULL ||
780 devinfo->node_type != HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO ||
781 index == NULL || devinfo->function.audio.ctl == NULL ||
782 devinfo->function.audio.ctlcnt < 1 ||
783 *index < 0 || *index >= devinfo->function.audio.ctlcnt)
784 return (NULL);
785 return (&devinfo->function.audio.ctl[(*index)++]);
786}
787
788static struct hdac_audio_ctl *
789hdac_audio_ctl_amp_get(struct hdac_devinfo *devinfo, nid_t nid,
790 int index, int cnt)
791{
792 struct hdac_audio_ctl *ctl, *retctl = NULL;
793 int i, at, atindex, found = 0;
794
795 if (devinfo == NULL || devinfo->function.audio.ctl == NULL)
796 return (NULL);
797
798 at = cnt;
799 if (at == 0)
800 at = 1;
801 else if (at < 0)
802 at = -1;
803 atindex = index;
804 if (atindex < 0)
805 atindex = -1;
806
807 i = 0;
808 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) {
809 if (ctl->enable == 0 || ctl->widget == NULL)
810 continue;
811 if (!(ctl->widget->nid == nid && (atindex == -1 ||
812 ctl->index == atindex)))
813 continue;
814 found++;
815 if (found == cnt)
816 return (ctl);
817 retctl = ctl;
818 }
819
820 return ((at == -1) ? retctl : NULL);
821}
822
823static void
824hdac_hp_switch_handler(struct hdac_devinfo *devinfo)
825{
826 struct hdac_softc *sc;
827 struct hdac_widget *w;
828 struct hdac_audio_ctl *ctl;
829 uint32_t val, id, res;
830 int i = 0, j, forcemute;
831 nid_t cad;
832
833 if (devinfo == NULL || devinfo->codec == NULL ||
834 devinfo->codec->sc == NULL)
835 return;
836
837 sc = devinfo->codec->sc;
838 cad = devinfo->codec->cad;
839 id = hdac_codec_id(devinfo);
840 for (i = 0; i < HDAC_HP_SWITCH_LEN; i++) {
841 if (HDA_DEV_MATCH(hdac_hp_switch[i].model,
842 sc->pci_subvendor) &&
843 hdac_hp_switch[i].id == id)
844 break;
845 }
846
847 if (i >= HDAC_HP_SWITCH_LEN)
848 return;
849
850 forcemute = 0;
851 if (hdac_hp_switch[i].eapdnid != -1) {
852 w = hdac_widget_get(devinfo, hdac_hp_switch[i].eapdnid);
853 if (w != NULL && w->param.eapdbtl != HDAC_INVALID)
854 forcemute = (w->param.eapdbtl &
855 HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD) ? 0 : 1;
856 }
857
858 if (hdac_hp_switch[i].execsense != -1)
859 hdac_command(sc,
860 HDA_CMD_SET_PIN_SENSE(cad, hdac_hp_switch[i].hpnid,
861 hdac_hp_switch[i].execsense), cad);
862 res = hdac_command(sc,
863 HDA_CMD_GET_PIN_SENSE(cad, hdac_hp_switch[i].hpnid), cad);
864 HDA_BOOTVERBOSE(
865 device_printf(sc->dev,
866 "HDA_DEBUG: Pin sense: nid=%d res=0x%08x\n",
867 hdac_hp_switch[i].hpnid, res);
868 );
869 res = HDA_CMD_GET_PIN_SENSE_PRESENCE_DETECT(res);
870 res ^= hdac_hp_switch[i].inverted;
871
872 switch (hdac_hp_switch[i].type) {
873 case HDAC_HP_SWITCH_CTL:
874 ctl = hdac_audio_ctl_amp_get(devinfo,
875 hdac_hp_switch[i].hpnid, 0, 1);
876 if (ctl != NULL) {
877 val = (res != 0 && forcemute == 0) ?
878 HDA_AMP_MUTE_NONE : HDA_AMP_MUTE_ALL;
879 if (val != ctl->muted) {
880 ctl->muted = val;
881 hdac_audio_ctl_amp_set(ctl,
882 HDA_AMP_MUTE_DEFAULT, ctl->left,
883 ctl->right);
884 }
885 }
886 for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) {
887 ctl = hdac_audio_ctl_amp_get(devinfo,
888 hdac_hp_switch[i].spkrnid[j], 0, 1);
889 if (ctl == NULL)
890 continue;
891 val = (res != 0 || forcemute == 1) ?
892 HDA_AMP_MUTE_ALL : HDA_AMP_MUTE_NONE;
893 if (val == ctl->muted)
894 continue;
895 ctl->muted = val;
896 hdac_audio_ctl_amp_set(ctl, HDA_AMP_MUTE_DEFAULT,
897 ctl->left, ctl->right);
898 }
899 break;
900 case HDAC_HP_SWITCH_CTRL:
901 if (res != 0) {
902 /* HP in */
903 w = hdac_widget_get(devinfo, hdac_hp_switch[i].hpnid);
904 if (w != NULL && w->type ==
905 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) {
906 if (forcemute == 0)
907 val = w->wclass.pin.ctrl |
908 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE;
909 else
910 val = w->wclass.pin.ctrl &
911 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE;
912 if (val != w->wclass.pin.ctrl) {
913 w->wclass.pin.ctrl = val;
914 hdac_command(sc,
915 HDA_CMD_SET_PIN_WIDGET_CTRL(cad,
916 w->nid, w->wclass.pin.ctrl), cad);
917 }
918 }
919 for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) {
920 w = hdac_widget_get(devinfo,
921 hdac_hp_switch[i].spkrnid[j]);
922 if (w == NULL || w->type !=
923 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX)
924 continue;
925 val = w->wclass.pin.ctrl &
926 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE;
927 if (val == w->wclass.pin.ctrl)
928 continue;
929 w->wclass.pin.ctrl = val;
930 hdac_command(sc, HDA_CMD_SET_PIN_WIDGET_CTRL(
931 cad, w->nid, w->wclass.pin.ctrl), cad);
932 }
933 } else {
934 /* HP out */
935 w = hdac_widget_get(devinfo, hdac_hp_switch[i].hpnid);
936 if (w != NULL && w->type ==
937 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) {
938 val = w->wclass.pin.ctrl &
939 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE;
940 if (val != w->wclass.pin.ctrl) {
941 w->wclass.pin.ctrl = val;
942 hdac_command(sc,
943 HDA_CMD_SET_PIN_WIDGET_CTRL(cad,
944 w->nid, w->wclass.pin.ctrl), cad);
945 }
946 }
947 for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) {
948 w = hdac_widget_get(devinfo,
949 hdac_hp_switch[i].spkrnid[j]);
950 if (w == NULL || w->type !=
951 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX)
952 continue;
953 if (forcemute == 0)
954 val = w->wclass.pin.ctrl |
955 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE;
956 else
957 val = w->wclass.pin.ctrl &
958 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE;
959 if (val == w->wclass.pin.ctrl)
960 continue;
961 w->wclass.pin.ctrl = val;
962 hdac_command(sc, HDA_CMD_SET_PIN_WIDGET_CTRL(
963 cad, w->nid, w->wclass.pin.ctrl), cad);
964 }
965 }
966 break;
967 case HDAC_HP_SWITCH_DEBUG:
968 if (hdac_hp_switch[i].execsense != -1)
969 hdac_command(sc,
970 HDA_CMD_SET_PIN_SENSE(cad, hdac_hp_switch[i].hpnid,
971 hdac_hp_switch[i].execsense), cad);
972 res = hdac_command(sc,
973 HDA_CMD_GET_PIN_SENSE(cad, hdac_hp_switch[i].hpnid), cad);
974 device_printf(sc->dev,
975 "[ 0] HDA_DEBUG: Pin sense: nid=%d res=0x%08x\n",
976 hdac_hp_switch[i].hpnid, res);
977 for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) {
978 w = hdac_widget_get(devinfo,
979 hdac_hp_switch[i].spkrnid[j]);
980 if (w == NULL || w->type !=
981 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX)
982 continue;
983 if (hdac_hp_switch[i].execsense != -1)
984 hdac_command(sc,
985 HDA_CMD_SET_PIN_SENSE(cad, w->nid,
986 hdac_hp_switch[i].execsense), cad);
987 res = hdac_command(sc,
988 HDA_CMD_GET_PIN_SENSE(cad, w->nid), cad);
989 device_printf(sc->dev,
990 "[%2d] HDA_DEBUG: Pin sense: nid=%d res=0x%08x\n",
991 j + 1, w->nid, res);
992 }
993 break;
994 default:
995 break;
996 }
997}
998
999static void
1000hdac_unsolicited_handler(struct hdac_codec *codec, uint32_t tag)
1001{
1002 struct hdac_softc *sc;
1003 struct hdac_devinfo *devinfo = NULL;
1004 device_t *devlist = NULL;
1005 int devcount, i;
1006
1007 if (codec == NULL || codec->sc == NULL)
1008 return;
1009
1010 sc = codec->sc;
1011
1012 HDA_BOOTVERBOSE(
1013 device_printf(sc->dev, "HDA_DEBUG: Unsol Tag: 0x%08x\n", tag);
1014 );
1015
1016 device_get_children(sc->dev, &devlist, &devcount);
1017 for (i = 0; devlist != NULL && i < devcount; i++) {
1018 devinfo = (struct hdac_devinfo *)device_get_ivars(devlist[i]);
1019 if (devinfo != NULL && devinfo->node_type ==
1020 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO &&
1021 devinfo->codec != NULL &&
1022 devinfo->codec->cad == codec->cad) {
1023 break;
1024 } else
1025 devinfo = NULL;
1026 }
1027 if (devlist != NULL)
1028 free(devlist, M_TEMP);
1029
1030 if (devinfo == NULL)
1031 return;
1032
1033 switch (tag) {
1034 case HDAC_UNSOLTAG_EVENT_HP:
1035 hdac_hp_switch_handler(devinfo);
1036 break;
1037 case HDAC_UNSOLTAG_EVENT_TEST:
1038 device_printf(sc->dev, "Unsol Test!\n");
1039 break;
1040 default:
1041 break;
1042 }
1043}
1044
1045static int
1046hdac_stream_intr(struct hdac_softc *sc, struct hdac_chan *ch)
1047{
1048 /* XXX to be removed */
1049#ifdef HDAC_INTR_EXTRA
1050 uint32_t res;
1051#endif
1052
1053 if (ch->blkcnt == 0)
1054 return (0);
1055
1056 /* XXX to be removed */
1057#ifdef HDAC_INTR_EXTRA
1058 res = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDSTS);
1059#endif
1060
1061 /* XXX to be removed */
1062#ifdef HDAC_INTR_EXTRA
1063 HDA_BOOTVERBOSE(
1064 if (res & (HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE))
1065 device_printf(sc->dev,
1066 "PCMDIR_%s intr triggered beyond stream boundary:"
1067 "%08x\n",
1068 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", res);
1069 );
1070#endif
1071
1072 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDSTS,
1073 HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE | HDAC_SDSTS_BCIS );
1074
1075 /* XXX to be removed */
1076#ifdef HDAC_INTR_EXTRA
1077 if (res & HDAC_SDSTS_BCIS) {
1078#endif
1079 return (1);
1080 /* XXX to be removed */
1081#ifdef HDAC_INTR_EXTRA
1082 }
1083#endif
1084
1085 return (0);
1086}
1087
1088/****************************************************************************
1089 * void hdac_intr_handler(void *)
1090 *
1091 * Interrupt handler. Processes interrupts received from the hdac.
1092 ****************************************************************************/
1093static void
1094hdac_intr_handler(void *context)
1095{
1096 struct hdac_softc *sc;
1097 uint32_t intsts;
1098 uint8_t rirbsts;
1099 struct hdac_rirb *rirb_base;
1100 uint32_t trigger = 0;
1101
1102 sc = (struct hdac_softc *)context;
1103
1104 hdac_lock(sc);
1105 if (sc->polling != 0) {
1106 hdac_unlock(sc);
1107 return;
1108 }
1109 /* Do we have anything to do? */
1110 intsts = HDAC_READ_4(&sc->mem, HDAC_INTSTS);
1111 if (!HDA_FLAG_MATCH(intsts, HDAC_INTSTS_GIS)) {
1112 hdac_unlock(sc);
1113 return;
1114 }
1115
1116 /* Was this a controller interrupt? */
1117 if (HDA_FLAG_MATCH(intsts, HDAC_INTSTS_CIS)) {
1118 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr;
1119 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS);
1120 /* Get as many responses that we can */
1121 while (HDA_FLAG_MATCH(rirbsts, HDAC_RIRBSTS_RINTFL)) {
1122 HDAC_WRITE_1(&sc->mem,
1123 HDAC_RIRBSTS, HDAC_RIRBSTS_RINTFL);
1124 hdac_rirb_flush(sc);
1125 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS);
1126 }
1127 /* XXX to be removed */
1128 /* Clear interrupt and exit */
1129#ifdef HDAC_INTR_EXTRA
1130 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, HDAC_INTSTS_CIS);
1131#endif
1132 }
1133
1134 hdac_unsolq_flush(sc);
1135
1136 if (intsts & HDAC_INTSTS_SIS_MASK) {
1137 if ((intsts & (1 << sc->num_iss)) &&
1138 hdac_stream_intr(sc, &sc->play) != 0)
1139 trigger |= 1;
1140 if ((intsts & (1 << 0)) &&
1141 hdac_stream_intr(sc, &sc->rec) != 0)
1142 trigger |= 2;
1143 /* XXX to be removed */
1144#ifdef HDAC_INTR_EXTRA
1145 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, intsts &
1146 HDAC_INTSTS_SIS_MASK);
1147#endif
1148 }
1149
1150 hdac_unlock(sc);
1151
1152 if (trigger & 1)
1153 chn_intr(sc->play.c);
1154 if (trigger & 2)
1155 chn_intr(sc->rec.c);
1156}
1157
1158/****************************************************************************
1159 * int hdac_reset(hdac_softc *)
1160 *
1161 * Reset the hdac to a quiescent and known state.
1162 ****************************************************************************/
1163static int
1164hdac_reset(struct hdac_softc *sc)
1165{
1166 uint32_t gctl;
1167 int count, i;
1168
1169 /*
1170 * Stop all Streams DMA engine
1171 */
1172 for (i = 0; i < sc->num_iss; i++)
1173 HDAC_WRITE_4(&sc->mem, HDAC_ISDCTL(sc, i), 0x0);
1174 for (i = 0; i < sc->num_oss; i++)
1175 HDAC_WRITE_4(&sc->mem, HDAC_OSDCTL(sc, i), 0x0);
1176 for (i = 0; i < sc->num_bss; i++)
1177 HDAC_WRITE_4(&sc->mem, HDAC_BSDCTL(sc, i), 0x0);
1178
1179 /*
1180 * Stop Control DMA engines.
1181 */
1182 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, 0x0);
1183 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 0x0);
1184
1185 /*
1186 * Reset DMA position buffer.
1187 */
1188 HDAC_WRITE_4(&sc->mem, HDAC_DPIBLBASE, 0x0);
1189 HDAC_WRITE_4(&sc->mem, HDAC_DPIBUBASE, 0x0);
1190
1191 /*
1192 * Reset the controller. The reset must remain asserted for
1193 * a minimum of 100us.
1194 */
1195 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL);
1196 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl & ~HDAC_GCTL_CRST);
1197 count = 10000;
1198 do {
1199 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL);
1200 if (!(gctl & HDAC_GCTL_CRST))
1201 break;
1202 DELAY(10);
1203 } while (--count);
1204 if (gctl & HDAC_GCTL_CRST) {
1205 device_printf(sc->dev, "Unable to put hdac in reset\n");
1206 return (ENXIO);
1207 }
1208 DELAY(100);
1209 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL);
1210 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl | HDAC_GCTL_CRST);
1211 count = 10000;
1212 do {
1213 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL);
1214 if (gctl & HDAC_GCTL_CRST)
1215 break;
1216 DELAY(10);
1217 } while (--count);
1218 if (!(gctl & HDAC_GCTL_CRST)) {
1219 device_printf(sc->dev, "Device stuck in reset\n");
1220 return (ENXIO);
1221 }
1222
1223 /*
1224 * Wait for codecs to finish their own reset sequence. The delay here
1225 * should be of 250us but for some reasons, on it's not enough on my
1226 * computer. Let's use twice as much as necessary to make sure that
1227 * it's reset properly.
1228 */
1229 DELAY(1000);
1230
1231 return (0);
1232}
1233
1234
1235/****************************************************************************
1236 * int hdac_get_capabilities(struct hdac_softc *);
1237 *
1238 * Retreive the general capabilities of the hdac;
1239 * Number of Input Streams
1240 * Number of Output Streams
1241 * Number of bidirectional Streams
1242 * 64bit ready
1243 * CORB and RIRB sizes
1244 ****************************************************************************/
1245static int
1246hdac_get_capabilities(struct hdac_softc *sc)
1247{
1248 uint16_t gcap;
1249 uint8_t corbsize, rirbsize;
1250
1251 gcap = HDAC_READ_2(&sc->mem, HDAC_GCAP);
1252 sc->num_iss = HDAC_GCAP_ISS(gcap);
1253 sc->num_oss = HDAC_GCAP_OSS(gcap);
1254 sc->num_bss = HDAC_GCAP_BSS(gcap);
1255
1256 sc->support_64bit = HDA_FLAG_MATCH(gcap, HDAC_GCAP_64OK);
1257
1258 corbsize = HDAC_READ_1(&sc->mem, HDAC_CORBSIZE);
1259 if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_256) ==
1260 HDAC_CORBSIZE_CORBSZCAP_256)
1261 sc->corb_size = 256;
1262 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_16) ==
1263 HDAC_CORBSIZE_CORBSZCAP_16)
1264 sc->corb_size = 16;
1265 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_2) ==
1266 HDAC_CORBSIZE_CORBSZCAP_2)
1267 sc->corb_size = 2;
1268 else {
1269 device_printf(sc->dev, "%s: Invalid corb size (%x)\n",
1270 __func__, corbsize);
1271 return (ENXIO);
1272 }
1273
1274 rirbsize = HDAC_READ_1(&sc->mem, HDAC_RIRBSIZE);
1275 if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_256) ==
1276 HDAC_RIRBSIZE_RIRBSZCAP_256)
1277 sc->rirb_size = 256;
1278 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_16) ==
1279 HDAC_RIRBSIZE_RIRBSZCAP_16)
1280 sc->rirb_size = 16;
1281 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_2) ==
1282 HDAC_RIRBSIZE_RIRBSZCAP_2)
1283 sc->rirb_size = 2;
1284 else {
1285 device_printf(sc->dev, "%s: Invalid rirb size (%x)\n",
1286 __func__, rirbsize);
1287 return (ENXIO);
1288 }
1289
1290 return (0);
1291}
1292
1293
1294/****************************************************************************
1295 * void hdac_dma_cb
1296 *
1297 * This function is called by bus_dmamap_load when the mapping has been
1298 * established. We just record the physical address of the mapping into
1299 * the struct hdac_dma passed in.
1300 ****************************************************************************/
1301static void
1302hdac_dma_cb(void *callback_arg, bus_dma_segment_t *segs, int nseg, int error)
1303{
1304 struct hdac_dma *dma;
1305
1306 if (error == 0) {
1307 dma = (struct hdac_dma *)callback_arg;
1308 dma->dma_paddr = segs[0].ds_addr;
1309 }
1310}
1311
1312
1313/****************************************************************************
1314 * int hdac_dma_alloc
1315 *
1316 * This function allocate and setup a dma region (struct hdac_dma).
1317 * It must be freed by a corresponding hdac_dma_free.
1318 ****************************************************************************/
1319static int
1320hdac_dma_alloc(struct hdac_softc *sc, struct hdac_dma *dma, bus_size_t size)
1321{
1322 bus_size_t roundsz;
1323 int result;
1324 int lowaddr;
1325
1326 roundsz = roundup2(size, HDAC_DMA_ALIGNMENT);
1327 lowaddr = (sc->support_64bit) ? BUS_SPACE_MAXADDR :
1328 BUS_SPACE_MAXADDR_32BIT;
1329 bzero(dma, sizeof(*dma));
1330
1331 /*
1332 * Create a DMA tag
1333 */
1334 result = bus_dma_tag_create(NULL, /* parent */
1335 HDAC_DMA_ALIGNMENT, /* alignment */
1336 0, /* boundary */
1337 lowaddr, /* lowaddr */
1338 BUS_SPACE_MAXADDR, /* highaddr */
1339 NULL, /* filtfunc */
1340 NULL, /* fistfuncarg */
1341 roundsz, /* maxsize */
1342 1, /* nsegments */
1343 roundsz, /* maxsegsz */
1344 0, /* flags */
1345 NULL, /* lockfunc */
1346 NULL, /* lockfuncarg */
1347 &dma->dma_tag); /* dmat */
1348 if (result != 0) {
1349 device_printf(sc->dev, "%s: bus_dma_tag_create failed (%x)\n",
1350 __func__, result);
1351 goto hdac_dma_alloc_fail;
1352 }
1353
1354 /*
1355 * Allocate DMA memory
1356 */
1357 result = bus_dmamem_alloc(dma->dma_tag, (void **)&dma->dma_vaddr,
1358 BUS_DMA_NOWAIT | BUS_DMA_ZERO |
1359 ((sc->nocache != 0) ? BUS_DMA_NOCACHE : 0), &dma->dma_map);
1360 if (result != 0) {
1361 device_printf(sc->dev, "%s: bus_dmamem_alloc failed (%x)\n",
1362 __func__, result);
1363 goto hdac_dma_alloc_fail;
1364 }
1365
1366 dma->dma_size = roundsz;
1367
1368 /*
1369 * Map the memory
1370 */
1371 result = bus_dmamap_load(dma->dma_tag, dma->dma_map,
1372 (void *)dma->dma_vaddr, roundsz, hdac_dma_cb, (void *)dma, 0);
1373 if (result != 0 || dma->dma_paddr == 0) {
1374 if (result == 0)
1375 result = ENOMEM;
1376 device_printf(sc->dev, "%s: bus_dmamem_load failed (%x)\n",
1377 __func__, result);
1378 goto hdac_dma_alloc_fail;
1379 }
1380
1381 HDA_BOOTVERBOSE(
1382 device_printf(sc->dev, "%s: size=%ju -> roundsz=%ju\n",
1383 __func__, (uintmax_t)size, (uintmax_t)roundsz);
1384 );
1385
1386 return (0);
1387
1388hdac_dma_alloc_fail:
1389 hdac_dma_free(sc, dma);
1390
1391 return (result);
1392}
1393
1394
1395/****************************************************************************
1396 * void hdac_dma_free(struct hdac_softc *, struct hdac_dma *)
1397 *
1398 * Free a struct dhac_dma that has been previously allocated via the
1399 * hdac_dma_alloc function.
1400 ****************************************************************************/
1401static void
1402hdac_dma_free(struct hdac_softc *sc, struct hdac_dma *dma)
1403{
1404 if (dma->dma_map != NULL) {
1405#if 0
1406 /* Flush caches */
1407 bus_dmamap_sync(dma->dma_tag, dma->dma_map,
1408 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1409#endif
1410 bus_dmamap_unload(dma->dma_tag, dma->dma_map);
1411 }
1412 if (dma->dma_vaddr != NULL) {
1413 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map);
1414 dma->dma_vaddr = NULL;
1415 }
1416 dma->dma_map = NULL;
1417 if (dma->dma_tag != NULL) {
1418 bus_dma_tag_destroy(dma->dma_tag);
1419 dma->dma_tag = NULL;
1420 }
1421 dma->dma_size = 0;
1422}
1423
1424/****************************************************************************
1425 * int hdac_mem_alloc(struct hdac_softc *)
1426 *
1427 * Allocate all the bus resources necessary to speak with the physical
1428 * controller.
1429 ****************************************************************************/
1430static int
1431hdac_mem_alloc(struct hdac_softc *sc)
1432{
1433 struct hdac_mem *mem;
1434
1435 mem = &sc->mem;
1436 mem->mem_rid = PCIR_BAR(0);
1437 mem->mem_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY,
1438 &mem->mem_rid, RF_ACTIVE);
1439 if (mem->mem_res == NULL) {
1440 device_printf(sc->dev,
1441 "%s: Unable to allocate memory resource\n", __func__);
1442 return (ENOMEM);
1443 }
1444 mem->mem_tag = rman_get_bustag(mem->mem_res);
1445 mem->mem_handle = rman_get_bushandle(mem->mem_res);
1446
1447 return (0);
1448}
1449
1450/****************************************************************************
1451 * void hdac_mem_free(struct hdac_softc *)
1452 *
1453 * Free up resources previously allocated by hdac_mem_alloc.
1454 ****************************************************************************/
1455static void
1456hdac_mem_free(struct hdac_softc *sc)
1457{
1458 struct hdac_mem *mem;
1459
1460 mem = &sc->mem;
1461 if (mem->mem_res != NULL)
1462 bus_release_resource(sc->dev, SYS_RES_MEMORY, mem->mem_rid,
1463 mem->mem_res);
1464 mem->mem_res = NULL;
1465}
1466
1467/****************************************************************************
1468 * int hdac_irq_alloc(struct hdac_softc *)
1469 *
1470 * Allocate and setup the resources necessary for interrupt handling.
1471 ****************************************************************************/
1472static int
1473hdac_irq_alloc(struct hdac_softc *sc)
1474{
1475 struct hdac_irq *irq;
1476 int result;
1477
1478 irq = &sc->irq;
1479 irq->irq_rid = 0x0;
1480 irq->irq_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ,
1481 &irq->irq_rid, RF_SHAREABLE | RF_ACTIVE);
1482 if (irq->irq_res == NULL) {
1483 device_printf(sc->dev, "%s: Unable to allocate irq\n",
1484 __func__);
1485 goto hdac_irq_alloc_fail;
1486 }
1487 result = snd_setup_intr(sc->dev, irq->irq_res, INTR_MPSAFE,
1488 hdac_intr_handler, sc, &irq->irq_handle);
1489 if (result != 0) {
1490 device_printf(sc->dev,
1491 "%s: Unable to setup interrupt handler (%x)\n",
1492 __func__, result);
1493 goto hdac_irq_alloc_fail;
1494 }
1495
1496 return (0);
1497
1498hdac_irq_alloc_fail:
1499 hdac_irq_free(sc);
1500
1501 return (ENXIO);
1502}
1503
1504/****************************************************************************
1505 * void hdac_irq_free(struct hdac_softc *)
1506 *
1507 * Free up resources previously allocated by hdac_irq_alloc.
1508 ****************************************************************************/
1509static void
1510hdac_irq_free(struct hdac_softc *sc)
1511{
1512 struct hdac_irq *irq;
1513
1514 irq = &sc->irq;
1515 if (irq->irq_res != NULL && irq->irq_handle != NULL)
1516 bus_teardown_intr(sc->dev, irq->irq_res, irq->irq_handle);
1517 if (irq->irq_res != NULL)
1518 bus_release_resource(sc->dev, SYS_RES_IRQ, irq->irq_rid,
1519 irq->irq_res);
1520 irq->irq_handle = NULL;
1521 irq->irq_res = NULL;
1522}
1523
1524/****************************************************************************
1525 * void hdac_corb_init(struct hdac_softc *)
1526 *
1527 * Initialize the corb registers for operations but do not start it up yet.
1528 * The CORB engine must not be running when this function is called.
1529 ****************************************************************************/
1530static void
1531hdac_corb_init(struct hdac_softc *sc)
1532{
1533 uint8_t corbsize;
1534 uint64_t corbpaddr;
1535
1536 /* Setup the CORB size. */
1537 switch (sc->corb_size) {
1538 case 256:
1539 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_256);
1540 break;
1541 case 16:
1542 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_16);
1543 break;
1544 case 2:
1545 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_2);
1546 break;
1547 default:
1548 panic("%s: Invalid CORB size (%x)\n", __func__, sc->corb_size);
1549 }
1550 HDAC_WRITE_1(&sc->mem, HDAC_CORBSIZE, corbsize);
1551
1552 /* Setup the CORB Address in the hdac */
1553 corbpaddr = (uint64_t)sc->corb_dma.dma_paddr;
1554 HDAC_WRITE_4(&sc->mem, HDAC_CORBLBASE, (uint32_t)corbpaddr);
1555 HDAC_WRITE_4(&sc->mem, HDAC_CORBUBASE, (uint32_t)(corbpaddr >> 32));
1556
1557 /* Set the WP and RP */
1558 sc->corb_wp = 0;
1559 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp);
1560 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, HDAC_CORBRP_CORBRPRST);
1561 /*
1562 * The HDA specification indicates that the CORBRPRST bit will always
1563 * read as zero. Unfortunately, it seems that at least the 82801G
1564 * doesn't reset the bit to zero, which stalls the corb engine.
1565 * manually reset the bit to zero before continuing.
1566 */
1567 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, 0x0);
1568
1569 /* Enable CORB error reporting */
1570#if 0
1571 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, HDAC_CORBCTL_CMEIE);
1572#endif
1573}
1574
1575/****************************************************************************
1576 * void hdac_rirb_init(struct hdac_softc *)
1577 *
1578 * Initialize the rirb registers for operations but do not start it up yet.
1579 * The RIRB engine must not be running when this function is called.
1580 ****************************************************************************/
1581static void
1582hdac_rirb_init(struct hdac_softc *sc)
1583{
1584 uint8_t rirbsize;
1585 uint64_t rirbpaddr;
1586
1587 /* Setup the RIRB size. */
1588 switch (sc->rirb_size) {
1589 case 256:
1590 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_256);
1591 break;
1592 case 16:
1593 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_16);
1594 break;
1595 case 2:
1596 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_2);
1597 break;
1598 default:
1599 panic("%s: Invalid RIRB size (%x)\n", __func__, sc->rirb_size);
1600 }
1601 HDAC_WRITE_1(&sc->mem, HDAC_RIRBSIZE, rirbsize);
1602
1603 /* Setup the RIRB Address in the hdac */
1604 rirbpaddr = (uint64_t)sc->rirb_dma.dma_paddr;
1605 HDAC_WRITE_4(&sc->mem, HDAC_RIRBLBASE, (uint32_t)rirbpaddr);
1606 HDAC_WRITE_4(&sc->mem, HDAC_RIRBUBASE, (uint32_t)(rirbpaddr >> 32));
1607
1608 /* Setup the WP and RP */
1609 sc->rirb_rp = 0;
1610 HDAC_WRITE_2(&sc->mem, HDAC_RIRBWP, HDAC_RIRBWP_RIRBWPRST);
1611
1612 if (sc->polling == 0) {
1613 /* Setup the interrupt threshold */
1614 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, sc->rirb_size / 2);
1615
1616 /* Enable Overrun and response received reporting */
1617#if 0
1618 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL,
1619 HDAC_RIRBCTL_RIRBOIC | HDAC_RIRBCTL_RINTCTL);
1620#else
1621 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, HDAC_RIRBCTL_RINTCTL);
1622#endif
1623 }
1624
1625#if 0
1626 /*
1627 * Make sure that the Host CPU cache doesn't contain any dirty
1628 * cache lines that falls in the rirb. If I understood correctly, it
1629 * should be sufficient to do this only once as the rirb is purely
1630 * read-only from now on.
1631 */
1632 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map,
1633 BUS_DMASYNC_PREREAD);
1634#endif
1635}
1636
1637/****************************************************************************
1638 * void hdac_corb_start(hdac_softc *)
1639 *
1640 * Startup the corb DMA engine
1641 ****************************************************************************/
1642static void
1643hdac_corb_start(struct hdac_softc *sc)
1644{
1645 uint32_t corbctl;
1646
1647 corbctl = HDAC_READ_1(&sc->mem, HDAC_CORBCTL);
1648 corbctl |= HDAC_CORBCTL_CORBRUN;
1649 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, corbctl);
1650}
1651
1652/****************************************************************************
1653 * void hdac_rirb_start(hdac_softc *)
1654 *
1655 * Startup the rirb DMA engine
1656 ****************************************************************************/
1657static void
1658hdac_rirb_start(struct hdac_softc *sc)
1659{
1660 uint32_t rirbctl;
1661
1662 rirbctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL);
1663 rirbctl |= HDAC_RIRBCTL_RIRBDMAEN;
1664 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, rirbctl);
1665}
1666
1667
1668/****************************************************************************
1669 * void hdac_scan_codecs(struct hdac_softc *)
1670 *
1671 * Scan the bus for available codecs.
1672 ****************************************************************************/
1673static void
1674hdac_scan_codecs(struct hdac_softc *sc)
1675{
1676 struct hdac_codec *codec;
1677 int i;
1678 uint16_t statests;
1679
1680 statests = HDAC_READ_2(&sc->mem, HDAC_STATESTS);
1681 for (i = 0; i < HDAC_CODEC_MAX; i++) {
1682 if (HDAC_STATESTS_SDIWAKE(statests, i)) {
1683 /* We have found a codec. */
1684 codec = (struct hdac_codec *)malloc(sizeof(*codec),
1685 M_HDAC, M_ZERO | M_NOWAIT);
1686 if (codec == NULL) {
1687 device_printf(sc->dev,
1688 "Unable to allocate memory for codec\n");
1689 continue;
1690 }
1691 codec->commands = NULL;
1692 codec->responses_received = 0;
1693 codec->verbs_sent = 0;
1694 codec->sc = sc;
1695 codec->cad = i;
1696 sc->codecs[i] = codec;
1697 if (hdac_probe_codec(codec) != 0)
1698 break;
1699 }
1700 }
1701 /* All codecs have been probed, now try to attach drivers to them */
1702 /* bus_generic_attach(sc->dev); */
1703}
1704
1705/****************************************************************************
1706 * void hdac_probe_codec(struct hdac_softc *, int)
1707 *
1708 * Probe a the given codec_id for available function groups.
1709 ****************************************************************************/
1710static int
1711hdac_probe_codec(struct hdac_codec *codec)
1712{
1713 struct hdac_softc *sc = codec->sc;
1714 struct hdac_devinfo *devinfo;
1715 uint32_t vendorid, revisionid, subnode;
1716 int startnode;
1717 int endnode;
1718 int i;
1719 nid_t cad = codec->cad;
1720
1721 HDA_BOOTVERBOSE(
1722 device_printf(sc->dev, "HDA_DEBUG: Probing codec: %d\n", cad);
1723 );
1724 vendorid = hdac_command(sc,
1725 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_VENDOR_ID),
1726 cad);
1727 revisionid = hdac_command(sc,
1728 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_REVISION_ID),
1729 cad);
1730 subnode = hdac_command(sc,
1731 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_SUB_NODE_COUNT),
1732 cad);
1733 startnode = HDA_PARAM_SUB_NODE_COUNT_START(subnode);
1734 endnode = startnode + HDA_PARAM_SUB_NODE_COUNT_TOTAL(subnode);
1735
1736 HDA_BOOTVERBOSE(
1737 device_printf(sc->dev, "HDA_DEBUG: \tstartnode=%d endnode=%d\n",
1738 startnode, endnode);
1739 );
1740 for (i = startnode; i < endnode; i++) {
1741 devinfo = hdac_probe_function(codec, i);
1742 if (devinfo != NULL) {
1743 /* XXX Ignore other FG. */
1744 devinfo->vendor_id =
1745 HDA_PARAM_VENDOR_ID_VENDOR_ID(vendorid);
1746 devinfo->device_id =
1747 HDA_PARAM_VENDOR_ID_DEVICE_ID(vendorid);
1748 devinfo->revision_id =
1749 HDA_PARAM_REVISION_ID_REVISION_ID(revisionid);
1750 devinfo->stepping_id =
1751 HDA_PARAM_REVISION_ID_STEPPING_ID(revisionid);
1752 HDA_BOOTVERBOSE(
1753 device_printf(sc->dev,
1754 "HDA_DEBUG: \tFound AFG nid=%d "
1755 "[startnode=%d endnode=%d]\n",
1756 devinfo->nid, startnode, endnode);
1757 );
1758 return (1);
1759 }
1760 }
1761
1762 HDA_BOOTVERBOSE(
1763 device_printf(sc->dev, "HDA_DEBUG: \tAFG not found\n");
1764 );
1765 return (0);
1766}
1767
1768static struct hdac_devinfo *
1769hdac_probe_function(struct hdac_codec *codec, nid_t nid)
1770{
1771 struct hdac_softc *sc = codec->sc;
1772 struct hdac_devinfo *devinfo;
1773 uint32_t fctgrptype;
1774 nid_t cad = codec->cad;
1775
1776 fctgrptype = HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE(hdac_command(sc,
1777 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_FCT_GRP_TYPE), cad));
1778
1779 /* XXX For now, ignore other FG. */
1780 if (fctgrptype != HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO)
1781 return (NULL);
1782
1783 devinfo = (struct hdac_devinfo *)malloc(sizeof(*devinfo), M_HDAC,
1784 M_NOWAIT | M_ZERO);
1785 if (devinfo == NULL) {
1786 device_printf(sc->dev, "%s: Unable to allocate ivar\n",
1787 __func__);
1788 return (NULL);
1789 }
1790
1791 devinfo->nid = nid;
1792 devinfo->node_type = fctgrptype;
1793 devinfo->codec = codec;
1794
1795 hdac_add_child(sc, devinfo);
1796
1797 return (devinfo);
1798}
1799
1800static void
1801hdac_add_child(struct hdac_softc *sc, struct hdac_devinfo *devinfo)
1802{
1803 devinfo->dev = device_add_child(sc->dev, NULL, -1);
1804 device_set_ivars(devinfo->dev, (void *)devinfo);
1805 /* XXX - Print more information when booting verbose??? */
1806}
1807
1808static void
1809hdac_widget_connection_parse(struct hdac_widget *w)
1810{
1811 struct hdac_softc *sc = w->devinfo->codec->sc;
1812 uint32_t res;
1813 int i, j, max, ents, entnum;
1814 nid_t cad = w->devinfo->codec->cad;
1815 nid_t nid = w->nid;
1816 nid_t cnid, addcnid, prevcnid;
1817
1818 w->nconns = 0;
1819
1820 res = hdac_command(sc,
1821 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_CONN_LIST_LENGTH), cad);
1822
1823 ents = HDA_PARAM_CONN_LIST_LENGTH_LIST_LENGTH(res);
1824
1825 if (ents < 1)
1826 return;
1827
1828 entnum = HDA_PARAM_CONN_LIST_LENGTH_LONG_FORM(res) ? 2 : 4;
1829 max = (sizeof(w->conns) / sizeof(w->conns[0])) - 1;
1830 prevcnid = 0;
1831
1832#define CONN_RMASK(e) (1 << ((32 / (e)) - 1))
1833#define CONN_NMASK(e) (CONN_RMASK(e) - 1)
1834#define CONN_RESVAL(r, e, n) ((r) >> ((32 / (e)) * (n)))
1835#define CONN_RANGE(r, e, n) (CONN_RESVAL(r, e, n) & CONN_RMASK(e))
1836#define CONN_CNID(r, e, n) (CONN_RESVAL(r, e, n) & CONN_NMASK(e))
1837
1838 for (i = 0; i < ents; i += entnum) {
1839 res = hdac_command(sc,
1840 HDA_CMD_GET_CONN_LIST_ENTRY(cad, nid, i), cad);
1841 for (j = 0; j < entnum; j++) {
1842 cnid = CONN_CNID(res, entnum, j);
1843 if (cnid == 0) {
1844 if (w->nconns < ents)
1845 device_printf(sc->dev,
1846 "%s: nid=%d WARNING: zero cnid "
1847 "entnum=%d j=%d index=%d "
1848 "entries=%d found=%d res=0x%08x\n",
1849 __func__, nid, entnum, j, i,
1850 ents, w->nconns, res);
1851 else
1852 goto getconns_out;
1853 }
1854 if (cnid < w->devinfo->startnode ||
1855 cnid >= w->devinfo->endnode) {
1856 HDA_BOOTVERBOSE(
1857 device_printf(sc->dev,
1858 "%s: GHOST: nid=%d j=%d "
1859 "entnum=%d index=%d res=0x%08x\n",
1860 __func__, nid, j, entnum, i, res);
1861 );
1862 }
1863 if (CONN_RANGE(res, entnum, j) == 0)
1864 addcnid = cnid;
1865 else if (prevcnid == 0 || prevcnid >= cnid) {
1866 device_printf(sc->dev,
1867 "%s: WARNING: Invalid child range "
1868 "nid=%d index=%d j=%d entnum=%d "
1869 "prevcnid=%d cnid=%d res=0x%08x\n",
1870 __func__, nid, i, j, entnum, prevcnid,
1871 cnid, res);
1872 addcnid = cnid;
1873 } else
1874 addcnid = prevcnid + 1;
1875 while (addcnid <= cnid) {
1876 if (w->nconns > max) {
1877 device_printf(sc->dev,
1878 "%s: nid=%d: Adding %d: "
1879 "Max connection reached! max=%d\n",
1880 __func__, nid, addcnid, max + 1);
1881 goto getconns_out;
1882 }
1883 w->conns[w->nconns++] = addcnid++;
1884 }
1885 prevcnid = cnid;
1886 }
1887 }
1888
1889getconns_out:
1890 HDA_BOOTVERBOSE(
1891 device_printf(sc->dev,
1892 "HDA_DEBUG: %s: nid=%d entries=%d found=%d\n",
1893 __func__, nid, ents, w->nconns);
1894 );
1895 return;
1896}
1897
1898static uint32_t
1899hdac_widget_pin_getconfig(struct hdac_widget *w)
1900{
1901 struct hdac_softc *sc;
1902 uint32_t config, orig, id;
1903 nid_t cad, nid;
1904
1905 sc = w->devinfo->codec->sc;
1906 cad = w->devinfo->codec->cad;
1907 nid = w->nid;
1908 id = hdac_codec_id(w->devinfo);
1909
1910 config = hdac_command(sc,
1911 HDA_CMD_GET_CONFIGURATION_DEFAULT(cad, nid),
1912 cad);
1913 orig = config;
1914
1915 /*
1916 * XXX REWRITE!!!! Don't argue!
1917 */
1918 if (id == HDA_CODEC_ALC880 && sc->pci_subvendor == LG_LW20_SUBVENDOR) {
1919 switch (nid) {
1920 case 26:
1921 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK;
1922 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN;
1923 break;
1924 case 27:
1925 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK;
1926 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT;
1927 break;
1928 default:
1929 break;
1930 }
1931 } else if (id == HDA_CODEC_ALC880 &&
1932 (sc->pci_subvendor == CLEVO_D900T_SUBVENDOR ||
1933 sc->pci_subvendor == ASUS_M5200_SUBVENDOR)) {
1934 /*
1935 * Super broken BIOS
1936 */
1937 switch (nid) {
1938 case 20:
1939 break;
1940 case 21:
1941 break;
1942 case 22:
1943 break;
1944 case 23:
1945 break;
1946 case 24: /* MIC1 */
1947 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK;
1948 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN;
1949 break;
1950 case 25: /* XXX MIC2 */
1951 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK;
1952 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN;
1953 break;
1954 case 26: /* LINE1 */
1955 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK;
1956 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN;
1957 break;
1958 case 27: /* XXX LINE2 */
1959 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK;
1960 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN;
1961 break;
1962 case 28: /* CD */
1963 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK;
1964 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_CD;
1965 break;
1966 case 30:
1967 break;
1968 case 31:
1969 break;
1970 default:
1971 break;
1972 }
1973 } else if (id == HDA_CODEC_ALC883 &&
1974 HDA_DEV_MATCH(ACER_ALL_SUBVENDOR, sc->pci_subvendor)) {
1975 switch (nid) {
1976 case 25:
1977 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK |
1978 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK);
1979 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN |
1980 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED);
1981 break;
1982 case 28:
1983 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK |
1984 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK);
1985 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_CD |
1986 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED);
1987 break;
1988 default:
1989 break;
1990 }
1991 } else if (id == HDA_CODEC_CXVENICE && sc->pci_subvendor ==
1992 HP_V3000_SUBVENDOR) {
1993 switch (nid) {
1994 case 18:
1995 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK;
1996 config |= HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE;
1997 break;
1998 case 20:
1999 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK |
2000 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK);
2001 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN |
2002 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED);
2003 break;
2004 case 21:
2005 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK |
2006 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK);
2007 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_CD |
2008 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED);
2009 break;
2010 default:
2011 break;
2012 }
2013 } else if (id == HDA_CODEC_CXWAIKIKI && sc->pci_subvendor ==
2014 HP_DV5000_SUBVENDOR) {
2015 switch (nid) {
2016 case 20:
2017 case 21:
2018 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK;
2019 config |= HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE;
2020 break;
2021 default:
2022 break;
2023 }
2024 } else if (id == HDA_CODEC_ALC861 && sc->pci_subvendor ==
2025 ASUS_W6F_SUBVENDOR) {
2026 switch (nid) {
2027 case 11:
2028 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK |
2029 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK);
2030 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT |
2031 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED);
2032 break;
2033 case 15:
2034 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK |
2035 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK);
2036 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT |
2037 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK);
2038 break;
2039 default:
2040 break;
2041 }
2042 } else if (id == HDA_CODEC_ALC861 && sc->pci_subvendor ==
2043 UNIWILL_9075_SUBVENDOR) {
2044 switch (nid) {
2045 case 15:
2046 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK |
2047 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK);
2048 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT |
2049 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK);
2050 break;
2051 default:
2052 break;
2053 }
2054 } else if (id == HDA_CODEC_AD1986A && sc->pci_subvendor ==
2055 ASUS_M2NPVMX_SUBVENDOR) {
2056 switch (nid) {
2057 case 28: /* LINE */
2058 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK;
2059 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN;
2060 break;
2061 case 29: /* MIC */
2062 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK;
2063 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN;
2064 break;
2065 default:
2066 break;
2067 }
2068 }
2069
2070 HDA_BOOTVERBOSE(
2071 if (config != orig)
2072 device_printf(sc->dev,
2073 "HDA_DEBUG: Pin config nid=%u 0x%08x -> 0x%08x\n",
2074 nid, orig, config);
2075 );
2076
2077 return (config);
2078}
2079
2080static uint32_t
2081hdac_widget_pin_getcaps(struct hdac_widget *w)
2082{
2083 struct hdac_softc *sc;
2084 uint32_t caps, orig, id;
2085 nid_t cad, nid;
2086
2087 sc = w->devinfo->codec->sc;
2088 cad = w->devinfo->codec->cad;
2089 nid = w->nid;
2090 id = hdac_codec_id(w->devinfo);
2091
2092 caps = hdac_command(sc,
2093 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_PIN_CAP), cad);
2094 orig = caps;
2095
2096 HDA_BOOTVERBOSE(
2097 if (caps != orig)
2098 device_printf(sc->dev,
2099 "HDA_DEBUG: Pin caps nid=%u 0x%08x -> 0x%08x\n",
2100 nid, orig, caps);
2101 );
2102
2103 return (caps);
2104}
2105
2106static void
2107hdac_widget_pin_parse(struct hdac_widget *w)
2108{
2109 struct hdac_softc *sc = w->devinfo->codec->sc;
2110 uint32_t config, pincap;
2111 char *devstr, *connstr;
2112 nid_t cad = w->devinfo->codec->cad;
2113 nid_t nid = w->nid;
2114
2115 config = hdac_widget_pin_getconfig(w);
2116 w->wclass.pin.config = config;
2117
2118 pincap = hdac_widget_pin_getcaps(w);
2119 w->wclass.pin.cap = pincap;
2120
2121 w->wclass.pin.ctrl = hdac_command(sc,
2122 HDA_CMD_GET_PIN_WIDGET_CTRL(cad, nid), cad) &
2123 ~(HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE |
2124 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE |
2125 HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE |
2126 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE_MASK);
2127
2128 if (HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap))
2129 w->wclass.pin.ctrl |= HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE;
2130 if (HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap))
2131 w->wclass.pin.ctrl |= HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE;
2132 if (HDA_PARAM_PIN_CAP_INPUT_CAP(pincap))
2133 w->wclass.pin.ctrl |= HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE;
2134 if (HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)) {
2135 w->param.eapdbtl = hdac_command(sc,
2136 HDA_CMD_GET_EAPD_BTL_ENABLE(cad, nid), cad);
2137 w->param.eapdbtl &= 0x7;
2138 w->param.eapdbtl |= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD;
2139 } else
2140 w->param.eapdbtl = HDAC_INVALID;
2141
2142 switch (config & HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) {
2143 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT:
2144 devstr = "line out";
2145 break;
2146 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER:
2147 devstr = "speaker";
2148 break;
2149 case HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT:
2150 devstr = "headphones out";
2151 break;
2152 case HDA_CONFIG_DEFAULTCONF_DEVICE_CD:
2153 devstr = "CD";
2154 break;
2155 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_OUT:
2156 devstr = "SPDIF out";
2157 break;
2158 case HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_OUT:
2159 devstr = "digital (other) out";
2160 break;
2161 case HDA_CONFIG_DEFAULTCONF_DEVICE_MODEM_LINE:
2162 devstr = "modem, line side";
2163 break;
2164 case HDA_CONFIG_DEFAULTCONF_DEVICE_MODEM_HANDSET:
2165 devstr = "modem, handset side";
2166 break;
2167 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN:
2168 devstr = "line in";
2169 break;
2170 case HDA_CONFIG_DEFAULTCONF_DEVICE_AUX:
2171 devstr = "AUX";
2172 break;
2173 case HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN:
2174 devstr = "Mic in";
2175 break;
2176 case HDA_CONFIG_DEFAULTCONF_DEVICE_TELEPHONY:
2177 devstr = "telephony";
2178 break;
2179 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_IN:
2180 devstr = "SPDIF in";
2181 break;
2182 case HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_IN:
2183 devstr = "digital (other) in";
2184 break;
2185 case HDA_CONFIG_DEFAULTCONF_DEVICE_OTHER:
2186 devstr = "other";
2187 break;
2188 default:
2189 devstr = "unknown";
2190 break;
2191 }
2192
2193 switch (config & HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) {
2194 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK:
2195 connstr = "jack";
2196 break;
2197 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE:
2198 connstr = "none";
2199 break;
2200 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED:
2201 connstr = "fixed";
2202 break;
2203 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_BOTH:
2204 connstr = "jack / fixed";
2205 break;
2206 default:
2207 connstr = "unknown";
2208 break;
2209 }
2210
2211 strlcat(w->name, ": ", sizeof(w->name));
2212 strlcat(w->name, devstr, sizeof(w->name));
2213 strlcat(w->name, " (", sizeof(w->name));
2214 strlcat(w->name, connstr, sizeof(w->name));
2215 strlcat(w->name, ")", sizeof(w->name));
2216}
2217
2218static void
2219hdac_widget_parse(struct hdac_widget *w)
2220{
2221 struct hdac_softc *sc = w->devinfo->codec->sc;
2222 uint32_t wcap, cap;
2223 char *typestr;
2224 nid_t cad = w->devinfo->codec->cad;
2225 nid_t nid = w->nid;
2226
2227 wcap = hdac_command(sc,
2228 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_AUDIO_WIDGET_CAP),
2229 cad);
2230 w->param.widget_cap = wcap;
2231 w->type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE(wcap);
2232
2233 switch (w->type) {
2234 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT:
2235 typestr = "audio output";
2236 break;
2237 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT:
2238 typestr = "audio input";
2239 break;
2240 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER:
2241 typestr = "audio mixer";
2242 break;
2243 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR:
2244 typestr = "audio selector";
2245 break;
2246 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX:
2247 typestr = "pin";
2248 break;
2249 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_POWER_WIDGET:
2250 typestr = "power widget";
2251 break;
2252 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VOLUME_WIDGET:
2253 typestr = "volume widget";
2254 break;
2255 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET:
2256 typestr = "beep widget";
2257 break;
2258 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VENDOR_WIDGET:
2259 typestr = "vendor widget";
2260 break;
2261 default:
2262 typestr = "unknown type";
2263 break;
2264 }
2265
2266 strlcpy(w->name, typestr, sizeof(w->name));
2267
2268 if (HDA_PARAM_AUDIO_WIDGET_CAP_POWER_CTRL(wcap)) {
2269 hdac_command(sc,
2270 HDA_CMD_SET_POWER_STATE(cad, nid, HDA_CMD_POWER_STATE_D0),
2271 cad);
2272 DELAY(1000);
2273 }
2274
2275 hdac_widget_connection_parse(w);
2276
2277 if (HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(wcap)) {
2278 if (HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(wcap))
2279 w->param.outamp_cap =
2280 hdac_command(sc,
2281 HDA_CMD_GET_PARAMETER(cad, nid,
2282 HDA_PARAM_OUTPUT_AMP_CAP), cad);
2283 else
2284 w->param.outamp_cap =
2285 w->devinfo->function.audio.outamp_cap;
2286 } else
2287 w->param.outamp_cap = 0;
2288
2289 if (HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(wcap)) {
2290 if (HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(wcap))
2291 w->param.inamp_cap =
2292 hdac_command(sc,
2293 HDA_CMD_GET_PARAMETER(cad, nid,
2294 HDA_PARAM_INPUT_AMP_CAP), cad);
2295 else
2296 w->param.inamp_cap =
2297 w->devinfo->function.audio.inamp_cap;
2298 } else
2299 w->param.inamp_cap = 0;
2300
2301 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT ||
2302 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) {
2303 if (HDA_PARAM_AUDIO_WIDGET_CAP_FORMAT_OVR(wcap)) {
2304 cap = hdac_command(sc,
2305 HDA_CMD_GET_PARAMETER(cad, nid,
2306 HDA_PARAM_SUPP_STREAM_FORMATS), cad);
2307 w->param.supp_stream_formats = (cap != 0) ? cap :
2308 w->devinfo->function.audio.supp_stream_formats;
2309 cap = hdac_command(sc,
2310 HDA_CMD_GET_PARAMETER(cad, nid,
2311 HDA_PARAM_SUPP_PCM_SIZE_RATE), cad);
2312 w->param.supp_pcm_size_rate = (cap != 0) ? cap :
2313 w->devinfo->function.audio.supp_pcm_size_rate;
2314 } else {
2315 w->param.supp_stream_formats =
2316 w->devinfo->function.audio.supp_stream_formats;
2317 w->param.supp_pcm_size_rate =
2318 w->devinfo->function.audio.supp_pcm_size_rate;
2319 }
2320 } else {
2321 w->param.supp_stream_formats = 0;
2322 w->param.supp_pcm_size_rate = 0;
2323 }
2324
2325 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX)
2326 hdac_widget_pin_parse(w);
2327}
2328
2329static struct hdac_widget *
2330hdac_widget_get(struct hdac_devinfo *devinfo, nid_t nid)
2331{
2332 if (devinfo == NULL || devinfo->widget == NULL ||
2333 nid < devinfo->startnode || nid >= devinfo->endnode)
2334 return (NULL);
2335 return (&devinfo->widget[nid - devinfo->startnode]);
2336}
2337
2338static __inline int
2339hda_poll_channel(struct hdac_chan *ch)
2340{
2341 uint32_t sz, delta;
2342 volatile uint32_t ptr;
2343
2344 if (ch->active == 0)
2345 return (0);
2346
2347 sz = ch->blksz * ch->blkcnt;
2348 if (ch->dmapos != NULL)
2349 ptr = *(ch->dmapos);
2350 else
2351 ptr = HDAC_READ_4(&ch->devinfo->codec->sc->mem,
2352 ch->off + HDAC_SDLPIB);
2353 ch->ptr = ptr;
2354 ptr %= sz;
2355 ptr &= ~(ch->blksz - 1);
2356 delta = (sz + ptr - ch->prevptr) % sz;
2357
2358 if (delta < ch->blksz)
2359 return (0);
2360
2361 ch->prevptr = ptr;
2362
2363 return (1);
2364}
2365
2366#define hda_chan_active(sc) ((sc)->play.active + (sc)->rec.active)
2367
2368static void
2369hda_poll_callback(void *arg)
2370{
2371 struct hdac_softc *sc = arg;
2372 uint32_t trigger = 0;
2373
2374 if (sc == NULL)
2375 return;
2376
2377 hdac_lock(sc);
2378 if (sc->polling == 0 || hda_chan_active(sc) == 0) {
2379 hdac_unlock(sc);
2380 return;
2381 }
2382
2383 trigger |= (hda_poll_channel(&sc->play) != 0) ? 1 : 0;
2384 trigger |= (hda_poll_channel(&sc->rec) != 0) ? 2 : 0;
2385
2386 /* XXX */
2387 callout_reset(&sc->poll_hda, 1/*sc->poll_ticks*/,
2388 hda_poll_callback, sc);
2389
2390 hdac_unlock(sc);
2391
2392 if (trigger & 1)
2393 chn_intr(sc->play.c);
2394 if (trigger & 2)
2395 chn_intr(sc->rec.c);
2396}
2397
2398static int
2399hdac_rirb_flush(struct hdac_softc *sc)
2400{
2401 struct hdac_rirb *rirb_base, *rirb;
2402 struct hdac_codec *codec;
2403 struct hdac_command_list *commands;
2404 nid_t cad;
2405 uint32_t resp;
2406 uint8_t rirbwp;
2407 int ret = 0;
2408
2409 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr;
2410 rirbwp = HDAC_READ_1(&sc->mem, HDAC_RIRBWP);
2411#if 0
2412 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map,
2413 BUS_DMASYNC_POSTREAD);
2414#endif
2415
2416 while (sc->rirb_rp != rirbwp) {
2417 sc->rirb_rp++;
2418 sc->rirb_rp %= sc->rirb_size;
2419 rirb = &rirb_base[sc->rirb_rp];
2420 cad = HDAC_RIRB_RESPONSE_EX_SDATA_IN(rirb->response_ex);
2421 if (cad < 0 || cad >= HDAC_CODEC_MAX ||
2422 sc->codecs[cad] == NULL)
2423 continue;
2424 resp = rirb->response;
2425 codec = sc->codecs[cad];
2426 commands = codec->commands;
2427 if (rirb->response_ex & HDAC_RIRB_RESPONSE_EX_UNSOLICITED) {
2428 sc->unsolq[sc->unsolq_wp++] = (cad << 16) |
2429 ((resp >> 26) & 0xffff);
2430 sc->unsolq_wp %= HDAC_UNSOLQ_MAX;
2431 } else if (commands != NULL && commands->num_commands > 0 &&
2432 codec->responses_received < commands->num_commands)
2433 commands->responses[codec->responses_received++] =
2434 resp;
2435 ret++;
2436 }
2437
2438 return (ret);
2439}
2440
2441static int
2442hdac_unsolq_flush(struct hdac_softc *sc)
2443{
2444 nid_t cad;
2445 uint32_t tag;
2446 int ret = 0;
2447
2448 if (sc->unsolq_st == HDAC_UNSOLQ_READY) {
2449 sc->unsolq_st = HDAC_UNSOLQ_BUSY;
2450 while (sc->unsolq_rp != sc->unsolq_wp) {
2451 cad = sc->unsolq[sc->unsolq_rp] >> 16;
2452 tag = sc->unsolq[sc->unsolq_rp++] & 0xffff;
2453 sc->unsolq_rp %= HDAC_UNSOLQ_MAX;
2454 hdac_unsolicited_handler(sc->codecs[cad], tag);
2455 ret++;
2456 }
2457 sc->unsolq_st = HDAC_UNSOLQ_READY;
2458 }
2459
2460 return (ret);
2461}
2462
2463static void
2464hdac_poll_callback(void *arg)
2465{
2466 struct hdac_softc *sc = arg;
2467 if (sc == NULL)
2468 return;
2469
2470 hdac_lock(sc);
2471 if (sc->polling == 0 || sc->poll_ival == 0) {
2472 hdac_unlock(sc);
2473 return;
2474 }
2475 hdac_rirb_flush(sc);
2476 hdac_unsolq_flush(sc);
2477 callout_reset(&sc->poll_hdac, sc->poll_ival, hdac_poll_callback, sc);
2478 hdac_unlock(sc);
2479}
2480
2481static void
2482hdac_stream_stop(struct hdac_chan *ch)
2483{
2484 struct hdac_softc *sc = ch->devinfo->codec->sc;
2485 uint32_t ctl;
2486
2487 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0);
2488 ctl &= ~(HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE |
2489 HDAC_SDCTL_RUN);
2490 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl);
2491
2492 ch->active = 0;
2493
2494 if (sc->polling != 0) {
2495 int pollticks;
2496
2497 if (hda_chan_active(sc) == 0) {
2498 callout_stop(&sc->poll_hda);
2499 sc->poll_ticks = 1;
2500 } else {
2501 if (sc->play.active != 0)
2502 ch = &sc->play;
2503 else
2504 ch = &sc->rec;
2505 pollticks = ((uint64_t)hz * ch->blksz) /
2506 ((uint64_t)sndbuf_getbps(ch->b) *
2507 sndbuf_getspd(ch->b));
2508 pollticks >>= 2;
2509 if (pollticks > hz)
2510 pollticks = hz;
2511 if (pollticks < 1) {
2512 HDA_BOOTVERBOSE(
2513 device_printf(sc->dev,
2514 "%s: pollticks=%d < 1 !\n",
2515 __func__, pollticks);
2516 );
2517 pollticks = 1;
2518 }
2519 if (pollticks > sc->poll_ticks) {
2520 HDA_BOOTVERBOSE(
2521 device_printf(sc->dev,
2522 "%s: pollticks %d -> %d\n",
2523 __func__, sc->poll_ticks,
2524 pollticks);
2525 );
2526 sc->poll_ticks = pollticks;
2527 callout_reset(&sc->poll_hda, 1,
2528 hda_poll_callback, sc);
2529 }
2530 }
2531 } else {
2532 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL);
2533 ctl &= ~(1 << (ch->off >> 5));
2534 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl);
2535 }
2536}
2537
2538static void
2539hdac_stream_start(struct hdac_chan *ch)
2540{
2541 struct hdac_softc *sc = ch->devinfo->codec->sc;
2542 uint32_t ctl;
2543
2544 if (sc->polling != 0) {
2545 int pollticks;
2546
2547 pollticks = ((uint64_t)hz * ch->blksz) /
2548 ((uint64_t)sndbuf_getbps(ch->b) * sndbuf_getspd(ch->b));
2549 pollticks >>= 2;
2550 if (pollticks > hz)
2551 pollticks = hz;
2552 if (pollticks < 1) {
2553 HDA_BOOTVERBOSE(
2554 device_printf(sc->dev,
2555 "%s: pollticks=%d < 1 !\n",
2556 __func__, pollticks);
2557 );
2558 pollticks = 1;
2559 }
2560 if (hda_chan_active(sc) == 0 || pollticks < sc->poll_ticks) {
2561 HDA_BOOTVERBOSE(
2562 if (hda_chan_active(sc) == 0) {
2563 device_printf(sc->dev,
2564 "%s: pollticks=%d\n",
2565 __func__, pollticks);
2566 } else {
2567 device_printf(sc->dev,
2568 "%s: pollticks %d -> %d\n",
2569 __func__, sc->poll_ticks,
2570 pollticks);
2571 }
2572 );
2573 sc->poll_ticks = pollticks;
2574 callout_reset(&sc->poll_hda, 1, hda_poll_callback,
2575 sc);
2576 }
2577 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0);
2578 ctl |= HDAC_SDCTL_RUN;
2579 } else {
2580 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL);
2581 ctl |= 1 << (ch->off >> 5);
2582 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl);
2583 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0);
2584 ctl |= HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE |
2585 HDAC_SDCTL_RUN;
2586 }
2587 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl);
2588
2589 ch->active = 1;
2590}
2591
2592static void
2593hdac_stream_reset(struct hdac_chan *ch)
2594{
2595 struct hdac_softc *sc = ch->devinfo->codec->sc;
2596 int timeout = 1000;
2597 int to = timeout;
2598 uint32_t ctl;
2599
2600 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0);
2601 ctl |= HDAC_SDCTL_SRST;
2602 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl);
2603 do {
2604 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0);
2605 if (ctl & HDAC_SDCTL_SRST)
2606 break;
2607 DELAY(10);
2608 } while (--to);
2609 if (!(ctl & HDAC_SDCTL_SRST)) {
2610 device_printf(sc->dev, "timeout in reset\n");
2611 }
2612 ctl &= ~HDAC_SDCTL_SRST;
2613 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl);
2614 to = timeout;
2615 do {
2616 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0);
2617 if (!(ctl & HDAC_SDCTL_SRST))
2618 break;
2619 DELAY(10);
2620 } while (--to);
2621 if (ctl & HDAC_SDCTL_SRST)
2622 device_printf(sc->dev, "can't reset!\n");
2623}
2624
2625static void
2626hdac_stream_setid(struct hdac_chan *ch)
2627{
2628 struct hdac_softc *sc = ch->devinfo->codec->sc;
2629 uint32_t ctl;
2630
2631 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL2);
2632 ctl &= ~HDAC_SDCTL2_STRM_MASK;
2633 ctl |= ch->sid << HDAC_SDCTL2_STRM_SHIFT;
2634 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL2, ctl);
2635}
2636
2637static void
2638hdac_bdl_setup(struct hdac_chan *ch)
2639{
2640 struct hdac_softc *sc = ch->devinfo->codec->sc;
2641 struct hdac_bdle *bdle;
2642 uint64_t addr;
2643 uint32_t blksz, blkcnt;
2644 int i;
2645
2646 addr = (uint64_t)sndbuf_getbufaddr(ch->b);
2647 bdle = (struct hdac_bdle *)ch->bdl_dma.dma_vaddr;
2648
2649 if (sc->polling != 0) {
2650 blksz = ch->blksz * ch->blkcnt;
2651 blkcnt = 1;
2652 } else {
2653 blksz = ch->blksz;
2654 blkcnt = ch->blkcnt;
2655 }
2656
2657 for (i = 0; i < blkcnt; i++, bdle++) {
2658 bdle->addrl = (uint32_t)addr;
2659 bdle->addrh = (uint32_t)(addr >> 32);
2660 bdle->len = blksz;
2661 bdle->ioc = 1 ^ sc->polling;
2662 addr += blksz;
2663 }
2664
2665 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDCBL, blksz * blkcnt);
2666 HDAC_WRITE_2(&sc->mem, ch->off + HDAC_SDLVI, blkcnt - 1);
2667 addr = ch->bdl_dma.dma_paddr;
2668 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDBDPL, (uint32_t)addr);
2669 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDBDPU, (uint32_t)(addr >> 32));
2670 if (ch->dmapos != NULL &&
2671 !(HDAC_READ_4(&sc->mem, HDAC_DPIBLBASE) & 0x00000001)) {
2672 addr = sc->pos_dma.dma_paddr;
2673 HDAC_WRITE_4(&sc->mem, HDAC_DPIBLBASE,
2674 ((uint32_t)addr & HDAC_DPLBASE_DPLBASE_MASK) | 0x00000001);
2675 HDAC_WRITE_4(&sc->mem, HDAC_DPIBUBASE, (uint32_t)(addr >> 32));
2676 }
2677}
2678
2679static int
2680hdac_bdl_alloc(struct hdac_chan *ch)
2681{
2682 struct hdac_softc *sc = ch->devinfo->codec->sc;
2683 int rc;
2684
2685 rc = hdac_dma_alloc(sc, &ch->bdl_dma,
2686 sizeof(struct hdac_bdle) * HDA_BDL_MAX);
2687 if (rc) {
2688 device_printf(sc->dev, "can't alloc bdl\n");
2689 return (rc);
2690 }
2691
2692 return (0);
2693}
2694
2695static void
2696hdac_audio_ctl_amp_set_internal(struct hdac_softc *sc, nid_t cad, nid_t nid,
2697 int index, int lmute, int rmute,
2698 int left, int right, int dir)
2699{
2700 uint16_t v = 0;
2701
2702 if (sc == NULL)
2703 return;
2704
2705 if (left != right || lmute != rmute) {
2706 v = (1 << (15 - dir)) | (1 << 13) | (index << 8) |
2707 (lmute << 7) | left;
2708 hdac_command(sc,
2709 HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, v), cad);
2710 v = (1 << (15 - dir)) | (1 << 12) | (index << 8) |
2711 (rmute << 7) | right;
2712 } else
2713 v = (1 << (15 - dir)) | (3 << 12) | (index << 8) |
2714 (lmute << 7) | left;
2715
2716 hdac_command(sc,
2717 HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, v), cad);
2718}
2719
2720static void
2721hdac_audio_ctl_amp_set(struct hdac_audio_ctl *ctl, uint32_t mute,
2722 int left, int right)
2723{
2724 struct hdac_softc *sc;
2725 nid_t nid, cad;
2726 int lmute, rmute;
2727
2728 if (ctl == NULL || ctl->widget == NULL ||
2729 ctl->widget->devinfo == NULL ||
2730 ctl->widget->devinfo->codec == NULL ||
2731 ctl->widget->devinfo->codec->sc == NULL)
2732 return;
2733
2734 sc = ctl->widget->devinfo->codec->sc;
2735 cad = ctl->widget->devinfo->codec->cad;
2736 nid = ctl->widget->nid;
2737
2738 if (mute == HDA_AMP_MUTE_DEFAULT) {
2739 lmute = HDA_AMP_LEFT_MUTED(ctl->muted);
2740 rmute = HDA_AMP_RIGHT_MUTED(ctl->muted);
2741 } else {
2742 lmute = HDA_AMP_LEFT_MUTED(mute);
2743 rmute = HDA_AMP_RIGHT_MUTED(mute);
2744 }
2745
2746 if (ctl->dir & HDA_CTL_OUT)
2747 hdac_audio_ctl_amp_set_internal(sc, cad, nid, ctl->index,
2748 lmute, rmute, left, right, 0);
2749 if (ctl->dir & HDA_CTL_IN)
2750 hdac_audio_ctl_amp_set_internal(sc, cad, nid, ctl->index,
2751 lmute, rmute, left, right, 1);
2752 ctl->left = left;
2753 ctl->right = right;
2754}
2755
2756static void
2757hdac_widget_connection_select(struct hdac_widget *w, uint8_t index)
2758{
2759 if (w == NULL || w->nconns < 1 || index > (w->nconns - 1))
2760 return;
2761 hdac_command(w->devinfo->codec->sc,
2762 HDA_CMD_SET_CONNECTION_SELECT_CONTROL(w->devinfo->codec->cad,
2763 w->nid, index), w->devinfo->codec->cad);
2764 w->selconn = index;
2765}
2766
2767
2768/****************************************************************************
2769 * uint32_t hdac_command_sendone_internal
2770 *
2771 * Wrapper function that sends only one command to a given codec
2772 ****************************************************************************/
2773static uint32_t
2774hdac_command_sendone_internal(struct hdac_softc *sc, uint32_t verb, nid_t cad)
2775{
2776 struct hdac_command_list cl;
2777 uint32_t response = HDAC_INVALID;
2778
2779 if (!hdac_lockowned(sc))
2780 device_printf(sc->dev, "WARNING!!!! mtx not owned!!!!\n");
2781 cl.num_commands = 1;
2782 cl.verbs = &verb;
2783 cl.responses = &response;
2784
2785 hdac_command_send_internal(sc, &cl, cad);
2786
2787 return (response);
2788}
2789
2790/****************************************************************************
2791 * hdac_command_send_internal
2792 *
2793 * Send a command list to the codec via the corb. We queue as much verbs as
2794 * we can and msleep on the codec. When the interrupt get the responses
2795 * back from the rirb, it will wake us up so we can queue the remaining verbs
2796 * if any.
2797 ****************************************************************************/
2798static void
2799hdac_command_send_internal(struct hdac_softc *sc,
2800 struct hdac_command_list *commands, nid_t cad)
2801{
2802 struct hdac_codec *codec;
2803 int corbrp;
2804 uint32_t *corb;
2805 int timeout;
2806 int retry = 10;
2807 struct hdac_rirb *rirb_base;
2808
2809 if (sc == NULL || sc->codecs[cad] == NULL || commands == NULL ||
2810 commands->num_commands < 1)
2811 return;
2812
2813 codec = sc->codecs[cad];
2814 codec->commands = commands;
2815 codec->responses_received = 0;
2816 codec->verbs_sent = 0;
2817 corb = (uint32_t *)sc->corb_dma.dma_vaddr;
2818 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr;
2819
2820 do {
2821 if (codec->verbs_sent != commands->num_commands) {
2822 /* Queue as many verbs as possible */
2823 corbrp = HDAC_READ_2(&sc->mem, HDAC_CORBRP);
2824#if 0
2825 bus_dmamap_sync(sc->corb_dma.dma_tag,
2826 sc->corb_dma.dma_map, BUS_DMASYNC_PREWRITE);
2827#endif
2828 while (codec->verbs_sent != commands->num_commands &&
2829 ((sc->corb_wp + 1) % sc->corb_size) != corbrp) {
2830 sc->corb_wp++;
2831 sc->corb_wp %= sc->corb_size;
2832 corb[sc->corb_wp] =
2833 commands->verbs[codec->verbs_sent++];
2834 }
2835
2836 /* Send the verbs to the codecs */
2837#if 0
2838 bus_dmamap_sync(sc->corb_dma.dma_tag,
2839 sc->corb_dma.dma_map, BUS_DMASYNC_POSTWRITE);
2840#endif
2841 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp);
2842 }
2843
2844 timeout = 1000;
2845 while (hdac_rirb_flush(sc) == 0 && --timeout)
2846 DELAY(10);
2847 } while ((codec->verbs_sent != commands->num_commands ||
2848 codec->responses_received != commands->num_commands) && --retry);
2849
2850 if (retry == 0)
2851 device_printf(sc->dev,
2852 "%s: TIMEOUT numcmd=%d, sent=%d, received=%d\n",
2853 __func__, commands->num_commands, codec->verbs_sent,
2854 codec->responses_received);
2855
2856 codec->commands = NULL;
2857 codec->responses_received = 0;
2858 codec->verbs_sent = 0;
2859
2860 hdac_unsolq_flush(sc);
2861}
2862
2863
2864/****************************************************************************
2865 * Device Methods
2866 ****************************************************************************/
2867
2868/****************************************************************************
2869 * int hdac_probe(device_t)
2870 *
2871 * Probe for the presence of an hdac. If none is found, check for a generic
2872 * match using the subclass of the device.
2873 ****************************************************************************/
2874static int
2875hdac_probe(device_t dev)
2876{
2877 int i, result;
2878 uint32_t model;
2879 uint16_t class, subclass;
2880 char desc[64];
2881
2882 model = (uint32_t)pci_get_device(dev) << 16;
2883 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff;
2884 class = pci_get_class(dev);
2885 subclass = pci_get_subclass(dev);
2886
2887 bzero(desc, sizeof(desc));
2888 result = ENXIO;
2889 for (i = 0; i < HDAC_DEVICES_LEN; i++) {
2890 if (hdac_devices[i].model == model) {
2891 strlcpy(desc, hdac_devices[i].desc, sizeof(desc));
2892 result = BUS_PROBE_DEFAULT;
2893 break;
2894 }
2895 if (HDA_DEV_MATCH(hdac_devices[i].model, model) &&
2896 class == PCIC_MULTIMEDIA &&
2897 subclass == PCIS_MULTIMEDIA_HDA) {
2898 strlcpy(desc, hdac_devices[i].desc, sizeof(desc));
2899 result = BUS_PROBE_GENERIC;
2900 break;
2901 }
2902 }
2903 if (result == ENXIO && class == PCIC_MULTIMEDIA &&
2904 subclass == PCIS_MULTIMEDIA_HDA) {
2905 strlcpy(desc, "Generic", sizeof(desc));
2906 result = BUS_PROBE_GENERIC;
2907 }
2908 if (result != ENXIO) {
2909 strlcat(desc, " High Definition Audio Controller",
2910 sizeof(desc));
2911 device_set_desc_copy(dev, desc);
2912 }
2913
2914 return (result);
2915}
2916
2917static void *
2918hdac_channel_init(kobj_t obj, void *data, struct snd_dbuf *b,
2919 struct pcm_channel *c, int dir)
2920{
2921 struct hdac_devinfo *devinfo = data;
2922 struct hdac_softc *sc = devinfo->codec->sc;
2923 struct hdac_chan *ch;
2924
2925 hdac_lock(sc);
2926 if (dir == PCMDIR_PLAY) {
2927 ch = &sc->play;
2928 ch->off = (sc->num_iss + devinfo->function.audio.playcnt) << 5;
2929 devinfo->function.audio.playcnt++;
2930 } else {
2931 ch = &sc->rec;
2932 ch->off = devinfo->function.audio.reccnt << 5;
2933 devinfo->function.audio.reccnt++;
2934 }
2935 if (devinfo->function.audio.quirks & HDA_QUIRK_FIXEDRATE) {
2936 ch->caps.minspeed = ch->caps.maxspeed = 48000;
2937 ch->pcmrates[0] = 48000;
2938 ch->pcmrates[1] = 0;
2939 }
2940 if (sc->pos_dma.dma_vaddr != NULL)
2941 ch->dmapos = (uint32_t *)(sc->pos_dma.dma_vaddr +
2942 (sc->streamcnt * 8));
2943 else
2944 ch->dmapos = NULL;
2945 ch->sid = ++sc->streamcnt;
2946 ch->dir = dir;
2947 ch->b = b;
2948 ch->c = c;
2949 ch->devinfo = devinfo;
2950 ch->blksz = sc->chan_size / sc->chan_blkcnt;
2951 ch->blkcnt = sc->chan_blkcnt;
2952 hdac_unlock(sc);
2953
2954 if (hdac_bdl_alloc(ch) != 0) {
2955 ch->blkcnt = 0;
2956 return (NULL);
2957 }
2958
2959 if (sndbuf_alloc(ch->b, sc->chan_dmat,
2960 (sc->nocache != 0) ? BUS_DMA_NOCACHE : 0, sc->chan_size) != 0)
2961 return (NULL);
2962
2963 return (ch);
2964}
2965
2966static int
2967hdac_channel_setformat(kobj_t obj, void *data, uint32_t format)
2968{
2969 struct hdac_chan *ch = data;
2970 int i;
2971
2972 for (i = 0; ch->caps.fmtlist[i] != 0; i++) {
2973 if (format == ch->caps.fmtlist[i]) {
2974 ch->fmt = format;
2975 return (0);
2976 }
2977 }
2978
2979 return (EINVAL);
2980}
2981
2982static int
2983hdac_channel_setspeed(kobj_t obj, void *data, uint32_t speed)
2984{
2985 struct hdac_chan *ch = data;
2986 uint32_t spd = 0, threshold;
2987 int i;
2988
2989 for (i = 0; ch->pcmrates[i] != 0; i++) {
2990 spd = ch->pcmrates[i];
2991 threshold = spd + ((ch->pcmrates[i + 1] != 0) ?
2992 ((ch->pcmrates[i + 1] - spd) >> 1) : 0);
2993 if (speed < threshold)
2994 break;
2995 }
2996
2997 if (spd == 0) /* impossible */
2998 ch->spd = 48000;
2999 else
3000 ch->spd = spd;
3001
3002 return (ch->spd);
3003}
3004
3005static void
3006hdac_stream_setup(struct hdac_chan *ch)
3007{
3008 struct hdac_softc *sc = ch->devinfo->codec->sc;
3009 int i;
3010 nid_t cad = ch->devinfo->codec->cad;
3011 uint16_t fmt;
3012
3013 fmt = 0;
3014 if (ch->fmt & AFMT_S16_LE)
3015 fmt |= ch->bit16 << 4;
3016 else if (ch->fmt & AFMT_S32_LE)
3017 fmt |= ch->bit32 << 4;
3018 else
3019 fmt |= 1 << 4;
3020
3021 for (i = 0; i < HDA_RATE_TAB_LEN; i++) {
3022 if (hda_rate_tab[i].valid && ch->spd == hda_rate_tab[i].rate) {
3023 fmt |= hda_rate_tab[i].base;
3024 fmt |= hda_rate_tab[i].mul;
3025 fmt |= hda_rate_tab[i].div;
3026 break;
3027 }
3028 }
3029
3030 if (ch->fmt & AFMT_STEREO)
3031 fmt |= 1;
3032
3033 HDAC_WRITE_2(&sc->mem, ch->off + HDAC_SDFMT, fmt);
3034
3035 for (i = 0; ch->io[i] != -1; i++) {
3036 HDA_BOOTVERBOSE(
3037 device_printf(sc->dev,
3038 "HDA_DEBUG: PCMDIR_%s: Stream setup nid=%d "
3039 "fmt=0x%08x\n",
3040 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC",
3041 ch->io[i], fmt);
3042 );
3043 hdac_command(sc,
3044 HDA_CMD_SET_CONV_FMT(cad, ch->io[i], fmt), cad);
3045 hdac_command(sc,
3046 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i],
3047 ch->sid << 4), cad);
3048 }
3049}
3050
3051static int
3052hdac_channel_setfragments(kobj_t obj, void *data,
3053 uint32_t blksz, uint32_t blkcnt)
3054{
3055 struct hdac_chan *ch = data;
3056 struct hdac_softc *sc = ch->devinfo->codec->sc;
3057
3058 blksz &= HDA_BLK_ALIGN;
3059
3060 if (blksz > (sndbuf_getmaxsize(ch->b) / HDA_BDL_MIN))
3061 blksz = sndbuf_getmaxsize(ch->b) / HDA_BDL_MIN;
3062 if (blksz < HDA_BLK_MIN)
3063 blksz = HDA_BLK_MIN;
3064 if (blkcnt > HDA_BDL_MAX)
3065 blkcnt = HDA_BDL_MAX;
3066 if (blkcnt < HDA_BDL_MIN)
3067 blkcnt = HDA_BDL_MIN;
3068
3069 while ((blksz * blkcnt) > sndbuf_getmaxsize(ch->b)) {
3070 if ((blkcnt >> 1) >= HDA_BDL_MIN)
3071 blkcnt >>= 1;
3072 else if ((blksz >> 1) >= HDA_BLK_MIN)
3073 blksz >>= 1;
3074 else
3075 break;
3076 }
3077
3078 if ((sndbuf_getblksz(ch->b) != blksz ||
3079 sndbuf_getblkcnt(ch->b) != blkcnt) &&
3080 sndbuf_resize(ch->b, blkcnt, blksz) != 0)
3081 device_printf(sc->dev, "%s: failed blksz=%u blkcnt=%u\n",
3082 __func__, blksz, blkcnt);
3083
3084 ch->blksz = sndbuf_getblksz(ch->b);
3085 ch->blkcnt = sndbuf_getblkcnt(ch->b);
3086
3087 return (1);
3088}
3089
3090static int
3091hdac_channel_setblocksize(kobj_t obj, void *data, uint32_t blksz)
3092{
3093 struct hdac_chan *ch = data;
3094 struct hdac_softc *sc = ch->devinfo->codec->sc;
3095
3096 hdac_channel_setfragments(obj, data, blksz, sc->chan_blkcnt);
3097
3098 return (ch->blksz);
3099}
3100
3101static void
3102hdac_channel_stop(struct hdac_softc *sc, struct hdac_chan *ch)
3103{
3104 struct hdac_devinfo *devinfo = ch->devinfo;
3105 nid_t cad = devinfo->codec->cad;
3106 int i;
3107
3108 hdac_stream_stop(ch);
3109
3110 for (i = 0; ch->io[i] != -1; i++) {
3111 hdac_command(sc,
3112 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i],
3113 0), cad);
3114 }
3115}
3116
3117static void
3118hdac_channel_start(struct hdac_softc *sc, struct hdac_chan *ch)
3119{
3120 ch->ptr = 0;
3121 ch->prevptr = 0;
3122 hdac_stream_stop(ch);
3123 hdac_stream_reset(ch);
3124 hdac_bdl_setup(ch);
3125 hdac_stream_setid(ch);
3126 hdac_stream_setup(ch);
3127 hdac_stream_start(ch);
3128}
3129
3130static int
3131hdac_channel_trigger(kobj_t obj, void *data, int go)
3132{
3133 struct hdac_chan *ch = data;
3134 struct hdac_softc *sc = ch->devinfo->codec->sc;
3135
3136 if (!PCMTRIG_COMMON(go))
3137 return (0);
3138
3139 hdac_lock(sc);
3140 switch (go) {
3141 case PCMTRIG_START:
3142 hdac_channel_start(sc, ch);
3143 break;
3144 case PCMTRIG_STOP:
3145 case PCMTRIG_ABORT:
3146 hdac_channel_stop(sc, ch);
3147 break;
3148 default:
3149 break;
3150 }
3151 hdac_unlock(sc);
3152
3153 return (0);
3154}
3155
3156static int
3157hdac_channel_getptr(kobj_t obj, void *data)
3158{
3159 struct hdac_chan *ch = data;
3160 struct hdac_softc *sc = ch->devinfo->codec->sc;
3161 uint32_t ptr;
3162
3163 hdac_lock(sc);
3164 if (sc->polling != 0)
3165 ptr = ch->ptr;
3166 else if (ch->dmapos != NULL)
3167 ptr = *(ch->dmapos);
3168 else
3169 ptr = HDAC_READ_4(&sc->mem, ch->off + HDAC_SDLPIB);
3170 hdac_unlock(sc);
3171
3172 /*
3173 * Round to available space and force 128 bytes aligment.
3174 */
3175 ptr %= ch->blksz * ch->blkcnt;
3176 ptr &= HDA_BLK_ALIGN;
3177
3178 return (ptr);
3179}
3180
3181static struct pcmchan_caps *
3182hdac_channel_getcaps(kobj_t obj, void *data)
3183{
3184 return (&((struct hdac_chan *)data)->caps);
3185}
3186
3187static kobj_method_t hdac_channel_methods[] = {
3188 KOBJMETHOD(channel_init, hdac_channel_init),
3189 KOBJMETHOD(channel_setformat, hdac_channel_setformat),
3190 KOBJMETHOD(channel_setspeed, hdac_channel_setspeed),
3191 KOBJMETHOD(channel_setblocksize, hdac_channel_setblocksize),
3192 KOBJMETHOD(channel_setfragments, hdac_channel_setfragments),
3193 KOBJMETHOD(channel_trigger, hdac_channel_trigger),
3194 KOBJMETHOD(channel_getptr, hdac_channel_getptr),
3195 KOBJMETHOD(channel_getcaps, hdac_channel_getcaps),
3196 { 0, 0 }
3197};
3198CHANNEL_DECLARE(hdac_channel);
3199
3200static void
3201hdac_jack_poll_callback(void *arg)
3202{
3203 struct hdac_devinfo *devinfo = arg;
3204 struct hdac_softc *sc;
3205
3206 if (devinfo == NULL || devinfo->codec == NULL ||
3207 devinfo->codec->sc == NULL)
3208 return;
3209 sc = devinfo->codec->sc;
3210 hdac_lock(sc);
3211 if (sc->poll_ival == 0) {
3212 hdac_unlock(sc);
3213 return;
3214 }
3215 hdac_hp_switch_handler(devinfo);
3216 callout_reset(&sc->poll_jack, sc->poll_ival,
3217 hdac_jack_poll_callback, devinfo);
3218 hdac_unlock(sc);
3219}
3220
3221static int
3222hdac_audio_ctl_ossmixer_init(struct snd_mixer *m)
3223{
3224 struct hdac_devinfo *devinfo = mix_getdevinfo(m);
3225 struct hdac_softc *sc = devinfo->codec->sc;
3226 struct hdac_widget *w, *cw;
3227 struct hdac_audio_ctl *ctl;
3228 uint32_t mask, recmask, id;
3229 int i, j, softpcmvol;
3230 nid_t cad;
3231
3232 hdac_lock(sc);
3233
3234 mask = 0;
3235 recmask = 0;
3236
3237 id = hdac_codec_id(devinfo);
3238 cad = devinfo->codec->cad;
3239 for (i = 0; i < HDAC_HP_SWITCH_LEN; i++) {
3240 if (!(HDA_DEV_MATCH(hdac_hp_switch[i].model,
3241 sc->pci_subvendor) && hdac_hp_switch[i].id == id))
3242 continue;
3243 w = hdac_widget_get(devinfo, hdac_hp_switch[i].hpnid);
3244 if (w == NULL || w->enable == 0 || w->type !=
3245 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX)
3246 continue;
3247 if (hdac_hp_switch[i].polling != 0)
3248 callout_reset(&sc->poll_jack, 1,
3249 hdac_jack_poll_callback, devinfo);
3250 else if (HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(w->param.widget_cap))
3251 hdac_command(sc,
3252 HDA_CMD_SET_UNSOLICITED_RESPONSE(cad, w->nid,
3253 HDA_CMD_SET_UNSOLICITED_RESPONSE_ENABLE |
3254 HDAC_UNSOLTAG_EVENT_HP), cad);
3255 else
3256 continue;
3257 hdac_hp_switch_handler(devinfo);
3258 HDA_BOOTVERBOSE(
3259 device_printf(sc->dev,
3260 "HDA_DEBUG: Enabling headphone/speaker "
3261 "audio routing switching:\n");
3262 device_printf(sc->dev,
3263 "HDA_DEBUG: \tindex=%d nid=%d "
3264 "pci_subvendor=0x%08x "
3265 "codec=0x%08x [%s]\n",
3266 i, w->nid, sc->pci_subvendor, id,
3267 (hdac_hp_switch[i].polling != 0) ? "POLL" :
3268 "UNSOL");
3269 );
3270 break;
3271 }
3272 for (i = 0; i < HDAC_EAPD_SWITCH_LEN; i++) {
3273 if (!(HDA_DEV_MATCH(hdac_eapd_switch[i].model,
3274 sc->pci_subvendor) &&
3275 hdac_eapd_switch[i].id == id))
3276 continue;
3277 w = hdac_widget_get(devinfo, hdac_eapd_switch[i].eapdnid);
3278 if (w == NULL || w->enable == 0)
3279 break;
3280 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX ||
3281 w->param.eapdbtl == HDAC_INVALID)
3282 break;
3283 mask |= SOUND_MASK_OGAIN;
3284 break;
3285 }
3286
3287 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
3288 w = hdac_widget_get(devinfo, i);
3289 if (w == NULL || w->enable == 0)
3290 continue;
3291 mask |= w->ctlflags;
3292 if (!(w->pflags & HDA_ADC_RECSEL))
3293 continue;
3294 for (j = 0; j < w->nconns; j++) {
3295 cw = hdac_widget_get(devinfo, w->conns[j]);
3296 if (cw == NULL || cw->enable == 0)
3297 continue;
3298 recmask |= cw->ctlflags;
3299 }
3300 }
3301
3302 if (!(mask & SOUND_MASK_PCM)) {
3303 softpcmvol = 1;
3304 mask |= SOUND_MASK_PCM;
3305 } else
3306 softpcmvol = (devinfo->function.audio.quirks &
3307 HDA_QUIRK_SOFTPCMVOL) ? 1 : 0;
3308
3309 i = 0;
3310 ctl = NULL;
3311 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) {
3312 if (ctl->widget == NULL || ctl->enable == 0)
3313 continue;
3314 if (!(ctl->ossmask & SOUND_MASK_PCM))
3315 continue;
3316 if (ctl->step > 0)
3317 break;
3318 }
3319
3320 if (softpcmvol == 1 || ctl == NULL) {
3321 pcm_setflags(sc->dev, pcm_getflags(sc->dev) | SD_F_SOFTPCMVOL);
3322 HDA_BOOTVERBOSE(
3323 device_printf(sc->dev,
3324 "HDA_DEBUG: %s Soft PCM volume\n",
3325 (softpcmvol == 1) ?
3326 "Forcing" : "Enabling");
3327 );
3328 i = 0;
3329 /*
3330 * XXX Temporary quirk for STAC9220, until the parser
3331 * become smarter.
3332 */
3333 if (id == HDA_CODEC_STAC9220) {
3334 mask |= SOUND_MASK_VOLUME;
3335 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) !=
3336 NULL) {
3337 if (ctl->widget == NULL || ctl->enable == 0)
3338 continue;
3339 if (ctl->widget->nid == 11 && ctl->index == 0) {
3340 ctl->ossmask = SOUND_MASK_VOLUME;
3341 ctl->ossval = 100 | (100 << 8);
3342 } else
3343 ctl->ossmask &= ~SOUND_MASK_VOLUME;
3344 }
3345 } else if (id == HDA_CODEC_STAC9221) {
3346 mask |= SOUND_MASK_VOLUME;
3347 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) !=
3348 NULL) {
3349 if (ctl->widget == NULL)
3350 continue;
3351 if (ctl->widget->type ==
3352 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT &&
3353 ctl->index == 0 && (ctl->widget->nid == 2 ||
3354 ctl->widget->enable != 0)) {
3355 ctl->enable = 1;
3356 ctl->ossmask = SOUND_MASK_VOLUME;
3357 ctl->ossval = 100 | (100 << 8);
3358 } else if (ctl->enable == 0)
3359 continue;
3360 else
3361 ctl->ossmask &= ~SOUND_MASK_VOLUME;
3362 }
3363 } else {
3364 mix_setparentchild(m, SOUND_MIXER_VOLUME,
3365 SOUND_MASK_PCM);
3366 if (!(mask & SOUND_MASK_VOLUME))
3367 mix_setrealdev(m, SOUND_MIXER_VOLUME,
3368 SOUND_MIXER_NONE);
3369 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) !=
3370 NULL) {
3371 if (ctl->widget == NULL || ctl->enable == 0)
3372 continue;
3373 if (!HDA_FLAG_MATCH(ctl->ossmask,
3374 SOUND_MASK_VOLUME | SOUND_MASK_PCM))
3375 continue;
3376 if (!(ctl->mute == 1 && ctl->step == 0))
3377 ctl->enable = 0;
3378 }
3379 }
3380 }
3381
3382 recmask &= ~(SOUND_MASK_PCM | SOUND_MASK_RECLEV | SOUND_MASK_SPEAKER |
3383 SOUND_MASK_BASS | SOUND_MASK_TREBLE | SOUND_MASK_IGAIN |
3384 SOUND_MASK_OGAIN);
3385 recmask &= (1 << SOUND_MIXER_NRDEVICES) - 1;
3386 mask &= (1 << SOUND_MIXER_NRDEVICES) - 1;
3387
3388 mix_setrecdevs(m, recmask);
3389 mix_setdevs(m, mask);
3390
3391 hdac_unlock(sc);
3392
3393 return (0);
3394}
3395
3396static int
3397hdac_audio_ctl_ossmixer_set(struct snd_mixer *m, unsigned dev,
3398 unsigned left, unsigned right)
3399{
3400 struct hdac_devinfo *devinfo = mix_getdevinfo(m);
3401 struct hdac_softc *sc = devinfo->codec->sc;
3402 struct hdac_widget *w;
3403 struct hdac_audio_ctl *ctl;
3404 uint32_t id, mute;
3405 int lvol, rvol, mlvol, mrvol;
3406 int i = 0;
3407
3408 hdac_lock(sc);
3409 if (dev == SOUND_MIXER_OGAIN) {
3410 uint32_t orig;
3411 /*if (left != right || !(left == 0 || left == 1)) {
3412 hdac_unlock(sc);
3413 return (-1);
3414 }*/
3415 id = hdac_codec_id(devinfo);
3416 for (i = 0; i < HDAC_EAPD_SWITCH_LEN; i++) {
3417 if (HDA_DEV_MATCH(hdac_eapd_switch[i].model,
3418 sc->pci_subvendor) &&
3419 hdac_eapd_switch[i].id == id)
3420 break;
3421 }
3422 if (i >= HDAC_EAPD_SWITCH_LEN) {
3423 hdac_unlock(sc);
3424 return (-1);
3425 }
3426 w = hdac_widget_get(devinfo, hdac_eapd_switch[i].eapdnid);
3427 if (w == NULL ||
3428 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX ||
3429 w->param.eapdbtl == HDAC_INVALID) {
3430 hdac_unlock(sc);
3431 return (-1);
3432 }
3433 orig = w->param.eapdbtl;
3434 if (left == 0)
3435 w->param.eapdbtl &= ~HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD;
3436 else
3437 w->param.eapdbtl |= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD;
3438 if (orig != w->param.eapdbtl) {
3439 uint32_t val;
3440
3441 if (hdac_eapd_switch[i].hp_switch != 0)
3442 hdac_hp_switch_handler(devinfo);
3443 val = w->param.eapdbtl;
3444 if (devinfo->function.audio.quirks & HDA_QUIRK_EAPDINV)
3445 val ^= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD;
3446 hdac_command(sc,
3447 HDA_CMD_SET_EAPD_BTL_ENABLE(devinfo->codec->cad,
3448 w->nid, val), devinfo->codec->cad);
3449 }
3450 hdac_unlock(sc);
3451 return (left | (left << 8));
3452 }
3453 if (dev == SOUND_MIXER_VOLUME)
3454 devinfo->function.audio.mvol = left | (right << 8);
3455
3456 mlvol = devinfo->function.audio.mvol & 0x7f;
3457 mrvol = (devinfo->function.audio.mvol >> 8) & 0x7f;
3458 lvol = 0;
3459 rvol = 0;
3460
3461 i = 0;
3462 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) {
3463 if (ctl->widget == NULL || ctl->enable == 0 ||
3464 !(ctl->ossmask & (1 << dev)))
3465 continue;
3466 switch (dev) {
3467 case SOUND_MIXER_VOLUME:
3468 lvol = ((ctl->ossval & 0x7f) * left) / 100;
3469 lvol = (lvol * ctl->step) / 100;
3470 rvol = (((ctl->ossval >> 8) & 0x7f) * right) / 100;
3471 rvol = (rvol * ctl->step) / 100;
3472 break;
3473 default:
3474 if (ctl->ossmask & SOUND_MASK_VOLUME) {
3475 lvol = (left * mlvol) / 100;
3476 lvol = (lvol * ctl->step) / 100;
3477 rvol = (right * mrvol) / 100;
3478 rvol = (rvol * ctl->step) / 100;
3479 } else {
3480 lvol = (left * ctl->step) / 100;
3481 rvol = (right * ctl->step) / 100;
3482 }
3483 ctl->ossval = left | (right << 8);
3484 break;
3485 }
3486 mute = 0;
3487 if (ctl->step < 1) {
3488 mute |= (left == 0) ? HDA_AMP_MUTE_LEFT :
3489 (ctl->muted & HDA_AMP_MUTE_LEFT);
3490 mute |= (right == 0) ? HDA_AMP_MUTE_RIGHT :
3491 (ctl->muted & HDA_AMP_MUTE_RIGHT);
3492 } else {
3493 mute |= (lvol == 0) ? HDA_AMP_MUTE_LEFT :
3494 (ctl->muted & HDA_AMP_MUTE_LEFT);
3495 mute |= (rvol == 0) ? HDA_AMP_MUTE_RIGHT :
3496 (ctl->muted & HDA_AMP_MUTE_RIGHT);
3497 }
3498 hdac_audio_ctl_amp_set(ctl, mute, lvol, rvol);
3499 }
3500 hdac_unlock(sc);
3501
3502 return (left | (right << 8));
3503}
3504
3505static int
3506hdac_audio_ctl_ossmixer_setrecsrc(struct snd_mixer *m, uint32_t src)
3507{
3508 struct hdac_devinfo *devinfo = mix_getdevinfo(m);
3509 struct hdac_widget *w, *cw;
3510 struct hdac_softc *sc = devinfo->codec->sc;
3511 uint32_t ret = src, target;
3512 int i, j;
3513
3514 target = 0;
3515 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) {
3516 if (src & (1 << i)) {
3517 target = 1 << i;
3518 break;
3519 }
3520 }
3521
3522 hdac_lock(sc);
3523
3524 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
3525 w = hdac_widget_get(devinfo, i);
3526 if (w == NULL || w->enable == 0)
3527 continue;
3528 if (!(w->pflags & HDA_ADC_RECSEL))
3529 continue;
3530 for (j = 0; j < w->nconns; j++) {
3531 cw = hdac_widget_get(devinfo, w->conns[j]);
3532 if (cw == NULL || cw->enable == 0)
3533 continue;
3534 if ((target == SOUND_MASK_VOLUME &&
3535 cw->type !=
3536 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) ||
3537 (target != SOUND_MASK_VOLUME &&
3538 cw->type ==
3539 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER))
3540 continue;
3541 if (cw->ctlflags & target) {
3542 if (!(w->pflags & HDA_ADC_LOCKED))
3543 hdac_widget_connection_select(w, j);
3544 ret = target;
3545 j += w->nconns;
3546 }
3547 }
3548 }
3549
3550 hdac_unlock(sc);
3551
3552 return (ret);
3553}
3554
3555static kobj_method_t hdac_audio_ctl_ossmixer_methods[] = {
3556 KOBJMETHOD(mixer_init, hdac_audio_ctl_ossmixer_init),
3557 KOBJMETHOD(mixer_set, hdac_audio_ctl_ossmixer_set),
3558 KOBJMETHOD(mixer_setrecsrc, hdac_audio_ctl_ossmixer_setrecsrc),
3559 { 0, 0 }
3560};
3561MIXER_DECLARE(hdac_audio_ctl_ossmixer);
3562
3563/****************************************************************************
3564 * int hdac_attach(device_t)
3565 *
3566 * Attach the device into the kernel. Interrupts usually won't be enabled
3567 * when this function is called. Setup everything that doesn't require
3568 * interrupts and defer probing of codecs until interrupts are enabled.
3569 ****************************************************************************/
3570static int
3571hdac_attach(device_t dev)
3572{
3573 struct hdac_softc *sc;
3574 int result;
3575 int i;
3576 uint16_t vendor;
3577 uint8_t v;
3578
|
3580 sc->lock = snd_mtxcreate(device_get_nameunit(dev), HDAC_MTX_NAME);
3581 sc->dev = dev;
3582 sc->pci_subvendor = (uint32_t)pci_get_subdevice(sc->dev) << 16;
3583 sc->pci_subvendor |= (uint32_t)pci_get_subvendor(sc->dev) & 0x0000ffff;
3584 vendor = pci_get_vendor(dev);
3585
3586 if (sc->pci_subvendor == HP_NX6325_SUBVENDORX) {
3587 /* Screw nx6325 - subdevice/subvendor swapped */
3588 sc->pci_subvendor = HP_NX6325_SUBVENDOR;
3589 }
3590
3591 callout_init(&sc->poll_hda, CALLOUT_MPSAFE);
3592 callout_init(&sc->poll_hdac, CALLOUT_MPSAFE);
3593 callout_init(&sc->poll_jack, CALLOUT_MPSAFE);
3594
3595 sc->poll_ticks = 1;
3596 sc->poll_ival = HDAC_POLL_INTERVAL;
3597 if (resource_int_value(device_get_name(dev),
3598 device_get_unit(dev), "polling", &i) == 0 && i != 0)
3599 sc->polling = 1;
3600 else
3601 sc->polling = 0;
3602
3603 sc->chan_size = pcm_getbuffersize(dev,
3604 HDA_BUFSZ_MIN, HDA_BUFSZ_DEFAULT, HDA_BUFSZ_MAX);
3605
3606 if (resource_int_value(device_get_name(dev),
3607 device_get_unit(dev), "blocksize", &i) == 0 && i > 0) {
3608 i &= HDA_BLK_ALIGN;
3609 if (i < HDA_BLK_MIN)
3610 i = HDA_BLK_MIN;
3611 sc->chan_blkcnt = sc->chan_size / i;
3612 i = 0;
3613 while (sc->chan_blkcnt >> i)
3614 i++;
3615 sc->chan_blkcnt = 1 << (i - 1);
3616 if (sc->chan_blkcnt < HDA_BDL_MIN)
3617 sc->chan_blkcnt = HDA_BDL_MIN;
3618 else if (sc->chan_blkcnt > HDA_BDL_MAX)
3619 sc->chan_blkcnt = HDA_BDL_MAX;
3620 } else
3621 sc->chan_blkcnt = HDA_BDL_DEFAULT;
3622
3623 result = bus_dma_tag_create(NULL, /* parent */
3624 HDAC_DMA_ALIGNMENT, /* alignment */
3625 0, /* boundary */
3626 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
3627 BUS_SPACE_MAXADDR, /* highaddr */
3628 NULL, /* filtfunc */
3629 NULL, /* fistfuncarg */
3630 sc->chan_size, /* maxsize */
3631 1, /* nsegments */
3632 sc->chan_size, /* maxsegsz */
3633 0, /* flags */
3634 NULL, /* lockfunc */
3635 NULL, /* lockfuncarg */
3636 &sc->chan_dmat); /* dmat */
3637 if (result != 0) {
3638 device_printf(dev, "%s: bus_dma_tag_create failed (%x)\n",
3639 __func__, result);
3640 snd_mtxfree(sc->lock);
3641 free(sc, M_DEVBUF);
3642 return (ENXIO);
3643 }
3644
3645
3646 sc->hdabus = NULL;
3647 for (i = 0; i < HDAC_CODEC_MAX; i++)
3648 sc->codecs[i] = NULL;
3649
3650 pci_enable_busmaster(dev);
3651
3652 if (vendor == INTEL_VENDORID) {
3653 /* TCSEL -> TC0 */
3654 v = pci_read_config(dev, 0x44, 1);
3655 pci_write_config(dev, 0x44, v & 0xf8, 1);
3656 HDA_BOOTVERBOSE(
3657 device_printf(dev, "TCSEL: 0x%02d -> 0x%02d\n", v,
3658 pci_read_config(dev, 0x44, 1));
3659 );
3660 }
3661
3662#if defined(__i386__) || defined(__amd64__)
3663 sc->nocache = 1;
3664
3665 if (resource_int_value(device_get_name(dev),
3666 device_get_unit(dev), "snoop", &i) == 0 && i != 0) {
3667#else
3668 sc->nocache = 0;
3669#endif
3670 /*
3671 * Try to enable PCIe snoop to avoid messing around with
3672 * uncacheable DMA attribute. Since PCIe snoop register
3673 * config is pretty much vendor specific, there are no
3674 * general solutions on how to enable it, forcing us (even
3675 * Microsoft) to enable uncacheable or write combined DMA
3676 * by default.
3677 *
3678 * http://msdn2.microsoft.com/en-us/library/ms790324.aspx
3679 */
3680 for (i = 0; i < HDAC_PCIESNOOP_LEN; i++) {
3681 if (hdac_pcie_snoop[i].vendor != vendor)
3682 continue;
3683 sc->nocache = 0;
3684 if (hdac_pcie_snoop[i].reg == 0x00)
3685 break;
3686 v = pci_read_config(dev, hdac_pcie_snoop[i].reg, 1);
3687 if ((v & hdac_pcie_snoop[i].enable) ==
3688 hdac_pcie_snoop[i].enable)
3689 break;
3690 v &= hdac_pcie_snoop[i].mask;
3691 v |= hdac_pcie_snoop[i].enable;
3692 pci_write_config(dev, hdac_pcie_snoop[i].reg, v, 1);
3693 v = pci_read_config(dev, hdac_pcie_snoop[i].reg, 1);
3694 if ((v & hdac_pcie_snoop[i].enable) !=
3695 hdac_pcie_snoop[i].enable) {
3696 HDA_BOOTVERBOSE(
3697 device_printf(dev,
3698 "WARNING: Failed to enable PCIe "
3699 "snoop!\n");
3700 );
3701#if defined(__i386__) || defined(__amd64__)
3702 sc->nocache = 1;
3703#endif
3704 }
3705 break;
3706 }
3707#if defined(__i386__) || defined(__amd64__)
3708 }
3709#endif
3710
3711 HDA_BOOTVERBOSE(
3712 device_printf(dev, "DMA Coherency: %s / vendor=0x%04x\n",
3713 (sc->nocache == 0) ? "PCIe snoop" : "Uncacheable", vendor);
3714 );
3715
3716 /* Allocate resources */
3717 result = hdac_mem_alloc(sc);
3718 if (result != 0)
3719 goto hdac_attach_fail;
3720 result = hdac_irq_alloc(sc);
3721 if (result != 0)
3722 goto hdac_attach_fail;
3723
3724 /* Get Capabilities */
3725 result = hdac_get_capabilities(sc);
3726 if (result != 0)
3727 goto hdac_attach_fail;
3728
3729 /* Allocate CORB and RIRB dma memory */
3730 result = hdac_dma_alloc(sc, &sc->corb_dma,
3731 sc->corb_size * sizeof(uint32_t));
3732 if (result != 0)
3733 goto hdac_attach_fail;
3734 result = hdac_dma_alloc(sc, &sc->rirb_dma,
3735 sc->rirb_size * sizeof(struct hdac_rirb));
3736 if (result != 0)
3737 goto hdac_attach_fail;
3738
3739 /* Quiesce everything */
3740 hdac_reset(sc);
3741
3742 /* Initialize the CORB and RIRB */
3743 hdac_corb_init(sc);
3744 hdac_rirb_init(sc);
3745
3746 /* Defer remaining of initialization until interrupts are enabled */
3747 sc->intrhook.ich_func = hdac_attach2;
3748 sc->intrhook.ich_arg = (void *)sc;
3749 if (cold == 0 || config_intrhook_establish(&sc->intrhook) != 0) {
3750 sc->intrhook.ich_func = NULL;
3751 hdac_attach2((void *)sc);
3752 }
3753
3754 return (0);
3755
3756hdac_attach_fail:
3757 hdac_irq_free(sc);
3758 hdac_dma_free(sc, &sc->rirb_dma);
3759 hdac_dma_free(sc, &sc->corb_dma);
3760 hdac_mem_free(sc);
3761 snd_mtxfree(sc->lock);
3762 free(sc, M_DEVBUF);
3763
3764 return (ENXIO);
3765}
3766
3767static void
3768hdac_audio_parse(struct hdac_devinfo *devinfo)
3769{
3770 struct hdac_softc *sc = devinfo->codec->sc;
3771 struct hdac_widget *w;
3772 uint32_t res;
3773 int i;
3774 nid_t cad, nid;
3775
3776 cad = devinfo->codec->cad;
3777 nid = devinfo->nid;
3778
3779 hdac_command(sc,
3780 HDA_CMD_SET_POWER_STATE(cad, nid, HDA_CMD_POWER_STATE_D0), cad);
3781
3782 DELAY(100);
3783
3784 res = hdac_command(sc,
3785 HDA_CMD_GET_PARAMETER(cad , nid, HDA_PARAM_SUB_NODE_COUNT), cad);
3786
3787 devinfo->nodecnt = HDA_PARAM_SUB_NODE_COUNT_TOTAL(res);
3788 devinfo->startnode = HDA_PARAM_SUB_NODE_COUNT_START(res);
3789 devinfo->endnode = devinfo->startnode + devinfo->nodecnt;
3790
3791 res = hdac_command(sc,
3792 HDA_CMD_GET_PARAMETER(cad , nid, HDA_PARAM_GPIO_COUNT), cad);
3793 devinfo->function.audio.gpio = res;
3794
3795 HDA_BOOTVERBOSE(
3796 device_printf(sc->dev, " Vendor: 0x%08x\n",
3797 devinfo->vendor_id);
3798 device_printf(sc->dev, " Device: 0x%08x\n",
3799 devinfo->device_id);
3800 device_printf(sc->dev, " Revision: 0x%08x\n",
3801 devinfo->revision_id);
3802 device_printf(sc->dev, " Stepping: 0x%08x\n",
3803 devinfo->stepping_id);
3804 device_printf(sc->dev, "PCI Subvendor: 0x%08x\n",
3805 sc->pci_subvendor);
3806 device_printf(sc->dev, " Nodes: start=%d "
3807 "endnode=%d total=%d\n",
3808 devinfo->startnode, devinfo->endnode, devinfo->nodecnt);
3809 device_printf(sc->dev, " CORB size: %d\n", sc->corb_size);
3810 device_printf(sc->dev, " RIRB size: %d\n", sc->rirb_size);
3811 device_printf(sc->dev, " Streams: ISS=%d OSS=%d BSS=%d\n",
3812 sc->num_iss, sc->num_oss, sc->num_bss);
3813 device_printf(sc->dev, " GPIO: 0x%08x\n",
3814 devinfo->function.audio.gpio);
3815 device_printf(sc->dev, " NumGPIO=%d NumGPO=%d "
3816 "NumGPI=%d GPIWake=%d GPIUnsol=%d\n",
3817 HDA_PARAM_GPIO_COUNT_NUM_GPIO(devinfo->function.audio.gpio),
3818 HDA_PARAM_GPIO_COUNT_NUM_GPO(devinfo->function.audio.gpio),
3819 HDA_PARAM_GPIO_COUNT_NUM_GPI(devinfo->function.audio.gpio),
3820 HDA_PARAM_GPIO_COUNT_GPI_WAKE(devinfo->function.audio.gpio),
3821 HDA_PARAM_GPIO_COUNT_GPI_UNSOL(devinfo->function.audio.gpio));
3822 );
3823
3824 res = hdac_command(sc,
3825 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_SUPP_STREAM_FORMATS),
3826 cad);
3827 devinfo->function.audio.supp_stream_formats = res;
3828
3829 res = hdac_command(sc,
3830 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_SUPP_PCM_SIZE_RATE),
3831 cad);
3832 devinfo->function.audio.supp_pcm_size_rate = res;
3833
3834 res = hdac_command(sc,
3835 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_OUTPUT_AMP_CAP),
3836 cad);
3837 devinfo->function.audio.outamp_cap = res;
3838
3839 res = hdac_command(sc,
3840 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_INPUT_AMP_CAP),
3841 cad);
3842 devinfo->function.audio.inamp_cap = res;
3843
3844 if (devinfo->nodecnt > 0)
3845 devinfo->widget = (struct hdac_widget *)malloc(
3846 sizeof(*(devinfo->widget)) * devinfo->nodecnt, M_HDAC,
3847 M_NOWAIT | M_ZERO);
3848 else
3849 devinfo->widget = NULL;
3850
3851 if (devinfo->widget == NULL) {
3852 device_printf(sc->dev, "unable to allocate widgets!\n");
3853 devinfo->endnode = devinfo->startnode;
3854 devinfo->nodecnt = 0;
3855 return;
3856 }
3857
3858 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
3859 w = hdac_widget_get(devinfo, i);
3860 if (w == NULL)
3861 device_printf(sc->dev, "Ghost widget! nid=%d!\n", i);
3862 else {
3863 w->devinfo = devinfo;
3864 w->nid = i;
3865 w->enable = 1;
3866 w->selconn = -1;
3867 w->pflags = 0;
3868 w->ctlflags = 0;
3869 w->param.eapdbtl = HDAC_INVALID;
3870 hdac_widget_parse(w);
3871 }
3872 }
3873}
3874
3875static void
3876hdac_audio_ctl_parse(struct hdac_devinfo *devinfo)
3877{
3878 struct hdac_softc *sc = devinfo->codec->sc;
3879 struct hdac_audio_ctl *ctls;
3880 struct hdac_widget *w, *cw;
3881 int i, j, cnt, max, ocap, icap;
3882 int mute, offset, step, size;
3883
3884 /* XXX This is redundant */
3885 max = 0;
3886 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
3887 w = hdac_widget_get(devinfo, i);
3888 if (w == NULL || w->enable == 0)
3889 continue;
3890 if (w->param.outamp_cap != 0)
3891 max++;
3892 if (w->param.inamp_cap != 0) {
3893 switch (w->type) {
3894 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR:
3895 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER:
3896 for (j = 0; j < w->nconns; j++) {
3897 cw = hdac_widget_get(devinfo,
3898 w->conns[j]);
3899 if (cw == NULL || cw->enable == 0)
3900 continue;
3901 max++;
3902 }
3903 break;
3904 default:
3905 max++;
3906 break;
3907 }
3908 }
3909 }
3910
3911 devinfo->function.audio.ctlcnt = max;
3912
3913 if (max < 1)
3914 return;
3915
3916 ctls = (struct hdac_audio_ctl *)malloc(
3917 sizeof(*ctls) * max, M_HDAC, M_ZERO | M_NOWAIT);
3918
3919 if (ctls == NULL) {
3920 /* Blekh! */
3921 device_printf(sc->dev, "unable to allocate ctls!\n");
3922 devinfo->function.audio.ctlcnt = 0;
3923 return;
3924 }
3925
3926 cnt = 0;
3927 for (i = devinfo->startnode; cnt < max && i < devinfo->endnode; i++) {
3928 if (cnt >= max) {
3929 device_printf(sc->dev, "%s: Ctl overflow!\n",
3930 __func__);
3931 break;
3932 }
3933 w = hdac_widget_get(devinfo, i);
3934 if (w == NULL || w->enable == 0)
3935 continue;
3936 ocap = w->param.outamp_cap;
3937 icap = w->param.inamp_cap;
3938 if (ocap != 0) {
3939 mute = HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(ocap);
3940 step = HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(ocap);
3941 size = HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(ocap);
3942 offset = HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(ocap);
3943 /*if (offset > step) {
3944 HDA_BOOTVERBOSE(
3945 device_printf(sc->dev,
3946 "HDA_DEBUG: BUGGY outamp: nid=%d "
3947 "[offset=%d > step=%d]\n",
3948 w->nid, offset, step);
3949 );
3950 offset = step;
3951 }*/
3952 ctls[cnt].enable = 1;
3953 ctls[cnt].widget = w;
3954 ctls[cnt].mute = mute;
3955 ctls[cnt].step = step;
3956 ctls[cnt].size = size;
3957 ctls[cnt].offset = offset;
3958 ctls[cnt].left = offset;
3959 ctls[cnt].right = offset;
3960 ctls[cnt++].dir = HDA_CTL_OUT;
3961 }
3962
3963 if (icap != 0) {
3964 mute = HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(icap);
3965 step = HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(icap);
3966 size = HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(icap);
3967 offset = HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(icap);
3968 /*if (offset > step) {
3969 HDA_BOOTVERBOSE(
3970 device_printf(sc->dev,
3971 "HDA_DEBUG: BUGGY inamp: nid=%d "
3972 "[offset=%d > step=%d]\n",
3973 w->nid, offset, step);
3974 );
3975 offset = step;
3976 }*/
3977 switch (w->type) {
3978 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR:
3979 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER:
3980 for (j = 0; j < w->nconns; j++) {
3981 if (cnt >= max) {
3982 device_printf(sc->dev,
3983 "%s: Ctl overflow!\n",
3984 __func__);
3985 break;
3986 }
3987 cw = hdac_widget_get(devinfo,
3988 w->conns[j]);
3989 if (cw == NULL || cw->enable == 0)
3990 continue;
3991 ctls[cnt].enable = 1;
3992 ctls[cnt].widget = w;
3993 ctls[cnt].childwidget = cw;
3994 ctls[cnt].index = j;
3995 ctls[cnt].mute = mute;
3996 ctls[cnt].step = step;
3997 ctls[cnt].size = size;
3998 ctls[cnt].offset = offset;
3999 ctls[cnt].left = offset;
4000 ctls[cnt].right = offset;
4001 ctls[cnt++].dir = HDA_CTL_IN;
4002 }
4003 break;
4004 default:
4005 if (cnt >= max) {
4006 device_printf(sc->dev,
4007 "%s: Ctl overflow!\n",
4008 __func__);
4009 break;
4010 }
4011 ctls[cnt].enable = 1;
4012 ctls[cnt].widget = w;
4013 ctls[cnt].mute = mute;
4014 ctls[cnt].step = step;
4015 ctls[cnt].size = size;
4016 ctls[cnt].offset = offset;
4017 ctls[cnt].left = offset;
4018 ctls[cnt].right = offset;
4019 ctls[cnt++].dir = HDA_CTL_IN;
4020 break;
4021 }
4022 }
4023 }
4024
4025 devinfo->function.audio.ctl = ctls;
4026}
4027
4028static const struct {
4029 uint32_t model;
4030 uint32_t id;
4031 uint32_t set, unset;
4032} hdac_quirks[] = {
4033 /*
4034 * XXX Force stereo quirk. Monoural recording / playback
4035 * on few codecs (especially ALC880) seems broken or
4036 * perhaps unsupported.
4037 */
4038 { HDA_MATCH_ALL, HDA_MATCH_ALL,
4039 HDA_QUIRK_FORCESTEREO | HDA_QUIRK_IVREF, 0 },
4040 { ACER_ALL_SUBVENDOR, HDA_MATCH_ALL,
4041 HDA_QUIRK_GPIO0, 0 },
4042 { ASUS_M5200_SUBVENDOR, HDA_CODEC_ALC880,
4043 HDA_QUIRK_GPIO0, 0 },
4044 { ASUS_A7M_SUBVENDOR, HDA_CODEC_ALC880,
4045 HDA_QUIRK_GPIO0, 0 },
4046 { ASUS_A7T_SUBVENDOR, HDA_CODEC_ALC882,
4047 HDA_QUIRK_GPIO0, 0 },
4048 { ASUS_W2J_SUBVENDOR, HDA_CODEC_ALC882,
4049 HDA_QUIRK_GPIO0, 0 },
4050 { ASUS_U5F_SUBVENDOR, HDA_CODEC_AD1986A,
4051 HDA_QUIRK_EAPDINV, 0 },
4052 { ASUS_A8JC_SUBVENDOR, HDA_CODEC_AD1986A,
4053 HDA_QUIRK_EAPDINV, 0 },
4054 { ASUS_F3JC_SUBVENDOR, HDA_CODEC_ALC861,
4055 HDA_QUIRK_OVREF, 0 },
4056 { ASUS_W6F_SUBVENDOR, HDA_CODEC_ALC861,
4057 HDA_QUIRK_OVREF, 0 },
4058 { UNIWILL_9075_SUBVENDOR, HDA_CODEC_ALC861,
4059 HDA_QUIRK_OVREF, 0 },
4060 /*{ ASUS_M2N_SUBVENDOR, HDA_CODEC_AD1988,
4061 HDA_QUIRK_IVREF80, HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF100 },*/
4062 { MEDION_MD95257_SUBVENDOR, HDA_CODEC_ALC880,
4063 HDA_QUIRK_GPIO1, 0 },
4064 { LENOVO_3KN100_SUBVENDOR, HDA_CODEC_AD1986A,
4065 HDA_QUIRK_EAPDINV, 0 },
4066 { SAMSUNG_Q1_SUBVENDOR, HDA_CODEC_AD1986A,
4067 HDA_QUIRK_EAPDINV, 0 },
4068 { APPLE_INTEL_MAC, HDA_CODEC_STAC9221,
4069 HDA_QUIRK_GPIO0 | HDA_QUIRK_GPIO1, 0 },
4070 { HDA_MATCH_ALL, HDA_CODEC_AD1988,
4071 HDA_QUIRK_IVREF80, HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF100 },
4072 { HDA_MATCH_ALL, HDA_CODEC_AD1988B,
4073 HDA_QUIRK_IVREF80, HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF100 },
4074 { HDA_MATCH_ALL, HDA_CODEC_CXVENICE,
4075 0, HDA_QUIRK_FORCESTEREO },
4076 { HDA_MATCH_ALL, HDA_CODEC_STACXXXX,
4077 HDA_QUIRK_SOFTPCMVOL, 0 }
4078};
4079#define HDAC_QUIRKS_LEN (sizeof(hdac_quirks) / sizeof(hdac_quirks[0]))
4080
4081static void
4082hdac_vendor_patch_parse(struct hdac_devinfo *devinfo)
4083{
4084 struct hdac_widget *w;
4085 struct hdac_audio_ctl *ctl;
4086 uint32_t id, subvendor;
4087 int i;
4088
4089 id = hdac_codec_id(devinfo);
4090 subvendor = devinfo->codec->sc->pci_subvendor;
4091
4092 /*
4093 * Quirks
4094 */
4095 for (i = 0; i < HDAC_QUIRKS_LEN; i++) {
4096 if (!(HDA_DEV_MATCH(hdac_quirks[i].model, subvendor) &&
4097 HDA_DEV_MATCH(hdac_quirks[i].id, id)))
4098 continue;
4099 if (hdac_quirks[i].set != 0)
4100 devinfo->function.audio.quirks |=
4101 hdac_quirks[i].set;
4102 if (hdac_quirks[i].unset != 0)
4103 devinfo->function.audio.quirks &=
4104 ~(hdac_quirks[i].unset);
4105 }
4106
4107 switch (id) {
4108 case HDA_CODEC_ALC260:
4109 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
4110 w = hdac_widget_get(devinfo, i);
4111 if (w == NULL || w->enable == 0)
4112 continue;
4113 if (w->type !=
4114 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT)
4115 continue;
4116 if (w->nid != 5)
4117 w->enable = 0;
4118 }
4119 if (subvendor == HP_XW4300_SUBVENDOR) {
4120 ctl = hdac_audio_ctl_amp_get(devinfo, 16, 0, 1);
4121 if (ctl != NULL && ctl->widget != NULL) {
4122 ctl->ossmask = SOUND_MASK_SPEAKER;
4123 ctl->widget->ctlflags |= SOUND_MASK_SPEAKER;
4124 }
4125 ctl = hdac_audio_ctl_amp_get(devinfo, 17, 0, 1);
4126 if (ctl != NULL && ctl->widget != NULL) {
4127 ctl->ossmask = SOUND_MASK_SPEAKER;
4128 ctl->widget->ctlflags |= SOUND_MASK_SPEAKER;
4129 }
4130 } else if (subvendor == HP_3010_SUBVENDOR) {
4131 ctl = hdac_audio_ctl_amp_get(devinfo, 17, 0, 1);
4132 if (ctl != NULL && ctl->widget != NULL) {
4133 ctl->ossmask = SOUND_MASK_SPEAKER;
4134 ctl->widget->ctlflags |= SOUND_MASK_SPEAKER;
4135 }
4136 ctl = hdac_audio_ctl_amp_get(devinfo, 21, 0, 1);
4137 if (ctl != NULL && ctl->widget != NULL) {
4138 ctl->ossmask = SOUND_MASK_SPEAKER;
4139 ctl->widget->ctlflags |= SOUND_MASK_SPEAKER;
4140 }
4141 }
4142 break;
4143 case HDA_CODEC_ALC861:
4144 ctl = hdac_audio_ctl_amp_get(devinfo, 21, 2, 1);
4145 if (ctl != NULL)
4146 ctl->muted = HDA_AMP_MUTE_ALL;
4147 break;
4148 case HDA_CODEC_ALC880:
4149 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
4150 w = hdac_widget_get(devinfo, i);
4151 if (w == NULL || w->enable == 0)
4152 continue;
4153 if (w->type ==
4154 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT &&
4155 w->nid != 9 && w->nid != 29) {
4156 w->enable = 0;
4157 } else if (w->type !=
4158 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET &&
4159 w->nid == 29) {
4160 w->type =
4161 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET;
4162 w->param.widget_cap &=
4163 ~HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_MASK;
4164 w->param.widget_cap |=
4165 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET <<
4166 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_SHIFT;
4167 strlcpy(w->name, "beep widget", sizeof(w->name));
4168 }
4169 }
4170 break;
4171 case HDA_CODEC_ALC883:
4172 /*
4173 * nid: 24/25 = External (jack) or Internal (fixed) Mic.
4174 * Clear vref cap for jack connectivity.
4175 */
4176 w = hdac_widget_get(devinfo, 24);
4177 if (w != NULL && w->enable != 0 && w->type ==
4178 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX &&
4179 (w->wclass.pin.config &
4180 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) ==
4181 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK)
4182 w->wclass.pin.cap &= ~(
4183 HDA_PARAM_PIN_CAP_VREF_CTRL_100_MASK |
4184 HDA_PARAM_PIN_CAP_VREF_CTRL_80_MASK |
4185 HDA_PARAM_PIN_CAP_VREF_CTRL_50_MASK);
4186 w = hdac_widget_get(devinfo, 25);
4187 if (w != NULL && w->enable != 0 && w->type ==
4188 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX &&
4189 (w->wclass.pin.config &
4190 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) ==
4191 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK)
4192 w->wclass.pin.cap &= ~(
4193 HDA_PARAM_PIN_CAP_VREF_CTRL_100_MASK |
4194 HDA_PARAM_PIN_CAP_VREF_CTRL_80_MASK |
4195 HDA_PARAM_PIN_CAP_VREF_CTRL_50_MASK);
4196 /*
4197 * nid: 26 = Line-in, leave it alone.
4198 */
4199 break;
4200 case HDA_CODEC_AD1981HD:
4201 w = hdac_widget_get(devinfo, 11);
4202 if (w != NULL && w->enable != 0 && w->nconns > 3)
4203 w->selconn = 3;
4204 if (subvendor == IBM_M52_SUBVENDOR) {
4205 ctl = hdac_audio_ctl_amp_get(devinfo, 7, 0, 1);
4206 if (ctl != NULL)
4207 ctl->ossmask = SOUND_MASK_SPEAKER;
4208 }
4209 break;
4210 case HDA_CODEC_AD1986A:
4211 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
4212 w = hdac_widget_get(devinfo, i);
4213 if (w == NULL || w->enable == 0)
4214 continue;
4215 if (w->type !=
4216 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT)
4217 continue;
4218 if (w->nid != 3)
4219 w->enable = 0;
4220 }
4221 if (subvendor == ASUS_M2NPVMX_SUBVENDOR) {
4222 /* nid 28 is mic, nid 29 is line-in */
4223 w = hdac_widget_get(devinfo, 15);
4224 if (w != NULL)
4225 w->selconn = 2;
4226 w = hdac_widget_get(devinfo, 16);
4227 if (w != NULL)
4228 w->selconn = 1;
4229 }
4230 break;
4231 case HDA_CODEC_AD1988:
4232 case HDA_CODEC_AD1988B:
4233 /*w = hdac_widget_get(devinfo, 12);
4234 if (w != NULL) {
4235 w->selconn = 1;
4236 w->pflags |= HDA_ADC_LOCKED;
4237 }
4238 w = hdac_widget_get(devinfo, 13);
4239 if (w != NULL) {
4240 w->selconn = 4;
4241 w->pflags |= HDA_ADC_LOCKED;
4242 }
4243 w = hdac_widget_get(devinfo, 14);
4244 if (w != NULL) {
4245 w->selconn = 2;
4246 w->pflags |= HDA_ADC_LOCKED;
4247 }*/
4248 ctl = hdac_audio_ctl_amp_get(devinfo, 57, 0, 1);
4249 if (ctl != NULL) {
4250 ctl->ossmask = SOUND_MASK_IGAIN;
4251 ctl->widget->ctlflags |= SOUND_MASK_IGAIN;
4252 }
4253 ctl = hdac_audio_ctl_amp_get(devinfo, 58, 0, 1);
4254 if (ctl != NULL) {
4255 ctl->ossmask = SOUND_MASK_IGAIN;
4256 ctl->widget->ctlflags |= SOUND_MASK_IGAIN;
4257 }
4258 ctl = hdac_audio_ctl_amp_get(devinfo, 60, 0, 1);
4259 if (ctl != NULL) {
4260 ctl->ossmask = SOUND_MASK_IGAIN;
4261 ctl->widget->ctlflags |= SOUND_MASK_IGAIN;
4262 }
4263 ctl = hdac_audio_ctl_amp_get(devinfo, 32, 0, 1);
4264 if (ctl != NULL) {
4265 ctl->ossmask = SOUND_MASK_MIC | SOUND_MASK_VOLUME;
4266 ctl->widget->ctlflags |= SOUND_MASK_MIC;
4267 }
4268 ctl = hdac_audio_ctl_amp_get(devinfo, 32, 4, 1);
4269 if (ctl != NULL) {
4270 ctl->ossmask = SOUND_MASK_MIC | SOUND_MASK_VOLUME;
4271 ctl->widget->ctlflags |= SOUND_MASK_MIC;
4272 }
4273 ctl = hdac_audio_ctl_amp_get(devinfo, 32, 1, 1);
4274 if (ctl != NULL) {
4275 ctl->ossmask = SOUND_MASK_LINE | SOUND_MASK_VOLUME;
4276 ctl->widget->ctlflags |= SOUND_MASK_LINE;
4277 }
4278 ctl = hdac_audio_ctl_amp_get(devinfo, 32, 7, 1);
4279 if (ctl != NULL) {
4280 ctl->ossmask = SOUND_MASK_SPEAKER | SOUND_MASK_VOLUME;
4281 ctl->widget->ctlflags |= SOUND_MASK_SPEAKER;
4282 }
4283 break;
4284 case HDA_CODEC_STAC9221:
4285 /*
4286 * Dell XPS M1210 need all DACs for each output jacks
4287 */
4288 if (subvendor == DELL_XPSM1210_SUBVENDOR)
4289 break;
4290 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
4291 w = hdac_widget_get(devinfo, i);
4292 if (w == NULL || w->enable == 0)
4293 continue;
4294 if (w->type !=
4295 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT)
4296 continue;
4297 if (w->nid != 2)
4298 w->enable = 0;
4299 }
4300 break;
4301 case HDA_CODEC_STAC9221D:
4302 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
4303 w = hdac_widget_get(devinfo, i);
4304 if (w == NULL || w->enable == 0)
4305 continue;
4306 if (w->type ==
4307 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT &&
4308 w->nid != 6)
4309 w->enable = 0;
4310
4311 }
4312 break;
4313 case HDA_CODEC_STAC9227:
4314 w = hdac_widget_get(devinfo, 8);
4315 if (w != NULL)
4316 w->enable = 0;
4317 w = hdac_widget_get(devinfo, 9);
4318 if (w != NULL)
4319 w->enable = 0;
4320 break;
4321 case HDA_CODEC_CXWAIKIKI:
4322 if (subvendor == HP_DV5000_SUBVENDOR) {
4323 w = hdac_widget_get(devinfo, 27);
4324 if (w != NULL)
4325 w->enable = 0;
4326 }
4327 ctl = hdac_audio_ctl_amp_get(devinfo, 16, 0, 1);
4328 if (ctl != NULL)
4329 ctl->ossmask = SOUND_MASK_SKIP;
4330 ctl = hdac_audio_ctl_amp_get(devinfo, 25, 0, 1);
4331 if (ctl != NULL && ctl->childwidget != NULL &&
4332 ctl->childwidget->enable != 0) {
4333 ctl->ossmask = SOUND_MASK_PCM | SOUND_MASK_VOLUME;
4334 ctl->childwidget->ctlflags |= SOUND_MASK_PCM;
4335 }
4336 ctl = hdac_audio_ctl_amp_get(devinfo, 25, 1, 1);
4337 if (ctl != NULL && ctl->childwidget != NULL &&
4338 ctl->childwidget->enable != 0) {
4339 ctl->ossmask = SOUND_MASK_LINE | SOUND_MASK_VOLUME;
4340 ctl->childwidget->ctlflags |= SOUND_MASK_LINE;
4341 }
4342 ctl = hdac_audio_ctl_amp_get(devinfo, 25, 2, 1);
4343 if (ctl != NULL && ctl->childwidget != NULL &&
4344 ctl->childwidget->enable != 0) {
4345 ctl->ossmask = SOUND_MASK_MIC | SOUND_MASK_VOLUME;
4346 ctl->childwidget->ctlflags |= SOUND_MASK_MIC;
4347 }
4348 ctl = hdac_audio_ctl_amp_get(devinfo, 26, 0, 1);
4349 if (ctl != NULL) {
4350 ctl->ossmask = SOUND_MASK_SKIP;
4351 /* XXX mixer \=rec mic broken.. why?!? */
4352 /* ctl->widget->ctlflags |= SOUND_MASK_MIC; */
4353 }
4354 break;
4355 default:
4356 break;
4357 }
4358}
4359
4360static int
4361hdac_audio_ctl_ossmixer_getnextdev(struct hdac_devinfo *devinfo)
4362{
4363 int *dev = &devinfo->function.audio.ossidx;
4364
4365 while (*dev < SOUND_MIXER_NRDEVICES) {
4366 switch (*dev) {
4367 case SOUND_MIXER_VOLUME:
4368 case SOUND_MIXER_BASS:
4369 case SOUND_MIXER_TREBLE:
4370 case SOUND_MIXER_PCM:
4371 case SOUND_MIXER_SPEAKER:
4372 case SOUND_MIXER_LINE:
4373 case SOUND_MIXER_MIC:
4374 case SOUND_MIXER_CD:
4375 case SOUND_MIXER_RECLEV:
4376 case SOUND_MIXER_IGAIN:
4377 case SOUND_MIXER_OGAIN: /* reserved for EAPD switch */
4378 (*dev)++;
4379 break;
4380 default:
4381 return (*dev)++;
4382 break;
4383 }
4384 }
4385
4386 return (-1);
4387}
4388
4389static int
4390hdac_widget_find_dac_path(struct hdac_devinfo *devinfo, nid_t nid, int depth)
4391{
4392 struct hdac_widget *w;
4393 int i, ret = 0;
4394
4395 if (depth > HDA_PARSE_MAXDEPTH)
4396 return (0);
4397 w = hdac_widget_get(devinfo, nid);
4398 if (w == NULL || w->enable == 0)
4399 return (0);
4400 switch (w->type) {
4401 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT:
4402 w->pflags |= HDA_DAC_PATH;
4403 ret = 1;
4404 break;
4405 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER:
4406 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR:
4407 for (i = 0; i < w->nconns; i++) {
4408 if (hdac_widget_find_dac_path(devinfo,
4409 w->conns[i], depth + 1) != 0) {
4410 if (w->selconn == -1)
4411 w->selconn = i;
4412 ret = 1;
4413 w->pflags |= HDA_DAC_PATH;
4414 }
4415 }
4416 break;
4417 default:
4418 break;
4419 }
4420 return (ret);
4421}
4422
4423static int
4424hdac_widget_find_adc_path(struct hdac_devinfo *devinfo, nid_t nid, int depth)
4425{
4426 struct hdac_widget *w;
4427 int i, conndev, ret = 0;
4428
4429 if (depth > HDA_PARSE_MAXDEPTH)
4430 return (0);
4431 w = hdac_widget_get(devinfo, nid);
4432 if (w == NULL || w->enable == 0)
4433 return (0);
4434 switch (w->type) {
4435 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT:
4436 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR:
4437 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER:
4438 for (i = 0; i < w->nconns; i++) {
4439 if (hdac_widget_find_adc_path(devinfo, w->conns[i],
4440 depth + 1) != 0) {
4441 if (w->selconn == -1)
4442 w->selconn = i;
4443 w->pflags |= HDA_ADC_PATH;
4444 ret = 1;
4445 }
4446 }
4447 break;
4448 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX:
4449 conndev = w->wclass.pin.config &
4450 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK;
4451 if (HDA_PARAM_PIN_CAP_INPUT_CAP(w->wclass.pin.cap) &&
4452 (conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_CD ||
4453 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN ||
4454 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN)) {
4455 w->pflags |= HDA_ADC_PATH;
4456 ret = 1;
4457 }
4458 break;
4459 /*case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER:
4460 if (w->pflags & HDA_DAC_PATH) {
4461 w->pflags |= HDA_ADC_PATH;
4462 ret = 1;
4463 }
4464 break;*/
4465 default:
4466 break;
4467 }
4468 return (ret);
4469}
4470
4471static uint32_t
4472hdac_audio_ctl_outamp_build(struct hdac_devinfo *devinfo,
4473 nid_t nid, nid_t pnid, int index, int depth)
4474{
4475 struct hdac_widget *w, *pw;
4476 struct hdac_audio_ctl *ctl;
4477 uint32_t fl = 0;
4478 int i, ossdev, conndev, strategy;
4479
4480 if (depth > HDA_PARSE_MAXDEPTH)
4481 return (0);
4482
4483 w = hdac_widget_get(devinfo, nid);
4484 if (w == NULL || w->enable == 0)
4485 return (0);
4486
4487 pw = hdac_widget_get(devinfo, pnid);
4488 strategy = devinfo->function.audio.parsing_strategy;
4489
4490 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER
4491 || w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR) {
4492 for (i = 0; i < w->nconns; i++) {
4493 fl |= hdac_audio_ctl_outamp_build(devinfo, w->conns[i],
4494 w->nid, i, depth + 1);
4495 }
4496 w->ctlflags |= fl;
4497 return (fl);
4498 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT &&
4499 (w->pflags & HDA_DAC_PATH)) {
4500 i = 0;
4501 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) {
4502 if (ctl->enable == 0 || ctl->widget == NULL)
4503 continue;
4504 /* XXX This should be compressed! */
4505 if (((ctl->widget->nid == w->nid) ||
4506 (ctl->widget->nid == pnid && ctl->index == index &&
4507 (ctl->dir & HDA_CTL_IN)) ||
4508 (ctl->widget->nid == pnid && pw != NULL &&
4509 pw->type ==
4510 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR &&
4511 (pw->nconns < 2 || pw->selconn == index ||
4512 pw->selconn == -1) &&
4513 (ctl->dir & HDA_CTL_OUT)) ||
4514 (strategy == HDA_PARSE_DIRECT &&
4515 ctl->widget->nid == w->nid)) &&
4516 !(ctl->ossmask & ~SOUND_MASK_VOLUME)) {
4517 /*if (pw != NULL && pw->selconn == -1)
4518 pw->selconn = index;
4519 fl |= SOUND_MASK_VOLUME;
4520 fl |= SOUND_MASK_PCM;
4521 ctl->ossmask |= SOUND_MASK_VOLUME;
4522 ctl->ossmask |= SOUND_MASK_PCM;
4523 ctl->ossdev = SOUND_MIXER_PCM;*/
4524 if (!(w->ctlflags & SOUND_MASK_PCM) ||
4525 (pw != NULL &&
4526 !(pw->ctlflags & SOUND_MASK_PCM))) {
4527 fl |= SOUND_MASK_VOLUME;
4528 fl |= SOUND_MASK_PCM;
4529 ctl->ossmask |= SOUND_MASK_VOLUME;
4530 ctl->ossmask |= SOUND_MASK_PCM;
4531 ctl->ossdev = SOUND_MIXER_PCM;
4532 w->ctlflags |= SOUND_MASK_VOLUME;
4533 w->ctlflags |= SOUND_MASK_PCM;
4534 if (pw != NULL) {
4535 if (pw->selconn == -1)
4536 pw->selconn = index;
4537 pw->ctlflags |=
4538 SOUND_MASK_VOLUME;
4539 pw->ctlflags |=
4540 SOUND_MASK_PCM;
4541 }
4542 }
4543 }
4544 }
4545 w->ctlflags |= fl;
4546 return (fl);
4547 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX &&
4548 HDA_PARAM_PIN_CAP_INPUT_CAP(w->wclass.pin.cap) &&
4549 (w->pflags & HDA_ADC_PATH)) {
4550 conndev = w->wclass.pin.config &
4551 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK;
4552 i = 0;
4553 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) {
4554 if (ctl->enable == 0 || ctl->widget == NULL)
4555 continue;
4556 /* XXX This should be compressed! */
4557 if (((ctl->widget->nid == pnid && ctl->index == index &&
4558 (ctl->dir & HDA_CTL_IN)) ||
4559 (ctl->widget->nid == pnid && pw != NULL &&
4560 pw->type ==
4561 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR &&
4562 (pw->nconns < 2 || pw->selconn == index ||
4563 pw->selconn == -1) &&
4564 (ctl->dir & HDA_CTL_OUT)) ||
4565 (strategy == HDA_PARSE_DIRECT &&
4566 ctl->widget->nid == w->nid)) &&
4567 !(ctl->ossmask & ~SOUND_MASK_VOLUME)) {
4568 if (pw != NULL && pw->selconn == -1)
4569 pw->selconn = index;
4570 ossdev = 0;
4571 switch (conndev) {
4572 case HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN:
4573 ossdev = SOUND_MIXER_MIC;
4574 break;
4575 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN:
4576 ossdev = SOUND_MIXER_LINE;
4577 break;
4578 case HDA_CONFIG_DEFAULTCONF_DEVICE_CD:
4579 ossdev = SOUND_MIXER_CD;
4580 break;
4581 default:
4582 ossdev =
4583 hdac_audio_ctl_ossmixer_getnextdev(
4584 devinfo);
4585 if (ossdev < 0)
4586 ossdev = 0;
4587 break;
4588 }
4589 if (strategy == HDA_PARSE_MIXER) {
4590 fl |= SOUND_MASK_VOLUME;
4591 ctl->ossmask |= SOUND_MASK_VOLUME;
4592 }
4593 fl |= 1 << ossdev;
4594 ctl->ossmask |= 1 << ossdev;
4595 ctl->ossdev = ossdev;
4596 }
4597 }
4598 w->ctlflags |= fl;
4599 return (fl);
4600 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET) {
4601 i = 0;
4602 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) {
4603 if (ctl->enable == 0 || ctl->widget == NULL)
4604 continue;
4605 /* XXX This should be compressed! */
4606 if (((ctl->widget->nid == pnid && ctl->index == index &&
4607 (ctl->dir & HDA_CTL_IN)) ||
4608 (ctl->widget->nid == pnid && pw != NULL &&
4609 pw->type ==
4610 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR &&
4611 (pw->nconns < 2 || pw->selconn == index ||
4612 pw->selconn == -1) &&
4613 (ctl->dir & HDA_CTL_OUT)) ||
4614 (strategy == HDA_PARSE_DIRECT &&
4615 ctl->widget->nid == w->nid)) &&
4616 !(ctl->ossmask & ~SOUND_MASK_VOLUME)) {
4617 if (pw != NULL && pw->selconn == -1)
4618 pw->selconn = index;
4619 fl |= SOUND_MASK_VOLUME;
4620 fl |= SOUND_MASK_SPEAKER;
4621 ctl->ossmask |= SOUND_MASK_VOLUME;
4622 ctl->ossmask |= SOUND_MASK_SPEAKER;
4623 ctl->ossdev = SOUND_MIXER_SPEAKER;
4624 }
4625 }
4626 w->ctlflags |= fl;
4627 return (fl);
4628 }
4629 return (0);
4630}
4631
4632static uint32_t
4633hdac_audio_ctl_inamp_build(struct hdac_devinfo *devinfo, nid_t nid, int depth)
4634{
4635 struct hdac_widget *w, *cw;
4636 struct hdac_audio_ctl *ctl;
4637 uint32_t fl;
4638 int i;
4639
4640 if (depth > HDA_PARSE_MAXDEPTH)
4641 return (0);
4642
4643 w = hdac_widget_get(devinfo, nid);
4644 if (w == NULL || w->enable == 0)
4645 return (0);
4646 /*if (!(w->pflags & HDA_ADC_PATH))
4647 return (0);
4648 if (!(w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT ||
4649 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR))
4650 return (0);*/
4651 i = 0;
4652 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) {
4653 if (ctl->enable == 0 || ctl->widget == NULL)
4654 continue;
4655 if (ctl->widget->nid == nid) {
4656 ctl->ossmask |= SOUND_MASK_RECLEV;
4657 w->ctlflags |= SOUND_MASK_RECLEV;
4658 return (SOUND_MASK_RECLEV);
4659 }
4660 }
4661 for (i = 0; i < w->nconns; i++) {
4662 cw = hdac_widget_get(devinfo, w->conns[i]);
4663 if (cw == NULL || cw->enable == 0)
4664 continue;
4665 if (cw->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR)
4666 continue;
4667 fl = hdac_audio_ctl_inamp_build(devinfo, cw->nid, depth + 1);
4668 if (fl != 0) {
4669 cw->ctlflags |= fl;
4670 w->ctlflags |= fl;
4671 return (fl);
4672 }
4673 }
4674 return (0);
4675}
4676
4677static int
4678hdac_audio_ctl_recsel_build(struct hdac_devinfo *devinfo, nid_t nid, int depth)
4679{
4680 struct hdac_widget *w, *cw;
4681 int i, child = 0;
4682
4683 if (depth > HDA_PARSE_MAXDEPTH)
4684 return (0);
4685
4686 w = hdac_widget_get(devinfo, nid);
4687 if (w == NULL || w->enable == 0)
4688 return (0);
4689 /*if (!(w->pflags & HDA_ADC_PATH))
4690 return (0);
4691 if (!(w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT ||
4692 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR))
4693 return (0);*/
4694 /* XXX weak! */
4695 for (i = 0; i < w->nconns; i++) {
4696 cw = hdac_widget_get(devinfo, w->conns[i]);
4697 if (cw == NULL)
4698 continue;
4699 if (++child > 1) {
4700 w->pflags |= HDA_ADC_RECSEL;
4701 return (1);
4702 }
4703 }
4704 for (i = 0; i < w->nconns; i++) {
4705 if (hdac_audio_ctl_recsel_build(devinfo,
4706 w->conns[i], depth + 1) != 0)
4707 return (1);
4708 }
4709 return (0);
4710}
4711
4712static int
4713hdac_audio_build_tree_strategy(struct hdac_devinfo *devinfo)
4714{
4715 struct hdac_widget *w, *cw;
4716 int i, j, conndev, found_dac = 0;
4717 int strategy;
4718
4719 strategy = devinfo->function.audio.parsing_strategy;
4720
4721 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
4722 w = hdac_widget_get(devinfo, i);
4723 if (w == NULL || w->enable == 0)
4724 continue;
4725 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX)
4726 continue;
4727 if (!HDA_PARAM_PIN_CAP_OUTPUT_CAP(w->wclass.pin.cap))
4728 continue;
4729 conndev = w->wclass.pin.config &
4730 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK;
4731 if (!(conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT ||
4732 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER ||
4733 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT))
4734 continue;
4735 for (j = 0; j < w->nconns; j++) {
4736 cw = hdac_widget_get(devinfo, w->conns[j]);
4737 if (cw == NULL || cw->enable == 0)
4738 continue;
4739 if (strategy == HDA_PARSE_MIXER && !(cw->type ==
4740 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER ||
4741 cw->type ==
4742 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR))
4743 continue;
4744 if (hdac_widget_find_dac_path(devinfo, cw->nid, 0)
4745 != 0) {
4746 if (w->selconn == -1)
4747 w->selconn = j;
4748 w->pflags |= HDA_DAC_PATH;
4749 found_dac++;
4750 }
4751 }
4752 }
4753
4754 return (found_dac);
4755}
4756
4757static void
4758hdac_audio_build_tree(struct hdac_devinfo *devinfo)
4759{
4760 struct hdac_widget *w;
4761 struct hdac_audio_ctl *ctl;
4762 int i, j, dacs, strategy;
4763
4764 /* Construct DAC path */
4765 strategy = HDA_PARSE_MIXER;
4766 devinfo->function.audio.parsing_strategy = strategy;
4767 HDA_BOOTVERBOSE(
4768 device_printf(devinfo->codec->sc->dev,
4769 "HDA_DEBUG: HWiP: HDA Widget Parser - Revision %d\n",
4770 HDA_WIDGET_PARSER_REV);
4771 );
4772 dacs = hdac_audio_build_tree_strategy(devinfo);
4773 if (dacs == 0) {
4774 HDA_BOOTVERBOSE(
4775 device_printf(devinfo->codec->sc->dev,
4776 "HDA_DEBUG: HWiP: 0 DAC path found! "
4777 "Retrying parser "
4778 "using HDA_PARSE_DIRECT strategy.\n");
4779 );
4780 strategy = HDA_PARSE_DIRECT;
4781 devinfo->function.audio.parsing_strategy = strategy;
4782 dacs = hdac_audio_build_tree_strategy(devinfo);
4783 }
4784
4785 HDA_BOOTVERBOSE(
4786 device_printf(devinfo->codec->sc->dev,
4787 "HDA_DEBUG: HWiP: Found %d DAC path using HDA_PARSE_%s "
4788 "strategy.\n",
4789 dacs, (strategy == HDA_PARSE_MIXER) ? "MIXER" : "DIRECT");
4790 );
4791
4792 /* Construct ADC path */
4793 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
4794 w = hdac_widget_get(devinfo, i);
4795 if (w == NULL || w->enable == 0)
4796 continue;
4797 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT)
4798 continue;
4799 (void)hdac_widget_find_adc_path(devinfo, w->nid, 0);
4800 }
4801
4802 /* Output mixers */
4803 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
4804 w = hdac_widget_get(devinfo, i);
4805 if (w == NULL || w->enable == 0)
4806 continue;
4807 if ((strategy == HDA_PARSE_MIXER &&
4808 (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER ||
4809 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR)
4810 && (w->pflags & HDA_DAC_PATH)) ||
4811 (strategy == HDA_PARSE_DIRECT && (w->pflags &
4812 (HDA_DAC_PATH | HDA_ADC_PATH)))) {
4813 w->ctlflags |= hdac_audio_ctl_outamp_build(devinfo,
4814 w->nid, devinfo->startnode - 1, 0, 0);
4815 } else if (w->type ==
4816 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET) {
4817 j = 0;
4818 while ((ctl = hdac_audio_ctl_each(devinfo, &j)) !=
4819 NULL) {
4820 if (ctl->enable == 0 || ctl->widget == NULL)
4821 continue;
4822 if (ctl->widget->nid != w->nid)
4823 continue;
4824 ctl->ossmask |= SOUND_MASK_VOLUME;
4825 ctl->ossmask |= SOUND_MASK_SPEAKER;
4826 ctl->ossdev = SOUND_MIXER_SPEAKER;
4827 w->ctlflags |= SOUND_MASK_VOLUME;
4828 w->ctlflags |= SOUND_MASK_SPEAKER;
4829 }
4830 }
4831 }
4832
4833 /* Input mixers (rec) */
4834 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
4835 w = hdac_widget_get(devinfo, i);
4836 if (w == NULL || w->enable == 0)
4837 continue;
4838 if (!(w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT &&
4839 w->pflags & HDA_ADC_PATH))
4840 continue;
4841 hdac_audio_ctl_inamp_build(devinfo, w->nid, 0);
4842 hdac_audio_ctl_recsel_build(devinfo, w->nid, 0);
4843 }
4844}
4845
4846#define HDA_COMMIT_CONN (1 << 0)
4847#define HDA_COMMIT_CTRL (1 << 1)
4848#define HDA_COMMIT_EAPD (1 << 2)
4849#define HDA_COMMIT_GPIO (1 << 3)
4850#define HDA_COMMIT_MISC (1 << 4)
4851#define HDA_COMMIT_ALL (HDA_COMMIT_CONN | HDA_COMMIT_CTRL | \
4852 HDA_COMMIT_EAPD | HDA_COMMIT_GPIO | HDA_COMMIT_MISC)
4853
4854static void
4855hdac_audio_commit(struct hdac_devinfo *devinfo, uint32_t cfl)
4856{
4857 struct hdac_softc *sc = devinfo->codec->sc;
4858 struct hdac_widget *w;
4859 nid_t cad;
4860 int i;
4861
4862 if (!(cfl & HDA_COMMIT_ALL))
4863 return;
4864
4865 cad = devinfo->codec->cad;
4866
4867 if ((cfl & HDA_COMMIT_MISC)) {
4868 if (sc->pci_subvendor == APPLE_INTEL_MAC)
4869 hdac_command(sc, HDA_CMD_12BIT(cad, devinfo->nid,
4870 0x7e7, 0), cad);
4871 }
4872
4873 if (cfl & HDA_COMMIT_GPIO) {
4874 uint32_t gdata, gmask, gdir;
4875 int commitgpio, numgpio;
4876
4877 gdata = 0;
4878 gmask = 0;
4879 gdir = 0;
4880 commitgpio = 0;
4881
4882 numgpio = HDA_PARAM_GPIO_COUNT_NUM_GPIO(
4883 devinfo->function.audio.gpio);
4884
4885 if (devinfo->function.audio.quirks & HDA_QUIRK_GPIOFLUSH)
4886 commitgpio = (numgpio > 0) ? 1 : 0;
4887 else {
4888 for (i = 0; i < numgpio && i < HDA_GPIO_MAX; i++) {
4889 if (!(devinfo->function.audio.quirks &
4890 (1 << i)))
4891 continue;
4892 if (commitgpio == 0) {
4893 commitgpio = 1;
4894 HDA_BOOTVERBOSE(
4895 gdata = hdac_command(sc,
4896 HDA_CMD_GET_GPIO_DATA(cad,
4897 devinfo->nid), cad);
4898 gmask = hdac_command(sc,
4899 HDA_CMD_GET_GPIO_ENABLE_MASK(cad,
4900 devinfo->nid), cad);
4901 gdir = hdac_command(sc,
4902 HDA_CMD_GET_GPIO_DIRECTION(cad,
4903 devinfo->nid), cad);
4904 device_printf(sc->dev,
4905 "GPIO init: data=0x%08x "
4906 "mask=0x%08x dir=0x%08x\n",
4907 gdata, gmask, gdir);
4908 gdata = 0;
4909 gmask = 0;
4910 gdir = 0;
4911 );
4912 }
4913 gdata |= 1 << i;
4914 gmask |= 1 << i;
4915 gdir |= 1 << i;
4916 }
4917 }
4918
4919 if (commitgpio != 0) {
4920 HDA_BOOTVERBOSE(
4921 device_printf(sc->dev,
4922 "GPIO commit: data=0x%08x mask=0x%08x "
4923 "dir=0x%08x\n",
4924 gdata, gmask, gdir);
4925 );
4926 hdac_command(sc,
4927 HDA_CMD_SET_GPIO_ENABLE_MASK(cad, devinfo->nid,
4928 gmask), cad);
4929 hdac_command(sc,
4930 HDA_CMD_SET_GPIO_DIRECTION(cad, devinfo->nid,
4931 gdir), cad);
4932 hdac_command(sc,
4933 HDA_CMD_SET_GPIO_DATA(cad, devinfo->nid,
4934 gdata), cad);
4935 }
4936 }
4937
4938 for (i = 0; i < devinfo->nodecnt; i++) {
4939 w = &devinfo->widget[i];
4940 if (w == NULL || w->enable == 0)
4941 continue;
4942 if (cfl & HDA_COMMIT_CONN) {
4943 if (w->selconn == -1)
4944 w->selconn = 0;
4945 if (w->nconns > 0)
4946 hdac_widget_connection_select(w, w->selconn);
4947 }
4948 if ((cfl & HDA_COMMIT_CTRL) &&
4949 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) {
4950 uint32_t pincap;
4951
4952 pincap = w->wclass.pin.cap;
4953
4954 if ((w->pflags & (HDA_DAC_PATH | HDA_ADC_PATH)) ==
4955 (HDA_DAC_PATH | HDA_ADC_PATH))
4956 device_printf(sc->dev, "WARNING: node %d "
4957 "participate both for DAC/ADC!\n", w->nid);
4958 if (w->pflags & HDA_DAC_PATH) {
4959 w->wclass.pin.ctrl &=
4960 ~HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE;
4961 if ((w->wclass.pin.config &
4962 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) !=
4963 HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT)
4964 w->wclass.pin.ctrl &=
4965 ~HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE;
4966 if ((devinfo->function.audio.quirks & HDA_QUIRK_OVREF100) &&
4967 HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap))
4968 w->wclass.pin.ctrl |=
4969 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE(
4970 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_100);
4971 else if ((devinfo->function.audio.quirks & HDA_QUIRK_OVREF80) &&
4972 HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap))
4973 w->wclass.pin.ctrl |=
4974 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE(
4975 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_80);
4976 else if ((devinfo->function.audio.quirks & HDA_QUIRK_OVREF50) &&
4977 HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap))
4978 w->wclass.pin.ctrl |=
4979 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE(
4980 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_50);
4981 } else if (w->pflags & HDA_ADC_PATH) {
4982 w->wclass.pin.ctrl &=
4983 ~(HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE |
4984 HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE);
4985 if ((devinfo->function.audio.quirks & HDA_QUIRK_IVREF100) &&
4986 HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap))
4987 w->wclass.pin.ctrl |=
4988 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE(
4989 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_100);
4990 else if ((devinfo->function.audio.quirks & HDA_QUIRK_IVREF80) &&
4991 HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap))
4992 w->wclass.pin.ctrl |=
4993 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE(
4994 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_80);
4995 else if ((devinfo->function.audio.quirks & HDA_QUIRK_IVREF50) &&
4996 HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap))
4997 w->wclass.pin.ctrl |=
4998 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE(
4999 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_50);
5000 } else
5001 w->wclass.pin.ctrl &= ~(
5002 HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE |
5003 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE |
5004 HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE |
5005 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE_MASK);
5006 hdac_command(sc,
5007 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, w->nid,
5008 w->wclass.pin.ctrl), cad);
5009 }
5010 if ((cfl & HDA_COMMIT_EAPD) &&
5011 w->param.eapdbtl != HDAC_INVALID) {
5012 uint32_t val;
5013
5014 val = w->param.eapdbtl;
5015 if (devinfo->function.audio.quirks &
5016 HDA_QUIRK_EAPDINV)
5017 val ^= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD;
5018 hdac_command(sc,
5019 HDA_CMD_SET_EAPD_BTL_ENABLE(cad, w->nid,
5020 val), cad);
5021
5022 }
5023 DELAY(1000);
5024 }
5025}
5026
5027static void
5028hdac_audio_ctl_commit(struct hdac_devinfo *devinfo)
5029{
5030 struct hdac_softc *sc = devinfo->codec->sc;
5031 struct hdac_audio_ctl *ctl;
5032 int i;
5033
5034 devinfo->function.audio.mvol = 100 | (100 << 8);
5035 i = 0;
5036 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) {
5037 if (ctl->enable == 0 || ctl->widget == NULL) {
5038 HDA_BOOTVERBOSE(
5039 device_printf(sc->dev, "[%2d] Ctl nid=%d",
5040 i, (ctl->widget != NULL) ?
5041 ctl->widget->nid : -1);
5042 if (ctl->childwidget != NULL)
5043 printf(" childnid=%d",
5044 ctl->childwidget->nid);
5045 if (ctl->widget == NULL)
5046 printf(" NULL WIDGET!");
5047 printf(" DISABLED\n");
5048 );
5049 continue;
5050 }
5051 HDA_BOOTVERBOSE(
5052 if (ctl->ossmask == 0) {
5053 device_printf(sc->dev, "[%2d] Ctl nid=%d",
5054 i, ctl->widget->nid);
5055 if (ctl->childwidget != NULL)
5056 printf(" childnid=%d",
5057 ctl->childwidget->nid);
5058 printf(" Bind to NONE\n");
5059 }
5060 );
5061 if (ctl->step > 0) {
5062 ctl->ossval = (ctl->left * 100) / ctl->step;
5063 ctl->ossval |= ((ctl->right * 100) / ctl->step) << 8;
5064 } else
5065 ctl->ossval = 0;
5066 hdac_audio_ctl_amp_set(ctl, HDA_AMP_MUTE_DEFAULT,
5067 ctl->left, ctl->right);
5068 }
5069}
5070
5071static int
5072hdac_pcmchannel_setup(struct hdac_devinfo *devinfo, int dir)
5073{
5074 struct hdac_chan *ch;
5075 struct hdac_widget *w;
5076 uint32_t cap, fmtcap, pcmcap, path;
5077 int i, type, ret, max;
5078
5079 if (dir == PCMDIR_PLAY) {
5080 type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT;
5081 ch = &devinfo->codec->sc->play;
5082 path = HDA_DAC_PATH;
5083 } else {
5084 type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT;
5085 ch = &devinfo->codec->sc->rec;
5086 path = HDA_ADC_PATH;
5087 }
5088
5089 ch->caps = hdac_caps;
5090 ch->caps.fmtlist = ch->fmtlist;
5091 ch->bit16 = 1;
5092 ch->bit32 = 0;
5093 ch->pcmrates[0] = 48000;
5094 ch->pcmrates[1] = 0;
5095
5096 ret = 0;
5097 fmtcap = devinfo->function.audio.supp_stream_formats;
5098 pcmcap = devinfo->function.audio.supp_pcm_size_rate;
5099 max = (sizeof(ch->io) / sizeof(ch->io[0])) - 1;
5100
5101 for (i = devinfo->startnode; i < devinfo->endnode && ret < max; i++) {
5102 w = hdac_widget_get(devinfo, i);
5103 if (w == NULL || w->enable == 0 || w->type != type ||
5104 !(w->pflags & path))
5105 continue;
5106 cap = w->param.widget_cap;
5107 /*if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(cap))
5108 continue;*/
5109 if (!HDA_PARAM_AUDIO_WIDGET_CAP_STEREO(cap))
5110 continue;
5111 cap = w->param.supp_stream_formats;
5112 /*if (HDA_PARAM_SUPP_STREAM_FORMATS_AC3(cap)) {
5113 }
5114 if (HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32(cap)) {
5115 }*/
5116 if (!HDA_PARAM_SUPP_STREAM_FORMATS_PCM(cap))
5117 continue;
5118 if (ret == 0) {
5119 fmtcap = w->param.supp_stream_formats;
5120 pcmcap = w->param.supp_pcm_size_rate;
5121 } else {
5122 fmtcap &= w->param.supp_stream_formats;
5123 pcmcap &= w->param.supp_pcm_size_rate;
5124 }
5125 ch->io[ret++] = i;
5126 }
5127 ch->io[ret] = -1;
5128
5129 ch->supp_stream_formats = fmtcap;
5130 ch->supp_pcm_size_rate = pcmcap;
5131
5132 /*
5133 * 8bit = 0
5134 * 16bit = 1
5135 * 20bit = 2
5136 * 24bit = 3
5137 * 32bit = 4
5138 */
5139 if (ret > 0) {
5140 cap = pcmcap;
5141 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(cap))
5142 ch->bit16 = 1;
5143 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(cap))
5144 ch->bit16 = 0;
5145 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(cap))
5146 ch->bit32 = 4;
5147 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(cap))
5148 ch->bit32 = 3;
5149 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(cap))
5150 ch->bit32 = 2;
5151 i = 0;
5152 if (!(devinfo->function.audio.quirks & HDA_QUIRK_FORCESTEREO))
5153 ch->fmtlist[i++] = AFMT_S16_LE;
5154 ch->fmtlist[i++] = AFMT_S16_LE | AFMT_STEREO;
5155 if (ch->bit32 > 0) {
5156 if (!(devinfo->function.audio.quirks &
5157 HDA_QUIRK_FORCESTEREO))
5158 ch->fmtlist[i++] = AFMT_S32_LE;
5159 ch->fmtlist[i++] = AFMT_S32_LE | AFMT_STEREO;
5160 }
5161 ch->fmtlist[i] = 0;
5162 i = 0;
5163 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(cap))
5164 ch->pcmrates[i++] = 8000;
5165 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(cap))
5166 ch->pcmrates[i++] = 11025;
5167 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(cap))
5168 ch->pcmrates[i++] = 16000;
5169 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(cap))
5170 ch->pcmrates[i++] = 22050;
5171 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(cap))
5172 ch->pcmrates[i++] = 32000;
5173 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(cap))
5174 ch->pcmrates[i++] = 44100;
5175 /* if (HDA_PARAM_SUPP_PCM_SIZE_RATE_48KHZ(cap)) */
5176 ch->pcmrates[i++] = 48000;
5177 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(cap))
5178 ch->pcmrates[i++] = 88200;
5179 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(cap))
5180 ch->pcmrates[i++] = 96000;
5181 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(cap))
5182 ch->pcmrates[i++] = 176400;
5183 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(cap))
5184 ch->pcmrates[i++] = 192000;
5185 /* if (HDA_PARAM_SUPP_PCM_SIZE_RATE_384KHZ(cap)) */
5186 ch->pcmrates[i] = 0;
5187 if (i > 0) {
5188 ch->caps.minspeed = ch->pcmrates[0];
5189 ch->caps.maxspeed = ch->pcmrates[i - 1];
5190 }
5191 }
5192
5193 return (ret);
5194}
5195
5196static void
5197hdac_dump_ctls(struct hdac_devinfo *devinfo, const char *banner, uint32_t flag)
5198{
5199 struct hdac_audio_ctl *ctl;
5200 struct hdac_softc *sc = devinfo->codec->sc;
5201 int i;
5202 uint32_t fl = 0;
5203
5204
5205 if (flag == 0) {
5206 fl = SOUND_MASK_VOLUME | SOUND_MASK_PCM |
5207 SOUND_MASK_CD | SOUND_MASK_LINE | SOUND_MASK_RECLEV |
5208 SOUND_MASK_MIC | SOUND_MASK_SPEAKER | SOUND_MASK_OGAIN;
5209 }
5210
5211 i = 0;
5212 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) {
5213 if (ctl->enable == 0 || ctl->widget == NULL ||
5214 ctl->widget->enable == 0 || (ctl->ossmask &
5215 (SOUND_MASK_SKIP | SOUND_MASK_DISABLE)))
5216 continue;
5217 if ((flag == 0 && (ctl->ossmask & ~fl)) ||
5218 (flag != 0 && (ctl->ossmask & flag))) {
5219 if (banner != NULL) {
5220 device_printf(sc->dev, "\n");
5221 device_printf(sc->dev, "%s\n", banner);
5222 }
5223 goto hdac_ctl_dump_it_all;
5224 }
5225 }
5226
5227 return;
5228
5229hdac_ctl_dump_it_all:
5230 i = 0;
5231 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) {
5232 if (ctl->enable == 0 || ctl->widget == NULL ||
5233 ctl->widget->enable == 0)
5234 continue;
5235 if (!((flag == 0 && (ctl->ossmask & ~fl)) ||
5236 (flag != 0 && (ctl->ossmask & flag))))
5237 continue;
5238 if (flag == 0) {
5239 device_printf(sc->dev, "\n");
5240 device_printf(sc->dev, "Unknown Ctl (OSS: %s)\n",
5241 hdac_audio_ctl_ossmixer_mask2name(ctl->ossmask));
5242 }
5243 device_printf(sc->dev, " |\n");
5244 device_printf(sc->dev, " +- nid: %2d index: %2d ",
5245 ctl->widget->nid, ctl->index);
5246 if (ctl->childwidget != NULL)
5247 printf("(nid: %2d) ", ctl->childwidget->nid);
5248 else
5249 printf(" ");
5250 printf("mute: %d step: %3d size: %3d off: %3d dir=0x%x ossmask=0x%08x\n",
5251 ctl->mute, ctl->step, ctl->size, ctl->offset, ctl->dir,
5252 ctl->ossmask);
5253 }
5254}
5255
5256static void
5257hdac_dump_audio_formats(struct hdac_softc *sc, uint32_t fcap, uint32_t pcmcap)
5258{
5259 uint32_t cap;
5260
5261 cap = fcap;
5262 if (cap != 0) {
5263 device_printf(sc->dev, " Stream cap: 0x%08x\n", cap);
5264 device_printf(sc->dev, " Format:");
5265 if (HDA_PARAM_SUPP_STREAM_FORMATS_AC3(cap))
5266 printf(" AC3");
5267 if (HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32(cap))
5268 printf(" FLOAT32");
5269 if (HDA_PARAM_SUPP_STREAM_FORMATS_PCM(cap))
5270 printf(" PCM");
5271 printf("\n");
5272 }
5273 cap = pcmcap;
5274 if (cap != 0) {
5275 device_printf(sc->dev, " PCM cap: 0x%08x\n", cap);
5276 device_printf(sc->dev, " PCM size:");
5277 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(cap))
5278 printf(" 8");
5279 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(cap))
5280 printf(" 16");
5281 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(cap))
5282 printf(" 20");
5283 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(cap))
5284 printf(" 24");
5285 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(cap))
5286 printf(" 32");
5287 printf("\n");
5288 device_printf(sc->dev, " PCM rate:");
5289 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(cap))
5290 printf(" 8");
5291 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(cap))
5292 printf(" 11");
5293 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(cap))
5294 printf(" 16");
5295 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(cap))
5296 printf(" 22");
5297 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(cap))
5298 printf(" 32");
5299 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(cap))
5300 printf(" 44");
5301 printf(" 48");
5302 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(cap))
5303 printf(" 88");
5304 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(cap))
5305 printf(" 96");
5306 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(cap))
5307 printf(" 176");
5308 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(cap))
5309 printf(" 192");
5310 printf("\n");
5311 }
5312}
5313
5314static void
5315hdac_dump_pin(struct hdac_softc *sc, struct hdac_widget *w)
5316{
5317 uint32_t pincap, wcap;
5318
5319 pincap = w->wclass.pin.cap;
5320 wcap = w->param.widget_cap;
5321
5322 device_printf(sc->dev, " Pin cap: 0x%08x\n", pincap);
5323 device_printf(sc->dev, " ");
5324 if (HDA_PARAM_PIN_CAP_IMP_SENSE_CAP(pincap))
5325 printf(" ISC");
5326 if (HDA_PARAM_PIN_CAP_TRIGGER_REQD(pincap))
5327 printf(" TRQD");
5328 if (HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(pincap))
5329 printf(" PDC");
5330 if (HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap))
5331 printf(" HP");
5332 if (HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap))
5333 printf(" OUT");
5334 if (HDA_PARAM_PIN_CAP_INPUT_CAP(pincap))
5335 printf(" IN");
5336 if (HDA_PARAM_PIN_CAP_BALANCED_IO_PINS(pincap))
5337 printf(" BAL");
5338 if (HDA_PARAM_PIN_CAP_VREF_CTRL(pincap)) {
5339 printf(" VREF[");
5340 if (HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap))
5341 printf(" 50");
5342 if (HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap))
5343 printf(" 80");
5344 if (HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap))
5345 printf(" 100");
5346 if (HDA_PARAM_PIN_CAP_VREF_CTRL_GROUND(pincap))
5347 printf(" GROUND");
5348 if (HDA_PARAM_PIN_CAP_VREF_CTRL_HIZ(pincap))
5349 printf(" HIZ");
5350 printf(" ]");
5351 }
5352 if (HDA_PARAM_PIN_CAP_EAPD_CAP(pincap))
5353 printf(" EAPD");
5354 if (HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(wcap))
5355 printf(" : UNSOL");
5356 printf("\n");
5357 device_printf(sc->dev, " Pin config: 0x%08x\n",
5358 w->wclass.pin.config);
5359 device_printf(sc->dev, " Pin control: 0x%08x", w->wclass.pin.ctrl);
5360 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE)
5361 printf(" HP");
5362 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE)
5363 printf(" IN");
5364 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE)
5365 printf(" OUT");
5366 printf("\n");
5367}
5368
5369static void
5370hdac_dump_amp(struct hdac_softc *sc, uint32_t cap, char *banner)
5371{
5372 device_printf(sc->dev, " %s amp: 0x%08x\n", banner, cap);
5373 device_printf(sc->dev, " "
5374 "mute=%d step=%d size=%d offset=%d\n",
5375 HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(cap),
5376 HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(cap),
5377 HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(cap),
5378 HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(cap));
5379}
5380
5381static void
5382hdac_dump_nodes(struct hdac_devinfo *devinfo)
5383{
5384 struct hdac_softc *sc = devinfo->codec->sc;
5385 struct hdac_widget *w, *cw;
5386 int i, j;
5387
5388 device_printf(sc->dev, "\n");
5389 device_printf(sc->dev, "Default Parameter\n");
5390 device_printf(sc->dev, "-----------------\n");
5391 hdac_dump_audio_formats(sc,
5392 devinfo->function.audio.supp_stream_formats,
5393 devinfo->function.audio.supp_pcm_size_rate);
5394 device_printf(sc->dev, " IN amp: 0x%08x\n",
5395 devinfo->function.audio.inamp_cap);
5396 device_printf(sc->dev, " OUT amp: 0x%08x\n",
5397 devinfo->function.audio.outamp_cap);
5398 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
5399 w = hdac_widget_get(devinfo, i);
5400 if (w == NULL) {
5401 device_printf(sc->dev, "Ghost widget nid=%d\n", i);
5402 continue;
5403 }
5404 device_printf(sc->dev, "\n");
5405 device_printf(sc->dev, " nid: %d [%s]%s\n", w->nid,
5406 HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap) ?
5407 "DIGITAL" : "ANALOG",
5408 (w->enable == 0) ? " [DISABLED]" : "");
5409 device_printf(sc->dev, " name: %s\n", w->name);
5410 device_printf(sc->dev, " widget_cap: 0x%08x\n",
5411 w->param.widget_cap);
5412 device_printf(sc->dev, " Parse flags: 0x%08x\n",
5413 w->pflags);
5414 device_printf(sc->dev, " Ctl flags: 0x%08x\n",
5415 w->ctlflags);
5416 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT ||
5417 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) {
5418 hdac_dump_audio_formats(sc,
5419 w->param.supp_stream_formats,
5420 w->param.supp_pcm_size_rate);
5421 } else if (w->type ==
5422 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX)
5423 hdac_dump_pin(sc, w);
5424 if (w->param.eapdbtl != HDAC_INVALID)
5425 device_printf(sc->dev, " EAPD: 0x%08x\n",
5426 w->param.eapdbtl);
5427 if (HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(w->param.widget_cap) &&
5428 w->param.outamp_cap != 0)
5429 hdac_dump_amp(sc, w->param.outamp_cap, "Output");
5430 if (HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(w->param.widget_cap) &&
5431 w->param.inamp_cap != 0)
5432 hdac_dump_amp(sc, w->param.inamp_cap, " Input");
5433 device_printf(sc->dev, " connections: %d\n", w->nconns);
5434 for (j = 0; j < w->nconns; j++) {
5435 cw = hdac_widget_get(devinfo, w->conns[j]);
5436 device_printf(sc->dev, " |\n");
5437 device_printf(sc->dev, " + <- nid=%d [%s]",
5438 w->conns[j], (cw == NULL) ? "GHOST!" : cw->name);
5439 if (cw == NULL)
5440 printf(" [UNKNOWN]");
5441 else if (cw->enable == 0)
5442 printf(" [DISABLED]");
5443 if (w->nconns > 1 && w->selconn == j && w->type !=
5444 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER)
5445 printf(" (selected)");
5446 printf("\n");
5447 }
5448 }
5449
5450}
5451
5452static int
5453hdac_dump_dac_internal(struct hdac_devinfo *devinfo, nid_t nid, int depth)
5454{
5455 struct hdac_widget *w, *cw;
5456 struct hdac_softc *sc = devinfo->codec->sc;
5457 int i;
5458
5459 if (depth > HDA_PARSE_MAXDEPTH)
5460 return (0);
5461
5462 w = hdac_widget_get(devinfo, nid);
5463 if (w == NULL || w->enable == 0 || !(w->pflags & HDA_DAC_PATH))
5464 return (0);
5465
5466 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) {
5467 device_printf(sc->dev, "\n");
5468 device_printf(sc->dev, " nid=%d [%s]\n", w->nid, w->name);
5469 device_printf(sc->dev, " ^\n");
5470 device_printf(sc->dev, " |\n");
5471 device_printf(sc->dev, " +-----<------+\n");
5472 } else {
5473 device_printf(sc->dev, " ^\n");
5474 device_printf(sc->dev, " |\n");
5475 device_printf(sc->dev, " ");
5476 printf(" nid=%d [%s]\n", w->nid, w->name);
5477 }
5478
5479 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT) {
5480 return (1);
5481 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) {
5482 for (i = 0; i < w->nconns; i++) {
5483 cw = hdac_widget_get(devinfo, w->conns[i]);
5484 if (cw == NULL || cw->enable == 0 || cw->type ==
5485 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX)
5486 continue;
5487 if (hdac_dump_dac_internal(devinfo, cw->nid,
5488 depth + 1) != 0)
5489 return (1);
5490 }
5491 } else if ((w->type ==
5492 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR ||
5493 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) &&
5494 w->selconn > -1 && w->selconn < w->nconns) {
5495 if (hdac_dump_dac_internal(devinfo, w->conns[w->selconn],
5496 depth + 1) != 0)
5497 return (1);
5498 }
5499
5500 return (0);
5501}
5502
5503static void
5504hdac_dump_dac(struct hdac_devinfo *devinfo)
5505{
5506 struct hdac_widget *w;
5507 struct hdac_softc *sc = devinfo->codec->sc;
5508 int i, printed = 0;
5509
5510 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
5511 w = hdac_widget_get(devinfo, i);
5512 if (w == NULL || w->enable == 0)
5513 continue;
5514 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX ||
5515 !(w->pflags & HDA_DAC_PATH))
5516 continue;
5517 if (printed == 0) {
5518 printed = 1;
5519 device_printf(sc->dev, "\n");
5520 device_printf(sc->dev, "Playback path:\n");
5521 }
5522 hdac_dump_dac_internal(devinfo, w->nid, 0);
5523 }
5524}
5525
5526static void
5527hdac_dump_adc(struct hdac_devinfo *devinfo)
5528{
5529 struct hdac_widget *w, *cw;
5530 struct hdac_softc *sc = devinfo->codec->sc;
5531 int i, j;
5532 int printed = 0;
5533 char ossdevs[256];
5534
5535 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
5536 w = hdac_widget_get(devinfo, i);
5537 if (w == NULL || w->enable == 0)
5538 continue;
5539 if (!(w->pflags & HDA_ADC_RECSEL))
5540 continue;
5541 if (printed == 0) {
5542 printed = 1;
5543 device_printf(sc->dev, "\n");
5544 device_printf(sc->dev, "Recording sources:\n");
5545 }
5546 device_printf(sc->dev, "\n");
5547 device_printf(sc->dev, " nid=%d [%s]\n", w->nid, w->name);
5548 for (j = 0; j < w->nconns; j++) {
5549 cw = hdac_widget_get(devinfo, w->conns[j]);
5550 if (cw == NULL || cw->enable == 0)
5551 continue;
5552 hdac_audio_ctl_ossmixer_mask2allname(cw->ctlflags,
5553 ossdevs, sizeof(ossdevs));
5554 device_printf(sc->dev, " |\n");
5555 device_printf(sc->dev, " + <- nid=%d [%s]",
5556 cw->nid, cw->name);
5557 if (strlen(ossdevs) > 0) {
5558 printf(" [recsrc: %s]", ossdevs);
5559 }
5560 printf("\n");
5561 }
5562 }
5563}
5564
5565static void
5566hdac_dump_pcmchannels(struct hdac_softc *sc, int pcnt, int rcnt)
5567{
5568 nid_t *nids;
5569
5570 if (pcnt > 0) {
5571 device_printf(sc->dev, "\n");
5572 device_printf(sc->dev, " PCM Playback: %d\n", pcnt);
5573 hdac_dump_audio_formats(sc, sc->play.supp_stream_formats,
5574 sc->play.supp_pcm_size_rate);
5575 device_printf(sc->dev, " DAC:");
5576 for (nids = sc->play.io; *nids != -1; nids++)
5577 printf(" %d", *nids);
5578 printf("\n");
5579 }
5580
5581 if (rcnt > 0) {
5582 device_printf(sc->dev, "\n");
5583 device_printf(sc->dev, " PCM Record: %d\n", rcnt);
5584 hdac_dump_audio_formats(sc, sc->play.supp_stream_formats,
5585 sc->rec.supp_pcm_size_rate);
5586 device_printf(sc->dev, " ADC:");
5587 for (nids = sc->rec.io; *nids != -1; nids++)
5588 printf(" %d", *nids);
5589 printf("\n");
5590 }
5591}
5592
5593static void
5594hdac_release_resources(struct hdac_softc *sc)
5595{
5596 struct hdac_devinfo *devinfo = NULL;
5597 device_t *devlist = NULL;
5598 int i, devcount;
5599
5600 if (sc == NULL)
5601 return;
5602
5603 hdac_lock(sc);
5604 sc->polling = 0;
5605 sc->poll_ival = 0;
|