27 */
28
29#include "pci.h"
30#include "pcm.h"
31
32#include <dev/sound/pcm/sound.h>
33#include <dev/sound/pcm/ac97.h>
34#include <dev/sound/pci/aureal.h>
35
36#include <pci/pcireg.h>
37#include <pci/pcivar.h>
38
39/* PCI IDs of supported chips */
40#define AU8820_PCI_ID 0x000112eb
41
42/* channel interface */
43static void *auchan_init(void *devinfo, snd_dbuf *b, pcm_channel *c, int dir);
44static int auchan_setdir(void *data, int dir);
45static int auchan_setformat(void *data, u_int32_t format);
46static int auchan_setspeed(void *data, u_int32_t speed);
47static int auchan_setblocksize(void *data, u_int32_t blocksize);
48static int auchan_trigger(void *data, int go);
49static int auchan_getptr(void *data);
50static pcmchan_caps *auchan_getcaps(void *data);
51
52static pcmchan_caps au_playcaps = {
53 4000, 48000,
54 AFMT_STEREO | AFMT_U8 | AFMT_S16_LE,
55 AFMT_STEREO | AFMT_S16_LE
56};
57
58static pcmchan_caps au_reccaps = {
59 4000, 48000,
60 AFMT_STEREO | AFMT_U8 | AFMT_S16_LE,
61 AFMT_STEREO | AFMT_S16_LE
62};
63
64static pcm_channel au_chantemplate = {
65 auchan_init,
66 auchan_setdir,
67 auchan_setformat,
68 auchan_setspeed,
69 auchan_setblocksize,
70 auchan_trigger,
71 auchan_getptr,
72 auchan_getcaps,
73};
74
75/* -------------------------------------------------------------------- */
76
77static u_int32_t au_rdcd(void *arg, int regno);
78static void au_wrcd(void *arg, int regno, u_int32_t data);
79
80struct au_info;
81
82struct au_chinfo {
83 struct au_info *parent;
84 pcm_channel *channel;
85 snd_dbuf *buffer;
86 int dir;
87};
88
89struct au_info {
90 int unit;
91
92 bus_space_tag_t st[3];
93 bus_space_handle_t sh[3];
94
95 bus_dma_tag_t parent_dmat;
96
97 u_int32_t x[32], y[128];
98 char z[128];
99 u_int32_t routes[4], interrupts;
100 struct au_chinfo pch;
101};
102
103static int au_init(device_t dev, struct au_info *au);
104static void au_intr(void *);
105
106/* -------------------------------------------------------------------- */
107
108static u_int32_t
109au_rd(struct au_info *au, int mapno, int regno, int size)
110{
111 switch(size) {
112 case 1:
113 return bus_space_read_1(au->st[mapno], au->sh[mapno], regno);
114 case 2:
115 return bus_space_read_2(au->st[mapno], au->sh[mapno], regno);
116 case 4:
117 return bus_space_read_4(au->st[mapno], au->sh[mapno], regno);
118 default:
119 return 0xffffffff;
120 }
121}
122
123static void
124au_wr(struct au_info *au, int mapno, int regno, u_int32_t data, int size)
125{
126 switch(size) {
127 case 1:
128 bus_space_write_1(au->st[mapno], au->sh[mapno], regno, data);
129 break;
130 case 2:
131 bus_space_write_2(au->st[mapno], au->sh[mapno], regno, data);
132 break;
133 case 4:
134 bus_space_write_4(au->st[mapno], au->sh[mapno], regno, data);
135 break;
136 }
137}
138
139static u_int32_t
140au_rdcd(void *arg, int regno)
141{
142 struct au_info *au = (struct au_info *)arg;
143 int i=0, j=0;
144
145 regno<<=16;
146 au_wr(au, 0, AU_REG_CODECIO, regno, 4);
147 while (j<50) {
148 i=au_rd(au, 0, AU_REG_CODECIO, 4);
149 if ((i & 0x00ff0000) == (regno | 0x00800000)) break;
150 DELAY(j * 200 + 2000);
151 j++;
152 }
153 if (j==50) printf("pcm%d: codec timeout reading register %x (%x)\n",
154 au->unit, (regno & AU_CDC_REGMASK)>>16, i);
155 return i & AU_CDC_DATAMASK;
156}
157
158static void
159au_wrcd(void *arg, int regno, u_int32_t data)
160{
161 struct au_info *au = (struct au_info *)arg;
162 int i, j, tries;
163 i=j=tries=0;
164 do {
165 while (j<50 && (i & AU_CDC_WROK) == 0) {
166 i=au_rd(au, 0, AU_REG_CODECST, 4);
167 DELAY(2000);
168 j++;
169 }
170 if (j==50) printf("codec timeout during write of register %x, data %x\n",
171 regno, data);
172 au_wr(au, 0, AU_REG_CODECIO, (regno<<16) | AU_CDC_REGSET | data, 4);
173/* DELAY(20000);
174 i=au_rdcd(au, regno);
175*/ tries++;
176 } while (0); /* (i != data && tries < 3); */
177 /*
178 if (tries == 3) printf("giving up writing 0x%4x to codec reg %2x\n", data, regno);
179 */
180}
181
182static void
183au_setbit(u_int32_t *p, char bit, u_int32_t value)
184{
185 p += bit >> 5;
186 bit &= 0x1f;
187 *p &= ~ (1 << bit);
188 *p |= (value << bit);
189}
190
191static void
192au_addroute(struct au_info *au, int a, int b, int route)
193{
194 int j = 0x1099c+(a<<2);
195 if (au->x[a] != a+0x67) j = AU_REG_RTBASE+(au->x[a]<<2);
196
197 au_wr(au, 0, AU_REG_RTBASE+(route<<2), 0xffffffff, 4);
198 au_wr(au, 0, j, route | (b<<7), 4);
199 au->y[route]=au->x[a];
200 au->x[a]=route;
201 au->z[route]=a & 0x000000ff;
202 au_setbit(au->routes, route, 1);
203}
204
205static void
206au_delroute(struct au_info *au, int route)
207{
208 int i;
209 int j=au->z[route];
210
211 au_setbit(au->routes, route, 0);
212 au->z[route]=0x1f;
213 i=au_rd(au, 0, AU_REG_RTBASE+(route<<2), 4);
214 au_wr(au, 0, AU_REG_RTBASE+(au->y[route]<<2), i, 4);
215 au->y[i & 0x7f]=au->y[route];
216 au_wr(au, 0, AU_REG_RTBASE+(route<<2), 0xfffffffe, 4);
217 if (au->x[j] == route) au->x[j]=au->y[route];
218 au->y[route]=0x7f;
219}
220
221static void
222au_encodec(struct au_info *au, char channel)
223{
224 au_wr(au, 0, AU_REG_CODECEN,
225 au_rd(au, 0, AU_REG_CODECEN, 4) | (1 << (channel + 8)), 4);
226}
227
228static void
229au_clrfifo(struct au_info *au, u_int32_t c)
230{
231 u_int32_t i;
232
233 for (i=0; i<32; i++) au_wr(au, 0, AU_REG_FIFOBASE+(c<<7)+(i<<2), 0, 4);
234}
235
236static void
237au_setadb(struct au_info *au, u_int32_t c, u_int32_t enable)
238{
239 int x;
240
241 x = au_rd(au, 0, AU_REG_ADB, 4);
242 x &= ~(1 << c);
243 x |= (enable << c);
244 au_wr(au, 0, AU_REG_ADB, x, 4);
245}
246
247static void
248au_prepareoutput(struct au_chinfo *ch, u_int32_t format)
249{
250 struct au_info *au = ch->parent;
251 int i, stereo = (format & AFMT_STEREO)? 1 : 0;
252 u_int32_t baseaddr = vtophys(ch->buffer->buf);
253
254 au_wr(au, 0, 0x1061c, 0, 4);
255 au_wr(au, 0, 0x10620, 0, 4);
256 au_wr(au, 0, 0x10624, 0, 4);
257 switch(format & ~AFMT_STEREO) {
258 case 1:
259 i=0xb000;
260 break;
261 case 2:
262 i=0xf000;
263 break;
264 case 8:
265 i=0x7000;
266 break;
267 case 16:
268 i=0x23000;
269 break;
270 default:
271 i=0x3000;
272 }
273 au_wr(au, 0, 0x10200, baseaddr, 4);
274 au_wr(au, 0, 0x10204, baseaddr+0x1000, 4);
275 au_wr(au, 0, 0x10208, baseaddr+0x2000, 4);
276 au_wr(au, 0, 0x1020c, baseaddr+0x3000, 4);
277
278 au_wr(au, 0, 0x10400, 0xdeffffff, 4);
279 au_wr(au, 0, 0x10404, 0xfcffffff, 4);
280
281 au_wr(au, 0, 0x10580, i, 4);
282
283 au_wr(au, 0, 0x10210, baseaddr, 4);
284 au_wr(au, 0, 0x10214, baseaddr+0x1000, 4);
285 au_wr(au, 0, 0x10218, baseaddr+0x2000, 4);
286 au_wr(au, 0, 0x1021c, baseaddr+0x3000, 4);
287
288 au_wr(au, 0, 0x10408, 0x00fff000 | 0x56000000 | 0x00000fff, 4);
289 au_wr(au, 0, 0x1040c, 0x00fff000 | 0x74000000 | 0x00000fff, 4);
290
291 au_wr(au, 0, 0x10584, i, 4);
292
293 au_wr(au, 0, 0x0f800, stereo? 0x00030032 : 0x00030030, 4);
294 au_wr(au, 0, 0x0f804, stereo? 0x00030032 : 0x00030030, 4);
295
296 au_addroute(au, 0x11, 0, 0x58);
297 au_addroute(au, 0x11, stereo? 0 : 1, 0x59);
298}
299
300/* channel interface */
301static void *
302auchan_init(void *devinfo, snd_dbuf *b, pcm_channel *c, int dir)
303{
304 struct au_info *au = devinfo;
305 struct au_chinfo *ch = (dir == PCMDIR_PLAY)? &au->pch : NULL;
306
307 ch->parent = au;
308 ch->channel = c;
309 ch->buffer = b;
310 ch->buffer->bufsize = AU_BUFFSIZE;
311 if (chn_allocbuf(ch->buffer, au->parent_dmat) == -1) return NULL;
312 return ch;
313}
314
315static int
316auchan_setdir(void *data, int dir)
317{
318 struct au_chinfo *ch = data;
319 if (dir == PCMDIR_PLAY) {
320 } else {
321 }
322 ch->dir = dir;
323 return 0;
324}
325
326static int
327auchan_setformat(void *data, u_int32_t format)
328{
329 struct au_chinfo *ch = data;
330
331 if (ch->dir == PCMDIR_PLAY) au_prepareoutput(ch, format);
332 return 0;
333}
334
335static int
336auchan_setspeed(void *data, u_int32_t speed)
337{
338 struct au_chinfo *ch = data;
339 if (ch->dir == PCMDIR_PLAY) {
340 } else {
341 }
342 return speed;
343}
344
345static int
346auchan_setblocksize(void *data, u_int32_t blocksize)
347{
348 return blocksize;
349}
350
351static int
352auchan_trigger(void *data, int go)
353{
354 struct au_chinfo *ch = data;
355 struct au_info *au = ch->parent;
| 27 */
28
29#include "pci.h"
30#include "pcm.h"
31
32#include <dev/sound/pcm/sound.h>
33#include <dev/sound/pcm/ac97.h>
34#include <dev/sound/pci/aureal.h>
35
36#include <pci/pcireg.h>
37#include <pci/pcivar.h>
38
39/* PCI IDs of supported chips */
40#define AU8820_PCI_ID 0x000112eb
41
42/* channel interface */
43static void *auchan_init(void *devinfo, snd_dbuf *b, pcm_channel *c, int dir);
44static int auchan_setdir(void *data, int dir);
45static int auchan_setformat(void *data, u_int32_t format);
46static int auchan_setspeed(void *data, u_int32_t speed);
47static int auchan_setblocksize(void *data, u_int32_t blocksize);
48static int auchan_trigger(void *data, int go);
49static int auchan_getptr(void *data);
50static pcmchan_caps *auchan_getcaps(void *data);
51
52static pcmchan_caps au_playcaps = {
53 4000, 48000,
54 AFMT_STEREO | AFMT_U8 | AFMT_S16_LE,
55 AFMT_STEREO | AFMT_S16_LE
56};
57
58static pcmchan_caps au_reccaps = {
59 4000, 48000,
60 AFMT_STEREO | AFMT_U8 | AFMT_S16_LE,
61 AFMT_STEREO | AFMT_S16_LE
62};
63
64static pcm_channel au_chantemplate = {
65 auchan_init,
66 auchan_setdir,
67 auchan_setformat,
68 auchan_setspeed,
69 auchan_setblocksize,
70 auchan_trigger,
71 auchan_getptr,
72 auchan_getcaps,
73};
74
75/* -------------------------------------------------------------------- */
76
77static u_int32_t au_rdcd(void *arg, int regno);
78static void au_wrcd(void *arg, int regno, u_int32_t data);
79
80struct au_info;
81
82struct au_chinfo {
83 struct au_info *parent;
84 pcm_channel *channel;
85 snd_dbuf *buffer;
86 int dir;
87};
88
89struct au_info {
90 int unit;
91
92 bus_space_tag_t st[3];
93 bus_space_handle_t sh[3];
94
95 bus_dma_tag_t parent_dmat;
96
97 u_int32_t x[32], y[128];
98 char z[128];
99 u_int32_t routes[4], interrupts;
100 struct au_chinfo pch;
101};
102
103static int au_init(device_t dev, struct au_info *au);
104static void au_intr(void *);
105
106/* -------------------------------------------------------------------- */
107
108static u_int32_t
109au_rd(struct au_info *au, int mapno, int regno, int size)
110{
111 switch(size) {
112 case 1:
113 return bus_space_read_1(au->st[mapno], au->sh[mapno], regno);
114 case 2:
115 return bus_space_read_2(au->st[mapno], au->sh[mapno], regno);
116 case 4:
117 return bus_space_read_4(au->st[mapno], au->sh[mapno], regno);
118 default:
119 return 0xffffffff;
120 }
121}
122
123static void
124au_wr(struct au_info *au, int mapno, int regno, u_int32_t data, int size)
125{
126 switch(size) {
127 case 1:
128 bus_space_write_1(au->st[mapno], au->sh[mapno], regno, data);
129 break;
130 case 2:
131 bus_space_write_2(au->st[mapno], au->sh[mapno], regno, data);
132 break;
133 case 4:
134 bus_space_write_4(au->st[mapno], au->sh[mapno], regno, data);
135 break;
136 }
137}
138
139static u_int32_t
140au_rdcd(void *arg, int regno)
141{
142 struct au_info *au = (struct au_info *)arg;
143 int i=0, j=0;
144
145 regno<<=16;
146 au_wr(au, 0, AU_REG_CODECIO, regno, 4);
147 while (j<50) {
148 i=au_rd(au, 0, AU_REG_CODECIO, 4);
149 if ((i & 0x00ff0000) == (regno | 0x00800000)) break;
150 DELAY(j * 200 + 2000);
151 j++;
152 }
153 if (j==50) printf("pcm%d: codec timeout reading register %x (%x)\n",
154 au->unit, (regno & AU_CDC_REGMASK)>>16, i);
155 return i & AU_CDC_DATAMASK;
156}
157
158static void
159au_wrcd(void *arg, int regno, u_int32_t data)
160{
161 struct au_info *au = (struct au_info *)arg;
162 int i, j, tries;
163 i=j=tries=0;
164 do {
165 while (j<50 && (i & AU_CDC_WROK) == 0) {
166 i=au_rd(au, 0, AU_REG_CODECST, 4);
167 DELAY(2000);
168 j++;
169 }
170 if (j==50) printf("codec timeout during write of register %x, data %x\n",
171 regno, data);
172 au_wr(au, 0, AU_REG_CODECIO, (regno<<16) | AU_CDC_REGSET | data, 4);
173/* DELAY(20000);
174 i=au_rdcd(au, regno);
175*/ tries++;
176 } while (0); /* (i != data && tries < 3); */
177 /*
178 if (tries == 3) printf("giving up writing 0x%4x to codec reg %2x\n", data, regno);
179 */
180}
181
182static void
183au_setbit(u_int32_t *p, char bit, u_int32_t value)
184{
185 p += bit >> 5;
186 bit &= 0x1f;
187 *p &= ~ (1 << bit);
188 *p |= (value << bit);
189}
190
191static void
192au_addroute(struct au_info *au, int a, int b, int route)
193{
194 int j = 0x1099c+(a<<2);
195 if (au->x[a] != a+0x67) j = AU_REG_RTBASE+(au->x[a]<<2);
196
197 au_wr(au, 0, AU_REG_RTBASE+(route<<2), 0xffffffff, 4);
198 au_wr(au, 0, j, route | (b<<7), 4);
199 au->y[route]=au->x[a];
200 au->x[a]=route;
201 au->z[route]=a & 0x000000ff;
202 au_setbit(au->routes, route, 1);
203}
204
205static void
206au_delroute(struct au_info *au, int route)
207{
208 int i;
209 int j=au->z[route];
210
211 au_setbit(au->routes, route, 0);
212 au->z[route]=0x1f;
213 i=au_rd(au, 0, AU_REG_RTBASE+(route<<2), 4);
214 au_wr(au, 0, AU_REG_RTBASE+(au->y[route]<<2), i, 4);
215 au->y[i & 0x7f]=au->y[route];
216 au_wr(au, 0, AU_REG_RTBASE+(route<<2), 0xfffffffe, 4);
217 if (au->x[j] == route) au->x[j]=au->y[route];
218 au->y[route]=0x7f;
219}
220
221static void
222au_encodec(struct au_info *au, char channel)
223{
224 au_wr(au, 0, AU_REG_CODECEN,
225 au_rd(au, 0, AU_REG_CODECEN, 4) | (1 << (channel + 8)), 4);
226}
227
228static void
229au_clrfifo(struct au_info *au, u_int32_t c)
230{
231 u_int32_t i;
232
233 for (i=0; i<32; i++) au_wr(au, 0, AU_REG_FIFOBASE+(c<<7)+(i<<2), 0, 4);
234}
235
236static void
237au_setadb(struct au_info *au, u_int32_t c, u_int32_t enable)
238{
239 int x;
240
241 x = au_rd(au, 0, AU_REG_ADB, 4);
242 x &= ~(1 << c);
243 x |= (enable << c);
244 au_wr(au, 0, AU_REG_ADB, x, 4);
245}
246
247static void
248au_prepareoutput(struct au_chinfo *ch, u_int32_t format)
249{
250 struct au_info *au = ch->parent;
251 int i, stereo = (format & AFMT_STEREO)? 1 : 0;
252 u_int32_t baseaddr = vtophys(ch->buffer->buf);
253
254 au_wr(au, 0, 0x1061c, 0, 4);
255 au_wr(au, 0, 0x10620, 0, 4);
256 au_wr(au, 0, 0x10624, 0, 4);
257 switch(format & ~AFMT_STEREO) {
258 case 1:
259 i=0xb000;
260 break;
261 case 2:
262 i=0xf000;
263 break;
264 case 8:
265 i=0x7000;
266 break;
267 case 16:
268 i=0x23000;
269 break;
270 default:
271 i=0x3000;
272 }
273 au_wr(au, 0, 0x10200, baseaddr, 4);
274 au_wr(au, 0, 0x10204, baseaddr+0x1000, 4);
275 au_wr(au, 0, 0x10208, baseaddr+0x2000, 4);
276 au_wr(au, 0, 0x1020c, baseaddr+0x3000, 4);
277
278 au_wr(au, 0, 0x10400, 0xdeffffff, 4);
279 au_wr(au, 0, 0x10404, 0xfcffffff, 4);
280
281 au_wr(au, 0, 0x10580, i, 4);
282
283 au_wr(au, 0, 0x10210, baseaddr, 4);
284 au_wr(au, 0, 0x10214, baseaddr+0x1000, 4);
285 au_wr(au, 0, 0x10218, baseaddr+0x2000, 4);
286 au_wr(au, 0, 0x1021c, baseaddr+0x3000, 4);
287
288 au_wr(au, 0, 0x10408, 0x00fff000 | 0x56000000 | 0x00000fff, 4);
289 au_wr(au, 0, 0x1040c, 0x00fff000 | 0x74000000 | 0x00000fff, 4);
290
291 au_wr(au, 0, 0x10584, i, 4);
292
293 au_wr(au, 0, 0x0f800, stereo? 0x00030032 : 0x00030030, 4);
294 au_wr(au, 0, 0x0f804, stereo? 0x00030032 : 0x00030030, 4);
295
296 au_addroute(au, 0x11, 0, 0x58);
297 au_addroute(au, 0x11, stereo? 0 : 1, 0x59);
298}
299
300/* channel interface */
301static void *
302auchan_init(void *devinfo, snd_dbuf *b, pcm_channel *c, int dir)
303{
304 struct au_info *au = devinfo;
305 struct au_chinfo *ch = (dir == PCMDIR_PLAY)? &au->pch : NULL;
306
307 ch->parent = au;
308 ch->channel = c;
309 ch->buffer = b;
310 ch->buffer->bufsize = AU_BUFFSIZE;
311 if (chn_allocbuf(ch->buffer, au->parent_dmat) == -1) return NULL;
312 return ch;
313}
314
315static int
316auchan_setdir(void *data, int dir)
317{
318 struct au_chinfo *ch = data;
319 if (dir == PCMDIR_PLAY) {
320 } else {
321 }
322 ch->dir = dir;
323 return 0;
324}
325
326static int
327auchan_setformat(void *data, u_int32_t format)
328{
329 struct au_chinfo *ch = data;
330
331 if (ch->dir == PCMDIR_PLAY) au_prepareoutput(ch, format);
332 return 0;
333}
334
335static int
336auchan_setspeed(void *data, u_int32_t speed)
337{
338 struct au_chinfo *ch = data;
339 if (ch->dir == PCMDIR_PLAY) {
340 } else {
341 }
342 return speed;
343}
344
345static int
346auchan_setblocksize(void *data, u_int32_t blocksize)
347{
348 return blocksize;
349}
350
351static int
352auchan_trigger(void *data, int go)
353{
354 struct au_chinfo *ch = data;
355 struct au_info *au = ch->parent;
|
356 if (ch->dir == PCMDIR_PLAY) {
357 au_setadb(au, 0x11, (go)? 1 : 0);
358 if (!go) {
359 au_wr(au, 0, 0xf800, 0, 4);
360 au_wr(au, 0, 0xf804, 0, 4);
361 au_delroute(au, 0x58);
362 au_delroute(au, 0x59);
363 }
364 } else {
365 }
366 return 0;
367}
368
369static int
370auchan_getptr(void *data)
371{
372 struct au_chinfo *ch = data;
373 struct au_info *au = ch->parent;
374 if (ch->dir == PCMDIR_PLAY) {
375 return au_rd(au, 0, AU_REG_UNK2, 4) & (AU_BUFFSIZE-1);
376 } else {
377 return 0;
378 }
379}
380
381static pcmchan_caps *
382auchan_getcaps(void *data)
383{
384 struct au_chinfo *ch = data;
385 return (ch->dir == PCMDIR_PLAY)? &au_playcaps : &au_reccaps;
386}
387
388/* The interrupt handler */
389static void
390au_intr (void *p)
391{
392 struct au_info *au = p;
393 u_int32_t intsrc, i;
394
395 au->interrupts++;
396 intsrc=au_rd(au, 0, AU_REG_IRQSRC, 4);
397 printf("pcm%d: interrupt with src %x\n", au->unit, intsrc);
398 if (intsrc & AU_IRQ_FATAL) printf("pcm%d: fatal error irq\n", au->unit);
399 if (intsrc & AU_IRQ_PARITY) printf("pcm%d: parity error irq\n", au->unit);
400 if (intsrc & AU_IRQ_UNKNOWN) {
401 (void)au_rd(au, 0, AU_REG_UNK1, 4);
402 au_wr(au, 0, AU_REG_UNK1, 0, 4);
403 au_wr(au, 0, AU_REG_UNK1, 0x10000, 4);
404 }
405 if (intsrc & AU_IRQ_PCMOUT) {
406 i=au_rd(au, 0, AU_REG_UNK2, 4) & (AU_BUFFSIZE-1);
407 chn_intr(au->pch.channel);
408 (void)au_rd(au, 0, AU_REG_UNK3, 4);
409 (void)au_rd(au, 0, AU_REG_UNK4, 4);
410 (void)au_rd(au, 0, AU_REG_UNK5, 4);
411 }
412/* don't support midi
413 if (intsrc & AU_IRQ_MIDI) {
414 i=au_rd(au, 0, 0x11004, 4);
415 j=10;
416 while (i & 0xff) {
417 if (j-- <= 0) break;
418 i=au_rd(au, 0, 0x11000, 4);
419 if ((au->midi_stat & 1) && (au->midi_out))
420 au->midi_out(au->midi_devno, i);
421 i=au_rd(au, 0, 0x11004);
422 }
423 }
424*/
425 au_wr(au, 0, AU_REG_IRQSRC, intsrc & 0x7ff, 4);
426 au_rd(au, 0, AU_REG_IRQSRC, 4);
427}
428
429
430/* -------------------------------------------------------------------- */
431
432/* Probe and attach the card */
433
434static int
435au_init(device_t dev, struct au_info *au)
436{
437 u_int32_t i, j;
438
439 au_wr(au, 0, AU_REG_IRQGLOB, 0xffffffff, 4);
440 DELAY(100000);
441
442 /* init codec */
443 /* cold reset */
444 for (i=0; i<32; i++) {
445 au_wr(au, 0, AU_REG_CODECCHN+(i<<2), 0, 4);
446 DELAY(10000);
447 }
448 if (1) {
449 au_wr(au, 0, AU_REG_CODECST, 0x8068, 4);
450 DELAY(10000);
451 au_wr(au, 0, AU_REG_CODECST, 0x00e8, 4);
452 DELAY(10000);
453 } else {
454 au_wr(au, 0, AU_REG_CODECST, 0x00a8, 4);
455 DELAY(100000);
456 au_wr(au, 0, AU_REG_CODECST, 0x80a8, 4);
457 DELAY(100000);
458 au_wr(au, 0, AU_REG_CODECST, 0x80e8, 4);
459 DELAY(100000);
460 au_wr(au, 0, AU_REG_CODECST, 0x80a8, 4);
461 DELAY(100000);
462 au_wr(au, 0, AU_REG_CODECST, 0x00a8, 4);
463 DELAY(100000);
464 au_wr(au, 0, AU_REG_CODECST, 0x00e8, 4);
465 DELAY(100000);
466 }
467
468 /* init */
469 for (i=0; i<32; i++) {
470 au_wr(au, 0, AU_REG_CODECCHN+(i<<2), 0, 4);
471 DELAY(10000);
472 }
473 au_wr(au, 0, AU_REG_CODECST, 0xe8, 4);
474 DELAY(10000);
475 au_wr(au, 0, AU_REG_CODECEN, 0, 4);
476
477 /* setup codec */
478 i=j=0;
479 while (j<100 && (i & AU_CDC_READY)==0) {
480 i=au_rd(au, 0, AU_REG_CODECST, 4);
481 DELAY(1000);
482 j++;
483 }
484 if (j==100) device_printf(dev, "codec not ready, status 0x%x\n", i);
485
486 /* init adb */
487 /*au->x5c=0;*/
488 for (i=0; i<32; i++) au->x[i]=i+0x67;
489 for (i=0; i<128; i++) au->y[i]=0x7f;
490 for (i=0; i<128; i++) au->z[i]=0x1f;
491 au_wr(au, 0, AU_REG_ADB, 0, 4);
492 for (i=0; i<124; i++) au_wr(au, 0, AU_REG_RTBASE+(i<<2), 0xffffffff, 4);
493
494 /* test */
495 i=au_rd(au, 0, 0x107c0, 4);
496 if (i!=0xdeadbeef) device_printf(dev, "dma check failed: 0x%x\n", i);
497
498 /* install mixer */
499 au_wr(au, 0, AU_REG_IRQGLOB,
500 au_rd(au, 0, AU_REG_IRQGLOB, 4) | AU_IRQ_ENABLE, 4);
501 /* braindead but it's what the oss/linux driver does
502 * for (i=0; i<0x80000000; i++) au_wr(au, 0, i<<2, 0, 4);
503 */
504 au->routes[0]=au->routes[1]=au->routes[2]=au->routes[3]=0;
505 /*au->x1e4=0;*/
506
507 /* attach channel */
508 au_addroute(au, 0x11, 0x48, 0x02);
509 au_addroute(au, 0x11, 0x49, 0x03);
510 au_encodec(au, 0);
511 au_encodec(au, 1);
512
513 for (i=0; i<48; i++) au_wr(au, 0, 0xf800+(i<<2), 0x20, 4);
514 for (i=2; i<6; i++) au_wr(au, 0, 0xf800+(i<<2), 0, 4);
515 au_wr(au, 0, 0xf8c0, 0x0843, 4);
516 for (i=0; i<4; i++) au_clrfifo(au, i);
517
518 return (0);
519}
520
521static int
522au_testirq(struct au_info *au)
523{
524 au_wr(au, 0, AU_REG_UNK1, 0x80001000, 4);
525 au_wr(au, 0, AU_REG_IRQEN, 0x00001030, 4);
526 au_wr(au, 0, AU_REG_IRQSRC, 0x000007ff, 4);
527 DELAY(1000000);
528 if (au->interrupts==0) printf("pcm%d: irq test failed\n", au->unit);
529 /* this apparently generates an irq */
530 return 0;
531}
532
533static int
534au_pci_probe(device_t dev)
535{
536 if (pci_get_devid(dev) == AU8820_PCI_ID) {
537 device_set_desc(dev, "Aureal Vortex 8820");
538 return 0;
539 }
540
541 return ENXIO;
542}
543
544static int
545au_pci_attach(device_t dev)
546{
547 snddev_info *d;
548 u_int32_t data;
549 struct au_info *au;
550 int type[10];
551 int regid[10];
552 struct resource *reg[10];
553 int i, j, mapped = 0;
554 int irqid;
555 struct resource *irq = 0;
556 void *ih = 0;
557 struct ac97_info *codec;
558 char status[SND_STATUSLEN];
559
560 d = device_get_softc(dev);
561 if ((au = malloc(sizeof(*au), M_DEVBUF, M_NOWAIT)) == NULL) {
562 device_printf(dev, "cannot allocate softc\n");
563 return ENXIO;
564 }
565
566 bzero(au, sizeof(*au));
567 au->unit = device_get_unit(dev);
568
569 data = pci_read_config(dev, PCIR_COMMAND, 2);
570 data |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN);
571 pci_write_config(dev, PCIR_COMMAND, data, 2);
572 data = pci_read_config(dev, PCIR_COMMAND, 2);
573
574 j=0;
575 /* XXX dfr: is this strictly necessary? */
576 for (i=0; i<PCI_MAXMAPS_0; i++) {
577#if 0
578 /* Slapped wrist: config_id and map are private structures */
579 if (bootverbose) {
580 printf("pcm%d: map %d - allocating ", unit, i+1);
581 printf("0x%x bytes of ", 1<<config_id->map[i].ln2size);
582 printf("%s space ", (config_id->map[i].type & PCI_MAPPORT)?
583 "io" : "memory");
584 printf("at 0x%x...", config_id->map[i].base);
585 }
586#endif
587 regid[j] = PCIR_MAPS + i*4;
588 type[j] = SYS_RES_MEMORY;
589 reg[j] = bus_alloc_resource(dev, type[j], ®id[j],
590 0, ~0, 1, RF_ACTIVE);
591 if (!reg[j]) {
592 type[j] = SYS_RES_IOPORT;
593 reg[j] = bus_alloc_resource(dev, type[j], ®id[j],
594 0, ~0, 1, RF_ACTIVE);
595 }
596 if (reg[j]) {
597 au->st[i] = rman_get_bustag(reg[j]);
598 au->sh[i] = rman_get_bushandle(reg[j]);
599 mapped++;
600 }
601#if 0
602 if (bootverbose) printf("%s\n", mapped? "ok" : "failed");
603#endif
604 if (mapped) j++;
605 if (j == 10) {
606 /* XXX */
607 device_printf(dev, "too many resources");
608 goto bad;
609 }
610 }
611
612#if 0
613 if (j < config_id->nummaps) {
614 printf("pcm%d: unable to map a required resource\n", unit);
615 free(au, M_DEVBUF);
616 return;
617 }
618#endif
619
620 au_wr(au, 0, AU_REG_IRQEN, 0, 4);
621
622 irqid = 0;
623 irq = bus_alloc_resource(dev, SYS_RES_IRQ, &irqid,
624 0, ~0, 1, RF_ACTIVE | RF_SHAREABLE);
625 if (!irq
626 || bus_setup_intr(dev, irq, INTR_TYPE_TTY, au_intr, au, &ih)) {
627 device_printf(dev, "unable to map interrupt\n");
628 goto bad;
629 }
630
631 if (au_testirq(au)) device_printf(dev, "irq test failed\n");
632
633 if (au_init(dev, au) == -1) {
634 device_printf(dev, "unable to initialize the card\n");
635 goto bad;
636 }
637
638 codec = ac97_create(au, au_rdcd, au_wrcd);
639 if (codec == NULL) goto bad;
640 mixer_init(d, &ac97_mixer, codec);
641
642 if (bus_dma_tag_create(/*parent*/NULL, /*alignment*/2, /*boundary*/0,
643 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
644 /*highaddr*/BUS_SPACE_MAXADDR,
645 /*filter*/NULL, /*filterarg*/NULL,
646 /*maxsize*/AU_BUFFSIZE, /*nsegments*/1, /*maxsegz*/0x3ffff,
647 /*flags*/0, &au->parent_dmat) != 0) {
648 device_printf(dev, "unable to create dma tag\n");
649 goto bad;
650 }
651
652 snprintf(status, SND_STATUSLEN, "at %s 0x%lx irq %ld",
653 (type[0] == SYS_RES_IOPORT)? "io" : "memory",
654 rman_get_start(reg[0]), rman_get_start(irq));
655
656 if (pcm_register(dev, au, 1, 1)) goto bad;
657 /* pcm_addchan(dev, PCMDIR_REC, &au_chantemplate, au); */
658 pcm_addchan(dev, PCMDIR_PLAY, &au_chantemplate, au);
659 pcm_setstatus(dev, status);
660
661 return 0;
662
663 bad:
664 if (au) free(au, M_DEVBUF);
665 for (i = 0; i < j; i++)
666 bus_release_resource(dev, type[i], regid[i], reg[i]);
667 if (ih) bus_teardown_intr(dev, irq, ih);
668 if (irq) bus_release_resource(dev, SYS_RES_IRQ, irqid, irq);
669 return ENXIO;
670}
671
672static device_method_t au_methods[] = {
673 /* Device interface */
674 DEVMETHOD(device_probe, au_pci_probe),
675 DEVMETHOD(device_attach, au_pci_attach),
676
677 { 0, 0 }
678};
679
680static driver_t au_driver = {
681 "pcm",
682 au_methods,
683 sizeof(snddev_info),
684};
685
686static devclass_t pcm_devclass;
687
688DRIVER_MODULE(au, pci, au_driver, pcm_devclass, 0, 0);
| 357 if (ch->dir == PCMDIR_PLAY) {
358 au_setadb(au, 0x11, (go)? 1 : 0);
359 if (!go) {
360 au_wr(au, 0, 0xf800, 0, 4);
361 au_wr(au, 0, 0xf804, 0, 4);
362 au_delroute(au, 0x58);
363 au_delroute(au, 0x59);
364 }
365 } else {
366 }
367 return 0;
368}
369
370static int
371auchan_getptr(void *data)
372{
373 struct au_chinfo *ch = data;
374 struct au_info *au = ch->parent;
375 if (ch->dir == PCMDIR_PLAY) {
376 return au_rd(au, 0, AU_REG_UNK2, 4) & (AU_BUFFSIZE-1);
377 } else {
378 return 0;
379 }
380}
381
382static pcmchan_caps *
383auchan_getcaps(void *data)
384{
385 struct au_chinfo *ch = data;
386 return (ch->dir == PCMDIR_PLAY)? &au_playcaps : &au_reccaps;
387}
388
389/* The interrupt handler */
390static void
391au_intr (void *p)
392{
393 struct au_info *au = p;
394 u_int32_t intsrc, i;
395
396 au->interrupts++;
397 intsrc=au_rd(au, 0, AU_REG_IRQSRC, 4);
398 printf("pcm%d: interrupt with src %x\n", au->unit, intsrc);
399 if (intsrc & AU_IRQ_FATAL) printf("pcm%d: fatal error irq\n", au->unit);
400 if (intsrc & AU_IRQ_PARITY) printf("pcm%d: parity error irq\n", au->unit);
401 if (intsrc & AU_IRQ_UNKNOWN) {
402 (void)au_rd(au, 0, AU_REG_UNK1, 4);
403 au_wr(au, 0, AU_REG_UNK1, 0, 4);
404 au_wr(au, 0, AU_REG_UNK1, 0x10000, 4);
405 }
406 if (intsrc & AU_IRQ_PCMOUT) {
407 i=au_rd(au, 0, AU_REG_UNK2, 4) & (AU_BUFFSIZE-1);
408 chn_intr(au->pch.channel);
409 (void)au_rd(au, 0, AU_REG_UNK3, 4);
410 (void)au_rd(au, 0, AU_REG_UNK4, 4);
411 (void)au_rd(au, 0, AU_REG_UNK5, 4);
412 }
413/* don't support midi
414 if (intsrc & AU_IRQ_MIDI) {
415 i=au_rd(au, 0, 0x11004, 4);
416 j=10;
417 while (i & 0xff) {
418 if (j-- <= 0) break;
419 i=au_rd(au, 0, 0x11000, 4);
420 if ((au->midi_stat & 1) && (au->midi_out))
421 au->midi_out(au->midi_devno, i);
422 i=au_rd(au, 0, 0x11004);
423 }
424 }
425*/
426 au_wr(au, 0, AU_REG_IRQSRC, intsrc & 0x7ff, 4);
427 au_rd(au, 0, AU_REG_IRQSRC, 4);
428}
429
430
431/* -------------------------------------------------------------------- */
432
433/* Probe and attach the card */
434
435static int
436au_init(device_t dev, struct au_info *au)
437{
438 u_int32_t i, j;
439
440 au_wr(au, 0, AU_REG_IRQGLOB, 0xffffffff, 4);
441 DELAY(100000);
442
443 /* init codec */
444 /* cold reset */
445 for (i=0; i<32; i++) {
446 au_wr(au, 0, AU_REG_CODECCHN+(i<<2), 0, 4);
447 DELAY(10000);
448 }
449 if (1) {
450 au_wr(au, 0, AU_REG_CODECST, 0x8068, 4);
451 DELAY(10000);
452 au_wr(au, 0, AU_REG_CODECST, 0x00e8, 4);
453 DELAY(10000);
454 } else {
455 au_wr(au, 0, AU_REG_CODECST, 0x00a8, 4);
456 DELAY(100000);
457 au_wr(au, 0, AU_REG_CODECST, 0x80a8, 4);
458 DELAY(100000);
459 au_wr(au, 0, AU_REG_CODECST, 0x80e8, 4);
460 DELAY(100000);
461 au_wr(au, 0, AU_REG_CODECST, 0x80a8, 4);
462 DELAY(100000);
463 au_wr(au, 0, AU_REG_CODECST, 0x00a8, 4);
464 DELAY(100000);
465 au_wr(au, 0, AU_REG_CODECST, 0x00e8, 4);
466 DELAY(100000);
467 }
468
469 /* init */
470 for (i=0; i<32; i++) {
471 au_wr(au, 0, AU_REG_CODECCHN+(i<<2), 0, 4);
472 DELAY(10000);
473 }
474 au_wr(au, 0, AU_REG_CODECST, 0xe8, 4);
475 DELAY(10000);
476 au_wr(au, 0, AU_REG_CODECEN, 0, 4);
477
478 /* setup codec */
479 i=j=0;
480 while (j<100 && (i & AU_CDC_READY)==0) {
481 i=au_rd(au, 0, AU_REG_CODECST, 4);
482 DELAY(1000);
483 j++;
484 }
485 if (j==100) device_printf(dev, "codec not ready, status 0x%x\n", i);
486
487 /* init adb */
488 /*au->x5c=0;*/
489 for (i=0; i<32; i++) au->x[i]=i+0x67;
490 for (i=0; i<128; i++) au->y[i]=0x7f;
491 for (i=0; i<128; i++) au->z[i]=0x1f;
492 au_wr(au, 0, AU_REG_ADB, 0, 4);
493 for (i=0; i<124; i++) au_wr(au, 0, AU_REG_RTBASE+(i<<2), 0xffffffff, 4);
494
495 /* test */
496 i=au_rd(au, 0, 0x107c0, 4);
497 if (i!=0xdeadbeef) device_printf(dev, "dma check failed: 0x%x\n", i);
498
499 /* install mixer */
500 au_wr(au, 0, AU_REG_IRQGLOB,
501 au_rd(au, 0, AU_REG_IRQGLOB, 4) | AU_IRQ_ENABLE, 4);
502 /* braindead but it's what the oss/linux driver does
503 * for (i=0; i<0x80000000; i++) au_wr(au, 0, i<<2, 0, 4);
504 */
505 au->routes[0]=au->routes[1]=au->routes[2]=au->routes[3]=0;
506 /*au->x1e4=0;*/
507
508 /* attach channel */
509 au_addroute(au, 0x11, 0x48, 0x02);
510 au_addroute(au, 0x11, 0x49, 0x03);
511 au_encodec(au, 0);
512 au_encodec(au, 1);
513
514 for (i=0; i<48; i++) au_wr(au, 0, 0xf800+(i<<2), 0x20, 4);
515 for (i=2; i<6; i++) au_wr(au, 0, 0xf800+(i<<2), 0, 4);
516 au_wr(au, 0, 0xf8c0, 0x0843, 4);
517 for (i=0; i<4; i++) au_clrfifo(au, i);
518
519 return (0);
520}
521
522static int
523au_testirq(struct au_info *au)
524{
525 au_wr(au, 0, AU_REG_UNK1, 0x80001000, 4);
526 au_wr(au, 0, AU_REG_IRQEN, 0x00001030, 4);
527 au_wr(au, 0, AU_REG_IRQSRC, 0x000007ff, 4);
528 DELAY(1000000);
529 if (au->interrupts==0) printf("pcm%d: irq test failed\n", au->unit);
530 /* this apparently generates an irq */
531 return 0;
532}
533
534static int
535au_pci_probe(device_t dev)
536{
537 if (pci_get_devid(dev) == AU8820_PCI_ID) {
538 device_set_desc(dev, "Aureal Vortex 8820");
539 return 0;
540 }
541
542 return ENXIO;
543}
544
545static int
546au_pci_attach(device_t dev)
547{
548 snddev_info *d;
549 u_int32_t data;
550 struct au_info *au;
551 int type[10];
552 int regid[10];
553 struct resource *reg[10];
554 int i, j, mapped = 0;
555 int irqid;
556 struct resource *irq = 0;
557 void *ih = 0;
558 struct ac97_info *codec;
559 char status[SND_STATUSLEN];
560
561 d = device_get_softc(dev);
562 if ((au = malloc(sizeof(*au), M_DEVBUF, M_NOWAIT)) == NULL) {
563 device_printf(dev, "cannot allocate softc\n");
564 return ENXIO;
565 }
566
567 bzero(au, sizeof(*au));
568 au->unit = device_get_unit(dev);
569
570 data = pci_read_config(dev, PCIR_COMMAND, 2);
571 data |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN);
572 pci_write_config(dev, PCIR_COMMAND, data, 2);
573 data = pci_read_config(dev, PCIR_COMMAND, 2);
574
575 j=0;
576 /* XXX dfr: is this strictly necessary? */
577 for (i=0; i<PCI_MAXMAPS_0; i++) {
578#if 0
579 /* Slapped wrist: config_id and map are private structures */
580 if (bootverbose) {
581 printf("pcm%d: map %d - allocating ", unit, i+1);
582 printf("0x%x bytes of ", 1<<config_id->map[i].ln2size);
583 printf("%s space ", (config_id->map[i].type & PCI_MAPPORT)?
584 "io" : "memory");
585 printf("at 0x%x...", config_id->map[i].base);
586 }
587#endif
588 regid[j] = PCIR_MAPS + i*4;
589 type[j] = SYS_RES_MEMORY;
590 reg[j] = bus_alloc_resource(dev, type[j], ®id[j],
591 0, ~0, 1, RF_ACTIVE);
592 if (!reg[j]) {
593 type[j] = SYS_RES_IOPORT;
594 reg[j] = bus_alloc_resource(dev, type[j], ®id[j],
595 0, ~0, 1, RF_ACTIVE);
596 }
597 if (reg[j]) {
598 au->st[i] = rman_get_bustag(reg[j]);
599 au->sh[i] = rman_get_bushandle(reg[j]);
600 mapped++;
601 }
602#if 0
603 if (bootverbose) printf("%s\n", mapped? "ok" : "failed");
604#endif
605 if (mapped) j++;
606 if (j == 10) {
607 /* XXX */
608 device_printf(dev, "too many resources");
609 goto bad;
610 }
611 }
612
613#if 0
614 if (j < config_id->nummaps) {
615 printf("pcm%d: unable to map a required resource\n", unit);
616 free(au, M_DEVBUF);
617 return;
618 }
619#endif
620
621 au_wr(au, 0, AU_REG_IRQEN, 0, 4);
622
623 irqid = 0;
624 irq = bus_alloc_resource(dev, SYS_RES_IRQ, &irqid,
625 0, ~0, 1, RF_ACTIVE | RF_SHAREABLE);
626 if (!irq
627 || bus_setup_intr(dev, irq, INTR_TYPE_TTY, au_intr, au, &ih)) {
628 device_printf(dev, "unable to map interrupt\n");
629 goto bad;
630 }
631
632 if (au_testirq(au)) device_printf(dev, "irq test failed\n");
633
634 if (au_init(dev, au) == -1) {
635 device_printf(dev, "unable to initialize the card\n");
636 goto bad;
637 }
638
639 codec = ac97_create(au, au_rdcd, au_wrcd);
640 if (codec == NULL) goto bad;
641 mixer_init(d, &ac97_mixer, codec);
642
643 if (bus_dma_tag_create(/*parent*/NULL, /*alignment*/2, /*boundary*/0,
644 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
645 /*highaddr*/BUS_SPACE_MAXADDR,
646 /*filter*/NULL, /*filterarg*/NULL,
647 /*maxsize*/AU_BUFFSIZE, /*nsegments*/1, /*maxsegz*/0x3ffff,
648 /*flags*/0, &au->parent_dmat) != 0) {
649 device_printf(dev, "unable to create dma tag\n");
650 goto bad;
651 }
652
653 snprintf(status, SND_STATUSLEN, "at %s 0x%lx irq %ld",
654 (type[0] == SYS_RES_IOPORT)? "io" : "memory",
655 rman_get_start(reg[0]), rman_get_start(irq));
656
657 if (pcm_register(dev, au, 1, 1)) goto bad;
658 /* pcm_addchan(dev, PCMDIR_REC, &au_chantemplate, au); */
659 pcm_addchan(dev, PCMDIR_PLAY, &au_chantemplate, au);
660 pcm_setstatus(dev, status);
661
662 return 0;
663
664 bad:
665 if (au) free(au, M_DEVBUF);
666 for (i = 0; i < j; i++)
667 bus_release_resource(dev, type[i], regid[i], reg[i]);
668 if (ih) bus_teardown_intr(dev, irq, ih);
669 if (irq) bus_release_resource(dev, SYS_RES_IRQ, irqid, irq);
670 return ENXIO;
671}
672
673static device_method_t au_methods[] = {
674 /* Device interface */
675 DEVMETHOD(device_probe, au_pci_probe),
676 DEVMETHOD(device_attach, au_pci_attach),
677
678 { 0, 0 }
679};
680
681static driver_t au_driver = {
682 "pcm",
683 au_methods,
684 sizeof(snddev_info),
685};
686
687static devclass_t pcm_devclass;
688
689DRIVER_MODULE(au, pci, au_driver, pcm_devclass, 0, 0);
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