36/* 37 * This is a driver for SMC's 9000 series of Ethernet adapters. 38 * 39 * This FreeBSD driver is derived from the smc9194 Linux driver by 40 * Erik Stahlman and is Copyright (C) 1996 by Erik Stahlman. 41 * This driver also shamelessly borrows from the FreeBSD ep driver 42 * which is Copyright (C) 1994 Herb Peyerl <hpeyerl@novatel.ca> 43 * All rights reserved. 44 * 45 * It is set up for my SMC91C92 equipped Ampro LittleBoard embedded 46 * PC. It is adapted from Erik Stahlman's Linux driver which worked 47 * with his EFA Info*Express SVC VLB adaptor. According to SMC's databook, 48 * it will work for the entire SMC 9xxx series. (Ha Ha) 49 * 50 * "Features" of the SMC chip: 51 * 4608 byte packet memory. (for the 91C92. Others have more) 52 * EEPROM for configuration 53 * AUI/TP selection 54 * 55 * Authors: 56 * Erik Stahlman erik@vt.edu 57 * Herb Peyerl hpeyerl@novatel.ca 58 * Andres Vega Garcia avega@sophia.inria.fr 59 * Serge Babkin babkin@hq.icb.chel.su 60 * Gardner Buchanan gbuchanan@shl.com 61 * 62 * Sources: 63 * o SMC databook 64 * o "smc9194.c:v0.10(FIXED) 02/15/96 by Erik Stahlman (erik@vt.edu)" 65 * o "if_ep.c,v 1.19 1995/01/24 20:53:45 davidg Exp" 66 * 67 * Known Bugs: 68 * o The hardware multicast filter isn't used yet. 69 * o Setting of the hardware address isn't supported. 70 * o Hardware padding isn't used. 71 */ 72 73/* 74 * Modifications for Megahertz X-Jack Ethernet Card (XJ-10BT) 75 * 76 * Copyright (c) 1996 by Tatsumi Hosokawa <hosokawa@jp.FreeBSD.org> 77 * BSD-nomads, Tokyo, Japan. 78 */ 79/* 80 * Multicast support by Kei TANAKA <kei@pal.xerox.com> 81 * Special thanks to itojun@itojun.org 82 */ 83 84#include <sys/param.h> 85#include <sys/systm.h> 86#include <sys/errno.h> 87#include <sys/sockio.h> 88#include <sys/mbuf.h> 89#include <sys/socket.h> 90#include <sys/syslog.h> 91 92#include <sys/module.h> 93#include <sys/bus.h> 94 95#include <machine/bus.h> 96#include <machine/resource.h> 97#include <sys/rman.h> 98 99#include <net/ethernet.h> 100#include <net/if.h> 101#include <net/if_arp.h> 102#include <net/if_dl.h> 103#include <net/if_types.h> 104#include <net/if_mib.h> 105 106#ifdef INET 107#include <netinet/in.h> 108#include <netinet/in_systm.h> 109#include <netinet/in_var.h> 110#include <netinet/ip.h> 111#endif 112 113#include <net/bpf.h> 114#include <net/bpfdesc.h> 115 116 117#include <dev/sn/if_snreg.h> 118#include <dev/sn/if_snvar.h> 119 120/* Exported variables */ 121devclass_t sn_devclass; 122 123static int snioctl(struct ifnet * ifp, u_long, caddr_t); 124 125static void snresume(struct ifnet *); 126 127void sninit(void *); 128void snread(struct ifnet *); 129void snreset(struct sn_softc *); 130void snstart(struct ifnet *); 131void snstop(struct sn_softc *); 132void snwatchdog(struct ifnet *); 133 134static void sn_setmcast(struct sn_softc *); 135static int sn_getmcf(struct arpcom *ac, u_char *mcf); 136static u_int smc_crc(u_char *); 137 138/* I (GB) have been unlucky getting the hardware padding 139 * to work properly. 140 */ 141#define SW_PAD 142 143static const char *chip_ids[15] = { 144 NULL, NULL, NULL, 145 /* 3 */ "SMC91C90/91C92", 146 /* 4 */ "SMC91C94", 147 /* 5 */ "SMC91C95", 148 NULL, 149 /* 7 */ "SMC91C100", 150 /* 8 */ "SMC91C100FD", 151 NULL, NULL, NULL, 152 NULL, NULL, NULL 153}; 154 155int 156sn_attach(device_t dev) 157{ 158 struct sn_softc *sc = device_get_softc(dev); 159 struct ifnet *ifp = &sc->arpcom.ac_if; 160 u_short i; 161 u_char *p; 162 struct ifaddr *ifa; 163 struct sockaddr_dl *sdl; 164 int rev; 165 u_short address; 166 int j; 167 168 sn_activate(dev); 169 170 snstop(sc); 171 172 sc->dev = dev; 173 sc->pages_wanted = -1; 174 175 device_printf(dev, " "); 176 177 SMC_SELECT_BANK(3); 178 rev = inw(BASE + REVISION_REG_W); 179 if (chip_ids[(rev >> 4) & 0xF]) 180 printf("%s ", chip_ids[(rev >> 4) & 0xF]); 181 182 SMC_SELECT_BANK(1); 183 i = inw(BASE + CONFIG_REG_W); 184 printf(i & CR_AUI_SELECT ? "AUI" : "UTP"); 185 186 if (sc->pccard_enaddr) 187 for (j = 0; j < 3; j++) { 188 u_short w; 189 190 w = (u_short)sc->arpcom.ac_enaddr[j * 2] | 191 (((u_short)sc->arpcom.ac_enaddr[j * 2 + 1]) << 8); 192 outw(BASE + IAR_ADDR0_REG_W + j * 2, w); 193 } 194 195 /* 196 * Read the station address from the chip. The MAC address is bank 1, 197 * regs 4 - 9 198 */ 199 SMC_SELECT_BANK(1); 200 p = (u_char *) & sc->arpcom.ac_enaddr; 201 for (i = 0; i < 6; i += 2) { 202 address = inw(BASE + IAR_ADDR0_REG_W + i); 203 p[i + 1] = address >> 8; 204 p[i] = address & 0xFF; 205 } 206 printf(" MAC address %6D\n", sc->arpcom.ac_enaddr, ":"); 207 ifp->if_softc = sc; 208 ifp->if_unit = device_get_unit(dev); 209 ifp->if_name = "sn"; 210 ifp->if_mtu = ETHERMTU; 211 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 212 ifp->if_output = ether_output; 213 ifp->if_start = snstart; 214 ifp->if_ioctl = snioctl; 215 ifp->if_watchdog = snwatchdog; 216 ifp->if_init = sninit; 217 ifp->if_snd.ifq_maxlen = IFQ_MAXLEN; 218 ifp->if_timer = 0; 219 220 ether_ifattach(ifp, sc->arpcom.ac_enaddr); 221 222 /* 223 * Fill the hardware address into ifa_addr if we find an AF_LINK 224 * entry. We need to do this so bpf's can get the hardware addr of 225 * this card. netstat likes this too! 226 */ 227 ifa = TAILQ_FIRST(&ifp->if_addrhead); 228 while ((ifa != 0) && (ifa->ifa_addr != 0) && 229 (ifa->ifa_addr->sa_family != AF_LINK)) 230 ifa = TAILQ_NEXT(ifa, ifa_link); 231 232 if ((ifa != 0) && (ifa->ifa_addr != 0)) { 233 sdl = (struct sockaddr_dl *) ifa->ifa_addr; 234 sdl->sdl_type = IFT_ETHER; 235 sdl->sdl_alen = ETHER_ADDR_LEN; 236 sdl->sdl_slen = 0; 237 bcopy(sc->arpcom.ac_enaddr, LLADDR(sdl), ETHER_ADDR_LEN); 238 } 239 240 return 0; 241} 242 243 244int 245sn_detach(device_t dev) 246{ 247 struct sn_softc *sc = device_get_softc(dev); 248 249 sc->arpcom.ac_if.if_flags &= ~IFF_RUNNING; 250 ether_ifdetach(&sc->arpcom.ac_if); 251 sn_deactivate(dev); 252 return 0; 253} 254 255/* 256 * Reset and initialize the chip 257 */ 258void 259sninit(void *xsc) 260{ 261 register struct sn_softc *sc = xsc; 262 register struct ifnet *ifp = &sc->arpcom.ac_if; 263 int s; 264 int flags; 265 int mask; 266 267 s = splimp(); 268 269 /* 270 * This resets the registers mostly to defaults, but doesn't affect 271 * EEPROM. After the reset cycle, we pause briefly for the chip to 272 * be happy. 273 */ 274 SMC_SELECT_BANK(0); 275 outw(BASE + RECV_CONTROL_REG_W, RCR_SOFTRESET); 276 SMC_DELAY(); 277 outw(BASE + RECV_CONTROL_REG_W, 0x0000); 278 SMC_DELAY(); 279 SMC_DELAY(); 280 281 outw(BASE + TXMIT_CONTROL_REG_W, 0x0000); 282 283 /* 284 * Set the control register to automatically release succesfully 285 * transmitted packets (making the best use out of our limited 286 * memory) and to enable the EPH interrupt on certain TX errors. 287 */ 288 SMC_SELECT_BANK(1); 289 outw(BASE + CONTROL_REG_W, (CTR_AUTO_RELEASE | CTR_TE_ENABLE | 290 CTR_CR_ENABLE | CTR_LE_ENABLE)); 291 292 /* Set squelch level to 240mV (default 480mV) */ 293 flags = inw(BASE + CONFIG_REG_W); 294 flags |= CR_SET_SQLCH; 295 outw(BASE + CONFIG_REG_W, flags); 296 297 /* 298 * Reset the MMU and wait for it to be un-busy. 299 */ 300 SMC_SELECT_BANK(2); 301 outw(BASE + MMU_CMD_REG_W, MMUCR_RESET); 302 while (inw(BASE + MMU_CMD_REG_W) & MMUCR_BUSY) /* NOTHING */ 303 ; 304 305 /* 306 * Disable all interrupts 307 */ 308 outb(BASE + INTR_MASK_REG_B, 0x00); 309 310 sn_setmcast(sc); 311 312 /* 313 * Set the transmitter control. We want it enabled. 314 */ 315 flags = TCR_ENABLE; 316 317#ifndef SW_PAD 318 /* 319 * I (GB) have been unlucky getting this to work. 320 */ 321 flags |= TCR_PAD_ENABLE; 322#endif /* SW_PAD */ 323 324 outw(BASE + TXMIT_CONTROL_REG_W, flags); 325 326 327 /* 328 * Now, enable interrupts 329 */ 330 SMC_SELECT_BANK(2); 331 332 mask = IM_EPH_INT | 333 IM_RX_OVRN_INT | 334 IM_RCV_INT | 335 IM_TX_INT; 336 337 outb(BASE + INTR_MASK_REG_B, mask); 338 sc->intr_mask = mask; 339 sc->pages_wanted = -1; 340 341 342 /* 343 * Mark the interface running but not active. 344 */ 345 ifp->if_flags |= IFF_RUNNING; 346 ifp->if_flags &= ~IFF_OACTIVE; 347 348 /* 349 * Attempt to push out any waiting packets. 350 */ 351 snstart(ifp); 352 353 splx(s); 354} 355 356 357void 358snstart(struct ifnet *ifp) 359{ 360 register struct sn_softc *sc = ifp->if_softc; 361 register u_int len; 362 register struct mbuf *m; 363 struct mbuf *top; 364 int s, pad; 365 int mask; 366 u_short length; 367 u_short numPages; 368 u_char packet_no; 369 int time_out; 370 int junk = 0; 371 372 s = splimp(); 373 374 if (sc->arpcom.ac_if.if_flags & IFF_OACTIVE) { 375 splx(s); 376 return; 377 } 378 if (sc->pages_wanted != -1) { 379 splx(s); 380 if_printf(ifp, "snstart() while memory allocation pending\n"); 381 return; 382 } 383startagain: 384 385 /* 386 * Sneak a peek at the next packet 387 */ 388 m = sc->arpcom.ac_if.if_snd.ifq_head; 389 if (m == 0) { 390 splx(s); 391 return; 392 } 393 /* 394 * Compute the frame length and set pad to give an overall even 395 * number of bytes. Below we assume that the packet length is even. 396 */ 397 for (len = 0, top = m; m; m = m->m_next) 398 len += m->m_len; 399 400 pad = (len & 1); 401 402 /* 403 * We drop packets that are too large. Perhaps we should truncate 404 * them instead? 405 */ 406 if (len + pad > ETHER_MAX_LEN - ETHER_CRC_LEN) { 407 if_printf(ifp, "large packet discarded (A)\n"); 408 ++sc->arpcom.ac_if.if_oerrors; 409 IF_DEQUEUE(&sc->arpcom.ac_if.if_snd, m); 410 m_freem(m); 411 goto readcheck; 412 } 413#ifdef SW_PAD 414 415 /* 416 * If HW padding is not turned on, then pad to ETHER_MIN_LEN. 417 */ 418 if (len < ETHER_MIN_LEN - ETHER_CRC_LEN) 419 pad = ETHER_MIN_LEN - ETHER_CRC_LEN - len; 420 421#endif /* SW_PAD */ 422 423 length = pad + len; 424 425 /* 426 * The MMU wants the number of pages to be the number of 256 byte 427 * 'pages', minus 1 (A packet can't ever have 0 pages. We also 428 * include space for the status word, byte count and control bytes in 429 * the allocation request. 430 */ 431 numPages = (length + 6) >> 8; 432 433 434 /* 435 * Now, try to allocate the memory 436 */ 437 SMC_SELECT_BANK(2); 438 outw(BASE + MMU_CMD_REG_W, MMUCR_ALLOC | numPages); 439 440 /* 441 * Wait a short amount of time to see if the allocation request 442 * completes. Otherwise, I enable the interrupt and wait for 443 * completion asyncronously. 444 */ 445 446 time_out = MEMORY_WAIT_TIME; 447 do { 448 if (inb(BASE + INTR_STAT_REG_B) & IM_ALLOC_INT) 449 break; 450 } while (--time_out); 451 452 if (!time_out || junk > 10) { 453 454 /* 455 * No memory now. Oh well, wait until the chip finds memory 456 * later. Remember how many pages we were asking for and 457 * enable the allocation completion interrupt. Also set a 458 * watchdog in case we miss the interrupt. We mark the 459 * interface active since there is no point in attempting an 460 * snstart() until after the memory is available. 461 */ 462 mask = inb(BASE + INTR_MASK_REG_B) | IM_ALLOC_INT; 463 outb(BASE + INTR_MASK_REG_B, mask); 464 sc->intr_mask = mask; 465 466 sc->arpcom.ac_if.if_timer = 1; 467 sc->arpcom.ac_if.if_flags |= IFF_OACTIVE; 468 sc->pages_wanted = numPages; 469 470 splx(s); 471 return; 472 } 473 /* 474 * The memory allocation completed. Check the results. 475 */ 476 packet_no = inb(BASE + ALLOC_RESULT_REG_B); 477 if (packet_no & ARR_FAILED) { 478 if (junk++ > 10) 479 if_printf(ifp, "Memory allocation failed\n"); 480 goto startagain; 481 } 482 /* 483 * We have a packet number, so tell the card to use it. 484 */ 485 outb(BASE + PACKET_NUM_REG_B, packet_no); 486 487 /* 488 * Point to the beginning of the packet 489 */ 490 outw(BASE + POINTER_REG_W, PTR_AUTOINC | 0x0000); 491 492 /* 493 * Send the packet length (+6 for status, length and control byte) 494 * and the status word (set to zeros) 495 */ 496 outw(BASE + DATA_REG_W, 0); 497 outb(BASE + DATA_REG_B, (length + 6) & 0xFF); 498 outb(BASE + DATA_REG_B, (length + 6) >> 8); 499 500 /* 501 * Get the packet from the kernel. This will include the Ethernet 502 * frame header, MAC Addresses etc. 503 */ 504 IF_DEQUEUE(&sc->arpcom.ac_if.if_snd, m); 505 506 /* 507 * Push out the data to the card. 508 */ 509 for (top = m; m != 0; m = m->m_next) { 510 511 /* 512 * Push out words. 513 */ 514 outsw(BASE + DATA_REG_W, mtod(m, caddr_t), m->m_len / 2); 515 516 /* 517 * Push out remaining byte. 518 */ 519 if (m->m_len & 1) 520 outb(BASE + DATA_REG_B, *(mtod(m, caddr_t) + m->m_len - 1)); 521 } 522 523 /* 524 * Push out padding. 525 */ 526 while (pad > 1) { 527 outw(BASE + DATA_REG_W, 0); 528 pad -= 2; 529 } 530 if (pad) 531 outb(BASE + DATA_REG_B, 0); 532 533 /* 534 * Push out control byte and unused packet byte The control byte is 0 535 * meaning the packet is even lengthed and no special CRC handling is 536 * desired. 537 */ 538 outw(BASE + DATA_REG_W, 0); 539 540 /* 541 * Enable the interrupts and let the chipset deal with it Also set a 542 * watchdog in case we miss the interrupt. 543 */ 544 mask = inb(BASE + INTR_MASK_REG_B) | (IM_TX_INT | IM_TX_EMPTY_INT); 545 outb(BASE + INTR_MASK_REG_B, mask); 546 sc->intr_mask = mask; 547 548 outw(BASE + MMU_CMD_REG_W, MMUCR_ENQUEUE); 549 550 sc->arpcom.ac_if.if_flags |= IFF_OACTIVE; 551 sc->arpcom.ac_if.if_timer = 1; 552 553 BPF_MTAP(ifp, top); 554 555 sc->arpcom.ac_if.if_opackets++; 556 m_freem(top); 557 558 559readcheck: 560 561 /* 562 * Is another packet coming in? We don't want to overflow the tiny 563 * RX FIFO. If nothing has arrived then attempt to queue another 564 * transmit packet. 565 */ 566 if (inw(BASE + FIFO_PORTS_REG_W) & FIFO_REMPTY) 567 goto startagain; 568 569 splx(s); 570 return; 571} 572 573 574 575/* Resume a packet transmit operation after a memory allocation 576 * has completed. 577 * 578 * This is basically a hacked up copy of snstart() which handles 579 * a completed memory allocation the same way snstart() does. 580 * It then passes control to snstart to handle any other queued 581 * packets. 582 */ 583static void 584snresume(struct ifnet *ifp) 585{ 586 register struct sn_softc *sc = ifp->if_softc; 587 register u_int len; 588 register struct mbuf *m; 589 struct mbuf *top; 590 int pad; 591 int mask; 592 u_short length; 593 u_short numPages; 594 u_short pages_wanted; 595 u_char packet_no; 596 597 if (sc->pages_wanted < 0) 598 return; 599 600 pages_wanted = sc->pages_wanted; 601 sc->pages_wanted = -1; 602 603 /* 604 * Sneak a peek at the next packet 605 */ 606 m = sc->arpcom.ac_if.if_snd.ifq_head; 607 if (m == 0) { 608 if_printf(ifp, "snresume() with nothing to send\n"); 609 return; 610 } 611 /* 612 * Compute the frame length and set pad to give an overall even 613 * number of bytes. Below we assume that the packet length is even. 614 */ 615 for (len = 0, top = m; m; m = m->m_next) 616 len += m->m_len; 617 618 pad = (len & 1); 619 620 /* 621 * We drop packets that are too large. Perhaps we should truncate 622 * them instead? 623 */ 624 if (len + pad > ETHER_MAX_LEN - ETHER_CRC_LEN) { 625 if_printf(ifp, "large packet discarded (B)\n"); 626 ++sc->arpcom.ac_if.if_oerrors; 627 IF_DEQUEUE(&sc->arpcom.ac_if.if_snd, m); 628 m_freem(m); 629 return; 630 } 631#ifdef SW_PAD 632 633 /* 634 * If HW padding is not turned on, then pad to ETHER_MIN_LEN. 635 */ 636 if (len < ETHER_MIN_LEN - ETHER_CRC_LEN) 637 pad = ETHER_MIN_LEN - ETHER_CRC_LEN - len; 638 639#endif /* SW_PAD */ 640 641 length = pad + len; 642 643 644 /* 645 * The MMU wants the number of pages to be the number of 256 byte 646 * 'pages', minus 1 (A packet can't ever have 0 pages. We also 647 * include space for the status word, byte count and control bytes in 648 * the allocation request. 649 */ 650 numPages = (length + 6) >> 8; 651 652 653 SMC_SELECT_BANK(2); 654 655 /* 656 * The memory allocation completed. Check the results. If it failed, 657 * we simply set a watchdog timer and hope for the best. 658 */ 659 packet_no = inb(BASE + ALLOC_RESULT_REG_B); 660 if (packet_no & ARR_FAILED) { 661 if_printf(ifp, "Memory allocation failed. Weird.\n"); 662 sc->arpcom.ac_if.if_timer = 1; 663 goto try_start; 664 } 665 /* 666 * We have a packet number, so tell the card to use it. 667 */ 668 outb(BASE + PACKET_NUM_REG_B, packet_no); 669 670 /* 671 * Now, numPages should match the pages_wanted recorded when the 672 * memory allocation was initiated. 673 */ 674 if (pages_wanted != numPages) { 675 if_printf(ifp, "memory allocation wrong size. Weird.\n"); 676 /* 677 * If the allocation was the wrong size we simply release the 678 * memory once it is granted. Wait for the MMU to be un-busy. 679 */ 680 while (inw(BASE + MMU_CMD_REG_W) & MMUCR_BUSY) /* NOTHING */ 681 ; 682 outw(BASE + MMU_CMD_REG_W, MMUCR_FREEPKT); 683 684 return; 685 } 686 /* 687 * Point to the beginning of the packet 688 */ 689 outw(BASE + POINTER_REG_W, PTR_AUTOINC | 0x0000); 690 691 /* 692 * Send the packet length (+6 for status, length and control byte) 693 * and the status word (set to zeros) 694 */ 695 outw(BASE + DATA_REG_W, 0); 696 outb(BASE + DATA_REG_B, (length + 6) & 0xFF); 697 outb(BASE + DATA_REG_B, (length + 6) >> 8); 698 699 /* 700 * Get the packet from the kernel. This will include the Ethernet 701 * frame header, MAC Addresses etc. 702 */ 703 IF_DEQUEUE(&sc->arpcom.ac_if.if_snd, m); 704 705 /* 706 * Push out the data to the card. 707 */ 708 for (top = m; m != 0; m = m->m_next) { 709 710 /* 711 * Push out words. 712 */ 713 outsw(BASE + DATA_REG_W, mtod(m, caddr_t), m->m_len / 2); 714 715 /* 716 * Push out remaining byte. 717 */ 718 if (m->m_len & 1) 719 outb(BASE + DATA_REG_B, *(mtod(m, caddr_t) + m->m_len - 1)); 720 } 721 722 /* 723 * Push out padding. 724 */ 725 while (pad > 1) { 726 outw(BASE + DATA_REG_W, 0); 727 pad -= 2; 728 } 729 if (pad) 730 outb(BASE + DATA_REG_B, 0); 731 732 /* 733 * Push out control byte and unused packet byte The control byte is 0 734 * meaning the packet is even lengthed and no special CRC handling is 735 * desired. 736 */ 737 outw(BASE + DATA_REG_W, 0); 738 739 /* 740 * Enable the interrupts and let the chipset deal with it Also set a 741 * watchdog in case we miss the interrupt. 742 */ 743 mask = inb(BASE + INTR_MASK_REG_B) | (IM_TX_INT | IM_TX_EMPTY_INT); 744 outb(BASE + INTR_MASK_REG_B, mask); 745 sc->intr_mask = mask; 746 outw(BASE + MMU_CMD_REG_W, MMUCR_ENQUEUE); 747 748 BPF_MTAP(ifp, top); 749 750 sc->arpcom.ac_if.if_opackets++; 751 m_freem(top); 752 753try_start: 754 755 /* 756 * Now pass control to snstart() to queue any additional packets 757 */ 758 sc->arpcom.ac_if.if_flags &= ~IFF_OACTIVE; 759 snstart(ifp); 760 761 /* 762 * We've sent something, so we're active. Set a watchdog in case the 763 * TX_EMPTY interrupt is lost. 764 */ 765 sc->arpcom.ac_if.if_flags |= IFF_OACTIVE; 766 sc->arpcom.ac_if.if_timer = 1; 767 768 return; 769} 770 771 772void 773sn_intr(void *arg) 774{ 775 int status, interrupts; 776 register struct sn_softc *sc = (struct sn_softc *) arg; 777 struct ifnet *ifp = &sc->arpcom.ac_if; 778 int x; 779 780 /* 781 * Chip state registers 782 */ 783 u_char mask; 784 u_char packet_no; 785 u_short tx_status; 786 u_short card_stats; 787 788 /* 789 * if_ep.c did this, so I do too. Yet if_ed.c doesn't. I wonder... 790 */ 791 x = splbio(); 792 793 /* 794 * Clear the watchdog. 795 */ 796 ifp->if_timer = 0; 797 798 SMC_SELECT_BANK(2); 799 800 /* 801 * Obtain the current interrupt mask and clear the hardware mask 802 * while servicing interrupts. 803 */ 804 mask = inb(BASE + INTR_MASK_REG_B); 805 outb(BASE + INTR_MASK_REG_B, 0x00); 806 807 /* 808 * Get the set of interrupts which occurred and eliminate any which 809 * are masked. 810 */ 811 interrupts = inb(BASE + INTR_STAT_REG_B); 812 status = interrupts & mask; 813 814 /* 815 * Now, process each of the interrupt types. 816 */ 817 818 /* 819 * Receive Overrun. 820 */ 821 if (status & IM_RX_OVRN_INT) { 822 /* 823 * Acknowlege Interrupt 824 */ 825 SMC_SELECT_BANK(2); 826 outb(BASE + INTR_ACK_REG_B, IM_RX_OVRN_INT); 827 828 ++sc->arpcom.ac_if.if_ierrors; 829 } 830 /* 831 * Got a packet. 832 */ 833 if (status & IM_RCV_INT) { 834 int packet_number; 835 836 SMC_SELECT_BANK(2); 837 packet_number = inw(BASE + FIFO_PORTS_REG_W); 838 839 if (packet_number & FIFO_REMPTY) { 840 /* 841 * we got called , but nothing was on the FIFO 842 */ 843 printf("sn: Receive interrupt with nothing on FIFO\n"); 844 goto out; 845 } 846 snread(ifp); 847 } 848 /* 849 * An on-card memory allocation came through. 850 */ 851 if (status & IM_ALLOC_INT) { 852 /* 853 * Disable this interrupt. 854 */ 855 mask &= ~IM_ALLOC_INT; 856 sc->arpcom.ac_if.if_flags &= ~IFF_OACTIVE; 857 snresume(&sc->arpcom.ac_if); 858 } 859 /* 860 * TX Completion. Handle a transmit error message. This will only be 861 * called when there is an error, because of the AUTO_RELEASE mode. 862 */ 863 if (status & IM_TX_INT) { 864 /* 865 * Acknowlege Interrupt 866 */ 867 SMC_SELECT_BANK(2); 868 outb(BASE + INTR_ACK_REG_B, IM_TX_INT); 869 870 packet_no = inw(BASE + FIFO_PORTS_REG_W); 871 packet_no &= FIFO_TX_MASK; 872 873 /* 874 * select this as the packet to read from 875 */ 876 outb(BASE + PACKET_NUM_REG_B, packet_no); 877 878 /* 879 * Position the pointer to the first word from this packet 880 */ 881 outw(BASE + POINTER_REG_W, PTR_AUTOINC | PTR_READ | 0x0000); 882 883 /* 884 * Fetch the TX status word. The value found here will be a 885 * copy of the EPH_STATUS_REG_W at the time the transmit 886 * failed. 887 */ 888 tx_status = inw(BASE + DATA_REG_W); 889 890 if (tx_status & EPHSR_TX_SUC) { 891 device_printf(sc->dev, 892 "Successful packet caused interrupt\n"); 893 } else { 894 ++sc->arpcom.ac_if.if_oerrors; 895 } 896 897 if (tx_status & EPHSR_LATCOL) 898 ++sc->arpcom.ac_if.if_collisions; 899 900 /* 901 * Some of these errors will have disabled transmit. 902 * Re-enable transmit now. 903 */ 904 SMC_SELECT_BANK(0); 905 906#ifdef SW_PAD 907 outw(BASE + TXMIT_CONTROL_REG_W, TCR_ENABLE); 908#else 909 outw(BASE + TXMIT_CONTROL_REG_W, TCR_ENABLE | TCR_PAD_ENABLE); 910#endif /* SW_PAD */ 911 912 /* 913 * kill the failed packet. Wait for the MMU to be un-busy. 914 */ 915 SMC_SELECT_BANK(2); 916 while (inw(BASE + MMU_CMD_REG_W) & MMUCR_BUSY) /* NOTHING */ 917 ; 918 outw(BASE + MMU_CMD_REG_W, MMUCR_FREEPKT); 919 920 /* 921 * Attempt to queue more transmits. 922 */ 923 sc->arpcom.ac_if.if_flags &= ~IFF_OACTIVE; 924 snstart(&sc->arpcom.ac_if); 925 } 926 /* 927 * Transmit underrun. We use this opportunity to update transmit 928 * statistics from the card. 929 */ 930 if (status & IM_TX_EMPTY_INT) { 931 932 /* 933 * Acknowlege Interrupt 934 */ 935 SMC_SELECT_BANK(2); 936 outb(BASE + INTR_ACK_REG_B, IM_TX_EMPTY_INT); 937 938 /* 939 * Disable this interrupt. 940 */ 941 mask &= ~IM_TX_EMPTY_INT; 942 943 SMC_SELECT_BANK(0); 944 card_stats = inw(BASE + COUNTER_REG_W); 945 946 /* 947 * Single collisions 948 */ 949 sc->arpcom.ac_if.if_collisions += card_stats & ECR_COLN_MASK; 950 951 /* 952 * Multiple collisions 953 */ 954 sc->arpcom.ac_if.if_collisions += (card_stats & ECR_MCOLN_MASK) >> 4; 955 956 SMC_SELECT_BANK(2); 957 958 /* 959 * Attempt to enqueue some more stuff. 960 */ 961 sc->arpcom.ac_if.if_flags &= ~IFF_OACTIVE; 962 snstart(&sc->arpcom.ac_if); 963 } 964 /* 965 * Some other error. Try to fix it by resetting the adapter. 966 */ 967 if (status & IM_EPH_INT) { 968 snstop(sc); 969 sninit(sc); 970 } 971 972out: 973 /* 974 * Handled all interrupt sources. 975 */ 976 977 SMC_SELECT_BANK(2); 978 979 /* 980 * Reestablish interrupts from mask which have not been deselected 981 * during this interrupt. Note that the hardware mask, which was set 982 * to 0x00 at the start of this service routine, may have been 983 * updated by one or more of the interrupt handers and we must let 984 * those new interrupts stay enabled here. 985 */ 986 mask |= inb(BASE + INTR_MASK_REG_B); 987 outb(BASE + INTR_MASK_REG_B, mask); 988 sc->intr_mask = mask; 989 990 splx(x); 991} 992 993void 994snread(register struct ifnet *ifp) 995{ 996 struct sn_softc *sc = ifp->if_softc; 997 struct ether_header *eh; 998 struct mbuf *m; 999 short status; 1000 int packet_number; 1001 u_short packet_length; 1002 u_char *data; 1003 1004 SMC_SELECT_BANK(2); 1005#if 0 1006 packet_number = inw(BASE + FIFO_PORTS_REG_W); 1007 1008 if (packet_number & FIFO_REMPTY) { 1009 1010 /* 1011 * we got called , but nothing was on the FIFO 1012 */ 1013 printf("sn: Receive interrupt with nothing on FIFO\n"); 1014 return; 1015 } 1016#endif 1017read_another: 1018 1019 /* 1020 * Start reading from the start of the packet. Since PTR_RCV is set, 1021 * packet number is found in FIFO_PORTS_REG_W, FIFO_RX_MASK. 1022 */ 1023 outw(BASE + POINTER_REG_W, PTR_READ | PTR_RCV | PTR_AUTOINC | 0x0000); 1024 1025 /* 1026 * First two words are status and packet_length 1027 */ 1028 status = inw(BASE + DATA_REG_W); 1029 packet_length = inw(BASE + DATA_REG_W) & RLEN_MASK; 1030 1031 /* 1032 * The packet length contains 3 extra words: status, length, and a 1033 * extra word with the control byte. 1034 */ 1035 packet_length -= 6; 1036 1037 /* 1038 * Account for receive errors and discard. 1039 */ 1040 if (status & RS_ERRORS) { 1041 ++sc->arpcom.ac_if.if_ierrors; 1042 goto out; 1043 } 1044 /* 1045 * A packet is received. 1046 */ 1047 1048 /* 1049 * Adjust for odd-length packet. 1050 */ 1051 if (status & RS_ODDFRAME) 1052 packet_length++; 1053 1054 /* 1055 * Allocate a header mbuf from the kernel. 1056 */ 1057 MGETHDR(m, M_DONTWAIT, MT_DATA); 1058 if (m == NULL) 1059 goto out; 1060 1061 m->m_pkthdr.rcvif = &sc->arpcom.ac_if; 1062 m->m_pkthdr.len = m->m_len = packet_length; 1063 1064 /* 1065 * Attach an mbuf cluster 1066 */ 1067 MCLGET(m, M_DONTWAIT); 1068 1069 /* 1070 * Insist on getting a cluster 1071 */ 1072 if ((m->m_flags & M_EXT) == 0) { 1073 m_freem(m); 1074 ++sc->arpcom.ac_if.if_ierrors; 1075 printf("sn: snread() kernel memory allocation problem\n"); 1076 goto out; 1077 } 1078 eh = mtod(m, struct ether_header *); 1079 1080 /* 1081 * Get packet, including link layer address, from interface. 1082 */ 1083 1084 data = (u_char *) eh; 1085 insw(BASE + DATA_REG_W, data, packet_length >> 1); 1086 if (packet_length & 1) { 1087 data += packet_length & ~1; 1088 *data = inb(BASE + DATA_REG_B); 1089 } 1090 ++sc->arpcom.ac_if.if_ipackets; 1091 1092 /* 1093 * Remove link layer addresses and whatnot. 1094 */ 1095 m->m_pkthdr.len = m->m_len = packet_length; 1096 1097 (*ifp->if_input)(ifp, m); 1098 1099out: 1100 1101 /* 1102 * Error or good, tell the card to get rid of this packet Wait for 1103 * the MMU to be un-busy. 1104 */ 1105 SMC_SELECT_BANK(2); 1106 while (inw(BASE + MMU_CMD_REG_W) & MMUCR_BUSY) /* NOTHING */ 1107 ; 1108 outw(BASE + MMU_CMD_REG_W, MMUCR_RELEASE); 1109 1110 /* 1111 * Check whether another packet is ready 1112 */ 1113 packet_number = inw(BASE + FIFO_PORTS_REG_W); 1114 if (packet_number & FIFO_REMPTY) { 1115 return; 1116 } 1117 goto read_another; 1118} 1119 1120 1121/* 1122 * Handle IOCTLS. This function is completely stolen from if_ep.c 1123 * As with its progenitor, it does not handle hardware address 1124 * changes. 1125 */ 1126static int 1127snioctl(register struct ifnet *ifp, u_long cmd, caddr_t data) 1128{ 1129 struct sn_softc *sc = ifp->if_softc; 1130 int s, error = 0; 1131 1132 s = splimp(); 1133 1134 switch (cmd) { 1135 case SIOCSIFFLAGS: 1136 if ((ifp->if_flags & IFF_UP) == 0 && ifp->if_flags & IFF_RUNNING) { 1137 ifp->if_flags &= ~IFF_RUNNING; 1138 snstop(sc); 1139 break; 1140 } else { 1141 /* reinitialize card on any parameter change */ 1142 sninit(sc); 1143 break; 1144 } 1145 break; 1146 1147#ifdef notdef 1148 case SIOCGHWADDR: 1149 bcopy((caddr_t) sc->sc_addr, (caddr_t) & ifr->ifr_data, 1150 sizeof(sc->sc_addr)); 1151 break; 1152#endif 1153 1154 case SIOCADDMULTI: 1155 /* update multicast filter list. */ 1156 sn_setmcast(sc); 1157 error = 0; 1158 break; 1159 case SIOCDELMULTI: 1160 /* update multicast filter list. */ 1161 sn_setmcast(sc); 1162 error = 0; 1163 break; 1164 default: 1165 error = EINVAL; 1166 error = ether_ioctl(ifp, cmd, data); 1167 break; 1168 } 1169 1170 splx(s); 1171 1172 return (error); 1173} 1174 1175void 1176snreset(struct sn_softc *sc) 1177{ 1178 int s; 1179 1180 s = splimp(); 1181 snstop(sc); 1182 sninit(sc); 1183 1184 splx(s); 1185} 1186 1187void 1188snwatchdog(struct ifnet *ifp) 1189{ 1190 int s; 1191 s = splimp(); 1192 sn_intr(ifp->if_softc); 1193 splx(s); 1194} 1195 1196 1197/* 1. zero the interrupt mask 1198 * 2. clear the enable receive flag 1199 * 3. clear the enable xmit flags 1200 */ 1201void 1202snstop(struct sn_softc *sc) 1203{ 1204 1205 struct ifnet *ifp = &sc->arpcom.ac_if; 1206 1207 /* 1208 * Clear interrupt mask; disable all interrupts. 1209 */ 1210 SMC_SELECT_BANK(2); 1211 outb(BASE + INTR_MASK_REG_B, 0x00); 1212 1213 /* 1214 * Disable transmitter and Receiver 1215 */ 1216 SMC_SELECT_BANK(0); 1217 outw(BASE + RECV_CONTROL_REG_W, 0x0000); 1218 outw(BASE + TXMIT_CONTROL_REG_W, 0x0000); 1219 1220 /* 1221 * Cancel watchdog. 1222 */ 1223 ifp->if_timer = 0; 1224} 1225 1226 1227int 1228sn_activate(device_t dev) 1229{ 1230 struct sn_softc *sc = device_get_softc(dev); 1231 int err; 1232 1233 sc->port_rid = 0; 1234 sc->port_res = bus_alloc_resource(dev, SYS_RES_IOPORT, &sc->port_rid, 1235 0, ~0, SMC_IO_EXTENT, RF_ACTIVE); 1236 if (!sc->port_res) { 1237 if (bootverbose) 1238 device_printf(dev, "Cannot allocate ioport\n"); 1239 return ENOMEM; 1240 } 1241 1242 sc->irq_rid = 0; 1243 sc->irq_res = bus_alloc_resource(dev, SYS_RES_IRQ, &sc->irq_rid, 1244 0, ~0, 1, RF_ACTIVE); 1245 if (!sc->irq_res) { 1246 if (bootverbose) 1247 device_printf(dev, "Cannot allocate irq\n"); 1248 sn_deactivate(dev); 1249 return ENOMEM; 1250 } 1251 if ((err = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_NET, sn_intr, sc, 1252 &sc->intrhand)) != 0) { 1253 sn_deactivate(dev); 1254 return err; 1255 } 1256 1257 sc->sn_io_addr = rman_get_start(sc->port_res); 1258 return (0); 1259} 1260 1261void 1262sn_deactivate(device_t dev) 1263{ 1264 struct sn_softc *sc = device_get_softc(dev); 1265 1266 if (sc->intrhand) 1267 bus_teardown_intr(dev, sc->irq_res, sc->intrhand); 1268 sc->intrhand = 0; 1269 if (sc->port_res) 1270 bus_release_resource(dev, SYS_RES_IOPORT, sc->port_rid, 1271 sc->port_res); 1272 sc->port_res = 0; 1273 if (sc->irq_res) 1274 bus_release_resource(dev, SYS_RES_IRQ, sc->irq_rid, 1275 sc->irq_res); 1276 sc->irq_res = 0; 1277 return; 1278} 1279 1280/* 1281 * Function: sn_probe( device_t dev, int pccard ) 1282 * 1283 * Purpose: 1284 * Tests to see if a given ioaddr points to an SMC9xxx chip. 1285 * Tries to cause as little damage as possible if it's not a SMC chip. 1286 * Returns a 0 on success 1287 * 1288 * Algorithm: 1289 * (1) see if the high byte of BANK_SELECT is 0x33 1290 * (2) compare the ioaddr with the base register's address 1291 * (3) see if I recognize the chip ID in the appropriate register 1292 * 1293 * 1294 */ 1295int 1296sn_probe(device_t dev, int pccard) 1297{ 1298 struct sn_softc *sc = device_get_softc(dev); 1299 u_int bank; 1300 u_short revision_register; 1301 u_short base_address_register; 1302 u_short ioaddr; 1303 int err; 1304 1305 if ((err = sn_activate(dev)) != 0) 1306 return err; 1307 1308 ioaddr = sc->sn_io_addr; 1309#ifdef SN_DEBUG 1310 device_printf(dev, "ioaddr is 0x%x\n", ioaddr); 1311#endif 1312 /* 1313 * First, see if the high byte is 0x33 1314 */ 1315 bank = inw(ioaddr + BANK_SELECT_REG_W); 1316 if ((bank & BSR_DETECT_MASK) != BSR_DETECT_VALUE) { 1317#ifdef SN_DEBUG 1318 device_printf(dev, "test1 failed\n"); 1319#endif 1320 goto error; 1321 } 1322 /* 1323 * The above MIGHT indicate a device, but I need to write to further 1324 * test this. Go to bank 0, then test that the register still 1325 * reports the high byte is 0x33. 1326 */ 1327 outw(ioaddr + BANK_SELECT_REG_W, 0x0000); 1328 bank = inw(ioaddr + BANK_SELECT_REG_W); 1329 if ((bank & BSR_DETECT_MASK) != BSR_DETECT_VALUE) { 1330#ifdef SN_DEBUG 1331 device_printf(dev, "test2 failed\n"); 1332#endif 1333 goto error; 1334 } 1335 /* 1336 * well, we've already written once, so hopefully another time won't 1337 * hurt. This time, I need to switch the bank register to bank 1, so 1338 * I can access the base address register. The contents of the 1339 * BASE_ADDR_REG_W register, after some jiggery pokery, is expected 1340 * to match the I/O port address where the adapter is being probed. 1341 */ 1342 outw(ioaddr + BANK_SELECT_REG_W, 0x0001); 1343 base_address_register = inw(ioaddr + BASE_ADDR_REG_W); 1344 1345 /* 1346 * This test is nonsence on PC-card architecture, so if 1347 * pccard == 1, skip this test. (hosokawa) 1348 */ 1349 if (!pccard && (ioaddr != (base_address_register >> 3 & 0x3E0))) { 1350 1351 /* 1352 * Well, the base address register didn't match. Must not 1353 * have been a SMC chip after all. 1354 */ 1355#ifdef SN_DEBUG 1356 device_printf(dev, "test3 failed ioaddr = 0x%x, " 1357 "base_address_register = 0x%x\n", ioaddr, 1358 base_address_register >> 3 & 0x3E0); 1359#endif 1360 goto error; 1361 } 1362 1363 /* 1364 * Check if the revision register is something that I recognize. 1365 * These might need to be added to later, as future revisions could 1366 * be added. 1367 */ 1368 outw(ioaddr + BANK_SELECT_REG_W, 0x3); 1369 revision_register = inw(ioaddr + REVISION_REG_W); 1370 if (!chip_ids[(revision_register >> 4) & 0xF]) { 1371 1372 /* 1373 * I don't regonize this chip, so... 1374 */ 1375#ifdef SN_DEBUG 1376 device_printf(dev, "test4 failed\n"); 1377#endif 1378 goto error; 1379 } 1380 1381 /* 1382 * at this point I'll assume that the chip is an SMC9xxx. It might be 1383 * prudent to check a listing of MAC addresses against the hardware 1384 * address, or do some other tests. 1385 */ 1386 sn_deactivate(dev); 1387 return 0; 1388 error: 1389 sn_deactivate(dev); 1390 return ENXIO; 1391} 1392 1393#define MCFSZ 8 1394 1395static void 1396sn_setmcast(struct sn_softc *sc) 1397{ 1398 struct ifnet *ifp = (struct ifnet *)sc; 1399 int flags; 1400 1401 /* 1402 * Set the receiver filter. We want receive enabled and auto strip 1403 * of CRC from received packet. If we are promiscuous then set that 1404 * bit too. 1405 */ 1406 flags = RCR_ENABLE | RCR_STRIP_CRC; 1407 1408 if (ifp->if_flags & IFF_PROMISC) { 1409 flags |= RCR_PROMISC | RCR_ALMUL; 1410 } else if (ifp->if_flags & IFF_ALLMULTI) { 1411 flags |= RCR_ALMUL; 1412 } else { 1413 u_char mcf[MCFSZ]; 1414 if (sn_getmcf(&sc->arpcom, mcf)) { 1415 /* set filter */ 1416 SMC_SELECT_BANK(3); 1417 outw(BASE + MULTICAST1_REG_W, 1418 ((u_short)mcf[1] << 8) | mcf[0]); 1419 outw(BASE + MULTICAST2_REG_W, 1420 ((u_short)mcf[3] << 8) | mcf[2]); 1421 outw(BASE + MULTICAST3_REG_W, 1422 ((u_short)mcf[5] << 8) | mcf[4]); 1423 outw(BASE + MULTICAST4_REG_W, 1424 ((u_short)mcf[7] << 8) | mcf[6]); 1425 } else { 1426 flags |= RCR_ALMUL; 1427 } 1428 } 1429 SMC_SELECT_BANK(0); 1430 outw(BASE + RECV_CONTROL_REG_W, flags); 1431} 1432 1433static int 1434sn_getmcf(struct arpcom *ac, u_char *mcf) 1435{ 1436 int i; 1437 register u_int index, index2; 1438 register u_char *af = (u_char *) mcf; 1439 struct ifmultiaddr *ifma; 1440 1441 bzero(mcf, MCFSZ); 1442 1443 TAILQ_FOREACH(ifma, &ac->ac_if.if_multiaddrs, ifma_link) { 1444 if (ifma->ifma_addr->sa_family != AF_LINK) 1445 return 0; 1446 index = smc_crc(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)) & 0x3f; 1447 index2 = 0; 1448 for (i = 0; i < 6; i++) { 1449 index2 <<= 1; 1450 index2 |= (index & 0x01); 1451 index >>= 1; 1452 } 1453 af[index2 >> 3] |= 1 << (index2 & 7); 1454 } 1455 return 1; /* use multicast filter */ 1456} 1457 1458static u_int 1459smc_crc(u_char *s) 1460{ 1461 int perByte; 1462 int perBit; 1463 const u_int poly = 0xedb88320; 1464 u_int v = 0xffffffff; 1465 u_char c; 1466 1467 for (perByte = 0; perByte < ETHER_ADDR_LEN; perByte++) { 1468 c = s[perByte]; 1469 for (perBit = 0; perBit < 8; perBit++) { 1470 v = (v >> 1)^(((v ^ c) & 0x01) ? poly : 0); 1471 c >>= 1; 1472 } 1473 } 1474 return v; 1475}
|