34
35/*
36 * This is a driver for SMC's 9000 series of Ethernet adapters.
37 *
38 * This FreeBSD driver is derived from the smc9194 Linux driver by
39 * Erik Stahlman and is Copyright (C) 1996 by Erik Stahlman.
40 * This driver also shamelessly borrows from the FreeBSD ep driver
41 * which is Copyright (C) 1994 Herb Peyerl <hpeyerl@novatel.ca>
42 * All rights reserved.
43 *
44 * It is set up for my SMC91C92 equipped Ampro LittleBoard embedded
45 * PC. It is adapted from Erik Stahlman's Linux driver which worked
46 * with his EFA Info*Express SVC VLB adaptor. According to SMC's databook,
47 * it will work for the entire SMC 9xxx series. (Ha Ha)
48 *
49 * "Features" of the SMC chip:
50 * 4608 byte packet memory. (for the 91C92. Others have more)
51 * EEPROM for configuration
52 * AUI/TP selection
53 *
54 * Authors:
55 * Erik Stahlman erik@vt.edu
56 * Herb Peyerl hpeyerl@novatel.ca
57 * Andres Vega Garcia avega@sophia.inria.fr
58 * Serge Babkin babkin@hq.icb.chel.su
59 * Gardner Buchanan gbuchanan@shl.com
60 *
61 * Sources:
62 * o SMC databook
63 * o "smc9194.c:v0.10(FIXED) 02/15/96 by Erik Stahlman (erik@vt.edu)"
64 * o "if_ep.c,v 1.19 1995/01/24 20:53:45 davidg Exp"
65 *
66 * Known Bugs:
67 * o Setting of the hardware address isn't supported.
68 * o Hardware padding isn't used.
69 */
70
71/*
72 * Modifications for Megahertz X-Jack Ethernet Card (XJ-10BT)
73 *
74 * Copyright (c) 1996 by Tatsumi Hosokawa <hosokawa@jp.FreeBSD.org>
75 * BSD-nomads, Tokyo, Japan.
76 */
77/*
78 * Multicast support by Kei TANAKA <kei@pal.xerox.com>
79 * Special thanks to itojun@itojun.org
80 */
81
82#include <sys/param.h>
83#include <sys/systm.h>
84#include <sys/errno.h>
85#include <sys/kernel.h>
86#include <sys/sockio.h>
87#include <sys/mbuf.h>
88#include <sys/socket.h>
89#include <sys/syslog.h>
90
91#include <sys/module.h>
92#include <sys/bus.h>
93
94#include <machine/bus.h>
95#include <machine/resource.h>
96#include <sys/rman.h>
97
98#include <net/ethernet.h>
99#include <net/if.h>
100#include <net/if_arp.h>
101#include <net/if_dl.h>
102#include <net/if_types.h>
103#include <net/if_mib.h>
104
105#ifdef INET
106#include <netinet/in.h>
107#include <netinet/in_systm.h>
108#include <netinet/in_var.h>
109#include <netinet/ip.h>
110#endif
111
112#include <net/bpf.h>
113#include <net/bpfdesc.h>
114
115#include <dev/sn/if_snreg.h>
116#include <dev/sn/if_snvar.h>
117
118/* Exported variables */
119devclass_t sn_devclass;
120
121static int snioctl(struct ifnet * ifp, u_long, caddr_t);
122
123static void snresume(struct ifnet *);
124
125static void snintr_locked(struct sn_softc *);
126static void sninit_locked(void *);
127static void snstart_locked(struct ifnet *);
128
129static void sninit(void *);
130static void snread(struct ifnet *);
131static void snstart(struct ifnet *);
132static void snstop(struct sn_softc *);
133static void snwatchdog(void *);
134
135static void sn_setmcast(struct sn_softc *);
136static int sn_getmcf(struct ifnet *ifp, u_char *mcf);
137
138/* I (GB) have been unlucky getting the hardware padding
139 * to work properly.
140 */
141#define SW_PAD
142
143static const char *chip_ids[15] = {
144 NULL, NULL, NULL,
145 /* 3 */ "SMC91C90/91C92",
146 /* 4 */ "SMC91C94/91C96",
147 /* 5 */ "SMC91C95",
148 NULL,
149 /* 7 */ "SMC91C100",
150 /* 8 */ "SMC91C100FD",
151 /* 9 */ "SMC91C110",
152 NULL, NULL,
153 NULL, NULL, NULL
154};
155
156int
157sn_attach(device_t dev)
158{
159 struct sn_softc *sc = device_get_softc(dev);
160 struct ifnet *ifp;
161 uint16_t i;
162 uint8_t *p;
163 int rev;
164 uint16_t address;
165 int err;
166 u_char eaddr[6];
167
168 ifp = sc->ifp = if_alloc(IFT_ETHER);
169 if (ifp == NULL) {
170 device_printf(dev, "can not if_alloc()\n");
171 return (ENOSPC);
172 }
173
174 SN_LOCK_INIT(sc);
175 callout_init_mtx(&sc->watchdog, &sc->sc_mtx, 0);
176 snstop(sc);
177 sc->pages_wanted = -1;
178
179 if (bootverbose || 1) {
180 SMC_SELECT_BANK(sc, 3);
181 rev = (CSR_READ_2(sc, REVISION_REG_W) >> 4) & 0xf;
182 if (chip_ids[rev])
183 device_printf(dev, " %s ", chip_ids[rev]);
184 else
185 device_printf(dev, " unsupported chip: rev %d ", rev);
186 SMC_SELECT_BANK(sc, 1);
187 i = CSR_READ_2(sc, CONFIG_REG_W);
188 printf("%s\n", i & CR_AUI_SELECT ? "AUI" : "UTP");
189 }
190
191 /*
192 * Read the station address from the chip. The MAC address is bank 1,
193 * regs 4 - 9
194 */
195 SMC_SELECT_BANK(sc, 1);
196 p = (uint8_t *) eaddr;
197 for (i = 0; i < 6; i += 2) {
198 address = CSR_READ_2(sc, IAR_ADDR0_REG_W + i);
199 p[i + 1] = address >> 8;
200 p[i] = address & 0xFF;
201 }
202 ifp->if_softc = sc;
203 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
204 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
205 ifp->if_start = snstart;
206 ifp->if_ioctl = snioctl;
207 ifp->if_init = sninit;
208 ifp->if_baudrate = 10000000;
209 IFQ_SET_MAXLEN(&ifp->if_snd, ifqmaxlen);
210 ifp->if_snd.ifq_maxlen = ifqmaxlen;
211 IFQ_SET_READY(&ifp->if_snd);
212
213 ether_ifattach(ifp, eaddr);
214
215 /*
216 * Activate the interrupt so we can get card interrupts. This
217 * needs to be done last so that we don't have/hold the lock
218 * during startup to avoid LORs in the network layer.
219 */
220 if ((err = bus_setup_intr(dev, sc->irq_res,
221 INTR_TYPE_NET | INTR_MPSAFE, NULL, sn_intr, sc,
222 &sc->intrhand)) != 0) {
223 sn_detach(dev);
224 return err;
225 }
226 return 0;
227}
228
229
230int
231sn_detach(device_t dev)
232{
233 struct sn_softc *sc = device_get_softc(dev);
234 struct ifnet *ifp = sc->ifp;
235
236 ether_ifdetach(ifp);
237 SN_LOCK(sc);
238 snstop(sc);
239 SN_UNLOCK(sc);
240 callout_drain(&sc->watchdog);
241 sn_deactivate(dev);
242 if_free(ifp);
243 SN_LOCK_DESTROY(sc);
244 return 0;
245}
246
247static void
248sninit(void *xsc)
249{
250 struct sn_softc *sc = xsc;
251 SN_LOCK(sc);
252 sninit_locked(sc);
253 SN_UNLOCK(sc);
254}
255
256/*
257 * Reset and initialize the chip
258 */
259static void
260sninit_locked(void *xsc)
261{
262 struct sn_softc *sc = xsc;
263 struct ifnet *ifp = sc->ifp;
264 int flags;
265 int mask;
266
267 SN_ASSERT_LOCKED(sc);
268
269 /*
270 * This resets the registers mostly to defaults, but doesn't affect
271 * EEPROM. After the reset cycle, we pause briefly for the chip to
272 * be happy.
273 */
274 SMC_SELECT_BANK(sc, 0);
275 CSR_WRITE_2(sc, RECV_CONTROL_REG_W, RCR_SOFTRESET);
276 SMC_DELAY(sc);
277 CSR_WRITE_2(sc, RECV_CONTROL_REG_W, 0x0000);
278 SMC_DELAY(sc);
279 SMC_DELAY(sc);
280
281 CSR_WRITE_2(sc, TXMIT_CONTROL_REG_W, 0x0000);
282
283 /*
284 * Set the control register to automatically release succesfully
285 * transmitted packets (making the best use out of our limited
286 * memory) and to enable the EPH interrupt on certain TX errors.
287 */
288 SMC_SELECT_BANK(sc, 1);
289 CSR_WRITE_2(sc, CONTROL_REG_W, (CTR_AUTO_RELEASE | CTR_TE_ENABLE |
290 CTR_CR_ENABLE | CTR_LE_ENABLE));
291
292 /* Set squelch level to 240mV (default 480mV) */
293 flags = CSR_READ_2(sc, CONFIG_REG_W);
294 flags |= CR_SET_SQLCH;
295 CSR_WRITE_2(sc, CONFIG_REG_W, flags);
296
297 /*
298 * Reset the MMU and wait for it to be un-busy.
299 */
300 SMC_SELECT_BANK(sc, 2);
301 CSR_WRITE_2(sc, MMU_CMD_REG_W, MMUCR_RESET);
302 while (CSR_READ_2(sc, MMU_CMD_REG_W) & MMUCR_BUSY) /* NOTHING */
303 ;
304
305 /*
306 * Disable all interrupts
307 */
308 CSR_WRITE_1(sc, INTR_MASK_REG_B, 0x00);
309
310 sn_setmcast(sc);
311
312 /*
313 * Set the transmitter control. We want it enabled.
314 */
315 flags = TCR_ENABLE;
316
317#ifndef SW_PAD
318 /*
319 * I (GB) have been unlucky getting this to work.
320 */
321 flags |= TCR_PAD_ENABLE;
322#endif /* SW_PAD */
323
324 CSR_WRITE_2(sc, TXMIT_CONTROL_REG_W, flags);
325
326
327 /*
328 * Now, enable interrupts
329 */
330 SMC_SELECT_BANK(sc, 2);
331
332 mask = IM_EPH_INT |
333 IM_RX_OVRN_INT |
334 IM_RCV_INT |
335 IM_TX_INT;
336
337 CSR_WRITE_1(sc, INTR_MASK_REG_B, mask);
338 sc->intr_mask = mask;
339 sc->pages_wanted = -1;
340
341
342 /*
343 * Mark the interface running but not active.
344 */
345 ifp->if_drv_flags |= IFF_DRV_RUNNING;
346 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
347 callout_reset(&sc->watchdog, hz, snwatchdog, sc);
348
349 /*
350 * Attempt to push out any waiting packets.
351 */
352 snstart_locked(ifp);
353}
354
355static void
356snstart(struct ifnet *ifp)
357{
358 struct sn_softc *sc = ifp->if_softc;
359 SN_LOCK(sc);
360 snstart_locked(ifp);
361 SN_UNLOCK(sc);
362}
363
364
365static void
366snstart_locked(struct ifnet *ifp)
367{
368 struct sn_softc *sc = ifp->if_softc;
369 u_int len;
370 struct mbuf *m;
371 struct mbuf *top;
372 int pad;
373 int mask;
374 uint16_t length;
375 uint16_t numPages;
376 uint8_t packet_no;
377 int time_out;
378 int junk = 0;
379
380 SN_ASSERT_LOCKED(sc);
381
382 if (ifp->if_drv_flags & IFF_DRV_OACTIVE)
383 return;
384 if (sc->pages_wanted != -1) {
385 if_printf(ifp, "snstart() while memory allocation pending\n");
386 return;
387 }
388startagain:
389
390 /*
391 * Sneak a peek at the next packet
392 */
393 m = ifp->if_snd.ifq_head;
394 if (m == 0)
395 return;
396 /*
397 * Compute the frame length and set pad to give an overall even
398 * number of bytes. Below we assume that the packet length is even.
399 */
400 for (len = 0, top = m; m; m = m->m_next)
401 len += m->m_len;
402
403 pad = (len & 1);
404
405 /*
406 * We drop packets that are too large. Perhaps we should truncate
407 * them instead?
408 */
409 if (len + pad > ETHER_MAX_LEN - ETHER_CRC_LEN) {
410 if_printf(ifp, "large packet discarded (A)\n");
411 ++ifp->if_oerrors;
412 IFQ_DRV_DEQUEUE(&ifp->if_snd, m);
413 m_freem(m);
414 goto readcheck;
415 }
416#ifdef SW_PAD
417
418 /*
419 * If HW padding is not turned on, then pad to ETHER_MIN_LEN.
420 */
421 if (len < ETHER_MIN_LEN - ETHER_CRC_LEN)
422 pad = ETHER_MIN_LEN - ETHER_CRC_LEN - len;
423
424#endif /* SW_PAD */
425
426 length = pad + len;
427
428 /*
429 * The MMU wants the number of pages to be the number of 256 byte
430 * 'pages', minus 1 (A packet can't ever have 0 pages. We also
431 * include space for the status word, byte count and control bytes in
432 * the allocation request.
433 */
434 numPages = (length + 6) >> 8;
435
436
437 /*
438 * Now, try to allocate the memory
439 */
440 SMC_SELECT_BANK(sc, 2);
441 CSR_WRITE_2(sc, MMU_CMD_REG_W, MMUCR_ALLOC | numPages);
442
443 /*
444 * Wait a short amount of time to see if the allocation request
445 * completes. Otherwise, I enable the interrupt and wait for
| 34
35/*
36 * This is a driver for SMC's 9000 series of Ethernet adapters.
37 *
38 * This FreeBSD driver is derived from the smc9194 Linux driver by
39 * Erik Stahlman and is Copyright (C) 1996 by Erik Stahlman.
40 * This driver also shamelessly borrows from the FreeBSD ep driver
41 * which is Copyright (C) 1994 Herb Peyerl <hpeyerl@novatel.ca>
42 * All rights reserved.
43 *
44 * It is set up for my SMC91C92 equipped Ampro LittleBoard embedded
45 * PC. It is adapted from Erik Stahlman's Linux driver which worked
46 * with his EFA Info*Express SVC VLB adaptor. According to SMC's databook,
47 * it will work for the entire SMC 9xxx series. (Ha Ha)
48 *
49 * "Features" of the SMC chip:
50 * 4608 byte packet memory. (for the 91C92. Others have more)
51 * EEPROM for configuration
52 * AUI/TP selection
53 *
54 * Authors:
55 * Erik Stahlman erik@vt.edu
56 * Herb Peyerl hpeyerl@novatel.ca
57 * Andres Vega Garcia avega@sophia.inria.fr
58 * Serge Babkin babkin@hq.icb.chel.su
59 * Gardner Buchanan gbuchanan@shl.com
60 *
61 * Sources:
62 * o SMC databook
63 * o "smc9194.c:v0.10(FIXED) 02/15/96 by Erik Stahlman (erik@vt.edu)"
64 * o "if_ep.c,v 1.19 1995/01/24 20:53:45 davidg Exp"
65 *
66 * Known Bugs:
67 * o Setting of the hardware address isn't supported.
68 * o Hardware padding isn't used.
69 */
70
71/*
72 * Modifications for Megahertz X-Jack Ethernet Card (XJ-10BT)
73 *
74 * Copyright (c) 1996 by Tatsumi Hosokawa <hosokawa@jp.FreeBSD.org>
75 * BSD-nomads, Tokyo, Japan.
76 */
77/*
78 * Multicast support by Kei TANAKA <kei@pal.xerox.com>
79 * Special thanks to itojun@itojun.org
80 */
81
82#include <sys/param.h>
83#include <sys/systm.h>
84#include <sys/errno.h>
85#include <sys/kernel.h>
86#include <sys/sockio.h>
87#include <sys/mbuf.h>
88#include <sys/socket.h>
89#include <sys/syslog.h>
90
91#include <sys/module.h>
92#include <sys/bus.h>
93
94#include <machine/bus.h>
95#include <machine/resource.h>
96#include <sys/rman.h>
97
98#include <net/ethernet.h>
99#include <net/if.h>
100#include <net/if_arp.h>
101#include <net/if_dl.h>
102#include <net/if_types.h>
103#include <net/if_mib.h>
104
105#ifdef INET
106#include <netinet/in.h>
107#include <netinet/in_systm.h>
108#include <netinet/in_var.h>
109#include <netinet/ip.h>
110#endif
111
112#include <net/bpf.h>
113#include <net/bpfdesc.h>
114
115#include <dev/sn/if_snreg.h>
116#include <dev/sn/if_snvar.h>
117
118/* Exported variables */
119devclass_t sn_devclass;
120
121static int snioctl(struct ifnet * ifp, u_long, caddr_t);
122
123static void snresume(struct ifnet *);
124
125static void snintr_locked(struct sn_softc *);
126static void sninit_locked(void *);
127static void snstart_locked(struct ifnet *);
128
129static void sninit(void *);
130static void snread(struct ifnet *);
131static void snstart(struct ifnet *);
132static void snstop(struct sn_softc *);
133static void snwatchdog(void *);
134
135static void sn_setmcast(struct sn_softc *);
136static int sn_getmcf(struct ifnet *ifp, u_char *mcf);
137
138/* I (GB) have been unlucky getting the hardware padding
139 * to work properly.
140 */
141#define SW_PAD
142
143static const char *chip_ids[15] = {
144 NULL, NULL, NULL,
145 /* 3 */ "SMC91C90/91C92",
146 /* 4 */ "SMC91C94/91C96",
147 /* 5 */ "SMC91C95",
148 NULL,
149 /* 7 */ "SMC91C100",
150 /* 8 */ "SMC91C100FD",
151 /* 9 */ "SMC91C110",
152 NULL, NULL,
153 NULL, NULL, NULL
154};
155
156int
157sn_attach(device_t dev)
158{
159 struct sn_softc *sc = device_get_softc(dev);
160 struct ifnet *ifp;
161 uint16_t i;
162 uint8_t *p;
163 int rev;
164 uint16_t address;
165 int err;
166 u_char eaddr[6];
167
168 ifp = sc->ifp = if_alloc(IFT_ETHER);
169 if (ifp == NULL) {
170 device_printf(dev, "can not if_alloc()\n");
171 return (ENOSPC);
172 }
173
174 SN_LOCK_INIT(sc);
175 callout_init_mtx(&sc->watchdog, &sc->sc_mtx, 0);
176 snstop(sc);
177 sc->pages_wanted = -1;
178
179 if (bootverbose || 1) {
180 SMC_SELECT_BANK(sc, 3);
181 rev = (CSR_READ_2(sc, REVISION_REG_W) >> 4) & 0xf;
182 if (chip_ids[rev])
183 device_printf(dev, " %s ", chip_ids[rev]);
184 else
185 device_printf(dev, " unsupported chip: rev %d ", rev);
186 SMC_SELECT_BANK(sc, 1);
187 i = CSR_READ_2(sc, CONFIG_REG_W);
188 printf("%s\n", i & CR_AUI_SELECT ? "AUI" : "UTP");
189 }
190
191 /*
192 * Read the station address from the chip. The MAC address is bank 1,
193 * regs 4 - 9
194 */
195 SMC_SELECT_BANK(sc, 1);
196 p = (uint8_t *) eaddr;
197 for (i = 0; i < 6; i += 2) {
198 address = CSR_READ_2(sc, IAR_ADDR0_REG_W + i);
199 p[i + 1] = address >> 8;
200 p[i] = address & 0xFF;
201 }
202 ifp->if_softc = sc;
203 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
204 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
205 ifp->if_start = snstart;
206 ifp->if_ioctl = snioctl;
207 ifp->if_init = sninit;
208 ifp->if_baudrate = 10000000;
209 IFQ_SET_MAXLEN(&ifp->if_snd, ifqmaxlen);
210 ifp->if_snd.ifq_maxlen = ifqmaxlen;
211 IFQ_SET_READY(&ifp->if_snd);
212
213 ether_ifattach(ifp, eaddr);
214
215 /*
216 * Activate the interrupt so we can get card interrupts. This
217 * needs to be done last so that we don't have/hold the lock
218 * during startup to avoid LORs in the network layer.
219 */
220 if ((err = bus_setup_intr(dev, sc->irq_res,
221 INTR_TYPE_NET | INTR_MPSAFE, NULL, sn_intr, sc,
222 &sc->intrhand)) != 0) {
223 sn_detach(dev);
224 return err;
225 }
226 return 0;
227}
228
229
230int
231sn_detach(device_t dev)
232{
233 struct sn_softc *sc = device_get_softc(dev);
234 struct ifnet *ifp = sc->ifp;
235
236 ether_ifdetach(ifp);
237 SN_LOCK(sc);
238 snstop(sc);
239 SN_UNLOCK(sc);
240 callout_drain(&sc->watchdog);
241 sn_deactivate(dev);
242 if_free(ifp);
243 SN_LOCK_DESTROY(sc);
244 return 0;
245}
246
247static void
248sninit(void *xsc)
249{
250 struct sn_softc *sc = xsc;
251 SN_LOCK(sc);
252 sninit_locked(sc);
253 SN_UNLOCK(sc);
254}
255
256/*
257 * Reset and initialize the chip
258 */
259static void
260sninit_locked(void *xsc)
261{
262 struct sn_softc *sc = xsc;
263 struct ifnet *ifp = sc->ifp;
264 int flags;
265 int mask;
266
267 SN_ASSERT_LOCKED(sc);
268
269 /*
270 * This resets the registers mostly to defaults, but doesn't affect
271 * EEPROM. After the reset cycle, we pause briefly for the chip to
272 * be happy.
273 */
274 SMC_SELECT_BANK(sc, 0);
275 CSR_WRITE_2(sc, RECV_CONTROL_REG_W, RCR_SOFTRESET);
276 SMC_DELAY(sc);
277 CSR_WRITE_2(sc, RECV_CONTROL_REG_W, 0x0000);
278 SMC_DELAY(sc);
279 SMC_DELAY(sc);
280
281 CSR_WRITE_2(sc, TXMIT_CONTROL_REG_W, 0x0000);
282
283 /*
284 * Set the control register to automatically release succesfully
285 * transmitted packets (making the best use out of our limited
286 * memory) and to enable the EPH interrupt on certain TX errors.
287 */
288 SMC_SELECT_BANK(sc, 1);
289 CSR_WRITE_2(sc, CONTROL_REG_W, (CTR_AUTO_RELEASE | CTR_TE_ENABLE |
290 CTR_CR_ENABLE | CTR_LE_ENABLE));
291
292 /* Set squelch level to 240mV (default 480mV) */
293 flags = CSR_READ_2(sc, CONFIG_REG_W);
294 flags |= CR_SET_SQLCH;
295 CSR_WRITE_2(sc, CONFIG_REG_W, flags);
296
297 /*
298 * Reset the MMU and wait for it to be un-busy.
299 */
300 SMC_SELECT_BANK(sc, 2);
301 CSR_WRITE_2(sc, MMU_CMD_REG_W, MMUCR_RESET);
302 while (CSR_READ_2(sc, MMU_CMD_REG_W) & MMUCR_BUSY) /* NOTHING */
303 ;
304
305 /*
306 * Disable all interrupts
307 */
308 CSR_WRITE_1(sc, INTR_MASK_REG_B, 0x00);
309
310 sn_setmcast(sc);
311
312 /*
313 * Set the transmitter control. We want it enabled.
314 */
315 flags = TCR_ENABLE;
316
317#ifndef SW_PAD
318 /*
319 * I (GB) have been unlucky getting this to work.
320 */
321 flags |= TCR_PAD_ENABLE;
322#endif /* SW_PAD */
323
324 CSR_WRITE_2(sc, TXMIT_CONTROL_REG_W, flags);
325
326
327 /*
328 * Now, enable interrupts
329 */
330 SMC_SELECT_BANK(sc, 2);
331
332 mask = IM_EPH_INT |
333 IM_RX_OVRN_INT |
334 IM_RCV_INT |
335 IM_TX_INT;
336
337 CSR_WRITE_1(sc, INTR_MASK_REG_B, mask);
338 sc->intr_mask = mask;
339 sc->pages_wanted = -1;
340
341
342 /*
343 * Mark the interface running but not active.
344 */
345 ifp->if_drv_flags |= IFF_DRV_RUNNING;
346 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
347 callout_reset(&sc->watchdog, hz, snwatchdog, sc);
348
349 /*
350 * Attempt to push out any waiting packets.
351 */
352 snstart_locked(ifp);
353}
354
355static void
356snstart(struct ifnet *ifp)
357{
358 struct sn_softc *sc = ifp->if_softc;
359 SN_LOCK(sc);
360 snstart_locked(ifp);
361 SN_UNLOCK(sc);
362}
363
364
365static void
366snstart_locked(struct ifnet *ifp)
367{
368 struct sn_softc *sc = ifp->if_softc;
369 u_int len;
370 struct mbuf *m;
371 struct mbuf *top;
372 int pad;
373 int mask;
374 uint16_t length;
375 uint16_t numPages;
376 uint8_t packet_no;
377 int time_out;
378 int junk = 0;
379
380 SN_ASSERT_LOCKED(sc);
381
382 if (ifp->if_drv_flags & IFF_DRV_OACTIVE)
383 return;
384 if (sc->pages_wanted != -1) {
385 if_printf(ifp, "snstart() while memory allocation pending\n");
386 return;
387 }
388startagain:
389
390 /*
391 * Sneak a peek at the next packet
392 */
393 m = ifp->if_snd.ifq_head;
394 if (m == 0)
395 return;
396 /*
397 * Compute the frame length and set pad to give an overall even
398 * number of bytes. Below we assume that the packet length is even.
399 */
400 for (len = 0, top = m; m; m = m->m_next)
401 len += m->m_len;
402
403 pad = (len & 1);
404
405 /*
406 * We drop packets that are too large. Perhaps we should truncate
407 * them instead?
408 */
409 if (len + pad > ETHER_MAX_LEN - ETHER_CRC_LEN) {
410 if_printf(ifp, "large packet discarded (A)\n");
411 ++ifp->if_oerrors;
412 IFQ_DRV_DEQUEUE(&ifp->if_snd, m);
413 m_freem(m);
414 goto readcheck;
415 }
416#ifdef SW_PAD
417
418 /*
419 * If HW padding is not turned on, then pad to ETHER_MIN_LEN.
420 */
421 if (len < ETHER_MIN_LEN - ETHER_CRC_LEN)
422 pad = ETHER_MIN_LEN - ETHER_CRC_LEN - len;
423
424#endif /* SW_PAD */
425
426 length = pad + len;
427
428 /*
429 * The MMU wants the number of pages to be the number of 256 byte
430 * 'pages', minus 1 (A packet can't ever have 0 pages. We also
431 * include space for the status word, byte count and control bytes in
432 * the allocation request.
433 */
434 numPages = (length + 6) >> 8;
435
436
437 /*
438 * Now, try to allocate the memory
439 */
440 SMC_SELECT_BANK(sc, 2);
441 CSR_WRITE_2(sc, MMU_CMD_REG_W, MMUCR_ALLOC | numPages);
442
443 /*
444 * Wait a short amount of time to see if the allocation request
445 * completes. Otherwise, I enable the interrupt and wait for
|
447 */
448
449 time_out = MEMORY_WAIT_TIME;
450 do {
451 if (CSR_READ_1(sc, INTR_STAT_REG_B) & IM_ALLOC_INT)
452 break;
453 } while (--time_out);
454
455 if (!time_out || junk > 10) {
456
457 /*
458 * No memory now. Oh well, wait until the chip finds memory
459 * later. Remember how many pages we were asking for and
460 * enable the allocation completion interrupt. Also set a
461 * watchdog in case we miss the interrupt. We mark the
462 * interface active since there is no point in attempting an
463 * snstart() until after the memory is available.
464 */
465 mask = CSR_READ_1(sc, INTR_MASK_REG_B) | IM_ALLOC_INT;
466 CSR_WRITE_1(sc, INTR_MASK_REG_B, mask);
467 sc->intr_mask = mask;
468
469 sc->timer = 1;
470 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
471 sc->pages_wanted = numPages;
472 return;
473 }
474 /*
475 * The memory allocation completed. Check the results.
476 */
477 packet_no = CSR_READ_1(sc, ALLOC_RESULT_REG_B);
478 if (packet_no & ARR_FAILED) {
479 if (junk++ > 10)
480 if_printf(ifp, "Memory allocation failed\n");
481 goto startagain;
482 }
483 /*
484 * We have a packet number, so tell the card to use it.
485 */
486 CSR_WRITE_1(sc, PACKET_NUM_REG_B, packet_no);
487
488 /*
489 * Point to the beginning of the packet
490 */
491 CSR_WRITE_2(sc, POINTER_REG_W, PTR_AUTOINC | 0x0000);
492
493 /*
494 * Send the packet length (+6 for status, length and control byte)
495 * and the status word (set to zeros)
496 */
497 CSR_WRITE_2(sc, DATA_REG_W, 0);
498 CSR_WRITE_1(sc, DATA_REG_B, (length + 6) & 0xFF);
499 CSR_WRITE_1(sc, DATA_REG_B, (length + 6) >> 8);
500
501 /*
502 * Get the packet from the kernel. This will include the Ethernet
503 * frame header, MAC Addresses etc.
504 */
505 IFQ_DRV_DEQUEUE(&ifp->if_snd, m);
506
507 /*
508 * Push out the data to the card.
509 */
510 for (top = m; m != 0; m = m->m_next) {
511
512 /*
513 * Push out words.
514 */
515 CSR_WRITE_MULTI_2(sc, DATA_REG_W, mtod(m, uint16_t *),
516 m->m_len / 2);
517
518 /*
519 * Push out remaining byte.
520 */
521 if (m->m_len & 1)
522 CSR_WRITE_1(sc, DATA_REG_B,
523 *(mtod(m, caddr_t) + m->m_len - 1));
524 }
525
526 /*
527 * Push out padding.
528 */
529 while (pad > 1) {
530 CSR_WRITE_2(sc, DATA_REG_W, 0);
531 pad -= 2;
532 }
533 if (pad)
534 CSR_WRITE_1(sc, DATA_REG_B, 0);
535
536 /*
537 * Push out control byte and unused packet byte The control byte is 0
538 * meaning the packet is even lengthed and no special CRC handling is
539 * desired.
540 */
541 CSR_WRITE_2(sc, DATA_REG_W, 0);
542
543 /*
544 * Enable the interrupts and let the chipset deal with it Also set a
545 * watchdog in case we miss the interrupt.
546 */
547 mask = CSR_READ_1(sc, INTR_MASK_REG_B) | (IM_TX_INT | IM_TX_EMPTY_INT);
548 CSR_WRITE_1(sc, INTR_MASK_REG_B, mask);
549 sc->intr_mask = mask;
550
551 CSR_WRITE_2(sc, MMU_CMD_REG_W, MMUCR_ENQUEUE);
552
553 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
554 sc->timer = 1;
555
556 BPF_MTAP(ifp, top);
557
558 ifp->if_opackets++;
559 m_freem(top);
560
561
562readcheck:
563
564 /*
565 * Is another packet coming in? We don't want to overflow the tiny
566 * RX FIFO. If nothing has arrived then attempt to queue another
567 * transmit packet.
568 */
569 if (CSR_READ_2(sc, FIFO_PORTS_REG_W) & FIFO_REMPTY)
570 goto startagain;
571 return;
572}
573
574
575
576/* Resume a packet transmit operation after a memory allocation
577 * has completed.
578 *
579 * This is basically a hacked up copy of snstart() which handles
580 * a completed memory allocation the same way snstart() does.
581 * It then passes control to snstart to handle any other queued
582 * packets.
583 */
584static void
585snresume(struct ifnet *ifp)
586{
587 struct sn_softc *sc = ifp->if_softc;
588 u_int len;
589 struct mbuf *m;
590 struct mbuf *top;
591 int pad;
592 int mask;
593 uint16_t length;
594 uint16_t numPages;
595 uint16_t pages_wanted;
596 uint8_t packet_no;
597
598 if (sc->pages_wanted < 0)
599 return;
600
601 pages_wanted = sc->pages_wanted;
602 sc->pages_wanted = -1;
603
604 /*
605 * Sneak a peek at the next packet
606 */
607 m = ifp->if_snd.ifq_head;
608 if (m == 0) {
609 if_printf(ifp, "snresume() with nothing to send\n");
610 return;
611 }
612 /*
613 * Compute the frame length and set pad to give an overall even
614 * number of bytes. Below we assume that the packet length is even.
615 */
616 for (len = 0, top = m; m; m = m->m_next)
617 len += m->m_len;
618
619 pad = (len & 1);
620
621 /*
622 * We drop packets that are too large. Perhaps we should truncate
623 * them instead?
624 */
625 if (len + pad > ETHER_MAX_LEN - ETHER_CRC_LEN) {
626 if_printf(ifp, "large packet discarded (B)\n");
627 ++ifp->if_oerrors;
628 IFQ_DRV_DEQUEUE(&ifp->if_snd, m);
629 m_freem(m);
630 return;
631 }
632#ifdef SW_PAD
633
634 /*
635 * If HW padding is not turned on, then pad to ETHER_MIN_LEN.
636 */
637 if (len < ETHER_MIN_LEN - ETHER_CRC_LEN)
638 pad = ETHER_MIN_LEN - ETHER_CRC_LEN - len;
639
640#endif /* SW_PAD */
641
642 length = pad + len;
643
644
645 /*
646 * The MMU wants the number of pages to be the number of 256 byte
647 * 'pages', minus 1 (A packet can't ever have 0 pages. We also
648 * include space for the status word, byte count and control bytes in
649 * the allocation request.
650 */
651 numPages = (length + 6) >> 8;
652
653
654 SMC_SELECT_BANK(sc, 2);
655
656 /*
657 * The memory allocation completed. Check the results. If it failed,
658 * we simply set a watchdog timer and hope for the best.
659 */
660 packet_no = CSR_READ_1(sc, ALLOC_RESULT_REG_B);
661 if (packet_no & ARR_FAILED) {
662 if_printf(ifp, "Memory allocation failed. Weird.\n");
663 sc->timer = 1;
664 goto try_start;
665 }
666 /*
667 * We have a packet number, so tell the card to use it.
668 */
669 CSR_WRITE_1(sc, PACKET_NUM_REG_B, packet_no);
670
671 /*
672 * Now, numPages should match the pages_wanted recorded when the
673 * memory allocation was initiated.
674 */
675 if (pages_wanted != numPages) {
676 if_printf(ifp, "memory allocation wrong size. Weird.\n");
677 /*
678 * If the allocation was the wrong size we simply release the
679 * memory once it is granted. Wait for the MMU to be un-busy.
680 */
681 while (CSR_READ_2(sc, MMU_CMD_REG_W) & MMUCR_BUSY) /* NOTHING */
682 ;
683 CSR_WRITE_2(sc, MMU_CMD_REG_W, MMUCR_FREEPKT);
684
685 return;
686 }
687 /*
688 * Point to the beginning of the packet
689 */
690 CSR_WRITE_2(sc, POINTER_REG_W, PTR_AUTOINC | 0x0000);
691
692 /*
693 * Send the packet length (+6 for status, length and control byte)
694 * and the status word (set to zeros)
695 */
696 CSR_WRITE_2(sc, DATA_REG_W, 0);
697 CSR_WRITE_1(sc, DATA_REG_B, (length + 6) & 0xFF);
698 CSR_WRITE_1(sc, DATA_REG_B, (length + 6) >> 8);
699
700 /*
701 * Get the packet from the kernel. This will include the Ethernet
702 * frame header, MAC Addresses etc.
703 */
704 IFQ_DRV_DEQUEUE(&ifp->if_snd, m);
705
706 /*
707 * Push out the data to the card.
708 */
709 for (top = m; m != 0; m = m->m_next) {
710
711 /*
712 * Push out words.
713 */
714 CSR_WRITE_MULTI_2(sc, DATA_REG_W, mtod(m, uint16_t *),
715 m->m_len / 2);
716 /*
717 * Push out remaining byte.
718 */
719 if (m->m_len & 1)
720 CSR_WRITE_1(sc, DATA_REG_B,
721 *(mtod(m, caddr_t) + m->m_len - 1));
722 }
723
724 /*
725 * Push out padding.
726 */
727 while (pad > 1) {
728 CSR_WRITE_2(sc, DATA_REG_W, 0);
729 pad -= 2;
730 }
731 if (pad)
732 CSR_WRITE_1(sc, DATA_REG_B, 0);
733
734 /*
735 * Push out control byte and unused packet byte The control byte is 0
736 * meaning the packet is even lengthed and no special CRC handling is
737 * desired.
738 */
739 CSR_WRITE_2(sc, DATA_REG_W, 0);
740
741 /*
742 * Enable the interrupts and let the chipset deal with it Also set a
743 * watchdog in case we miss the interrupt.
744 */
745 mask = CSR_READ_1(sc, INTR_MASK_REG_B) | (IM_TX_INT | IM_TX_EMPTY_INT);
746 CSR_WRITE_1(sc, INTR_MASK_REG_B, mask);
747 sc->intr_mask = mask;
748 CSR_WRITE_2(sc, MMU_CMD_REG_W, MMUCR_ENQUEUE);
749
750 BPF_MTAP(ifp, top);
751
752 ifp->if_opackets++;
753 m_freem(top);
754
755try_start:
756
757 /*
758 * Now pass control to snstart() to queue any additional packets
759 */
760 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
761 snstart_locked(ifp);
762
763 /*
764 * We've sent something, so we're active. Set a watchdog in case the
765 * TX_EMPTY interrupt is lost.
766 */
767 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
768 sc->timer = 1;
769
770 return;
771}
772
773void
774sn_intr(void *arg)
775{
776 struct sn_softc *sc = (struct sn_softc *) arg;
777
778 SN_LOCK(sc);
779 snintr_locked(sc);
780 SN_UNLOCK(sc);
781}
782
783static void
784snintr_locked(struct sn_softc *sc)
785{
786 int status, interrupts;
787 struct ifnet *ifp = sc->ifp;
788
789 /*
790 * Chip state registers
791 */
792 uint8_t mask;
793 uint8_t packet_no;
794 uint16_t tx_status;
795 uint16_t card_stats;
796
797 /*
798 * Clear the watchdog.
799 */
800 sc->timer = 0;
801
802 SMC_SELECT_BANK(sc, 2);
803
804 /*
805 * Obtain the current interrupt mask and clear the hardware mask
806 * while servicing interrupts.
807 */
808 mask = CSR_READ_1(sc, INTR_MASK_REG_B);
809 CSR_WRITE_1(sc, INTR_MASK_REG_B, 0x00);
810
811 /*
812 * Get the set of interrupts which occurred and eliminate any which
813 * are masked.
814 */
815 interrupts = CSR_READ_1(sc, INTR_STAT_REG_B);
816 status = interrupts & mask;
817
818 /*
819 * Now, process each of the interrupt types.
820 */
821
822 /*
823 * Receive Overrun.
824 */
825 if (status & IM_RX_OVRN_INT) {
826 /*
827 * Acknowlege Interrupt
828 */
829 SMC_SELECT_BANK(sc, 2);
830 CSR_WRITE_1(sc, INTR_ACK_REG_B, IM_RX_OVRN_INT);
831
832 ++ifp->if_ierrors;
833 }
834 /*
835 * Got a packet.
836 */
837 if (status & IM_RCV_INT) {
838 int packet_number;
839
840 SMC_SELECT_BANK(sc, 2);
841 packet_number = CSR_READ_2(sc, FIFO_PORTS_REG_W);
842
843 if (packet_number & FIFO_REMPTY) {
844 /*
845 * we got called , but nothing was on the FIFO
846 */
847 printf("sn: Receive interrupt with nothing on FIFO\n");
848 goto out;
849 }
850 snread(ifp);
851 }
852 /*
853 * An on-card memory allocation came through.
854 */
855 if (status & IM_ALLOC_INT) {
856 /*
857 * Disable this interrupt.
858 */
859 mask &= ~IM_ALLOC_INT;
860 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
861 snresume(ifp);
862 }
863 /*
864 * TX Completion. Handle a transmit error message. This will only be
865 * called when there is an error, because of the AUTO_RELEASE mode.
866 */
867 if (status & IM_TX_INT) {
868 /*
869 * Acknowlege Interrupt
870 */
871 SMC_SELECT_BANK(sc, 2);
872 CSR_WRITE_1(sc, INTR_ACK_REG_B, IM_TX_INT);
873
874 packet_no = CSR_READ_2(sc, FIFO_PORTS_REG_W);
875 packet_no &= FIFO_TX_MASK;
876
877 /*
878 * select this as the packet to read from
879 */
880 CSR_WRITE_1(sc, PACKET_NUM_REG_B, packet_no);
881
882 /*
883 * Position the pointer to the first word from this packet
884 */
885 CSR_WRITE_2(sc, POINTER_REG_W, PTR_AUTOINC | PTR_READ | 0x0000);
886
887 /*
888 * Fetch the TX status word. The value found here will be a
889 * copy of the EPH_STATUS_REG_W at the time the transmit
890 * failed.
891 */
892 tx_status = CSR_READ_2(sc, DATA_REG_W);
893
894 if (tx_status & EPHSR_TX_SUC) {
895 device_printf(sc->dev,
896 "Successful packet caused interrupt\n");
897 } else {
898 ++ifp->if_oerrors;
899 }
900
901 if (tx_status & EPHSR_LATCOL)
902 ++ifp->if_collisions;
903
904 /*
905 * Some of these errors will have disabled transmit.
906 * Re-enable transmit now.
907 */
908 SMC_SELECT_BANK(sc, 0);
909
910#ifdef SW_PAD
911 CSR_WRITE_2(sc, TXMIT_CONTROL_REG_W, TCR_ENABLE);
912#else
913 CSR_WRITE_2(sc, TXMIT_CONTROL_REG_W, TCR_ENABLE | TCR_PAD_ENABLE);
914#endif /* SW_PAD */
915
916 /*
917 * kill the failed packet. Wait for the MMU to be un-busy.
918 */
919 SMC_SELECT_BANK(sc, 2);
920 while (CSR_READ_2(sc, MMU_CMD_REG_W) & MMUCR_BUSY) /* NOTHING */
921 ;
922 CSR_WRITE_2(sc, MMU_CMD_REG_W, MMUCR_FREEPKT);
923
924 /*
925 * Attempt to queue more transmits.
926 */
927 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
928 snstart_locked(ifp);
929 }
930 /*
931 * Transmit underrun. We use this opportunity to update transmit
932 * statistics from the card.
933 */
934 if (status & IM_TX_EMPTY_INT) {
935
936 /*
937 * Acknowlege Interrupt
938 */
939 SMC_SELECT_BANK(sc, 2);
940 CSR_WRITE_1(sc, INTR_ACK_REG_B, IM_TX_EMPTY_INT);
941
942 /*
943 * Disable this interrupt.
944 */
945 mask &= ~IM_TX_EMPTY_INT;
946
947 SMC_SELECT_BANK(sc, 0);
948 card_stats = CSR_READ_2(sc, COUNTER_REG_W);
949
950 /*
951 * Single collisions
952 */
953 ifp->if_collisions += card_stats & ECR_COLN_MASK;
954
955 /*
956 * Multiple collisions
957 */
958 ifp->if_collisions += (card_stats & ECR_MCOLN_MASK) >> 4;
959
960 SMC_SELECT_BANK(sc, 2);
961
962 /*
963 * Attempt to enqueue some more stuff.
964 */
965 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
966 snstart_locked(ifp);
967 }
968 /*
969 * Some other error. Try to fix it by resetting the adapter.
970 */
971 if (status & IM_EPH_INT) {
972 snstop(sc);
973 sninit_locked(sc);
974 }
975
976out:
977 /*
978 * Handled all interrupt sources.
979 */
980
981 SMC_SELECT_BANK(sc, 2);
982
983 /*
984 * Reestablish interrupts from mask which have not been deselected
985 * during this interrupt. Note that the hardware mask, which was set
986 * to 0x00 at the start of this service routine, may have been
987 * updated by one or more of the interrupt handers and we must let
988 * those new interrupts stay enabled here.
989 */
990 mask |= CSR_READ_1(sc, INTR_MASK_REG_B);
991 CSR_WRITE_1(sc, INTR_MASK_REG_B, mask);
992 sc->intr_mask = mask;
993}
994
995static void
996snread(struct ifnet *ifp)
997{
998 struct sn_softc *sc = ifp->if_softc;
999 struct ether_header *eh;
1000 struct mbuf *m;
1001 short status;
1002 int packet_number;
1003 uint16_t packet_length;
1004 uint8_t *data;
1005
1006 SMC_SELECT_BANK(sc, 2);
1007#if 0
1008 packet_number = CSR_READ_2(sc, FIFO_PORTS_REG_W);
1009
1010 if (packet_number & FIFO_REMPTY) {
1011
1012 /*
1013 * we got called , but nothing was on the FIFO
1014 */
1015 printf("sn: Receive interrupt with nothing on FIFO\n");
1016 return;
1017 }
1018#endif
1019read_another:
1020
1021 /*
1022 * Start reading from the start of the packet. Since PTR_RCV is set,
1023 * packet number is found in FIFO_PORTS_REG_W, FIFO_RX_MASK.
1024 */
1025 CSR_WRITE_2(sc, POINTER_REG_W, PTR_READ | PTR_RCV | PTR_AUTOINC | 0x0000);
1026
1027 /*
1028 * First two words are status and packet_length
1029 */
1030 status = CSR_READ_2(sc, DATA_REG_W);
1031 packet_length = CSR_READ_2(sc, DATA_REG_W) & RLEN_MASK;
1032
1033 /*
1034 * The packet length contains 3 extra words: status, length, and a
1035 * extra word with the control byte.
1036 */
1037 packet_length -= 6;
1038
1039 /*
1040 * Account for receive errors and discard.
1041 */
1042 if (status & RS_ERRORS) {
1043 ++ifp->if_ierrors;
1044 goto out;
1045 }
1046 /*
1047 * A packet is received.
1048 */
1049
1050 /*
1051 * Adjust for odd-length packet.
1052 */
1053 if (status & RS_ODDFRAME)
1054 packet_length++;
1055
1056 /*
1057 * Allocate a header mbuf from the kernel.
1058 */
1059 MGETHDR(m, M_NOWAIT, MT_DATA);
1060 if (m == NULL)
1061 goto out;
1062
1063 m->m_pkthdr.rcvif = ifp;
1064 m->m_pkthdr.len = m->m_len = packet_length;
1065
1066 /*
1067 * Attach an mbuf cluster
1068 */
1069 MCLGET(m, M_NOWAIT);
1070
1071 /*
1072 * Insist on getting a cluster
1073 */
1074 if ((m->m_flags & M_EXT) == 0) {
1075 m_freem(m);
1076 ++ifp->if_ierrors;
1077 printf("sn: snread() kernel memory allocation problem\n");
1078 goto out;
1079 }
1080 eh = mtod(m, struct ether_header *);
1081
1082 /*
1083 * Get packet, including link layer address, from interface.
1084 */
1085 data = (uint8_t *) eh;
1086 CSR_READ_MULTI_2(sc, DATA_REG_W, (uint16_t *) data, packet_length >> 1);
1087 if (packet_length & 1) {
1088 data += packet_length & ~1;
1089 *data = CSR_READ_1(sc, DATA_REG_B);
1090 }
1091 ++ifp->if_ipackets;
1092
1093 /*
1094 * Remove link layer addresses and whatnot.
1095 */
1096 m->m_pkthdr.len = m->m_len = packet_length;
1097
1098 /*
1099 * Drop locks before calling if_input() since it may re-enter
1100 * snstart() in the netisr case. This would result in a
1101 * lock reversal. Better performance might be obtained by
1102 * chaining all packets received, dropping the lock, and then
1103 * calling if_input() on each one.
1104 */
1105 SN_UNLOCK(sc);
1106 (*ifp->if_input)(ifp, m);
1107 SN_LOCK(sc);
1108
1109out:
1110
1111 /*
1112 * Error or good, tell the card to get rid of this packet Wait for
1113 * the MMU to be un-busy.
1114 */
1115 SMC_SELECT_BANK(sc, 2);
1116 while (CSR_READ_2(sc, MMU_CMD_REG_W) & MMUCR_BUSY) /* NOTHING */
1117 ;
1118 CSR_WRITE_2(sc, MMU_CMD_REG_W, MMUCR_RELEASE);
1119
1120 /*
1121 * Check whether another packet is ready
1122 */
1123 packet_number = CSR_READ_2(sc, FIFO_PORTS_REG_W);
1124 if (packet_number & FIFO_REMPTY) {
1125 return;
1126 }
1127 goto read_another;
1128}
1129
1130
1131/*
1132 * Handle IOCTLS. This function is completely stolen from if_ep.c
1133 * As with its progenitor, it does not handle hardware address
1134 * changes.
1135 */
1136static int
1137snioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
1138{
1139 struct sn_softc *sc = ifp->if_softc;
1140 int error = 0;
1141
1142 switch (cmd) {
1143 case SIOCSIFFLAGS:
1144 SN_LOCK(sc);
1145 if ((ifp->if_flags & IFF_UP) == 0 &&
1146 ifp->if_drv_flags & IFF_DRV_RUNNING) {
1147 snstop(sc);
1148 } else {
1149 /* reinitialize card on any parameter change */
1150 sninit_locked(sc);
1151 }
1152 SN_UNLOCK(sc);
1153 break;
1154
1155 case SIOCADDMULTI:
1156 case SIOCDELMULTI:
1157 /* update multicast filter list. */
1158 SN_LOCK(sc);
1159 sn_setmcast(sc);
1160 error = 0;
1161 SN_UNLOCK(sc);
1162 break;
1163 default:
1164 error = ether_ioctl(ifp, cmd, data);
1165 break;
1166 }
1167 return (error);
1168}
1169
1170static void
1171snwatchdog(void *arg)
1172{
1173 struct sn_softc *sc;
1174
1175 sc = arg;
1176 SN_ASSERT_LOCKED(sc);
1177 callout_reset(&sc->watchdog, hz, snwatchdog, sc);
1178 if (sc->timer == 0 || --sc->timer > 0)
1179 return;
1180 snintr_locked(sc);
1181}
1182
1183
1184/* 1. zero the interrupt mask
1185 * 2. clear the enable receive flag
1186 * 3. clear the enable xmit flags
1187 */
1188static void
1189snstop(struct sn_softc *sc)
1190{
1191
1192 struct ifnet *ifp = sc->ifp;
1193
1194 /*
1195 * Clear interrupt mask; disable all interrupts.
1196 */
1197 SMC_SELECT_BANK(sc, 2);
1198 CSR_WRITE_1(sc, INTR_MASK_REG_B, 0x00);
1199
1200 /*
1201 * Disable transmitter and Receiver
1202 */
1203 SMC_SELECT_BANK(sc, 0);
1204 CSR_WRITE_2(sc, RECV_CONTROL_REG_W, 0x0000);
1205 CSR_WRITE_2(sc, TXMIT_CONTROL_REG_W, 0x0000);
1206
1207 /*
1208 * Cancel watchdog.
1209 */
1210 sc->timer = 0;
1211 callout_stop(&sc->watchdog);
1212 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
1213}
1214
1215
1216int
1217sn_activate(device_t dev)
1218{
1219 struct sn_softc *sc = device_get_softc(dev);
1220
1221 sc->port_rid = 0;
1222 sc->port_res = bus_alloc_resource(dev, SYS_RES_IOPORT, &sc->port_rid,
1223 0, ~0, SMC_IO_EXTENT, RF_ACTIVE);
1224 if (!sc->port_res) {
1225 if (bootverbose)
1226 device_printf(dev, "Cannot allocate ioport\n");
1227 return ENOMEM;
1228 }
1229
1230 sc->irq_rid = 0;
1231 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->irq_rid,
1232 RF_ACTIVE);
1233 if (!sc->irq_res) {
1234 if (bootverbose)
1235 device_printf(dev, "Cannot allocate irq\n");
1236 sn_deactivate(dev);
1237 return ENOMEM;
1238 }
1239 return (0);
1240}
1241
1242void
1243sn_deactivate(device_t dev)
1244{
1245 struct sn_softc *sc = device_get_softc(dev);
1246
1247 if (sc->intrhand)
1248 bus_teardown_intr(dev, sc->irq_res, sc->intrhand);
1249 sc->intrhand = 0;
1250 if (sc->port_res)
1251 bus_release_resource(dev, SYS_RES_IOPORT, sc->port_rid,
1252 sc->port_res);
1253 sc->port_res = 0;
1254 if (sc->modem_res)
1255 bus_release_resource(dev, SYS_RES_IOPORT, sc->modem_rid,
1256 sc->modem_res);
1257 sc->modem_res = 0;
1258 if (sc->irq_res)
1259 bus_release_resource(dev, SYS_RES_IRQ, sc->irq_rid,
1260 sc->irq_res);
1261 sc->irq_res = 0;
1262 return;
1263}
1264
1265/*
1266 * Function: sn_probe(device_t dev)
1267 *
1268 * Purpose:
1269 * Tests to see if a given ioaddr points to an SMC9xxx chip.
1270 * Tries to cause as little damage as possible if it's not a SMC chip.
1271 * Returns a 0 on success
1272 *
1273 * Algorithm:
1274 * (1) see if the high byte of BANK_SELECT is 0x33
1275 * (2) compare the ioaddr with the base register's address
1276 * (3) see if I recognize the chip ID in the appropriate register
1277 *
1278 *
1279 */
1280int
1281sn_probe(device_t dev)
1282{
1283 struct sn_softc *sc = device_get_softc(dev);
1284 uint16_t bank;
1285 uint16_t revision_register;
1286 uint16_t base_address_register;
1287 int err;
1288
1289 if ((err = sn_activate(dev)) != 0)
1290 return err;
1291
1292 /*
1293 * First, see if the high byte is 0x33
1294 */
1295 bank = CSR_READ_2(sc, BANK_SELECT_REG_W);
1296 if ((bank & BSR_DETECT_MASK) != BSR_DETECT_VALUE) {
1297#ifdef SN_DEBUG
1298 device_printf(dev, "test1 failed\n");
1299#endif
1300 goto error;
1301 }
1302 /*
1303 * The above MIGHT indicate a device, but I need to write to further
1304 * test this. Go to bank 0, then test that the register still
1305 * reports the high byte is 0x33.
1306 */
1307 CSR_WRITE_2(sc, BANK_SELECT_REG_W, 0x0000);
1308 bank = CSR_READ_2(sc, BANK_SELECT_REG_W);
1309 if ((bank & BSR_DETECT_MASK) != BSR_DETECT_VALUE) {
1310#ifdef SN_DEBUG
1311 device_printf(dev, "test2 failed\n");
1312#endif
1313 goto error;
1314 }
1315 /*
1316 * well, we've already written once, so hopefully another time won't
1317 * hurt. This time, I need to switch the bank register to bank 1, so
1318 * I can access the base address register. The contents of the
1319 * BASE_ADDR_REG_W register, after some jiggery pokery, is expected
1320 * to match the I/O port address where the adapter is being probed.
1321 */
1322 CSR_WRITE_2(sc, BANK_SELECT_REG_W, 0x0001);
1323 base_address_register = (CSR_READ_2(sc, BASE_ADDR_REG_W) >> 3) & 0x3e0;
1324
1325 if (rman_get_start(sc->port_res) != base_address_register) {
1326
1327 /*
1328 * Well, the base address register didn't match. Must not
1329 * have been a SMC chip after all.
1330 */
1331#ifdef SN_DEBUG
1332 device_printf(dev, "test3 failed ioaddr = 0x%x, "
1333 "base_address_register = 0x%x\n",
1334 rman_get_start(sc->port_res), base_address_register);
1335#endif
1336 goto error;
1337 }
1338
1339 /*
1340 * Check if the revision register is something that I recognize.
1341 * These might need to be added to later, as future revisions could
1342 * be added.
1343 */
1344 CSR_WRITE_2(sc, BANK_SELECT_REG_W, 0x3);
1345 revision_register = CSR_READ_2(sc, REVISION_REG_W);
1346 if (!chip_ids[(revision_register >> 4) & 0xF]) {
1347
1348 /*
1349 * I don't regonize this chip, so...
1350 */
1351#ifdef SN_DEBUG
1352 device_printf(dev, "test4 failed\n");
1353#endif
1354 goto error;
1355 }
1356
1357 /*
1358 * at this point I'll assume that the chip is an SMC9xxx. It might be
1359 * prudent to check a listing of MAC addresses against the hardware
1360 * address, or do some other tests.
1361 */
1362 sn_deactivate(dev);
1363 return 0;
1364 error:
1365 sn_deactivate(dev);
1366 return ENXIO;
1367}
1368
1369#define MCFSZ 8
1370
1371static void
1372sn_setmcast(struct sn_softc *sc)
1373{
1374 struct ifnet *ifp = sc->ifp;
1375 int flags;
1376 uint8_t mcf[MCFSZ];
1377
1378 SN_ASSERT_LOCKED(sc);
1379
1380 /*
1381 * Set the receiver filter. We want receive enabled and auto strip
1382 * of CRC from received packet. If we are promiscuous then set that
1383 * bit too.
1384 */
1385 flags = RCR_ENABLE | RCR_STRIP_CRC;
1386
1387 if (ifp->if_flags & IFF_PROMISC) {
1388 flags |= RCR_PROMISC | RCR_ALMUL;
1389 } else if (ifp->if_flags & IFF_ALLMULTI) {
1390 flags |= RCR_ALMUL;
1391 } else {
1392 if (sn_getmcf(ifp, mcf)) {
1393 /* set filter */
1394 SMC_SELECT_BANK(sc, 3);
1395 CSR_WRITE_2(sc, MULTICAST1_REG_W,
1396 ((uint16_t)mcf[1] << 8) | mcf[0]);
1397 CSR_WRITE_2(sc, MULTICAST2_REG_W,
1398 ((uint16_t)mcf[3] << 8) | mcf[2]);
1399 CSR_WRITE_2(sc, MULTICAST3_REG_W,
1400 ((uint16_t)mcf[5] << 8) | mcf[4]);
1401 CSR_WRITE_2(sc, MULTICAST4_REG_W,
1402 ((uint16_t)mcf[7] << 8) | mcf[6]);
1403 } else {
1404 flags |= RCR_ALMUL;
1405 }
1406 }
1407 SMC_SELECT_BANK(sc, 0);
1408 CSR_WRITE_2(sc, RECV_CONTROL_REG_W, flags);
1409}
1410
1411static int
1412sn_getmcf(struct ifnet *ifp, uint8_t *mcf)
1413{
1414 int i;
1415 uint32_t index, index2;
1416 uint8_t *af = mcf;
1417 struct ifmultiaddr *ifma;
1418
1419 bzero(mcf, MCFSZ);
1420
1421 if_maddr_rlock(ifp);
1422 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1423 if (ifma->ifma_addr->sa_family != AF_LINK) {
1424 if_maddr_runlock(ifp);
1425 return 0;
1426 }
1427 index = ether_crc32_le(LLADDR((struct sockaddr_dl *)
1428 ifma->ifma_addr), ETHER_ADDR_LEN) & 0x3f;
1429 index2 = 0;
1430 for (i = 0; i < 6; i++) {
1431 index2 <<= 1;
1432 index2 |= (index & 0x01);
1433 index >>= 1;
1434 }
1435 af[index2 >> 3] |= 1 << (index2 & 7);
1436 }
1437 if_maddr_runlock(ifp);
1438 return 1; /* use multicast filter */
1439}
| 447 */
448
449 time_out = MEMORY_WAIT_TIME;
450 do {
451 if (CSR_READ_1(sc, INTR_STAT_REG_B) & IM_ALLOC_INT)
452 break;
453 } while (--time_out);
454
455 if (!time_out || junk > 10) {
456
457 /*
458 * No memory now. Oh well, wait until the chip finds memory
459 * later. Remember how many pages we were asking for and
460 * enable the allocation completion interrupt. Also set a
461 * watchdog in case we miss the interrupt. We mark the
462 * interface active since there is no point in attempting an
463 * snstart() until after the memory is available.
464 */
465 mask = CSR_READ_1(sc, INTR_MASK_REG_B) | IM_ALLOC_INT;
466 CSR_WRITE_1(sc, INTR_MASK_REG_B, mask);
467 sc->intr_mask = mask;
468
469 sc->timer = 1;
470 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
471 sc->pages_wanted = numPages;
472 return;
473 }
474 /*
475 * The memory allocation completed. Check the results.
476 */
477 packet_no = CSR_READ_1(sc, ALLOC_RESULT_REG_B);
478 if (packet_no & ARR_FAILED) {
479 if (junk++ > 10)
480 if_printf(ifp, "Memory allocation failed\n");
481 goto startagain;
482 }
483 /*
484 * We have a packet number, so tell the card to use it.
485 */
486 CSR_WRITE_1(sc, PACKET_NUM_REG_B, packet_no);
487
488 /*
489 * Point to the beginning of the packet
490 */
491 CSR_WRITE_2(sc, POINTER_REG_W, PTR_AUTOINC | 0x0000);
492
493 /*
494 * Send the packet length (+6 for status, length and control byte)
495 * and the status word (set to zeros)
496 */
497 CSR_WRITE_2(sc, DATA_REG_W, 0);
498 CSR_WRITE_1(sc, DATA_REG_B, (length + 6) & 0xFF);
499 CSR_WRITE_1(sc, DATA_REG_B, (length + 6) >> 8);
500
501 /*
502 * Get the packet from the kernel. This will include the Ethernet
503 * frame header, MAC Addresses etc.
504 */
505 IFQ_DRV_DEQUEUE(&ifp->if_snd, m);
506
507 /*
508 * Push out the data to the card.
509 */
510 for (top = m; m != 0; m = m->m_next) {
511
512 /*
513 * Push out words.
514 */
515 CSR_WRITE_MULTI_2(sc, DATA_REG_W, mtod(m, uint16_t *),
516 m->m_len / 2);
517
518 /*
519 * Push out remaining byte.
520 */
521 if (m->m_len & 1)
522 CSR_WRITE_1(sc, DATA_REG_B,
523 *(mtod(m, caddr_t) + m->m_len - 1));
524 }
525
526 /*
527 * Push out padding.
528 */
529 while (pad > 1) {
530 CSR_WRITE_2(sc, DATA_REG_W, 0);
531 pad -= 2;
532 }
533 if (pad)
534 CSR_WRITE_1(sc, DATA_REG_B, 0);
535
536 /*
537 * Push out control byte and unused packet byte The control byte is 0
538 * meaning the packet is even lengthed and no special CRC handling is
539 * desired.
540 */
541 CSR_WRITE_2(sc, DATA_REG_W, 0);
542
543 /*
544 * Enable the interrupts and let the chipset deal with it Also set a
545 * watchdog in case we miss the interrupt.
546 */
547 mask = CSR_READ_1(sc, INTR_MASK_REG_B) | (IM_TX_INT | IM_TX_EMPTY_INT);
548 CSR_WRITE_1(sc, INTR_MASK_REG_B, mask);
549 sc->intr_mask = mask;
550
551 CSR_WRITE_2(sc, MMU_CMD_REG_W, MMUCR_ENQUEUE);
552
553 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
554 sc->timer = 1;
555
556 BPF_MTAP(ifp, top);
557
558 ifp->if_opackets++;
559 m_freem(top);
560
561
562readcheck:
563
564 /*
565 * Is another packet coming in? We don't want to overflow the tiny
566 * RX FIFO. If nothing has arrived then attempt to queue another
567 * transmit packet.
568 */
569 if (CSR_READ_2(sc, FIFO_PORTS_REG_W) & FIFO_REMPTY)
570 goto startagain;
571 return;
572}
573
574
575
576/* Resume a packet transmit operation after a memory allocation
577 * has completed.
578 *
579 * This is basically a hacked up copy of snstart() which handles
580 * a completed memory allocation the same way snstart() does.
581 * It then passes control to snstart to handle any other queued
582 * packets.
583 */
584static void
585snresume(struct ifnet *ifp)
586{
587 struct sn_softc *sc = ifp->if_softc;
588 u_int len;
589 struct mbuf *m;
590 struct mbuf *top;
591 int pad;
592 int mask;
593 uint16_t length;
594 uint16_t numPages;
595 uint16_t pages_wanted;
596 uint8_t packet_no;
597
598 if (sc->pages_wanted < 0)
599 return;
600
601 pages_wanted = sc->pages_wanted;
602 sc->pages_wanted = -1;
603
604 /*
605 * Sneak a peek at the next packet
606 */
607 m = ifp->if_snd.ifq_head;
608 if (m == 0) {
609 if_printf(ifp, "snresume() with nothing to send\n");
610 return;
611 }
612 /*
613 * Compute the frame length and set pad to give an overall even
614 * number of bytes. Below we assume that the packet length is even.
615 */
616 for (len = 0, top = m; m; m = m->m_next)
617 len += m->m_len;
618
619 pad = (len & 1);
620
621 /*
622 * We drop packets that are too large. Perhaps we should truncate
623 * them instead?
624 */
625 if (len + pad > ETHER_MAX_LEN - ETHER_CRC_LEN) {
626 if_printf(ifp, "large packet discarded (B)\n");
627 ++ifp->if_oerrors;
628 IFQ_DRV_DEQUEUE(&ifp->if_snd, m);
629 m_freem(m);
630 return;
631 }
632#ifdef SW_PAD
633
634 /*
635 * If HW padding is not turned on, then pad to ETHER_MIN_LEN.
636 */
637 if (len < ETHER_MIN_LEN - ETHER_CRC_LEN)
638 pad = ETHER_MIN_LEN - ETHER_CRC_LEN - len;
639
640#endif /* SW_PAD */
641
642 length = pad + len;
643
644
645 /*
646 * The MMU wants the number of pages to be the number of 256 byte
647 * 'pages', minus 1 (A packet can't ever have 0 pages. We also
648 * include space for the status word, byte count and control bytes in
649 * the allocation request.
650 */
651 numPages = (length + 6) >> 8;
652
653
654 SMC_SELECT_BANK(sc, 2);
655
656 /*
657 * The memory allocation completed. Check the results. If it failed,
658 * we simply set a watchdog timer and hope for the best.
659 */
660 packet_no = CSR_READ_1(sc, ALLOC_RESULT_REG_B);
661 if (packet_no & ARR_FAILED) {
662 if_printf(ifp, "Memory allocation failed. Weird.\n");
663 sc->timer = 1;
664 goto try_start;
665 }
666 /*
667 * We have a packet number, so tell the card to use it.
668 */
669 CSR_WRITE_1(sc, PACKET_NUM_REG_B, packet_no);
670
671 /*
672 * Now, numPages should match the pages_wanted recorded when the
673 * memory allocation was initiated.
674 */
675 if (pages_wanted != numPages) {
676 if_printf(ifp, "memory allocation wrong size. Weird.\n");
677 /*
678 * If the allocation was the wrong size we simply release the
679 * memory once it is granted. Wait for the MMU to be un-busy.
680 */
681 while (CSR_READ_2(sc, MMU_CMD_REG_W) & MMUCR_BUSY) /* NOTHING */
682 ;
683 CSR_WRITE_2(sc, MMU_CMD_REG_W, MMUCR_FREEPKT);
684
685 return;
686 }
687 /*
688 * Point to the beginning of the packet
689 */
690 CSR_WRITE_2(sc, POINTER_REG_W, PTR_AUTOINC | 0x0000);
691
692 /*
693 * Send the packet length (+6 for status, length and control byte)
694 * and the status word (set to zeros)
695 */
696 CSR_WRITE_2(sc, DATA_REG_W, 0);
697 CSR_WRITE_1(sc, DATA_REG_B, (length + 6) & 0xFF);
698 CSR_WRITE_1(sc, DATA_REG_B, (length + 6) >> 8);
699
700 /*
701 * Get the packet from the kernel. This will include the Ethernet
702 * frame header, MAC Addresses etc.
703 */
704 IFQ_DRV_DEQUEUE(&ifp->if_snd, m);
705
706 /*
707 * Push out the data to the card.
708 */
709 for (top = m; m != 0; m = m->m_next) {
710
711 /*
712 * Push out words.
713 */
714 CSR_WRITE_MULTI_2(sc, DATA_REG_W, mtod(m, uint16_t *),
715 m->m_len / 2);
716 /*
717 * Push out remaining byte.
718 */
719 if (m->m_len & 1)
720 CSR_WRITE_1(sc, DATA_REG_B,
721 *(mtod(m, caddr_t) + m->m_len - 1));
722 }
723
724 /*
725 * Push out padding.
726 */
727 while (pad > 1) {
728 CSR_WRITE_2(sc, DATA_REG_W, 0);
729 pad -= 2;
730 }
731 if (pad)
732 CSR_WRITE_1(sc, DATA_REG_B, 0);
733
734 /*
735 * Push out control byte and unused packet byte The control byte is 0
736 * meaning the packet is even lengthed and no special CRC handling is
737 * desired.
738 */
739 CSR_WRITE_2(sc, DATA_REG_W, 0);
740
741 /*
742 * Enable the interrupts and let the chipset deal with it Also set a
743 * watchdog in case we miss the interrupt.
744 */
745 mask = CSR_READ_1(sc, INTR_MASK_REG_B) | (IM_TX_INT | IM_TX_EMPTY_INT);
746 CSR_WRITE_1(sc, INTR_MASK_REG_B, mask);
747 sc->intr_mask = mask;
748 CSR_WRITE_2(sc, MMU_CMD_REG_W, MMUCR_ENQUEUE);
749
750 BPF_MTAP(ifp, top);
751
752 ifp->if_opackets++;
753 m_freem(top);
754
755try_start:
756
757 /*
758 * Now pass control to snstart() to queue any additional packets
759 */
760 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
761 snstart_locked(ifp);
762
763 /*
764 * We've sent something, so we're active. Set a watchdog in case the
765 * TX_EMPTY interrupt is lost.
766 */
767 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
768 sc->timer = 1;
769
770 return;
771}
772
773void
774sn_intr(void *arg)
775{
776 struct sn_softc *sc = (struct sn_softc *) arg;
777
778 SN_LOCK(sc);
779 snintr_locked(sc);
780 SN_UNLOCK(sc);
781}
782
783static void
784snintr_locked(struct sn_softc *sc)
785{
786 int status, interrupts;
787 struct ifnet *ifp = sc->ifp;
788
789 /*
790 * Chip state registers
791 */
792 uint8_t mask;
793 uint8_t packet_no;
794 uint16_t tx_status;
795 uint16_t card_stats;
796
797 /*
798 * Clear the watchdog.
799 */
800 sc->timer = 0;
801
802 SMC_SELECT_BANK(sc, 2);
803
804 /*
805 * Obtain the current interrupt mask and clear the hardware mask
806 * while servicing interrupts.
807 */
808 mask = CSR_READ_1(sc, INTR_MASK_REG_B);
809 CSR_WRITE_1(sc, INTR_MASK_REG_B, 0x00);
810
811 /*
812 * Get the set of interrupts which occurred and eliminate any which
813 * are masked.
814 */
815 interrupts = CSR_READ_1(sc, INTR_STAT_REG_B);
816 status = interrupts & mask;
817
818 /*
819 * Now, process each of the interrupt types.
820 */
821
822 /*
823 * Receive Overrun.
824 */
825 if (status & IM_RX_OVRN_INT) {
826 /*
827 * Acknowlege Interrupt
828 */
829 SMC_SELECT_BANK(sc, 2);
830 CSR_WRITE_1(sc, INTR_ACK_REG_B, IM_RX_OVRN_INT);
831
832 ++ifp->if_ierrors;
833 }
834 /*
835 * Got a packet.
836 */
837 if (status & IM_RCV_INT) {
838 int packet_number;
839
840 SMC_SELECT_BANK(sc, 2);
841 packet_number = CSR_READ_2(sc, FIFO_PORTS_REG_W);
842
843 if (packet_number & FIFO_REMPTY) {
844 /*
845 * we got called , but nothing was on the FIFO
846 */
847 printf("sn: Receive interrupt with nothing on FIFO\n");
848 goto out;
849 }
850 snread(ifp);
851 }
852 /*
853 * An on-card memory allocation came through.
854 */
855 if (status & IM_ALLOC_INT) {
856 /*
857 * Disable this interrupt.
858 */
859 mask &= ~IM_ALLOC_INT;
860 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
861 snresume(ifp);
862 }
863 /*
864 * TX Completion. Handle a transmit error message. This will only be
865 * called when there is an error, because of the AUTO_RELEASE mode.
866 */
867 if (status & IM_TX_INT) {
868 /*
869 * Acknowlege Interrupt
870 */
871 SMC_SELECT_BANK(sc, 2);
872 CSR_WRITE_1(sc, INTR_ACK_REG_B, IM_TX_INT);
873
874 packet_no = CSR_READ_2(sc, FIFO_PORTS_REG_W);
875 packet_no &= FIFO_TX_MASK;
876
877 /*
878 * select this as the packet to read from
879 */
880 CSR_WRITE_1(sc, PACKET_NUM_REG_B, packet_no);
881
882 /*
883 * Position the pointer to the first word from this packet
884 */
885 CSR_WRITE_2(sc, POINTER_REG_W, PTR_AUTOINC | PTR_READ | 0x0000);
886
887 /*
888 * Fetch the TX status word. The value found here will be a
889 * copy of the EPH_STATUS_REG_W at the time the transmit
890 * failed.
891 */
892 tx_status = CSR_READ_2(sc, DATA_REG_W);
893
894 if (tx_status & EPHSR_TX_SUC) {
895 device_printf(sc->dev,
896 "Successful packet caused interrupt\n");
897 } else {
898 ++ifp->if_oerrors;
899 }
900
901 if (tx_status & EPHSR_LATCOL)
902 ++ifp->if_collisions;
903
904 /*
905 * Some of these errors will have disabled transmit.
906 * Re-enable transmit now.
907 */
908 SMC_SELECT_BANK(sc, 0);
909
910#ifdef SW_PAD
911 CSR_WRITE_2(sc, TXMIT_CONTROL_REG_W, TCR_ENABLE);
912#else
913 CSR_WRITE_2(sc, TXMIT_CONTROL_REG_W, TCR_ENABLE | TCR_PAD_ENABLE);
914#endif /* SW_PAD */
915
916 /*
917 * kill the failed packet. Wait for the MMU to be un-busy.
918 */
919 SMC_SELECT_BANK(sc, 2);
920 while (CSR_READ_2(sc, MMU_CMD_REG_W) & MMUCR_BUSY) /* NOTHING */
921 ;
922 CSR_WRITE_2(sc, MMU_CMD_REG_W, MMUCR_FREEPKT);
923
924 /*
925 * Attempt to queue more transmits.
926 */
927 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
928 snstart_locked(ifp);
929 }
930 /*
931 * Transmit underrun. We use this opportunity to update transmit
932 * statistics from the card.
933 */
934 if (status & IM_TX_EMPTY_INT) {
935
936 /*
937 * Acknowlege Interrupt
938 */
939 SMC_SELECT_BANK(sc, 2);
940 CSR_WRITE_1(sc, INTR_ACK_REG_B, IM_TX_EMPTY_INT);
941
942 /*
943 * Disable this interrupt.
944 */
945 mask &= ~IM_TX_EMPTY_INT;
946
947 SMC_SELECT_BANK(sc, 0);
948 card_stats = CSR_READ_2(sc, COUNTER_REG_W);
949
950 /*
951 * Single collisions
952 */
953 ifp->if_collisions += card_stats & ECR_COLN_MASK;
954
955 /*
956 * Multiple collisions
957 */
958 ifp->if_collisions += (card_stats & ECR_MCOLN_MASK) >> 4;
959
960 SMC_SELECT_BANK(sc, 2);
961
962 /*
963 * Attempt to enqueue some more stuff.
964 */
965 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
966 snstart_locked(ifp);
967 }
968 /*
969 * Some other error. Try to fix it by resetting the adapter.
970 */
971 if (status & IM_EPH_INT) {
972 snstop(sc);
973 sninit_locked(sc);
974 }
975
976out:
977 /*
978 * Handled all interrupt sources.
979 */
980
981 SMC_SELECT_BANK(sc, 2);
982
983 /*
984 * Reestablish interrupts from mask which have not been deselected
985 * during this interrupt. Note that the hardware mask, which was set
986 * to 0x00 at the start of this service routine, may have been
987 * updated by one or more of the interrupt handers and we must let
988 * those new interrupts stay enabled here.
989 */
990 mask |= CSR_READ_1(sc, INTR_MASK_REG_B);
991 CSR_WRITE_1(sc, INTR_MASK_REG_B, mask);
992 sc->intr_mask = mask;
993}
994
995static void
996snread(struct ifnet *ifp)
997{
998 struct sn_softc *sc = ifp->if_softc;
999 struct ether_header *eh;
1000 struct mbuf *m;
1001 short status;
1002 int packet_number;
1003 uint16_t packet_length;
1004 uint8_t *data;
1005
1006 SMC_SELECT_BANK(sc, 2);
1007#if 0
1008 packet_number = CSR_READ_2(sc, FIFO_PORTS_REG_W);
1009
1010 if (packet_number & FIFO_REMPTY) {
1011
1012 /*
1013 * we got called , but nothing was on the FIFO
1014 */
1015 printf("sn: Receive interrupt with nothing on FIFO\n");
1016 return;
1017 }
1018#endif
1019read_another:
1020
1021 /*
1022 * Start reading from the start of the packet. Since PTR_RCV is set,
1023 * packet number is found in FIFO_PORTS_REG_W, FIFO_RX_MASK.
1024 */
1025 CSR_WRITE_2(sc, POINTER_REG_W, PTR_READ | PTR_RCV | PTR_AUTOINC | 0x0000);
1026
1027 /*
1028 * First two words are status and packet_length
1029 */
1030 status = CSR_READ_2(sc, DATA_REG_W);
1031 packet_length = CSR_READ_2(sc, DATA_REG_W) & RLEN_MASK;
1032
1033 /*
1034 * The packet length contains 3 extra words: status, length, and a
1035 * extra word with the control byte.
1036 */
1037 packet_length -= 6;
1038
1039 /*
1040 * Account for receive errors and discard.
1041 */
1042 if (status & RS_ERRORS) {
1043 ++ifp->if_ierrors;
1044 goto out;
1045 }
1046 /*
1047 * A packet is received.
1048 */
1049
1050 /*
1051 * Adjust for odd-length packet.
1052 */
1053 if (status & RS_ODDFRAME)
1054 packet_length++;
1055
1056 /*
1057 * Allocate a header mbuf from the kernel.
1058 */
1059 MGETHDR(m, M_NOWAIT, MT_DATA);
1060 if (m == NULL)
1061 goto out;
1062
1063 m->m_pkthdr.rcvif = ifp;
1064 m->m_pkthdr.len = m->m_len = packet_length;
1065
1066 /*
1067 * Attach an mbuf cluster
1068 */
1069 MCLGET(m, M_NOWAIT);
1070
1071 /*
1072 * Insist on getting a cluster
1073 */
1074 if ((m->m_flags & M_EXT) == 0) {
1075 m_freem(m);
1076 ++ifp->if_ierrors;
1077 printf("sn: snread() kernel memory allocation problem\n");
1078 goto out;
1079 }
1080 eh = mtod(m, struct ether_header *);
1081
1082 /*
1083 * Get packet, including link layer address, from interface.
1084 */
1085 data = (uint8_t *) eh;
1086 CSR_READ_MULTI_2(sc, DATA_REG_W, (uint16_t *) data, packet_length >> 1);
1087 if (packet_length & 1) {
1088 data += packet_length & ~1;
1089 *data = CSR_READ_1(sc, DATA_REG_B);
1090 }
1091 ++ifp->if_ipackets;
1092
1093 /*
1094 * Remove link layer addresses and whatnot.
1095 */
1096 m->m_pkthdr.len = m->m_len = packet_length;
1097
1098 /*
1099 * Drop locks before calling if_input() since it may re-enter
1100 * snstart() in the netisr case. This would result in a
1101 * lock reversal. Better performance might be obtained by
1102 * chaining all packets received, dropping the lock, and then
1103 * calling if_input() on each one.
1104 */
1105 SN_UNLOCK(sc);
1106 (*ifp->if_input)(ifp, m);
1107 SN_LOCK(sc);
1108
1109out:
1110
1111 /*
1112 * Error or good, tell the card to get rid of this packet Wait for
1113 * the MMU to be un-busy.
1114 */
1115 SMC_SELECT_BANK(sc, 2);
1116 while (CSR_READ_2(sc, MMU_CMD_REG_W) & MMUCR_BUSY) /* NOTHING */
1117 ;
1118 CSR_WRITE_2(sc, MMU_CMD_REG_W, MMUCR_RELEASE);
1119
1120 /*
1121 * Check whether another packet is ready
1122 */
1123 packet_number = CSR_READ_2(sc, FIFO_PORTS_REG_W);
1124 if (packet_number & FIFO_REMPTY) {
1125 return;
1126 }
1127 goto read_another;
1128}
1129
1130
1131/*
1132 * Handle IOCTLS. This function is completely stolen from if_ep.c
1133 * As with its progenitor, it does not handle hardware address
1134 * changes.
1135 */
1136static int
1137snioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
1138{
1139 struct sn_softc *sc = ifp->if_softc;
1140 int error = 0;
1141
1142 switch (cmd) {
1143 case SIOCSIFFLAGS:
1144 SN_LOCK(sc);
1145 if ((ifp->if_flags & IFF_UP) == 0 &&
1146 ifp->if_drv_flags & IFF_DRV_RUNNING) {
1147 snstop(sc);
1148 } else {
1149 /* reinitialize card on any parameter change */
1150 sninit_locked(sc);
1151 }
1152 SN_UNLOCK(sc);
1153 break;
1154
1155 case SIOCADDMULTI:
1156 case SIOCDELMULTI:
1157 /* update multicast filter list. */
1158 SN_LOCK(sc);
1159 sn_setmcast(sc);
1160 error = 0;
1161 SN_UNLOCK(sc);
1162 break;
1163 default:
1164 error = ether_ioctl(ifp, cmd, data);
1165 break;
1166 }
1167 return (error);
1168}
1169
1170static void
1171snwatchdog(void *arg)
1172{
1173 struct sn_softc *sc;
1174
1175 sc = arg;
1176 SN_ASSERT_LOCKED(sc);
1177 callout_reset(&sc->watchdog, hz, snwatchdog, sc);
1178 if (sc->timer == 0 || --sc->timer > 0)
1179 return;
1180 snintr_locked(sc);
1181}
1182
1183
1184/* 1. zero the interrupt mask
1185 * 2. clear the enable receive flag
1186 * 3. clear the enable xmit flags
1187 */
1188static void
1189snstop(struct sn_softc *sc)
1190{
1191
1192 struct ifnet *ifp = sc->ifp;
1193
1194 /*
1195 * Clear interrupt mask; disable all interrupts.
1196 */
1197 SMC_SELECT_BANK(sc, 2);
1198 CSR_WRITE_1(sc, INTR_MASK_REG_B, 0x00);
1199
1200 /*
1201 * Disable transmitter and Receiver
1202 */
1203 SMC_SELECT_BANK(sc, 0);
1204 CSR_WRITE_2(sc, RECV_CONTROL_REG_W, 0x0000);
1205 CSR_WRITE_2(sc, TXMIT_CONTROL_REG_W, 0x0000);
1206
1207 /*
1208 * Cancel watchdog.
1209 */
1210 sc->timer = 0;
1211 callout_stop(&sc->watchdog);
1212 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
1213}
1214
1215
1216int
1217sn_activate(device_t dev)
1218{
1219 struct sn_softc *sc = device_get_softc(dev);
1220
1221 sc->port_rid = 0;
1222 sc->port_res = bus_alloc_resource(dev, SYS_RES_IOPORT, &sc->port_rid,
1223 0, ~0, SMC_IO_EXTENT, RF_ACTIVE);
1224 if (!sc->port_res) {
1225 if (bootverbose)
1226 device_printf(dev, "Cannot allocate ioport\n");
1227 return ENOMEM;
1228 }
1229
1230 sc->irq_rid = 0;
1231 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->irq_rid,
1232 RF_ACTIVE);
1233 if (!sc->irq_res) {
1234 if (bootverbose)
1235 device_printf(dev, "Cannot allocate irq\n");
1236 sn_deactivate(dev);
1237 return ENOMEM;
1238 }
1239 return (0);
1240}
1241
1242void
1243sn_deactivate(device_t dev)
1244{
1245 struct sn_softc *sc = device_get_softc(dev);
1246
1247 if (sc->intrhand)
1248 bus_teardown_intr(dev, sc->irq_res, sc->intrhand);
1249 sc->intrhand = 0;
1250 if (sc->port_res)
1251 bus_release_resource(dev, SYS_RES_IOPORT, sc->port_rid,
1252 sc->port_res);
1253 sc->port_res = 0;
1254 if (sc->modem_res)
1255 bus_release_resource(dev, SYS_RES_IOPORT, sc->modem_rid,
1256 sc->modem_res);
1257 sc->modem_res = 0;
1258 if (sc->irq_res)
1259 bus_release_resource(dev, SYS_RES_IRQ, sc->irq_rid,
1260 sc->irq_res);
1261 sc->irq_res = 0;
1262 return;
1263}
1264
1265/*
1266 * Function: sn_probe(device_t dev)
1267 *
1268 * Purpose:
1269 * Tests to see if a given ioaddr points to an SMC9xxx chip.
1270 * Tries to cause as little damage as possible if it's not a SMC chip.
1271 * Returns a 0 on success
1272 *
1273 * Algorithm:
1274 * (1) see if the high byte of BANK_SELECT is 0x33
1275 * (2) compare the ioaddr with the base register's address
1276 * (3) see if I recognize the chip ID in the appropriate register
1277 *
1278 *
1279 */
1280int
1281sn_probe(device_t dev)
1282{
1283 struct sn_softc *sc = device_get_softc(dev);
1284 uint16_t bank;
1285 uint16_t revision_register;
1286 uint16_t base_address_register;
1287 int err;
1288
1289 if ((err = sn_activate(dev)) != 0)
1290 return err;
1291
1292 /*
1293 * First, see if the high byte is 0x33
1294 */
1295 bank = CSR_READ_2(sc, BANK_SELECT_REG_W);
1296 if ((bank & BSR_DETECT_MASK) != BSR_DETECT_VALUE) {
1297#ifdef SN_DEBUG
1298 device_printf(dev, "test1 failed\n");
1299#endif
1300 goto error;
1301 }
1302 /*
1303 * The above MIGHT indicate a device, but I need to write to further
1304 * test this. Go to bank 0, then test that the register still
1305 * reports the high byte is 0x33.
1306 */
1307 CSR_WRITE_2(sc, BANK_SELECT_REG_W, 0x0000);
1308 bank = CSR_READ_2(sc, BANK_SELECT_REG_W);
1309 if ((bank & BSR_DETECT_MASK) != BSR_DETECT_VALUE) {
1310#ifdef SN_DEBUG
1311 device_printf(dev, "test2 failed\n");
1312#endif
1313 goto error;
1314 }
1315 /*
1316 * well, we've already written once, so hopefully another time won't
1317 * hurt. This time, I need to switch the bank register to bank 1, so
1318 * I can access the base address register. The contents of the
1319 * BASE_ADDR_REG_W register, after some jiggery pokery, is expected
1320 * to match the I/O port address where the adapter is being probed.
1321 */
1322 CSR_WRITE_2(sc, BANK_SELECT_REG_W, 0x0001);
1323 base_address_register = (CSR_READ_2(sc, BASE_ADDR_REG_W) >> 3) & 0x3e0;
1324
1325 if (rman_get_start(sc->port_res) != base_address_register) {
1326
1327 /*
1328 * Well, the base address register didn't match. Must not
1329 * have been a SMC chip after all.
1330 */
1331#ifdef SN_DEBUG
1332 device_printf(dev, "test3 failed ioaddr = 0x%x, "
1333 "base_address_register = 0x%x\n",
1334 rman_get_start(sc->port_res), base_address_register);
1335#endif
1336 goto error;
1337 }
1338
1339 /*
1340 * Check if the revision register is something that I recognize.
1341 * These might need to be added to later, as future revisions could
1342 * be added.
1343 */
1344 CSR_WRITE_2(sc, BANK_SELECT_REG_W, 0x3);
1345 revision_register = CSR_READ_2(sc, REVISION_REG_W);
1346 if (!chip_ids[(revision_register >> 4) & 0xF]) {
1347
1348 /*
1349 * I don't regonize this chip, so...
1350 */
1351#ifdef SN_DEBUG
1352 device_printf(dev, "test4 failed\n");
1353#endif
1354 goto error;
1355 }
1356
1357 /*
1358 * at this point I'll assume that the chip is an SMC9xxx. It might be
1359 * prudent to check a listing of MAC addresses against the hardware
1360 * address, or do some other tests.
1361 */
1362 sn_deactivate(dev);
1363 return 0;
1364 error:
1365 sn_deactivate(dev);
1366 return ENXIO;
1367}
1368
1369#define MCFSZ 8
1370
1371static void
1372sn_setmcast(struct sn_softc *sc)
1373{
1374 struct ifnet *ifp = sc->ifp;
1375 int flags;
1376 uint8_t mcf[MCFSZ];
1377
1378 SN_ASSERT_LOCKED(sc);
1379
1380 /*
1381 * Set the receiver filter. We want receive enabled and auto strip
1382 * of CRC from received packet. If we are promiscuous then set that
1383 * bit too.
1384 */
1385 flags = RCR_ENABLE | RCR_STRIP_CRC;
1386
1387 if (ifp->if_flags & IFF_PROMISC) {
1388 flags |= RCR_PROMISC | RCR_ALMUL;
1389 } else if (ifp->if_flags & IFF_ALLMULTI) {
1390 flags |= RCR_ALMUL;
1391 } else {
1392 if (sn_getmcf(ifp, mcf)) {
1393 /* set filter */
1394 SMC_SELECT_BANK(sc, 3);
1395 CSR_WRITE_2(sc, MULTICAST1_REG_W,
1396 ((uint16_t)mcf[1] << 8) | mcf[0]);
1397 CSR_WRITE_2(sc, MULTICAST2_REG_W,
1398 ((uint16_t)mcf[3] << 8) | mcf[2]);
1399 CSR_WRITE_2(sc, MULTICAST3_REG_W,
1400 ((uint16_t)mcf[5] << 8) | mcf[4]);
1401 CSR_WRITE_2(sc, MULTICAST4_REG_W,
1402 ((uint16_t)mcf[7] << 8) | mcf[6]);
1403 } else {
1404 flags |= RCR_ALMUL;
1405 }
1406 }
1407 SMC_SELECT_BANK(sc, 0);
1408 CSR_WRITE_2(sc, RECV_CONTROL_REG_W, flags);
1409}
1410
1411static int
1412sn_getmcf(struct ifnet *ifp, uint8_t *mcf)
1413{
1414 int i;
1415 uint32_t index, index2;
1416 uint8_t *af = mcf;
1417 struct ifmultiaddr *ifma;
1418
1419 bzero(mcf, MCFSZ);
1420
1421 if_maddr_rlock(ifp);
1422 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1423 if (ifma->ifma_addr->sa_family != AF_LINK) {
1424 if_maddr_runlock(ifp);
1425 return 0;
1426 }
1427 index = ether_crc32_le(LLADDR((struct sockaddr_dl *)
1428 ifma->ifma_addr), ETHER_ADDR_LEN) & 0x3f;
1429 index2 = 0;
1430 for (i = 0; i < 6; i++) {
1431 index2 <<= 1;
1432 index2 |= (index & 0x01);
1433 index >>= 1;
1434 }
1435 af[index2 >> 3] |= 1 << (index2 & 7);
1436 }
1437 if_maddr_runlock(ifp);
1438 return 1; /* use multicast filter */
1439}
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