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sio.c (89470) sio.c (89986)
1/*-
2 * Copyright (c) 1991 The Regents of the University of California.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

--- 16 unchanged lines hidden (view full) ---

25 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 * SUCH DAMAGE.
32 *
1/*-
2 * Copyright (c) 1991 The Regents of the University of California.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

--- 16 unchanged lines hidden (view full) ---

25 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 * SUCH DAMAGE.
32 *
33 * $FreeBSD: head/sys/dev/sio/sio.c 89470 2002-01-17 20:05:47Z bmah $
33 * $FreeBSD: head/sys/dev/sio/sio.c 89986 2002-01-30 17:22:04Z jhay $
34 * from: @(#)com.c 7.5 (Berkeley) 5/16/91
35 * from: i386/isa sio.c,v 1.234
36 */
37
38#include "opt_comconsole.h"
39#include "opt_compat.h"
40#include "opt_ddb.h"
41#include "opt_sio.h"

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250 struct timeval dcd_timestamp;
251 struct pps_state pps;
252
253 u_long bytes_in; /* statistics */
254 u_long bytes_out;
255 u_int delta_error_counts[CE_NTYPES];
256 u_long error_counts[CE_NTYPES];
257
34 * from: @(#)com.c 7.5 (Berkeley) 5/16/91
35 * from: i386/isa sio.c,v 1.234
36 */
37
38#include "opt_comconsole.h"
39#include "opt_compat.h"
40#include "opt_ddb.h"
41#include "opt_sio.h"

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250 struct timeval dcd_timestamp;
251 struct pps_state pps;
252
253 u_long bytes_in; /* statistics */
254 u_long bytes_out;
255 u_int delta_error_counts[CE_NTYPES];
256 u_long error_counts[CE_NTYPES];
257
258 u_long rclk;
259
258 struct resource *irqres;
259 struct resource *ioportres;
260 void *cookie;
261 dev_t devs[6];
262
263 /*
264 * Data area for output buffers. Someday we should build the output
265 * buffer queue without copying data.
266 */
267 u_char obuf1[256];
268 u_char obuf2[256];
269};
270
271#ifdef COM_ESP
272static int espattach __P((struct com_s *com, Port_t esp_port));
273#endif
274
275static timeout_t siobusycheck;
260 struct resource *irqres;
261 struct resource *ioportres;
262 void *cookie;
263 dev_t devs[6];
264
265 /*
266 * Data area for output buffers. Someday we should build the output
267 * buffer queue without copying data.
268 */
269 u_char obuf1[256];
270 u_char obuf2[256];
271};
272
273#ifdef COM_ESP
274static int espattach __P((struct com_s *com, Port_t esp_port));
275#endif
276
277static timeout_t siobusycheck;
278static u_int siodivisor __P((u_long rclk, speed_t speed));
276static timeout_t siodtrwakeup;
277static void comhardclose __P((struct com_s *com));
278static void sioinput __P((struct com_s *com));
279static void siointr1 __P((struct com_s *com));
280static void siointr __P((void *arg));
281static int commctl __P((struct com_s *com, int bits, int how));
282static int comparam __P((struct tty *tp, struct termios *t));
283static void siopoll __P((void *));

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319 /* dump */ nodump,
320 /* psize */ nopsize,
321 /* flags */ D_TTY | D_KQFILTER,
322 /* kqfilter */ ttykqfilter,
323};
324
325int comconsole = -1;
326static volatile speed_t comdefaultrate = CONSPEED;
279static timeout_t siodtrwakeup;
280static void comhardclose __P((struct com_s *com));
281static void sioinput __P((struct com_s *com));
282static void siointr1 __P((struct com_s *com));
283static void siointr __P((void *arg));
284static int commctl __P((struct com_s *com, int bits, int how));
285static int comparam __P((struct tty *tp, struct termios *t));
286static void siopoll __P((void *));

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322 /* dump */ nodump,
323 /* psize */ nopsize,
324 /* flags */ D_TTY | D_KQFILTER,
325 /* kqfilter */ ttykqfilter,
326};
327
328int comconsole = -1;
329static volatile speed_t comdefaultrate = CONSPEED;
330static u_long comdefaultrclk = DEFAULT_RCLK;
331SYSCTL_ULONG(_machdep, OID_AUTO, conrclk, CTLFLAG_RW, &comdefaultrclk, 0, "");
327#ifdef __alpha__
328static volatile speed_t gdbdefaultrate = CONSPEED;
329#endif
330static u_int com_events; /* input chars + weighted output completions */
331static Port_t siocniobase;
332#ifndef __alpha__
333static int siocnunit;
334#endif
335static Port_t siogdbiobase;
336static int siogdbunit = -1;
337static void *sio_slow_ih;
338static void *sio_fast_ih;
339static int sio_timeout;
340static int sio_timeouts_until_log;
341static struct callout_handle sio_timeout_handle
342 = CALLOUT_HANDLE_INITIALIZER(&sio_timeout_handle);
343static int sio_numunits;
344
332#ifdef __alpha__
333static volatile speed_t gdbdefaultrate = CONSPEED;
334#endif
335static u_int com_events; /* input chars + weighted output completions */
336static Port_t siocniobase;
337#ifndef __alpha__
338static int siocnunit;
339#endif
340static Port_t siogdbiobase;
341static int siogdbunit = -1;
342static void *sio_slow_ih;
343static void *sio_fast_ih;
344static int sio_timeout;
345static int sio_timeouts_until_log;
346static struct callout_handle sio_timeout_handle
347 = CALLOUT_HANDLE_INITIALIZER(&sio_timeout_handle);
348static int sio_numunits;
349
345static struct speedtab comspeedtab[] = {
346 { 0, 0 },
347 { 50, COMBRD(50) },
348 { 75, COMBRD(75) },
349 { 110, COMBRD(110) },
350 { 134, COMBRD(134) },
351 { 150, COMBRD(150) },
352 { 200, COMBRD(200) },
353 { 300, COMBRD(300) },
354 { 600, COMBRD(600) },
355 { 1200, COMBRD(1200) },
356 { 1800, COMBRD(1800) },
357 { 2400, COMBRD(2400) },
358 { 4800, COMBRD(4800) },
359 { 9600, COMBRD(9600) },
360 { 19200, COMBRD(19200) },
361 { 28800, COMBRD(28800) },
362 { 38400, COMBRD(38400) },
363 { 57600, COMBRD(57600) },
364 { 115200, COMBRD(115200) },
365 { -1, -1 }
366};
367
368#ifdef COM_ESP
369/* XXX configure this properly. */
370/* XXX quite broken for new-bus. */
371static Port_t likely_com_ports[] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8, };
372static Port_t likely_esp_ports[] = { 0x140, 0x180, 0x280, 0 };
373#endif
374
375/*

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478 free(com->ibuf, M_DEVBUF);
479 device_set_softc(dev, NULL);
480 free(com, M_DEVBUF);
481 }
482 return (0);
483}
484
485int
350#ifdef COM_ESP
351/* XXX configure this properly. */
352/* XXX quite broken for new-bus. */
353static Port_t likely_com_ports[] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8, };
354static Port_t likely_esp_ports[] = { 0x140, 0x180, 0x280, 0 };
355#endif
356
357/*

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460 free(com->ibuf, M_DEVBUF);
461 device_set_softc(dev, NULL);
462 free(com, M_DEVBUF);
463 }
464 return (0);
465}
466
467int
486sioprobe(dev, xrid, noprobe)
468sioprobe(dev, xrid, rclk, noprobe)
487 device_t dev;
488 int xrid;
469 device_t dev;
470 int xrid;
471 u_long rclk;
489 int noprobe;
490{
491#if 0
492 static bool_t already_init;
493 device_t xdev;
494#endif
495 struct com_s *com;
472 int noprobe;
473{
474#if 0
475 static bool_t already_init;
476 device_t xdev;
477#endif
478 struct com_s *com;
479 u_int divisor;
496 bool_t failures[10];
497 int fn;
498 device_t idev;
499 Port_t iobase;
500 intrmask_t irqmap[4];
501 intrmask_t irqs;
502 u_char mcr_image;
503 int result;

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513 return (ENXIO);
514
515 com = malloc(sizeof(*com), M_DEVBUF, M_NOWAIT | M_ZERO);
516 if (com == NULL)
517 return (ENOMEM);
518 device_set_softc(dev, com);
519 com->bst = rman_get_bustag(port);
520 com->bsh = rman_get_bushandle(port);
480 bool_t failures[10];
481 int fn;
482 device_t idev;
483 Port_t iobase;
484 intrmask_t irqmap[4];
485 intrmask_t irqs;
486 u_char mcr_image;
487 int result;

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497 return (ENXIO);
498
499 com = malloc(sizeof(*com), M_DEVBUF, M_NOWAIT | M_ZERO);
500 if (com == NULL)
501 return (ENOMEM);
502 device_set_softc(dev, com);
503 com->bst = rman_get_bustag(port);
504 com->bsh = rman_get_bushandle(port);
505 if (rclk == 0)
506 rclk = DEFAULT_RCLK;
507 com->rclk = rclk;
521
522 while (sio_inited != 2)
523 if (atomic_cmpset_int(&sio_inited, 0, 1)) {
524 mtx_init(&sio_lock, sio_driver_name, (comconsole != -1) ?
525 MTX_SPIN | MTX_QUIET : MTX_SPIN);
526 atomic_store_rel_int(&sio_inited, 2);
527 }
528

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625 * master reset.
626 * XXX what about the UART bug avoided by waiting in comparam()?
627 * We don't want to to wait long enough to drain at 2 bps.
628 */
629 if (iobase == siocniobase)
630 DELAY((16 + 1) * 1000000 / (comdefaultrate / 10));
631 else {
632 sio_setreg(com, com_cfcr, CFCR_DLAB | CFCR_8BITS);
508
509 while (sio_inited != 2)
510 if (atomic_cmpset_int(&sio_inited, 0, 1)) {
511 mtx_init(&sio_lock, sio_driver_name, (comconsole != -1) ?
512 MTX_SPIN | MTX_QUIET : MTX_SPIN);
513 atomic_store_rel_int(&sio_inited, 2);
514 }
515

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612 * master reset.
613 * XXX what about the UART bug avoided by waiting in comparam()?
614 * We don't want to to wait long enough to drain at 2 bps.
615 */
616 if (iobase == siocniobase)
617 DELAY((16 + 1) * 1000000 / (comdefaultrate / 10));
618 else {
619 sio_setreg(com, com_cfcr, CFCR_DLAB | CFCR_8BITS);
633 sio_setreg(com, com_dlbl, COMBRD(SIO_TEST_SPEED) & 0xff);
634 sio_setreg(com, com_dlbh, (u_int) COMBRD(SIO_TEST_SPEED) >> 8);
620 divisor = siodivisor(rclk, SIO_TEST_SPEED);
621 sio_setreg(com, com_dlbl, divisor & 0xff);
622 sio_setreg(com, com_dlbh, divisor >> 8);
635 sio_setreg(com, com_cfcr, CFCR_8BITS);
636 DELAY((16 + 1) * 1000000 / (SIO_TEST_SPEED / 10));
637 }
638
639 /*
640 * Enable the interrupt gate and disable device interupts. This
641 * should leave the device driving the interrupt line low and
642 * guarantee an edge trigger if an interrupt can be generated.

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861 */
862 com->esp = TRUE;
863 com->esp_port = esp_port;
864 return (1);
865}
866#endif /* COM_ESP */
867
868int
623 sio_setreg(com, com_cfcr, CFCR_8BITS);
624 DELAY((16 + 1) * 1000000 / (SIO_TEST_SPEED / 10));
625 }
626
627 /*
628 * Enable the interrupt gate and disable device interupts. This
629 * should leave the device driving the interrupt line low and
630 * guarantee an edge trigger if an interrupt can be generated.

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849 */
850 com->esp = TRUE;
851 com->esp_port = esp_port;
852 return (1);
853}
854#endif /* COM_ESP */
855
856int
869sioattach(dev, xrid)
857sioattach(dev, xrid, rclk)
870 device_t dev;
871 int xrid;
858 device_t dev;
859 int xrid;
860 u_long rclk;
872{
873 struct com_s *com;
874#ifdef COM_ESP
875 Port_t *espp;
876#endif
877 Port_t iobase;
878 int unit;
879 u_int flags;

--- 42 unchanged lines hidden (view full) ---

922 com->data_port = iobase + com_data;
923 com->int_id_port = iobase + com_iir;
924 com->modem_ctl_port = iobase + com_mcr;
925 com->mcr_image = inb(com->modem_ctl_port);
926 com->line_status_port = iobase + com_lsr;
927 com->modem_status_port = iobase + com_msr;
928 com->intr_ctl_port = iobase + com_ier;
929
861{
862 struct com_s *com;
863#ifdef COM_ESP
864 Port_t *espp;
865#endif
866 Port_t iobase;
867 int unit;
868 u_int flags;

--- 42 unchanged lines hidden (view full) ---

911 com->data_port = iobase + com_data;
912 com->int_id_port = iobase + com_iir;
913 com->modem_ctl_port = iobase + com_mcr;
914 com->mcr_image = inb(com->modem_ctl_port);
915 com->line_status_port = iobase + com_lsr;
916 com->modem_status_port = iobase + com_msr;
917 com->intr_ctl_port = iobase + com_ier;
918
919 if (rclk == 0)
920 rclk = DEFAULT_RCLK;
921 com->rclk = rclk;
922
930 /*
931 * We don't use all the flags from <sys/ttydefaults.h> since they
932 * are only relevant for logins. It's important to have echo off
933 * initially so that the line doesn't start blathering before the
934 * echo flag can be turned off.
935 */
936 com->it_in.c_iflag = 0;
937 com->it_in.c_oflag = 0;

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1490 com->tp->t_state &= ~TS_BUSY;
1491 ttwwakeup(com->tp);
1492 com->extra_state &= ~CSE_BUSYCHECK;
1493 } else
1494 timeout(siobusycheck, com, hz / 100);
1495 splx(s);
1496}
1497
923 /*
924 * We don't use all the flags from <sys/ttydefaults.h> since they
925 * are only relevant for logins. It's important to have echo off
926 * initially so that the line doesn't start blathering before the
927 * echo flag can be turned off.
928 */
929 com->it_in.c_iflag = 0;
930 com->it_in.c_oflag = 0;

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1483 com->tp->t_state &= ~TS_BUSY;
1484 ttwwakeup(com->tp);
1485 com->extra_state &= ~CSE_BUSYCHECK;
1486 } else
1487 timeout(siobusycheck, com, hz / 100);
1488 splx(s);
1489}
1490
1491static u_int
1492siodivisor(rclk, speed)
1493 u_long rclk;
1494 speed_t speed;
1495{
1496 long actual_speed;
1497 u_int divisor;
1498 int error;
1499
1500 if (speed == 0 || speed > (ULONG_MAX - 1) / 8)
1501 return (0);
1502 divisor = (rclk / (8UL * speed) + 1) / 2;
1503 if (divisor == 0 || divisor >= 65536)
1504 return (0);
1505 actual_speed = rclk / (16UL * divisor);
1506
1507 /* 10 times error in percent: */
1508 error = ((actual_speed - (long)speed) * 2000 / (long)speed + 1) / 2;
1509
1510 /* 3.0% maximum error tolerance: */
1511 if (error < -30 || error > 30)
1512 return (0);
1513
1514 return (divisor);
1515}
1516
1498static void
1499siodtrwakeup(chan)
1500 void *chan;
1501{
1502 struct com_s *com;
1503
1504 com = (struct com_s *)chan;
1505 com->state &= ~CS_DTR_OFF;

--- 598 unchanged lines hidden (view full) ---

2104static int
2105comparam(tp, t)
2106 struct tty *tp;
2107 struct termios *t;
2108{
2109 u_int cfcr;
2110 int cflag;
2111 struct com_s *com;
1517static void
1518siodtrwakeup(chan)
1519 void *chan;
1520{
1521 struct com_s *com;
1522
1523 com = (struct com_s *)chan;
1524 com->state &= ~CS_DTR_OFF;

--- 598 unchanged lines hidden (view full) ---

2123static int
2124comparam(tp, t)
2125 struct tty *tp;
2126 struct termios *t;
2127{
2128 u_int cfcr;
2129 int cflag;
2130 struct com_s *com;
2112 int divisor;
2131 u_int divisor;
2113 u_char dlbh;
2114 u_char dlbl;
2115 int s;
2116 int unit;
2117
2132 u_char dlbh;
2133 u_char dlbl;
2134 int s;
2135 int unit;
2136
2137 unit = DEV_TO_UNIT(tp->t_dev);
2138 com = com_addr(unit);
2139 if (com == NULL)
2140 return (ENODEV);
2141
2118 /* do historical conversions */
2119 if (t->c_ispeed == 0)
2120 t->c_ispeed = t->c_ospeed;
2121
2122 /* check requested parameters */
2142 /* do historical conversions */
2143 if (t->c_ispeed == 0)
2144 t->c_ispeed = t->c_ospeed;
2145
2146 /* check requested parameters */
2123 divisor = ttspeedtab(t->c_ospeed, comspeedtab);
2124 if (divisor < 0 || (divisor > 0 && t->c_ispeed != t->c_ospeed))
2125 return (EINVAL);
2147 if (t->c_ospeed == 0)
2148 divisor = 0;
2149 else {
2150 if (t->c_ispeed != t->c_ospeed)
2151 return (EINVAL);
2152 divisor = siodivisor(com->rclk, t->c_ispeed);
2153 if (divisor == 0)
2154 return (EINVAL);
2155 }
2126
2127 /* parameters are OK, convert them to the com struct and the device */
2156
2157 /* parameters are OK, convert them to the com struct and the device */
2128 unit = DEV_TO_UNIT(tp->t_dev);
2129 com = com_addr(unit);
2130 if (com == NULL)
2131 return (ENODEV);
2132 s = spltty();
2133 if (divisor == 0)
2134 (void)commctl(com, TIOCM_DTR, DMBIC); /* hang up line */
2135 else
2136 (void)commctl(com, TIOCM_DTR, DMBIS);
2137 cflag = t->c_cflag;
2138 switch (cflag & CSIZE) {
2139 case CS5:

--- 58 unchanged lines hidden (view full) ---

2198 * Only set the divisor registers if they would change,
2199 * since on some 16550 incompatibles (UMC8669F), setting
2200 * them while input is arriving them loses sync until
2201 * data stops arriving.
2202 */
2203 dlbl = divisor & 0xFF;
2204 if (sio_getreg(com, com_dlbl) != dlbl)
2205 sio_setreg(com, com_dlbl, dlbl);
2158 s = spltty();
2159 if (divisor == 0)
2160 (void)commctl(com, TIOCM_DTR, DMBIC); /* hang up line */
2161 else
2162 (void)commctl(com, TIOCM_DTR, DMBIS);
2163 cflag = t->c_cflag;
2164 switch (cflag & CSIZE) {
2165 case CS5:

--- 58 unchanged lines hidden (view full) ---

2224 * Only set the divisor registers if they would change,
2225 * since on some 16550 incompatibles (UMC8669F), setting
2226 * them while input is arriving them loses sync until
2227 * data stops arriving.
2228 */
2229 dlbl = divisor & 0xFF;
2230 if (sio_getreg(com, com_dlbl) != dlbl)
2231 sio_setreg(com, com_dlbl, dlbl);
2206 dlbh = (u_int) divisor >> 8;
2232 dlbh = divisor >> 8;
2207 if (sio_getreg(com, com_dlbh) != dlbh)
2208 sio_setreg(com, com_dlbh, dlbh);
2209 }
2210
2211 sio_setreg(com, com_cfcr, com->cfcr_image = cfcr);
2212
2213 if (!(tp->t_state & TS_TTSTOP))
2214 com->state |= CS_TTGO;

--- 449 unchanged lines hidden (view full) ---

2664 u_char dlbl;
2665 u_char dlbh;
2666 u_char ier;
2667 u_char cfcr;
2668 u_char mcr;
2669};
2670
2671#ifndef __alpha__
2233 if (sio_getreg(com, com_dlbh) != dlbh)
2234 sio_setreg(com, com_dlbh, dlbh);
2235 }
2236
2237 sio_setreg(com, com_cfcr, com->cfcr_image = cfcr);
2238
2239 if (!(tp->t_state & TS_TTSTOP))
2240 com->state |= CS_TTGO;

--- 449 unchanged lines hidden (view full) ---

2690 u_char dlbl;
2691 u_char dlbh;
2692 u_char ier;
2693 u_char cfcr;
2694 u_char mcr;
2695};
2696
2697#ifndef __alpha__
2672static speed_t siocngetspeed __P((Port_t, struct speedtab *));
2698static speed_t siocngetspeed __P((Port_t, u_long rclk));
2673#endif
2674static void siocnclose __P((struct siocnstate *sp, Port_t iobase));
2675static void siocnopen __P((struct siocnstate *sp, Port_t iobase, int speed));
2676static void siocntxwait __P((Port_t iobase));
2677
2678#ifdef __alpha__
2679int siocnattach __P((int port, int speed));
2680int siogdbattach __P((int port, int speed));

--- 42 unchanged lines hidden (view full) ---

2723 * it's currently running at. We're assuming the serial port has
2724 * been initialized and is basicly idle. This routine is only intended
2725 * to be run at system startup.
2726 *
2727 * If the value read from the serial port doesn't make sense, return 0.
2728 */
2729
2730static speed_t
2699#endif
2700static void siocnclose __P((struct siocnstate *sp, Port_t iobase));
2701static void siocnopen __P((struct siocnstate *sp, Port_t iobase, int speed));
2702static void siocntxwait __P((Port_t iobase));
2703
2704#ifdef __alpha__
2705int siocnattach __P((int port, int speed));
2706int siogdbattach __P((int port, int speed));

--- 42 unchanged lines hidden (view full) ---

2749 * it's currently running at. We're assuming the serial port has
2750 * been initialized and is basicly idle. This routine is only intended
2751 * to be run at system startup.
2752 *
2753 * If the value read from the serial port doesn't make sense, return 0.
2754 */
2755
2756static speed_t
2731siocngetspeed(iobase, table)
2732 Port_t iobase;
2733 struct speedtab *table;
2757siocngetspeed(iobase, rclk)
2758 Port_t iobase;
2759 u_long rclk;
2734{
2760{
2735 int code;
2761 u_int divisor;
2736 u_char dlbh;
2737 u_char dlbl;
2738 u_char cfcr;
2739
2740 cfcr = inb(iobase + com_cfcr);
2741 outb(iobase + com_cfcr, CFCR_DLAB | cfcr);
2742
2743 dlbl = inb(iobase + com_dlbl);
2744 dlbh = inb(iobase + com_dlbh);
2745
2746 outb(iobase + com_cfcr, cfcr);
2747
2762 u_char dlbh;
2763 u_char dlbl;
2764 u_char cfcr;
2765
2766 cfcr = inb(iobase + com_cfcr);
2767 outb(iobase + com_cfcr, CFCR_DLAB | cfcr);
2768
2769 dlbl = inb(iobase + com_dlbl);
2770 dlbh = inb(iobase + com_dlbh);
2771
2772 outb(iobase + com_cfcr, cfcr);
2773
2748 code = dlbh << 8 | dlbl;
2774 divisor = dlbh << 8 | dlbl;
2749
2775
2750 for (; table->sp_speed != -1; table++)
2751 if (table->sp_code == code)
2752 return (table->sp_speed);
2753
2754 return (0); /* didn't match anything sane */
2776 /* XXX there should be more sanity checking. */
2777 if (divisor == 0)
2778 return (CONSPEED);
2779 return (rclk / (16UL * divisor));
2755}
2756
2757#endif
2758
2759static void
2760siocnopen(sp, iobase, speed)
2761 struct siocnstate *sp;
2762 Port_t iobase;
2763 int speed;
2764{
2780}
2781
2782#endif
2783
2784static void
2785siocnopen(sp, iobase, speed)
2786 struct siocnstate *sp;
2787 Port_t iobase;
2788 int speed;
2789{
2765 int divisor;
2790 u_int divisor;
2766 u_char dlbh;
2767 u_char dlbl;
2768
2769 /*
2770 * Save all the device control registers except the fifo register
2771 * and set our default ones (cs8 -parenb speed=comdefaultrate).
2772 * We can't save the fifo register since it is read-only.
2773 */

--- 5 unchanged lines hidden (view full) ---

2779 sp->dlbl = inb(iobase + com_dlbl);
2780 sp->dlbh = inb(iobase + com_dlbh);
2781 /*
2782 * Only set the divisor registers if they would change, since on
2783 * some 16550 incompatibles (Startech), setting them clears the
2784 * data input register. This also reduces the effects of the
2785 * UMC8669F bug.
2786 */
2791 u_char dlbh;
2792 u_char dlbl;
2793
2794 /*
2795 * Save all the device control registers except the fifo register
2796 * and set our default ones (cs8 -parenb speed=comdefaultrate).
2797 * We can't save the fifo register since it is read-only.
2798 */

--- 5 unchanged lines hidden (view full) ---

2804 sp->dlbl = inb(iobase + com_dlbl);
2805 sp->dlbh = inb(iobase + com_dlbh);
2806 /*
2807 * Only set the divisor registers if they would change, since on
2808 * some 16550 incompatibles (Startech), setting them clears the
2809 * data input register. This also reduces the effects of the
2810 * UMC8669F bug.
2811 */
2787 divisor = ttspeedtab(speed, comspeedtab);
2812 divisor = siodivisor(comdefaultrclk, speed);
2788 dlbl = divisor & 0xFF;
2789 if (sp->dlbl != dlbl)
2790 outb(iobase + com_dlbl, dlbl);
2813 dlbl = divisor & 0xFF;
2814 if (sp->dlbl != dlbl)
2815 outb(iobase + com_dlbl, dlbl);
2791 dlbh = (u_int) divisor >> 8;
2816 dlbh = divisor >> 8;
2792 if (sp->dlbh != dlbh)
2793 outb(iobase + com_dlbh, dlbh);
2794 outb(iobase + com_cfcr, CFCR_8BITS);
2795 sp->mcr = inb(iobase + com_mcr);
2796 /*
2797 * We don't want interrupts, but must be careful not to "disable"
2798 * them by clearing the MCR_IENABLE bit, since that might cause
2799 * an interrupt by floating the IRQ line.

--- 26 unchanged lines hidden (view full) ---

2826#ifndef __alpha__
2827
2828static void
2829siocnprobe(cp)
2830 struct consdev *cp;
2831{
2832 speed_t boot_speed;
2833 u_char cfcr;
2817 if (sp->dlbh != dlbh)
2818 outb(iobase + com_dlbh, dlbh);
2819 outb(iobase + com_cfcr, CFCR_8BITS);
2820 sp->mcr = inb(iobase + com_mcr);
2821 /*
2822 * We don't want interrupts, but must be careful not to "disable"
2823 * them by clearing the MCR_IENABLE bit, since that might cause
2824 * an interrupt by floating the IRQ line.

--- 26 unchanged lines hidden (view full) ---

2851#ifndef __alpha__
2852
2853static void
2854siocnprobe(cp)
2855 struct consdev *cp;
2856{
2857 speed_t boot_speed;
2858 u_char cfcr;
2859 u_int divisor;
2834 int s, unit;
2835 struct siocnstate sp;
2836
2837 /*
2838 * Find our first enabled console, if any. If it is a high-level
2839 * console device, then initialize it and return successfully.
2840 * If it is a low-level console device, then initialize it and
2841 * return unsuccessfully. It must be initialized in both cases

--- 21 unchanged lines hidden (view full) ---

2863 int port;
2864 Port_t iobase;
2865
2866 if (resource_int_value("sio", unit, "port", &port))
2867 continue;
2868 iobase = port;
2869 s = spltty();
2870 if (boothowto & RB_SERIAL) {
2860 int s, unit;
2861 struct siocnstate sp;
2862
2863 /*
2864 * Find our first enabled console, if any. If it is a high-level
2865 * console device, then initialize it and return successfully.
2866 * If it is a low-level console device, then initialize it and
2867 * return unsuccessfully. It must be initialized in both cases

--- 21 unchanged lines hidden (view full) ---

2889 int port;
2890 Port_t iobase;
2891
2892 if (resource_int_value("sio", unit, "port", &port))
2893 continue;
2894 iobase = port;
2895 s = spltty();
2896 if (boothowto & RB_SERIAL) {
2871 boot_speed = siocngetspeed(iobase, comspeedtab);
2897 boot_speed =
2898 siocngetspeed(iobase, comdefaultrclk);
2872 if (boot_speed)
2873 comdefaultrate = boot_speed;
2874 }
2875
2876 /*
2877 * Initialize the divisor latch. We can't rely on
2878 * siocnopen() to do this the first time, since it
2879 * avoids writing to the latch if the latch appears
2880 * to have the correct value. Also, if we didn't
2881 * just read the speed from the hardware, then we
2882 * need to set the speed in hardware so that
2883 * switching it later is null.
2884 */
2885 cfcr = inb(iobase + com_cfcr);
2886 outb(iobase + com_cfcr, CFCR_DLAB | cfcr);
2899 if (boot_speed)
2900 comdefaultrate = boot_speed;
2901 }
2902
2903 /*
2904 * Initialize the divisor latch. We can't rely on
2905 * siocnopen() to do this the first time, since it
2906 * avoids writing to the latch if the latch appears
2907 * to have the correct value. Also, if we didn't
2908 * just read the speed from the hardware, then we
2909 * need to set the speed in hardware so that
2910 * switching it later is null.
2911 */
2912 cfcr = inb(iobase + com_cfcr);
2913 outb(iobase + com_cfcr, CFCR_DLAB | cfcr);
2887 outb(iobase + com_dlbl,
2888 COMBRD(comdefaultrate) & 0xff);
2889 outb(iobase + com_dlbh,
2890 (u_int) COMBRD(comdefaultrate) >> 8);
2914 divisor = siodivisor(comdefaultrclk, comdefaultrate);
2915 outb(iobase + com_dlbl, divisor & 0xff);
2916 outb(iobase + com_dlbh, divisor >> 8);
2891 outb(iobase + com_cfcr, cfcr);
2892
2893 siocnopen(&sp, iobase, comdefaultrate);
2894
2895 splx(s);
2896 if (COM_CONSOLE(flags) && !COM_LLCONSOLE(flags)) {
2897 cp->cn_dev = makedev(CDEV_MAJOR, unit);
2898 cp->cn_pri = COM_FORCECONSOLE(flags)

--- 58 unchanged lines hidden (view full) ---

2957
2958int
2959siocnattach(port, speed)
2960 int port;
2961 int speed;
2962{
2963 int s;
2964 u_char cfcr;
2917 outb(iobase + com_cfcr, cfcr);
2918
2919 siocnopen(&sp, iobase, comdefaultrate);
2920
2921 splx(s);
2922 if (COM_CONSOLE(flags) && !COM_LLCONSOLE(flags)) {
2923 cp->cn_dev = makedev(CDEV_MAJOR, unit);
2924 cp->cn_pri = COM_FORCECONSOLE(flags)

--- 58 unchanged lines hidden (view full) ---

2983
2984int
2985siocnattach(port, speed)
2986 int port;
2987 int speed;
2988{
2989 int s;
2990 u_char cfcr;
2991 u_int divisor;
2965 struct siocnstate sp;
2966
2967 siocniobase = port;
2968 comdefaultrate = speed;
2969 sio_consdev.cn_pri = CN_NORMAL;
2970 sio_consdev.cn_dev = makedev(CDEV_MAJOR, 0);
2971
2972 s = spltty();

--- 4 unchanged lines hidden (view full) ---

2977 * avoids writing to the latch if the latch appears
2978 * to have the correct value. Also, if we didn't
2979 * just read the speed from the hardware, then we
2980 * need to set the speed in hardware so that
2981 * switching it later is null.
2982 */
2983 cfcr = inb(siocniobase + com_cfcr);
2984 outb(siocniobase + com_cfcr, CFCR_DLAB | cfcr);
2992 struct siocnstate sp;
2993
2994 siocniobase = port;
2995 comdefaultrate = speed;
2996 sio_consdev.cn_pri = CN_NORMAL;
2997 sio_consdev.cn_dev = makedev(CDEV_MAJOR, 0);
2998
2999 s = spltty();

--- 4 unchanged lines hidden (view full) ---

3004 * avoids writing to the latch if the latch appears
3005 * to have the correct value. Also, if we didn't
3006 * just read the speed from the hardware, then we
3007 * need to set the speed in hardware so that
3008 * switching it later is null.
3009 */
3010 cfcr = inb(siocniobase + com_cfcr);
3011 outb(siocniobase + com_cfcr, CFCR_DLAB | cfcr);
2985 outb(siocniobase + com_dlbl,
2986 COMBRD(comdefaultrate) & 0xff);
2987 outb(siocniobase + com_dlbh,
2988 (u_int) COMBRD(comdefaultrate) >> 8);
3012 divisor = siodivisor(comdefaultrclk, comdefaultrate);
3013 outb(siocniobase + com_dlbl, divisor & 0xff);
3014 outb(siocniobase + com_dlbh, divisor >> 8);
2989 outb(siocniobase + com_cfcr, cfcr);
2990
2991 siocnopen(&sp, siocniobase, comdefaultrate);
2992 splx(s);
2993
2994 cnadd(&sio_consdev);
2995 return (0);
2996}
2997
2998int
2999siogdbattach(port, speed)
3000 int port;
3001 int speed;
3002{
3003 int s;
3004 u_char cfcr;
3015 outb(siocniobase + com_cfcr, cfcr);
3016
3017 siocnopen(&sp, siocniobase, comdefaultrate);
3018 splx(s);
3019
3020 cnadd(&sio_consdev);
3021 return (0);
3022}
3023
3024int
3025siogdbattach(port, speed)
3026 int port;
3027 int speed;
3028{
3029 int s;
3030 u_char cfcr;
3031 u_int divisor;
3005 struct siocnstate sp;
3006 int unit = 1; /* XXX !!! */
3007
3008 siogdbiobase = port;
3009 gdbdefaultrate = speed;
3010
3011 printf("sio%d: gdb debugging port\n", unit);
3012 siogdbunit = unit;

--- 11 unchanged lines hidden (view full) ---

3024 * avoids writing to the latch if the latch appears
3025 * to have the correct value. Also, if we didn't
3026 * just read the speed from the hardware, then we
3027 * need to set the speed in hardware so that
3028 * switching it later is null.
3029 */
3030 cfcr = inb(siogdbiobase + com_cfcr);
3031 outb(siogdbiobase + com_cfcr, CFCR_DLAB | cfcr);
3032 struct siocnstate sp;
3033 int unit = 1; /* XXX !!! */
3034
3035 siogdbiobase = port;
3036 gdbdefaultrate = speed;
3037
3038 printf("sio%d: gdb debugging port\n", unit);
3039 siogdbunit = unit;

--- 11 unchanged lines hidden (view full) ---

3051 * avoids writing to the latch if the latch appears
3052 * to have the correct value. Also, if we didn't
3053 * just read the speed from the hardware, then we
3054 * need to set the speed in hardware so that
3055 * switching it later is null.
3056 */
3057 cfcr = inb(siogdbiobase + com_cfcr);
3058 outb(siogdbiobase + com_cfcr, CFCR_DLAB | cfcr);
3032 outb(siogdbiobase + com_dlbl,
3033 COMBRD(gdbdefaultrate) & 0xff);
3034 outb(siogdbiobase + com_dlbh,
3035 (u_int) COMBRD(gdbdefaultrate) >> 8);
3059 divisor = siodivisor(comdefaultrclk, gdbdefaultrate);
3060 outb(siogdbiobase + com_dlbl, divisor & 0xff);
3061 outb(siogdbiobase + com_dlbh, divisor >> 8);
3036 outb(siogdbiobase + com_cfcr, cfcr);
3037
3038 siocnopen(&sp, siogdbiobase, gdbdefaultrate);
3039 splx(s);
3040
3041 return (0);
3042}
3043

--- 114 unchanged lines hidden --- 		3062 outb(siogdbiobase + com_cfcr, cfcr);
3063
3064 siocnopen(&sp, siogdbiobase, gdbdefaultrate);
3065 splx(s);
3066
3067 return (0);
3068}
3069

--- 114 unchanged lines hidden ---