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hunt_impl.h (293889) hunt_impl.h (293890)
1/*-
2 * Copyright (c) 2012-2015 Solarflare Communications Inc.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 *
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
18 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
19 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
21 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
22 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
23 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
24 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 *
26 * The views and conclusions contained in the software and documentation are
27 * those of the authors and should not be interpreted as representing official
28 * policies, either expressed or implied, of the FreeBSD Project.
29 *
1/*-
2 * Copyright (c) 2012-2015 Solarflare Communications Inc.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 *
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
18 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
19 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
21 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
22 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
23 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
24 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 *
26 * The views and conclusions contained in the software and documentation are
27 * those of the authors and should not be interpreted as representing official
28 * policies, either expressed or implied, of the FreeBSD Project.
29 *
30 * $FreeBSD: head/sys/dev/sfxge/common/hunt_impl.h 293889 2016-01-14 09:01:53Z arybchik $
30 * $FreeBSD: head/sys/dev/sfxge/common/hunt_impl.h 293890 2016-01-14 09:03:02Z arybchik $
31 */
32
33#ifndef _SYS_HUNT_IMPL_H
34#define _SYS_HUNT_IMPL_H
35
36#include "efx.h"
37#include "efx_regs.h"
38#include "efx_regs_ef10.h"
39#include "efx_mcdi.h"
40
41#ifdef __cplusplus
42extern "C" {
43#endif
44
45/*
46 * FIXME: This is just a power of 2 which fits in an MCDI v1 message, and could
47 * possibly be increased, or the write size reported by newer firmware used
48 * instead.
49 */
50#define EF10_NVRAM_CHUNK 0x80
51
52/* Alignment requirement for value written to RX WPTR:
53 * the WPTR must be aligned to an 8 descriptor boundary
54 */
55#define EF10_RX_WPTR_ALIGN 8
56
57/*
58 * Max byte offset into the packet the TCP header must start for the hardware
59 * to be able to parse the packet correctly.
60 * FIXME: Move to ef10_impl.h when it is included in all driver builds.
61 */
62#define EF10_TCP_HEADER_OFFSET_LIMIT 208
63
64/* Invalid RSS context handle */
65#define EF10_RSS_CONTEXT_INVALID (0xffffffff)
66
67
68/* EV */
69
70 __checkReturn efx_rc_t
71ef10_ev_init(
72 __in efx_nic_t *enp);
73
74 void
75ef10_ev_fini(
76 __in efx_nic_t *enp);
77
78 __checkReturn efx_rc_t
79ef10_ev_qcreate(
80 __in efx_nic_t *enp,
81 __in unsigned int index,
82 __in efsys_mem_t *esmp,
83 __in size_t n,
84 __in uint32_t id,
85 __in efx_evq_t *eep);
86
87 void
88ef10_ev_qdestroy(
89 __in efx_evq_t *eep);
90
91 __checkReturn efx_rc_t
92ef10_ev_qprime(
93 __in efx_evq_t *eep,
94 __in unsigned int count);
95
96 void
97ef10_ev_qpost(
98 __in efx_evq_t *eep,
99 __in uint16_t data);
100
101 __checkReturn efx_rc_t
102ef10_ev_qmoderate(
103 __in efx_evq_t *eep,
104 __in unsigned int us);
105
106#if EFSYS_OPT_QSTATS
107 void
108ef10_ev_qstats_update(
109 __in efx_evq_t *eep,
110 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat);
111#endif /* EFSYS_OPT_QSTATS */
112
113 void
114ef10_ev_rxlabel_init(
115 __in efx_evq_t *eep,
116 __in efx_rxq_t *erp,
117 __in unsigned int label);
118
119 void
120ef10_ev_rxlabel_fini(
121 __in efx_evq_t *eep,
122 __in unsigned int label);
123
124/* INTR */
125
126 __checkReturn efx_rc_t
127ef10_intr_init(
128 __in efx_nic_t *enp,
129 __in efx_intr_type_t type,
130 __in efsys_mem_t *esmp);
131
132 void
133ef10_intr_enable(
134 __in efx_nic_t *enp);
135
136 void
137ef10_intr_disable(
138 __in efx_nic_t *enp);
139
140 void
141ef10_intr_disable_unlocked(
142 __in efx_nic_t *enp);
143
144 __checkReturn efx_rc_t
145ef10_intr_trigger(
146 __in efx_nic_t *enp,
147 __in unsigned int level);
148
149 void
150ef10_intr_status_line(
151 __in efx_nic_t *enp,
152 __out boolean_t *fatalp,
153 __out uint32_t *qmaskp);
154
155 void
156ef10_intr_status_message(
157 __in efx_nic_t *enp,
158 __in unsigned int message,
159 __out boolean_t *fatalp);
160
161 void
162ef10_intr_fatal(
163 __in efx_nic_t *enp);
164 void
165ef10_intr_fini(
166 __in efx_nic_t *enp);
167
168/* NIC */
169
170extern __checkReturn efx_rc_t
171ef10_nic_probe(
172 __in efx_nic_t *enp);
173
174extern __checkReturn efx_rc_t
175hunt_board_cfg(
176 __in efx_nic_t *enp);
177
178extern __checkReturn efx_rc_t
179ef10_nic_set_drv_limits(
180 __inout efx_nic_t *enp,
181 __in efx_drv_limits_t *edlp);
182
183extern __checkReturn efx_rc_t
184ef10_nic_get_vi_pool(
185 __in efx_nic_t *enp,
186 __out uint32_t *vi_countp);
187
188extern __checkReturn efx_rc_t
189ef10_nic_get_bar_region(
190 __in efx_nic_t *enp,
191 __in efx_nic_region_t region,
192 __out uint32_t *offsetp,
193 __out size_t *sizep);
194
195extern __checkReturn efx_rc_t
196ef10_nic_reset(
197 __in efx_nic_t *enp);
198
199extern __checkReturn efx_rc_t
200ef10_nic_init(
201 __in efx_nic_t *enp);
202
203#if EFSYS_OPT_DIAG
204
205extern __checkReturn efx_rc_t
206ef10_nic_register_test(
207 __in efx_nic_t *enp);
208
209#endif /* EFSYS_OPT_DIAG */
210
211extern void
212ef10_nic_fini(
213 __in efx_nic_t *enp);
214
215extern void
216ef10_nic_unprobe(
217 __in efx_nic_t *enp);
218
219
220/* MAC */
221
222extern __checkReturn efx_rc_t
223hunt_mac_poll(
224 __in efx_nic_t *enp,
225 __out efx_link_mode_t *link_modep);
226
227extern __checkReturn efx_rc_t
228hunt_mac_up(
229 __in efx_nic_t *enp,
230 __out boolean_t *mac_upp);
231
232extern __checkReturn efx_rc_t
233hunt_mac_addr_set(
234 __in efx_nic_t *enp);
235
236extern __checkReturn efx_rc_t
237hunt_mac_reconfigure(
238 __in efx_nic_t *enp);
239
240extern __checkReturn efx_rc_t
241hunt_mac_multicast_list_set(
242 __in efx_nic_t *enp);
243
244extern __checkReturn efx_rc_t
245hunt_mac_filter_default_rxq_set(
246 __in efx_nic_t *enp,
247 __in efx_rxq_t *erp,
248 __in boolean_t using_rss);
249
250extern void
251hunt_mac_filter_default_rxq_clear(
252 __in efx_nic_t *enp);
253
254#if EFSYS_OPT_LOOPBACK
255
256extern __checkReturn efx_rc_t
257hunt_mac_loopback_set(
258 __in efx_nic_t *enp,
259 __in efx_link_mode_t link_mode,
260 __in efx_loopback_type_t loopback_type);
261
262#endif /* EFSYS_OPT_LOOPBACK */
263
264#if EFSYS_OPT_MAC_STATS
265
266extern __checkReturn efx_rc_t
267hunt_mac_stats_update(
268 __in efx_nic_t *enp,
269 __in efsys_mem_t *esmp,
270 __inout_ecount(EFX_MAC_NSTATS) efsys_stat_t *stat,
271 __inout_opt uint32_t *generationp);
272
273#endif /* EFSYS_OPT_MAC_STATS */
274
275
276/* MCDI */
277
278#if EFSYS_OPT_MCDI
279
280extern __checkReturn efx_rc_t
281ef10_mcdi_init(
282 __in efx_nic_t *enp,
283 __in const efx_mcdi_transport_t *mtp);
284
285extern void
286ef10_mcdi_fini(
287 __in efx_nic_t *enp);
288
289extern void
290ef10_mcdi_send_request(
291 __in efx_nic_t *enp,
292 __in void *hdrp,
293 __in size_t hdr_len,
294 __in void *sdup,
295 __in size_t sdu_len);
296
297extern __checkReturn boolean_t
298ef10_mcdi_poll_response(
299 __in efx_nic_t *enp);
300
301extern void
302ef10_mcdi_read_response(
303 __in efx_nic_t *enp,
304 __out_bcount(length) void *bufferp,
305 __in size_t offset,
306 __in size_t length);
307
308extern void
309ef10_mcdi_request_copyout(
310 __in efx_nic_t *enp,
311 __in efx_mcdi_req_t *emrp);
312
313extern efx_rc_t
314ef10_mcdi_poll_reboot(
315 __in efx_nic_t *enp);
316
317extern __checkReturn efx_rc_t
318ef10_mcdi_feature_supported(
319 __in efx_nic_t *enp,
320 __in efx_mcdi_feature_id_t id,
321 __out boolean_t *supportedp);
322
323#endif /* EFSYS_OPT_MCDI */
324
325/* NVRAM */
326
327#if EFSYS_OPT_NVRAM || EFSYS_OPT_VPD
328
329extern __checkReturn efx_rc_t
330ef10_nvram_buf_read_tlv(
331 __in efx_nic_t *enp,
332 __in_bcount(max_seg_size) caddr_t seg_data,
333 __in size_t max_seg_size,
334 __in uint32_t tag,
335 __deref_out_bcount_opt(*sizep) caddr_t *datap,
336 __out size_t *sizep);
337
338extern __checkReturn efx_rc_t
339ef10_nvram_buf_write_tlv(
340 __inout_bcount(partn_size) caddr_t partn_data,
341 __in size_t partn_size,
342 __in uint32_t tag,
343 __in_bcount(tag_size) caddr_t tag_data,
344 __in size_t tag_size,
345 __out size_t *total_lengthp);
346
347extern __checkReturn efx_rc_t
348ef10_nvram_partn_read_tlv(
349 __in efx_nic_t *enp,
350 __in uint32_t partn,
351 __in uint32_t tag,
352 __deref_out_bcount_opt(*sizep) caddr_t *datap,
353 __out size_t *sizep);
354
355extern __checkReturn efx_rc_t
356ef10_nvram_partn_write_tlv(
357 __in efx_nic_t *enp,
358 __in uint32_t partn,
359 __in uint32_t tag,
360 __in_bcount(size) caddr_t data,
361 __in size_t size);
362
363extern __checkReturn efx_rc_t
364ef10_nvram_partn_write_segment_tlv(
365 __in efx_nic_t *enp,
366 __in uint32_t partn,
367 __in uint32_t tag,
368 __in_bcount(size) caddr_t data,
369 __in size_t size,
370 __in boolean_t all_segments);
371
372extern __checkReturn efx_rc_t
373ef10_nvram_partn_lock(
374 __in efx_nic_t *enp,
375 __in uint32_t partn);
376
377extern __checkReturn efx_rc_t
378ef10_nvram_partn_read(
379 __in efx_nic_t *enp,
380 __in uint32_t partn,
381 __in unsigned int offset,
382 __out_bcount(size) caddr_t data,
383 __in size_t size);
384
385extern __checkReturn efx_rc_t
386ef10_nvram_partn_erase(
387 __in efx_nic_t *enp,
388 __in uint32_t partn,
389 __in unsigned int offset,
390 __in size_t size);
391
392extern __checkReturn efx_rc_t
393ef10_nvram_partn_write(
394 __in efx_nic_t *enp,
395 __in uint32_t partn,
396 __in unsigned int offset,
397 __out_bcount(size) caddr_t data,
398 __in size_t size);
399
400extern void
401ef10_nvram_partn_unlock(
402 __in efx_nic_t *enp,
403 __in uint32_t partn);
404
405#endif /* EFSYS_OPT_NVRAM || EFSYS_OPT_VPD */
406
407#if EFSYS_OPT_NVRAM
408
409#if EFSYS_OPT_DIAG
410
411extern __checkReturn efx_rc_t
412ef10_nvram_test(
413 __in efx_nic_t *enp);
414
415#endif /* EFSYS_OPT_DIAG */
416
417extern __checkReturn efx_rc_t
418ef10_nvram_get_version(
419 __in efx_nic_t *enp,
420 __in efx_nvram_type_t type,
421 __out uint32_t *subtypep,
422 __out_ecount(4) uint16_t version[4]);
423
424extern __checkReturn efx_rc_t
425ef10_nvram_rw_start(
426 __in efx_nic_t *enp,
427 __in efx_nvram_type_t type,
428 __out size_t *pref_chunkp);
429
430extern __checkReturn efx_rc_t
431ef10_nvram_read_chunk(
432 __in efx_nic_t *enp,
433 __in efx_nvram_type_t type,
434 __in unsigned int offset,
435 __out_bcount(size) caddr_t data,
436 __in size_t size);
437
438extern __checkReturn efx_rc_t
439ef10_nvram_erase(
440 __in efx_nic_t *enp,
441 __in efx_nvram_type_t type);
442
443extern __checkReturn efx_rc_t
444ef10_nvram_write_chunk(
445 __in efx_nic_t *enp,
446 __in efx_nvram_type_t type,
447 __in unsigned int offset,
448 __in_bcount(size) caddr_t data,
449 __in size_t size);
450
451extern void
452ef10_nvram_rw_finish(
453 __in efx_nic_t *enp,
454 __in efx_nvram_type_t type);
455
456extern __checkReturn efx_rc_t
457ef10_nvram_partn_set_version(
458 __in efx_nic_t *enp,
459 __in uint32_t partn,
460 __in_ecount(4) uint16_t version[4]);
461
462extern __checkReturn efx_rc_t
463ef10_nvram_set_version(
464 __in efx_nic_t *enp,
465 __in efx_nvram_type_t type,
466 __in_ecount(4) uint16_t version[4]);
467
468extern __checkReturn efx_rc_t
469ef10_nvram_type_to_partn(
470 __in efx_nic_t *enp,
471 __in efx_nvram_type_t type,
472 __out uint32_t *partnp);
473
474extern __checkReturn efx_rc_t
475ef10_nvram_partn_size(
476 __in efx_nic_t *enp,
477 __in uint32_t partn,
478 __out size_t *sizep);
479
480#endif /* EFSYS_OPT_NVRAM */
481
482
483/* PHY */
484
485typedef struct hunt_link_state_s {
486 uint32_t hls_adv_cap_mask;
487 uint32_t hls_lp_cap_mask;
488 unsigned int hls_fcntl;
489 efx_link_mode_t hls_link_mode;
490#if EFSYS_OPT_LOOPBACK
491 efx_loopback_type_t hls_loopback;
492#endif
493 boolean_t hls_mac_up;
494} hunt_link_state_t;
495
496extern void
497hunt_phy_link_ev(
498 __in efx_nic_t *enp,
499 __in efx_qword_t *eqp,
500 __out efx_link_mode_t *link_modep);
501
502extern __checkReturn efx_rc_t
503hunt_phy_get_link(
504 __in efx_nic_t *enp,
505 __out hunt_link_state_t *hlsp);
506
507extern __checkReturn efx_rc_t
508hunt_phy_power(
509 __in efx_nic_t *enp,
510 __in boolean_t on);
511
512extern __checkReturn efx_rc_t
513hunt_phy_reconfigure(
514 __in efx_nic_t *enp);
515
516extern __checkReturn efx_rc_t
517hunt_phy_verify(
518 __in efx_nic_t *enp);
519
520extern __checkReturn efx_rc_t
521hunt_phy_oui_get(
522 __in efx_nic_t *enp,
523 __out uint32_t *ouip);
524
525#if EFSYS_OPT_PHY_STATS
526
527extern __checkReturn efx_rc_t
528hunt_phy_stats_update(
529 __in efx_nic_t *enp,
530 __in efsys_mem_t *esmp,
531 __inout_ecount(EFX_PHY_NSTATS) uint32_t *stat);
532
533#endif /* EFSYS_OPT_PHY_STATS */
534
535#if EFSYS_OPT_PHY_PROPS
536
537#if EFSYS_OPT_NAMES
538
539extern const char *
540hunt_phy_prop_name(
541 __in efx_nic_t *enp,
542 __in unsigned int id);
543
544#endif /* EFSYS_OPT_NAMES */
545
546extern __checkReturn efx_rc_t
547hunt_phy_prop_get(
548 __in efx_nic_t *enp,
549 __in unsigned int id,
550 __in uint32_t flags,
551 __out uint32_t *valp);
552
553extern __checkReturn efx_rc_t
554hunt_phy_prop_set(
555 __in efx_nic_t *enp,
556 __in unsigned int id,
557 __in uint32_t val);
558
559#endif /* EFSYS_OPT_PHY_PROPS */
560
561#if EFSYS_OPT_BIST
562
563extern __checkReturn efx_rc_t
564hunt_bist_enable_offline(
565 __in efx_nic_t *enp);
566
567extern __checkReturn efx_rc_t
568hunt_bist_start(
569 __in efx_nic_t *enp,
570 __in efx_bist_type_t type);
571
572extern __checkReturn efx_rc_t
573hunt_bist_poll(
574 __in efx_nic_t *enp,
575 __in efx_bist_type_t type,
576 __out efx_bist_result_t *resultp,
577 __out_opt __drv_when(count > 0, __notnull)
578 uint32_t *value_maskp,
579 __out_ecount_opt(count) __drv_when(count > 0, __notnull)
580 unsigned long *valuesp,
581 __in size_t count);
582
583extern void
584hunt_bist_stop(
585 __in efx_nic_t *enp,
586 __in efx_bist_type_t type);
587
588#endif /* EFSYS_OPT_BIST */
589
590
591/* SRAM */
592
593#if EFSYS_OPT_DIAG
594
595extern __checkReturn efx_rc_t
596ef10_sram_test(
597 __in efx_nic_t *enp,
598 __in efx_sram_pattern_fn_t func);
599
600#endif /* EFSYS_OPT_DIAG */
601
602
603/* TX */
604
605extern __checkReturn efx_rc_t
606ef10_tx_init(
607 __in efx_nic_t *enp);
608
609extern void
610ef10_tx_fini(
611 __in efx_nic_t *enp);
612
613extern __checkReturn efx_rc_t
614ef10_tx_qcreate(
615 __in efx_nic_t *enp,
616 __in unsigned int index,
617 __in unsigned int label,
618 __in efsys_mem_t *esmp,
619 __in size_t n,
620 __in uint32_t id,
621 __in uint16_t flags,
622 __in efx_evq_t *eep,
623 __in efx_txq_t *etp,
624 __out unsigned int *addedp);
625
626extern void
627ef10_tx_qdestroy(
628 __in efx_txq_t *etp);
629
630extern __checkReturn efx_rc_t
631ef10_tx_qpost(
632 __in efx_txq_t *etp,
633 __in_ecount(n) efx_buffer_t *eb,
634 __in unsigned int n,
635 __in unsigned int completed,
636 __inout unsigned int *addedp);
637
638extern void
639ef10_tx_qpush(
640 __in efx_txq_t *etp,
641 __in unsigned int added,
642 __in unsigned int pushed);
643
644extern __checkReturn efx_rc_t
645ef10_tx_qpace(
646 __in efx_txq_t *etp,
647 __in unsigned int ns);
648
649extern __checkReturn efx_rc_t
650ef10_tx_qflush(
651 __in efx_txq_t *etp);
652
653extern void
654ef10_tx_qenable(
655 __in efx_txq_t *etp);
656
657extern __checkReturn efx_rc_t
658ef10_tx_qpio_enable(
659 __in efx_txq_t *etp);
660
661extern void
662ef10_tx_qpio_disable(
663 __in efx_txq_t *etp);
664
665extern __checkReturn efx_rc_t
666ef10_tx_qpio_write(
667 __in efx_txq_t *etp,
668 __in_ecount(buf_length) uint8_t *buffer,
669 __in size_t buf_length,
670 __in size_t pio_buf_offset);
671
672extern __checkReturn efx_rc_t
673ef10_tx_qpio_post(
674 __in efx_txq_t *etp,
675 __in size_t pkt_length,
676 __in unsigned int completed,
677 __inout unsigned int *addedp);
678
679extern __checkReturn efx_rc_t
680ef10_tx_qdesc_post(
681 __in efx_txq_t *etp,
682 __in_ecount(n) efx_desc_t *ed,
683 __in unsigned int n,
684 __in unsigned int completed,
685 __inout unsigned int *addedp);
686
687extern void
688ef10_tx_qdesc_dma_create(
689 __in efx_txq_t *etp,
690 __in efsys_dma_addr_t addr,
691 __in size_t size,
692 __in boolean_t eop,
693 __out efx_desc_t *edp);
694
695extern void
696hunt_tx_qdesc_tso_create(
697 __in efx_txq_t *etp,
698 __in uint16_t ipv4_id,
699 __in uint32_t tcp_seq,
700 __in uint8_t tcp_flags,
701 __out efx_desc_t *edp);
702
703extern void
704ef10_tx_qdesc_vlantci_create(
705 __in efx_txq_t *etp,
706 __in uint16_t vlan_tci,
707 __out efx_desc_t *edp);
708
709
710#if EFSYS_OPT_QSTATS
711
712extern void
713ef10_tx_qstats_update(
714 __in efx_txq_t *etp,
715 __inout_ecount(TX_NQSTATS) efsys_stat_t *stat);
716
717#endif /* EFSYS_OPT_QSTATS */
718
719/* PIO */
720
721/* Missing register definitions */
722#ifndef ER_DZ_TX_PIOBUF_OFST
723#define ER_DZ_TX_PIOBUF_OFST 0x00001000
724#endif
725#ifndef ER_DZ_TX_PIOBUF_STEP
726#define ER_DZ_TX_PIOBUF_STEP 8192
727#endif
728#ifndef ER_DZ_TX_PIOBUF_ROWS
729#define ER_DZ_TX_PIOBUF_ROWS 2048
730#endif
731
732#ifndef ER_DZ_TX_PIOBUF_SIZE
733#define ER_DZ_TX_PIOBUF_SIZE 2048
734#endif
735
736#define HUNT_PIOBUF_NBUFS (16)
737#define HUNT_PIOBUF_SIZE (ER_DZ_TX_PIOBUF_SIZE)
738
739#define HUNT_MIN_PIO_ALLOC_SIZE (HUNT_PIOBUF_SIZE / 32)
740
741#define HUNT_LEGACY_PF_PRIVILEGE_MASK \
742 (MC_CMD_PRIVILEGE_MASK_IN_GRP_ADMIN | \
743 MC_CMD_PRIVILEGE_MASK_IN_GRP_LINK | \
744 MC_CMD_PRIVILEGE_MASK_IN_GRP_ONLOAD | \
745 MC_CMD_PRIVILEGE_MASK_IN_GRP_PTP | \
746 MC_CMD_PRIVILEGE_MASK_IN_GRP_INSECURE_FILTERS | \
747 MC_CMD_PRIVILEGE_MASK_IN_GRP_MAC_SPOOFING | \
748 MC_CMD_PRIVILEGE_MASK_IN_GRP_UNICAST | \
749 MC_CMD_PRIVILEGE_MASK_IN_GRP_MULTICAST | \
750 MC_CMD_PRIVILEGE_MASK_IN_GRP_BROADCAST | \
751 MC_CMD_PRIVILEGE_MASK_IN_GRP_ALL_MULTICAST | \
752 MC_CMD_PRIVILEGE_MASK_IN_GRP_PROMISCUOUS)
753
754#define HUNT_LEGACY_VF_PRIVILEGE_MASK 0
755
756typedef uint32_t efx_piobuf_handle_t;
757
758#define EFX_PIOBUF_HANDLE_INVALID ((efx_piobuf_handle_t) -1)
759
760extern __checkReturn efx_rc_t
761ef10_nic_pio_alloc(
762 __inout efx_nic_t *enp,
763 __out uint32_t *bufnump,
764 __out efx_piobuf_handle_t *handlep,
765 __out uint32_t *blknump,
766 __out uint32_t *offsetp,
767 __out size_t *sizep);
768
769extern __checkReturn efx_rc_t
770ef10_nic_pio_free(
771 __inout efx_nic_t *enp,
772 __in uint32_t bufnum,
773 __in uint32_t blknum);
774
775extern __checkReturn efx_rc_t
776ef10_nic_pio_link(
777 __inout efx_nic_t *enp,
778 __in uint32_t vi_index,
779 __in efx_piobuf_handle_t handle);
780
781extern __checkReturn efx_rc_t
782ef10_nic_pio_unlink(
783 __inout efx_nic_t *enp,
784 __in uint32_t vi_index);
785
786
787/* VPD */
788
789#if EFSYS_OPT_VPD
790
791extern __checkReturn efx_rc_t
792ef10_vpd_init(
793 __in efx_nic_t *enp);
794
795extern __checkReturn efx_rc_t
796ef10_vpd_size(
797 __in efx_nic_t *enp,
798 __out size_t *sizep);
799
800extern __checkReturn efx_rc_t
801ef10_vpd_read(
802 __in efx_nic_t *enp,
803 __out_bcount(size) caddr_t data,
804 __in size_t size);
805
806extern __checkReturn efx_rc_t
807ef10_vpd_verify(
808 __in efx_nic_t *enp,
809 __in_bcount(size) caddr_t data,
810 __in size_t size);
811
812extern __checkReturn efx_rc_t
813ef10_vpd_reinit(
814 __in efx_nic_t *enp,
815 __in_bcount(size) caddr_t data,
816 __in size_t size);
817
818extern __checkReturn efx_rc_t
819ef10_vpd_get(
820 __in efx_nic_t *enp,
821 __in_bcount(size) caddr_t data,
822 __in size_t size,
823 __inout efx_vpd_value_t *evvp);
824
825extern __checkReturn efx_rc_t
826ef10_vpd_set(
827 __in efx_nic_t *enp,
828 __in_bcount(size) caddr_t data,
829 __in size_t size,
830 __in efx_vpd_value_t *evvp);
831
832extern __checkReturn efx_rc_t
833ef10_vpd_next(
834 __in efx_nic_t *enp,
835 __in_bcount(size) caddr_t data,
836 __in size_t size,
837 __out efx_vpd_value_t *evvp,
838 __inout unsigned int *contp);
839
840extern __checkReturn efx_rc_t
841ef10_vpd_write(
842 __in efx_nic_t *enp,
843 __in_bcount(size) caddr_t data,
844 __in size_t size);
845
846extern void
847ef10_vpd_fini(
848 __in efx_nic_t *enp);
849
850#endif /* EFSYS_OPT_VPD */
851
852
853/* RX */
854
855extern __checkReturn efx_rc_t
856ef10_rx_init(
857 __in efx_nic_t *enp);
858
859#if EFSYS_OPT_RX_SCATTER
860extern __checkReturn efx_rc_t
861ef10_rx_scatter_enable(
862 __in efx_nic_t *enp,
863 __in unsigned int buf_size);
864#endif /* EFSYS_OPT_RX_SCATTER */
865
866
867#if EFSYS_OPT_RX_SCALE
868
869extern __checkReturn efx_rc_t
870ef10_rx_scale_mode_set(
871 __in efx_nic_t *enp,
872 __in efx_rx_hash_alg_t alg,
873 __in efx_rx_hash_type_t type,
874 __in boolean_t insert);
875
876extern __checkReturn efx_rc_t
877ef10_rx_scale_key_set(
878 __in efx_nic_t *enp,
879 __in_ecount(n) uint8_t *key,
880 __in size_t n);
881
882extern __checkReturn efx_rc_t
883ef10_rx_scale_tbl_set(
884 __in efx_nic_t *enp,
885 __in_ecount(n) unsigned int *table,
886 __in size_t n);
887
888extern __checkReturn uint32_t
889ef10_rx_prefix_hash(
890 __in efx_nic_t *enp,
891 __in efx_rx_hash_alg_t func,
892 __in uint8_t *buffer);
893
31 */
32
33#ifndef _SYS_HUNT_IMPL_H
34#define _SYS_HUNT_IMPL_H
35
36#include "efx.h"
37#include "efx_regs.h"
38#include "efx_regs_ef10.h"
39#include "efx_mcdi.h"
40
41#ifdef __cplusplus
42extern "C" {
43#endif
44
45/*
46 * FIXME: This is just a power of 2 which fits in an MCDI v1 message, and could
47 * possibly be increased, or the write size reported by newer firmware used
48 * instead.
49 */
50#define EF10_NVRAM_CHUNK 0x80
51
52/* Alignment requirement for value written to RX WPTR:
53 * the WPTR must be aligned to an 8 descriptor boundary
54 */
55#define EF10_RX_WPTR_ALIGN 8
56
57/*
58 * Max byte offset into the packet the TCP header must start for the hardware
59 * to be able to parse the packet correctly.
60 * FIXME: Move to ef10_impl.h when it is included in all driver builds.
61 */
62#define EF10_TCP_HEADER_OFFSET_LIMIT 208
63
64/* Invalid RSS context handle */
65#define EF10_RSS_CONTEXT_INVALID (0xffffffff)
66
67
68/* EV */
69
70 __checkReturn efx_rc_t
71ef10_ev_init(
72 __in efx_nic_t *enp);
73
74 void
75ef10_ev_fini(
76 __in efx_nic_t *enp);
77
78 __checkReturn efx_rc_t
79ef10_ev_qcreate(
80 __in efx_nic_t *enp,
81 __in unsigned int index,
82 __in efsys_mem_t *esmp,
83 __in size_t n,
84 __in uint32_t id,
85 __in efx_evq_t *eep);
86
87 void
88ef10_ev_qdestroy(
89 __in efx_evq_t *eep);
90
91 __checkReturn efx_rc_t
92ef10_ev_qprime(
93 __in efx_evq_t *eep,
94 __in unsigned int count);
95
96 void
97ef10_ev_qpost(
98 __in efx_evq_t *eep,
99 __in uint16_t data);
100
101 __checkReturn efx_rc_t
102ef10_ev_qmoderate(
103 __in efx_evq_t *eep,
104 __in unsigned int us);
105
106#if EFSYS_OPT_QSTATS
107 void
108ef10_ev_qstats_update(
109 __in efx_evq_t *eep,
110 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat);
111#endif /* EFSYS_OPT_QSTATS */
112
113 void
114ef10_ev_rxlabel_init(
115 __in efx_evq_t *eep,
116 __in efx_rxq_t *erp,
117 __in unsigned int label);
118
119 void
120ef10_ev_rxlabel_fini(
121 __in efx_evq_t *eep,
122 __in unsigned int label);
123
124/* INTR */
125
126 __checkReturn efx_rc_t
127ef10_intr_init(
128 __in efx_nic_t *enp,
129 __in efx_intr_type_t type,
130 __in efsys_mem_t *esmp);
131
132 void
133ef10_intr_enable(
134 __in efx_nic_t *enp);
135
136 void
137ef10_intr_disable(
138 __in efx_nic_t *enp);
139
140 void
141ef10_intr_disable_unlocked(
142 __in efx_nic_t *enp);
143
144 __checkReturn efx_rc_t
145ef10_intr_trigger(
146 __in efx_nic_t *enp,
147 __in unsigned int level);
148
149 void
150ef10_intr_status_line(
151 __in efx_nic_t *enp,
152 __out boolean_t *fatalp,
153 __out uint32_t *qmaskp);
154
155 void
156ef10_intr_status_message(
157 __in efx_nic_t *enp,
158 __in unsigned int message,
159 __out boolean_t *fatalp);
160
161 void
162ef10_intr_fatal(
163 __in efx_nic_t *enp);
164 void
165ef10_intr_fini(
166 __in efx_nic_t *enp);
167
168/* NIC */
169
170extern __checkReturn efx_rc_t
171ef10_nic_probe(
172 __in efx_nic_t *enp);
173
174extern __checkReturn efx_rc_t
175hunt_board_cfg(
176 __in efx_nic_t *enp);
177
178extern __checkReturn efx_rc_t
179ef10_nic_set_drv_limits(
180 __inout efx_nic_t *enp,
181 __in efx_drv_limits_t *edlp);
182
183extern __checkReturn efx_rc_t
184ef10_nic_get_vi_pool(
185 __in efx_nic_t *enp,
186 __out uint32_t *vi_countp);
187
188extern __checkReturn efx_rc_t
189ef10_nic_get_bar_region(
190 __in efx_nic_t *enp,
191 __in efx_nic_region_t region,
192 __out uint32_t *offsetp,
193 __out size_t *sizep);
194
195extern __checkReturn efx_rc_t
196ef10_nic_reset(
197 __in efx_nic_t *enp);
198
199extern __checkReturn efx_rc_t
200ef10_nic_init(
201 __in efx_nic_t *enp);
202
203#if EFSYS_OPT_DIAG
204
205extern __checkReturn efx_rc_t
206ef10_nic_register_test(
207 __in efx_nic_t *enp);
208
209#endif /* EFSYS_OPT_DIAG */
210
211extern void
212ef10_nic_fini(
213 __in efx_nic_t *enp);
214
215extern void
216ef10_nic_unprobe(
217 __in efx_nic_t *enp);
218
219
220/* MAC */
221
222extern __checkReturn efx_rc_t
223hunt_mac_poll(
224 __in efx_nic_t *enp,
225 __out efx_link_mode_t *link_modep);
226
227extern __checkReturn efx_rc_t
228hunt_mac_up(
229 __in efx_nic_t *enp,
230 __out boolean_t *mac_upp);
231
232extern __checkReturn efx_rc_t
233hunt_mac_addr_set(
234 __in efx_nic_t *enp);
235
236extern __checkReturn efx_rc_t
237hunt_mac_reconfigure(
238 __in efx_nic_t *enp);
239
240extern __checkReturn efx_rc_t
241hunt_mac_multicast_list_set(
242 __in efx_nic_t *enp);
243
244extern __checkReturn efx_rc_t
245hunt_mac_filter_default_rxq_set(
246 __in efx_nic_t *enp,
247 __in efx_rxq_t *erp,
248 __in boolean_t using_rss);
249
250extern void
251hunt_mac_filter_default_rxq_clear(
252 __in efx_nic_t *enp);
253
254#if EFSYS_OPT_LOOPBACK
255
256extern __checkReturn efx_rc_t
257hunt_mac_loopback_set(
258 __in efx_nic_t *enp,
259 __in efx_link_mode_t link_mode,
260 __in efx_loopback_type_t loopback_type);
261
262#endif /* EFSYS_OPT_LOOPBACK */
263
264#if EFSYS_OPT_MAC_STATS
265
266extern __checkReturn efx_rc_t
267hunt_mac_stats_update(
268 __in efx_nic_t *enp,
269 __in efsys_mem_t *esmp,
270 __inout_ecount(EFX_MAC_NSTATS) efsys_stat_t *stat,
271 __inout_opt uint32_t *generationp);
272
273#endif /* EFSYS_OPT_MAC_STATS */
274
275
276/* MCDI */
277
278#if EFSYS_OPT_MCDI
279
280extern __checkReturn efx_rc_t
281ef10_mcdi_init(
282 __in efx_nic_t *enp,
283 __in const efx_mcdi_transport_t *mtp);
284
285extern void
286ef10_mcdi_fini(
287 __in efx_nic_t *enp);
288
289extern void
290ef10_mcdi_send_request(
291 __in efx_nic_t *enp,
292 __in void *hdrp,
293 __in size_t hdr_len,
294 __in void *sdup,
295 __in size_t sdu_len);
296
297extern __checkReturn boolean_t
298ef10_mcdi_poll_response(
299 __in efx_nic_t *enp);
300
301extern void
302ef10_mcdi_read_response(
303 __in efx_nic_t *enp,
304 __out_bcount(length) void *bufferp,
305 __in size_t offset,
306 __in size_t length);
307
308extern void
309ef10_mcdi_request_copyout(
310 __in efx_nic_t *enp,
311 __in efx_mcdi_req_t *emrp);
312
313extern efx_rc_t
314ef10_mcdi_poll_reboot(
315 __in efx_nic_t *enp);
316
317extern __checkReturn efx_rc_t
318ef10_mcdi_feature_supported(
319 __in efx_nic_t *enp,
320 __in efx_mcdi_feature_id_t id,
321 __out boolean_t *supportedp);
322
323#endif /* EFSYS_OPT_MCDI */
324
325/* NVRAM */
326
327#if EFSYS_OPT_NVRAM || EFSYS_OPT_VPD
328
329extern __checkReturn efx_rc_t
330ef10_nvram_buf_read_tlv(
331 __in efx_nic_t *enp,
332 __in_bcount(max_seg_size) caddr_t seg_data,
333 __in size_t max_seg_size,
334 __in uint32_t tag,
335 __deref_out_bcount_opt(*sizep) caddr_t *datap,
336 __out size_t *sizep);
337
338extern __checkReturn efx_rc_t
339ef10_nvram_buf_write_tlv(
340 __inout_bcount(partn_size) caddr_t partn_data,
341 __in size_t partn_size,
342 __in uint32_t tag,
343 __in_bcount(tag_size) caddr_t tag_data,
344 __in size_t tag_size,
345 __out size_t *total_lengthp);
346
347extern __checkReturn efx_rc_t
348ef10_nvram_partn_read_tlv(
349 __in efx_nic_t *enp,
350 __in uint32_t partn,
351 __in uint32_t tag,
352 __deref_out_bcount_opt(*sizep) caddr_t *datap,
353 __out size_t *sizep);
354
355extern __checkReturn efx_rc_t
356ef10_nvram_partn_write_tlv(
357 __in efx_nic_t *enp,
358 __in uint32_t partn,
359 __in uint32_t tag,
360 __in_bcount(size) caddr_t data,
361 __in size_t size);
362
363extern __checkReturn efx_rc_t
364ef10_nvram_partn_write_segment_tlv(
365 __in efx_nic_t *enp,
366 __in uint32_t partn,
367 __in uint32_t tag,
368 __in_bcount(size) caddr_t data,
369 __in size_t size,
370 __in boolean_t all_segments);
371
372extern __checkReturn efx_rc_t
373ef10_nvram_partn_lock(
374 __in efx_nic_t *enp,
375 __in uint32_t partn);
376
377extern __checkReturn efx_rc_t
378ef10_nvram_partn_read(
379 __in efx_nic_t *enp,
380 __in uint32_t partn,
381 __in unsigned int offset,
382 __out_bcount(size) caddr_t data,
383 __in size_t size);
384
385extern __checkReturn efx_rc_t
386ef10_nvram_partn_erase(
387 __in efx_nic_t *enp,
388 __in uint32_t partn,
389 __in unsigned int offset,
390 __in size_t size);
391
392extern __checkReturn efx_rc_t
393ef10_nvram_partn_write(
394 __in efx_nic_t *enp,
395 __in uint32_t partn,
396 __in unsigned int offset,
397 __out_bcount(size) caddr_t data,
398 __in size_t size);
399
400extern void
401ef10_nvram_partn_unlock(
402 __in efx_nic_t *enp,
403 __in uint32_t partn);
404
405#endif /* EFSYS_OPT_NVRAM || EFSYS_OPT_VPD */
406
407#if EFSYS_OPT_NVRAM
408
409#if EFSYS_OPT_DIAG
410
411extern __checkReturn efx_rc_t
412ef10_nvram_test(
413 __in efx_nic_t *enp);
414
415#endif /* EFSYS_OPT_DIAG */
416
417extern __checkReturn efx_rc_t
418ef10_nvram_get_version(
419 __in efx_nic_t *enp,
420 __in efx_nvram_type_t type,
421 __out uint32_t *subtypep,
422 __out_ecount(4) uint16_t version[4]);
423
424extern __checkReturn efx_rc_t
425ef10_nvram_rw_start(
426 __in efx_nic_t *enp,
427 __in efx_nvram_type_t type,
428 __out size_t *pref_chunkp);
429
430extern __checkReturn efx_rc_t
431ef10_nvram_read_chunk(
432 __in efx_nic_t *enp,
433 __in efx_nvram_type_t type,
434 __in unsigned int offset,
435 __out_bcount(size) caddr_t data,
436 __in size_t size);
437
438extern __checkReturn efx_rc_t
439ef10_nvram_erase(
440 __in efx_nic_t *enp,
441 __in efx_nvram_type_t type);
442
443extern __checkReturn efx_rc_t
444ef10_nvram_write_chunk(
445 __in efx_nic_t *enp,
446 __in efx_nvram_type_t type,
447 __in unsigned int offset,
448 __in_bcount(size) caddr_t data,
449 __in size_t size);
450
451extern void
452ef10_nvram_rw_finish(
453 __in efx_nic_t *enp,
454 __in efx_nvram_type_t type);
455
456extern __checkReturn efx_rc_t
457ef10_nvram_partn_set_version(
458 __in efx_nic_t *enp,
459 __in uint32_t partn,
460 __in_ecount(4) uint16_t version[4]);
461
462extern __checkReturn efx_rc_t
463ef10_nvram_set_version(
464 __in efx_nic_t *enp,
465 __in efx_nvram_type_t type,
466 __in_ecount(4) uint16_t version[4]);
467
468extern __checkReturn efx_rc_t
469ef10_nvram_type_to_partn(
470 __in efx_nic_t *enp,
471 __in efx_nvram_type_t type,
472 __out uint32_t *partnp);
473
474extern __checkReturn efx_rc_t
475ef10_nvram_partn_size(
476 __in efx_nic_t *enp,
477 __in uint32_t partn,
478 __out size_t *sizep);
479
480#endif /* EFSYS_OPT_NVRAM */
481
482
483/* PHY */
484
485typedef struct hunt_link_state_s {
486 uint32_t hls_adv_cap_mask;
487 uint32_t hls_lp_cap_mask;
488 unsigned int hls_fcntl;
489 efx_link_mode_t hls_link_mode;
490#if EFSYS_OPT_LOOPBACK
491 efx_loopback_type_t hls_loopback;
492#endif
493 boolean_t hls_mac_up;
494} hunt_link_state_t;
495
496extern void
497hunt_phy_link_ev(
498 __in efx_nic_t *enp,
499 __in efx_qword_t *eqp,
500 __out efx_link_mode_t *link_modep);
501
502extern __checkReturn efx_rc_t
503hunt_phy_get_link(
504 __in efx_nic_t *enp,
505 __out hunt_link_state_t *hlsp);
506
507extern __checkReturn efx_rc_t
508hunt_phy_power(
509 __in efx_nic_t *enp,
510 __in boolean_t on);
511
512extern __checkReturn efx_rc_t
513hunt_phy_reconfigure(
514 __in efx_nic_t *enp);
515
516extern __checkReturn efx_rc_t
517hunt_phy_verify(
518 __in efx_nic_t *enp);
519
520extern __checkReturn efx_rc_t
521hunt_phy_oui_get(
522 __in efx_nic_t *enp,
523 __out uint32_t *ouip);
524
525#if EFSYS_OPT_PHY_STATS
526
527extern __checkReturn efx_rc_t
528hunt_phy_stats_update(
529 __in efx_nic_t *enp,
530 __in efsys_mem_t *esmp,
531 __inout_ecount(EFX_PHY_NSTATS) uint32_t *stat);
532
533#endif /* EFSYS_OPT_PHY_STATS */
534
535#if EFSYS_OPT_PHY_PROPS
536
537#if EFSYS_OPT_NAMES
538
539extern const char *
540hunt_phy_prop_name(
541 __in efx_nic_t *enp,
542 __in unsigned int id);
543
544#endif /* EFSYS_OPT_NAMES */
545
546extern __checkReturn efx_rc_t
547hunt_phy_prop_get(
548 __in efx_nic_t *enp,
549 __in unsigned int id,
550 __in uint32_t flags,
551 __out uint32_t *valp);
552
553extern __checkReturn efx_rc_t
554hunt_phy_prop_set(
555 __in efx_nic_t *enp,
556 __in unsigned int id,
557 __in uint32_t val);
558
559#endif /* EFSYS_OPT_PHY_PROPS */
560
561#if EFSYS_OPT_BIST
562
563extern __checkReturn efx_rc_t
564hunt_bist_enable_offline(
565 __in efx_nic_t *enp);
566
567extern __checkReturn efx_rc_t
568hunt_bist_start(
569 __in efx_nic_t *enp,
570 __in efx_bist_type_t type);
571
572extern __checkReturn efx_rc_t
573hunt_bist_poll(
574 __in efx_nic_t *enp,
575 __in efx_bist_type_t type,
576 __out efx_bist_result_t *resultp,
577 __out_opt __drv_when(count > 0, __notnull)
578 uint32_t *value_maskp,
579 __out_ecount_opt(count) __drv_when(count > 0, __notnull)
580 unsigned long *valuesp,
581 __in size_t count);
582
583extern void
584hunt_bist_stop(
585 __in efx_nic_t *enp,
586 __in efx_bist_type_t type);
587
588#endif /* EFSYS_OPT_BIST */
589
590
591/* SRAM */
592
593#if EFSYS_OPT_DIAG
594
595extern __checkReturn efx_rc_t
596ef10_sram_test(
597 __in efx_nic_t *enp,
598 __in efx_sram_pattern_fn_t func);
599
600#endif /* EFSYS_OPT_DIAG */
601
602
603/* TX */
604
605extern __checkReturn efx_rc_t
606ef10_tx_init(
607 __in efx_nic_t *enp);
608
609extern void
610ef10_tx_fini(
611 __in efx_nic_t *enp);
612
613extern __checkReturn efx_rc_t
614ef10_tx_qcreate(
615 __in efx_nic_t *enp,
616 __in unsigned int index,
617 __in unsigned int label,
618 __in efsys_mem_t *esmp,
619 __in size_t n,
620 __in uint32_t id,
621 __in uint16_t flags,
622 __in efx_evq_t *eep,
623 __in efx_txq_t *etp,
624 __out unsigned int *addedp);
625
626extern void
627ef10_tx_qdestroy(
628 __in efx_txq_t *etp);
629
630extern __checkReturn efx_rc_t
631ef10_tx_qpost(
632 __in efx_txq_t *etp,
633 __in_ecount(n) efx_buffer_t *eb,
634 __in unsigned int n,
635 __in unsigned int completed,
636 __inout unsigned int *addedp);
637
638extern void
639ef10_tx_qpush(
640 __in efx_txq_t *etp,
641 __in unsigned int added,
642 __in unsigned int pushed);
643
644extern __checkReturn efx_rc_t
645ef10_tx_qpace(
646 __in efx_txq_t *etp,
647 __in unsigned int ns);
648
649extern __checkReturn efx_rc_t
650ef10_tx_qflush(
651 __in efx_txq_t *etp);
652
653extern void
654ef10_tx_qenable(
655 __in efx_txq_t *etp);
656
657extern __checkReturn efx_rc_t
658ef10_tx_qpio_enable(
659 __in efx_txq_t *etp);
660
661extern void
662ef10_tx_qpio_disable(
663 __in efx_txq_t *etp);
664
665extern __checkReturn efx_rc_t
666ef10_tx_qpio_write(
667 __in efx_txq_t *etp,
668 __in_ecount(buf_length) uint8_t *buffer,
669 __in size_t buf_length,
670 __in size_t pio_buf_offset);
671
672extern __checkReturn efx_rc_t
673ef10_tx_qpio_post(
674 __in efx_txq_t *etp,
675 __in size_t pkt_length,
676 __in unsigned int completed,
677 __inout unsigned int *addedp);
678
679extern __checkReturn efx_rc_t
680ef10_tx_qdesc_post(
681 __in efx_txq_t *etp,
682 __in_ecount(n) efx_desc_t *ed,
683 __in unsigned int n,
684 __in unsigned int completed,
685 __inout unsigned int *addedp);
686
687extern void
688ef10_tx_qdesc_dma_create(
689 __in efx_txq_t *etp,
690 __in efsys_dma_addr_t addr,
691 __in size_t size,
692 __in boolean_t eop,
693 __out efx_desc_t *edp);
694
695extern void
696hunt_tx_qdesc_tso_create(
697 __in efx_txq_t *etp,
698 __in uint16_t ipv4_id,
699 __in uint32_t tcp_seq,
700 __in uint8_t tcp_flags,
701 __out efx_desc_t *edp);
702
703extern void
704ef10_tx_qdesc_vlantci_create(
705 __in efx_txq_t *etp,
706 __in uint16_t vlan_tci,
707 __out efx_desc_t *edp);
708
709
710#if EFSYS_OPT_QSTATS
711
712extern void
713ef10_tx_qstats_update(
714 __in efx_txq_t *etp,
715 __inout_ecount(TX_NQSTATS) efsys_stat_t *stat);
716
717#endif /* EFSYS_OPT_QSTATS */
718
719/* PIO */
720
721/* Missing register definitions */
722#ifndef ER_DZ_TX_PIOBUF_OFST
723#define ER_DZ_TX_PIOBUF_OFST 0x00001000
724#endif
725#ifndef ER_DZ_TX_PIOBUF_STEP
726#define ER_DZ_TX_PIOBUF_STEP 8192
727#endif
728#ifndef ER_DZ_TX_PIOBUF_ROWS
729#define ER_DZ_TX_PIOBUF_ROWS 2048
730#endif
731
732#ifndef ER_DZ_TX_PIOBUF_SIZE
733#define ER_DZ_TX_PIOBUF_SIZE 2048
734#endif
735
736#define HUNT_PIOBUF_NBUFS (16)
737#define HUNT_PIOBUF_SIZE (ER_DZ_TX_PIOBUF_SIZE)
738
739#define HUNT_MIN_PIO_ALLOC_SIZE (HUNT_PIOBUF_SIZE / 32)
740
741#define HUNT_LEGACY_PF_PRIVILEGE_MASK \
742 (MC_CMD_PRIVILEGE_MASK_IN_GRP_ADMIN | \
743 MC_CMD_PRIVILEGE_MASK_IN_GRP_LINK | \
744 MC_CMD_PRIVILEGE_MASK_IN_GRP_ONLOAD | \
745 MC_CMD_PRIVILEGE_MASK_IN_GRP_PTP | \
746 MC_CMD_PRIVILEGE_MASK_IN_GRP_INSECURE_FILTERS | \
747 MC_CMD_PRIVILEGE_MASK_IN_GRP_MAC_SPOOFING | \
748 MC_CMD_PRIVILEGE_MASK_IN_GRP_UNICAST | \
749 MC_CMD_PRIVILEGE_MASK_IN_GRP_MULTICAST | \
750 MC_CMD_PRIVILEGE_MASK_IN_GRP_BROADCAST | \
751 MC_CMD_PRIVILEGE_MASK_IN_GRP_ALL_MULTICAST | \
752 MC_CMD_PRIVILEGE_MASK_IN_GRP_PROMISCUOUS)
753
754#define HUNT_LEGACY_VF_PRIVILEGE_MASK 0
755
756typedef uint32_t efx_piobuf_handle_t;
757
758#define EFX_PIOBUF_HANDLE_INVALID ((efx_piobuf_handle_t) -1)
759
760extern __checkReturn efx_rc_t
761ef10_nic_pio_alloc(
762 __inout efx_nic_t *enp,
763 __out uint32_t *bufnump,
764 __out efx_piobuf_handle_t *handlep,
765 __out uint32_t *blknump,
766 __out uint32_t *offsetp,
767 __out size_t *sizep);
768
769extern __checkReturn efx_rc_t
770ef10_nic_pio_free(
771 __inout efx_nic_t *enp,
772 __in uint32_t bufnum,
773 __in uint32_t blknum);
774
775extern __checkReturn efx_rc_t
776ef10_nic_pio_link(
777 __inout efx_nic_t *enp,
778 __in uint32_t vi_index,
779 __in efx_piobuf_handle_t handle);
780
781extern __checkReturn efx_rc_t
782ef10_nic_pio_unlink(
783 __inout efx_nic_t *enp,
784 __in uint32_t vi_index);
785
786
787/* VPD */
788
789#if EFSYS_OPT_VPD
790
791extern __checkReturn efx_rc_t
792ef10_vpd_init(
793 __in efx_nic_t *enp);
794
795extern __checkReturn efx_rc_t
796ef10_vpd_size(
797 __in efx_nic_t *enp,
798 __out size_t *sizep);
799
800extern __checkReturn efx_rc_t
801ef10_vpd_read(
802 __in efx_nic_t *enp,
803 __out_bcount(size) caddr_t data,
804 __in size_t size);
805
806extern __checkReturn efx_rc_t
807ef10_vpd_verify(
808 __in efx_nic_t *enp,
809 __in_bcount(size) caddr_t data,
810 __in size_t size);
811
812extern __checkReturn efx_rc_t
813ef10_vpd_reinit(
814 __in efx_nic_t *enp,
815 __in_bcount(size) caddr_t data,
816 __in size_t size);
817
818extern __checkReturn efx_rc_t
819ef10_vpd_get(
820 __in efx_nic_t *enp,
821 __in_bcount(size) caddr_t data,
822 __in size_t size,
823 __inout efx_vpd_value_t *evvp);
824
825extern __checkReturn efx_rc_t
826ef10_vpd_set(
827 __in efx_nic_t *enp,
828 __in_bcount(size) caddr_t data,
829 __in size_t size,
830 __in efx_vpd_value_t *evvp);
831
832extern __checkReturn efx_rc_t
833ef10_vpd_next(
834 __in efx_nic_t *enp,
835 __in_bcount(size) caddr_t data,
836 __in size_t size,
837 __out efx_vpd_value_t *evvp,
838 __inout unsigned int *contp);
839
840extern __checkReturn efx_rc_t
841ef10_vpd_write(
842 __in efx_nic_t *enp,
843 __in_bcount(size) caddr_t data,
844 __in size_t size);
845
846extern void
847ef10_vpd_fini(
848 __in efx_nic_t *enp);
849
850#endif /* EFSYS_OPT_VPD */
851
852
853/* RX */
854
855extern __checkReturn efx_rc_t
856ef10_rx_init(
857 __in efx_nic_t *enp);
858
859#if EFSYS_OPT_RX_SCATTER
860extern __checkReturn efx_rc_t
861ef10_rx_scatter_enable(
862 __in efx_nic_t *enp,
863 __in unsigned int buf_size);
864#endif /* EFSYS_OPT_RX_SCATTER */
865
866
867#if EFSYS_OPT_RX_SCALE
868
869extern __checkReturn efx_rc_t
870ef10_rx_scale_mode_set(
871 __in efx_nic_t *enp,
872 __in efx_rx_hash_alg_t alg,
873 __in efx_rx_hash_type_t type,
874 __in boolean_t insert);
875
876extern __checkReturn efx_rc_t
877ef10_rx_scale_key_set(
878 __in efx_nic_t *enp,
879 __in_ecount(n) uint8_t *key,
880 __in size_t n);
881
882extern __checkReturn efx_rc_t
883ef10_rx_scale_tbl_set(
884 __in efx_nic_t *enp,
885 __in_ecount(n) unsigned int *table,
886 __in size_t n);
887
888extern __checkReturn uint32_t
889ef10_rx_prefix_hash(
890 __in efx_nic_t *enp,
891 __in efx_rx_hash_alg_t func,
892 __in uint8_t *buffer);
893
894#endif /* EFSYS_OPT_RX_SCALE */
895
894extern __checkReturn efx_rc_t
895ef10_rx_prefix_pktlen(
896 __in efx_nic_t *enp,
897 __in uint8_t *buffer,
898 __out uint16_t *lengthp);
899
896extern __checkReturn efx_rc_t
897ef10_rx_prefix_pktlen(
898 __in efx_nic_t *enp,
899 __in uint8_t *buffer,
900 __out uint16_t *lengthp);
901
900#endif /* EFSYS_OPT_RX_SCALE */
901
902extern void
903ef10_rx_qpost(
904 __in efx_rxq_t *erp,
905 __in_ecount(n) efsys_dma_addr_t *addrp,
906 __in size_t size,
907 __in unsigned int n,
908 __in unsigned int completed,
909 __in unsigned int added);
910
911extern void
912ef10_rx_qpush(
913 __in efx_rxq_t *erp,
914 __in unsigned int added,
915 __inout unsigned int *pushedp);
916
917extern __checkReturn efx_rc_t
918ef10_rx_qflush(
919 __in efx_rxq_t *erp);
920
921extern void
922ef10_rx_qenable(
923 __in efx_rxq_t *erp);
924
925extern __checkReturn efx_rc_t
926ef10_rx_qcreate(
927 __in efx_nic_t *enp,
928 __in unsigned int index,
929 __in unsigned int label,
930 __in efx_rxq_type_t type,
931 __in efsys_mem_t *esmp,
932 __in size_t n,
933 __in uint32_t id,
934 __in efx_evq_t *eep,
935 __in efx_rxq_t *erp);
936
937extern void
938ef10_rx_qdestroy(
939 __in efx_rxq_t *erp);
940
941extern void
942ef10_rx_fini(
943 __in efx_nic_t *enp);
944
945#if EFSYS_OPT_FILTER
946
947typedef struct ef10_filter_handle_s {
948 uint32_t efh_lo;
949 uint32_t efh_hi;
950} ef10_filter_handle_t;
951
952typedef struct ef10_filter_entry_s {
953 uintptr_t efe_spec; /* pointer to filter spec plus busy bit */
954 ef10_filter_handle_t efe_handle;
955} ef10_filter_entry_t;
956
957/*
958 * BUSY flag indicates that an update is in progress.
959 * AUTO_OLD flag is used to mark and sweep MAC packet filters.
960 */
961#define EFX_EF10_FILTER_FLAG_BUSY 1U
962#define EFX_EF10_FILTER_FLAG_AUTO_OLD 2U
963#define EFX_EF10_FILTER_FLAGS 3U
964
965/*
966 * Size of the hash table used by the driver. Doesn't need to be the
967 * same size as the hardware's table.
968 */
969#define EFX_EF10_FILTER_TBL_ROWS 8192
970
971/* Allow for the broadcast address to be added to the multicast list */
972#define EFX_EF10_FILTER_MULTICAST_FILTERS_MAX (EFX_MAC_MULTICAST_LIST_MAX + 1)
973
974typedef struct ef10_filter_table_s {
975 ef10_filter_entry_t eft_entry[EFX_EF10_FILTER_TBL_ROWS];
976 efx_rxq_t * eft_default_rxq;
977 boolean_t eft_using_rss;
978 uint32_t eft_unicst_filter_index;
979 boolean_t eft_unicst_filter_set;
980 uint32_t eft_mulcst_filter_indexes[
981 EFX_EF10_FILTER_MULTICAST_FILTERS_MAX];
982 uint32_t eft_mulcst_filter_count;
983} ef10_filter_table_t;
984
985 __checkReturn efx_rc_t
986ef10_filter_init(
987 __in efx_nic_t *enp);
988
989 void
990ef10_filter_fini(
991 __in efx_nic_t *enp);
992
993 __checkReturn efx_rc_t
994ef10_filter_restore(
995 __in efx_nic_t *enp);
996
997 __checkReturn efx_rc_t
998ef10_filter_add(
999 __in efx_nic_t *enp,
1000 __inout efx_filter_spec_t *spec,
1001 __in boolean_t may_replace);
1002
1003 __checkReturn efx_rc_t
1004ef10_filter_delete(
1005 __in efx_nic_t *enp,
1006 __inout efx_filter_spec_t *spec);
1007
1008extern __checkReturn efx_rc_t
1009ef10_filter_supported_filters(
1010 __in efx_nic_t *enp,
1011 __out uint32_t *list,
1012 __out size_t *length);
1013
1014extern __checkReturn efx_rc_t
1015ef10_filter_reconfigure(
1016 __in efx_nic_t *enp,
1017 __in_ecount(6) uint8_t const *mac_addr,
1018 __in boolean_t all_unicst,
1019 __in boolean_t mulcst,
1020 __in boolean_t all_mulcst,
1021 __in boolean_t brdcst,
1022 __in_ecount(6*count) uint8_t const *addrs,
1023 __in int count);
1024
1025extern void
1026ef10_filter_get_default_rxq(
1027 __in efx_nic_t *enp,
1028 __out efx_rxq_t **erpp,
1029 __out boolean_t *using_rss);
1030
1031extern void
1032ef10_filter_default_rxq_set(
1033 __in efx_nic_t *enp,
1034 __in efx_rxq_t *erp,
1035 __in boolean_t using_rss);
1036
1037extern void
1038ef10_filter_default_rxq_clear(
1039 __in efx_nic_t *enp);
1040
1041
1042#endif /* EFSYS_OPT_FILTER */
1043
1044extern __checkReturn efx_rc_t
1045efx_mcdi_get_function_info(
1046 __in efx_nic_t *enp,
1047 __out uint32_t *pfp,
1048 __out_opt uint32_t *vfp);
1049
1050extern __checkReturn efx_rc_t
1051efx_mcdi_privilege_mask(
1052 __in efx_nic_t *enp,
1053 __in uint32_t pf,
1054 __in uint32_t vf,
1055 __out uint32_t *maskp);
1056
1057#ifdef __cplusplus
1058}
1059#endif
1060
1061#endif /* _SYS_HUNT_IMPL_H */
902extern void
903ef10_rx_qpost(
904 __in efx_rxq_t *erp,
905 __in_ecount(n) efsys_dma_addr_t *addrp,
906 __in size_t size,
907 __in unsigned int n,
908 __in unsigned int completed,
909 __in unsigned int added);
910
911extern void
912ef10_rx_qpush(
913 __in efx_rxq_t *erp,
914 __in unsigned int added,
915 __inout unsigned int *pushedp);
916
917extern __checkReturn efx_rc_t
918ef10_rx_qflush(
919 __in efx_rxq_t *erp);
920
921extern void
922ef10_rx_qenable(
923 __in efx_rxq_t *erp);
924
925extern __checkReturn efx_rc_t
926ef10_rx_qcreate(
927 __in efx_nic_t *enp,
928 __in unsigned int index,
929 __in unsigned int label,
930 __in efx_rxq_type_t type,
931 __in efsys_mem_t *esmp,
932 __in size_t n,
933 __in uint32_t id,
934 __in efx_evq_t *eep,
935 __in efx_rxq_t *erp);
936
937extern void
938ef10_rx_qdestroy(
939 __in efx_rxq_t *erp);
940
941extern void
942ef10_rx_fini(
943 __in efx_nic_t *enp);
944
945#if EFSYS_OPT_FILTER
946
947typedef struct ef10_filter_handle_s {
948 uint32_t efh_lo;
949 uint32_t efh_hi;
950} ef10_filter_handle_t;
951
952typedef struct ef10_filter_entry_s {
953 uintptr_t efe_spec; /* pointer to filter spec plus busy bit */
954 ef10_filter_handle_t efe_handle;
955} ef10_filter_entry_t;
956
957/*
958 * BUSY flag indicates that an update is in progress.
959 * AUTO_OLD flag is used to mark and sweep MAC packet filters.
960 */
961#define EFX_EF10_FILTER_FLAG_BUSY 1U
962#define EFX_EF10_FILTER_FLAG_AUTO_OLD 2U
963#define EFX_EF10_FILTER_FLAGS 3U
964
965/*
966 * Size of the hash table used by the driver. Doesn't need to be the
967 * same size as the hardware's table.
968 */
969#define EFX_EF10_FILTER_TBL_ROWS 8192
970
971/* Allow for the broadcast address to be added to the multicast list */
972#define EFX_EF10_FILTER_MULTICAST_FILTERS_MAX (EFX_MAC_MULTICAST_LIST_MAX + 1)
973
974typedef struct ef10_filter_table_s {
975 ef10_filter_entry_t eft_entry[EFX_EF10_FILTER_TBL_ROWS];
976 efx_rxq_t * eft_default_rxq;
977 boolean_t eft_using_rss;
978 uint32_t eft_unicst_filter_index;
979 boolean_t eft_unicst_filter_set;
980 uint32_t eft_mulcst_filter_indexes[
981 EFX_EF10_FILTER_MULTICAST_FILTERS_MAX];
982 uint32_t eft_mulcst_filter_count;
983} ef10_filter_table_t;
984
985 __checkReturn efx_rc_t
986ef10_filter_init(
987 __in efx_nic_t *enp);
988
989 void
990ef10_filter_fini(
991 __in efx_nic_t *enp);
992
993 __checkReturn efx_rc_t
994ef10_filter_restore(
995 __in efx_nic_t *enp);
996
997 __checkReturn efx_rc_t
998ef10_filter_add(
999 __in efx_nic_t *enp,
1000 __inout efx_filter_spec_t *spec,
1001 __in boolean_t may_replace);
1002
1003 __checkReturn efx_rc_t
1004ef10_filter_delete(
1005 __in efx_nic_t *enp,
1006 __inout efx_filter_spec_t *spec);
1007
1008extern __checkReturn efx_rc_t
1009ef10_filter_supported_filters(
1010 __in efx_nic_t *enp,
1011 __out uint32_t *list,
1012 __out size_t *length);
1013
1014extern __checkReturn efx_rc_t
1015ef10_filter_reconfigure(
1016 __in efx_nic_t *enp,
1017 __in_ecount(6) uint8_t const *mac_addr,
1018 __in boolean_t all_unicst,
1019 __in boolean_t mulcst,
1020 __in boolean_t all_mulcst,
1021 __in boolean_t brdcst,
1022 __in_ecount(6*count) uint8_t const *addrs,
1023 __in int count);
1024
1025extern void
1026ef10_filter_get_default_rxq(
1027 __in efx_nic_t *enp,
1028 __out efx_rxq_t **erpp,
1029 __out boolean_t *using_rss);
1030
1031extern void
1032ef10_filter_default_rxq_set(
1033 __in efx_nic_t *enp,
1034 __in efx_rxq_t *erp,
1035 __in boolean_t using_rss);
1036
1037extern void
1038ef10_filter_default_rxq_clear(
1039 __in efx_nic_t *enp);
1040
1041
1042#endif /* EFSYS_OPT_FILTER */
1043
1044extern __checkReturn efx_rc_t
1045efx_mcdi_get_function_info(
1046 __in efx_nic_t *enp,
1047 __out uint32_t *pfp,
1048 __out_opt uint32_t *vfp);
1049
1050extern __checkReturn efx_rc_t
1051efx_mcdi_privilege_mask(
1052 __in efx_nic_t *enp,
1053 __in uint32_t pf,
1054 __in uint32_t vf,
1055 __out uint32_t *maskp);
1056
1057#ifdef __cplusplus
1058}
1059#endif
1060
1061#endif /* _SYS_HUNT_IMPL_H */