40#if EFSYS_OPT_MAC_FALCON_XMAC
41#include "falcon_xmac.h"
42#endif
43
44#if EFSYS_OPT_MAC_FALCON_GMAC
45#include "falcon_gmac.h"
46#endif
47
48#if EFSYS_OPT_PHY_NULL
49#include "nullphy.h"
50#endif
51
52#if EFSYS_OPT_PHY_QT2022C2
53#include "qt2022c2.h"
54#endif
55
56#if EFSYS_OPT_PHY_SFX7101
57#include "sfx7101.h"
58#endif
59
60#if EFSYS_OPT_PHY_TXC43128
61#include "txc43128.h"
62#endif
63
64#if EFSYS_OPT_PHY_SFT9001
65#include "sft9001.h"
66#endif
67
68#if EFSYS_OPT_PHY_QT2025C
69#include "qt2025c.h"
70#endif
71
72#if EFSYS_OPT_PHY_NULL
73static efx_phy_ops_t __efx_phy_null_ops = {
74 NULL, /* epo_power */
75 nullphy_reset, /* epo_reset */
76 nullphy_reconfigure, /* epo_reconfigure */
77 nullphy_verify, /* epo_verify */
78 NULL, /* epo_uplink_check */
79 nullphy_downlink_check, /* epo_downlink_check */
80 nullphy_oui_get, /* epo_oui_get */
81#if EFSYS_OPT_PHY_STATS
82 nullphy_stats_update, /* epo_stats_update */
83#endif /* EFSYS_OPT_PHY_STATS */
84#if EFSYS_OPT_PHY_PROPS
85#if EFSYS_OPT_NAMES
86 nullphy_prop_name, /* epo_prop_name */
87#endif
88 nullphy_prop_get, /* epo_prop_get */
89 nullphy_prop_set, /* epo_prop_set */
90#endif /* EFSYS_OPT_PHY_PROPS */
91#if EFSYS_OPT_BIST
92 NULL, /* epo_bist_enable_offline */
93 NULL, /* epo_bist_start */
94 NULL, /* epo_bist_poll */
95 NULL, /* epo_bist_stop */
96#endif /* EFSYS_OPT_BIST */
97};
98#endif /* EFSYS_OPT_PHY_NULL */
99
100#if EFSYS_OPT_PHY_QT2022C2
101static efx_phy_ops_t __efx_phy_qt2022c2_ops = {
102 NULL, /* epo_power */
103 qt2022c2_reset, /* epo_reset */
104 qt2022c2_reconfigure, /* epo_reconfigure */
105 qt2022c2_verify, /* epo_verify */
106 qt2022c2_uplink_check, /* epo_uplink_check */
107 qt2022c2_downlink_check, /* epo_downlink_check */
108 qt2022c2_oui_get, /* epo_oui_get */
109#if EFSYS_OPT_PHY_STATS
110 qt2022c2_stats_update, /* epo_stats_update */
111#endif /* EFSYS_OPT_PHY_STATS */
112#if EFSYS_OPT_PHY_PROPS
113#if EFSYS_OPT_NAMES
114 qt2022c2_prop_name, /* epo_prop_name */
115#endif
116 qt2022c2_prop_get, /* epo_prop_get */
117 qt2022c2_prop_set, /* epo_prop_set */
118#endif /* EFSYS_OPT_PHY_PROPS */
119#if EFSYS_OPT_BIST
120 NULL, /* epo_bist_enable_offline */
121 NULL, /* epo_bist_start */
122 NULL, /* epo_bist_poll */
123 NULL, /* epo_bist_stop */
124#endif /* EFSYS_OPT_BIST */
125};
126#endif /* EFSYS_OPT_PHY_QT2022C2 */
127
128#if EFSYS_OPT_PHY_SFX7101
129static efx_phy_ops_t __efx_phy_sfx7101_ops = {
130 sfx7101_power, /* epo_power */
131 sfx7101_reset, /* epo_reset */
132 sfx7101_reconfigure, /* epo_reconfigure */
133 sfx7101_verify, /* epo_verify */
134 sfx7101_uplink_check, /* epo_uplink_check */
135 sfx7101_downlink_check, /* epo_downlink_check */
136 sfx7101_oui_get, /* epo_oui_get */
137#if EFSYS_OPT_PHY_STATS
138 sfx7101_stats_update, /* epo_stats_update */
139#endif /* EFSYS_OPT_PHY_STATS */
140#if EFSYS_OPT_PHY_PROPS
141#if EFSYS_OPT_NAMES
142 sfx7101_prop_name, /* epo_prop_name */
143#endif
144 sfx7101_prop_get, /* epo_prop_get */
145 sfx7101_prop_set, /* epo_prop_set */
146#endif /* EFSYS_OPT_PHY_PROPS */
147#if EFSYS_OPT_BIST
148 NULL, /* epo_bist_enable_offline */
149 NULL, /* epo_bist_start */
150 NULL, /* epo_bist_poll */
151 NULL, /* epo_bist_stop */
152#endif /* EFSYS_OPT_BIST */
153};
154#endif /* EFSYS_OPT_PHY_SFX7101 */
155
156#if EFSYS_OPT_PHY_TXC43128
157static efx_phy_ops_t __efx_phy_txc43128_ops = {
158 NULL, /* epo_power */
159 txc43128_reset, /* epo_reset */
160 txc43128_reconfigure, /* epo_reconfigure */
161 txc43128_verify, /* epo_verify */
162 txc43128_uplink_check, /* epo_uplink_check */
163 txc43128_downlink_check, /* epo_downlink_check */
164 txc43128_oui_get, /* epo_oui_get */
165#if EFSYS_OPT_PHY_STATS
166 txc43128_stats_update, /* epo_stats_update */
167#endif /* EFSYS_OPT_PHY_STATS */
168#if EFSYS_OPT_PHY_PROPS
169#if EFSYS_OPT_NAMES
170 txc43128_prop_name, /* epo_prop_name */
171#endif
172 txc43128_prop_get, /* epo_prop_get */
173 txc43128_prop_set, /* epo_prop_set */
174#endif /* EFSYS_OPT_PHY_PROPS */
175#if EFSYS_OPT_BIST
176 NULL, /* epo_bist_enable_offline */
177 NULL, /* epo_bist_start */
178 NULL, /* epo_bist_poll */
179 NULL, /* epo_bist_stop */
180#endif /* EFSYS_OPT_BIST */
181};
182#endif /* EFSYS_OPT_PHY_TXC43128 */
183
184#if EFSYS_OPT_PHY_SFT9001
185static efx_phy_ops_t __efx_phy_sft9001_ops = {
186 NULL, /* epo_power */
187 sft9001_reset, /* epo_reset */
188 sft9001_reconfigure, /* epo_reconfigure */
189 sft9001_verify, /* epo_verify */
190 sft9001_uplink_check, /* epo_uplink_check */
191 sft9001_downlink_check, /* epo_downlink_check */
192 sft9001_oui_get, /* epo_oui_get */
193#if EFSYS_OPT_PHY_STATS
194 sft9001_stats_update, /* epo_stats_update */
195#endif /* EFSYS_OPT_PHY_STATS */
196#if EFSYS_OPT_PHY_PROPS
197#if EFSYS_OPT_NAMES
198 sft9001_prop_name, /* epo_prop_name */
199#endif
200 sft9001_prop_get, /* epo_prop_get */
201 sft9001_prop_set, /* epo_prop_set */
202#endif /* EFSYS_OPT_PHY_PROPS */
203#if EFSYS_OPT_BIST
204 NULL, /* epo_bist_enable_offline */
205 sft9001_bist_start, /* epo_bist_start */
206 sft9001_bist_poll, /* epo_bist_poll */
207 sft9001_bist_stop, /* epo_bist_stop */
208#endif /* EFSYS_OPT_BIST */
209};
210#endif /* EFSYS_OPT_PHY_SFT9001 */
211
212#if EFSYS_OPT_PHY_QT2025C
213static efx_phy_ops_t __efx_phy_qt2025c_ops = {
214 NULL, /* epo_power */
215 qt2025c_reset, /* epo_reset */
216 qt2025c_reconfigure, /* epo_reconfigure */
217 qt2025c_verify, /* epo_verify */
218 qt2025c_uplink_check, /* epo_uplink_check */
219 qt2025c_downlink_check, /* epo_downlink_check */
220 qt2025c_oui_get, /* epo_oui_get */
221#if EFSYS_OPT_PHY_STATS
222 qt2025c_stats_update, /* epo_stats_update */
223#endif /* EFSYS_OPT_PHY_STATS */
224#if EFSYS_OPT_PHY_PROPS
225#if EFSYS_OPT_NAMES
226 qt2025c_prop_name, /* epo_prop_name */
227#endif
228 qt2025c_prop_get, /* epo_prop_get */
229 qt2025c_prop_set, /* epo_prop_set */
230#endif /* EFSYS_OPT_PHY_PROPS */
231#if EFSYS_OPT_BIST
232 NULL, /* epo_bist_enable_offline */
233 NULL, /* epo_bist_start */
234 NULL, /* epo_bist_poll */
235 NULL, /* epo_bist_stop */
236#endif /* EFSYS_OPT_BIST */
237};
238#endif /* EFSYS_OPT_PHY_QT2025C */
239
240#if EFSYS_OPT_SIENA
241static efx_phy_ops_t __efx_phy_siena_ops = {
242 siena_phy_power, /* epo_power */
243 NULL, /* epo_reset */
244 siena_phy_reconfigure, /* epo_reconfigure */
245 siena_phy_verify, /* epo_verify */
246 NULL, /* epo_uplink_check */
247 NULL, /* epo_downlink_check */
248 siena_phy_oui_get, /* epo_oui_get */
249#if EFSYS_OPT_PHY_STATS
250 siena_phy_stats_update, /* epo_stats_update */
251#endif /* EFSYS_OPT_PHY_STATS */
252#if EFSYS_OPT_PHY_PROPS
253#if EFSYS_OPT_NAMES
254 siena_phy_prop_name, /* epo_prop_name */
255#endif
256 siena_phy_prop_get, /* epo_prop_get */
257 siena_phy_prop_set, /* epo_prop_set */
258#endif /* EFSYS_OPT_PHY_PROPS */
259#if EFSYS_OPT_BIST
260 NULL, /* epo_bist_enable_offline */
261 siena_phy_bist_start, /* epo_bist_start */
262 siena_phy_bist_poll, /* epo_bist_poll */
263 siena_phy_bist_stop, /* epo_bist_stop */
264#endif /* EFSYS_OPT_BIST */
265};
266#endif /* EFSYS_OPT_SIENA */
267
268#if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
269static efx_phy_ops_t __efx_phy_ef10_ops = {
270 ef10_phy_power, /* epo_power */
271 NULL, /* epo_reset */
272 ef10_phy_reconfigure, /* epo_reconfigure */
273 ef10_phy_verify, /* epo_verify */
274 NULL, /* epo_uplink_check */
275 NULL, /* epo_downlink_check */
276 ef10_phy_oui_get, /* epo_oui_get */
277#if EFSYS_OPT_PHY_STATS
278 ef10_phy_stats_update, /* epo_stats_update */
279#endif /* EFSYS_OPT_PHY_STATS */
280#if EFSYS_OPT_PHY_PROPS
281#if EFSYS_OPT_NAMES
282 ef10_phy_prop_name, /* epo_prop_name */
283#endif
284 ef10_phy_prop_get, /* epo_prop_get */
285 ef10_phy_prop_set, /* epo_prop_set */
286#endif /* EFSYS_OPT_PHY_PROPS */
287#if EFSYS_OPT_BIST
288 /* FIXME: Are these BIST methods appropriate for Medford? */
289 hunt_bist_enable_offline, /* epo_bist_enable_offline */
290 hunt_bist_start, /* epo_bist_start */
291 hunt_bist_poll, /* epo_bist_poll */
292 hunt_bist_stop, /* epo_bist_stop */
293#endif /* EFSYS_OPT_BIST */
294};
295#endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */
296
297 __checkReturn efx_rc_t
298efx_phy_probe(
299 __in efx_nic_t *enp)
300{
301 efx_port_t *epp = &(enp->en_port);
302 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
303 efx_phy_ops_t *epop;
304 efx_rc_t rc;
305
306 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
307
308 epp->ep_port = encp->enc_port;
309 epp->ep_phy_type = encp->enc_phy_type;
310
311 /* Hook in operations structure */
312 switch (enp->en_family) {
| 36#if EFSYS_OPT_MAC_FALCON_XMAC
37#include "falcon_xmac.h"
38#endif
39
40#if EFSYS_OPT_MAC_FALCON_GMAC
41#include "falcon_gmac.h"
42#endif
43
44#if EFSYS_OPT_PHY_NULL
45#include "nullphy.h"
46#endif
47
48#if EFSYS_OPT_PHY_QT2022C2
49#include "qt2022c2.h"
50#endif
51
52#if EFSYS_OPT_PHY_SFX7101
53#include "sfx7101.h"
54#endif
55
56#if EFSYS_OPT_PHY_TXC43128
57#include "txc43128.h"
58#endif
59
60#if EFSYS_OPT_PHY_SFT9001
61#include "sft9001.h"
62#endif
63
64#if EFSYS_OPT_PHY_QT2025C
65#include "qt2025c.h"
66#endif
67
68#if EFSYS_OPT_PHY_NULL
69static efx_phy_ops_t __efx_phy_null_ops = {
70 NULL, /* epo_power */
71 nullphy_reset, /* epo_reset */
72 nullphy_reconfigure, /* epo_reconfigure */
73 nullphy_verify, /* epo_verify */
74 NULL, /* epo_uplink_check */
75 nullphy_downlink_check, /* epo_downlink_check */
76 nullphy_oui_get, /* epo_oui_get */
77#if EFSYS_OPT_PHY_STATS
78 nullphy_stats_update, /* epo_stats_update */
79#endif /* EFSYS_OPT_PHY_STATS */
80#if EFSYS_OPT_PHY_PROPS
81#if EFSYS_OPT_NAMES
82 nullphy_prop_name, /* epo_prop_name */
83#endif
84 nullphy_prop_get, /* epo_prop_get */
85 nullphy_prop_set, /* epo_prop_set */
86#endif /* EFSYS_OPT_PHY_PROPS */
87#if EFSYS_OPT_BIST
88 NULL, /* epo_bist_enable_offline */
89 NULL, /* epo_bist_start */
90 NULL, /* epo_bist_poll */
91 NULL, /* epo_bist_stop */
92#endif /* EFSYS_OPT_BIST */
93};
94#endif /* EFSYS_OPT_PHY_NULL */
95
96#if EFSYS_OPT_PHY_QT2022C2
97static efx_phy_ops_t __efx_phy_qt2022c2_ops = {
98 NULL, /* epo_power */
99 qt2022c2_reset, /* epo_reset */
100 qt2022c2_reconfigure, /* epo_reconfigure */
101 qt2022c2_verify, /* epo_verify */
102 qt2022c2_uplink_check, /* epo_uplink_check */
103 qt2022c2_downlink_check, /* epo_downlink_check */
104 qt2022c2_oui_get, /* epo_oui_get */
105#if EFSYS_OPT_PHY_STATS
106 qt2022c2_stats_update, /* epo_stats_update */
107#endif /* EFSYS_OPT_PHY_STATS */
108#if EFSYS_OPT_PHY_PROPS
109#if EFSYS_OPT_NAMES
110 qt2022c2_prop_name, /* epo_prop_name */
111#endif
112 qt2022c2_prop_get, /* epo_prop_get */
113 qt2022c2_prop_set, /* epo_prop_set */
114#endif /* EFSYS_OPT_PHY_PROPS */
115#if EFSYS_OPT_BIST
116 NULL, /* epo_bist_enable_offline */
117 NULL, /* epo_bist_start */
118 NULL, /* epo_bist_poll */
119 NULL, /* epo_bist_stop */
120#endif /* EFSYS_OPT_BIST */
121};
122#endif /* EFSYS_OPT_PHY_QT2022C2 */
123
124#if EFSYS_OPT_PHY_SFX7101
125static efx_phy_ops_t __efx_phy_sfx7101_ops = {
126 sfx7101_power, /* epo_power */
127 sfx7101_reset, /* epo_reset */
128 sfx7101_reconfigure, /* epo_reconfigure */
129 sfx7101_verify, /* epo_verify */
130 sfx7101_uplink_check, /* epo_uplink_check */
131 sfx7101_downlink_check, /* epo_downlink_check */
132 sfx7101_oui_get, /* epo_oui_get */
133#if EFSYS_OPT_PHY_STATS
134 sfx7101_stats_update, /* epo_stats_update */
135#endif /* EFSYS_OPT_PHY_STATS */
136#if EFSYS_OPT_PHY_PROPS
137#if EFSYS_OPT_NAMES
138 sfx7101_prop_name, /* epo_prop_name */
139#endif
140 sfx7101_prop_get, /* epo_prop_get */
141 sfx7101_prop_set, /* epo_prop_set */
142#endif /* EFSYS_OPT_PHY_PROPS */
143#if EFSYS_OPT_BIST
144 NULL, /* epo_bist_enable_offline */
145 NULL, /* epo_bist_start */
146 NULL, /* epo_bist_poll */
147 NULL, /* epo_bist_stop */
148#endif /* EFSYS_OPT_BIST */
149};
150#endif /* EFSYS_OPT_PHY_SFX7101 */
151
152#if EFSYS_OPT_PHY_TXC43128
153static efx_phy_ops_t __efx_phy_txc43128_ops = {
154 NULL, /* epo_power */
155 txc43128_reset, /* epo_reset */
156 txc43128_reconfigure, /* epo_reconfigure */
157 txc43128_verify, /* epo_verify */
158 txc43128_uplink_check, /* epo_uplink_check */
159 txc43128_downlink_check, /* epo_downlink_check */
160 txc43128_oui_get, /* epo_oui_get */
161#if EFSYS_OPT_PHY_STATS
162 txc43128_stats_update, /* epo_stats_update */
163#endif /* EFSYS_OPT_PHY_STATS */
164#if EFSYS_OPT_PHY_PROPS
165#if EFSYS_OPT_NAMES
166 txc43128_prop_name, /* epo_prop_name */
167#endif
168 txc43128_prop_get, /* epo_prop_get */
169 txc43128_prop_set, /* epo_prop_set */
170#endif /* EFSYS_OPT_PHY_PROPS */
171#if EFSYS_OPT_BIST
172 NULL, /* epo_bist_enable_offline */
173 NULL, /* epo_bist_start */
174 NULL, /* epo_bist_poll */
175 NULL, /* epo_bist_stop */
176#endif /* EFSYS_OPT_BIST */
177};
178#endif /* EFSYS_OPT_PHY_TXC43128 */
179
180#if EFSYS_OPT_PHY_SFT9001
181static efx_phy_ops_t __efx_phy_sft9001_ops = {
182 NULL, /* epo_power */
183 sft9001_reset, /* epo_reset */
184 sft9001_reconfigure, /* epo_reconfigure */
185 sft9001_verify, /* epo_verify */
186 sft9001_uplink_check, /* epo_uplink_check */
187 sft9001_downlink_check, /* epo_downlink_check */
188 sft9001_oui_get, /* epo_oui_get */
189#if EFSYS_OPT_PHY_STATS
190 sft9001_stats_update, /* epo_stats_update */
191#endif /* EFSYS_OPT_PHY_STATS */
192#if EFSYS_OPT_PHY_PROPS
193#if EFSYS_OPT_NAMES
194 sft9001_prop_name, /* epo_prop_name */
195#endif
196 sft9001_prop_get, /* epo_prop_get */
197 sft9001_prop_set, /* epo_prop_set */
198#endif /* EFSYS_OPT_PHY_PROPS */
199#if EFSYS_OPT_BIST
200 NULL, /* epo_bist_enable_offline */
201 sft9001_bist_start, /* epo_bist_start */
202 sft9001_bist_poll, /* epo_bist_poll */
203 sft9001_bist_stop, /* epo_bist_stop */
204#endif /* EFSYS_OPT_BIST */
205};
206#endif /* EFSYS_OPT_PHY_SFT9001 */
207
208#if EFSYS_OPT_PHY_QT2025C
209static efx_phy_ops_t __efx_phy_qt2025c_ops = {
210 NULL, /* epo_power */
211 qt2025c_reset, /* epo_reset */
212 qt2025c_reconfigure, /* epo_reconfigure */
213 qt2025c_verify, /* epo_verify */
214 qt2025c_uplink_check, /* epo_uplink_check */
215 qt2025c_downlink_check, /* epo_downlink_check */
216 qt2025c_oui_get, /* epo_oui_get */
217#if EFSYS_OPT_PHY_STATS
218 qt2025c_stats_update, /* epo_stats_update */
219#endif /* EFSYS_OPT_PHY_STATS */
220#if EFSYS_OPT_PHY_PROPS
221#if EFSYS_OPT_NAMES
222 qt2025c_prop_name, /* epo_prop_name */
223#endif
224 qt2025c_prop_get, /* epo_prop_get */
225 qt2025c_prop_set, /* epo_prop_set */
226#endif /* EFSYS_OPT_PHY_PROPS */
227#if EFSYS_OPT_BIST
228 NULL, /* epo_bist_enable_offline */
229 NULL, /* epo_bist_start */
230 NULL, /* epo_bist_poll */
231 NULL, /* epo_bist_stop */
232#endif /* EFSYS_OPT_BIST */
233};
234#endif /* EFSYS_OPT_PHY_QT2025C */
235
236#if EFSYS_OPT_SIENA
237static efx_phy_ops_t __efx_phy_siena_ops = {
238 siena_phy_power, /* epo_power */
239 NULL, /* epo_reset */
240 siena_phy_reconfigure, /* epo_reconfigure */
241 siena_phy_verify, /* epo_verify */
242 NULL, /* epo_uplink_check */
243 NULL, /* epo_downlink_check */
244 siena_phy_oui_get, /* epo_oui_get */
245#if EFSYS_OPT_PHY_STATS
246 siena_phy_stats_update, /* epo_stats_update */
247#endif /* EFSYS_OPT_PHY_STATS */
248#if EFSYS_OPT_PHY_PROPS
249#if EFSYS_OPT_NAMES
250 siena_phy_prop_name, /* epo_prop_name */
251#endif
252 siena_phy_prop_get, /* epo_prop_get */
253 siena_phy_prop_set, /* epo_prop_set */
254#endif /* EFSYS_OPT_PHY_PROPS */
255#if EFSYS_OPT_BIST
256 NULL, /* epo_bist_enable_offline */
257 siena_phy_bist_start, /* epo_bist_start */
258 siena_phy_bist_poll, /* epo_bist_poll */
259 siena_phy_bist_stop, /* epo_bist_stop */
260#endif /* EFSYS_OPT_BIST */
261};
262#endif /* EFSYS_OPT_SIENA */
263
264#if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
265static efx_phy_ops_t __efx_phy_ef10_ops = {
266 ef10_phy_power, /* epo_power */
267 NULL, /* epo_reset */
268 ef10_phy_reconfigure, /* epo_reconfigure */
269 ef10_phy_verify, /* epo_verify */
270 NULL, /* epo_uplink_check */
271 NULL, /* epo_downlink_check */
272 ef10_phy_oui_get, /* epo_oui_get */
273#if EFSYS_OPT_PHY_STATS
274 ef10_phy_stats_update, /* epo_stats_update */
275#endif /* EFSYS_OPT_PHY_STATS */
276#if EFSYS_OPT_PHY_PROPS
277#if EFSYS_OPT_NAMES
278 ef10_phy_prop_name, /* epo_prop_name */
279#endif
280 ef10_phy_prop_get, /* epo_prop_get */
281 ef10_phy_prop_set, /* epo_prop_set */
282#endif /* EFSYS_OPT_PHY_PROPS */
283#if EFSYS_OPT_BIST
284 /* FIXME: Are these BIST methods appropriate for Medford? */
285 hunt_bist_enable_offline, /* epo_bist_enable_offline */
286 hunt_bist_start, /* epo_bist_start */
287 hunt_bist_poll, /* epo_bist_poll */
288 hunt_bist_stop, /* epo_bist_stop */
289#endif /* EFSYS_OPT_BIST */
290};
291#endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */
292
293 __checkReturn efx_rc_t
294efx_phy_probe(
295 __in efx_nic_t *enp)
296{
297 efx_port_t *epp = &(enp->en_port);
298 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
299 efx_phy_ops_t *epop;
300 efx_rc_t rc;
301
302 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
303
304 epp->ep_port = encp->enc_port;
305 epp->ep_phy_type = encp->enc_phy_type;
306
307 /* Hook in operations structure */
308 switch (enp->en_family) {
|
353#if EFSYS_OPT_SIENA
354 case EFX_FAMILY_SIENA:
355 epop = (efx_phy_ops_t *)&__efx_phy_siena_ops;
356 break;
357#endif /* EFSYS_OPT_SIENA */
358#if EFSYS_OPT_HUNTINGTON
359 case EFX_FAMILY_HUNTINGTON:
360 epop = (efx_phy_ops_t *)&__efx_phy_ef10_ops;
361 break;
362#endif /* EFSYS_OPT_HUNTINGTON */
363#if EFSYS_OPT_MEDFORD
364 case EFX_FAMILY_MEDFORD:
365 epop = (efx_phy_ops_t *)&__efx_phy_ef10_ops;
366 break;
367#endif /* EFSYS_OPT_MEDFORD */
368 default:
369 rc = ENOTSUP;
370 goto fail1;
371 }
372
373 epp->ep_epop = epop;
374
375 return (0);
376
377fail1:
378 EFSYS_PROBE1(fail1, efx_rc_t, rc);
379
380 epp->ep_port = 0;
381 epp->ep_phy_type = 0;
382
383 return (rc);
384}
385
386 __checkReturn efx_rc_t
387efx_phy_verify(
388 __in efx_nic_t *enp)
389{
390 efx_port_t *epp = &(enp->en_port);
391 efx_phy_ops_t *epop = epp->ep_epop;
392
393 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
394 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
395
396 return (epop->epo_verify(enp));
397}
398
399#if EFSYS_OPT_PHY_LED_CONTROL
400
401 __checkReturn efx_rc_t
402efx_phy_led_set(
403 __in efx_nic_t *enp,
404 __in efx_phy_led_mode_t mode)
405{
406 efx_nic_cfg_t *encp = (&enp->en_nic_cfg);
407 efx_port_t *epp = &(enp->en_port);
408 efx_phy_ops_t *epop = epp->ep_epop;
409 uint32_t mask;
410 efx_rc_t rc;
411
412 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
413 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
414
415 if (epp->ep_phy_led_mode == mode)
416 goto done;
417
418 mask = (1 << EFX_PHY_LED_DEFAULT);
419 mask |= encp->enc_led_mask;
420
421 if (!((1 << mode) & mask)) {
422 rc = ENOTSUP;
423 goto fail1;
424 }
425
426 EFSYS_ASSERT3U(mode, <, EFX_PHY_LED_NMODES);
427 epp->ep_phy_led_mode = mode;
428
429 if ((rc = epop->epo_reconfigure(enp)) != 0)
430 goto fail2;
431
432done:
433 return (0);
434
435fail2:
436 EFSYS_PROBE(fail2);
437fail1:
438 EFSYS_PROBE1(fail1, efx_rc_t, rc);
439
440 return (rc);
441}
442#endif /* EFSYS_OPT_PHY_LED_CONTROL */
443
444 void
445efx_phy_adv_cap_get(
446 __in efx_nic_t *enp,
447 __in uint32_t flag,
448 __out uint32_t *maskp)
449{
450 efx_port_t *epp = &(enp->en_port);
451
452 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
453 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
454
455 switch (flag) {
456 case EFX_PHY_CAP_CURRENT:
457 *maskp = epp->ep_adv_cap_mask;
458 break;
459 case EFX_PHY_CAP_DEFAULT:
460 *maskp = epp->ep_default_adv_cap_mask;
461 break;
462 case EFX_PHY_CAP_PERM:
463 *maskp = epp->ep_phy_cap_mask;
464 break;
465 default:
466 EFSYS_ASSERT(B_FALSE);
467 break;
468 }
469}
470
471 __checkReturn efx_rc_t
472efx_phy_adv_cap_set(
473 __in efx_nic_t *enp,
474 __in uint32_t mask)
475{
476 efx_port_t *epp = &(enp->en_port);
477 efx_phy_ops_t *epop = epp->ep_epop;
478 uint32_t old_mask;
479 efx_rc_t rc;
480
481 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
482 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
483
484 if ((mask & ~epp->ep_phy_cap_mask) != 0) {
485 rc = ENOTSUP;
486 goto fail1;
487 }
488
489 if (epp->ep_adv_cap_mask == mask)
490 goto done;
491
492 old_mask = epp->ep_adv_cap_mask;
493 epp->ep_adv_cap_mask = mask;
494
495 if ((rc = epop->epo_reconfigure(enp)) != 0)
496 goto fail2;
497
498done:
499 return (0);
500
501fail2:
502 EFSYS_PROBE(fail2);
503
504 epp->ep_adv_cap_mask = old_mask;
505 /* Reconfigure for robustness */
506 if (epop->epo_reconfigure(enp) != 0) {
507 /*
508 * We may have an inconsistent view of our advertised speed
509 * capabilities.
510 */
511 EFSYS_ASSERT(0);
512 }
513
514fail1:
515 EFSYS_PROBE1(fail1, efx_rc_t, rc);
516
517 return (rc);
518}
519
520 void
521efx_phy_lp_cap_get(
522 __in efx_nic_t *enp,
523 __out uint32_t *maskp)
524{
525 efx_port_t *epp = &(enp->en_port);
526
527 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
528 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
529
530 *maskp = epp->ep_lp_cap_mask;
531}
532
533 __checkReturn efx_rc_t
534efx_phy_oui_get(
535 __in efx_nic_t *enp,
536 __out uint32_t *ouip)
537{
538 efx_port_t *epp = &(enp->en_port);
539 efx_phy_ops_t *epop = epp->ep_epop;
540
541 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
542 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
543
544 return (epop->epo_oui_get(enp, ouip));
545}
546
547 void
548efx_phy_media_type_get(
549 __in efx_nic_t *enp,
550 __out efx_phy_media_type_t *typep)
551{
552 efx_port_t *epp = &(enp->en_port);
553
554 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
555 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
556
557 if (epp->ep_module_type != EFX_PHY_MEDIA_INVALID)
558 *typep = epp->ep_module_type;
559 else
560 *typep = epp->ep_fixed_port_type;
561}
562
563 __checkReturn efx_rc_t
564efx_phy_module_get_info(
565 __in efx_nic_t *enp,
566 __in uint8_t dev_addr,
567 __in uint8_t offset,
568 __in uint8_t len,
569 __out_bcount(len) uint8_t *data)
570{
571 efx_rc_t rc;
572
573 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
574 EFSYS_ASSERT(data != NULL);
575
576 if ((uint32_t)offset + len > 0xff) {
577 rc = EINVAL;
578 goto fail1;
579 }
580
581 if ((rc = efx_mcdi_phy_module_get_info(enp, dev_addr,
582 offset, len, data)) != 0)
583 goto fail2;
584
585 return (0);
586
587fail2:
588 EFSYS_PROBE(fail2);
589fail1:
590 EFSYS_PROBE1(fail1, efx_rc_t, rc);
591
592 return (rc);
593}
594
595#if EFSYS_OPT_PHY_STATS
596
597#if EFSYS_OPT_NAMES
598
599/* START MKCONFIG GENERATED PhyStatNamesBlock d5f79b4bc2c050fe */
600static const char *__efx_phy_stat_name[] = {
601 "oui",
602 "pma_pmd_link_up",
603 "pma_pmd_rx_fault",
604 "pma_pmd_tx_fault",
605 "pma_pmd_rev_a",
606 "pma_pmd_rev_b",
607 "pma_pmd_rev_c",
608 "pma_pmd_rev_d",
609 "pcs_link_up",
610 "pcs_rx_fault",
611 "pcs_tx_fault",
612 "pcs_ber",
613 "pcs_block_errors",
614 "phy_xs_link_up",
615 "phy_xs_rx_fault",
616 "phy_xs_tx_fault",
617 "phy_xs_align",
618 "phy_xs_sync_a",
619 "phy_xs_sync_b",
620 "phy_xs_sync_c",
621 "phy_xs_sync_d",
622 "an_link_up",
623 "an_master",
624 "an_local_rx_ok",
625 "an_remote_rx_ok",
626 "cl22ext_link_up",
627 "snr_a",
628 "snr_b",
629 "snr_c",
630 "snr_d",
631 "pma_pmd_signal_a",
632 "pma_pmd_signal_b",
633 "pma_pmd_signal_c",
634 "pma_pmd_signal_d",
635 "an_complete",
636 "pma_pmd_rev_major",
637 "pma_pmd_rev_minor",
638 "pma_pmd_rev_micro",
639 "pcs_fw_version_0",
640 "pcs_fw_version_1",
641 "pcs_fw_version_2",
642 "pcs_fw_version_3",
643 "pcs_fw_build_yy",
644 "pcs_fw_build_mm",
645 "pcs_fw_build_dd",
646 "pcs_op_mode",
647};
648
649/* END MKCONFIG GENERATED PhyStatNamesBlock */
650
651 const char *
652efx_phy_stat_name(
653 __in efx_nic_t *enp,
654 __in efx_phy_stat_t type)
655{
656 _NOTE(ARGUNUSED(enp))
657 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
658 EFSYS_ASSERT3U(type, <, EFX_PHY_NSTATS);
659
660 return (__efx_phy_stat_name[type]);
661}
662
663#endif /* EFSYS_OPT_NAMES */
664
665 __checkReturn efx_rc_t
666efx_phy_stats_update(
667 __in efx_nic_t *enp,
668 __in efsys_mem_t *esmp,
669 __inout_ecount(EFX_PHY_NSTATS) uint32_t *stat)
670{
671 efx_port_t *epp = &(enp->en_port);
672 efx_phy_ops_t *epop = epp->ep_epop;
673
674 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
675 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
676
677 return (epop->epo_stats_update(enp, esmp, stat));
678}
679
680#endif /* EFSYS_OPT_PHY_STATS */
681
682#if EFSYS_OPT_PHY_PROPS
683
684#if EFSYS_OPT_NAMES
685 const char *
686efx_phy_prop_name(
687 __in efx_nic_t *enp,
688 __in unsigned int id)
689{
690 efx_port_t *epp = &(enp->en_port);
691 efx_phy_ops_t *epop = epp->ep_epop;
692
693 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
694 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
695
696 return (epop->epo_prop_name(enp, id));
697}
698#endif /* EFSYS_OPT_NAMES */
699
700 __checkReturn efx_rc_t
701efx_phy_prop_get(
702 __in efx_nic_t *enp,
703 __in unsigned int id,
704 __in uint32_t flags,
705 __out uint32_t *valp)
706{
707 efx_port_t *epp = &(enp->en_port);
708 efx_phy_ops_t *epop = epp->ep_epop;
709
710 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
711 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
712
713 return (epop->epo_prop_get(enp, id, flags, valp));
714}
715
716 __checkReturn efx_rc_t
717efx_phy_prop_set(
718 __in efx_nic_t *enp,
719 __in unsigned int id,
720 __in uint32_t val)
721{
722 efx_port_t *epp = &(enp->en_port);
723 efx_phy_ops_t *epop = epp->ep_epop;
724
725 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
726 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
727
728 return (epop->epo_prop_set(enp, id, val));
729}
730#endif /* EFSYS_OPT_PHY_STATS */
731
732#if EFSYS_OPT_BIST
733
734 __checkReturn efx_rc_t
735efx_bist_enable_offline(
736 __in efx_nic_t *enp)
737{
738 efx_port_t *epp = &(enp->en_port);
739 efx_phy_ops_t *epop = epp->ep_epop;
740 efx_rc_t rc;
741
742 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
743
744 if (epop->epo_bist_enable_offline == NULL) {
745 rc = ENOTSUP;
746 goto fail1;
747 }
748
749 if ((rc = epop->epo_bist_enable_offline(enp)) != 0)
750 goto fail2;
751
752 return (0);
753
754fail2:
755 EFSYS_PROBE(fail2);
756fail1:
757 EFSYS_PROBE1(fail1, efx_rc_t, rc);
758
759 return (rc);
760
761}
762
763 __checkReturn efx_rc_t
764efx_bist_start(
765 __in efx_nic_t *enp,
766 __in efx_bist_type_t type)
767{
768 efx_port_t *epp = &(enp->en_port);
769 efx_phy_ops_t *epop = epp->ep_epop;
770 efx_rc_t rc;
771
772 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
773
774 EFSYS_ASSERT3U(type, !=, EFX_BIST_TYPE_UNKNOWN);
775 EFSYS_ASSERT3U(type, <, EFX_BIST_TYPE_NTYPES);
776 EFSYS_ASSERT3U(epp->ep_current_bist, ==, EFX_BIST_TYPE_UNKNOWN);
777
778 if (epop->epo_bist_start == NULL) {
779 rc = ENOTSUP;
780 goto fail1;
781 }
782
783 if ((rc = epop->epo_bist_start(enp, type)) != 0)
784 goto fail2;
785
786 epp->ep_current_bist = type;
787
788 return (0);
789
790fail2:
791 EFSYS_PROBE(fail2);
792fail1:
793 EFSYS_PROBE1(fail1, efx_rc_t, rc);
794
795 return (rc);
796}
797
798 __checkReturn efx_rc_t
799efx_bist_poll(
800 __in efx_nic_t *enp,
801 __in efx_bist_type_t type,
802 __out efx_bist_result_t *resultp,
803 __out_opt uint32_t *value_maskp,
804 __out_ecount_opt(count) unsigned long *valuesp,
805 __in size_t count)
806{
807 efx_port_t *epp = &(enp->en_port);
808 efx_phy_ops_t *epop = epp->ep_epop;
809 efx_rc_t rc;
810
811 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
812
813 EFSYS_ASSERT3U(type, !=, EFX_BIST_TYPE_UNKNOWN);
814 EFSYS_ASSERT3U(type, <, EFX_BIST_TYPE_NTYPES);
815 EFSYS_ASSERT3U(epp->ep_current_bist, ==, type);
816
817 EFSYS_ASSERT(epop->epo_bist_poll != NULL);
818 if (epop->epo_bist_poll == NULL) {
819 rc = ENOTSUP;
820 goto fail1;
821 }
822
823 if ((rc = epop->epo_bist_poll(enp, type, resultp, value_maskp,
824 valuesp, count)) != 0)
825 goto fail2;
826
827 return (0);
828
829fail2:
830 EFSYS_PROBE(fail2);
831fail1:
832 EFSYS_PROBE1(fail1, efx_rc_t, rc);
833
834 return (rc);
835}
836
837 void
838efx_bist_stop(
839 __in efx_nic_t *enp,
840 __in efx_bist_type_t type)
841{
842 efx_port_t *epp = &(enp->en_port);
843 efx_phy_ops_t *epop = epp->ep_epop;
844
845 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
846
847 EFSYS_ASSERT3U(type, !=, EFX_BIST_TYPE_UNKNOWN);
848 EFSYS_ASSERT3U(type, <, EFX_BIST_TYPE_NTYPES);
849 EFSYS_ASSERT3U(epp->ep_current_bist, ==, type);
850
851 EFSYS_ASSERT(epop->epo_bist_stop != NULL);
852
853 if (epop->epo_bist_stop != NULL)
854 epop->epo_bist_stop(enp, type);
855
856 epp->ep_current_bist = EFX_BIST_TYPE_UNKNOWN;
857}
858
859#endif /* EFSYS_OPT_BIST */
860 void
861efx_phy_unprobe(
862 __in efx_nic_t *enp)
863{
864 efx_port_t *epp = &(enp->en_port);
865
866 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
867
868 epp->ep_epop = NULL;
869
870 epp->ep_adv_cap_mask = 0;
871
872 epp->ep_port = 0;
873 epp->ep_phy_type = 0;
874}
| 309#if EFSYS_OPT_SIENA
310 case EFX_FAMILY_SIENA:
311 epop = (efx_phy_ops_t *)&__efx_phy_siena_ops;
312 break;
313#endif /* EFSYS_OPT_SIENA */
314#if EFSYS_OPT_HUNTINGTON
315 case EFX_FAMILY_HUNTINGTON:
316 epop = (efx_phy_ops_t *)&__efx_phy_ef10_ops;
317 break;
318#endif /* EFSYS_OPT_HUNTINGTON */
319#if EFSYS_OPT_MEDFORD
320 case EFX_FAMILY_MEDFORD:
321 epop = (efx_phy_ops_t *)&__efx_phy_ef10_ops;
322 break;
323#endif /* EFSYS_OPT_MEDFORD */
324 default:
325 rc = ENOTSUP;
326 goto fail1;
327 }
328
329 epp->ep_epop = epop;
330
331 return (0);
332
333fail1:
334 EFSYS_PROBE1(fail1, efx_rc_t, rc);
335
336 epp->ep_port = 0;
337 epp->ep_phy_type = 0;
338
339 return (rc);
340}
341
342 __checkReturn efx_rc_t
343efx_phy_verify(
344 __in efx_nic_t *enp)
345{
346 efx_port_t *epp = &(enp->en_port);
347 efx_phy_ops_t *epop = epp->ep_epop;
348
349 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
350 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
351
352 return (epop->epo_verify(enp));
353}
354
355#if EFSYS_OPT_PHY_LED_CONTROL
356
357 __checkReturn efx_rc_t
358efx_phy_led_set(
359 __in efx_nic_t *enp,
360 __in efx_phy_led_mode_t mode)
361{
362 efx_nic_cfg_t *encp = (&enp->en_nic_cfg);
363 efx_port_t *epp = &(enp->en_port);
364 efx_phy_ops_t *epop = epp->ep_epop;
365 uint32_t mask;
366 efx_rc_t rc;
367
368 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
369 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
370
371 if (epp->ep_phy_led_mode == mode)
372 goto done;
373
374 mask = (1 << EFX_PHY_LED_DEFAULT);
375 mask |= encp->enc_led_mask;
376
377 if (!((1 << mode) & mask)) {
378 rc = ENOTSUP;
379 goto fail1;
380 }
381
382 EFSYS_ASSERT3U(mode, <, EFX_PHY_LED_NMODES);
383 epp->ep_phy_led_mode = mode;
384
385 if ((rc = epop->epo_reconfigure(enp)) != 0)
386 goto fail2;
387
388done:
389 return (0);
390
391fail2:
392 EFSYS_PROBE(fail2);
393fail1:
394 EFSYS_PROBE1(fail1, efx_rc_t, rc);
395
396 return (rc);
397}
398#endif /* EFSYS_OPT_PHY_LED_CONTROL */
399
400 void
401efx_phy_adv_cap_get(
402 __in efx_nic_t *enp,
403 __in uint32_t flag,
404 __out uint32_t *maskp)
405{
406 efx_port_t *epp = &(enp->en_port);
407
408 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
409 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
410
411 switch (flag) {
412 case EFX_PHY_CAP_CURRENT:
413 *maskp = epp->ep_adv_cap_mask;
414 break;
415 case EFX_PHY_CAP_DEFAULT:
416 *maskp = epp->ep_default_adv_cap_mask;
417 break;
418 case EFX_PHY_CAP_PERM:
419 *maskp = epp->ep_phy_cap_mask;
420 break;
421 default:
422 EFSYS_ASSERT(B_FALSE);
423 break;
424 }
425}
426
427 __checkReturn efx_rc_t
428efx_phy_adv_cap_set(
429 __in efx_nic_t *enp,
430 __in uint32_t mask)
431{
432 efx_port_t *epp = &(enp->en_port);
433 efx_phy_ops_t *epop = epp->ep_epop;
434 uint32_t old_mask;
435 efx_rc_t rc;
436
437 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
438 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
439
440 if ((mask & ~epp->ep_phy_cap_mask) != 0) {
441 rc = ENOTSUP;
442 goto fail1;
443 }
444
445 if (epp->ep_adv_cap_mask == mask)
446 goto done;
447
448 old_mask = epp->ep_adv_cap_mask;
449 epp->ep_adv_cap_mask = mask;
450
451 if ((rc = epop->epo_reconfigure(enp)) != 0)
452 goto fail2;
453
454done:
455 return (0);
456
457fail2:
458 EFSYS_PROBE(fail2);
459
460 epp->ep_adv_cap_mask = old_mask;
461 /* Reconfigure for robustness */
462 if (epop->epo_reconfigure(enp) != 0) {
463 /*
464 * We may have an inconsistent view of our advertised speed
465 * capabilities.
466 */
467 EFSYS_ASSERT(0);
468 }
469
470fail1:
471 EFSYS_PROBE1(fail1, efx_rc_t, rc);
472
473 return (rc);
474}
475
476 void
477efx_phy_lp_cap_get(
478 __in efx_nic_t *enp,
479 __out uint32_t *maskp)
480{
481 efx_port_t *epp = &(enp->en_port);
482
483 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
484 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
485
486 *maskp = epp->ep_lp_cap_mask;
487}
488
489 __checkReturn efx_rc_t
490efx_phy_oui_get(
491 __in efx_nic_t *enp,
492 __out uint32_t *ouip)
493{
494 efx_port_t *epp = &(enp->en_port);
495 efx_phy_ops_t *epop = epp->ep_epop;
496
497 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
498 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
499
500 return (epop->epo_oui_get(enp, ouip));
501}
502
503 void
504efx_phy_media_type_get(
505 __in efx_nic_t *enp,
506 __out efx_phy_media_type_t *typep)
507{
508 efx_port_t *epp = &(enp->en_port);
509
510 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
511 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
512
513 if (epp->ep_module_type != EFX_PHY_MEDIA_INVALID)
514 *typep = epp->ep_module_type;
515 else
516 *typep = epp->ep_fixed_port_type;
517}
518
519 __checkReturn efx_rc_t
520efx_phy_module_get_info(
521 __in efx_nic_t *enp,
522 __in uint8_t dev_addr,
523 __in uint8_t offset,
524 __in uint8_t len,
525 __out_bcount(len) uint8_t *data)
526{
527 efx_rc_t rc;
528
529 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
530 EFSYS_ASSERT(data != NULL);
531
532 if ((uint32_t)offset + len > 0xff) {
533 rc = EINVAL;
534 goto fail1;
535 }
536
537 if ((rc = efx_mcdi_phy_module_get_info(enp, dev_addr,
538 offset, len, data)) != 0)
539 goto fail2;
540
541 return (0);
542
543fail2:
544 EFSYS_PROBE(fail2);
545fail1:
546 EFSYS_PROBE1(fail1, efx_rc_t, rc);
547
548 return (rc);
549}
550
551#if EFSYS_OPT_PHY_STATS
552
553#if EFSYS_OPT_NAMES
554
555/* START MKCONFIG GENERATED PhyStatNamesBlock d5f79b4bc2c050fe */
556static const char *__efx_phy_stat_name[] = {
557 "oui",
558 "pma_pmd_link_up",
559 "pma_pmd_rx_fault",
560 "pma_pmd_tx_fault",
561 "pma_pmd_rev_a",
562 "pma_pmd_rev_b",
563 "pma_pmd_rev_c",
564 "pma_pmd_rev_d",
565 "pcs_link_up",
566 "pcs_rx_fault",
567 "pcs_tx_fault",
568 "pcs_ber",
569 "pcs_block_errors",
570 "phy_xs_link_up",
571 "phy_xs_rx_fault",
572 "phy_xs_tx_fault",
573 "phy_xs_align",
574 "phy_xs_sync_a",
575 "phy_xs_sync_b",
576 "phy_xs_sync_c",
577 "phy_xs_sync_d",
578 "an_link_up",
579 "an_master",
580 "an_local_rx_ok",
581 "an_remote_rx_ok",
582 "cl22ext_link_up",
583 "snr_a",
584 "snr_b",
585 "snr_c",
586 "snr_d",
587 "pma_pmd_signal_a",
588 "pma_pmd_signal_b",
589 "pma_pmd_signal_c",
590 "pma_pmd_signal_d",
591 "an_complete",
592 "pma_pmd_rev_major",
593 "pma_pmd_rev_minor",
594 "pma_pmd_rev_micro",
595 "pcs_fw_version_0",
596 "pcs_fw_version_1",
597 "pcs_fw_version_2",
598 "pcs_fw_version_3",
599 "pcs_fw_build_yy",
600 "pcs_fw_build_mm",
601 "pcs_fw_build_dd",
602 "pcs_op_mode",
603};
604
605/* END MKCONFIG GENERATED PhyStatNamesBlock */
606
607 const char *
608efx_phy_stat_name(
609 __in efx_nic_t *enp,
610 __in efx_phy_stat_t type)
611{
612 _NOTE(ARGUNUSED(enp))
613 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
614 EFSYS_ASSERT3U(type, <, EFX_PHY_NSTATS);
615
616 return (__efx_phy_stat_name[type]);
617}
618
619#endif /* EFSYS_OPT_NAMES */
620
621 __checkReturn efx_rc_t
622efx_phy_stats_update(
623 __in efx_nic_t *enp,
624 __in efsys_mem_t *esmp,
625 __inout_ecount(EFX_PHY_NSTATS) uint32_t *stat)
626{
627 efx_port_t *epp = &(enp->en_port);
628 efx_phy_ops_t *epop = epp->ep_epop;
629
630 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
631 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
632
633 return (epop->epo_stats_update(enp, esmp, stat));
634}
635
636#endif /* EFSYS_OPT_PHY_STATS */
637
638#if EFSYS_OPT_PHY_PROPS
639
640#if EFSYS_OPT_NAMES
641 const char *
642efx_phy_prop_name(
643 __in efx_nic_t *enp,
644 __in unsigned int id)
645{
646 efx_port_t *epp = &(enp->en_port);
647 efx_phy_ops_t *epop = epp->ep_epop;
648
649 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
650 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
651
652 return (epop->epo_prop_name(enp, id));
653}
654#endif /* EFSYS_OPT_NAMES */
655
656 __checkReturn efx_rc_t
657efx_phy_prop_get(
658 __in efx_nic_t *enp,
659 __in unsigned int id,
660 __in uint32_t flags,
661 __out uint32_t *valp)
662{
663 efx_port_t *epp = &(enp->en_port);
664 efx_phy_ops_t *epop = epp->ep_epop;
665
666 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
667 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
668
669 return (epop->epo_prop_get(enp, id, flags, valp));
670}
671
672 __checkReturn efx_rc_t
673efx_phy_prop_set(
674 __in efx_nic_t *enp,
675 __in unsigned int id,
676 __in uint32_t val)
677{
678 efx_port_t *epp = &(enp->en_port);
679 efx_phy_ops_t *epop = epp->ep_epop;
680
681 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
682 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
683
684 return (epop->epo_prop_set(enp, id, val));
685}
686#endif /* EFSYS_OPT_PHY_STATS */
687
688#if EFSYS_OPT_BIST
689
690 __checkReturn efx_rc_t
691efx_bist_enable_offline(
692 __in efx_nic_t *enp)
693{
694 efx_port_t *epp = &(enp->en_port);
695 efx_phy_ops_t *epop = epp->ep_epop;
696 efx_rc_t rc;
697
698 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
699
700 if (epop->epo_bist_enable_offline == NULL) {
701 rc = ENOTSUP;
702 goto fail1;
703 }
704
705 if ((rc = epop->epo_bist_enable_offline(enp)) != 0)
706 goto fail2;
707
708 return (0);
709
710fail2:
711 EFSYS_PROBE(fail2);
712fail1:
713 EFSYS_PROBE1(fail1, efx_rc_t, rc);
714
715 return (rc);
716
717}
718
719 __checkReturn efx_rc_t
720efx_bist_start(
721 __in efx_nic_t *enp,
722 __in efx_bist_type_t type)
723{
724 efx_port_t *epp = &(enp->en_port);
725 efx_phy_ops_t *epop = epp->ep_epop;
726 efx_rc_t rc;
727
728 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
729
730 EFSYS_ASSERT3U(type, !=, EFX_BIST_TYPE_UNKNOWN);
731 EFSYS_ASSERT3U(type, <, EFX_BIST_TYPE_NTYPES);
732 EFSYS_ASSERT3U(epp->ep_current_bist, ==, EFX_BIST_TYPE_UNKNOWN);
733
734 if (epop->epo_bist_start == NULL) {
735 rc = ENOTSUP;
736 goto fail1;
737 }
738
739 if ((rc = epop->epo_bist_start(enp, type)) != 0)
740 goto fail2;
741
742 epp->ep_current_bist = type;
743
744 return (0);
745
746fail2:
747 EFSYS_PROBE(fail2);
748fail1:
749 EFSYS_PROBE1(fail1, efx_rc_t, rc);
750
751 return (rc);
752}
753
754 __checkReturn efx_rc_t
755efx_bist_poll(
756 __in efx_nic_t *enp,
757 __in efx_bist_type_t type,
758 __out efx_bist_result_t *resultp,
759 __out_opt uint32_t *value_maskp,
760 __out_ecount_opt(count) unsigned long *valuesp,
761 __in size_t count)
762{
763 efx_port_t *epp = &(enp->en_port);
764 efx_phy_ops_t *epop = epp->ep_epop;
765 efx_rc_t rc;
766
767 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
768
769 EFSYS_ASSERT3U(type, !=, EFX_BIST_TYPE_UNKNOWN);
770 EFSYS_ASSERT3U(type, <, EFX_BIST_TYPE_NTYPES);
771 EFSYS_ASSERT3U(epp->ep_current_bist, ==, type);
772
773 EFSYS_ASSERT(epop->epo_bist_poll != NULL);
774 if (epop->epo_bist_poll == NULL) {
775 rc = ENOTSUP;
776 goto fail1;
777 }
778
779 if ((rc = epop->epo_bist_poll(enp, type, resultp, value_maskp,
780 valuesp, count)) != 0)
781 goto fail2;
782
783 return (0);
784
785fail2:
786 EFSYS_PROBE(fail2);
787fail1:
788 EFSYS_PROBE1(fail1, efx_rc_t, rc);
789
790 return (rc);
791}
792
793 void
794efx_bist_stop(
795 __in efx_nic_t *enp,
796 __in efx_bist_type_t type)
797{
798 efx_port_t *epp = &(enp->en_port);
799 efx_phy_ops_t *epop = epp->ep_epop;
800
801 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
802
803 EFSYS_ASSERT3U(type, !=, EFX_BIST_TYPE_UNKNOWN);
804 EFSYS_ASSERT3U(type, <, EFX_BIST_TYPE_NTYPES);
805 EFSYS_ASSERT3U(epp->ep_current_bist, ==, type);
806
807 EFSYS_ASSERT(epop->epo_bist_stop != NULL);
808
809 if (epop->epo_bist_stop != NULL)
810 epop->epo_bist_stop(enp, type);
811
812 epp->ep_current_bist = EFX_BIST_TYPE_UNKNOWN;
813}
814
815#endif /* EFSYS_OPT_BIST */
816 void
817efx_phy_unprobe(
818 __in efx_nic_t *enp)
819{
820 efx_port_t *epp = &(enp->en_port);
821
822 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
823
824 epp->ep_epop = NULL;
825
826 epp->ep_adv_cap_mask = 0;
827
828 epp->ep_port = 0;
829 epp->ep_phy_type = 0;
830}
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