28 29#include "efsys.h" 30#include "efx.h" 31#include "efx_types.h" 32#include "efx_regs.h" 33#include "efx_impl.h" 34 35 __checkReturn int 36efx_family( 37 __in uint16_t venid, 38 __in uint16_t devid, 39 __out efx_family_t *efp) 40{ 41#if EFSYS_OPT_FALCON 42 if (venid == EFX_PCI_VENID_SFC && devid == EFX_PCI_DEVID_FALCON) { 43 *efp = EFX_FAMILY_FALCON; 44 return (0); 45 } 46#endif 47#if EFSYS_OPT_SIENA 48 if (venid == EFX_PCI_VENID_SFC && devid == EFX_PCI_DEVID_BETHPAGE) { 49 *efp = EFX_FAMILY_SIENA; 50 return (0); 51 } 52 if (venid == EFX_PCI_VENID_SFC && devid == EFX_PCI_DEVID_SIENA) { 53 *efp = EFX_FAMILY_SIENA; 54 return (0); 55 } 56 if (venid == EFX_PCI_VENID_SFC && 57 devid == EFX_PCI_DEVID_SIENA_F1_UNINIT) { 58 *efp = EFX_FAMILY_SIENA; 59 return (0); 60 } 61#endif 62 return (ENOTSUP); 63} 64 65/* 66 * To support clients which aren't provided with any PCI context infer 67 * the hardware family by inspecting the hardware. Obviously the caller 68 * must be damn sure they're really talking to a supported device. 69 */ 70 __checkReturn int 71efx_infer_family( 72 __in efsys_bar_t *esbp, 73 __out efx_family_t *efp) 74{ 75 efx_family_t family; 76 efx_oword_t oword; 77 unsigned int portnum; 78 int rc; 79 80 EFSYS_BAR_READO(esbp, FR_AZ_CS_DEBUG_REG_OFST, &oword, B_TRUE); 81 portnum = EFX_OWORD_FIELD(oword, FRF_CZ_CS_PORT_NUM); 82 switch (portnum) { 83#if EFSYS_OPT_FALCON 84 case 0: 85 family = EFX_FAMILY_FALCON; 86 break; 87#endif 88#if EFSYS_OPT_SIENA 89 case 1: 90 case 2: 91 family = EFX_FAMILY_SIENA; 92 break; 93#endif 94 default: 95 rc = ENOTSUP; 96 goto fail1; 97 } 98 99 if (efp != NULL) 100 *efp = family; 101 return (0); 102 103fail1: 104 EFSYS_PROBE1(fail1, int, rc); 105 106 return (rc); 107} 108 109/* 110 * The built-in default value device id for port 1 of Siena is 0x0810. 111 * manftest needs to be able to cope with that. 112 */ 113 114#define EFX_BIU_MAGIC0 0x01234567 115#define EFX_BIU_MAGIC1 0xfedcba98 116 117static __checkReturn int 118efx_nic_biu_test( 119 __in efx_nic_t *enp) 120{ 121 efx_oword_t oword; 122 int rc; 123 124 /* 125 * Write magic values to scratch registers 0 and 1, then 126 * verify that the values were written correctly. Interleave 127 * the accesses to ensure that the BIU is not just reading 128 * back the cached value that was last written. 129 */ 130 EFX_POPULATE_OWORD_1(oword, FRF_AZ_DRIVER_DW0, EFX_BIU_MAGIC0); 131 EFX_BAR_TBL_WRITEO(enp, FR_AZ_DRIVER_REG, 0, &oword); 132 133 EFX_POPULATE_OWORD_1(oword, FRF_AZ_DRIVER_DW0, EFX_BIU_MAGIC1); 134 EFX_BAR_TBL_WRITEO(enp, FR_AZ_DRIVER_REG, 1, &oword); 135 136 EFX_BAR_TBL_READO(enp, FR_AZ_DRIVER_REG, 0, &oword); 137 if (EFX_OWORD_FIELD(oword, FRF_AZ_DRIVER_DW0) != EFX_BIU_MAGIC0) { 138 rc = EIO; 139 goto fail1; 140 } 141 142 EFX_BAR_TBL_READO(enp, FR_AZ_DRIVER_REG, 1, &oword); 143 if (EFX_OWORD_FIELD(oword, FRF_AZ_DRIVER_DW0) != EFX_BIU_MAGIC1) { 144 rc = EIO; 145 goto fail2; 146 } 147 148 /* 149 * Perform the same test, with the values swapped. This 150 * ensures that subsequent tests don't start with the correct 151 * values already written into the scratch registers. 152 */ 153 EFX_POPULATE_OWORD_1(oword, FRF_AZ_DRIVER_DW0, EFX_BIU_MAGIC1); 154 EFX_BAR_TBL_WRITEO(enp, FR_AZ_DRIVER_REG, 0, &oword); 155 156 EFX_POPULATE_OWORD_1(oword, FRF_AZ_DRIVER_DW0, EFX_BIU_MAGIC0); 157 EFX_BAR_TBL_WRITEO(enp, FR_AZ_DRIVER_REG, 1, &oword); 158 159 EFX_BAR_TBL_READO(enp, FR_AZ_DRIVER_REG, 0, &oword); 160 if (EFX_OWORD_FIELD(oword, FRF_AZ_DRIVER_DW0) != EFX_BIU_MAGIC1) { 161 rc = EIO; 162 goto fail3; 163 } 164 165 EFX_BAR_TBL_READO(enp, FR_AZ_DRIVER_REG, 1, &oword); 166 if (EFX_OWORD_FIELD(oword, FRF_AZ_DRIVER_DW0) != EFX_BIU_MAGIC0) { 167 rc = EIO; 168 goto fail4; 169 } 170 171 return (0); 172 173fail4: 174 EFSYS_PROBE(fail4); 175fail3: 176 EFSYS_PROBE(fail3); 177fail2: 178 EFSYS_PROBE(fail2); 179fail1: 180 EFSYS_PROBE1(fail1, int, rc); 181 182 return (rc); 183} 184 185#if EFSYS_OPT_FALCON 186 187static efx_nic_ops_t __cs __efx_nic_falcon_ops = { 188 falcon_nic_probe, /* eno_probe */ 189 falcon_nic_reset, /* eno_reset */ 190 falcon_nic_init, /* eno_init */ 191#if EFSYS_OPT_DIAG 192 falcon_sram_test, /* eno_sram_test */ 193 falcon_nic_register_test, /* eno_register_test */ 194#endif /* EFSYS_OPT_DIAG */ 195 falcon_nic_fini, /* eno_fini */ 196 falcon_nic_unprobe, /* eno_unprobe */ 197}; 198 199#endif /* EFSYS_OPT_FALCON */ 200 201#if EFSYS_OPT_SIENA 202 203static efx_nic_ops_t __cs __efx_nic_siena_ops = { 204 siena_nic_probe, /* eno_probe */ 205 siena_nic_reset, /* eno_reset */ 206 siena_nic_init, /* eno_init */ 207#if EFSYS_OPT_DIAG 208 siena_sram_test, /* eno_sram_test */ 209 siena_nic_register_test, /* eno_register_test */ 210#endif /* EFSYS_OPT_DIAG */ 211 siena_nic_fini, /* eno_fini */ 212 siena_nic_unprobe, /* eno_unprobe */ 213}; 214 215#endif /* EFSYS_OPT_SIENA */ 216 217 __checkReturn int 218efx_nic_create( 219 __in efx_family_t family, 220 __in efsys_identifier_t *esip, 221 __in efsys_bar_t *esbp, 222 __in efsys_lock_t *eslp, 223 __deref_out efx_nic_t **enpp) 224{ 225 efx_nic_t *enp; 226 int rc; 227 228 EFSYS_ASSERT3U(family, >, EFX_FAMILY_INVALID); 229 EFSYS_ASSERT3U(family, <, EFX_FAMILY_NTYPES); 230 231 /* Allocate a NIC object */ 232 EFSYS_KMEM_ALLOC(esip, sizeof (efx_nic_t), enp); 233 234 if (enp == NULL) { 235 rc = ENOMEM; 236 goto fail1; 237 } 238 239 enp->en_magic = EFX_NIC_MAGIC; 240 241 switch (family) { 242#if EFSYS_OPT_FALCON 243 case EFX_FAMILY_FALCON: 244 enp->en_enop = (efx_nic_ops_t *)&__efx_nic_falcon_ops; 245 enp->en_features = 0; 246 break; 247#endif /* EFSYS_OPT_FALCON */ 248 249#if EFSYS_OPT_SIENA 250 case EFX_FAMILY_SIENA: 251 enp->en_enop = (efx_nic_ops_t *)&__efx_nic_siena_ops; 252 enp->en_features = EFX_FEATURE_IPV6 | 253 EFX_FEATURE_LFSR_HASH_INSERT | 254 EFX_FEATURE_LINK_EVENTS | EFX_FEATURE_PERIODIC_MAC_STATS | 255 EFX_FEATURE_WOL | EFX_FEATURE_MCDI |
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258 break; 259#endif /* EFSYS_OPT_SIENA */ 260 261 default: 262 rc = ENOTSUP; 263 goto fail2; 264 } 265 266 enp->en_family = family; 267 enp->en_esip = esip; 268 enp->en_esbp = esbp; 269 enp->en_eslp = eslp; 270 271 *enpp = enp; 272 273 return (0); 274 275fail2: 276 EFSYS_PROBE(fail3); 277 278 enp->en_magic = 0; 279 280 /* Free the NIC object */ 281 EFSYS_KMEM_FREE(esip, sizeof (efx_nic_t), enp); 282 283fail1: 284 EFSYS_PROBE1(fail1, int, rc); 285 286 return (rc); 287} 288 289 __checkReturn int 290efx_nic_probe( 291 __in efx_nic_t *enp) 292{ 293 efx_nic_ops_t *enop; 294 efx_oword_t oword; 295 int rc; 296 297 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); 298#if EFSYS_OPT_MCDI 299 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_MCDI); 300#endif /* EFSYS_OPT_MCDI */ 301 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_PROBE)); 302 303 /* Test BIU */ 304 if ((rc = efx_nic_biu_test(enp)) != 0) 305 goto fail1; 306 307 /* Clear the region register */ 308 EFX_POPULATE_OWORD_4(oword, 309 FRF_AZ_ADR_REGION0, 0, 310 FRF_AZ_ADR_REGION1, (1 << 16), 311 FRF_AZ_ADR_REGION2, (2 << 16), 312 FRF_AZ_ADR_REGION3, (3 << 16)); 313 EFX_BAR_WRITEO(enp, FR_AZ_ADR_REGION_REG, &oword); 314 315 enop = enp->en_enop; 316 if ((rc = enop->eno_probe(enp)) != 0) 317 goto fail2; 318 319 if ((rc = efx_phy_probe(enp)) != 0) 320 goto fail3; 321 322 enp->en_mod_flags |= EFX_MOD_PROBE; 323 324 return (0); 325 326fail3: 327 EFSYS_PROBE(fail3); 328 329 enop->eno_unprobe(enp); 330 331fail2: 332 EFSYS_PROBE(fail2); 333fail1: 334 EFSYS_PROBE1(fail1, int, rc); 335 336 return (rc); 337} 338 339#if EFSYS_OPT_PCIE_TUNE 340 341 __checkReturn int 342efx_nic_pcie_tune( 343 __in efx_nic_t *enp, 344 unsigned int nlanes) 345{ 346 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); 347 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE); 348 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_NIC)); 349 350#if EFSYS_OPT_FALCON 351 if (enp->en_family == EFX_FAMILY_FALCON) 352 return (falcon_nic_pcie_tune(enp, nlanes)); 353#endif 354 return (ENOTSUP); 355} 356 357 __checkReturn int 358efx_nic_pcie_extended_sync( 359 __in efx_nic_t *enp) 360{ 361 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); 362 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE); 363 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_NIC)); 364 365#if EFSYS_OPT_SIENA 366 if (enp->en_family == EFX_FAMILY_SIENA) 367 return (siena_nic_pcie_extended_sync(enp)); 368#endif 369 370 return (ENOTSUP); 371} 372 373#endif /* EFSYS_OPT_PCIE_TUNE */ 374 375 __checkReturn int 376efx_nic_init( 377 __in efx_nic_t *enp) 378{ 379 efx_nic_ops_t *enop = enp->en_enop; 380 int rc; 381 382 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); 383 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE); 384 385 if (enp->en_mod_flags & EFX_MOD_NIC) { 386 rc = EINVAL; 387 goto fail1; 388 } 389 390 if ((rc = enop->eno_init(enp)) != 0) 391 goto fail2; 392 393 enp->en_mod_flags |= EFX_MOD_NIC; 394 395 return (0); 396 397fail2: 398 EFSYS_PROBE(fail2); 399fail1: 400 EFSYS_PROBE1(fail1, int, rc); 401 402 return (rc); 403} 404 405 void 406efx_nic_fini( 407 __in efx_nic_t *enp) 408{ 409 efx_nic_ops_t *enop = enp->en_enop; 410 411 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); 412 EFSYS_ASSERT(enp->en_mod_flags & EFX_MOD_PROBE); 413 EFSYS_ASSERT(enp->en_mod_flags & EFX_MOD_NIC); 414 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_INTR)); 415 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_EV)); 416 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_RX)); 417 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_TX)); 418 419 enop->eno_fini(enp); 420 421 enp->en_mod_flags &= ~EFX_MOD_NIC; 422} 423 424 void 425efx_nic_unprobe( 426 __in efx_nic_t *enp) 427{ 428 efx_nic_ops_t *enop = enp->en_enop; 429 430 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); 431#if EFSYS_OPT_MCDI 432 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_MCDI); 433#endif /* EFSYS_OPT_MCDI */ 434 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE); 435 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_NIC)); 436 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_INTR)); 437 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_EV)); 438 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_RX)); 439 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_TX)); 440 441 efx_phy_unprobe(enp); 442 443 enop->eno_unprobe(enp); 444 445 enp->en_mod_flags &= ~EFX_MOD_PROBE; 446} 447 448 void 449efx_nic_destroy( 450 __in efx_nic_t *enp) 451{ 452 efsys_identifier_t *esip = enp->en_esip; 453 454 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); 455 EFSYS_ASSERT3U(enp->en_mod_flags, ==, 0); 456 457 enp->en_family = 0; 458 enp->en_esip = NULL; 459 enp->en_esbp = NULL; 460 enp->en_eslp = NULL; 461 462 enp->en_enop = NULL; 463 464 enp->en_magic = 0; 465 466 /* Free the NIC object */ 467 EFSYS_KMEM_FREE(esip, sizeof (efx_nic_t), enp); 468} 469 470 __checkReturn int 471efx_nic_reset( 472 __in efx_nic_t *enp) 473{ 474 efx_nic_ops_t *enop = enp->en_enop; 475 unsigned int mod_flags; 476 int rc; 477 478 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); 479 EFSYS_ASSERT(enp->en_mod_flags & EFX_MOD_PROBE); 480 /* 481 * All modules except the MCDI, PROBE, NVRAM, VPD, MON (which we 482 * do not reset here) must have been shut down or never initialized. 483 * 484 * A rule of thumb here is: If the controller or MC reboots, is *any* 485 * state lost. If it's lost and needs reapplying, then the module 486 * *must* not be initialised during the reset. 487 */ 488 mod_flags = enp->en_mod_flags; 489 mod_flags &= ~(EFX_MOD_MCDI | EFX_MOD_PROBE | EFX_MOD_NVRAM | 490 EFX_MOD_VPD | EFX_MOD_MON); 491 EFSYS_ASSERT3U(mod_flags, ==, 0); 492 if (mod_flags != 0) { 493 rc = EINVAL; 494 goto fail1; 495 } 496 497 if ((rc = enop->eno_reset(enp)) != 0) 498 goto fail2; 499 500 enp->en_reset_flags |= EFX_RESET_MAC; 501 502 return (0); 503 504fail2: 505 EFSYS_PROBE(fail2); 506fail1: 507 EFSYS_PROBE1(fail1, int, rc); 508 509 return (rc); 510} 511 512 const efx_nic_cfg_t * 513efx_nic_cfg_get( 514 __in efx_nic_t *enp) 515{ 516 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); 517 518 return (&(enp->en_nic_cfg)); 519} 520 521#if EFSYS_OPT_DIAG 522 523 __checkReturn int 524efx_nic_register_test( 525 __in efx_nic_t *enp) 526{ 527 efx_nic_ops_t *enop = enp->en_enop; 528 int rc; 529 530 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); 531 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE); 532 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_NIC)); 533 534 if ((rc = enop->eno_register_test(enp)) != 0) 535 goto fail1; 536 537 return (0); 538 539fail1: 540 EFSYS_PROBE1(fail1, int, rc); 541 542 return (rc); 543} 544 545 __checkReturn int 546efx_nic_test_registers( 547 __in efx_nic_t *enp, 548 __in efx_register_set_t *rsp, 549 __in size_t count) 550{ 551 unsigned int bit; 552 efx_oword_t original; 553 efx_oword_t reg; 554 efx_oword_t buf; 555 int rc; 556 557 while (count > 0) { 558 /* This function is only suitable for registers */ 559 EFSYS_ASSERT(rsp->rows == 1); 560 561 /* bit sweep on and off */ 562 EFSYS_BAR_READO(enp->en_esbp, rsp->address, &original, 563 B_TRUE); 564 for (bit = 0; bit < 128; bit++) { 565 /* Is this bit in the mask? */ 566 if (~(rsp->mask.eo_u32[bit >> 5]) & (1 << bit)) 567 continue; 568 569 /* Test this bit can be set in isolation */ 570 reg = original; 571 EFX_AND_OWORD(reg, rsp->mask); 572 EFX_SET_OWORD_BIT(reg, bit); 573 574 EFSYS_BAR_WRITEO(enp->en_esbp, rsp->address, ®, 575 B_TRUE); 576 EFSYS_BAR_READO(enp->en_esbp, rsp->address, &buf, 577 B_TRUE); 578 579 EFX_AND_OWORD(buf, rsp->mask); 580 if (memcmp(®, &buf, sizeof (reg))) { 581 rc = EIO; 582 goto fail1; 583 } 584 585 /* Test this bit can be cleared in isolation */ 586 EFX_OR_OWORD(reg, rsp->mask); 587 EFX_CLEAR_OWORD_BIT(reg, bit); 588 589 EFSYS_BAR_WRITEO(enp->en_esbp, rsp->address, ®, 590 B_TRUE); 591 EFSYS_BAR_READO(enp->en_esbp, rsp->address, &buf, 592 B_TRUE); 593 594 EFX_AND_OWORD(buf, rsp->mask); 595 if (memcmp(®, &buf, sizeof (reg))) { 596 rc = EIO; 597 goto fail2; 598 } 599 } 600 601 /* Restore the old value */ 602 EFSYS_BAR_WRITEO(enp->en_esbp, rsp->address, &original, 603 B_TRUE); 604 605 --count; 606 ++rsp; 607 } 608 609 return (0); 610 611fail2: 612 EFSYS_PROBE(fail2); 613fail1: 614 EFSYS_PROBE1(fail1, int, rc); 615 616 /* Restore the old value */ 617 EFSYS_BAR_WRITEO(enp->en_esbp, rsp->address, &original, B_TRUE); 618 619 return (rc); 620} 621 622 __checkReturn int 623efx_nic_test_tables( 624 __in efx_nic_t *enp, 625 __in efx_register_set_t *rsp, 626 __in efx_pattern_type_t pattern, 627 __in size_t count) 628{ 629 efx_sram_pattern_fn_t func; 630 unsigned int index; 631 unsigned int address; 632 efx_oword_t reg; 633 efx_oword_t buf; 634 int rc; 635 636 EFSYS_ASSERT(pattern < EFX_PATTERN_NTYPES); 637 func = __efx_sram_pattern_fns[pattern]; 638 639 while (count > 0) { 640 /* Write */ 641 address = rsp->address; 642 for (index = 0; index < rsp->rows; ++index) { 643 func(2 * index + 0, B_FALSE, ®.eo_qword[0]); 644 func(2 * index + 1, B_FALSE, ®.eo_qword[1]); 645 EFX_AND_OWORD(reg, rsp->mask); 646 EFSYS_BAR_WRITEO(enp->en_esbp, address, ®, B_TRUE); 647 648 address += rsp->step; 649 } 650 651 /* Read */ 652 address = rsp->address; 653 for (index = 0; index < rsp->rows; ++index) { 654 func(2 * index + 0, B_FALSE, ®.eo_qword[0]); 655 func(2 * index + 1, B_FALSE, ®.eo_qword[1]); 656 EFX_AND_OWORD(reg, rsp->mask); 657 EFSYS_BAR_READO(enp->en_esbp, address, &buf, B_TRUE); 658 if (memcmp(®, &buf, sizeof (reg))) { 659 rc = EIO; 660 goto fail1; 661 } 662 663 address += rsp->step; 664 } 665 666 ++rsp; 667 --count; 668 } 669 670 return (0); 671 672fail1: 673 EFSYS_PROBE1(fail1, int, rc); 674 675 return (rc); 676} 677 678#endif /* EFSYS_OPT_DIAG */
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