1/*-
2 * Copyright (c) 2007-2015 Solarflare Communications Inc.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 *
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
18 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
19 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
21 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
22 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
23 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
24 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 *
26 * The views and conclusions contained in the software and documentation are
27 * those of the authors and should not be interpreted as representing official
28 * policies, either expressed or implied, of the FreeBSD Project.
29 *
|
30 * $FreeBSD: head/sys/dev/sfxge/common/efx_impl.h 299318 2016-05-10 06:51:20Z arybchik $
|
| 30 * $FreeBSD: head/sys/dev/sfxge/common/efx_impl.h 299320 2016-05-10 07:01:06Z arybchik $ |
31 */
32
33#ifndef _SYS_EFX_IMPL_H
34#define _SYS_EFX_IMPL_H
35
36#include "efsys.h"
37#include "efx_check.h"
38#include "efx.h"
39#include "efx_regs.h"
40#include "efx_regs_ef10.h"
41
42/* FIXME: Add definition for driver generated software events */
43#ifndef ESE_DZ_EV_CODE_DRV_GEN_EV
44#define ESE_DZ_EV_CODE_DRV_GEN_EV FSE_AZ_EV_CODE_DRV_GEN_EV
45#endif
46
47
|
48#if EFSYS_OPT_FALCON
49#include "falcon_impl.h"
50#endif /* EFSYS_OPT_FALCON */
51
|
48#if EFSYS_OPT_SIENA
49#include "siena_impl.h"
50#endif /* EFSYS_OPT_SIENA */
51
52#if EFSYS_OPT_HUNTINGTON
53#include "hunt_impl.h"
54#endif /* EFSYS_OPT_HUNTINGTON */
55
56#if EFSYS_OPT_MEDFORD
57#include "medford_impl.h"
58#endif /* EFSYS_OPT_MEDFORD */
59
60#if (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD)
61#include "ef10_impl.h"
62#endif /* (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD) */
63
64#ifdef __cplusplus
65extern "C" {
66#endif
67
68#define EFX_MOD_MCDI 0x00000001
69#define EFX_MOD_PROBE 0x00000002
70#define EFX_MOD_NVRAM 0x00000004
71#define EFX_MOD_VPD 0x00000008
72#define EFX_MOD_NIC 0x00000010
73#define EFX_MOD_INTR 0x00000020
74#define EFX_MOD_EV 0x00000040
75#define EFX_MOD_RX 0x00000080
76#define EFX_MOD_TX 0x00000100
77#define EFX_MOD_PORT 0x00000200
78#define EFX_MOD_MON 0x00000400
79#define EFX_MOD_WOL 0x00000800
80#define EFX_MOD_FILTER 0x00001000
81#define EFX_MOD_PKTFILTER 0x00002000
82#define EFX_MOD_LIC 0x00004000
83
84#define EFX_RESET_MAC 0x00000001
85#define EFX_RESET_PHY 0x00000002
86#define EFX_RESET_RXQ_ERR 0x00000004
87#define EFX_RESET_TXQ_ERR 0x00000008
88
89typedef enum efx_mac_type_e {
90 EFX_MAC_INVALID = 0,
91 EFX_MAC_FALCON_GMAC,
92 EFX_MAC_FALCON_XMAC,
93 EFX_MAC_SIENA,
94 EFX_MAC_HUNTINGTON,
95 EFX_MAC_MEDFORD,
96 EFX_MAC_NTYPES
97} efx_mac_type_t;
98
99typedef struct efx_ev_ops_s {
100 efx_rc_t (*eevo_init)(efx_nic_t *);
101 void (*eevo_fini)(efx_nic_t *);
102 efx_rc_t (*eevo_qcreate)(efx_nic_t *, unsigned int,
103 efsys_mem_t *, size_t, uint32_t,
104 efx_evq_t *);
105 void (*eevo_qdestroy)(efx_evq_t *);
106 efx_rc_t (*eevo_qprime)(efx_evq_t *, unsigned int);
107 void (*eevo_qpost)(efx_evq_t *, uint16_t);
108 efx_rc_t (*eevo_qmoderate)(efx_evq_t *, unsigned int);
109#if EFSYS_OPT_QSTATS
110 void (*eevo_qstats_update)(efx_evq_t *, efsys_stat_t *);
111#endif
112} efx_ev_ops_t;
113
114typedef struct efx_tx_ops_s {
115 efx_rc_t (*etxo_init)(efx_nic_t *);
116 void (*etxo_fini)(efx_nic_t *);
117 efx_rc_t (*etxo_qcreate)(efx_nic_t *,
118 unsigned int, unsigned int,
119 efsys_mem_t *, size_t,
120 uint32_t, uint16_t,
121 efx_evq_t *, efx_txq_t *,
122 unsigned int *);
123 void (*etxo_qdestroy)(efx_txq_t *);
124 efx_rc_t (*etxo_qpost)(efx_txq_t *, efx_buffer_t *,
125 unsigned int, unsigned int,
126 unsigned int *);
127 void (*etxo_qpush)(efx_txq_t *, unsigned int, unsigned int);
128 efx_rc_t (*etxo_qpace)(efx_txq_t *, unsigned int);
129 efx_rc_t (*etxo_qflush)(efx_txq_t *);
130 void (*etxo_qenable)(efx_txq_t *);
131 efx_rc_t (*etxo_qpio_enable)(efx_txq_t *);
132 void (*etxo_qpio_disable)(efx_txq_t *);
133 efx_rc_t (*etxo_qpio_write)(efx_txq_t *,uint8_t *, size_t,
134 size_t);
135 efx_rc_t (*etxo_qpio_post)(efx_txq_t *, size_t, unsigned int,
136 unsigned int *);
137 efx_rc_t (*etxo_qdesc_post)(efx_txq_t *, efx_desc_t *,
138 unsigned int, unsigned int,
139 unsigned int *);
140 void (*etxo_qdesc_dma_create)(efx_txq_t *, efsys_dma_addr_t,
141 size_t, boolean_t,
142 efx_desc_t *);
143 void (*etxo_qdesc_tso_create)(efx_txq_t *, uint16_t,
144 uint32_t, uint8_t,
145 efx_desc_t *);
146 void (*etxo_qdesc_tso2_create)(efx_txq_t *, uint16_t,
147 uint32_t, uint16_t,
148 efx_desc_t *, int);
149 void (*etxo_qdesc_vlantci_create)(efx_txq_t *, uint16_t,
150 efx_desc_t *);
151#if EFSYS_OPT_QSTATS
152 void (*etxo_qstats_update)(efx_txq_t *,
153 efsys_stat_t *);
154#endif
155} efx_tx_ops_t;
156
157typedef struct efx_rx_ops_s {
158 efx_rc_t (*erxo_init)(efx_nic_t *);
159 void (*erxo_fini)(efx_nic_t *);
160#if EFSYS_OPT_RX_SCATTER
161 efx_rc_t (*erxo_scatter_enable)(efx_nic_t *, unsigned int);
162#endif
163#if EFSYS_OPT_RX_SCALE
164 efx_rc_t (*erxo_scale_mode_set)(efx_nic_t *, efx_rx_hash_alg_t,
165 efx_rx_hash_type_t, boolean_t);
166 efx_rc_t (*erxo_scale_key_set)(efx_nic_t *, uint8_t *, size_t);
167 efx_rc_t (*erxo_scale_tbl_set)(efx_nic_t *, unsigned int *,
168 size_t);
169 uint32_t (*erxo_prefix_hash)(efx_nic_t *, efx_rx_hash_alg_t,
170 uint8_t *);
171#endif /* EFSYS_OPT_RX_SCALE */
172 efx_rc_t (*erxo_prefix_pktlen)(efx_nic_t *, uint8_t *,
173 uint16_t *);
174 void (*erxo_qpost)(efx_rxq_t *, efsys_dma_addr_t *, size_t,
175 unsigned int, unsigned int,
176 unsigned int);
177 void (*erxo_qpush)(efx_rxq_t *, unsigned int, unsigned int *);
178 efx_rc_t (*erxo_qflush)(efx_rxq_t *);
179 void (*erxo_qenable)(efx_rxq_t *);
180 efx_rc_t (*erxo_qcreate)(efx_nic_t *enp, unsigned int,
181 unsigned int, efx_rxq_type_t,
182 efsys_mem_t *, size_t, uint32_t,
183 efx_evq_t *, efx_rxq_t *);
184 void (*erxo_qdestroy)(efx_rxq_t *);
185} efx_rx_ops_t;
186
187typedef struct efx_mac_ops_s {
188 efx_rc_t (*emo_reset)(efx_nic_t *); /* optional */
189 efx_rc_t (*emo_poll)(efx_nic_t *, efx_link_mode_t *);
190 efx_rc_t (*emo_up)(efx_nic_t *, boolean_t *);
191 efx_rc_t (*emo_addr_set)(efx_nic_t *);
192 efx_rc_t (*emo_pdu_set)(efx_nic_t *);
193 efx_rc_t (*emo_reconfigure)(efx_nic_t *);
194 efx_rc_t (*emo_multicast_list_set)(efx_nic_t *);
195 efx_rc_t (*emo_filter_default_rxq_set)(efx_nic_t *,
196 efx_rxq_t *, boolean_t);
197 void (*emo_filter_default_rxq_clear)(efx_nic_t *);
198#if EFSYS_OPT_LOOPBACK
199 efx_rc_t (*emo_loopback_set)(efx_nic_t *, efx_link_mode_t,
200 efx_loopback_type_t);
201#endif /* EFSYS_OPT_LOOPBACK */
202#if EFSYS_OPT_MAC_STATS
203 efx_rc_t (*emo_stats_upload)(efx_nic_t *, efsys_mem_t *);
204 efx_rc_t (*emo_stats_periodic)(efx_nic_t *, efsys_mem_t *,
205 uint16_t, boolean_t);
206 efx_rc_t (*emo_stats_update)(efx_nic_t *, efsys_mem_t *,
207 efsys_stat_t *, uint32_t *);
208#endif /* EFSYS_OPT_MAC_STATS */
209} efx_mac_ops_t;
210
211typedef struct efx_phy_ops_s {
212 efx_rc_t (*epo_power)(efx_nic_t *, boolean_t); /* optional */
213 efx_rc_t (*epo_reset)(efx_nic_t *);
214 efx_rc_t (*epo_reconfigure)(efx_nic_t *);
215 efx_rc_t (*epo_verify)(efx_nic_t *);
216 efx_rc_t (*epo_uplink_check)(efx_nic_t *,
217 boolean_t *); /* optional */
218 efx_rc_t (*epo_downlink_check)(efx_nic_t *, efx_link_mode_t *,
219 unsigned int *, uint32_t *);
220 efx_rc_t (*epo_oui_get)(efx_nic_t *, uint32_t *);
221#if EFSYS_OPT_PHY_STATS
222 efx_rc_t (*epo_stats_update)(efx_nic_t *, efsys_mem_t *,
223 uint32_t *);
224#endif /* EFSYS_OPT_PHY_STATS */
225#if EFSYS_OPT_PHY_PROPS
226#if EFSYS_OPT_NAMES
227 const char *(*epo_prop_name)(efx_nic_t *, unsigned int);
228#endif /* EFSYS_OPT_PHY_PROPS */
229 efx_rc_t (*epo_prop_get)(efx_nic_t *, unsigned int, uint32_t,
230 uint32_t *);
231 efx_rc_t (*epo_prop_set)(efx_nic_t *, unsigned int, uint32_t);
232#endif /* EFSYS_OPT_PHY_PROPS */
233#if EFSYS_OPT_BIST
234 efx_rc_t (*epo_bist_enable_offline)(efx_nic_t *);
235 efx_rc_t (*epo_bist_start)(efx_nic_t *, efx_bist_type_t);
236 efx_rc_t (*epo_bist_poll)(efx_nic_t *, efx_bist_type_t,
237 efx_bist_result_t *, uint32_t *,
238 unsigned long *, size_t);
239 void (*epo_bist_stop)(efx_nic_t *, efx_bist_type_t);
240#endif /* EFSYS_OPT_BIST */
241} efx_phy_ops_t;
242
243#if EFSYS_OPT_FILTER
244typedef struct efx_filter_ops_s {
245 efx_rc_t (*efo_init)(efx_nic_t *);
246 void (*efo_fini)(efx_nic_t *);
247 efx_rc_t (*efo_restore)(efx_nic_t *);
248 efx_rc_t (*efo_add)(efx_nic_t *, efx_filter_spec_t *,
249 boolean_t may_replace);
250 efx_rc_t (*efo_delete)(efx_nic_t *, efx_filter_spec_t *);
251 efx_rc_t (*efo_supported_filters)(efx_nic_t *, uint32_t *, size_t *);
252 efx_rc_t (*efo_reconfigure)(efx_nic_t *, uint8_t const *, boolean_t,
253 boolean_t, boolean_t, boolean_t,
254 uint8_t const *, int);
255} efx_filter_ops_t;
256
257extern __checkReturn efx_rc_t
258efx_filter_reconfigure(
259 __in efx_nic_t *enp,
260 __in_ecount(6) uint8_t const *mac_addr,
261 __in boolean_t all_unicst,
262 __in boolean_t mulcst,
263 __in boolean_t all_mulcst,
264 __in boolean_t brdcst,
265 __in_ecount(6*count) uint8_t const *addrs,
266 __in int count);
267
268#endif /* EFSYS_OPT_FILTER */
269
270
271typedef struct efx_port_s {
272 efx_mac_type_t ep_mac_type;
273 uint32_t ep_phy_type;
274 uint8_t ep_port;
275 uint32_t ep_mac_pdu;
276 uint8_t ep_mac_addr[6];
277 efx_link_mode_t ep_link_mode;
278 boolean_t ep_all_unicst;
279 boolean_t ep_mulcst;
280 boolean_t ep_all_mulcst;
281 boolean_t ep_brdcst;
282 unsigned int ep_fcntl;
283 boolean_t ep_fcntl_autoneg;
284 efx_oword_t ep_multicst_hash[2];
285 uint8_t ep_mulcst_addr_list[EFX_MAC_ADDR_LEN *
286 EFX_MAC_MULTICAST_LIST_MAX];
287 uint32_t ep_mulcst_addr_count;
288#if EFSYS_OPT_LOOPBACK
289 efx_loopback_type_t ep_loopback_type;
290 efx_link_mode_t ep_loopback_link_mode;
291#endif /* EFSYS_OPT_LOOPBACK */
292#if EFSYS_OPT_PHY_FLAGS
293 uint32_t ep_phy_flags;
294#endif /* EFSYS_OPT_PHY_FLAGS */
295#if EFSYS_OPT_PHY_LED_CONTROL
296 efx_phy_led_mode_t ep_phy_led_mode;
297#endif /* EFSYS_OPT_PHY_LED_CONTROL */
298 efx_phy_media_type_t ep_fixed_port_type;
299 efx_phy_media_type_t ep_module_type;
300 uint32_t ep_adv_cap_mask;
301 uint32_t ep_lp_cap_mask;
302 uint32_t ep_default_adv_cap_mask;
303 uint32_t ep_phy_cap_mask;
304#if EFSYS_OPT_PHY_TXC43128 || EFSYS_OPT_PHY_QT2025C
305 union {
306 struct {
307 unsigned int bug10934_count;
308 } ep_txc43128;
309 struct {
310 unsigned int bug17190_count;
311 } ep_qt2025c;
312 };
313#endif
314 boolean_t ep_mac_poll_needed; /* falcon only */
315 boolean_t ep_mac_up; /* falcon only */
316 uint32_t ep_fwver; /* falcon only */
317 boolean_t ep_mac_drain;
318 boolean_t ep_mac_stats_pending;
319#if EFSYS_OPT_BIST
320 efx_bist_type_t ep_current_bist;
321#endif
322 efx_mac_ops_t *ep_emop;
323 efx_phy_ops_t *ep_epop;
324} efx_port_t;
325
326typedef struct efx_mon_ops_s {
327 efx_rc_t (*emo_reset)(efx_nic_t *);
328 efx_rc_t (*emo_reconfigure)(efx_nic_t *);
329#if EFSYS_OPT_MON_STATS
330 efx_rc_t (*emo_stats_update)(efx_nic_t *, efsys_mem_t *,
331 efx_mon_stat_value_t *);
332#endif /* EFSYS_OPT_MON_STATS */
333} efx_mon_ops_t;
334
335typedef struct efx_mon_s {
336 efx_mon_type_t em_type;
337 efx_mon_ops_t *em_emop;
338} efx_mon_t;
339
340typedef struct efx_intr_ops_s {
341 efx_rc_t (*eio_init)(efx_nic_t *, efx_intr_type_t, efsys_mem_t *);
342 void (*eio_enable)(efx_nic_t *);
343 void (*eio_disable)(efx_nic_t *);
344 void (*eio_disable_unlocked)(efx_nic_t *);
345 efx_rc_t (*eio_trigger)(efx_nic_t *, unsigned int);
346 void (*eio_status_line)(efx_nic_t *, boolean_t *, uint32_t *);
347 void (*eio_status_message)(efx_nic_t *, unsigned int,
348 boolean_t *);
349 void (*eio_fatal)(efx_nic_t *);
350 void (*eio_fini)(efx_nic_t *);
351} efx_intr_ops_t;
352
353typedef struct efx_intr_s {
354 efx_intr_ops_t *ei_eiop;
355 efsys_mem_t *ei_esmp;
356 efx_intr_type_t ei_type;
357 unsigned int ei_level;
358} efx_intr_t;
359
360typedef struct efx_nic_ops_s {
361 efx_rc_t (*eno_probe)(efx_nic_t *);
362 efx_rc_t (*eno_board_cfg)(efx_nic_t *);
363 efx_rc_t (*eno_set_drv_limits)(efx_nic_t *, efx_drv_limits_t*);
364 efx_rc_t (*eno_reset)(efx_nic_t *);
365 efx_rc_t (*eno_init)(efx_nic_t *);
366 efx_rc_t (*eno_get_vi_pool)(efx_nic_t *, uint32_t *);
367 efx_rc_t (*eno_get_bar_region)(efx_nic_t *, efx_nic_region_t,
368 uint32_t *, size_t *);
369#if EFSYS_OPT_DIAG
370 efx_rc_t (*eno_sram_test)(efx_nic_t *, efx_sram_pattern_fn_t);
371 efx_rc_t (*eno_register_test)(efx_nic_t *);
372#endif /* EFSYS_OPT_DIAG */
373 void (*eno_fini)(efx_nic_t *);
374 void (*eno_unprobe)(efx_nic_t *);
375} efx_nic_ops_t;
376
377#ifndef EFX_TXQ_LIMIT_TARGET
378#define EFX_TXQ_LIMIT_TARGET 259
379#endif
380#ifndef EFX_RXQ_LIMIT_TARGET
381#define EFX_RXQ_LIMIT_TARGET 512
382#endif
383#ifndef EFX_TXQ_DC_SIZE
384#define EFX_TXQ_DC_SIZE 1 /* 16 descriptors */
385#endif
386#ifndef EFX_RXQ_DC_SIZE
387#define EFX_RXQ_DC_SIZE 3 /* 64 descriptors */
388#endif
389
390#if EFSYS_OPT_FILTER
391
392typedef struct falconsiena_filter_spec_s {
393 uint8_t fsfs_type;
394 uint32_t fsfs_flags;
395 uint32_t fsfs_dmaq_id;
396 uint32_t fsfs_dword[3];
397} falconsiena_filter_spec_t;
398
399typedef enum falconsiena_filter_type_e {
400 EFX_FS_FILTER_RX_TCP_FULL, /* TCP/IPv4 4-tuple {dIP,dTCP,sIP,sTCP} */
401 EFX_FS_FILTER_RX_TCP_WILD, /* TCP/IPv4 dest {dIP,dTCP, -, -} */
402 EFX_FS_FILTER_RX_UDP_FULL, /* UDP/IPv4 4-tuple {dIP,dUDP,sIP,sUDP} */
403 EFX_FS_FILTER_RX_UDP_WILD, /* UDP/IPv4 dest {dIP,dUDP, -, -} */
404
405#if EFSYS_OPT_SIENA
406 EFX_FS_FILTER_RX_MAC_FULL, /* Ethernet {dMAC,VLAN} */
407 EFX_FS_FILTER_RX_MAC_WILD, /* Ethernet {dMAC, -} */
408
409 EFX_FS_FILTER_TX_TCP_FULL, /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */
410 EFX_FS_FILTER_TX_TCP_WILD, /* TCP/IPv4 { -, -,sIP,sTCP} */
411 EFX_FS_FILTER_TX_UDP_FULL, /* UDP/IPv4 {dIP,dTCP,sIP,sTCP} */
412 EFX_FS_FILTER_TX_UDP_WILD, /* UDP/IPv4 source (host, port) */
413
414 EFX_FS_FILTER_TX_MAC_FULL, /* Ethernet source (MAC address, VLAN ID) */
415 EFX_FS_FILTER_TX_MAC_WILD, /* Ethernet source (MAC address) */
416#endif /* EFSYS_OPT_SIENA */
417
418 EFX_FS_FILTER_NTYPES
419} falconsiena_filter_type_t;
420
421typedef enum falconsiena_filter_tbl_id_e {
422 EFX_FS_FILTER_TBL_RX_IP = 0,
423 EFX_FS_FILTER_TBL_RX_MAC,
424 EFX_FS_FILTER_TBL_TX_IP,
425 EFX_FS_FILTER_TBL_TX_MAC,
426 EFX_FS_FILTER_NTBLS
427} falconsiena_filter_tbl_id_t;
428
429typedef struct falconsiena_filter_tbl_s {
430 int fsft_size; /* number of entries */
431 int fsft_used; /* active count */
432 uint32_t *fsft_bitmap; /* active bitmap */
433 falconsiena_filter_spec_t *fsft_spec; /* array of saved specs */
434} falconsiena_filter_tbl_t;
435
436typedef struct falconsiena_filter_s {
437 falconsiena_filter_tbl_t fsf_tbl[EFX_FS_FILTER_NTBLS];
438 unsigned int fsf_depth[EFX_FS_FILTER_NTYPES];
439} falconsiena_filter_t;
440
441typedef struct efx_filter_s {
|
446#if EFSYS_OPT_FALCON || EFSYS_OPT_SIENA
|
| 442#if EFSYS_OPT_SIENA |
443 falconsiena_filter_t *ef_falconsiena_filter;
|
448#endif /* EFSYS_OPT_FALCON || EFSYS_OPT_SIENA */
|
| 444#endif /* EFSYS_OPT_SIENA */ |
445#if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
446 ef10_filter_table_t *ef_ef10_filter_table;
447#endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */
448} efx_filter_t;
449
450extern void
451falconsiena_filter_tbl_clear(
452 __in efx_nic_t *enp,
453 __in falconsiena_filter_tbl_id_t tbl);
454
455#endif /* EFSYS_OPT_FILTER */
456
457#if EFSYS_OPT_MCDI
458
459typedef struct efx_mcdi_ops_s {
460 efx_rc_t (*emco_init)(efx_nic_t *, const efx_mcdi_transport_t *);
461 void (*emco_send_request)(efx_nic_t *, void *, size_t,
462 void *, size_t);
463 efx_rc_t (*emco_poll_reboot)(efx_nic_t *);
464 boolean_t (*emco_poll_response)(efx_nic_t *);
465 void (*emco_read_response)(efx_nic_t *, void *, size_t, size_t);
466 void (*emco_fini)(efx_nic_t *);
467 efx_rc_t (*emco_feature_supported)(efx_nic_t *, efx_mcdi_feature_id_t, boolean_t *);
468} efx_mcdi_ops_t;
469
470typedef struct efx_mcdi_s {
471 efx_mcdi_ops_t *em_emcop;
472 const efx_mcdi_transport_t *em_emtp;
473 efx_mcdi_iface_t em_emip;
474} efx_mcdi_t;
475
476#endif /* EFSYS_OPT_MCDI */
477
478#if EFSYS_OPT_NVRAM
479typedef struct efx_nvram_ops_s {
480#if EFSYS_OPT_DIAG
481 efx_rc_t (*envo_test)(efx_nic_t *);
482#endif /* EFSYS_OPT_DIAG */
483 efx_rc_t (*envo_type_to_partn)(efx_nic_t *, efx_nvram_type_t,
484 uint32_t *);
485 efx_rc_t (*envo_partn_size)(efx_nic_t *, uint32_t, size_t *);
486 efx_rc_t (*envo_partn_rw_start)(efx_nic_t *, uint32_t, size_t *);
487 efx_rc_t (*envo_partn_read)(efx_nic_t *, uint32_t,
488 unsigned int, caddr_t, size_t);
489 efx_rc_t (*envo_partn_erase)(efx_nic_t *, uint32_t,
490 unsigned int, size_t);
491 efx_rc_t (*envo_partn_write)(efx_nic_t *, uint32_t,
492 unsigned int, caddr_t, size_t);
493 void (*envo_partn_rw_finish)(efx_nic_t *, uint32_t);
494 efx_rc_t (*envo_partn_get_version)(efx_nic_t *, uint32_t,
495 uint32_t *, uint16_t *);
496 efx_rc_t (*envo_partn_set_version)(efx_nic_t *, uint32_t,
497 uint16_t *);
498 efx_rc_t (*envo_buffer_validate)(efx_nic_t *, uint32_t,
499 caddr_t, size_t);
500} efx_nvram_ops_t;
501#endif /* EFSYS_OPT_NVRAM */
502
503extern __checkReturn efx_rc_t
504efx_nvram_tlv_validate(
505 __in efx_nic_t *enp,
506 __in uint32_t partn,
507 __in_bcount(partn_size) caddr_t partn_data,
508 __in size_t partn_size);
509
510
511#if EFSYS_OPT_VPD
512typedef struct efx_vpd_ops_s {
513 efx_rc_t (*evpdo_init)(efx_nic_t *);
514 efx_rc_t (*evpdo_size)(efx_nic_t *, size_t *);
515 efx_rc_t (*evpdo_read)(efx_nic_t *, caddr_t, size_t);
516 efx_rc_t (*evpdo_verify)(efx_nic_t *, caddr_t, size_t);
517 efx_rc_t (*evpdo_reinit)(efx_nic_t *, caddr_t, size_t);
518 efx_rc_t (*evpdo_get)(efx_nic_t *, caddr_t, size_t,
519 efx_vpd_value_t *);
520 efx_rc_t (*evpdo_set)(efx_nic_t *, caddr_t, size_t,
521 efx_vpd_value_t *);
522 efx_rc_t (*evpdo_next)(efx_nic_t *, caddr_t, size_t,
523 efx_vpd_value_t *, unsigned int *);
524 efx_rc_t (*evpdo_write)(efx_nic_t *, caddr_t, size_t);
525 void (*evpdo_fini)(efx_nic_t *);
526} efx_vpd_ops_t;
527#endif /* EFSYS_OPT_VPD */
528
529#if EFSYS_OPT_VPD || EFSYS_OPT_NVRAM
530
531 __checkReturn efx_rc_t
532efx_mcdi_nvram_partitions(
533 __in efx_nic_t *enp,
534 __out_bcount(size) caddr_t data,
535 __in size_t size,
536 __out unsigned int *npartnp);
537
538 __checkReturn efx_rc_t
539efx_mcdi_nvram_metadata(
540 __in efx_nic_t *enp,
541 __in uint32_t partn,
542 __out uint32_t *subtypep,
543 __out_ecount(4) uint16_t version[4],
544 __out_bcount_opt(size) char *descp,
545 __in size_t size);
546
547 __checkReturn efx_rc_t
548efx_mcdi_nvram_info(
549 __in efx_nic_t *enp,
550 __in uint32_t partn,
551 __out_opt size_t *sizep,
552 __out_opt uint32_t *addressp,
553 __out_opt uint32_t *erase_sizep,
554 __out_opt uint32_t *write_sizep);
555
556 __checkReturn efx_rc_t
557efx_mcdi_nvram_update_start(
558 __in efx_nic_t *enp,
559 __in uint32_t partn);
560
561 __checkReturn efx_rc_t
562efx_mcdi_nvram_read(
563 __in efx_nic_t *enp,
564 __in uint32_t partn,
565 __in uint32_t offset,
566 __out_bcount(size) caddr_t data,
567 __in size_t size,
568 __in uint32_t mode);
569
570 __checkReturn efx_rc_t
571efx_mcdi_nvram_erase(
572 __in efx_nic_t *enp,
573 __in uint32_t partn,
574 __in uint32_t offset,
575 __in size_t size);
576
577 __checkReturn efx_rc_t
578efx_mcdi_nvram_write(
579 __in efx_nic_t *enp,
580 __in uint32_t partn,
581 __in uint32_t offset,
582 __out_bcount(size) caddr_t data,
583 __in size_t size);
584
585 __checkReturn efx_rc_t
586efx_mcdi_nvram_update_finish(
587 __in efx_nic_t *enp,
588 __in uint32_t partn,
589 __in boolean_t reboot);
590
591#if EFSYS_OPT_DIAG
592
593 __checkReturn efx_rc_t
594efx_mcdi_nvram_test(
595 __in efx_nic_t *enp,
596 __in uint32_t partn);
597
598#endif /* EFSYS_OPT_DIAG */
599
600#endif /* EFSYS_OPT_VPD || EFSYS_OPT_NVRAM */
601
602#if EFSYS_OPT_LICENSING
603
604typedef struct efx_lic_ops_s {
605 efx_rc_t (*elo_update_licenses)(efx_nic_t *);
606 efx_rc_t (*elo_get_key_stats)(efx_nic_t *, efx_key_stats_t *);
607 efx_rc_t (*elo_app_state)(efx_nic_t *, uint64_t, boolean_t *);
608 efx_rc_t (*elo_get_id)(efx_nic_t *, size_t, uint32_t *,
609 size_t *, uint8_t *);
610} efx_lic_ops_t;
611
612#endif
613
614typedef struct efx_drv_cfg_s {
615 uint32_t edc_min_vi_count;
616 uint32_t edc_max_vi_count;
617
618 uint32_t edc_max_piobuf_count;
619 uint32_t edc_pio_alloc_size;
620} efx_drv_cfg_t;
621
622struct efx_nic_s {
623 uint32_t en_magic;
624 efx_family_t en_family;
625 uint32_t en_features;
626 efsys_identifier_t *en_esip;
627 efsys_lock_t *en_eslp;
628 efsys_bar_t *en_esbp;
629 unsigned int en_mod_flags;
630 unsigned int en_reset_flags;
631 efx_nic_cfg_t en_nic_cfg;
632 efx_drv_cfg_t en_drv_cfg;
633 efx_port_t en_port;
634 efx_mon_t en_mon;
635 efx_intr_t en_intr;
636 uint32_t en_ev_qcount;
637 uint32_t en_rx_qcount;
638 uint32_t en_tx_qcount;
639 efx_nic_ops_t *en_enop;
640 efx_ev_ops_t *en_eevop;
641 efx_tx_ops_t *en_etxop;
642 efx_rx_ops_t *en_erxop;
643#if EFSYS_OPT_FILTER
644 efx_filter_t en_filter;
645 efx_filter_ops_t *en_efop;
646#endif /* EFSYS_OPT_FILTER */
647#if EFSYS_OPT_MCDI
648 efx_mcdi_t en_mcdi;
649#endif /* EFSYS_OPT_MCDI */
650#if EFSYS_OPT_NVRAM
651 efx_nvram_type_t en_nvram_locked;
652 efx_nvram_ops_t *en_envop;
653#endif /* EFSYS_OPT_NVRAM */
654#if EFSYS_OPT_VPD
655 efx_vpd_ops_t *en_evpdop;
656#endif /* EFSYS_OPT_VPD */
657#if EFSYS_OPT_RX_SCALE
658 efx_rx_hash_support_t en_hash_support;
659 efx_rx_scale_support_t en_rss_support;
660 uint32_t en_rss_context;
661#endif /* EFSYS_OPT_RX_SCALE */
662 uint32_t en_vport_id;
663#if EFSYS_OPT_LICENSING
664 efx_lic_ops_t *en_elop;
665#endif
666 union {
|
671#if EFSYS_OPT_FALCON
672 struct {
673 falcon_spi_dev_t enu_fsd[FALCON_SPI_NTYPES];
674 falcon_i2c_t enu_fip;
675 boolean_t enu_i2c_locked;
676#if EFSYS_OPT_FALCON_NIC_CFG_OVERRIDE
677 const uint8_t *enu_forced_cfg;
678#endif /* EFSYS_OPT_FALCON_NIC_CFG_OVERRIDE */
679 uint8_t enu_mon_devid;
680 uint16_t enu_board_rev;
681 boolean_t enu_internal_sram;
682 uint8_t enu_sram_num_bank;
683 uint8_t enu_sram_bank_size;
684 } falcon;
685#endif /* EFSYS_OPT_FALCON */
|
667#if EFSYS_OPT_SIENA
668 struct {
669#if EFSYS_OPT_NVRAM || EFSYS_OPT_VPD
670 unsigned int enu_partn_mask;
671#endif /* EFSYS_OPT_NVRAM || EFSYS_OPT_VPD */
672#if EFSYS_OPT_VPD
673 caddr_t enu_svpd;
674 size_t enu_svpd_length;
675#endif /* EFSYS_OPT_VPD */
676 int enu_unused;
677 } siena;
678#endif /* EFSYS_OPT_SIENA */
679 int enu_unused;
680 } en_u;
681#if (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD)
682 union en_arch {
683 struct {
684 int ena_vi_base;
685 int ena_vi_count;
686 int ena_vi_shift;
687#if EFSYS_OPT_VPD
688 caddr_t ena_svpd;
689 size_t ena_svpd_length;
690#endif /* EFSYS_OPT_VPD */
691 efx_piobuf_handle_t ena_piobuf_handle[EF10_MAX_PIOBUF_NBUFS];
692 uint32_t ena_piobuf_count;
693 uint32_t ena_pio_alloc_map[EF10_MAX_PIOBUF_NBUFS];
694 uint32_t ena_pio_write_vi_base;
695 /* Memory BAR mapping regions */
696 uint32_t ena_uc_mem_map_offset;
697 size_t ena_uc_mem_map_size;
698 uint32_t ena_wc_mem_map_offset;
699 size_t ena_wc_mem_map_size;
700 } ef10;
701 } en_arch;
702#endif /* (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD) */
703};
704
705
706#define EFX_NIC_MAGIC 0x02121996
707
708typedef boolean_t (*efx_ev_handler_t)(efx_evq_t *, efx_qword_t *,
709 const efx_ev_callbacks_t *, void *);
710
711typedef struct efx_evq_rxq_state_s {
712 unsigned int eers_rx_read_ptr;
713 unsigned int eers_rx_mask;
714} efx_evq_rxq_state_t;
715
716struct efx_evq_s {
717 uint32_t ee_magic;
718 efx_nic_t *ee_enp;
719 unsigned int ee_index;
720 unsigned int ee_mask;
721 efsys_mem_t *ee_esmp;
722#if EFSYS_OPT_QSTATS
723 uint32_t ee_stat[EV_NQSTATS];
724#endif /* EFSYS_OPT_QSTATS */
725
726 efx_ev_handler_t ee_rx;
727 efx_ev_handler_t ee_tx;
728 efx_ev_handler_t ee_driver;
729 efx_ev_handler_t ee_global;
730 efx_ev_handler_t ee_drv_gen;
731#if EFSYS_OPT_MCDI
732 efx_ev_handler_t ee_mcdi;
733#endif /* EFSYS_OPT_MCDI */
734
735 efx_evq_rxq_state_t ee_rxq_state[EFX_EV_RX_NLABELS];
736};
737
738#define EFX_EVQ_MAGIC 0x08081997
739
740#define EFX_EVQ_FALCON_TIMER_QUANTUM_NS 4968 /* 621 cycles */
741#define EFX_EVQ_SIENA_TIMER_QUANTUM_NS 6144 /* 768 cycles */
742
743struct efx_rxq_s {
744 uint32_t er_magic;
745 efx_nic_t *er_enp;
746 efx_evq_t *er_eep;
747 unsigned int er_index;
748 unsigned int er_label;
749 unsigned int er_mask;
750 efsys_mem_t *er_esmp;
751};
752
753#define EFX_RXQ_MAGIC 0x15022005
754
755struct efx_txq_s {
756 uint32_t et_magic;
757 efx_nic_t *et_enp;
758 unsigned int et_index;
759 unsigned int et_mask;
760 efsys_mem_t *et_esmp;
761#if EFSYS_OPT_HUNTINGTON
762 uint32_t et_pio_bufnum;
763 uint32_t et_pio_blknum;
764 uint32_t et_pio_write_offset;
765 uint32_t et_pio_offset;
766 size_t et_pio_size;
767#endif
768#if EFSYS_OPT_QSTATS
769 uint32_t et_stat[TX_NQSTATS];
770#endif /* EFSYS_OPT_QSTATS */
771};
772
773#define EFX_TXQ_MAGIC 0x05092005
774
775#define EFX_MAC_ADDR_COPY(_dst, _src) \
776 do { \
777 (_dst)[0] = (_src)[0]; \
778 (_dst)[1] = (_src)[1]; \
779 (_dst)[2] = (_src)[2]; \
780 (_dst)[3] = (_src)[3]; \
781 (_dst)[4] = (_src)[4]; \
782 (_dst)[5] = (_src)[5]; \
783 _NOTE(CONSTANTCONDITION) \
784 } while (B_FALSE)
785
786#define EFX_MAC_BROADCAST_ADDR_SET(_dst) \
787 do { \
788 uint16_t *_d = (uint16_t *)(_dst); \
789 _d[0] = 0xffff; \
790 _d[1] = 0xffff; \
791 _d[2] = 0xffff; \
792 _NOTE(CONSTANTCONDITION) \
793 } while (B_FALSE)
794
795#if EFSYS_OPT_CHECK_REG
796#define EFX_CHECK_REG(_enp, _reg) \
797 do { \
798 const char *name = #_reg; \
799 char min = name[4]; \
800 char max = name[5]; \
801 char rev; \
802 \
803 switch ((_enp)->en_family) { \
804 case EFX_FAMILY_FALCON: \
805 rev = 'B'; \
806 break; \
807 \
808 case EFX_FAMILY_SIENA: \
809 rev = 'C'; \
810 break; \
811 \
812 case EFX_FAMILY_HUNTINGTON: \
813 rev = 'D'; \
814 break; \
815 \
816 case EFX_FAMILY_MEDFORD: \
817 rev = 'E'; \
818 break; \
819 \
820 default: \
821 rev = '?'; \
822 break; \
823 } \
824 \
825 EFSYS_ASSERT3S(rev, >=, min); \
826 EFSYS_ASSERT3S(rev, <=, max); \
827 \
828 _NOTE(CONSTANTCONDITION) \
829 } while (B_FALSE)
830#else
831#define EFX_CHECK_REG(_enp, _reg) do { \
832 _NOTE(CONSTANTCONDITION) \
833 } while(B_FALSE)
834#endif
835
836#define EFX_BAR_READD(_enp, _reg, _edp, _lock) \
837 do { \
838 EFX_CHECK_REG((_enp), (_reg)); \
839 EFSYS_BAR_READD((_enp)->en_esbp, _reg ## _OFST, \
840 (_edp), (_lock)); \
841 EFSYS_PROBE3(efx_bar_readd, const char *, #_reg, \
842 uint32_t, _reg ## _OFST, \
843 uint32_t, (_edp)->ed_u32[0]); \
844 _NOTE(CONSTANTCONDITION) \
845 } while (B_FALSE)
846
847#define EFX_BAR_WRITED(_enp, _reg, _edp, _lock) \
848 do { \
849 EFX_CHECK_REG((_enp), (_reg)); \
850 EFSYS_PROBE3(efx_bar_writed, const char *, #_reg, \
851 uint32_t, _reg ## _OFST, \
852 uint32_t, (_edp)->ed_u32[0]); \
853 EFSYS_BAR_WRITED((_enp)->en_esbp, _reg ## _OFST, \
854 (_edp), (_lock)); \
855 _NOTE(CONSTANTCONDITION) \
856 } while (B_FALSE)
857
858#define EFX_BAR_READQ(_enp, _reg, _eqp) \
859 do { \
860 EFX_CHECK_REG((_enp), (_reg)); \
861 EFSYS_BAR_READQ((_enp)->en_esbp, _reg ## _OFST, \
862 (_eqp)); \
863 EFSYS_PROBE4(efx_bar_readq, const char *, #_reg, \
864 uint32_t, _reg ## _OFST, \
865 uint32_t, (_eqp)->eq_u32[1], \
866 uint32_t, (_eqp)->eq_u32[0]); \
867 _NOTE(CONSTANTCONDITION) \
868 } while (B_FALSE)
869
870#define EFX_BAR_WRITEQ(_enp, _reg, _eqp) \
871 do { \
872 EFX_CHECK_REG((_enp), (_reg)); \
873 EFSYS_PROBE4(efx_bar_writeq, const char *, #_reg, \
874 uint32_t, _reg ## _OFST, \
875 uint32_t, (_eqp)->eq_u32[1], \
876 uint32_t, (_eqp)->eq_u32[0]); \
877 EFSYS_BAR_WRITEQ((_enp)->en_esbp, _reg ## _OFST, \
878 (_eqp)); \
879 _NOTE(CONSTANTCONDITION) \
880 } while (B_FALSE)
881
882#define EFX_BAR_READO(_enp, _reg, _eop) \
883 do { \
884 EFX_CHECK_REG((_enp), (_reg)); \
885 EFSYS_BAR_READO((_enp)->en_esbp, _reg ## _OFST, \
886 (_eop), B_TRUE); \
887 EFSYS_PROBE6(efx_bar_reado, const char *, #_reg, \
888 uint32_t, _reg ## _OFST, \
889 uint32_t, (_eop)->eo_u32[3], \
890 uint32_t, (_eop)->eo_u32[2], \
891 uint32_t, (_eop)->eo_u32[1], \
892 uint32_t, (_eop)->eo_u32[0]); \
893 _NOTE(CONSTANTCONDITION) \
894 } while (B_FALSE)
895
896#define EFX_BAR_WRITEO(_enp, _reg, _eop) \
897 do { \
898 EFX_CHECK_REG((_enp), (_reg)); \
899 EFSYS_PROBE6(efx_bar_writeo, const char *, #_reg, \
900 uint32_t, _reg ## _OFST, \
901 uint32_t, (_eop)->eo_u32[3], \
902 uint32_t, (_eop)->eo_u32[2], \
903 uint32_t, (_eop)->eo_u32[1], \
904 uint32_t, (_eop)->eo_u32[0]); \
905 EFSYS_BAR_WRITEO((_enp)->en_esbp, _reg ## _OFST, \
906 (_eop), B_TRUE); \
907 _NOTE(CONSTANTCONDITION) \
908 } while (B_FALSE)
909
910#define EFX_BAR_TBL_READD(_enp, _reg, _index, _edp, _lock) \
911 do { \
912 EFX_CHECK_REG((_enp), (_reg)); \
913 EFSYS_BAR_READD((_enp)->en_esbp, \
914 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
915 (_edp), (_lock)); \
916 EFSYS_PROBE4(efx_bar_tbl_readd, const char *, #_reg, \
917 uint32_t, (_index), \
918 uint32_t, _reg ## _OFST, \
919 uint32_t, (_edp)->ed_u32[0]); \
920 _NOTE(CONSTANTCONDITION) \
921 } while (B_FALSE)
922
923#define EFX_BAR_TBL_WRITED(_enp, _reg, _index, _edp, _lock) \
924 do { \
925 EFX_CHECK_REG((_enp), (_reg)); \
926 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg, \
927 uint32_t, (_index), \
928 uint32_t, _reg ## _OFST, \
929 uint32_t, (_edp)->ed_u32[0]); \
930 EFSYS_BAR_WRITED((_enp)->en_esbp, \
931 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
932 (_edp), (_lock)); \
933 _NOTE(CONSTANTCONDITION) \
934 } while (B_FALSE)
935
936#define EFX_BAR_TBL_WRITED2(_enp, _reg, _index, _edp, _lock) \
937 do { \
938 EFX_CHECK_REG((_enp), (_reg)); \
939 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg, \
940 uint32_t, (_index), \
941 uint32_t, _reg ## _OFST, \
942 uint32_t, (_edp)->ed_u32[0]); \
943 EFSYS_BAR_WRITED((_enp)->en_esbp, \
944 (_reg ## _OFST + \
945 (2 * sizeof (efx_dword_t)) + \
946 ((_index) * _reg ## _STEP)), \
947 (_edp), (_lock)); \
948 _NOTE(CONSTANTCONDITION) \
949 } while (B_FALSE)
950
951#define EFX_BAR_TBL_WRITED3(_enp, _reg, _index, _edp, _lock) \
952 do { \
953 EFX_CHECK_REG((_enp), (_reg)); \
954 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg, \
955 uint32_t, (_index), \
956 uint32_t, _reg ## _OFST, \
957 uint32_t, (_edp)->ed_u32[0]); \
958 EFSYS_BAR_WRITED((_enp)->en_esbp, \
959 (_reg ## _OFST + \
960 (3 * sizeof (efx_dword_t)) + \
961 ((_index) * _reg ## _STEP)), \
962 (_edp), (_lock)); \
963 _NOTE(CONSTANTCONDITION) \
964 } while (B_FALSE)
965
966#define EFX_BAR_TBL_READQ(_enp, _reg, _index, _eqp) \
967 do { \
968 EFX_CHECK_REG((_enp), (_reg)); \
969 EFSYS_BAR_READQ((_enp)->en_esbp, \
970 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
971 (_eqp)); \
972 EFSYS_PROBE5(efx_bar_tbl_readq, const char *, #_reg, \
973 uint32_t, (_index), \
974 uint32_t, _reg ## _OFST, \
975 uint32_t, (_eqp)->eq_u32[1], \
976 uint32_t, (_eqp)->eq_u32[0]); \
977 _NOTE(CONSTANTCONDITION) \
978 } while (B_FALSE)
979
980#define EFX_BAR_TBL_WRITEQ(_enp, _reg, _index, _eqp) \
981 do { \
982 EFX_CHECK_REG((_enp), (_reg)); \
983 EFSYS_PROBE5(efx_bar_tbl_writeq, const char *, #_reg, \
984 uint32_t, (_index), \
985 uint32_t, _reg ## _OFST, \
986 uint32_t, (_eqp)->eq_u32[1], \
987 uint32_t, (_eqp)->eq_u32[0]); \
988 EFSYS_BAR_WRITEQ((_enp)->en_esbp, \
989 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
990 (_eqp)); \
991 _NOTE(CONSTANTCONDITION) \
992 } while (B_FALSE)
993
994#define EFX_BAR_TBL_READO(_enp, _reg, _index, _eop, _lock) \
995 do { \
996 EFX_CHECK_REG((_enp), (_reg)); \
997 EFSYS_BAR_READO((_enp)->en_esbp, \
998 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
999 (_eop), (_lock)); \
1000 EFSYS_PROBE7(efx_bar_tbl_reado, const char *, #_reg, \
1001 uint32_t, (_index), \
1002 uint32_t, _reg ## _OFST, \
1003 uint32_t, (_eop)->eo_u32[3], \
1004 uint32_t, (_eop)->eo_u32[2], \
1005 uint32_t, (_eop)->eo_u32[1], \
1006 uint32_t, (_eop)->eo_u32[0]); \
1007 _NOTE(CONSTANTCONDITION) \
1008 } while (B_FALSE)
1009
1010#define EFX_BAR_TBL_WRITEO(_enp, _reg, _index, _eop, _lock) \
1011 do { \
1012 EFX_CHECK_REG((_enp), (_reg)); \
1013 EFSYS_PROBE7(efx_bar_tbl_writeo, const char *, #_reg, \
1014 uint32_t, (_index), \
1015 uint32_t, _reg ## _OFST, \
1016 uint32_t, (_eop)->eo_u32[3], \
1017 uint32_t, (_eop)->eo_u32[2], \
1018 uint32_t, (_eop)->eo_u32[1], \
1019 uint32_t, (_eop)->eo_u32[0]); \
1020 EFSYS_BAR_WRITEO((_enp)->en_esbp, \
1021 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
1022 (_eop), (_lock)); \
1023 _NOTE(CONSTANTCONDITION) \
1024 } while (B_FALSE)
1025
1026/*
1027 * Allow drivers to perform optimised 128-bit doorbell writes.
1028 * The DMA descriptor pointers (RX_DESC_UPD and TX_DESC_UPD) are
1029 * special-cased in the BIU on the Falcon/Siena and EF10 architectures to avoid
1030 * the need for locking in the host, and are the only ones known to be safe to
1031 * use 128-bites write with.
1032 */
1033#define EFX_BAR_TBL_DOORBELL_WRITEO(_enp, _reg, _index, _eop) \
1034 do { \
1035 EFX_CHECK_REG((_enp), (_reg)); \
1036 EFSYS_PROBE7(efx_bar_tbl_doorbell_writeo, \
1037 const char *, \
1038 #_reg, \
1039 uint32_t, (_index), \
1040 uint32_t, _reg ## _OFST, \
1041 uint32_t, (_eop)->eo_u32[3], \
1042 uint32_t, (_eop)->eo_u32[2], \
1043 uint32_t, (_eop)->eo_u32[1], \
1044 uint32_t, (_eop)->eo_u32[0]); \
1045 EFSYS_BAR_DOORBELL_WRITEO((_enp)->en_esbp, \
1046 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
1047 (_eop)); \
1048 _NOTE(CONSTANTCONDITION) \
1049 } while (B_FALSE)
1050
1051#define EFX_DMA_SYNC_QUEUE_FOR_DEVICE(_esmp, _entries, _wptr, _owptr) \
1052 do { \
1053 unsigned int _new = (_wptr); \
1054 unsigned int _old = (_owptr); \
1055 \
1056 if ((_new) >= (_old)) \
1057 EFSYS_DMA_SYNC_FOR_DEVICE((_esmp), \
1058 (_old) * sizeof (efx_desc_t), \
1059 ((_new) - (_old)) * sizeof (efx_desc_t)); \
1060 else \
1061 /* \
1062 * It is cheaper to sync entire map than sync \
1063 * two parts especially when offset/size are \
1064 * ignored and entire map is synced in any case.\
1065 */ \
1066 EFSYS_DMA_SYNC_FOR_DEVICE((_esmp), \
1067 0, \
1068 (_entries) * sizeof (efx_desc_t)); \
1069 _NOTE(CONSTANTCONDITION) \
1070 } while (B_FALSE)
1071
1072extern __checkReturn efx_rc_t
1073efx_nic_biu_test(
1074 __in efx_nic_t *enp);
1075
1076extern __checkReturn efx_rc_t
1077efx_mac_select(
1078 __in efx_nic_t *enp);
1079
1080extern void
1081efx_mac_multicast_hash_compute(
1082 __in_ecount(6*count) uint8_t const *addrs,
1083 __in int count,
1084 __out efx_oword_t *hash_low,
1085 __out efx_oword_t *hash_high);
1086
1087extern __checkReturn efx_rc_t
1088efx_phy_probe(
1089 __in efx_nic_t *enp);
1090
1091extern void
1092efx_phy_unprobe(
1093 __in efx_nic_t *enp);
1094
1095#if EFSYS_OPT_VPD
1096
1097/* VPD utility functions */
1098
1099extern __checkReturn efx_rc_t
1100efx_vpd_hunk_length(
1101 __in_bcount(size) caddr_t data,
1102 __in size_t size,
1103 __out size_t *lengthp);
1104
1105extern __checkReturn efx_rc_t
1106efx_vpd_hunk_verify(
1107 __in_bcount(size) caddr_t data,
1108 __in size_t size,
1109 __out_opt boolean_t *cksummedp);
1110
1111extern __checkReturn efx_rc_t
1112efx_vpd_hunk_reinit(
1113 __in_bcount(size) caddr_t data,
1114 __in size_t size,
1115 __in boolean_t wantpid);
1116
1117extern __checkReturn efx_rc_t
1118efx_vpd_hunk_get(
1119 __in_bcount(size) caddr_t data,
1120 __in size_t size,
1121 __in efx_vpd_tag_t tag,
1122 __in efx_vpd_keyword_t keyword,
1123 __out unsigned int *payloadp,
1124 __out uint8_t *paylenp);
1125
1126extern __checkReturn efx_rc_t
1127efx_vpd_hunk_next(
1128 __in_bcount(size) caddr_t data,
1129 __in size_t size,
1130 __out efx_vpd_tag_t *tagp,
1131 __out efx_vpd_keyword_t *keyword,
1132 __out_opt unsigned int *payloadp,
1133 __out_opt uint8_t *paylenp,
1134 __inout unsigned int *contp);
1135
1136extern __checkReturn efx_rc_t
1137efx_vpd_hunk_set(
1138 __in_bcount(size) caddr_t data,
1139 __in size_t size,
1140 __in efx_vpd_value_t *evvp);
1141
1142#endif /* EFSYS_OPT_VPD */
1143
1144#if EFSYS_OPT_DIAG
1145
1146extern efx_sram_pattern_fn_t __efx_sram_pattern_fns[];
1147
1148typedef struct efx_register_set_s {
1149 unsigned int address;
1150 unsigned int step;
1151 unsigned int rows;
1152 efx_oword_t mask;
1153} efx_register_set_t;
1154
1155extern __checkReturn efx_rc_t
1156efx_nic_test_registers(
1157 __in efx_nic_t *enp,
1158 __in efx_register_set_t *rsp,
1159 __in size_t count);
1160
1161extern __checkReturn efx_rc_t
1162efx_nic_test_tables(
1163 __in efx_nic_t *enp,
1164 __in efx_register_set_t *rsp,
1165 __in efx_pattern_type_t pattern,
1166 __in size_t count);
1167
1168#endif /* EFSYS_OPT_DIAG */
1169
1170#if EFSYS_OPT_MCDI
1171
1172extern __checkReturn efx_rc_t
1173efx_mcdi_set_workaround(
1174 __in efx_nic_t *enp,
1175 __in uint32_t type,
1176 __in boolean_t enabled,
1177 __out_opt uint32_t *flagsp);
1178
1179extern __checkReturn efx_rc_t
1180efx_mcdi_get_workarounds(
1181 __in efx_nic_t *enp,
1182 __out_opt uint32_t *implementedp,
1183 __out_opt uint32_t *enabledp);
1184
1185#endif /* EFSYS_OPT_MCDI */
1186
1187#ifdef __cplusplus
1188}
1189#endif
1190
1191#endif /* _SYS_EFX_IMPL_H */
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