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efx_impl.h (293889) efx_impl.h (293891)
1/*-
2 * Copyright (c) 2007-2015 Solarflare Communications Inc.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 *
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
18 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
19 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
21 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
22 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
23 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
24 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 *
26 * The views and conclusions contained in the software and documentation are
27 * those of the authors and should not be interpreted as representing official
28 * policies, either expressed or implied, of the FreeBSD Project.
29 *
1/*-
2 * Copyright (c) 2007-2015 Solarflare Communications Inc.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 *
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
18 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
19 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
21 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
22 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
23 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
24 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 *
26 * The views and conclusions contained in the software and documentation are
27 * those of the authors and should not be interpreted as representing official
28 * policies, either expressed or implied, of the FreeBSD Project.
29 *
30 * $FreeBSD: head/sys/dev/sfxge/common/efx_impl.h 293889 2016-01-14 09:01:53Z arybchik $
30 * $FreeBSD: head/sys/dev/sfxge/common/efx_impl.h 293891 2016-01-14 09:05:51Z arybchik $
31 */
32
33#ifndef _SYS_EFX_IMPL_H
34#define _SYS_EFX_IMPL_H
35
36#include "efsys.h"
37#include "efx.h"
38#include "efx_regs.h"
39#include "efx_regs_ef10.h"
40
41/* FIXME: Add definition for driver generated software events */
42#ifndef ESE_DZ_EV_CODE_DRV_GEN_EV
43#define ESE_DZ_EV_CODE_DRV_GEN_EV FSE_AZ_EV_CODE_DRV_GEN_EV
44#endif
45
46#include "efx_check.h"
47
48
49#if EFSYS_OPT_FALCON
50#include "falcon_impl.h"
51#endif /* EFSYS_OPT_FALCON */
52
53#if EFSYS_OPT_SIENA
54#include "siena_impl.h"
55#endif /* EFSYS_OPT_SIENA */
56
57#if EFSYS_OPT_HUNTINGTON
58#include "hunt_impl.h"
59#endif /* EFSYS_OPT_HUNTINGTON */
60
61#if EFSYS_OPT_MEDFORD
62#include "medford_impl.h"
63#endif /* EFSYS_OPT_MEDFORD */
64
65#if (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD)
66#include "ef10_impl.h"
67#endif /* (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD) */
68
69#ifdef __cplusplus
70extern "C" {
71#endif
72
73#define EFX_MOD_MCDI 0x00000001
74#define EFX_MOD_PROBE 0x00000002
75#define EFX_MOD_NVRAM 0x00000004
76#define EFX_MOD_VPD 0x00000008
77#define EFX_MOD_NIC 0x00000010
78#define EFX_MOD_INTR 0x00000020
79#define EFX_MOD_EV 0x00000040
80#define EFX_MOD_RX 0x00000080
81#define EFX_MOD_TX 0x00000100
82#define EFX_MOD_PORT 0x00000200
83#define EFX_MOD_MON 0x00000400
84#define EFX_MOD_WOL 0x00000800
85#define EFX_MOD_FILTER 0x00001000
86#define EFX_MOD_PKTFILTER 0x00002000
87
88#define EFX_RESET_MAC 0x00000001
89#define EFX_RESET_PHY 0x00000002
90#define EFX_RESET_RXQ_ERR 0x00000004
91#define EFX_RESET_TXQ_ERR 0x00000008
92
93typedef enum efx_mac_type_e {
94 EFX_MAC_INVALID = 0,
95 EFX_MAC_FALCON_GMAC,
96 EFX_MAC_FALCON_XMAC,
97 EFX_MAC_SIENA,
98 EFX_MAC_HUNTINGTON,
99 EFX_MAC_NTYPES
100} efx_mac_type_t;
101
102typedef struct efx_ev_ops_s {
103 efx_rc_t (*eevo_init)(efx_nic_t *);
104 void (*eevo_fini)(efx_nic_t *);
105 efx_rc_t (*eevo_qcreate)(efx_nic_t *, unsigned int,
106 efsys_mem_t *, size_t, uint32_t,
107 efx_evq_t *);
108 void (*eevo_qdestroy)(efx_evq_t *);
109 efx_rc_t (*eevo_qprime)(efx_evq_t *, unsigned int);
110 void (*eevo_qpost)(efx_evq_t *, uint16_t);
111 efx_rc_t (*eevo_qmoderate)(efx_evq_t *, unsigned int);
112#if EFSYS_OPT_QSTATS
113 void (*eevo_qstats_update)(efx_evq_t *, efsys_stat_t *);
114#endif
115} efx_ev_ops_t;
116
117typedef struct efx_tx_ops_s {
118 efx_rc_t (*etxo_init)(efx_nic_t *);
119 void (*etxo_fini)(efx_nic_t *);
120 efx_rc_t (*etxo_qcreate)(efx_nic_t *,
121 unsigned int, unsigned int,
122 efsys_mem_t *, size_t,
123 uint32_t, uint16_t,
124 efx_evq_t *, efx_txq_t *,
125 unsigned int *);
126 void (*etxo_qdestroy)(efx_txq_t *);
127 efx_rc_t (*etxo_qpost)(efx_txq_t *, efx_buffer_t *,
128 unsigned int, unsigned int,
129 unsigned int *);
130 void (*etxo_qpush)(efx_txq_t *, unsigned int, unsigned int);
131 efx_rc_t (*etxo_qpace)(efx_txq_t *, unsigned int);
132 efx_rc_t (*etxo_qflush)(efx_txq_t *);
133 void (*etxo_qenable)(efx_txq_t *);
134 efx_rc_t (*etxo_qpio_enable)(efx_txq_t *);
135 void (*etxo_qpio_disable)(efx_txq_t *);
136 efx_rc_t (*etxo_qpio_write)(efx_txq_t *,uint8_t *, size_t,
137 size_t);
138 efx_rc_t (*etxo_qpio_post)(efx_txq_t *, size_t, unsigned int,
139 unsigned int *);
140 efx_rc_t (*etxo_qdesc_post)(efx_txq_t *, efx_desc_t *,
141 unsigned int, unsigned int,
142 unsigned int *);
143 void (*etxo_qdesc_dma_create)(efx_txq_t *, efsys_dma_addr_t,
144 size_t, boolean_t,
145 efx_desc_t *);
146 void (*etxo_qdesc_tso_create)(efx_txq_t *, uint16_t,
147 uint32_t, uint8_t,
148 efx_desc_t *);
31 */
32
33#ifndef _SYS_EFX_IMPL_H
34#define _SYS_EFX_IMPL_H
35
36#include "efsys.h"
37#include "efx.h"
38#include "efx_regs.h"
39#include "efx_regs_ef10.h"
40
41/* FIXME: Add definition for driver generated software events */
42#ifndef ESE_DZ_EV_CODE_DRV_GEN_EV
43#define ESE_DZ_EV_CODE_DRV_GEN_EV FSE_AZ_EV_CODE_DRV_GEN_EV
44#endif
45
46#include "efx_check.h"
47
48
49#if EFSYS_OPT_FALCON
50#include "falcon_impl.h"
51#endif /* EFSYS_OPT_FALCON */
52
53#if EFSYS_OPT_SIENA
54#include "siena_impl.h"
55#endif /* EFSYS_OPT_SIENA */
56
57#if EFSYS_OPT_HUNTINGTON
58#include "hunt_impl.h"
59#endif /* EFSYS_OPT_HUNTINGTON */
60
61#if EFSYS_OPT_MEDFORD
62#include "medford_impl.h"
63#endif /* EFSYS_OPT_MEDFORD */
64
65#if (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD)
66#include "ef10_impl.h"
67#endif /* (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD) */
68
69#ifdef __cplusplus
70extern "C" {
71#endif
72
73#define EFX_MOD_MCDI 0x00000001
74#define EFX_MOD_PROBE 0x00000002
75#define EFX_MOD_NVRAM 0x00000004
76#define EFX_MOD_VPD 0x00000008
77#define EFX_MOD_NIC 0x00000010
78#define EFX_MOD_INTR 0x00000020
79#define EFX_MOD_EV 0x00000040
80#define EFX_MOD_RX 0x00000080
81#define EFX_MOD_TX 0x00000100
82#define EFX_MOD_PORT 0x00000200
83#define EFX_MOD_MON 0x00000400
84#define EFX_MOD_WOL 0x00000800
85#define EFX_MOD_FILTER 0x00001000
86#define EFX_MOD_PKTFILTER 0x00002000
87
88#define EFX_RESET_MAC 0x00000001
89#define EFX_RESET_PHY 0x00000002
90#define EFX_RESET_RXQ_ERR 0x00000004
91#define EFX_RESET_TXQ_ERR 0x00000008
92
93typedef enum efx_mac_type_e {
94 EFX_MAC_INVALID = 0,
95 EFX_MAC_FALCON_GMAC,
96 EFX_MAC_FALCON_XMAC,
97 EFX_MAC_SIENA,
98 EFX_MAC_HUNTINGTON,
99 EFX_MAC_NTYPES
100} efx_mac_type_t;
101
102typedef struct efx_ev_ops_s {
103 efx_rc_t (*eevo_init)(efx_nic_t *);
104 void (*eevo_fini)(efx_nic_t *);
105 efx_rc_t (*eevo_qcreate)(efx_nic_t *, unsigned int,
106 efsys_mem_t *, size_t, uint32_t,
107 efx_evq_t *);
108 void (*eevo_qdestroy)(efx_evq_t *);
109 efx_rc_t (*eevo_qprime)(efx_evq_t *, unsigned int);
110 void (*eevo_qpost)(efx_evq_t *, uint16_t);
111 efx_rc_t (*eevo_qmoderate)(efx_evq_t *, unsigned int);
112#if EFSYS_OPT_QSTATS
113 void (*eevo_qstats_update)(efx_evq_t *, efsys_stat_t *);
114#endif
115} efx_ev_ops_t;
116
117typedef struct efx_tx_ops_s {
118 efx_rc_t (*etxo_init)(efx_nic_t *);
119 void (*etxo_fini)(efx_nic_t *);
120 efx_rc_t (*etxo_qcreate)(efx_nic_t *,
121 unsigned int, unsigned int,
122 efsys_mem_t *, size_t,
123 uint32_t, uint16_t,
124 efx_evq_t *, efx_txq_t *,
125 unsigned int *);
126 void (*etxo_qdestroy)(efx_txq_t *);
127 efx_rc_t (*etxo_qpost)(efx_txq_t *, efx_buffer_t *,
128 unsigned int, unsigned int,
129 unsigned int *);
130 void (*etxo_qpush)(efx_txq_t *, unsigned int, unsigned int);
131 efx_rc_t (*etxo_qpace)(efx_txq_t *, unsigned int);
132 efx_rc_t (*etxo_qflush)(efx_txq_t *);
133 void (*etxo_qenable)(efx_txq_t *);
134 efx_rc_t (*etxo_qpio_enable)(efx_txq_t *);
135 void (*etxo_qpio_disable)(efx_txq_t *);
136 efx_rc_t (*etxo_qpio_write)(efx_txq_t *,uint8_t *, size_t,
137 size_t);
138 efx_rc_t (*etxo_qpio_post)(efx_txq_t *, size_t, unsigned int,
139 unsigned int *);
140 efx_rc_t (*etxo_qdesc_post)(efx_txq_t *, efx_desc_t *,
141 unsigned int, unsigned int,
142 unsigned int *);
143 void (*etxo_qdesc_dma_create)(efx_txq_t *, efsys_dma_addr_t,
144 size_t, boolean_t,
145 efx_desc_t *);
146 void (*etxo_qdesc_tso_create)(efx_txq_t *, uint16_t,
147 uint32_t, uint8_t,
148 efx_desc_t *);
149 void (*etxo_qdesc_tso2_create)(efx_txq_t *, uint16_t,
150 uint32_t, uint16_t,
151 efx_desc_t *, int);
149 void (*etxo_qdesc_vlantci_create)(efx_txq_t *, uint16_t,
150 efx_desc_t *);
151#if EFSYS_OPT_QSTATS
152 void (*etxo_qstats_update)(efx_txq_t *,
153 efsys_stat_t *);
154#endif
155} efx_tx_ops_t;
156
157typedef struct efx_rx_ops_s {
158 efx_rc_t (*erxo_init)(efx_nic_t *);
159 void (*erxo_fini)(efx_nic_t *);
160#if EFSYS_OPT_RX_SCATTER
161 efx_rc_t (*erxo_scatter_enable)(efx_nic_t *, unsigned int);
162#endif
163#if EFSYS_OPT_RX_SCALE
164 efx_rc_t (*erxo_scale_mode_set)(efx_nic_t *, efx_rx_hash_alg_t,
165 efx_rx_hash_type_t, boolean_t);
166 efx_rc_t (*erxo_scale_key_set)(efx_nic_t *, uint8_t *, size_t);
167 efx_rc_t (*erxo_scale_tbl_set)(efx_nic_t *, unsigned int *,
168 size_t);
169 uint32_t (*erxo_prefix_hash)(efx_nic_t *, efx_rx_hash_alg_t,
170 uint8_t *);
171#endif /* EFSYS_OPT_RX_SCALE */
172 efx_rc_t (*erxo_prefix_pktlen)(efx_nic_t *, uint8_t *,
173 uint16_t *);
174 void (*erxo_qpost)(efx_rxq_t *, efsys_dma_addr_t *, size_t,
175 unsigned int, unsigned int,
176 unsigned int);
177 void (*erxo_qpush)(efx_rxq_t *, unsigned int, unsigned int *);
178 efx_rc_t (*erxo_qflush)(efx_rxq_t *);
179 void (*erxo_qenable)(efx_rxq_t *);
180 efx_rc_t (*erxo_qcreate)(efx_nic_t *enp, unsigned int,
181 unsigned int, efx_rxq_type_t,
182 efsys_mem_t *, size_t, uint32_t,
183 efx_evq_t *, efx_rxq_t *);
184 void (*erxo_qdestroy)(efx_rxq_t *);
185} efx_rx_ops_t;
186
187typedef struct efx_mac_ops_s {
188 efx_rc_t (*emo_reset)(efx_nic_t *); /* optional */
189 efx_rc_t (*emo_poll)(efx_nic_t *, efx_link_mode_t *);
190 efx_rc_t (*emo_up)(efx_nic_t *, boolean_t *);
191 efx_rc_t (*emo_addr_set)(efx_nic_t *);
192 efx_rc_t (*emo_reconfigure)(efx_nic_t *);
193 efx_rc_t (*emo_multicast_list_set)(efx_nic_t *);
194 efx_rc_t (*emo_filter_default_rxq_set)(efx_nic_t *,
195 efx_rxq_t *, boolean_t);
196 void (*emo_filter_default_rxq_clear)(efx_nic_t *);
197#if EFSYS_OPT_LOOPBACK
198 efx_rc_t (*emo_loopback_set)(efx_nic_t *, efx_link_mode_t,
199 efx_loopback_type_t);
200#endif /* EFSYS_OPT_LOOPBACK */
201#if EFSYS_OPT_MAC_STATS
202 efx_rc_t (*emo_stats_upload)(efx_nic_t *, efsys_mem_t *);
203 efx_rc_t (*emo_stats_periodic)(efx_nic_t *, efsys_mem_t *,
204 uint16_t, boolean_t);
205 efx_rc_t (*emo_stats_update)(efx_nic_t *, efsys_mem_t *,
206 efsys_stat_t *, uint32_t *);
207#endif /* EFSYS_OPT_MAC_STATS */
208} efx_mac_ops_t;
209
210typedef struct efx_phy_ops_s {
211 efx_rc_t (*epo_power)(efx_nic_t *, boolean_t); /* optional */
212 efx_rc_t (*epo_reset)(efx_nic_t *);
213 efx_rc_t (*epo_reconfigure)(efx_nic_t *);
214 efx_rc_t (*epo_verify)(efx_nic_t *);
215 efx_rc_t (*epo_uplink_check)(efx_nic_t *,
216 boolean_t *); /* optional */
217 efx_rc_t (*epo_downlink_check)(efx_nic_t *, efx_link_mode_t *,
218 unsigned int *, uint32_t *);
219 efx_rc_t (*epo_oui_get)(efx_nic_t *, uint32_t *);
220#if EFSYS_OPT_PHY_STATS
221 efx_rc_t (*epo_stats_update)(efx_nic_t *, efsys_mem_t *,
222 uint32_t *);
223#endif /* EFSYS_OPT_PHY_STATS */
224#if EFSYS_OPT_PHY_PROPS
225#if EFSYS_OPT_NAMES
226 const char *(*epo_prop_name)(efx_nic_t *, unsigned int);
227#endif /* EFSYS_OPT_PHY_PROPS */
228 efx_rc_t (*epo_prop_get)(efx_nic_t *, unsigned int, uint32_t,
229 uint32_t *);
230 efx_rc_t (*epo_prop_set)(efx_nic_t *, unsigned int, uint32_t);
231#endif /* EFSYS_OPT_PHY_PROPS */
232#if EFSYS_OPT_BIST
233 efx_rc_t (*epo_bist_enable_offline)(efx_nic_t *);
234 efx_rc_t (*epo_bist_start)(efx_nic_t *, efx_bist_type_t);
235 efx_rc_t (*epo_bist_poll)(efx_nic_t *, efx_bist_type_t,
236 efx_bist_result_t *, uint32_t *,
237 unsigned long *, size_t);
238 void (*epo_bist_stop)(efx_nic_t *, efx_bist_type_t);
239#endif /* EFSYS_OPT_BIST */
240} efx_phy_ops_t;
241
242#if EFSYS_OPT_FILTER
243typedef struct efx_filter_ops_s {
244 efx_rc_t (*efo_init)(efx_nic_t *);
245 void (*efo_fini)(efx_nic_t *);
246 efx_rc_t (*efo_restore)(efx_nic_t *);
247 efx_rc_t (*efo_add)(efx_nic_t *, efx_filter_spec_t *,
248 boolean_t may_replace);
249 efx_rc_t (*efo_delete)(efx_nic_t *, efx_filter_spec_t *);
250 efx_rc_t (*efo_supported_filters)(efx_nic_t *, uint32_t *, size_t *);
251 efx_rc_t (*efo_reconfigure)(efx_nic_t *, uint8_t const *, boolean_t,
252 boolean_t, boolean_t, boolean_t,
253 uint8_t const *, int);
254} efx_filter_ops_t;
255
256extern __checkReturn efx_rc_t
257efx_filter_reconfigure(
258 __in efx_nic_t *enp,
259 __in_ecount(6) uint8_t const *mac_addr,
260 __in boolean_t all_unicst,
261 __in boolean_t mulcst,
262 __in boolean_t all_mulcst,
263 __in boolean_t brdcst,
264 __in_ecount(6*count) uint8_t const *addrs,
265 __in int count);
266
267#endif /* EFSYS_OPT_FILTER */
268
269
270typedef struct efx_port_s {
271 efx_mac_type_t ep_mac_type;
272 uint32_t ep_phy_type;
273 uint8_t ep_port;
274 uint32_t ep_mac_pdu;
275 uint8_t ep_mac_addr[6];
276 efx_link_mode_t ep_link_mode;
277 boolean_t ep_all_unicst;
278 boolean_t ep_mulcst;
279 boolean_t ep_all_mulcst;
280 boolean_t ep_brdcst;
281 unsigned int ep_fcntl;
282 boolean_t ep_fcntl_autoneg;
283 efx_oword_t ep_multicst_hash[2];
284 uint8_t ep_mulcst_addr_list[EFX_MAC_ADDR_LEN *
285 EFX_MAC_MULTICAST_LIST_MAX];
286 uint32_t ep_mulcst_addr_count;
287#if EFSYS_OPT_LOOPBACK
288 efx_loopback_type_t ep_loopback_type;
289 efx_link_mode_t ep_loopback_link_mode;
290#endif /* EFSYS_OPT_LOOPBACK */
291#if EFSYS_OPT_PHY_FLAGS
292 uint32_t ep_phy_flags;
293#endif /* EFSYS_OPT_PHY_FLAGS */
294#if EFSYS_OPT_PHY_LED_CONTROL
295 efx_phy_led_mode_t ep_phy_led_mode;
296#endif /* EFSYS_OPT_PHY_LED_CONTROL */
297 efx_phy_media_type_t ep_fixed_port_type;
298 efx_phy_media_type_t ep_module_type;
299 uint32_t ep_adv_cap_mask;
300 uint32_t ep_lp_cap_mask;
301 uint32_t ep_default_adv_cap_mask;
302 uint32_t ep_phy_cap_mask;
303#if EFSYS_OPT_PHY_TXC43128 || EFSYS_OPT_PHY_QT2025C
304 union {
305 struct {
306 unsigned int bug10934_count;
307 } ep_txc43128;
308 struct {
309 unsigned int bug17190_count;
310 } ep_qt2025c;
311 };
312#endif
313 boolean_t ep_mac_poll_needed; /* falcon only */
314 boolean_t ep_mac_up; /* falcon only */
315 uint32_t ep_fwver; /* falcon only */
316 boolean_t ep_mac_drain;
317 boolean_t ep_mac_stats_pending;
318#if EFSYS_OPT_BIST
319 efx_bist_type_t ep_current_bist;
320#endif
321 efx_mac_ops_t *ep_emop;
322 efx_phy_ops_t *ep_epop;
323} efx_port_t;
324
325typedef struct efx_mon_ops_s {
326 efx_rc_t (*emo_reset)(efx_nic_t *);
327 efx_rc_t (*emo_reconfigure)(efx_nic_t *);
328#if EFSYS_OPT_MON_STATS
329 efx_rc_t (*emo_stats_update)(efx_nic_t *, efsys_mem_t *,
330 efx_mon_stat_value_t *);
331#endif /* EFSYS_OPT_MON_STATS */
332} efx_mon_ops_t;
333
334typedef struct efx_mon_s {
335 efx_mon_type_t em_type;
336 efx_mon_ops_t *em_emop;
337} efx_mon_t;
338
339typedef struct efx_intr_ops_s {
340 efx_rc_t (*eio_init)(efx_nic_t *, efx_intr_type_t, efsys_mem_t *);
341 void (*eio_enable)(efx_nic_t *);
342 void (*eio_disable)(efx_nic_t *);
343 void (*eio_disable_unlocked)(efx_nic_t *);
344 efx_rc_t (*eio_trigger)(efx_nic_t *, unsigned int);
345 void (*eio_status_line)(efx_nic_t *, boolean_t *, uint32_t *);
346 void (*eio_status_message)(efx_nic_t *, unsigned int,
347 boolean_t *);
348 void (*eio_fatal)(efx_nic_t *);
349 void (*eio_fini)(efx_nic_t *);
350} efx_intr_ops_t;
351
352typedef struct efx_intr_s {
353 efx_intr_ops_t *ei_eiop;
354 efsys_mem_t *ei_esmp;
355 efx_intr_type_t ei_type;
356 unsigned int ei_level;
357} efx_intr_t;
358
359typedef struct efx_nic_ops_s {
360 efx_rc_t (*eno_probe)(efx_nic_t *);
361 efx_rc_t (*eno_board_cfg)(efx_nic_t *);
362 efx_rc_t (*eno_set_drv_limits)(efx_nic_t *, efx_drv_limits_t*);
363 efx_rc_t (*eno_reset)(efx_nic_t *);
364 efx_rc_t (*eno_init)(efx_nic_t *);
365 efx_rc_t (*eno_get_vi_pool)(efx_nic_t *, uint32_t *);
366 efx_rc_t (*eno_get_bar_region)(efx_nic_t *, efx_nic_region_t,
367 uint32_t *, size_t *);
368#if EFSYS_OPT_DIAG
369 efx_rc_t (*eno_sram_test)(efx_nic_t *, efx_sram_pattern_fn_t);
370 efx_rc_t (*eno_register_test)(efx_nic_t *);
371#endif /* EFSYS_OPT_DIAG */
372 void (*eno_fini)(efx_nic_t *);
373 void (*eno_unprobe)(efx_nic_t *);
374} efx_nic_ops_t;
375
376#ifndef EFX_TXQ_LIMIT_TARGET
377#define EFX_TXQ_LIMIT_TARGET 259
378#endif
379#ifndef EFX_RXQ_LIMIT_TARGET
380#define EFX_RXQ_LIMIT_TARGET 512
381#endif
382#ifndef EFX_TXQ_DC_SIZE
383#define EFX_TXQ_DC_SIZE 1 /* 16 descriptors */
384#endif
385#ifndef EFX_RXQ_DC_SIZE
386#define EFX_RXQ_DC_SIZE 3 /* 64 descriptors */
387#endif
388
389#if EFSYS_OPT_FILTER
390
391typedef struct falconsiena_filter_spec_s {
392 uint8_t fsfs_type;
393 uint32_t fsfs_flags;
394 uint32_t fsfs_dmaq_id;
395 uint32_t fsfs_dword[3];
396} falconsiena_filter_spec_t;
397
398typedef enum falconsiena_filter_type_e {
399 EFX_FS_FILTER_RX_TCP_FULL, /* TCP/IPv4 4-tuple {dIP,dTCP,sIP,sTCP} */
400 EFX_FS_FILTER_RX_TCP_WILD, /* TCP/IPv4 dest {dIP,dTCP, -, -} */
401 EFX_FS_FILTER_RX_UDP_FULL, /* UDP/IPv4 4-tuple {dIP,dUDP,sIP,sUDP} */
402 EFX_FS_FILTER_RX_UDP_WILD, /* UDP/IPv4 dest {dIP,dUDP, -, -} */
403
404#if EFSYS_OPT_SIENA
405 EFX_FS_FILTER_RX_MAC_FULL, /* Ethernet {dMAC,VLAN} */
406 EFX_FS_FILTER_RX_MAC_WILD, /* Ethernet {dMAC, -} */
407
408 EFX_FS_FILTER_TX_TCP_FULL, /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */
409 EFX_FS_FILTER_TX_TCP_WILD, /* TCP/IPv4 { -, -,sIP,sTCP} */
410 EFX_FS_FILTER_TX_UDP_FULL, /* UDP/IPv4 {dIP,dTCP,sIP,sTCP} */
411 EFX_FS_FILTER_TX_UDP_WILD, /* UDP/IPv4 source (host, port) */
412
413 EFX_FS_FILTER_TX_MAC_FULL, /* Ethernet source (MAC address, VLAN ID) */
414 EFX_FS_FILTER_TX_MAC_WILD, /* Ethernet source (MAC address) */
415#endif /* EFSYS_OPT_SIENA */
416
417 EFX_FS_FILTER_NTYPES
418} falconsiena_filter_type_t;
419
420typedef enum falconsiena_filter_tbl_id_e {
421 EFX_FS_FILTER_TBL_RX_IP = 0,
422 EFX_FS_FILTER_TBL_RX_MAC,
423 EFX_FS_FILTER_TBL_TX_IP,
424 EFX_FS_FILTER_TBL_TX_MAC,
425 EFX_FS_FILTER_NTBLS
426} falconsiena_filter_tbl_id_t;
427
428typedef struct falconsiena_filter_tbl_s {
429 int fsft_size; /* number of entries */
430 int fsft_used; /* active count */
431 uint32_t *fsft_bitmap; /* active bitmap */
432 falconsiena_filter_spec_t *fsft_spec; /* array of saved specs */
433} falconsiena_filter_tbl_t;
434
435typedef struct falconsiena_filter_s {
436 falconsiena_filter_tbl_t fsf_tbl[EFX_FS_FILTER_NTBLS];
437 unsigned int fsf_depth[EFX_FS_FILTER_NTYPES];
438} falconsiena_filter_t;
439
440typedef struct efx_filter_s {
441#if EFSYS_OPT_FALCON || EFSYS_OPT_SIENA
442 falconsiena_filter_t *ef_falconsiena_filter;
443#endif /* EFSYS_OPT_FALCON || EFSYS_OPT_SIENA */
444#if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
445 ef10_filter_table_t *ef_ef10_filter_table;
446#endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */
447} efx_filter_t;
448
449extern void
450falconsiena_filter_tbl_clear(
451 __in efx_nic_t *enp,
452 __in falconsiena_filter_tbl_id_t tbl);
453
454#endif /* EFSYS_OPT_FILTER */
455
456#if EFSYS_OPT_MCDI
457
458typedef struct efx_mcdi_ops_s {
459 efx_rc_t (*emco_init)(efx_nic_t *, const efx_mcdi_transport_t *);
460 void (*emco_send_request)(efx_nic_t *, void *, size_t,
461 void *, size_t);
462 void (*emco_request_copyout)(efx_nic_t *, efx_mcdi_req_t *);
463 efx_rc_t (*emco_poll_reboot)(efx_nic_t *);
464 boolean_t (*emco_poll_response)(efx_nic_t *);
465 void (*emco_read_response)(efx_nic_t *, void *, size_t, size_t);
466 void (*emco_fini)(efx_nic_t *);
467 efx_rc_t (*emco_feature_supported)(efx_nic_t *, efx_mcdi_feature_id_t, boolean_t *);
468} efx_mcdi_ops_t;
469
470typedef struct efx_mcdi_s {
471 efx_mcdi_ops_t *em_emcop;
472 const efx_mcdi_transport_t *em_emtp;
473 efx_mcdi_iface_t em_emip;
474} efx_mcdi_t;
475
476#endif /* EFSYS_OPT_MCDI */
477
478#if EFSYS_OPT_NVRAM
479typedef struct efx_nvram_ops_s {
480#if EFSYS_OPT_DIAG
481 efx_rc_t (*envo_test)(efx_nic_t *);
482#endif /* EFSYS_OPT_DIAG */
483 efx_rc_t (*envo_get_version)(efx_nic_t *, efx_nvram_type_t,
484 uint32_t *, uint16_t *);
485 efx_rc_t (*envo_rw_start)(efx_nic_t *, efx_nvram_type_t, size_t *);
486 efx_rc_t (*envo_read_chunk)(efx_nic_t *, efx_nvram_type_t,
487 unsigned int, caddr_t, size_t);
488 efx_rc_t (*envo_erase)(efx_nic_t *, efx_nvram_type_t);
489 efx_rc_t (*envo_write_chunk)(efx_nic_t *, efx_nvram_type_t,
490 unsigned int, caddr_t, size_t);
491 void (*envo_rw_finish)(efx_nic_t *, efx_nvram_type_t);
492 efx_rc_t (*envo_set_version)(efx_nic_t *, efx_nvram_type_t,
493 uint16_t *);
494
495 efx_rc_t (*envo_type_to_partn)(efx_nic_t *, efx_nvram_type_t,
496 uint32_t *);
497 efx_rc_t (*envo_partn_size)(efx_nic_t *, uint32_t, size_t *);
498} efx_nvram_ops_t;
499#endif /* EFSYS_OPT_NVRAM */
500
501#if EFSYS_OPT_VPD
502typedef struct efx_vpd_ops_s {
503 efx_rc_t (*evpdo_init)(efx_nic_t *);
504 efx_rc_t (*evpdo_size)(efx_nic_t *, size_t *);
505 efx_rc_t (*evpdo_read)(efx_nic_t *, caddr_t, size_t);
506 efx_rc_t (*evpdo_verify)(efx_nic_t *, caddr_t, size_t);
507 efx_rc_t (*evpdo_reinit)(efx_nic_t *, caddr_t, size_t);
508 efx_rc_t (*evpdo_get)(efx_nic_t *, caddr_t, size_t,
509 efx_vpd_value_t *);
510 efx_rc_t (*evpdo_set)(efx_nic_t *, caddr_t, size_t,
511 efx_vpd_value_t *);
512 efx_rc_t (*evpdo_next)(efx_nic_t *, caddr_t, size_t,
513 efx_vpd_value_t *, unsigned int *);
514 efx_rc_t (*evpdo_write)(efx_nic_t *, caddr_t, size_t);
515 void (*evpdo_fini)(efx_nic_t *);
516} efx_vpd_ops_t;
517#endif /* EFSYS_OPT_VPD */
518
519#if EFSYS_OPT_VPD || EFSYS_OPT_NVRAM
520
521 __checkReturn efx_rc_t
522efx_mcdi_nvram_partitions(
523 __in efx_nic_t *enp,
524 __out_bcount(size) caddr_t data,
525 __in size_t size,
526 __out unsigned int *npartnp);
527
528 __checkReturn efx_rc_t
529efx_mcdi_nvram_metadata(
530 __in efx_nic_t *enp,
531 __in uint32_t partn,
532 __out uint32_t *subtypep,
533 __out_ecount(4) uint16_t version[4],
534 __out_bcount_opt(size) char *descp,
535 __in size_t size);
536
537 __checkReturn efx_rc_t
538efx_mcdi_nvram_info(
539 __in efx_nic_t *enp,
540 __in uint32_t partn,
541 __out_opt size_t *sizep,
542 __out_opt uint32_t *addressp,
543 __out_opt uint32_t *erase_sizep,
544 __out_opt uint32_t *write_sizep);
545
546 __checkReturn efx_rc_t
547efx_mcdi_nvram_update_start(
548 __in efx_nic_t *enp,
549 __in uint32_t partn);
550
551 __checkReturn efx_rc_t
552efx_mcdi_nvram_read(
553 __in efx_nic_t *enp,
554 __in uint32_t partn,
555 __in uint32_t offset,
556 __out_bcount(size) caddr_t data,
557 __in size_t size);
558
559 __checkReturn efx_rc_t
560efx_mcdi_nvram_erase(
561 __in efx_nic_t *enp,
562 __in uint32_t partn,
563 __in uint32_t offset,
564 __in size_t size);
565
566 __checkReturn efx_rc_t
567efx_mcdi_nvram_write(
568 __in efx_nic_t *enp,
569 __in uint32_t partn,
570 __in uint32_t offset,
571 __out_bcount(size) caddr_t data,
572 __in size_t size);
573
574 __checkReturn efx_rc_t
575efx_mcdi_nvram_update_finish(
576 __in efx_nic_t *enp,
577 __in uint32_t partn,
578 __in boolean_t reboot);
579
580#if EFSYS_OPT_DIAG
581
582 __checkReturn efx_rc_t
583efx_mcdi_nvram_test(
584 __in efx_nic_t *enp,
585 __in uint32_t partn);
586
587#endif /* EFSYS_OPT_DIAG */
588
589#endif /* EFSYS_OPT_VPD || EFSYS_OPT_NVRAM */
590
591typedef struct efx_drv_cfg_s {
592 uint32_t edc_min_vi_count;
593 uint32_t edc_max_vi_count;
594
595 uint32_t edc_max_piobuf_count;
596 uint32_t edc_pio_alloc_size;
597} efx_drv_cfg_t;
598
599struct efx_nic_s {
600 uint32_t en_magic;
601 efx_family_t en_family;
602 uint32_t en_features;
603 efsys_identifier_t *en_esip;
604 efsys_lock_t *en_eslp;
605 efsys_bar_t *en_esbp;
606 unsigned int en_mod_flags;
607 unsigned int en_reset_flags;
608 efx_nic_cfg_t en_nic_cfg;
609 efx_drv_cfg_t en_drv_cfg;
610 efx_port_t en_port;
611 efx_mon_t en_mon;
612 efx_intr_t en_intr;
613 uint32_t en_ev_qcount;
614 uint32_t en_rx_qcount;
615 uint32_t en_tx_qcount;
616 efx_nic_ops_t *en_enop;
617 efx_ev_ops_t *en_eevop;
618 efx_tx_ops_t *en_etxop;
619 efx_rx_ops_t *en_erxop;
620#if EFSYS_OPT_FILTER
621 efx_filter_t en_filter;
622 efx_filter_ops_t *en_efop;
623#endif /* EFSYS_OPT_FILTER */
624#if EFSYS_OPT_MCDI
625 efx_mcdi_t en_mcdi;
626#endif /* EFSYS_OPT_MCDI */
627#if EFSYS_OPT_NVRAM
628 efx_nvram_type_t en_nvram_locked;
629 efx_nvram_ops_t *en_envop;
630#endif /* EFSYS_OPT_NVRAM */
631#if EFSYS_OPT_VPD
632 efx_vpd_ops_t *en_evpdop;
633#endif /* EFSYS_OPT_VPD */
634#if EFSYS_OPT_RX_SCALE
635 efx_rx_hash_support_t en_hash_support;
636 efx_rx_scale_support_t en_rss_support;
637 uint32_t en_rss_context;
638#endif /* EFSYS_OPT_RX_SCALE */
639 uint32_t en_vport_id;
640 union {
641#if EFSYS_OPT_FALCON
642 struct {
643 falcon_spi_dev_t enu_fsd[FALCON_SPI_NTYPES];
644 falcon_i2c_t enu_fip;
645 boolean_t enu_i2c_locked;
646#if EFSYS_OPT_FALCON_NIC_CFG_OVERRIDE
647 const uint8_t *enu_forced_cfg;
648#endif /* EFSYS_OPT_FALCON_NIC_CFG_OVERRIDE */
649 uint8_t enu_mon_devid;
650#if EFSYS_OPT_PCIE_TUNE
651 unsigned int enu_nlanes;
652#endif /* EFSYS_OPT_PCIE_TUNE */
653 uint16_t enu_board_rev;
654 boolean_t enu_internal_sram;
655 uint8_t enu_sram_num_bank;
656 uint8_t enu_sram_bank_size;
657 } falcon;
658#endif /* EFSYS_OPT_FALCON */
659#if EFSYS_OPT_SIENA
660 struct {
661#if EFSYS_OPT_NVRAM || EFSYS_OPT_VPD
662 unsigned int enu_partn_mask;
663#endif /* EFSYS_OPT_NVRAM || EFSYS_OPT_VPD */
664#if EFSYS_OPT_VPD
665 caddr_t enu_svpd;
666 size_t enu_svpd_length;
667#endif /* EFSYS_OPT_VPD */
668 int enu_unused;
669 } siena;
670#endif /* EFSYS_OPT_SIENA */
671 int enu_unused;
672 } en_u;
673#if (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD)
674 union en_arch {
675 struct {
676 int ena_vi_base;
677 int ena_vi_count;
678 int ena_vi_shift;
679#if EFSYS_OPT_VPD
680 caddr_t ena_svpd;
681 size_t ena_svpd_length;
682#endif /* EFSYS_OPT_VPD */
683 efx_piobuf_handle_t ena_piobuf_handle[EF10_MAX_PIOBUF_NBUFS];
684 uint32_t ena_piobuf_count;
685 uint32_t ena_pio_alloc_map[EF10_MAX_PIOBUF_NBUFS];
686 uint32_t ena_pio_write_vi_base;
687 /* Memory BAR mapping regions */
688 uint32_t ena_uc_mem_map_offset;
689 size_t ena_uc_mem_map_size;
690 uint32_t ena_wc_mem_map_offset;
691 size_t ena_wc_mem_map_size;
692 } ef10;
693 } en_arch;
694#endif /* (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD) */
695};
696
697
698#define EFX_NIC_MAGIC 0x02121996
699
700typedef boolean_t (*efx_ev_handler_t)(efx_evq_t *, efx_qword_t *,
701 const efx_ev_callbacks_t *, void *);
702
703typedef struct efx_evq_rxq_state_s {
704 unsigned int eers_rx_read_ptr;
705 unsigned int eers_rx_mask;
706} efx_evq_rxq_state_t;
707
708struct efx_evq_s {
709 uint32_t ee_magic;
710 efx_nic_t *ee_enp;
711 unsigned int ee_index;
712 unsigned int ee_mask;
713 efsys_mem_t *ee_esmp;
714#if EFSYS_OPT_QSTATS
715 uint32_t ee_stat[EV_NQSTATS];
716#endif /* EFSYS_OPT_QSTATS */
717
718 efx_ev_handler_t ee_rx;
719 efx_ev_handler_t ee_tx;
720 efx_ev_handler_t ee_driver;
721 efx_ev_handler_t ee_global;
722 efx_ev_handler_t ee_drv_gen;
723#if EFSYS_OPT_MCDI
724 efx_ev_handler_t ee_mcdi;
725#endif /* EFSYS_OPT_MCDI */
726
727 efx_evq_rxq_state_t ee_rxq_state[EFX_EV_RX_NLABELS];
728};
729
730#define EFX_EVQ_MAGIC 0x08081997
731
732#define EFX_EVQ_FALCON_TIMER_QUANTUM_NS 4968 /* 621 cycles */
733#define EFX_EVQ_SIENA_TIMER_QUANTUM_NS 6144 /* 768 cycles */
734
735struct efx_rxq_s {
736 uint32_t er_magic;
737 efx_nic_t *er_enp;
738 efx_evq_t *er_eep;
739 unsigned int er_index;
740 unsigned int er_label;
741 unsigned int er_mask;
742 efsys_mem_t *er_esmp;
743};
744
745#define EFX_RXQ_MAGIC 0x15022005
746
747struct efx_txq_s {
748 uint32_t et_magic;
749 efx_nic_t *et_enp;
750 unsigned int et_index;
751 unsigned int et_mask;
752 efsys_mem_t *et_esmp;
753#if EFSYS_OPT_HUNTINGTON
754 uint32_t et_pio_bufnum;
755 uint32_t et_pio_blknum;
756 uint32_t et_pio_write_offset;
757 uint32_t et_pio_offset;
758 size_t et_pio_size;
759#endif
760#if EFSYS_OPT_QSTATS
761 uint32_t et_stat[TX_NQSTATS];
762#endif /* EFSYS_OPT_QSTATS */
763};
764
765#define EFX_TXQ_MAGIC 0x05092005
766
767#define EFX_MAC_ADDR_COPY(_dst, _src) \
768 do { \
769 (_dst)[0] = (_src)[0]; \
770 (_dst)[1] = (_src)[1]; \
771 (_dst)[2] = (_src)[2]; \
772 (_dst)[3] = (_src)[3]; \
773 (_dst)[4] = (_src)[4]; \
774 (_dst)[5] = (_src)[5]; \
775 _NOTE(CONSTANTCONDITION) \
776 } while (B_FALSE)
777
778#define EFX_MAC_BROADCAST_ADDR_SET(_dst) \
779 do { \
780 uint16_t *_d = (uint16_t *)(_dst); \
781 _d[0] = 0xffff; \
782 _d[1] = 0xffff; \
783 _d[2] = 0xffff; \
784 _NOTE(CONSTANTCONDITION) \
785 } while (B_FALSE)
786
787#if EFSYS_OPT_CHECK_REG
788#define EFX_CHECK_REG(_enp, _reg) \
789 do { \
790 const char *name = #_reg; \
791 char min = name[4]; \
792 char max = name[5]; \
793 char rev; \
794 \
795 switch ((_enp)->en_family) { \
796 case EFX_FAMILY_FALCON: \
797 rev = 'B'; \
798 break; \
799 \
800 case EFX_FAMILY_SIENA: \
801 rev = 'C'; \
802 break; \
803 \
804 case EFX_FAMILY_HUNTINGTON: \
805 rev = 'D'; \
806 break; \
807 \
808 case EFX_FAMILY_MEDFORD: \
809 rev = 'E'; \
810 break; \
811 \
812 default: \
813 rev = '?'; \
814 break; \
815 } \
816 \
817 EFSYS_ASSERT3S(rev, >=, min); \
818 EFSYS_ASSERT3S(rev, <=, max); \
819 \
820 _NOTE(CONSTANTCONDITION) \
821 } while (B_FALSE)
822#else
823#define EFX_CHECK_REG(_enp, _reg) do { \
824 _NOTE(CONSTANTCONDITION) \
825 } while(B_FALSE)
826#endif
827
828#define EFX_BAR_READD(_enp, _reg, _edp, _lock) \
829 do { \
830 EFX_CHECK_REG((_enp), (_reg)); \
831 EFSYS_BAR_READD((_enp)->en_esbp, _reg ## _OFST, \
832 (_edp), (_lock)); \
833 EFSYS_PROBE3(efx_bar_readd, const char *, #_reg, \
834 uint32_t, _reg ## _OFST, \
835 uint32_t, (_edp)->ed_u32[0]); \
836 _NOTE(CONSTANTCONDITION) \
837 } while (B_FALSE)
838
839#define EFX_BAR_WRITED(_enp, _reg, _edp, _lock) \
840 do { \
841 EFX_CHECK_REG((_enp), (_reg)); \
842 EFSYS_PROBE3(efx_bar_writed, const char *, #_reg, \
843 uint32_t, _reg ## _OFST, \
844 uint32_t, (_edp)->ed_u32[0]); \
845 EFSYS_BAR_WRITED((_enp)->en_esbp, _reg ## _OFST, \
846 (_edp), (_lock)); \
847 _NOTE(CONSTANTCONDITION) \
848 } while (B_FALSE)
849
850#define EFX_BAR_READQ(_enp, _reg, _eqp) \
851 do { \
852 EFX_CHECK_REG((_enp), (_reg)); \
853 EFSYS_BAR_READQ((_enp)->en_esbp, _reg ## _OFST, \
854 (_eqp)); \
855 EFSYS_PROBE4(efx_bar_readq, const char *, #_reg, \
856 uint32_t, _reg ## _OFST, \
857 uint32_t, (_eqp)->eq_u32[1], \
858 uint32_t, (_eqp)->eq_u32[0]); \
859 _NOTE(CONSTANTCONDITION) \
860 } while (B_FALSE)
861
862#define EFX_BAR_WRITEQ(_enp, _reg, _eqp) \
863 do { \
864 EFX_CHECK_REG((_enp), (_reg)); \
865 EFSYS_PROBE4(efx_bar_writeq, const char *, #_reg, \
866 uint32_t, _reg ## _OFST, \
867 uint32_t, (_eqp)->eq_u32[1], \
868 uint32_t, (_eqp)->eq_u32[0]); \
869 EFSYS_BAR_WRITEQ((_enp)->en_esbp, _reg ## _OFST, \
870 (_eqp)); \
871 _NOTE(CONSTANTCONDITION) \
872 } while (B_FALSE)
873
874#define EFX_BAR_READO(_enp, _reg, _eop) \
875 do { \
876 EFX_CHECK_REG((_enp), (_reg)); \
877 EFSYS_BAR_READO((_enp)->en_esbp, _reg ## _OFST, \
878 (_eop), B_TRUE); \
879 EFSYS_PROBE6(efx_bar_reado, const char *, #_reg, \
880 uint32_t, _reg ## _OFST, \
881 uint32_t, (_eop)->eo_u32[3], \
882 uint32_t, (_eop)->eo_u32[2], \
883 uint32_t, (_eop)->eo_u32[1], \
884 uint32_t, (_eop)->eo_u32[0]); \
885 _NOTE(CONSTANTCONDITION) \
886 } while (B_FALSE)
887
888#define EFX_BAR_WRITEO(_enp, _reg, _eop) \
889 do { \
890 EFX_CHECK_REG((_enp), (_reg)); \
891 EFSYS_PROBE6(efx_bar_writeo, const char *, #_reg, \
892 uint32_t, _reg ## _OFST, \
893 uint32_t, (_eop)->eo_u32[3], \
894 uint32_t, (_eop)->eo_u32[2], \
895 uint32_t, (_eop)->eo_u32[1], \
896 uint32_t, (_eop)->eo_u32[0]); \
897 EFSYS_BAR_WRITEO((_enp)->en_esbp, _reg ## _OFST, \
898 (_eop), B_TRUE); \
899 _NOTE(CONSTANTCONDITION) \
900 } while (B_FALSE)
901
902#define EFX_BAR_TBL_READD(_enp, _reg, _index, _edp, _lock) \
903 do { \
904 EFX_CHECK_REG((_enp), (_reg)); \
905 EFSYS_BAR_READD((_enp)->en_esbp, \
906 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
907 (_edp), (_lock)); \
908 EFSYS_PROBE4(efx_bar_tbl_readd, const char *, #_reg, \
909 uint32_t, (_index), \
910 uint32_t, _reg ## _OFST, \
911 uint32_t, (_edp)->ed_u32[0]); \
912 _NOTE(CONSTANTCONDITION) \
913 } while (B_FALSE)
914
915#define EFX_BAR_TBL_WRITED(_enp, _reg, _index, _edp, _lock) \
916 do { \
917 EFX_CHECK_REG((_enp), (_reg)); \
918 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg, \
919 uint32_t, (_index), \
920 uint32_t, _reg ## _OFST, \
921 uint32_t, (_edp)->ed_u32[0]); \
922 EFSYS_BAR_WRITED((_enp)->en_esbp, \
923 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
924 (_edp), (_lock)); \
925 _NOTE(CONSTANTCONDITION) \
926 } while (B_FALSE)
927
928#define EFX_BAR_TBL_WRITED2(_enp, _reg, _index, _edp, _lock) \
929 do { \
930 EFX_CHECK_REG((_enp), (_reg)); \
931 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg, \
932 uint32_t, (_index), \
933 uint32_t, _reg ## _OFST, \
934 uint32_t, (_edp)->ed_u32[0]); \
935 EFSYS_BAR_WRITED((_enp)->en_esbp, \
936 (_reg ## _OFST + \
937 (2 * sizeof (efx_dword_t)) + \
938 ((_index) * _reg ## _STEP)), \
939 (_edp), (_lock)); \
940 _NOTE(CONSTANTCONDITION) \
941 } while (B_FALSE)
942
943#define EFX_BAR_TBL_WRITED3(_enp, _reg, _index, _edp, _lock) \
944 do { \
945 EFX_CHECK_REG((_enp), (_reg)); \
946 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg, \
947 uint32_t, (_index), \
948 uint32_t, _reg ## _OFST, \
949 uint32_t, (_edp)->ed_u32[0]); \
950 EFSYS_BAR_WRITED((_enp)->en_esbp, \
951 (_reg ## _OFST + \
952 (3 * sizeof (efx_dword_t)) + \
953 ((_index) * _reg ## _STEP)), \
954 (_edp), (_lock)); \
955 _NOTE(CONSTANTCONDITION) \
956 } while (B_FALSE)
957
958#define EFX_BAR_TBL_READQ(_enp, _reg, _index, _eqp) \
959 do { \
960 EFX_CHECK_REG((_enp), (_reg)); \
961 EFSYS_BAR_READQ((_enp)->en_esbp, \
962 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
963 (_eqp)); \
964 EFSYS_PROBE5(efx_bar_tbl_readq, const char *, #_reg, \
965 uint32_t, (_index), \
966 uint32_t, _reg ## _OFST, \
967 uint32_t, (_eqp)->eq_u32[1], \
968 uint32_t, (_eqp)->eq_u32[0]); \
969 _NOTE(CONSTANTCONDITION) \
970 } while (B_FALSE)
971
972#define EFX_BAR_TBL_WRITEQ(_enp, _reg, _index, _eqp) \
973 do { \
974 EFX_CHECK_REG((_enp), (_reg)); \
975 EFSYS_PROBE5(efx_bar_tbl_writeq, const char *, #_reg, \
976 uint32_t, (_index), \
977 uint32_t, _reg ## _OFST, \
978 uint32_t, (_eqp)->eq_u32[1], \
979 uint32_t, (_eqp)->eq_u32[0]); \
980 EFSYS_BAR_WRITEQ((_enp)->en_esbp, \
981 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
982 (_eqp)); \
983 _NOTE(CONSTANTCONDITION) \
984 } while (B_FALSE)
985
986#define EFX_BAR_TBL_READO(_enp, _reg, _index, _eop, _lock) \
987 do { \
988 EFX_CHECK_REG((_enp), (_reg)); \
989 EFSYS_BAR_READO((_enp)->en_esbp, \
990 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
991 (_eop), (_lock)); \
992 EFSYS_PROBE7(efx_bar_tbl_reado, const char *, #_reg, \
993 uint32_t, (_index), \
994 uint32_t, _reg ## _OFST, \
995 uint32_t, (_eop)->eo_u32[3], \
996 uint32_t, (_eop)->eo_u32[2], \
997 uint32_t, (_eop)->eo_u32[1], \
998 uint32_t, (_eop)->eo_u32[0]); \
999 _NOTE(CONSTANTCONDITION) \
1000 } while (B_FALSE)
1001
1002#define EFX_BAR_TBL_WRITEO(_enp, _reg, _index, _eop, _lock) \
1003 do { \
1004 EFX_CHECK_REG((_enp), (_reg)); \
1005 EFSYS_PROBE7(efx_bar_tbl_writeo, const char *, #_reg, \
1006 uint32_t, (_index), \
1007 uint32_t, _reg ## _OFST, \
1008 uint32_t, (_eop)->eo_u32[3], \
1009 uint32_t, (_eop)->eo_u32[2], \
1010 uint32_t, (_eop)->eo_u32[1], \
1011 uint32_t, (_eop)->eo_u32[0]); \
1012 EFSYS_BAR_WRITEO((_enp)->en_esbp, \
1013 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
1014 (_eop), (_lock)); \
1015 _NOTE(CONSTANTCONDITION) \
1016 } while (B_FALSE)
1017
1018/*
1019 * Allow drivers to perform optimised 128-bit doorbell writes.
1020 * The DMA descriptor pointers (RX_DESC_UPD and TX_DESC_UPD) are
1021 * special-cased in the BIU on the Falcon/Siena and EF10 architectures to avoid
1022 * the need for locking in the host, and are the only ones known to be safe to
1023 * use 128-bites write with.
1024 */
1025#define EFX_BAR_TBL_DOORBELL_WRITEO(_enp, _reg, _index, _eop) \
1026 do { \
1027 EFX_CHECK_REG((_enp), (_reg)); \
1028 EFSYS_PROBE7(efx_bar_tbl_doorbell_writeo, \
1029 const char *, \
1030 #_reg, \
1031 uint32_t, (_index), \
1032 uint32_t, _reg ## _OFST, \
1033 uint32_t, (_eop)->eo_u32[3], \
1034 uint32_t, (_eop)->eo_u32[2], \
1035 uint32_t, (_eop)->eo_u32[1], \
1036 uint32_t, (_eop)->eo_u32[0]); \
1037 EFSYS_BAR_DOORBELL_WRITEO((_enp)->en_esbp, \
1038 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
1039 (_eop)); \
1040 _NOTE(CONSTANTCONDITION) \
1041 } while (B_FALSE)
1042
1043#define EFX_DMA_SYNC_QUEUE_FOR_DEVICE(_esmp, _entries, _wptr, _owptr) \
1044 do { \
1045 unsigned int _new = (_wptr); \
1046 unsigned int _old = (_owptr); \
1047 \
1048 if ((_new) >= (_old)) \
1049 EFSYS_DMA_SYNC_FOR_DEVICE((_esmp), \
1050 (_old) * sizeof (efx_desc_t), \
1051 ((_new) - (_old)) * sizeof (efx_desc_t)); \
1052 else \
1053 /* \
1054 * It is cheaper to sync entire map than sync \
1055 * two parts especially when offset/size are \
1056 * ignored and entire map is synced in any case.\
1057 */ \
1058 EFSYS_DMA_SYNC_FOR_DEVICE((_esmp), \
1059 0, \
1060 (_entries) * sizeof (efx_desc_t)); \
1061 _NOTE(CONSTANTCONDITION) \
1062 } while (B_FALSE)
1063
1064extern __checkReturn efx_rc_t
1065efx_nic_biu_test(
1066 __in efx_nic_t *enp);
1067
1068extern __checkReturn efx_rc_t
1069efx_mac_select(
1070 __in efx_nic_t *enp);
1071
1072extern void
1073efx_mac_multicast_hash_compute(
1074 __in_ecount(6*count) uint8_t const *addrs,
1075 __in int count,
1076 __out efx_oword_t *hash_low,
1077 __out efx_oword_t *hash_high);
1078
1079extern __checkReturn efx_rc_t
1080efx_phy_probe(
1081 __in efx_nic_t *enp);
1082
1083extern void
1084efx_phy_unprobe(
1085 __in efx_nic_t *enp);
1086
1087#if EFSYS_OPT_VPD
1088
1089/* VPD utility functions */
1090
1091extern __checkReturn efx_rc_t
1092efx_vpd_hunk_length(
1093 __in_bcount(size) caddr_t data,
1094 __in size_t size,
1095 __out size_t *lengthp);
1096
1097extern __checkReturn efx_rc_t
1098efx_vpd_hunk_verify(
1099 __in_bcount(size) caddr_t data,
1100 __in size_t size,
1101 __out_opt boolean_t *cksummedp);
1102
1103extern __checkReturn efx_rc_t
1104efx_vpd_hunk_reinit(
1105 __in_bcount(size) caddr_t data,
1106 __in size_t size,
1107 __in boolean_t wantpid);
1108
1109extern __checkReturn efx_rc_t
1110efx_vpd_hunk_get(
1111 __in_bcount(size) caddr_t data,
1112 __in size_t size,
1113 __in efx_vpd_tag_t tag,
1114 __in efx_vpd_keyword_t keyword,
1115 __out unsigned int *payloadp,
1116 __out uint8_t *paylenp);
1117
1118extern __checkReturn efx_rc_t
1119efx_vpd_hunk_next(
1120 __in_bcount(size) caddr_t data,
1121 __in size_t size,
1122 __out efx_vpd_tag_t *tagp,
1123 __out efx_vpd_keyword_t *keyword,
1124 __out_opt unsigned int *payloadp,
1125 __out_opt uint8_t *paylenp,
1126 __inout unsigned int *contp);
1127
1128extern __checkReturn efx_rc_t
1129efx_vpd_hunk_set(
1130 __in_bcount(size) caddr_t data,
1131 __in size_t size,
1132 __in efx_vpd_value_t *evvp);
1133
1134#endif /* EFSYS_OPT_VPD */
1135
1136#if EFSYS_OPT_DIAG
1137
1138extern efx_sram_pattern_fn_t __efx_sram_pattern_fns[];
1139
1140typedef struct efx_register_set_s {
1141 unsigned int address;
1142 unsigned int step;
1143 unsigned int rows;
1144 efx_oword_t mask;
1145} efx_register_set_t;
1146
1147extern __checkReturn efx_rc_t
1148efx_nic_test_registers(
1149 __in efx_nic_t *enp,
1150 __in efx_register_set_t *rsp,
1151 __in size_t count);
1152
1153extern __checkReturn efx_rc_t
1154efx_nic_test_tables(
1155 __in efx_nic_t *enp,
1156 __in efx_register_set_t *rsp,
1157 __in efx_pattern_type_t pattern,
1158 __in size_t count);
1159
1160#endif /* EFSYS_OPT_DIAG */
1161
1162#if EFSYS_OPT_MCDI
1163
1164extern __checkReturn efx_rc_t
1165efx_mcdi_set_workaround(
1166 __in efx_nic_t *enp,
1167 __in uint32_t type,
1168 __in boolean_t enabled,
1169 __out_opt uint32_t *flagsp);
1170
1171extern __checkReturn efx_rc_t
1172efx_mcdi_get_workarounds(
1173 __in efx_nic_t *enp,
1174 __out_opt uint32_t *implementedp,
1175 __out_opt uint32_t *enabledp);
1176
1177#endif /* EFSYS_OPT_MCDI */
1178
1179#ifdef __cplusplus
1180}
1181#endif
1182
1183#endif /* _SYS_EFX_IMPL_H */
152 void (*etxo_qdesc_vlantci_create)(efx_txq_t *, uint16_t,
153 efx_desc_t *);
154#if EFSYS_OPT_QSTATS
155 void (*etxo_qstats_update)(efx_txq_t *,
156 efsys_stat_t *);
157#endif
158} efx_tx_ops_t;
159
160typedef struct efx_rx_ops_s {
161 efx_rc_t (*erxo_init)(efx_nic_t *);
162 void (*erxo_fini)(efx_nic_t *);
163#if EFSYS_OPT_RX_SCATTER
164 efx_rc_t (*erxo_scatter_enable)(efx_nic_t *, unsigned int);
165#endif
166#if EFSYS_OPT_RX_SCALE
167 efx_rc_t (*erxo_scale_mode_set)(efx_nic_t *, efx_rx_hash_alg_t,
168 efx_rx_hash_type_t, boolean_t);
169 efx_rc_t (*erxo_scale_key_set)(efx_nic_t *, uint8_t *, size_t);
170 efx_rc_t (*erxo_scale_tbl_set)(efx_nic_t *, unsigned int *,
171 size_t);
172 uint32_t (*erxo_prefix_hash)(efx_nic_t *, efx_rx_hash_alg_t,
173 uint8_t *);
174#endif /* EFSYS_OPT_RX_SCALE */
175 efx_rc_t (*erxo_prefix_pktlen)(efx_nic_t *, uint8_t *,
176 uint16_t *);
177 void (*erxo_qpost)(efx_rxq_t *, efsys_dma_addr_t *, size_t,
178 unsigned int, unsigned int,
179 unsigned int);
180 void (*erxo_qpush)(efx_rxq_t *, unsigned int, unsigned int *);
181 efx_rc_t (*erxo_qflush)(efx_rxq_t *);
182 void (*erxo_qenable)(efx_rxq_t *);
183 efx_rc_t (*erxo_qcreate)(efx_nic_t *enp, unsigned int,
184 unsigned int, efx_rxq_type_t,
185 efsys_mem_t *, size_t, uint32_t,
186 efx_evq_t *, efx_rxq_t *);
187 void (*erxo_qdestroy)(efx_rxq_t *);
188} efx_rx_ops_t;
189
190typedef struct efx_mac_ops_s {
191 efx_rc_t (*emo_reset)(efx_nic_t *); /* optional */
192 efx_rc_t (*emo_poll)(efx_nic_t *, efx_link_mode_t *);
193 efx_rc_t (*emo_up)(efx_nic_t *, boolean_t *);
194 efx_rc_t (*emo_addr_set)(efx_nic_t *);
195 efx_rc_t (*emo_reconfigure)(efx_nic_t *);
196 efx_rc_t (*emo_multicast_list_set)(efx_nic_t *);
197 efx_rc_t (*emo_filter_default_rxq_set)(efx_nic_t *,
198 efx_rxq_t *, boolean_t);
199 void (*emo_filter_default_rxq_clear)(efx_nic_t *);
200#if EFSYS_OPT_LOOPBACK
201 efx_rc_t (*emo_loopback_set)(efx_nic_t *, efx_link_mode_t,
202 efx_loopback_type_t);
203#endif /* EFSYS_OPT_LOOPBACK */
204#if EFSYS_OPT_MAC_STATS
205 efx_rc_t (*emo_stats_upload)(efx_nic_t *, efsys_mem_t *);
206 efx_rc_t (*emo_stats_periodic)(efx_nic_t *, efsys_mem_t *,
207 uint16_t, boolean_t);
208 efx_rc_t (*emo_stats_update)(efx_nic_t *, efsys_mem_t *,
209 efsys_stat_t *, uint32_t *);
210#endif /* EFSYS_OPT_MAC_STATS */
211} efx_mac_ops_t;
212
213typedef struct efx_phy_ops_s {
214 efx_rc_t (*epo_power)(efx_nic_t *, boolean_t); /* optional */
215 efx_rc_t (*epo_reset)(efx_nic_t *);
216 efx_rc_t (*epo_reconfigure)(efx_nic_t *);
217 efx_rc_t (*epo_verify)(efx_nic_t *);
218 efx_rc_t (*epo_uplink_check)(efx_nic_t *,
219 boolean_t *); /* optional */
220 efx_rc_t (*epo_downlink_check)(efx_nic_t *, efx_link_mode_t *,
221 unsigned int *, uint32_t *);
222 efx_rc_t (*epo_oui_get)(efx_nic_t *, uint32_t *);
223#if EFSYS_OPT_PHY_STATS
224 efx_rc_t (*epo_stats_update)(efx_nic_t *, efsys_mem_t *,
225 uint32_t *);
226#endif /* EFSYS_OPT_PHY_STATS */
227#if EFSYS_OPT_PHY_PROPS
228#if EFSYS_OPT_NAMES
229 const char *(*epo_prop_name)(efx_nic_t *, unsigned int);
230#endif /* EFSYS_OPT_PHY_PROPS */
231 efx_rc_t (*epo_prop_get)(efx_nic_t *, unsigned int, uint32_t,
232 uint32_t *);
233 efx_rc_t (*epo_prop_set)(efx_nic_t *, unsigned int, uint32_t);
234#endif /* EFSYS_OPT_PHY_PROPS */
235#if EFSYS_OPT_BIST
236 efx_rc_t (*epo_bist_enable_offline)(efx_nic_t *);
237 efx_rc_t (*epo_bist_start)(efx_nic_t *, efx_bist_type_t);
238 efx_rc_t (*epo_bist_poll)(efx_nic_t *, efx_bist_type_t,
239 efx_bist_result_t *, uint32_t *,
240 unsigned long *, size_t);
241 void (*epo_bist_stop)(efx_nic_t *, efx_bist_type_t);
242#endif /* EFSYS_OPT_BIST */
243} efx_phy_ops_t;
244
245#if EFSYS_OPT_FILTER
246typedef struct efx_filter_ops_s {
247 efx_rc_t (*efo_init)(efx_nic_t *);
248 void (*efo_fini)(efx_nic_t *);
249 efx_rc_t (*efo_restore)(efx_nic_t *);
250 efx_rc_t (*efo_add)(efx_nic_t *, efx_filter_spec_t *,
251 boolean_t may_replace);
252 efx_rc_t (*efo_delete)(efx_nic_t *, efx_filter_spec_t *);
253 efx_rc_t (*efo_supported_filters)(efx_nic_t *, uint32_t *, size_t *);
254 efx_rc_t (*efo_reconfigure)(efx_nic_t *, uint8_t const *, boolean_t,
255 boolean_t, boolean_t, boolean_t,
256 uint8_t const *, int);
257} efx_filter_ops_t;
258
259extern __checkReturn efx_rc_t
260efx_filter_reconfigure(
261 __in efx_nic_t *enp,
262 __in_ecount(6) uint8_t const *mac_addr,
263 __in boolean_t all_unicst,
264 __in boolean_t mulcst,
265 __in boolean_t all_mulcst,
266 __in boolean_t brdcst,
267 __in_ecount(6*count) uint8_t const *addrs,
268 __in int count);
269
270#endif /* EFSYS_OPT_FILTER */
271
272
273typedef struct efx_port_s {
274 efx_mac_type_t ep_mac_type;
275 uint32_t ep_phy_type;
276 uint8_t ep_port;
277 uint32_t ep_mac_pdu;
278 uint8_t ep_mac_addr[6];
279 efx_link_mode_t ep_link_mode;
280 boolean_t ep_all_unicst;
281 boolean_t ep_mulcst;
282 boolean_t ep_all_mulcst;
283 boolean_t ep_brdcst;
284 unsigned int ep_fcntl;
285 boolean_t ep_fcntl_autoneg;
286 efx_oword_t ep_multicst_hash[2];
287 uint8_t ep_mulcst_addr_list[EFX_MAC_ADDR_LEN *
288 EFX_MAC_MULTICAST_LIST_MAX];
289 uint32_t ep_mulcst_addr_count;
290#if EFSYS_OPT_LOOPBACK
291 efx_loopback_type_t ep_loopback_type;
292 efx_link_mode_t ep_loopback_link_mode;
293#endif /* EFSYS_OPT_LOOPBACK */
294#if EFSYS_OPT_PHY_FLAGS
295 uint32_t ep_phy_flags;
296#endif /* EFSYS_OPT_PHY_FLAGS */
297#if EFSYS_OPT_PHY_LED_CONTROL
298 efx_phy_led_mode_t ep_phy_led_mode;
299#endif /* EFSYS_OPT_PHY_LED_CONTROL */
300 efx_phy_media_type_t ep_fixed_port_type;
301 efx_phy_media_type_t ep_module_type;
302 uint32_t ep_adv_cap_mask;
303 uint32_t ep_lp_cap_mask;
304 uint32_t ep_default_adv_cap_mask;
305 uint32_t ep_phy_cap_mask;
306#if EFSYS_OPT_PHY_TXC43128 || EFSYS_OPT_PHY_QT2025C
307 union {
308 struct {
309 unsigned int bug10934_count;
310 } ep_txc43128;
311 struct {
312 unsigned int bug17190_count;
313 } ep_qt2025c;
314 };
315#endif
316 boolean_t ep_mac_poll_needed; /* falcon only */
317 boolean_t ep_mac_up; /* falcon only */
318 uint32_t ep_fwver; /* falcon only */
319 boolean_t ep_mac_drain;
320 boolean_t ep_mac_stats_pending;
321#if EFSYS_OPT_BIST
322 efx_bist_type_t ep_current_bist;
323#endif
324 efx_mac_ops_t *ep_emop;
325 efx_phy_ops_t *ep_epop;
326} efx_port_t;
327
328typedef struct efx_mon_ops_s {
329 efx_rc_t (*emo_reset)(efx_nic_t *);
330 efx_rc_t (*emo_reconfigure)(efx_nic_t *);
331#if EFSYS_OPT_MON_STATS
332 efx_rc_t (*emo_stats_update)(efx_nic_t *, efsys_mem_t *,
333 efx_mon_stat_value_t *);
334#endif /* EFSYS_OPT_MON_STATS */
335} efx_mon_ops_t;
336
337typedef struct efx_mon_s {
338 efx_mon_type_t em_type;
339 efx_mon_ops_t *em_emop;
340} efx_mon_t;
341
342typedef struct efx_intr_ops_s {
343 efx_rc_t (*eio_init)(efx_nic_t *, efx_intr_type_t, efsys_mem_t *);
344 void (*eio_enable)(efx_nic_t *);
345 void (*eio_disable)(efx_nic_t *);
346 void (*eio_disable_unlocked)(efx_nic_t *);
347 efx_rc_t (*eio_trigger)(efx_nic_t *, unsigned int);
348 void (*eio_status_line)(efx_nic_t *, boolean_t *, uint32_t *);
349 void (*eio_status_message)(efx_nic_t *, unsigned int,
350 boolean_t *);
351 void (*eio_fatal)(efx_nic_t *);
352 void (*eio_fini)(efx_nic_t *);
353} efx_intr_ops_t;
354
355typedef struct efx_intr_s {
356 efx_intr_ops_t *ei_eiop;
357 efsys_mem_t *ei_esmp;
358 efx_intr_type_t ei_type;
359 unsigned int ei_level;
360} efx_intr_t;
361
362typedef struct efx_nic_ops_s {
363 efx_rc_t (*eno_probe)(efx_nic_t *);
364 efx_rc_t (*eno_board_cfg)(efx_nic_t *);
365 efx_rc_t (*eno_set_drv_limits)(efx_nic_t *, efx_drv_limits_t*);
366 efx_rc_t (*eno_reset)(efx_nic_t *);
367 efx_rc_t (*eno_init)(efx_nic_t *);
368 efx_rc_t (*eno_get_vi_pool)(efx_nic_t *, uint32_t *);
369 efx_rc_t (*eno_get_bar_region)(efx_nic_t *, efx_nic_region_t,
370 uint32_t *, size_t *);
371#if EFSYS_OPT_DIAG
372 efx_rc_t (*eno_sram_test)(efx_nic_t *, efx_sram_pattern_fn_t);
373 efx_rc_t (*eno_register_test)(efx_nic_t *);
374#endif /* EFSYS_OPT_DIAG */
375 void (*eno_fini)(efx_nic_t *);
376 void (*eno_unprobe)(efx_nic_t *);
377} efx_nic_ops_t;
378
379#ifndef EFX_TXQ_LIMIT_TARGET
380#define EFX_TXQ_LIMIT_TARGET 259
381#endif
382#ifndef EFX_RXQ_LIMIT_TARGET
383#define EFX_RXQ_LIMIT_TARGET 512
384#endif
385#ifndef EFX_TXQ_DC_SIZE
386#define EFX_TXQ_DC_SIZE 1 /* 16 descriptors */
387#endif
388#ifndef EFX_RXQ_DC_SIZE
389#define EFX_RXQ_DC_SIZE 3 /* 64 descriptors */
390#endif
391
392#if EFSYS_OPT_FILTER
393
394typedef struct falconsiena_filter_spec_s {
395 uint8_t fsfs_type;
396 uint32_t fsfs_flags;
397 uint32_t fsfs_dmaq_id;
398 uint32_t fsfs_dword[3];
399} falconsiena_filter_spec_t;
400
401typedef enum falconsiena_filter_type_e {
402 EFX_FS_FILTER_RX_TCP_FULL, /* TCP/IPv4 4-tuple {dIP,dTCP,sIP,sTCP} */
403 EFX_FS_FILTER_RX_TCP_WILD, /* TCP/IPv4 dest {dIP,dTCP, -, -} */
404 EFX_FS_FILTER_RX_UDP_FULL, /* UDP/IPv4 4-tuple {dIP,dUDP,sIP,sUDP} */
405 EFX_FS_FILTER_RX_UDP_WILD, /* UDP/IPv4 dest {dIP,dUDP, -, -} */
406
407#if EFSYS_OPT_SIENA
408 EFX_FS_FILTER_RX_MAC_FULL, /* Ethernet {dMAC,VLAN} */
409 EFX_FS_FILTER_RX_MAC_WILD, /* Ethernet {dMAC, -} */
410
411 EFX_FS_FILTER_TX_TCP_FULL, /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */
412 EFX_FS_FILTER_TX_TCP_WILD, /* TCP/IPv4 { -, -,sIP,sTCP} */
413 EFX_FS_FILTER_TX_UDP_FULL, /* UDP/IPv4 {dIP,dTCP,sIP,sTCP} */
414 EFX_FS_FILTER_TX_UDP_WILD, /* UDP/IPv4 source (host, port) */
415
416 EFX_FS_FILTER_TX_MAC_FULL, /* Ethernet source (MAC address, VLAN ID) */
417 EFX_FS_FILTER_TX_MAC_WILD, /* Ethernet source (MAC address) */
418#endif /* EFSYS_OPT_SIENA */
419
420 EFX_FS_FILTER_NTYPES
421} falconsiena_filter_type_t;
422
423typedef enum falconsiena_filter_tbl_id_e {
424 EFX_FS_FILTER_TBL_RX_IP = 0,
425 EFX_FS_FILTER_TBL_RX_MAC,
426 EFX_FS_FILTER_TBL_TX_IP,
427 EFX_FS_FILTER_TBL_TX_MAC,
428 EFX_FS_FILTER_NTBLS
429} falconsiena_filter_tbl_id_t;
430
431typedef struct falconsiena_filter_tbl_s {
432 int fsft_size; /* number of entries */
433 int fsft_used; /* active count */
434 uint32_t *fsft_bitmap; /* active bitmap */
435 falconsiena_filter_spec_t *fsft_spec; /* array of saved specs */
436} falconsiena_filter_tbl_t;
437
438typedef struct falconsiena_filter_s {
439 falconsiena_filter_tbl_t fsf_tbl[EFX_FS_FILTER_NTBLS];
440 unsigned int fsf_depth[EFX_FS_FILTER_NTYPES];
441} falconsiena_filter_t;
442
443typedef struct efx_filter_s {
444#if EFSYS_OPT_FALCON || EFSYS_OPT_SIENA
445 falconsiena_filter_t *ef_falconsiena_filter;
446#endif /* EFSYS_OPT_FALCON || EFSYS_OPT_SIENA */
447#if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
448 ef10_filter_table_t *ef_ef10_filter_table;
449#endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */
450} efx_filter_t;
451
452extern void
453falconsiena_filter_tbl_clear(
454 __in efx_nic_t *enp,
455 __in falconsiena_filter_tbl_id_t tbl);
456
457#endif /* EFSYS_OPT_FILTER */
458
459#if EFSYS_OPT_MCDI
460
461typedef struct efx_mcdi_ops_s {
462 efx_rc_t (*emco_init)(efx_nic_t *, const efx_mcdi_transport_t *);
463 void (*emco_send_request)(efx_nic_t *, void *, size_t,
464 void *, size_t);
465 void (*emco_request_copyout)(efx_nic_t *, efx_mcdi_req_t *);
466 efx_rc_t (*emco_poll_reboot)(efx_nic_t *);
467 boolean_t (*emco_poll_response)(efx_nic_t *);
468 void (*emco_read_response)(efx_nic_t *, void *, size_t, size_t);
469 void (*emco_fini)(efx_nic_t *);
470 efx_rc_t (*emco_feature_supported)(efx_nic_t *, efx_mcdi_feature_id_t, boolean_t *);
471} efx_mcdi_ops_t;
472
473typedef struct efx_mcdi_s {
474 efx_mcdi_ops_t *em_emcop;
475 const efx_mcdi_transport_t *em_emtp;
476 efx_mcdi_iface_t em_emip;
477} efx_mcdi_t;
478
479#endif /* EFSYS_OPT_MCDI */
480
481#if EFSYS_OPT_NVRAM
482typedef struct efx_nvram_ops_s {
483#if EFSYS_OPT_DIAG
484 efx_rc_t (*envo_test)(efx_nic_t *);
485#endif /* EFSYS_OPT_DIAG */
486 efx_rc_t (*envo_get_version)(efx_nic_t *, efx_nvram_type_t,
487 uint32_t *, uint16_t *);
488 efx_rc_t (*envo_rw_start)(efx_nic_t *, efx_nvram_type_t, size_t *);
489 efx_rc_t (*envo_read_chunk)(efx_nic_t *, efx_nvram_type_t,
490 unsigned int, caddr_t, size_t);
491 efx_rc_t (*envo_erase)(efx_nic_t *, efx_nvram_type_t);
492 efx_rc_t (*envo_write_chunk)(efx_nic_t *, efx_nvram_type_t,
493 unsigned int, caddr_t, size_t);
494 void (*envo_rw_finish)(efx_nic_t *, efx_nvram_type_t);
495 efx_rc_t (*envo_set_version)(efx_nic_t *, efx_nvram_type_t,
496 uint16_t *);
497
498 efx_rc_t (*envo_type_to_partn)(efx_nic_t *, efx_nvram_type_t,
499 uint32_t *);
500 efx_rc_t (*envo_partn_size)(efx_nic_t *, uint32_t, size_t *);
501} efx_nvram_ops_t;
502#endif /* EFSYS_OPT_NVRAM */
503
504#if EFSYS_OPT_VPD
505typedef struct efx_vpd_ops_s {
506 efx_rc_t (*evpdo_init)(efx_nic_t *);
507 efx_rc_t (*evpdo_size)(efx_nic_t *, size_t *);
508 efx_rc_t (*evpdo_read)(efx_nic_t *, caddr_t, size_t);
509 efx_rc_t (*evpdo_verify)(efx_nic_t *, caddr_t, size_t);
510 efx_rc_t (*evpdo_reinit)(efx_nic_t *, caddr_t, size_t);
511 efx_rc_t (*evpdo_get)(efx_nic_t *, caddr_t, size_t,
512 efx_vpd_value_t *);
513 efx_rc_t (*evpdo_set)(efx_nic_t *, caddr_t, size_t,
514 efx_vpd_value_t *);
515 efx_rc_t (*evpdo_next)(efx_nic_t *, caddr_t, size_t,
516 efx_vpd_value_t *, unsigned int *);
517 efx_rc_t (*evpdo_write)(efx_nic_t *, caddr_t, size_t);
518 void (*evpdo_fini)(efx_nic_t *);
519} efx_vpd_ops_t;
520#endif /* EFSYS_OPT_VPD */
521
522#if EFSYS_OPT_VPD || EFSYS_OPT_NVRAM
523
524 __checkReturn efx_rc_t
525efx_mcdi_nvram_partitions(
526 __in efx_nic_t *enp,
527 __out_bcount(size) caddr_t data,
528 __in size_t size,
529 __out unsigned int *npartnp);
530
531 __checkReturn efx_rc_t
532efx_mcdi_nvram_metadata(
533 __in efx_nic_t *enp,
534 __in uint32_t partn,
535 __out uint32_t *subtypep,
536 __out_ecount(4) uint16_t version[4],
537 __out_bcount_opt(size) char *descp,
538 __in size_t size);
539
540 __checkReturn efx_rc_t
541efx_mcdi_nvram_info(
542 __in efx_nic_t *enp,
543 __in uint32_t partn,
544 __out_opt size_t *sizep,
545 __out_opt uint32_t *addressp,
546 __out_opt uint32_t *erase_sizep,
547 __out_opt uint32_t *write_sizep);
548
549 __checkReturn efx_rc_t
550efx_mcdi_nvram_update_start(
551 __in efx_nic_t *enp,
552 __in uint32_t partn);
553
554 __checkReturn efx_rc_t
555efx_mcdi_nvram_read(
556 __in efx_nic_t *enp,
557 __in uint32_t partn,
558 __in uint32_t offset,
559 __out_bcount(size) caddr_t data,
560 __in size_t size);
561
562 __checkReturn efx_rc_t
563efx_mcdi_nvram_erase(
564 __in efx_nic_t *enp,
565 __in uint32_t partn,
566 __in uint32_t offset,
567 __in size_t size);
568
569 __checkReturn efx_rc_t
570efx_mcdi_nvram_write(
571 __in efx_nic_t *enp,
572 __in uint32_t partn,
573 __in uint32_t offset,
574 __out_bcount(size) caddr_t data,
575 __in size_t size);
576
577 __checkReturn efx_rc_t
578efx_mcdi_nvram_update_finish(
579 __in efx_nic_t *enp,
580 __in uint32_t partn,
581 __in boolean_t reboot);
582
583#if EFSYS_OPT_DIAG
584
585 __checkReturn efx_rc_t
586efx_mcdi_nvram_test(
587 __in efx_nic_t *enp,
588 __in uint32_t partn);
589
590#endif /* EFSYS_OPT_DIAG */
591
592#endif /* EFSYS_OPT_VPD || EFSYS_OPT_NVRAM */
593
594typedef struct efx_drv_cfg_s {
595 uint32_t edc_min_vi_count;
596 uint32_t edc_max_vi_count;
597
598 uint32_t edc_max_piobuf_count;
599 uint32_t edc_pio_alloc_size;
600} efx_drv_cfg_t;
601
602struct efx_nic_s {
603 uint32_t en_magic;
604 efx_family_t en_family;
605 uint32_t en_features;
606 efsys_identifier_t *en_esip;
607 efsys_lock_t *en_eslp;
608 efsys_bar_t *en_esbp;
609 unsigned int en_mod_flags;
610 unsigned int en_reset_flags;
611 efx_nic_cfg_t en_nic_cfg;
612 efx_drv_cfg_t en_drv_cfg;
613 efx_port_t en_port;
614 efx_mon_t en_mon;
615 efx_intr_t en_intr;
616 uint32_t en_ev_qcount;
617 uint32_t en_rx_qcount;
618 uint32_t en_tx_qcount;
619 efx_nic_ops_t *en_enop;
620 efx_ev_ops_t *en_eevop;
621 efx_tx_ops_t *en_etxop;
622 efx_rx_ops_t *en_erxop;
623#if EFSYS_OPT_FILTER
624 efx_filter_t en_filter;
625 efx_filter_ops_t *en_efop;
626#endif /* EFSYS_OPT_FILTER */
627#if EFSYS_OPT_MCDI
628 efx_mcdi_t en_mcdi;
629#endif /* EFSYS_OPT_MCDI */
630#if EFSYS_OPT_NVRAM
631 efx_nvram_type_t en_nvram_locked;
632 efx_nvram_ops_t *en_envop;
633#endif /* EFSYS_OPT_NVRAM */
634#if EFSYS_OPT_VPD
635 efx_vpd_ops_t *en_evpdop;
636#endif /* EFSYS_OPT_VPD */
637#if EFSYS_OPT_RX_SCALE
638 efx_rx_hash_support_t en_hash_support;
639 efx_rx_scale_support_t en_rss_support;
640 uint32_t en_rss_context;
641#endif /* EFSYS_OPT_RX_SCALE */
642 uint32_t en_vport_id;
643 union {
644#if EFSYS_OPT_FALCON
645 struct {
646 falcon_spi_dev_t enu_fsd[FALCON_SPI_NTYPES];
647 falcon_i2c_t enu_fip;
648 boolean_t enu_i2c_locked;
649#if EFSYS_OPT_FALCON_NIC_CFG_OVERRIDE
650 const uint8_t *enu_forced_cfg;
651#endif /* EFSYS_OPT_FALCON_NIC_CFG_OVERRIDE */
652 uint8_t enu_mon_devid;
653#if EFSYS_OPT_PCIE_TUNE
654 unsigned int enu_nlanes;
655#endif /* EFSYS_OPT_PCIE_TUNE */
656 uint16_t enu_board_rev;
657 boolean_t enu_internal_sram;
658 uint8_t enu_sram_num_bank;
659 uint8_t enu_sram_bank_size;
660 } falcon;
661#endif /* EFSYS_OPT_FALCON */
662#if EFSYS_OPT_SIENA
663 struct {
664#if EFSYS_OPT_NVRAM || EFSYS_OPT_VPD
665 unsigned int enu_partn_mask;
666#endif /* EFSYS_OPT_NVRAM || EFSYS_OPT_VPD */
667#if EFSYS_OPT_VPD
668 caddr_t enu_svpd;
669 size_t enu_svpd_length;
670#endif /* EFSYS_OPT_VPD */
671 int enu_unused;
672 } siena;
673#endif /* EFSYS_OPT_SIENA */
674 int enu_unused;
675 } en_u;
676#if (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD)
677 union en_arch {
678 struct {
679 int ena_vi_base;
680 int ena_vi_count;
681 int ena_vi_shift;
682#if EFSYS_OPT_VPD
683 caddr_t ena_svpd;
684 size_t ena_svpd_length;
685#endif /* EFSYS_OPT_VPD */
686 efx_piobuf_handle_t ena_piobuf_handle[EF10_MAX_PIOBUF_NBUFS];
687 uint32_t ena_piobuf_count;
688 uint32_t ena_pio_alloc_map[EF10_MAX_PIOBUF_NBUFS];
689 uint32_t ena_pio_write_vi_base;
690 /* Memory BAR mapping regions */
691 uint32_t ena_uc_mem_map_offset;
692 size_t ena_uc_mem_map_size;
693 uint32_t ena_wc_mem_map_offset;
694 size_t ena_wc_mem_map_size;
695 } ef10;
696 } en_arch;
697#endif /* (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD) */
698};
699
700
701#define EFX_NIC_MAGIC 0x02121996
702
703typedef boolean_t (*efx_ev_handler_t)(efx_evq_t *, efx_qword_t *,
704 const efx_ev_callbacks_t *, void *);
705
706typedef struct efx_evq_rxq_state_s {
707 unsigned int eers_rx_read_ptr;
708 unsigned int eers_rx_mask;
709} efx_evq_rxq_state_t;
710
711struct efx_evq_s {
712 uint32_t ee_magic;
713 efx_nic_t *ee_enp;
714 unsigned int ee_index;
715 unsigned int ee_mask;
716 efsys_mem_t *ee_esmp;
717#if EFSYS_OPT_QSTATS
718 uint32_t ee_stat[EV_NQSTATS];
719#endif /* EFSYS_OPT_QSTATS */
720
721 efx_ev_handler_t ee_rx;
722 efx_ev_handler_t ee_tx;
723 efx_ev_handler_t ee_driver;
724 efx_ev_handler_t ee_global;
725 efx_ev_handler_t ee_drv_gen;
726#if EFSYS_OPT_MCDI
727 efx_ev_handler_t ee_mcdi;
728#endif /* EFSYS_OPT_MCDI */
729
730 efx_evq_rxq_state_t ee_rxq_state[EFX_EV_RX_NLABELS];
731};
732
733#define EFX_EVQ_MAGIC 0x08081997
734
735#define EFX_EVQ_FALCON_TIMER_QUANTUM_NS 4968 /* 621 cycles */
736#define EFX_EVQ_SIENA_TIMER_QUANTUM_NS 6144 /* 768 cycles */
737
738struct efx_rxq_s {
739 uint32_t er_magic;
740 efx_nic_t *er_enp;
741 efx_evq_t *er_eep;
742 unsigned int er_index;
743 unsigned int er_label;
744 unsigned int er_mask;
745 efsys_mem_t *er_esmp;
746};
747
748#define EFX_RXQ_MAGIC 0x15022005
749
750struct efx_txq_s {
751 uint32_t et_magic;
752 efx_nic_t *et_enp;
753 unsigned int et_index;
754 unsigned int et_mask;
755 efsys_mem_t *et_esmp;
756#if EFSYS_OPT_HUNTINGTON
757 uint32_t et_pio_bufnum;
758 uint32_t et_pio_blknum;
759 uint32_t et_pio_write_offset;
760 uint32_t et_pio_offset;
761 size_t et_pio_size;
762#endif
763#if EFSYS_OPT_QSTATS
764 uint32_t et_stat[TX_NQSTATS];
765#endif /* EFSYS_OPT_QSTATS */
766};
767
768#define EFX_TXQ_MAGIC 0x05092005
769
770#define EFX_MAC_ADDR_COPY(_dst, _src) \
771 do { \
772 (_dst)[0] = (_src)[0]; \
773 (_dst)[1] = (_src)[1]; \
774 (_dst)[2] = (_src)[2]; \
775 (_dst)[3] = (_src)[3]; \
776 (_dst)[4] = (_src)[4]; \
777 (_dst)[5] = (_src)[5]; \
778 _NOTE(CONSTANTCONDITION) \
779 } while (B_FALSE)
780
781#define EFX_MAC_BROADCAST_ADDR_SET(_dst) \
782 do { \
783 uint16_t *_d = (uint16_t *)(_dst); \
784 _d[0] = 0xffff; \
785 _d[1] = 0xffff; \
786 _d[2] = 0xffff; \
787 _NOTE(CONSTANTCONDITION) \
788 } while (B_FALSE)
789
790#if EFSYS_OPT_CHECK_REG
791#define EFX_CHECK_REG(_enp, _reg) \
792 do { \
793 const char *name = #_reg; \
794 char min = name[4]; \
795 char max = name[5]; \
796 char rev; \
797 \
798 switch ((_enp)->en_family) { \
799 case EFX_FAMILY_FALCON: \
800 rev = 'B'; \
801 break; \
802 \
803 case EFX_FAMILY_SIENA: \
804 rev = 'C'; \
805 break; \
806 \
807 case EFX_FAMILY_HUNTINGTON: \
808 rev = 'D'; \
809 break; \
810 \
811 case EFX_FAMILY_MEDFORD: \
812 rev = 'E'; \
813 break; \
814 \
815 default: \
816 rev = '?'; \
817 break; \
818 } \
819 \
820 EFSYS_ASSERT3S(rev, >=, min); \
821 EFSYS_ASSERT3S(rev, <=, max); \
822 \
823 _NOTE(CONSTANTCONDITION) \
824 } while (B_FALSE)
825#else
826#define EFX_CHECK_REG(_enp, _reg) do { \
827 _NOTE(CONSTANTCONDITION) \
828 } while(B_FALSE)
829#endif
830
831#define EFX_BAR_READD(_enp, _reg, _edp, _lock) \
832 do { \
833 EFX_CHECK_REG((_enp), (_reg)); \
834 EFSYS_BAR_READD((_enp)->en_esbp, _reg ## _OFST, \
835 (_edp), (_lock)); \
836 EFSYS_PROBE3(efx_bar_readd, const char *, #_reg, \
837 uint32_t, _reg ## _OFST, \
838 uint32_t, (_edp)->ed_u32[0]); \
839 _NOTE(CONSTANTCONDITION) \
840 } while (B_FALSE)
841
842#define EFX_BAR_WRITED(_enp, _reg, _edp, _lock) \
843 do { \
844 EFX_CHECK_REG((_enp), (_reg)); \
845 EFSYS_PROBE3(efx_bar_writed, const char *, #_reg, \
846 uint32_t, _reg ## _OFST, \
847 uint32_t, (_edp)->ed_u32[0]); \
848 EFSYS_BAR_WRITED((_enp)->en_esbp, _reg ## _OFST, \
849 (_edp), (_lock)); \
850 _NOTE(CONSTANTCONDITION) \
851 } while (B_FALSE)
852
853#define EFX_BAR_READQ(_enp, _reg, _eqp) \
854 do { \
855 EFX_CHECK_REG((_enp), (_reg)); \
856 EFSYS_BAR_READQ((_enp)->en_esbp, _reg ## _OFST, \
857 (_eqp)); \
858 EFSYS_PROBE4(efx_bar_readq, const char *, #_reg, \
859 uint32_t, _reg ## _OFST, \
860 uint32_t, (_eqp)->eq_u32[1], \
861 uint32_t, (_eqp)->eq_u32[0]); \
862 _NOTE(CONSTANTCONDITION) \
863 } while (B_FALSE)
864
865#define EFX_BAR_WRITEQ(_enp, _reg, _eqp) \
866 do { \
867 EFX_CHECK_REG((_enp), (_reg)); \
868 EFSYS_PROBE4(efx_bar_writeq, const char *, #_reg, \
869 uint32_t, _reg ## _OFST, \
870 uint32_t, (_eqp)->eq_u32[1], \
871 uint32_t, (_eqp)->eq_u32[0]); \
872 EFSYS_BAR_WRITEQ((_enp)->en_esbp, _reg ## _OFST, \
873 (_eqp)); \
874 _NOTE(CONSTANTCONDITION) \
875 } while (B_FALSE)
876
877#define EFX_BAR_READO(_enp, _reg, _eop) \
878 do { \
879 EFX_CHECK_REG((_enp), (_reg)); \
880 EFSYS_BAR_READO((_enp)->en_esbp, _reg ## _OFST, \
881 (_eop), B_TRUE); \
882 EFSYS_PROBE6(efx_bar_reado, const char *, #_reg, \
883 uint32_t, _reg ## _OFST, \
884 uint32_t, (_eop)->eo_u32[3], \
885 uint32_t, (_eop)->eo_u32[2], \
886 uint32_t, (_eop)->eo_u32[1], \
887 uint32_t, (_eop)->eo_u32[0]); \
888 _NOTE(CONSTANTCONDITION) \
889 } while (B_FALSE)
890
891#define EFX_BAR_WRITEO(_enp, _reg, _eop) \
892 do { \
893 EFX_CHECK_REG((_enp), (_reg)); \
894 EFSYS_PROBE6(efx_bar_writeo, const char *, #_reg, \
895 uint32_t, _reg ## _OFST, \
896 uint32_t, (_eop)->eo_u32[3], \
897 uint32_t, (_eop)->eo_u32[2], \
898 uint32_t, (_eop)->eo_u32[1], \
899 uint32_t, (_eop)->eo_u32[0]); \
900 EFSYS_BAR_WRITEO((_enp)->en_esbp, _reg ## _OFST, \
901 (_eop), B_TRUE); \
902 _NOTE(CONSTANTCONDITION) \
903 } while (B_FALSE)
904
905#define EFX_BAR_TBL_READD(_enp, _reg, _index, _edp, _lock) \
906 do { \
907 EFX_CHECK_REG((_enp), (_reg)); \
908 EFSYS_BAR_READD((_enp)->en_esbp, \
909 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
910 (_edp), (_lock)); \
911 EFSYS_PROBE4(efx_bar_tbl_readd, const char *, #_reg, \
912 uint32_t, (_index), \
913 uint32_t, _reg ## _OFST, \
914 uint32_t, (_edp)->ed_u32[0]); \
915 _NOTE(CONSTANTCONDITION) \
916 } while (B_FALSE)
917
918#define EFX_BAR_TBL_WRITED(_enp, _reg, _index, _edp, _lock) \
919 do { \
920 EFX_CHECK_REG((_enp), (_reg)); \
921 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg, \
922 uint32_t, (_index), \
923 uint32_t, _reg ## _OFST, \
924 uint32_t, (_edp)->ed_u32[0]); \
925 EFSYS_BAR_WRITED((_enp)->en_esbp, \
926 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
927 (_edp), (_lock)); \
928 _NOTE(CONSTANTCONDITION) \
929 } while (B_FALSE)
930
931#define EFX_BAR_TBL_WRITED2(_enp, _reg, _index, _edp, _lock) \
932 do { \
933 EFX_CHECK_REG((_enp), (_reg)); \
934 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg, \
935 uint32_t, (_index), \
936 uint32_t, _reg ## _OFST, \
937 uint32_t, (_edp)->ed_u32[0]); \
938 EFSYS_BAR_WRITED((_enp)->en_esbp, \
939 (_reg ## _OFST + \
940 (2 * sizeof (efx_dword_t)) + \
941 ((_index) * _reg ## _STEP)), \
942 (_edp), (_lock)); \
943 _NOTE(CONSTANTCONDITION) \
944 } while (B_FALSE)
945
946#define EFX_BAR_TBL_WRITED3(_enp, _reg, _index, _edp, _lock) \
947 do { \
948 EFX_CHECK_REG((_enp), (_reg)); \
949 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg, \
950 uint32_t, (_index), \
951 uint32_t, _reg ## _OFST, \
952 uint32_t, (_edp)->ed_u32[0]); \
953 EFSYS_BAR_WRITED((_enp)->en_esbp, \
954 (_reg ## _OFST + \
955 (3 * sizeof (efx_dword_t)) + \
956 ((_index) * _reg ## _STEP)), \
957 (_edp), (_lock)); \
958 _NOTE(CONSTANTCONDITION) \
959 } while (B_FALSE)
960
961#define EFX_BAR_TBL_READQ(_enp, _reg, _index, _eqp) \
962 do { \
963 EFX_CHECK_REG((_enp), (_reg)); \
964 EFSYS_BAR_READQ((_enp)->en_esbp, \
965 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
966 (_eqp)); \
967 EFSYS_PROBE5(efx_bar_tbl_readq, const char *, #_reg, \
968 uint32_t, (_index), \
969 uint32_t, _reg ## _OFST, \
970 uint32_t, (_eqp)->eq_u32[1], \
971 uint32_t, (_eqp)->eq_u32[0]); \
972 _NOTE(CONSTANTCONDITION) \
973 } while (B_FALSE)
974
975#define EFX_BAR_TBL_WRITEQ(_enp, _reg, _index, _eqp) \
976 do { \
977 EFX_CHECK_REG((_enp), (_reg)); \
978 EFSYS_PROBE5(efx_bar_tbl_writeq, const char *, #_reg, \
979 uint32_t, (_index), \
980 uint32_t, _reg ## _OFST, \
981 uint32_t, (_eqp)->eq_u32[1], \
982 uint32_t, (_eqp)->eq_u32[0]); \
983 EFSYS_BAR_WRITEQ((_enp)->en_esbp, \
984 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
985 (_eqp)); \
986 _NOTE(CONSTANTCONDITION) \
987 } while (B_FALSE)
988
989#define EFX_BAR_TBL_READO(_enp, _reg, _index, _eop, _lock) \
990 do { \
991 EFX_CHECK_REG((_enp), (_reg)); \
992 EFSYS_BAR_READO((_enp)->en_esbp, \
993 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
994 (_eop), (_lock)); \
995 EFSYS_PROBE7(efx_bar_tbl_reado, const char *, #_reg, \
996 uint32_t, (_index), \
997 uint32_t, _reg ## _OFST, \
998 uint32_t, (_eop)->eo_u32[3], \
999 uint32_t, (_eop)->eo_u32[2], \
1000 uint32_t, (_eop)->eo_u32[1], \
1001 uint32_t, (_eop)->eo_u32[0]); \
1002 _NOTE(CONSTANTCONDITION) \
1003 } while (B_FALSE)
1004
1005#define EFX_BAR_TBL_WRITEO(_enp, _reg, _index, _eop, _lock) \
1006 do { \
1007 EFX_CHECK_REG((_enp), (_reg)); \
1008 EFSYS_PROBE7(efx_bar_tbl_writeo, const char *, #_reg, \
1009 uint32_t, (_index), \
1010 uint32_t, _reg ## _OFST, \
1011 uint32_t, (_eop)->eo_u32[3], \
1012 uint32_t, (_eop)->eo_u32[2], \
1013 uint32_t, (_eop)->eo_u32[1], \
1014 uint32_t, (_eop)->eo_u32[0]); \
1015 EFSYS_BAR_WRITEO((_enp)->en_esbp, \
1016 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
1017 (_eop), (_lock)); \
1018 _NOTE(CONSTANTCONDITION) \
1019 } while (B_FALSE)
1020
1021/*
1022 * Allow drivers to perform optimised 128-bit doorbell writes.
1023 * The DMA descriptor pointers (RX_DESC_UPD and TX_DESC_UPD) are
1024 * special-cased in the BIU on the Falcon/Siena and EF10 architectures to avoid
1025 * the need for locking in the host, and are the only ones known to be safe to
1026 * use 128-bites write with.
1027 */
1028#define EFX_BAR_TBL_DOORBELL_WRITEO(_enp, _reg, _index, _eop) \
1029 do { \
1030 EFX_CHECK_REG((_enp), (_reg)); \
1031 EFSYS_PROBE7(efx_bar_tbl_doorbell_writeo, \
1032 const char *, \
1033 #_reg, \
1034 uint32_t, (_index), \
1035 uint32_t, _reg ## _OFST, \
1036 uint32_t, (_eop)->eo_u32[3], \
1037 uint32_t, (_eop)->eo_u32[2], \
1038 uint32_t, (_eop)->eo_u32[1], \
1039 uint32_t, (_eop)->eo_u32[0]); \
1040 EFSYS_BAR_DOORBELL_WRITEO((_enp)->en_esbp, \
1041 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
1042 (_eop)); \
1043 _NOTE(CONSTANTCONDITION) \
1044 } while (B_FALSE)
1045
1046#define EFX_DMA_SYNC_QUEUE_FOR_DEVICE(_esmp, _entries, _wptr, _owptr) \
1047 do { \
1048 unsigned int _new = (_wptr); \
1049 unsigned int _old = (_owptr); \
1050 \
1051 if ((_new) >= (_old)) \
1052 EFSYS_DMA_SYNC_FOR_DEVICE((_esmp), \
1053 (_old) * sizeof (efx_desc_t), \
1054 ((_new) - (_old)) * sizeof (efx_desc_t)); \
1055 else \
1056 /* \
1057 * It is cheaper to sync entire map than sync \
1058 * two parts especially when offset/size are \
1059 * ignored and entire map is synced in any case.\
1060 */ \
1061 EFSYS_DMA_SYNC_FOR_DEVICE((_esmp), \
1062 0, \
1063 (_entries) * sizeof (efx_desc_t)); \
1064 _NOTE(CONSTANTCONDITION) \
1065 } while (B_FALSE)
1066
1067extern __checkReturn efx_rc_t
1068efx_nic_biu_test(
1069 __in efx_nic_t *enp);
1070
1071extern __checkReturn efx_rc_t
1072efx_mac_select(
1073 __in efx_nic_t *enp);
1074
1075extern void
1076efx_mac_multicast_hash_compute(
1077 __in_ecount(6*count) uint8_t const *addrs,
1078 __in int count,
1079 __out efx_oword_t *hash_low,
1080 __out efx_oword_t *hash_high);
1081
1082extern __checkReturn efx_rc_t
1083efx_phy_probe(
1084 __in efx_nic_t *enp);
1085
1086extern void
1087efx_phy_unprobe(
1088 __in efx_nic_t *enp);
1089
1090#if EFSYS_OPT_VPD
1091
1092/* VPD utility functions */
1093
1094extern __checkReturn efx_rc_t
1095efx_vpd_hunk_length(
1096 __in_bcount(size) caddr_t data,
1097 __in size_t size,
1098 __out size_t *lengthp);
1099
1100extern __checkReturn efx_rc_t
1101efx_vpd_hunk_verify(
1102 __in_bcount(size) caddr_t data,
1103 __in size_t size,
1104 __out_opt boolean_t *cksummedp);
1105
1106extern __checkReturn efx_rc_t
1107efx_vpd_hunk_reinit(
1108 __in_bcount(size) caddr_t data,
1109 __in size_t size,
1110 __in boolean_t wantpid);
1111
1112extern __checkReturn efx_rc_t
1113efx_vpd_hunk_get(
1114 __in_bcount(size) caddr_t data,
1115 __in size_t size,
1116 __in efx_vpd_tag_t tag,
1117 __in efx_vpd_keyword_t keyword,
1118 __out unsigned int *payloadp,
1119 __out uint8_t *paylenp);
1120
1121extern __checkReturn efx_rc_t
1122efx_vpd_hunk_next(
1123 __in_bcount(size) caddr_t data,
1124 __in size_t size,
1125 __out efx_vpd_tag_t *tagp,
1126 __out efx_vpd_keyword_t *keyword,
1127 __out_opt unsigned int *payloadp,
1128 __out_opt uint8_t *paylenp,
1129 __inout unsigned int *contp);
1130
1131extern __checkReturn efx_rc_t
1132efx_vpd_hunk_set(
1133 __in_bcount(size) caddr_t data,
1134 __in size_t size,
1135 __in efx_vpd_value_t *evvp);
1136
1137#endif /* EFSYS_OPT_VPD */
1138
1139#if EFSYS_OPT_DIAG
1140
1141extern efx_sram_pattern_fn_t __efx_sram_pattern_fns[];
1142
1143typedef struct efx_register_set_s {
1144 unsigned int address;
1145 unsigned int step;
1146 unsigned int rows;
1147 efx_oword_t mask;
1148} efx_register_set_t;
1149
1150extern __checkReturn efx_rc_t
1151efx_nic_test_registers(
1152 __in efx_nic_t *enp,
1153 __in efx_register_set_t *rsp,
1154 __in size_t count);
1155
1156extern __checkReturn efx_rc_t
1157efx_nic_test_tables(
1158 __in efx_nic_t *enp,
1159 __in efx_register_set_t *rsp,
1160 __in efx_pattern_type_t pattern,
1161 __in size_t count);
1162
1163#endif /* EFSYS_OPT_DIAG */
1164
1165#if EFSYS_OPT_MCDI
1166
1167extern __checkReturn efx_rc_t
1168efx_mcdi_set_workaround(
1169 __in efx_nic_t *enp,
1170 __in uint32_t type,
1171 __in boolean_t enabled,
1172 __out_opt uint32_t *flagsp);
1173
1174extern __checkReturn efx_rc_t
1175efx_mcdi_get_workarounds(
1176 __in efx_nic_t *enp,
1177 __out_opt uint32_t *implementedp,
1178 __out_opt uint32_t *enabledp);
1179
1180#endif /* EFSYS_OPT_MCDI */
1181
1182#ifdef __cplusplus
1183}
1184#endif
1185
1186#endif /* _SYS_EFX_IMPL_H */